David Adler Lectureship Award Talk: III-V Semiconductor Nanowires on Silicon for Future Devices

NASA Astrophysics Data System (ADS)

Riel, Heike

Bottom-up grown nanowires are very attractive materials for direct integration of III-V semiconductors on silicon thus opening up new possibilities for the design and fabrication of nanoscale devices for electronic, optoelectronic as well as quantum information applications. Template-Assisted Selective Epitaxy (TASE) allows the well-defined and monolithic integration of complex III-V nanostructures and devices on silicon. Achieving atomically abrupt heterointerfaces, high crystal quality and control of dimension down to 1D nanowires enabled the demonstration of FETs and tunnel devices based on In(Ga)As and GaSb. Furthermore, the strong influence of strain on nanowires as well as results on quantum transport studies of InAs nanowires with well-defined geometry will be presented.

Compact Quantum Random Number Generator with Silicon Nanocrystals Light Emitting Device Coupled to a Silicon Photomultiplier

NASA Astrophysics Data System (ADS)

Bisadi, Zahra; Acerbi, Fabio; Fontana, Giorgio; Zorzi, Nicola; Piemonte, Claudio; Pucker, Georg; Pavesi, Lorenzo

2018-02-01

A small-sized photonic quantum random number generator, easy to be implemented in small electronic devices for secure data encryption and other applications, is highly demanding nowadays. Here, we propose a compact configuration with Silicon nanocrystals large area light emitting device (LED) coupled to a Silicon photomultiplier to generate random numbers. The random number generation methodology is based on the photon arrival time and is robust against the non-idealities of the detector and the source of quantum entropy. The raw data show high quality of randomness and pass all the statistical tests in national institute of standards and technology tests (NIST) suite without a post-processing algorithm. The highest bit rate is 0.5 Mbps with the efficiency of 4 bits per detected photon.

High-frequency and high-quality silicon carbide optomechanical microresonators

PubMed Central

Lu, Xiyuan; Lee, Jonathan Y.; Lin, Qiang

2015-01-01

Silicon carbide (SiC) exhibits excellent material properties attractive for broad applications. We demonstrate the first SiC optomechanical microresonators that integrate high mechanical frequency, high mechanical quality, and high optical quality into a single device. The radial-breathing mechanical mode has a mechanical frequency up to 1.69 GHz with a mechanical Q around 5500 in atmosphere, which corresponds to a fm · Qm product as high as 9.47 × 1012 Hz. The strong optomechanical coupling allows us to efficiently excite and probe the coherent mechanical oscillation by optical waves. The demonstrated devices, in combination with the superior thermal property, chemical inertness, and defect characteristics of SiC, show great potential for applications in metrology, sensing, and quantum photonics, particularly in harsh environments that are challenging for other device platforms. PMID:26585637

Silicon-Based Thermoelectrics: Harvesting Low Quality Heat Using Economically Printed Flexible Nanostructured Stacked Thermoelectric Junctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-03-01

Broad Funding Opportunity Announcement Project: UIUC is experimenting with silicon-based materials to develop flexible thermoelectric devices—which convert heat into energy—that can be mass-produced at low cost. A thermoelectric device, which resembles a computer chip, creates electricity when a different temperature is applied to each of its sides. Existing commercial thermoelectric devices contain the element tellurium, which limits production levels because tellurium has become increasingly rare. UIUC is replacing this material with microscopic silicon wires that are considerably cheaper and could be equally effective. Improvements in thermoelectric device production could return enough wasted heat to add up to 23% to ourmore » current annual electricity production.« less

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Silicon-on ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Grung, B. L.; Heaps, J. D.; Schmit, F. M.; Schuldt, S. B.; Zook, J. D.

1981-01-01

The technical feasibility of producing solar-cell-quality sheet silicon to meet the Department of Energy (DOE) 1986 overall price goal of $0.70/watt was investigated. With the silicon-on-ceramic (SOC) approach, a low-cost ceramic substrate is coated with large-grain polycrystalline silicon by unidirectional solidification of molten silicon. This effort was divided into several areas of investigation in order to most efficiently meet the goals of the program. These areas include: (1) dip-coating; (2) continuous coating designated SCIM-coating, and acronym for Silicon Coating by an Inverted Meniscus (SCIM); (3) material characterization; (4) cell fabrication and evaluation; and (5) theoretical analysis. Both coating approaches were successful in producing thin layers of large grain, solar-cell-quality silicon. The dip-coating approach was initially investigated and considerable effort was given to this technique. The SCIM technique was adopted because of its scale-up potential and its capability to produce more conventiently large areas of SOC.

Effects of silicone expanders and implants on echocardiographic image quality after breast reconstruction.

PubMed

Pignatti, Marco; Mantovani, Francesca; Bertelli, Luca; Barbieri, Andrea; Pacchioni, Lucrezia; Loschi, Pietro; De Santis, Giorgio

2013-08-01

Use of silicone expanders and implants is the most common breast reconstruction technique after mastectomy. Postmastectomy patients often need echocardiographic monitoring of potential cardiotoxicity induced by cancer chemotherapy. The impairment of the echocardiographic acoustic window caused by silicone implants for breast augmentation has been reported. This study investigates whether the echocardiographic image quality was impaired in women reconstructed with silicone expanders and implants. The records of 44 consecutive women who underwent echocardiographic follow-up after breast reconstruction with expanders and implants at the authors' institution from January of 2000 to August of 2012 were reviewed. The population was divided into a study group (left or bilateral breast expanders/implants, n=30) and a control group (right breast expanders/implants, n=14). The impact of breast expanders/implants on echocardiographic image quality was tested (analysis of covariance model). Patients with a breast expander/implant (left or bilateral and right breast expanders/implants) were included. The mean volume of the breast devices was 353.2±125.5 cc. The quality of the echocardiographic images was good or sufficient in the control group; in the study group, it was judged as adequate in only 50 percent of cases (15 patients) and inadequate in the remaining 15 patients (p<0.001). At multivariable analysis, a persistent relationship between device position (left versus right) and image quality (p=0.001) was shown, independent from other factors. Silicone expanders and implants in postmastectomy left breast reconstruction considerably reduce the image quality of echocardiography. This may have important clinical implications, given the need for periodic echocardiographic surveillance before and during chemotherapy. Therapeutic, III.

Periodically poled silicon

NASA Astrophysics Data System (ADS)

Hon, Nick K.; Tsia, Kevin K.; Solli, Daniel R.; Khurgin, Jacob B.; Jalali, Bahram

2010-02-01

Bulk centrosymmetric silicon lacks second-order optical nonlinearity χ(2) - a foundational component of nonlinear optics. Here, we propose a new class of photonic device which enables χ(2) as well as quasi-phase matching based on periodic stress fields in silicon - periodically-poled silicon (PePSi). This concept adds the periodic poling capability to silicon photonics, and allows the excellent crystal quality and advanced manufacturing capabilities of silicon to be harnessed for devices based on χ(2)) effects. The concept can also be simply achieved by having periodic arrangement of stressed thin films along a silicon waveguide. As an example of the utility, we present simulations showing that mid-wave infrared radiation can be efficiently generated through difference frequency generation from near-infrared with a conversion efficiency of 50% based on χ(2) values measurements for strained silicon reported in the literature [Jacobson et al. Nature 441, 199 (2006)]. The use of PePSi for frequency conversion can also be extended to terahertz generation. With integrated piezoelectric material, dynamically control of χ(2)nonlinearity in PePSi waveguide may also be achieved. The successful realization of PePSi based devices depends on the strength of the stress induced χ(2) in silicon. Presently, there exists a significant discrepancy in the literature between the theoretical and experimentally measured values. We present a simple theoretical model that produces result consistent with prior theoretical works and use this model to identify possible reasons for this discrepancy.

Glass-embedded two-dimensional silicon photonic crystal devices with a broad bandwidth waveguide and a high quality nanocavity.

PubMed

Jeon, Seung-Woo; Han, Jin-Kyu; Song, Bong-Shik; Noda, Susumu

2010-08-30

To enhance the mechanical stability of a two-dimensional photonic crystal slab structure and maintain its excellent performance, we designed a glass-embedded silicon photonic crystal device consisting of a broad bandwidth waveguide and a nanocavity with a high quality (Q) factor, and then fabricated the structure using spin-on glass (SOG). Furthermore, we showed that the refractive index of the SOG could be tuned from 1.37 to 1.57 by varying the curing temperature of the SOG. Finally, we demonstrated a glass-embedded heterostructured cavity with an ultrahigh Q factor of 160,000 by adjusting the refractive index of the SOG.

Weakly modulated silicon-dioxide-cladding gratings for silicon waveguide Fabry-Pérot cavities.

PubMed

Grote, Richard R; Driscoll, Jeffrey B; Biris, Claudiu G; Panoiu, Nicolae C; Osgood, Richard M

2011-12-19

We show by theory and experiment that silicon-dioxide-cladding gratings for Fabry-Pérot cavities on silicon-on-insulator channel ("wire") waveguides provide a low-refractive-index perturbation, which is required for several important integrated photonics components. The underlying refractive index perturbation of these gratings is significantly weaker than that of analogous silicon gratings, leading to finer control of the coupling coefficient κ. Our Fabry-Pérot cavities are designed using the transfer-matrix method (TMM) in conjunction with the finite element method (FEM) for calculating the effective index of each waveguide section. Device parameters such as coupling coefficient, κ, Bragg mirror stop band, Bragg mirror reflectivity, and quality factor Q are examined via TMM modeling. Devices are fabricated with representative values of distributed Bragg reflector lengths, cavity lengths, and propagation losses. The measured transmission spectra show excellent agreement with the FEM/TMM calculations.

Silicon-on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell-quality silicon was investigated. This was done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress in the following areas was demonstrated: (1) fabricating a 10 sq cm cell having 9.9 percent conversion efficiency; (2) producing a 225 sq cm layer of sheet silicon; and (3) obtaining 100 microns thick coatings at pull speed of 0.15 cm/sec, although approximately 50 percent of the layer exhibited dendritic growth.

Inkjet 3D printing of UV and thermal cure silicone elastomers for dielectric elastomer actuators

NASA Astrophysics Data System (ADS)

McCoul, David; Rosset, Samuel; Schlatter, Samuel; Shea, Herbert

2017-12-01

Dielectric elastomer actuators (DEAs) are an attractive form of electromechanical transducer, possessing high energy densities, an efficient design, mechanical compliance, high speed, and noiseless operation. They have been incorporated into a wide variety of devices, such as microfluidic systems, cell bioreactors, tunable optics, haptic displays, and actuators for soft robotics. Fabrication of DEA devices is complex, and the majority are inefficiently made by hand. 3D printing offers an automated and flexible manufacturing alternative that can fabricate complex, multi-material, integrated devices consistently and in high resolution. We present a novel additive manufacturing approach to DEA devices in which five commercially available, thermal and UV-cure DEA silicone rubber materials have been 3D printed with a drop-on-demand, piezoelectric inkjet system. Using this process, 3D structures and high-quality silicone dielectric elastomer membranes as thin as 2 μm have been printed that exhibit mechanical and actuation performance at least as good as conventionally blade-cast membranes. Printed silicone membranes exhibited maximum tensile strains of up to 727%, and DEAs with printed silicone dielectrics were actuated up to 6.1% area strain at a breakdown strength of 84 V μm-1 and also up to 130 V μm-1 at 2.4% strain. This approach holds great potential to manufacture reliable, high-performance DEA devices with high throughput.

Defects and device performance

NASA Technical Reports Server (NTRS)

Storti, G.; Armstrong, R.; Johnson, S.; Lin, H. C.; Regnault, W.; Yoo, K. C.

1985-01-01

The necessity for a low-cost crystalline silicon sheet material for photovoltaics has generated a number of alternative crystal growth techniques that would replace Czochralski (Cz) and float-zone (FZ) technologies. Efficiencies of devices fabricated from low resistivity FZ silicon are approaching 20%, and it is highly likely that this value will be superseded in the near future. However, FZ silicon is expensive, and is unlikely ever to be used for photovoltaics. Cz silicon has many of the desirable qualities of FZ except that minority-carrier lifetimes at lower resistivities are significantly less than those of FZ silicon. Even with Cz silicon, it is unlikely that cost goals can be met because of the poor-material yield that results from sawing and other aspects of the crystal rowth. Although other silicon sheet technologies have been investigated, almost all have characteristics that limit efficiency to approx. 16%. In summary, 20% efficient solar cells can likely be fabricated from both FZ and Cz silicon, but costs are likely to be ultimately unacceptable. Alternate silicon technologies are not likely to achieve this goal, but cost per watt figures may be eventually better than either of the single crystal technologies and may rival any thin-film technology.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1981-01-01

The photoelectric effect in structures consisting of metal deposited barium titanate film silicon is described. A radio frequency sputtering technique is used to deposit ferroelectric barium titantate films on silicon and quartz. Film properties are measured and correlated with the photoelectric effect characteristics of the films. It was found that to obtain good quality pin hole free films, it is necessary to reduce the substrate temperature during the last part of the deposition. The switching ability of the device with internal applied voltage is improved when applied with a ferroelectric memory device.

Increasing Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1999-08-24

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Increased Stabilized Performance Of Amorphous Silicon Based Devices Produced By Highly Hydrogen Diluted Lower Temperature Plasma Deposition.

DOEpatents

Li, Yaun-Min; Bennett, Murray S.; Yang, Liyou

1997-07-08

High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.

Theoretical-Experimental Analysis of the Effects of Grain Boundaries on the Electrical Properties of SOI (Silicon-on-Insulator) MOSFETS.

DTIC Science & Technology

1983-11-01

work on recrystallization of polycrystalline silicon ( polysilicon ) films deposited on silicon-dioxide has demonstrated remarkable improvement in film...quality, and thus has identified another possibly viable 1SO technology for ICs. The polysilicon -on-S10 2 technology not only has the advantages alluded...and consequently higher areal device densities. Virtually all the research to date on polysilicon -on-SiO 2 has concentrated on the

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Significant accomplishments during this reporting period include design of a plan to provide standard silicon wafers for four-probe resistivity measurements for the industry, publication of a summary report on the photoconductive decay method for measuring carrier lifetime, publication of a comprehensive review of the field of wire bond fabrication and testing, and successful completion of organizational activity leading to the establishment of a new group on quality and hardness assurance in ASTM Committee F-1 on Electronics. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers in silicon; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

Vertical power MOS transistor as a thermoelectric quasi-nanowire device

NASA Astrophysics Data System (ADS)

Roizin, Gregory; Beeri, Ofer; Peretz, Mor Mordechai; Gelbstein, Yaniv

2016-12-01

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved.

A silicon carbide array for electrocorticography and peripheral nerve recording.

PubMed

Diaz-Botia, C A; Luna, L E; Neely, R M; Chamanzar, M; Carraro, C; Carmena, J M; Sabes, P N; Maboudian, R; Maharbiz, M M

2017-10-01

Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

A silicon carbide array for electrocorticography and peripheral nerve recording

NASA Astrophysics Data System (ADS)

Diaz-Botia, C. A.; Luna, L. E.; Neely, R. M.; Chamanzar, M.; Carraro, C.; Carmena, J. M.; Sabes, P. N.; Maboudian, R.; Maharbiz, M. M.

2017-10-01

Objective. Current neural probes have a limited device lifetime of a few years. Their common failure mode is the degradation of insulating films and/or the delamination of the conductor-insulator interfaces. We sought to develop a technology that does not suffer from such limitations and would be suitable for chronic applications with very long device lifetimes. Approach. We developed a fabrication method that integrates polycrystalline conductive silicon carbide with insulating silicon carbide. The technology employs amorphous silicon carbide as the insulator and conductive silicon carbide at the recording sites, resulting in a seamless transition between doped and amorphous regions of the same material, eliminating heterogeneous interfaces prone to delamination. Silicon carbide has outstanding chemical stability, is biocompatible, is an excellent molecular barrier and is compatible with standard microfabrication processes. Main results. We have fabricated silicon carbide electrode arrays using our novel fabrication method. We conducted in vivo experiments in which electrocorticography recordings from the primary visual cortex of a rat were obtained and were of similar quality to those of polymer based electrocorticography arrays. The silicon carbide electrode arrays were also used as a cuff electrode wrapped around the sciatic nerve of a rat to record the nerve response to electrical stimulation. Finally, we demonstrated the outstanding long term stability of our insulating silicon carbide films through accelerated aging tests. Significance. Clinical translation in neural engineering has been slowed in part due to the poor long term performance of current probes. Silicon carbide devices are a promising technology that may accelerate this transition by enabling truly chronic applications.

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

PubMed Central

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F.; Ross, Caroline A.

2013-01-01

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4)O3−δ and polycrystalline (CeY2)Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2)Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates. PMID:28788379

Thermal oxidation of silicon in a residual oxygen atmosphere—the RESOX process—for self-limiting growth of thin silicon dioxide films

NASA Astrophysics Data System (ADS)

Wright, Jason T.; Carbaugh, Daniel J.; Haggerty, Morgan E.; Richard, Andrea L.; Ingram, David C.; Kaya, Savas; Jadwisienczak, Wojciech M.; Rahman, Faiz

2016-10-01

We describe in detail the growth procedures and properties of thermal silicon dioxide grown in a limited and dilute oxygen atmosphere. Thin thermal oxide films have become increasingly important in recent years due to the continuing down-scaling of ultra large scale integration metal oxide silicon field effect transistors. Such films are also of importance for organic transistors where back-gating is needed. The technique described here is novel and allows self-limited formation of high quality thin oxide films on silicon surfaces. This technique is easy to implement in both research laboratory and industrial settings. Growth conditions and their effects on film growth have been described. Properties of the resulting oxide films, relevant for microelectronic device applications, have also been investigated and reported here. Overall, our findings are that thin, high quality, dense silicon dioxide films of thicknesses up to 100 nm can be easily grown in a depleted oxygen environment at temperatures similar to that used for usual silicon dioxide thermal growth in flowing dry oxygen.

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies.

PubMed

Yoon, Jongseung; Jo, Sungjin; Chun, Ik Su; Jung, Inhwa; Kim, Hoon-Sik; Meitl, Matthew; Menard, Etienne; Li, Xiuling; Coleman, James J; Paik, Ungyu; Rogers, John A

2010-05-20

Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices to radio-frequency electronics and most forms of optoelectronics. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.

A review of recent progress in heterogeneous silicon tandem solar cells

NASA Astrophysics Data System (ADS)

Yamaguchi, Masafumi; Lee, Kan-Hua; Araki, Kenji; Kojima, Nobuaki

2018-04-01

Silicon solar cells are the most established solar cell technology and are expected to dominate the market in the near future. As state-of-the-art silicon solar cells are approaching the Shockley-Queisser limit, stacking silicon solar cells with other photovoltaic materials to form multi-junction devices is an obvious pathway to further raise the efficiency. However, many challenges stand in the way of fully realizing the potential of silicon tandem solar cells because heterogeneously integrating silicon with other materials often degrades their qualities. Recently, above or near 30% silicon tandem solar cell has been demonstrated, showing the promise of achieving high-efficiency and low-cost solar cells via silicon tandem. This paper reviews the recent progress of integrating solar cell with other mainstream solar cell materials. The first part of this review focuses on the integration of silicon with III-V semiconductor solar cells, which is a long-researched topic since the emergence of III-V semiconductors. We will describe the main approaches—heteroepitaxy, wafer bonding and mechanical stacking—as well as other novel approaches. The second part introduces the integration of silicon with polycrystalline thin-film solar cells, mainly perovskites on silicon solar cells because of its rapid progress recently. We will also use an analytical model to compare the material qualities of different types of silicon tandem solar cells and project their practical efficiency limits.

Progress in performance enhancement methods for capacitive silicon resonators

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Ono, Takahito

2017-11-01

In this paper, we review the progress in recent studies on the performance enhancement methods for capacitive silicon resonators. We provide information on various fabrication technologies and design considerations that can be employed to improve the performance of capacitive silicon resonators, including low motional resistance, small insertion loss, and high quality factor (Q). This paper contains an overview of device structures and working principles, fabrication technologies consisting of hermetic packaging, deep reactive-ion etching and neutral beam etching, and design considerations including mechanically coupled, movable electrode structures and piezoresistive heat engines.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

Tailoring the optical characteristics of microsized InP nanoneedles directly grown on silicon.

PubMed

Li, Kun; Sun, Hao; Ren, Fan; Ng, Kar Wei; Tran, Thai-Truong D; Chen, Roger; Chang-Hasnain, Connie J

2014-01-08

Nanoscale self-assembly offers a pathway to realize heterogeneous integration of III-V materials on silicon. However, for III-V nanowires directly grown on silicon, dislocation-free single-crystal quality could only be attained below certain critical dimensions. We recently reported a new approach that overcomes this size constraint, demonstrating the growth of single-crystal InGaAs/GaAs and InP nanoneedles with the base diameters exceeding 1 μm. Here, we report distinct optical characteristics of InP nanoneedles which are varied from mostly zincblende, zincblende/wurtzite-mixed, to pure wurtzite crystalline phase. We achieved, for the first time, pure single-crystal wurtzite-phase InP nanoneedles grown on silicon with bandgaps of 80 meV larger than that of zincblende-phase InP. Being able to attain excellent material quality while scaling up in size promises outstanding device performance of these nanoneedles. At room temperature, a high internal quantum efficiency of 25% and optically pumped lasing are demonstrated for single nanoneedle as-grown on silicon substrate. Recombination dynamics proves the excellent surface quality of the InP nanoneedles, which paves the way toward achieving multijunction photovoltaic cells, long-wavelength heterostructure lasers, and advanced photonic integrated circuits.

Trampoline Resonator Fabrication for Tests of Quantum Mechanics at High Mass

NASA Astrophysics Data System (ADS)

Weaver, Matthew; Pepper, Brian; Sonin, Petro; Eerkens, Hedwig; Buters, Frank; de Man, Sven; Bouwmeester, Dirk

2014-03-01

There has been much interest recently in optomechanical devices that can reach the ground state. Two requirements for achieving ground state cooling are high optical finesse in the cavity and high mechanical quality factor. We present a set of trampoline resonator devices using high stress silicon nitride and superpolishing of mirrors with sufficient finesse (as high as 60,000) and quality factor (as high as 480,000) for ground state cooling in a dilution refrigerator. These devices have a higher mass, between 80 and 100 ng, and lower frequency, between 200 and 500 kHz, than other devices that have been cooled to the ground state, enabling tests of quantum mechanics at a larger mass scale.

Fabrication Of SNS Weak Links On SOS Substrates

NASA Technical Reports Server (NTRS)

Hunt, Brian D.

1995-01-01

High-quality superconductor/normal-conductor/superconductor (SNS) devices ("weak links") containing epitaxial films of YBa(2)Cu(3)O(7-x) and SrTiO(3) fabricated on silicon-on-sapphire (SOS) substrates with help of improved multilayer buffer system. Process for fabrication of edge-defined SNS weak links described in "Edge-Geometry SNS Devices Made of Y/Ba/Cu" (NPO-18552).

Single-Event Effects in Silicon and Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaurex, Bénédicte, E-mail: benedicte.demaurex@epfl.ch; Bartlome, Richard; Seif, Johannes P.

2014-08-07

Low-temperature (≤200 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-enhanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems not only frommore » the growth conditions but also from unintentional contamination of the reactor. Based on our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

High-Q photonic resonators and electro-optic coupling using silicon-on-lithium-niobate

NASA Astrophysics Data System (ADS)

Witmer, Jeremy D.; Valery, Joseph A.; Arrangoiz-Arriola, Patricio; Sarabalis, Christopher J.; Hill, Jeff T.; Safavi-Naeini, Amir H.

2017-04-01

Future quantum networks, in which superconducting quantum processors are connected via optical links, will require microwave-to-optical photon converters that preserve entanglement. A doubly-resonant electro-optic modulator (EOM) is a promising platform to realize this conversion. Here, we present our progress towards building such a modulator by demonstrating the optically-resonant half of the device. We demonstrate high quality (Q) factor ring, disk and photonic crystal resonators using a hybrid silicon-on-lithium-niobate material system. Optical Q factors up to 730,000 are achieved, corresponding to propagation loss of 0.8 dB/cm. We also use the electro-optic effect to modulate the resonance frequency of a photonic crystal cavity, achieving a electro-optic modulation coefficient between 1 and 2 pm/V. In addition to quantum technology, we expect that our results will be useful both in traditional silicon photonics applications and in high-sensitivity acousto-optic devices.

Linear integrated optics in 3C silicon carbide.

PubMed

Martini, Francesco; Politi, Alberto

2017-05-15

The development of new photonic materials that combine diverse optical capabilities is needed to boost the integration of different quantum and classical components within the same chip. Amongst all candidates, the superior optical properties of cubic silicon carbide (3C SiC) could be merged with its crystalline point defects, enabling single photon generation, manipulation and light-matter interaction on a single device. The development of photonics devices in SiC has been limited by the presence of the silicon substrate, over which thin crystalline films are heteroepitaxially grown. By employing a novel approach in the material fabrication, we demonstrate grating couplers with coupling efficiency reaching -6 dB, sub-µm waveguides and high intrinsic quality factor (up to 24,000) ring resonators. These components are the basis for linear optical networks and essential for developing a wide range of photonics component for non-linear and quantum optics.

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

DOE PAGES

Demaurex, Bénédicte; Bartlome, Richard; Seif, Johannes P.; ...

2014-08-05

Low-temperature (≤ 180 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-ehanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems notmore » only from the growth conditions but also from unintentional contamination of the reactor. As a result of our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.« less

Silicon carbide, a semiconductor for space power electronics

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Matus, Lawrence G.

1991-01-01

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

All-optical switching in silicon-on-insulator photonic wire nano-cavities.

PubMed

Belotti, Michele; Galli, Matteo; Gerace, Dario; Andreani, Lucio Claudio; Guizzetti, Giorgio; Md Zain, Ahmad R; Johnson, Nigel P; Sorel, Marc; De La Rue, Richard M

2010-01-18

We report on experimental demonstration of all-optical switching in a silicon-on-insulator photonic wire nanocavity operating at telecom wavelengths. The switching is performed with a control pulse energy as low as approximately 0.1 pJ on a cavity device that presents very high signal transmission, an ultra-high quality-factor, almost diffraction-limited modal volume and a footprint of only 5 microm(2). High-speed modulation of the cavity mode is achieved by means of optical injection of free carriers using a nanosecond pulsed laser. Experimental results are interpreted by means of finite-difference time-domain simulations. The possibility of using this device as a logic gate is also demonstrated.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Probing Intrawire, Interwire, and Diameter-Dependent Variations in Silicon Nanowire Surface Trap Density with Pump-Probe Microscopy.

PubMed

Cating, Emma E M; Pinion, Christopher W; Christesen, Joseph D; Christie, Caleb A; Grumstrup, Erik M; Cahoon, James F; Papanikolas, John M

2017-10-11

Surface trap density in silicon nanowires (NWs) plays a key role in the performance of many semiconductor NW-based devices. We use pump-probe microscopy to characterize the surface recombination dynamics on a point-by-point basis in 301 silicon NWs grown using the vapor-liquid-solid (VLS) method. The surface recombination velocity (S), a metric of the surface quality that is directly proportional to trap density, is determined by the relationship S = d/4τ from measurements of the recombination lifetime (τ) and NW diameter (d) at distinct spatial locations in individual NWs. We find that S varies by as much as 2 orders of magnitude between NWs grown at the same time but varies only by a factor of 2 or three within an individual NW. Although we find that, as expected, smaller-diameter NWs exhibit shorter τ, we also find that smaller wires exhibit higher values of S; this indicates that τ is shorter both because of the geometrical effect of smaller d and because of a poorer quality surface. These results highlight the need to consider interwire heterogeneity as well as diameter-dependent surface effects when fabricating NW-based devices.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Optically efficient InAsSb nanowires for silicon-based mid-wavelength infrared optoelectronics.

PubMed

Zhuang, Q D; Alradhi, H; Jin, Z M; Chen, X R; Shao, J; Chen, X; Sanchez, Ana M; Cao, Y C; Liu, J Y; Yates, P; Durose, K; Jin, C J

2017-03-10

InAsSb nanowires (NWs) with a high Sb content have potential in the fabrication of advanced silicon-based optoelectronics such as infrared photondetectors/emitters and highly sensitive phototransistors, as well as in the generation of renewable electricity. However, producing optically efficient InAsSb NWs with a high Sb content remains a challenge, and optical emission is limited to 4.0 μm due to the quality of the nanowires. Here, we report, for the first time, the success of high-quality and optically efficient InAsSb NWs enabling silicon-based optoelectronics operating in entirely mid-wavelength infrared. Pure zinc-blende InAsSb NWs were realized with efficient photoluminescence emission. We obtained room-temperature photoluminescence emission in InAs NWs and successfully extended the emission wavelength in InAsSb NWs to 5.1 μm. The realization of this optically efficient InAsSb NW material paves the way to realizing next-generation devices, combining advances in III-V semiconductors and silicon.

Surface Participation Effects in Titanium Nitride and Niobium Resonators

NASA Astrophysics Data System (ADS)

Dove, Allison; Kreikebaum, John Mark; Livingston, William; Delva, Remy; Qiu, Yanjie; Lolowang, Reinhard; Ramasesh, Vinay; O'Brien, Kevin; Siddiqi, Irfan

Improving the coherence time of superconducting qubits requires a precise understanding of the location and density of surface defects. Superconducting microwave resonators are commonly used for quantum state readout and are a versatile testbed to systematically characterize materials properties as a function of device geometry and fabrication method. We report on sputter deposited titanium nitride and niobium on silicon coplanar waveguide resonators patterned using reactive ion etches to define the device geometry. We discuss the impact of different growth conditions (temperature and electrical bias) and processing techniques on the internal quality factor (Q) of these devices. In particular, to investigate the effect of surface participation, we use a Bosch process to etch many-micron-deep trenches in the silicon substrate and quantify the impact of etch depth and profile on the internal Q. This research was supported by the ARO.

Microstructure factor and mechanical and electronic properties of hydrogenated amorphous and nanocrystalline silicon thin-films for microelectromechanical systems applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mouro, J.; Gualdino, A.; Chu, V.

2013-11-14

Thin-film silicon allows the fabrication of MEMS devices at low processing temperatures, compatible with monolithic integration in advanced electronic circuits, on large-area, low-cost, and flexible substrates. The most relevant thin-film properties for applications as MEMS structural layers are the deposition rate, electrical conductivity, and mechanical stress. In this work, n{sup +}-type doped hydrogenated amorphous and nanocrystalline silicon thin-films were deposited by RF-PECVD, and the influence of the hydrogen dilution in the reactive mixture, the RF-power coupled to the plasma, the substrate temperature, and the deposition pressure on the structural, electrical, and mechanical properties of the films was studied. Three differentmore » types of silicon films were identified, corresponding to three internal structures: (i) porous amorphous silicon, deposited at high rates and presenting tensile mechanical stress and low electrical conductivity, (ii) dense amorphous silicon, deposited at intermediate rates and presenting compressive mechanical stress and higher values of electrical conductivity, and (iii) nanocrystalline silicon, deposited at very low rates and presenting the highest compressive mechanical stress and electrical conductivity. These results show the combinations of electromechanical material properties available in silicon thin-films and thus allow the optimized selection of a thin silicon film for a given MEMS application. Four representative silicon thin-films were chosen to be used as structural material of electrostatically actuated MEMS microresonators fabricated by surface micromachining. The effect of the mechanical stress of the structural layer was observed to have a great impact on the device resonance frequency, quality factor, and actuation force.« less

3D Integration for Wireless Multimedia

NASA Astrophysics Data System (ADS)

Kimmich, Georg

The convergence of mobile phone, internet, mapping, gaming and office automation tools with high quality video and still imaging capture capability is becoming a strong market trend for portable devices. High-density video encode and decode, 3D graphics for gaming, increased application-software complexity and ultra-high-bandwidth 4G modem technologies are driving the CPU performance and memory bandwidth requirements close to the PC segment. These portable multimedia devices are battery operated, which requires the deployment of new low-power-optimized silicon process technologies and ultra-low-power design techniques at system, architecture and device level. Mobile devices also need to comply with stringent silicon-area and package-volume constraints. As for all consumer devices, low production cost and fast time-to-volume production is key for success. This chapter shows how 3D architectures can bring a possible breakthrough to meet the conflicting power, performance and area constraints. Multiple 3D die-stacking partitioning strategies are described and analyzed on their potential to improve the overall system power, performance and cost for specific application scenarios. Requirements and maturity of the basic process-technology bricks including through-silicon via (TSV) and die-to-die attachment techniques are reviewed. Finally, we highlight new challenges which will arise with 3D stacking and an outlook on how they may be addressed: Higher power density will require thermal design considerations, new EDA tools will need to be developed to cope with the integration of heterogeneous technologies and to guarantee signal and power integrity across the die stack. The silicon/wafer test strategies have to be adapted to handle high-density IO arrays, ultra-thin wafers and provide built-in self-test of attached memories. New standards and business models have to be developed to allow cost-efficient assembly and testing of devices from different silicon and technology providers.

Programmable 2-D Addressable Cryogenic Aperture Masks

NASA Technical Reports Server (NTRS)

Kutyrev, A. S.; Moseley, S. H.; Jhabvala, M.; Li, M.; Schwinger, D. S.; Silverberg, R. F.; Wesenberg, R. P.

2004-01-01

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Low temperature surface passivation of crystalline silicon and its application to interdigitated back contact silicon heterojunction (ibc-shj) solar cell

NASA Astrophysics Data System (ADS)

Shu, Zhan

With the absence of shading loss together with improved quality of surface passivation introduced by low temperature processed amorphous silicon crystalline silicon (a-Si:H/c-Si) heterojunction, the interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell exhibits a potential for higher conversion efficiency and lower cost than a traditional front contact diffused junction solar cell. In such solar cells, the front surface passivation is of great importance to achieve both high open-circuit voltage (Voc) and short-circuit current (Jsc). Therefore, the motivation of this work is to develop a low temperature processed structure for the front surface passivation of IBC-SHJ solar cells, which must have an excellent and stable passivation quality as well as a good anti-reflection property. Four different thin film materials/structures were studied and evaluated for this purpose, namely: amorphous silicon nitride (a-SiNx:H), thick amorphous silicon film (a-Si:H), amorphous silicon/silicon nitride/silicon carbide (a-Si:H/a-SiN x:H/a-SiC:H) stack structure with an ultra-thin a-Si:H layer, and zinc sulfide (ZnS). It was demonstrated that the a-Si:H/a-SiNx:H/a-SiC:H stack surpasses other candidates due to both of its excellent surface passivation quality (SRV<5 cm/s) and lower absorption losses. The low recombination rate at the stack structure passivated c-Si surface is found to be resulted from (i) field effect passivation due to the positive fixed charge (Q fix~1x1011 cm-2 with 5 nm a-Si:H layer) in a-SiNx:H as measured from capacitance-voltage technique, and (ii) reduced defect state density (mid-gap Dit~4x1010 cm-2eV-1) at a-Si:H/c-Si interface provided by a 5 nm thick a-Si:H layer, as characterized by conductance-frequency measurements. Paralleled with the experimental studies, a computer program was developed in this work based on the extended Shockley-Read-Hall (SRH) model of surface recombination. With the help of this program, the experimental injection level dependent SRV curves of the stack passivated c-Si samples were successfully reproduced and the carrier capture cross sections of interface defect states were extracted. Additionally, anti-reflection properties of the stack structure were optimized and optical losses were analyzed. The Voc over 700 mV and Jsc over 38 mA/cm2 were achieved in IBC-SHJ solar cells using the stack structure for front surface passivation. Direct comparison shows that such low temperature deposited stack structure developed in this work achieves comparable device performance to the high temperature processed front surface passivation structure used in other high efficiency IBC solar cells. However, the lower fill factor (FF) of IBC-SHJ solar cell as compared with traditional front a-Si:H/c-Si heterojunction cell (HIT cell) greatly limits the overall performance of these devices. Two-dimensional (2D) simulations were used to comparatively model the HIT and IBC-SHJ solar cells to understand the underlying device physics which controls cell performance. The effects of a wide range of device parameters were investigated in the simulation, and pathways to improve the FF of IBC-SHJ solar cell were suggested.

Low optical-loss facet preparation for silica-on-silicon photonics using the ductile dicing regime

NASA Astrophysics Data System (ADS)

Carpenter, Lewis G.; Rogers, Helen L.; Cooper, Peter A.; Holmes, Christopher; Gates, James C.; Smith, Peter G. R.

2013-11-01

The efficient production of high-quality facets for low-loss coupling is a significant production issue in integrated optics, usually requiring time consuming and manually intensive lapping and polishing steps, which add considerably to device fabrication costs. The development of precision dicing saws with diamond impregnated blades has allowed optical grade surfaces to be machined in crystalline materials such as lithium niobate and garnets. In this report we investigate the optimization of dicing machine parameters to obtain optical quality surfaces in a silica-on-silicon planar device demonstrating high optical quality in a commercially important glassy material. We achieve a surface roughness of 4.9 nm (Sa) using the optimized dicing conditions. By machining a groove across a waveguide, using the optimized dicing parameters, a grating based loss measurement technique is used to measure precisely the average free space interface loss per facet caused by scattering as a consequence of surface roughness. The average interface loss per facet was calculated to be: -0.63 dB and -0.76 dB for the TE and TM polarizations, respectively.

Electron-beam-induced information storage in hydrogenated amorphous silicon devices

DOEpatents

Yacobi, B.G.

1985-03-18

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge collection efficiency and thus in the charge collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage.

Thermal and Kerr nonlinear properties of plasma-deposited silicon nitride/ silicon dioxide waveguides.

PubMed

Ikeda, Kazuhiro; Saperstein, Robert E; Alic, Nikola; Fainman, Yeshaiahu

2008-08-18

We introduce and present experimental evaluations of loss and nonlinear optical response in a waveguide and an optical resonator, both implemented with a silicon nitride/ silicon dioxide material platform prepared by plasma-enhanced chemical vapor deposition with dual frequency reactors that significantly reduce the stress and the consequent loss of the devices. We measure a relatively small loss of approximately 4dB/cm in the waveguides. The fabricated ring resonators in add-drop and all-pass arrangements demonstrate quality factors of Q=12,900 and 35,600. The resonators are used to measure both the thermal and ultrafast Kerr nonlinearities. The measured thermal nonlinearity is larger than expected, which is attributed to slower heat dissipation in the plasma-deposited silicon dioxide film. The n2 for silicon nitride that is unknown in the literature is measured, for the first time, as 2.4 x 10(-15)cm(2)/W, which is 10 times larger than that for silicon dioxide.

Electron-beam-induced information storage in hydrogenated amorphous silicon device

DOEpatents

Yacobi, Ben G.

1986-01-01

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge-collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge-collection efficiency; and thus in the charge-collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage, in the device, which darkened areas can be restored to their original charge-collection efficiency by heating the hydrogenated amorphous silicon to a temperature of about 100.degree. C. to 250.degree. C. for a sufficient period of time to provide for such restoration.

Quality Control Method for a Micro-Nano-Channel Microfabricated Device

NASA Technical Reports Server (NTRS)

Grattoni, Alessandro; Ferrari, Mauro; Li, Xuewu

2012-01-01

A variety of silicon-fabricated devices is used in medical applications such as drug and cell delivery, and DNA and protein separation and analysis. When a fluidic device inlet is connected to a compressed gas reservoir, and the outlet is at a lower pressure, a gas flow occurs through the membrane toward the outside. The method relies on the measurement of the gas pressure over the elapsed time inside the upstream and downstream environments. By knowing the volume of the upstream reservoir, the gas flow rate through the membrane over the pressure drop can be calculated. This quality control method consists of measuring the gas flow through a device and comparing the results with a standard curve, which can be obtained by testing standard devices. Standard devices can be selected through a variety of techniques, both destructive and nondestructive, such as SEM, AFM, and standard particle filtration.

Grating-assisted coupling to nanophotonic circuits in microcrystalline diamond thin films.

PubMed

Rath, Patrik; Khasminskaya, Svetlana; Nebel, Christoph; Wild, Christoph; Pernice, Wolfram Hp

2013-01-01

Synthetic diamond films can be prepared on a waferscale by using chemical vapour deposition (CVD) on suitable substrates such as silicon or silicon dioxide. While such films find a wealth of applications in thermal management, in X-ray and terahertz window design, and in gyrotron tubes and microwave transmission lines, their use for nanoscale optical components remains largely unexplored. Here we demonstrate that CVD diamond provides a high-quality template for realizing nanophotonic integrated optical circuits. Using efficient grating coupling devices prepared from partially etched diamond thin films, we investigate millimetre-sized optical circuits and achieve single-mode waveguiding at telecoms wavelengths. Our results pave the way towards broadband optical applications for sensing in harsh environments and visible photonic devices.

Radiation Resistance Studies of Amorphous Silicon Alloy Photovoltaic Materials

NASA Technical Reports Server (NTRS)

Woodyard, James R.

1994-01-01

The radiation resistance of commercial solar cells fabricated from hydrogenated amorphous silicon alloys was investigated. A number of different device structures were irradiated with 1.0 MeV protons. The cells were insensitive to proton fluences below 1E12 sq cm. The parameters of the irradiated cells were restored with annealing at 200 C. The annealing time was dependent on proton fluence. Annealing devices for one hour restores cell parameters for fluences below lE14 sq cm require longer annealing times. A parametric fitting model was used to characterize current mechanisms observed in dark I-V measurements. The current mechanisms were explored with irradiation fluence, and voltage and light soaking times. The thermal generation current density and quality factor increased with proton fluence. Device simulation shows the degradation in cell characteristics may be explained by the reduction of the electric field in the intrinsic layer.

Investigation of the stability and 1.0 MeV proton radiation resistance of commercially produced hydrogenated amorphous silicon alloy solar cells

NASA Technical Reports Server (NTRS)

Lord, Kenneth R., II; Walters, Michael R.; Woodyard, James R.

1994-01-01

The radiation resistance of commercial solar cells fabricated from hydrogenated amorphous silicon alloys is reported. A number of different device structures were irradiated with 1.0 MeV protons. The cells were annealing at 200 C. The annealing time was dependent on proton fluence. Annealing devices for one hour restores cell parameters or fluences below 1(exp 14) cm(exp -2); fluences above 1(exp 14) cm(exp -2) require longer annealing times. A parametric fitting model was used to characterize current mechanisms observed in dark I-V measurements. The current mechanisms were explored with irradiation fluence, and voltage and light soaking times. The thermal generation current density and quality factor increased with proton fluence. Device simulation shows the degradation in cell characteristics may be explained by the reduction of the electric field in the intrinsic layer.

Technological processes of grating light valve as diffractive spatial light modulator in laser phototypesetting system

NASA Astrophysics Data System (ADS)

Zhang, Wei; Geng, Yu; Hou, Changlun; Yang, Guoguang; Bai, Jian

2008-11-01

Grating Light Valve (GLV) is a kind of optics device based on Micro-Opto-Electro-Mechanical System (MOEMS) technology, utilizing diffraction principle to switch, attenuate and modulate light. In this paper, traditional GLV device's structure and its working principle are illuminated, and a kind of modified GLV structure is presented, with details introduction of the fabrication technology. The GLV structure includes single crystal silicon substrate, silicon dioxide isolating layer, aluminum layer of fixed ribbons and silicon nitride of movable ribbons. In the fabrication, lots of techniques are adopted, such as low-pressure chemical vapor deposition (LPCVD), photolithography, etching and evaporation. During the fabrication processes, Photolithography is a fundamental and fatal technology, which determines etching result and GLV quality. Some methods are proposed through repeated experiments, to improve etching result greatly and guide the practical application. This kind of GLV device can be made both small and inexpensively, and has been tested to show proper range of actuation under DC bias, with good performance. The GLV device also has merits such as low cost, simple technology, high fill ratio and low driving voltage. It can properly be well used and match the demands of high light power needed in laser phototypesetting system, as a high-speed, high-resolution light modulator.

High-efficiency cell concepts on low-cost silicon sheets

NASA Technical Reports Server (NTRS)

Bell, R. O.; Ravi, K. V.

1985-01-01

The limitations on sheet growth material in terms of the defect structure and minority carrier lifetime are discussed. The effect of various defects on performance are estimated. Given these limitations designs for a sheet growth cell that will make the best of the material characteristics are proposed. Achievement of optimum synergy between base material quality and device processing variables is proposed. A strong coupling exists between material quality and the variables during crystal growth, and device processing variables. Two objectives are outlined: (1) optimization of the coupling for maximum performance at minimal cost; and (2) decoupling of materials from processing by improvement in base material quality to make it less sensitive to processing variables.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Graphene optical modulator

NASA Astrophysics Data System (ADS)

Liu, Ming; Yin, Xiaobo; Wang, Feng; Zhang, Xiang

2011-10-01

Data communications have been growing at a speed even faster than Moore's Law, with a 44-fold increase expected within the next 10 years. Data Transfer on such scale would have to recruit optical communication technology and inspire new designs of light sources, modulators, and photodetectors. An ideal optical modulator will require high modulation speed, small device footprint and large operating bandwidth. Silicon modulators based on free carrier plasma dispersion effect and compound semiconductors utilizing direct bandgap transition have seen rapid improvement over the past decade. One of the key limitations for using silicon as modulator material is its weak refractive index change, which limits the footprint of silicon Mach-Zehnder interferometer modulators to millimeters. Other approaches such as silicon microring modulators reduce the operation wavelength range to around 100 pm and are highly sensitive to typical fabrication tolerances and temperature fluctuations. Growing large, high quality wafers of compound semiconductors, and integrating them on silicon or other substrates is expensive, which also restricts their commercialization. In this work, we demonstrate that graphene can be used as the active media for electroabsorption modulators. By tuning the Fermi energy level of the graphene layer, we induced changes in the absorption coefficient of graphene at communication wavelength and achieve a modulation depth above 3 dB. This integrated device also has the potential of working at high speed.

Nanostructured Silicon Used for Flexible and Mobile Electricity Generation.

PubMed

Sun, Baoquan; Shao, Mingwang; Lee, Shuitong

2016-12-01

The use of nanostructured silicon for the generation of electricity in flexible and mobile devices is reviewed. This field has attracted widespread interest in recent years due to the emergence of plastic electronics. Such developments are likely to alter the nature of power sources in the near future. For example, flexible photovoltaic cells can supply electricity to rugged and collapsible electronics, biomedical devices, and conformable solar panels that are integrated with the curved surfaces of vehicles or buildings. Here, the unique optical and electrical properties of nanostructured silicon are examined, with regard to how they can be exploited in flexible photovoltaics, thermoelectric generators, and piezoelectric devices, which serve as power generators. Particular emphasis is placed on organic-silicon heterojunction photovoltaic devices, silicon-nanowire-based thermoelectric generators, and core-shell silicon/silicon oxide nanowire-based piezoelectric devices, because they are flexible, lightweight, and portable. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Structural Color Filters Enabled by a Dielectric Metasurface Incorporating Hydrogenated Amorphous Silicon Nanodisks.

PubMed

Park, Chul-Soon; Shrestha, Vivek Raj; Yue, Wenjing; Gao, Song; Lee, Sang-Shin; Kim, Eun-Soo; Choi, Duk-Yong

2017-05-31

It is advantageous to construct a dielectric metasurface in silicon due to its compatibility with cost-effective, mature processes for complementary metal-oxide-semiconductor devices. However, high-quality crystalline-silicon films are difficult to grow on foreign substrates. In this work, we propose and realize highly efficient structural color filters based on a dielectric metasurface exploiting hydrogenated amorphous silicon (a-Si:H), known to be lossy in the visible regime. The metasurface is comprised of an array of a-Si:H nanodisks embedded in a polymer, providing a homogeneously planarized surface that is crucial for practical applications. The a-Si:H nanodisk element is deemed to individually support an electric dipole (ED) and magnetic dipole (MD) resonance via Mie scattering, thereby leading to wavelength-dependent filtering characteristics. The ED and MD can be precisely identified by observing the resonant field profiles with the assistance of finite-difference time-domain simulations. The completed color filters provide a high transmission of around 90% in the off-resonance band longer than their resonant wavelengths, exhibiting vivid subtractive colors. A wide range of colors can be facilitated by tuning the resonance by adjusting the structural parameters like the period and diameter of the a-Si:H nanodisk. The proposed devices will be actively utilized to implement color displays, imaging devices, and photorealistic color printing.

High-Q photonic resonators and electro-optic coupling using silicon-on-lithium-niobate

PubMed Central

Witmer, Jeremy D.; Valery, Joseph A.; Arrangoiz-Arriola, Patricio; Sarabalis, Christopher J.; Hill, Jeff T.; Safavi-Naeini, Amir H.

2017-01-01

Future quantum networks, in which superconducting quantum processors are connected via optical links, will require microwave-to-optical photon converters that preserve entanglement. A doubly-resonant electro-optic modulator (EOM) is a promising platform to realize this conversion. Here, we present our progress towards building such a modulator by demonstrating the optically-resonant half of the device. We demonstrate high quality (Q) factor ring, disk and photonic crystal resonators using a hybrid silicon-on-lithium-niobate material system. Optical Q factors up to 730,000 are achieved, corresponding to propagation loss of 0.8 dB/cm. We also use the electro-optic effect to modulate the resonance frequency of a photonic crystal cavity, achieving a electro-optic modulation coefficient between 1 and 2 pm/V. In addition to quantum technology, we expect that our results will be useful both in traditional silicon photonics applications and in high-sensitivity acousto-optic devices. PMID:28406177

Mode-converting coupler for silicon-on-sapphire devices

NASA Astrophysics Data System (ADS)

Zlatanovic, S.; Offord, B. W.; Owen, M.; Shimabukuro, R.; Jacobs, E. W.

2015-02-01

Silicon-on-sapphire devices are attractive for the mid-infrared optical applications up to 5 microns due to the low loss of both silicon and sapphire in this wavelength band. Designing efficient couplers for silicon-on-sapphire devices presents a challenge due to a highly confined mode in silicon and large values of refractive index of both silicon and sapphire. Here, we present design, fabrication, and measurements of a mode-converting coupler for silicon-on-sapphire waveguides. We utilize a mode converter layout that consists of a large waveguide that is overlays a silicon inverse tapered waveguide. While this geometry was previously utilized for silicon-on-oxide devices, the novelty is in using materials that are compatible with the silicon-on-sapphire platform. In the current coupler the overlaying waveguide is made of silicon nitride. Silicon nitride is the material of choice because of the large index of refraction and low absorption from near-infrared to mid-infrared. The couplers were fabricated using a 0.25 micron silicon-on-sapphire process. The measured coupling loss from tapered lensed silica fibers to the silicon was 4.8dB/coupler. We will describe some challenges in fabrication process and discuss ways to overcome them.

Use of silicon oxynitride as a sacrificial material for microelectromechanical devices

DOEpatents

Habermehl, Scott D.; Sniegowski, Jeffry J.

2001-01-01

The use of silicon oxynitride (SiO.sub.x N.sub.y) as a sacrificial material for forming a microelectromechanical (MEM) device is disclosed. Whereas conventional sacrificial materials such as silicon dioxide and silicate glasses are compressively strained, the composition of silicon oxynitride can be selected to be either tensile-strained or substantially-stress-free. Thus, silicon oxynitride can be used in combination with conventional sacrificial materials to limit an accumulation of compressive stress in a MEM device; or alternately the MEM device can be formed entirely with silicon oxynitride. Advantages to be gained from the use of silicon oxynitride as a sacrificial material for a MEM device include the formation of polysilicon members that are substantially free from residual stress, thereby improving the reliability of the MEM device; an ability to form the MEM device with a higher degree of complexity and more layers of structural polysilicon than would be possible using conventional compressively-strained sacrificial materials; and improved manufacturability resulting from the elimination of wafer distortion that can arise from an excess of accumulated stress in conventional sacrificial materials. The present invention is useful for forming many different types of MEM devices including accelerometers, sensors, motors, switches, coded locks, and flow-control devices, with or without integrated electronic circuitry.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

A Silicon Disk with Sandwiched Piezoelectric Springs for Ultra-low Frequency Energy Harvesting

NASA Astrophysics Data System (ADS)

Lu, J.; Zhang, L.; Yamashita, T.; Takei, R.; Makimoto, N.; Kobayashi, T.

2015-12-01

Exploiting the sporadic availability of energy by energy harvesting devices is an attractive solution to power wireless sensor nodes and many other distributed modules for much longer operation duration and much lower maintenance cost after they are deployed. MEMS energy harvesting devices exhibit unique advantageous of super-compact size, mass productivity, and easy-integration with sensors, actuators and other integrated circuits. However, MEMS vibration energy harvesting devices are rather difficult to be used practically due to their poor response to most of the ambient vibrations at ultra-low frequency range. In this paper, a micromachined silicon disk with sandwiched piezoelectric springs was successfully developed with resonant frequency of 15.36∼42.42 Hz and quality factor of 39∼55 for energy harvesting. Footprint size of the device was 6 mm × 6 mm, which is less than half of the piezoelectric cantilevers, while the device can scavenge reasonably high power of 0.57 μW at the acceleration of 0.1 g. The evaluation results also suggested that the device was quite sensitive as a sensor for selective monitoring of vibrations at a certain frequency.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Lateral power MOSFETs in silicon carbide

NASA Astrophysics Data System (ADS)

Spitz, Jan

2001-07-01

Because of its large bandgap, its high critical electric field, and its high quality native SiO2, silicon carbide is considered to be the material of choice for power switching electronics in the future. Until 1997 the maximum thickness of commercially available epilayers serving as the drift region for power devices has been limited to 10--15 mum, limiting the maximum blocking voltage to 1500 V for vertical power devices in silicon carbide. In this study, we present the first lateral power devices on a semi-insulating vanadium doped substrate of silicon carbide. The first generation of lateral DMOSFETs in 4H-SiC yielded a blocking voltage of 2.6 kV---more than twice what was previously reported for any SiC MOSFETs---but suffered from low MOS channel mobility caused by the high anneal temperatures (≥1600°C) required to activate the p-type ion-implant. Combining the high blocking-voltage of the vanadium-doped substrate with the higher MOS mobility previously achieved by an epitaxially-grown accumulation channel leads us to the LACCUFET device: No p-type implant is necessary. This device shows a blocking voltage of 2.7 kV unmatched by any SiC transistor until February 2000 combined with a much lower specific on-resistance of 3.6 O•cm2. The ability to combine long-channel test MOSFETs with high channel mobility of 27 cm2/(volt·sec) in 4H-SiC with power devices of 13 cm2/(volt·sec) on the same chip has been demonstrated. The Figure of Merit Vblock 2/Ron,sp for this new NON-RESURF LDMOSFET in 4H-SiC is close to the theoretical limit for vertical power devices made of silicon. The specific on-resistance can be reduced by factor 2.5 by forward-biasing the p-base to source junction by 2 to 3 volts. Basic operation in Static Induction Injection Accumulation FET (SIAFET) mode has been demonstrated. Lateral (Non-Punch-Through) Insulated Gate Bipolar Transistors (LIGBT) have been presented for the first time showing similar on-resistance and blocking voltages but significantly higher on-currents for both 4H and 6H-SiC devices compared to their MOSFET counterparts. Test p-i-n diodes show lower on-resistance by carrier injection into the drift region.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.

Aerospace Sensor Component and Subsystem Investigation and Innovation-2 Component Exploration and Development (ASCSII-2 CED) Delivery Order 0003: Hermetically Sealed Cavities in 3-D GaAs-Silicon and Silicon-Silicon Packages for Microelectromechanical System (MEMS) Devices Using Selective and Large-Scale Bonding

DTIC Science & Technology

2003-03-01

and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and eutectic SnPb solders. Laser and...of GaAs-to-silicon and silicon-to-silicon to produce cavities for 3-D assembly of MEMS devices has been demonstrated using SnAgCu and euctectic...research_images/ 3.2 Solder Reflow The reflow profile for SnAgCu solder was developed on the Sikama convection/ conduction reflow oven using a continuous

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Fabrication of ultra-high aspect ratio (>160:1) silicon nanostructures by using Au metal assisted chemical etching

NASA Astrophysics Data System (ADS)

Li, Hailiang; Ye, Tianchun; Shi, Lina; Xie, Changqing

2017-12-01

We present a facile and effective approach for fabricating high aspect ratio, dense and vertical silicon nanopillar arrays, using a combination of metal etching following electron-beam lithography and Au metal assisted chemical etching (MacEtch). Ti/Au nanostructures used as catalysts in MacEtch are formed by single layer resist-based electron-beam exposure followed by ion beam etching. The effects of MacEtch process parameters, including half period, etching time, the concentrations of H2O2 and HF, etching temperature and drying method are systematically investigated. Especially, we demonstrate an enhancement of etching quality by employing cold MacEtch process, and an enhancement in preventing the collapse of high aspect ratio nanostructures by employing low surface tension rinse liquid and natural evaporation in the drying stage. Using an optimized MacEtch process, vertical silicon nanopillar arrays with a period of 250 nm and aspect ratio up to 160:1 are realized. Our results should be instructive for exploring the achievable aspect ratio limit in silicon nanostructures and may find potential applications in photovoltaic devices, thermoelectric devices and x-ray diffractive optics.

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

NASA Technical Reports Server (NTRS)

Kuczmarski, Maria A.; Neudeck, Philip G.

2000-01-01

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

A practical guide for the fabrication of microfluidic devices using glass and silicon

PubMed Central

Iliescu, Ciprian; Taylor, Hayden; Avram, Marioara; Miao, Jianmin; Franssila, Sami

2012-01-01

This paper describes the main protocols that are used for fabricating microfluidic devices from glass and silicon. Methods for micropatterning glass and silicon are surveyed, and their limitations are discussed. Bonding methods that can be used for joining these materials are summarized and key process parameters are indicated. The paper also outlines techniques for forming electrical connections between microfluidic devices and external circuits. A framework is proposed for the synthesis of a complete glass/silicon device fabrication flow. PMID:22662101

Evaluation of transition metal oxide as carrier-selective contacts for silicon heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ding, L.; Boccard, Matthieu; Holman, Zachary

2015-04-06

"Reducing light absorption in the non-active solar cell layers, while enabling the extraction of the photogenerated minority carriers at quasi-Fermi levels are two key factors to improve current generation and voltage, and therefore efficiency of silicon heterojunction solar devices. To address these two critical aspects, transition metal oxide materials have been proposed as alternative to the n- and p-type amorphous silicon used as electron and hole selective contacts, respectively. Indeed, transition metal oxides such as molybdenum oxide, titanium oxide, nickel oxide or tungsten oxide combine a wide band gap typically over 3 eV with a band structure and theoretical bandmore » alignment with silicon that results in high transparency to the solar spectrum and in selectivity for the transport of only one carrier type. Improving carrier extraction or injection using transition metal oxide has been a topic of investigation in the field of organic solar cells and organic LEDs; from these pioneering works a lot of knowledge has been gained on materials properties, ways to control these during synthesis and deposition, and their impact on device performance. Recently, the transfer of some of this knowledge to silicon solar cells and the successful application of some metal oxide to contact heterojunction devices have gained much attention. In this contribution, we investigate the suitability of various transition metal oxide films (molybdenum oxide, titanium oxide, and tungsten oxide) deposited either by thermal evaporation or sputtering as transparent hole or electron selective transport layer for silicon solar cells. In addition to systematically characterize their optical and structural properties, we use photoemission spectroscopy to relate compound stoichiometry to band structure and characterize band alignment to silicon. The direct silicon/metal oxide interface is further analyzed by quasi-steady state photoconductance decay method to assess the quality of surface passivation. In complement, we construct full device structures incorporating in some cases surface passivation schemes, with measured initial conversion efficiency over 15% and evaluate the carrier transport properties using temperature-dependent current-voltage and capacitance-voltage measurements. With this detailed characterization study, we aim at providing the framework to assess the potential of a material as a carrier selective contact and the understanding of how each of the aforementioned parameters on the metal oxide films influence the full solar cell operating performances.« less

Advances in Single and Multijunction III-V Photovoltaics on Silicon for Space Power

NASA Technical Reports Server (NTRS)

Wilt, David M.; Fitzgerald, Eugene A.; Ringel, Steven A.

2005-01-01

A collaborative research effort at MIT, Ohio State University and NASA has resulted in the demonstration of record quality gallium arsenide (GaAs) based single junction photovoltaic devices on silicon (Si) substrates. The ability to integrate highly efficient, radiation hard III-V based devices on silicon offers the potential for dramatic reductions in cell mass (approx.2x) and increases in cell area. Both of these improvements offer the potential for dramatic reductions in the cost of on-orbit electrical power. Recently, lattice matched InGaP/GaAs and metamorphic InGaP/InGaAs dual junction solar cells were demonstrated by MBE and OMVPE, respectively. Single junction GaAs on Si devices have been integrated into a space flight experiment (MISSES), scheduled to be launched to the International Space Station in March of 2005. I-V performance data from the GaAs/Si will be collected on-orbit and telemetered to ground stations daily. Microcracks in the GaAs epitaxial material, generated because of differences in the thermal expansion coefficient between GaAs and Si, are of concern in the widely varying thermal environment encountered in low Earth orbit. Ground based thermal life cycling (-80 C to + 80 C) equivalent to 1 year in LEO has been conducted on GaAs/Si devices with no discernable degradation in device performance, suggesting that microcracks may not limit the ability to field GaAs/Si in harsh thermal environments. Recent advances in the development and testing of III-V photovoltaic devices on Si will be presented.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-03-21

A method is disclosed for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics. 7 figures.

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2014 CFR

2014-04-01

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21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

21 CFR 878.4025 - Silicone sheeting.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone sheeting. 878.4025 Section 878.4025 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Surgical Devices § 878.4025 Silicone sheeting. (a...

Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer

DOEpatents

Carlson, David E.

1980-01-01

Amorphous silicon Schottky barrier solar cells which incorporate a thin insulating layer and a thin doped layer adjacent to the junction forming metal layer exhibit increased open circuit voltages compared to standard rectifying junction metal devices, i.e., Schottky barrier devices, and rectifying junction metal insulating silicon devices, i.e., MIS devices.

Silicon-graphene photonic devices

NASA Astrophysics Data System (ADS)

Yin, Yanlong; Li, Jiang; Xu, Yang; Tsang, Hon Ki; Dai, Daoxin

2018-06-01

Silicon photonics has attracted much attention because of the advantages of CMOS (complementary-metal-oxide-semiconductor) compatibility, ultra-high integrated density, etc. Great progress has been achieved in the past decades. However, it is still not easy to realize active silicon photonic devices and circuits by utilizing the material system of pure silicon due to the limitation of the intrinsic properties of silicon. Graphene has been regarded as a promising material for optoelectronics due to its unique properties and thus provides a potential option for realizing active photonic integrated devices on silicon. In this paper, we present a review on recent progress of some silicon-graphene photonic devices for photodetection, all-optical modulation, as well as thermal-tuning. Project supported by the National Major Research and Development Program (No. 2016YFB0402502), the National Natural Science Foundation of China (Nos. 11374263, 61422510, 61431166001, 61474099, 61674127), and the National Key Research and Development Program (No. 2016YFA0200200).

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

21 CFR 878.3540 - Silicone gel-filled breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone gel-filled breast prosthesis. 878.3540 Section 878.3540 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3540 Silicone gel...

21 CFR 878.3530 - Silicone inflatable breast prosthesis.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Silicone inflatable breast prosthesis. 878.3530 Section 878.3530 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES GENERAL AND PLASTIC SURGERY DEVICES Prosthetic Devices § 878.3530 Silicone...

Method for sputtering a PIN microcrystalline/amorphous silicon semiconductor device with the P and N-layers sputtered from boron and phosphorous heavily doped targets

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-04-02

A silicon PIN microcrystalline/amorphous silicon semiconductor device is constructed by the sputtering of N, and P layers of silicon from silicon doped targets and the I layer from an undoped target, and at least one semi-transparent ohmic electrode.

Oxygen-aided synthesis of polycrystalline graphene on silicon dioxide substrates.

PubMed

Chen, Jianyi; Wen, Yugeng; Guo, Yunlong; Wu, Bin; Huang, Liping; Xue, Yunzhou; Geng, Dechao; Wang, Dong; Yu, Gui; Liu, Yunqi

2011-11-09

We report the metal-catalyst-free synthesis of high-quality polycrystalline graphene on dielectric substrates [silicon dioxide (SiO(2)) or quartz] using an oxygen-aided chemical vapor deposition (CVD) process. The growth was carried out using a CVD system at atmospheric pressure. After high-temperature activation of the growth substrates in air, high-quality polycrystalline graphene is subsequently grown on SiO(2) by utilizing the oxygen-based nucleation sites. The growth mechanism is analogous to that of growth for single-walled carbon nanotubes. Graphene-modified SiO(2) substrates can be directly used in transparent conducting films and field-effect devices. The carrier mobilities are about 531 cm(2) V(-1) s(-1) in air and 472 cm(2) V(-1) s(-1) in N(2), which are close to that of metal-catalyzed polycrystalline graphene. The method avoids the need for either a metal catalyst or a complicated and skilled postgrowth transfer process and is compatible with current silicon processing techniques.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Significant accomplishments include development of a procedure to correct for the substantial differences of transistor delay time as measured with different instruments or with the same instrument at different frequencies; association of infrared response spectra of poor quality germanium gamma ray detectors with spectra of detectors fabricated from portions of a good crystal that had been degraded in known ways; and confirmation of the excellent quality and cosmetic appearance of ultrasonic bonds made with aluminum ribbon wire. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon, development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

Investigation of the Stability and 1.0 MeV Proton Radiation Resistance of Commercially Produced Hydrogenated Amorphous Silicon Alloy Solar Cells

NASA Technical Reports Server (NTRS)

Lord, Kenneth R., II; Walters, Michael R.; Woodyard, James R.

1994-01-01

The radiation resistance of commercial solar cells fabricated from hydrogenated amorphous silicon alloys is reported. A number of different device structures were irradiated with 1.0 MeV protons. The cells were insensitive to proton fluences below 1E12 sq cm. The parameters of the irradiated cells were restored with annealing at 200 C. The annealing time was dependent on proton fluence. Annealing devices for one hour restores cell parameters for fluences below 1E14 sq cm fluences above 1E14 sq cm require longer annealing times. A parametric fitting model was used to characterize current mechanisms observed In dark I-V measurements. The current mechanism were explored with irradiation fluence, and voltage and light soaking times. The thermal generation current density and quality factor increased with proton fluence. Device simulation shows the degradation in cell characteristics may be explained by the reduction of the electric field in the intrinsic layer.

Single-Event Effects in Silicon Carbide Power Devices

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dong, Rui; Moore, Logan; Ocola, Leonidas E.

The mask-free patterning technique is employed to fabricate arrays of MoS2 and WS2 structures on silicon and graphene substrates with quality interfaces. By depositing precursor inks with the AFM cantilevers and subsequent heat treatment in the CVD furnace, it is demonstrated that MoS2 and WS2 structures can be formed on graphene surfaces at predefined device architectures.

Semiconductor technology program: Progress briefs

NASA Technical Reports Server (NTRS)

Galloway, K. F.; Scace, R. I.; Walters, E. J.

1981-01-01

Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon.

Pilot evaluation of electricity-reliability and power-quality monitoring in California's Silicon Valley with the I-Grid(R) system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Eto, Joseph; Divan, Deepak; Brumsickle, William

2004-02-01

Power-quality events are of increasing concern for the economy because today's equipment, particularly computers and automated manufacturing devices, is susceptible to these imperceptible voltage changes. A small variation in voltage can cause this equipment to shut down for long periods, resulting in significant business losses. Tiny variations in power quality are difficult to detect except with expensive monitoring equipment used by trained technicians, so many electricity customers are unaware of the role of power-quality events in equipment malfunctioning. This report describes the findings from a pilot study coordinated through the Silicon Valley Manufacturers Group in California to explore the capabilitiesmore » of I-Grid(R), a new power-quality monitoring system. This system is designed to improve the accessibility of power-quality in formation and to increase understanding of the growing importance of electricity reliability and power quality to the economy. The study used data collected by I-Grid sensors at seven Silicon Valley firms to investigate the impacts of power quality on individual study participants as well as to explore the capabilities of the I-Grid system to detect events on the larger electricity grid by means of correlation of data from the sensors at the different sites. In addition, study participants were interviewed about the value they place on power quality, and their efforts to address electricity-reliability and power-quality problems. Issues were identified that should be taken into consideration in developing a larger, potentially nationwide, network of power-quality sensors.« less

Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

PubMed

Choi, Wonchul; Park, Young-Sam; Hyun, Younghoon; Zyung, Taehyoung; Kim, Jaehyeon; Kim, Soojung; Jeon, Hyojin; Shin, Mincheol; Jang, Moongyu

2013-12-01

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured. The laminated thermoelectric device shows suppression of heat flow from the hot to cold side. This is supported by the theory that the atomic mass difference between silicide and silicon creates a scattering center for phonons. The major impact of our work is that phonon transmission is suppressed at the interface between silicide and silicon without degrading electrical conductivity. The estimated thermal conductivity of the 3-layer laminated device is 126.2 +/- 3.7 W/m. K. Thus, by using the 3-layer laminated structure, thermal conductivity is reduced by around 16% compared to bulk silicon. However, the Seebeck coefficient of the thermoelectric device is degraded compared to that of bulk silicon. It is understood that electrical conductivity is improved by using silicide as a scattering center.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Conformal chemically resistant coatings for microflow devices

DOEpatents

Folta, James A.; Zdeblick, Mark

2003-05-13

A process for coating the inside surfaces of silicon microflow devices, such as electrophoresis microchannels, with a low-stress, conformal (uniform) silicon nitride film which has the ability to uniformly coat deeply-recessed cavities with, for example, aspect ratios of up to 40:1 or higher. The silicon nitride coating allows extended exposure to caustic solutions. The coating enables a microflow device fabricated in silicon to be resistant to all classes of chemicals: acids, bases, and solvents. The process involves low-pressure (vacuum) chemical vapor deposition. The ultra-low-stress silicon nitride deposition process allows 1-2 .mu.m thick films without cracks, and so enables extended chemical protection of a silicon microflow device against caustics for up to 1 year. Tests have demonstrated the resistance of the films to caustic solutions at both ambient and elevated temperatures to 65.degree. C.

Silicon/HfO{sub 2} interface: Effects of gamma irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maurya, Savita

2016-05-23

Quality of MOS devices is a strong function of substrate and oxide interface. In this work we have studied how gamma photon irradiation affects the interface of a 13 nm thick, atomic layer deposited hafnium dioxide deposited on silicon wafer. CV and GV measurements have been done for pristine and irradiated samples to quantify the effect of gamma photon irradiation. Gamma photon irradiation not only introduces positive charge in the oxide and at the interface of Si/HfO{sub 2} interface but also induce phase change of oxide layer. Maximum oxide capacitances are affected by gamma photon irradiation.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Vacancy-type defects in TiO2/SiO2/SiC dielectric stacks

NASA Astrophysics Data System (ADS)

Coleman, P. G.; Burrows, C. P.; Mahapatra, R.; Wright, N. G.

2007-07-01

Open-volume (vacancy-type) point defects have been observed in ˜80-nm-thick titanium dioxide films grown on silicon dioxide/4H silicon carbide substrates as stacks with high dielectric constant for power device applications, using variable-energy positron annihilation spectroscopy. The concentration of vacancies decreases as the titanium dioxide growth temperature is increased in the range from 700to1000°C, whereas grain boundaries form in the polycrystalline material at the highest growth temperatures. It is proposed that the optimal electrical performance for films grown at 800°C reflects a balance between decreasing vacancy concentration and increasing grain boundary formation. The concentration of vacancies at the silicon dioxide/silicon carbide interface appears to saturate after 2.5h oxidation at 1150°C. A supplementary result suggests that the quality of the 10-μm-thick deposited silicon carbide epilayer is compromised at depths of about 2μm and beyond, possibly by the migration of impurities and/or other defects from the standard-grade highly doped 4H silicon carbide wafer beneath the epilayer during oxidation.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

2000-01-01

An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

DOEpatents

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Plasmonic engineering of spontaneous emission from silicon nanocrystals.

PubMed

Goffard, Julie; Gérard, Davy; Miska, Patrice; Baudrion, Anne-Laure; Deturche, Régis; Plain, Jérôme

2013-01-01

Silicon nanocrystals offer huge advantages compared to other semi-conductor quantum dots as they are made from an abundant, non-toxic material and are compatible with silicon devices. Besides, among a wealth of extraordinary properties ranging from catalysis to nanomedicine, metal nanoparticles are known to increase the radiative emission rate of semiconductor quantum dots. Here, we use gold nanoparticles to accelerate the emission of silicon nanocrystals. The resulting integrated hybrid emitter is 5-fold brighter than bare silicon nanocrystals. We also propose an in-depth analysis highlighting the role of the different physical parameters in the photoluminescence enhancement phenomenon. This result has important implications for the practical use of silicon nanocrystals in optoelectronic devices, for instance for the design of efficient down-shifting devices that could be integrated within future silicon solar cells.

Micro-opto-mechanical devices and systems using epitaxial lift off

NASA Technical Reports Server (NTRS)

Camperi-Ginestet, C.; Kim, Young W.; Wilkinson, S.; Allen, M.; Jokerst, N. M.

1993-01-01

The integration of high quality, single crystal thin film gallium arsenide (GaAs) and indium phosphide (InP) based photonic and electronic materials and devices with host microstructures fabricated from materials such as silicon (Si), glass, and polymers will enable the fabrication of the next generation of micro-opto-mechanical systems (MOMS) and optoelectronic integrated circuits. Thin film semiconductor devices deposited onto arbitrary host substrates and structures create hybrid (more than one material) near-monolithic integrated systems which can be interconnected electrically using standard inexpensive microfabrication techniques such as vacuum metallization and photolithography. These integrated systems take advantage of the optical and electronic properties of compound semiconductor devices while still using host substrate materials such as silicon, polysilicon, glass and polymers in the microstructures. This type of materials optimization for specific tasks creates higher performance systems than those systems which must use trade-offs in device performance to integrate all of the function in a single material system. The low weight of these thin film devices also makes them attractive for integration with micromechanical devices which may have difficulty supporting and translating the full weight of a standard device. These thin film devices and integrated systems will be attractive for applications, however, only when the development of low cost, high yield fabrication and integration techniques makes their use economically feasible. In this paper, we discuss methods for alignment, selective deposition, and interconnection of thin film epitaxial GaAs and InP based devices onto host substrates and host microstructures.

Process for forming a porous silicon member in a crystalline silicon member

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

Magneto-optical non-reciprocal devices in silicon photonics

PubMed Central

Shoji, Yuya; Mizumoto, Tetsuya

2014-01-01

Silicon waveguide optical non-reciprocal devices based on the magneto-optical effect are reviewed. The non-reciprocal phase shift caused by the first-order magneto-optical effect is effective in realizing optical non-reciprocal devices in silicon waveguide platforms. In a silicon-on-insulator waveguide, the low refractive index of the buried oxide layer enhances the magneto-optical phase shift, which reduces the device footprints. A surface activated direct bonding technique was developed to integrate a magneto-optical garnet crystal on the silicon waveguides. A silicon waveguide optical isolator based on the magneto-optical phase shift was demonstrated with an optical isolation of 30 dB and insertion loss of 13 dB at a wavelength of 1548 nm. Furthermore, a four port optical circulator was demonstrated with maximum isolations of 15.3 and 9.3 dB in cross and bar ports, respectively, at a wavelength of 1531 nm. PMID:27877640

Hybrid Integration of Solid-State Quantum Emitters on a Silicon Photonic Chip.

PubMed

Kim, Je-Hyung; Aghaeimeibodi, Shahriar; Richardson, Christopher J K; Leavitt, Richard P; Englund, Dirk; Waks, Edo

2017-12-13

Scalable quantum photonic systems require efficient single photon sources coupled to integrated photonic devices. Solid-state quantum emitters can generate single photons with high efficiency, while silicon photonic circuits can manipulate them in an integrated device structure. Combining these two material platforms could, therefore, significantly increase the complexity of integrated quantum photonic devices. Here, we demonstrate hybrid integration of solid-state quantum emitters to a silicon photonic device. We develop a pick-and-place technique that can position epitaxially grown InAs/InP quantum dots emitting at telecom wavelengths on a silicon photonic chip deterministically with nanoscale precision. We employ an adiabatic tapering approach to transfer the emission from the quantum dots to the waveguide with high efficiency. We also incorporate an on-chip silicon-photonic beamsplitter to perform a Hanbury-Brown and Twiss measurement. Our approach could enable integration of precharacterized III-V quantum photonic devices into large-scale photonic structures to enable complex devices composed of many emitters and photons.

Annealing pressure induced ions transfer in Cobalt-Ferrite thin films on amorphous SiO2/Si substrates

NASA Astrophysics Data System (ADS)

Huang, Shun-Yu; Chong, Cheong-Wei; Chen, Pin-Hui; Li, Hong-Lin; Li, Min-Kai; Huang, J. C. Andrew

2017-11-01

In this work, Cobalt-Ferrite (CFO) films were grown on silicon substrates with 300 nm amorphous silicon dioxide by Pulsed Laser Deposition (PLD) with different annealing conditions. The results of structural analysis prove that the CFO films have high crystalline quality with (1 1 1) preferred orientation. The Raman spectra and X-ray absorption spectra (XAS) indicate that the Co ions can transfer from tetrahedral sites to octahedral sites with increasing the annealing pressure. The site exchange of Co and Fe ions leads to the change of saturation magnetization in the CFO films. Our experiments provide not only a way to control the magnetism of CFO films, but also a suitable magnetic layer to develop silicon and semiconductor based spintronic devices.

Light Trapping in Thin Film Silicon Solar Cells on Plastic Substrates

NASA Astrophysics Data System (ADS)

de Jong, M. M.

2013-01-01

In the search for sustainable energy sources, solar energy can fulfil a large part of the growing demand. The biggest threshold for large-scale solar energy harvesting is the solar panel price. For drastic cost reductions, roll-to-roll fabrication of thin film silicon solar cells using plastic substrates can be a solution. In this thesis, we investigate the possibilities of depositing thin film solar cells directly onto cheap plastic substrates. Micro-textured glass and sheets, which have a wide range of applications, such as in green house, lighting etc, are applied in these solar cells for light trapping. Thin silicon films can be produced by decomposing silane gas, using a plasma process. In these types of processes, the temperature of the growing surface has a large influence on the quality of the grown films. Because plastic substrates limit the maximum tolerable substrate temperature, new methods have to be developed to produce device-grade silicon layers. At low temperature, polysilanes can form in the plasma, eventually forming dust particles, which can deteriorate device performance. By studying the spatially resolved optical emission from the plasma between the electrodes, we can identify whether we have a dusty plasma. Furthermore, we found an explanation for the temperature dependence of dust formation; Monitoring the formation of polysilanes as a function of temperature using a mass-spectrometer, we observed that the polymerization rate is indeed influenced by the substrate temperature. For solar cell substrate material, our choice was polycarbonate (PC), because of its low cost, its excellent transparency and its relatively high glass transition temperature of 130-140°C. At 130°C we searched for deposition recipes for device quality silicon, using a very high frequency plasma enhanced chemical deposition process. By diluting the feedstock silane with hydrogen gas, the silicon quality can be improved for amorphous silicon (a-Si), until we reach the nanocrystalline silicon (nc-Si) regime. In the nc-Si regime, the crystalline fraction can be further controlled by changing the power input into the plasma. With these layers, a-Si thin film solar cells were fabricated, on glass and PC substrates. The adverse effect of the low temperature growth on the photoactive material is further mitigated by using thinner silicon layers, which can deliver a good current only with an adequate light trapping technique. We have simulated and experimentally tested three light trapping techniques, using embossed structures in PC substrates and random structures on glass: regular pyramid structures larger than the wavelength of light (micropyramids), regular pyramid structures comparable to the wavelength of light (nanopyramids) and random nano-textures (Asahi U-type). The use of nanostructured polycarbonate substrates results in initial conversion efficiencies of 7.4%, compared to 7.6% for cells deposited under identical conditions on Asahi U-type glass. The potential of manufacturing thin film solar cells at processing temperatures lower than 130oC is further illustrated by obtained results on texture-etched aluminium doped zinc-oxide (ZnO:Al) on glass: we achieved 6.9% for nc-Si cells using a very thin absorber layer of only 750 nm, and by combining a-Si and nc-Si cells in tandem solar cells we reached an initial conversion efficiency of 9.5%.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Rapid Prototyping of Nanofluidic Slits in a Silicone Bilayer

PubMed Central

Kole, Thomas P.; Liao, Kuo-Tang; Schiffels, Daniel; Ilic, B. Robert; Strychalski, Elizabeth A.; Kralj, Jason G.; Liddle, J. Alexander; Dritschilo, Anatoly; Stavis, Samuel M.

2015-01-01

This article reports a process for rapidly prototyping nanofluidic devices, particularly those comprising slits with microscale widths and nanoscale depths, in silicone. This process consists of designing a nanofluidic device, fabricating a photomask, fabricating a device mold in epoxy photoresist, molding a device in silicone, cutting and punching a molded silicone device, bonding a silicone device to a glass substrate, and filling the device with aqueous solution. By using a bilayer of hard and soft silicone, we have formed and filled nanofluidic slits with depths of less than 400 nm and aspect ratios of width to depth exceeding 250 without collapse of the slits. An important attribute of this article is that the description of this rapid prototyping process is very comprehensive, presenting context and details which are highly relevant to the rational implementation and reliable repetition of the process. Moreover, this process makes use of equipment commonly found in nanofabrication facilities and research laboratories, facilitating the broad adaptation and application of the process. Therefore, while this article specifically informs users of the Center for Nanoscale Science and Technology (CNST) at the National Institute of Standards and Technology (NIST), we anticipate that this information will be generally useful for the nanofabrication and nanofluidics research communities at large, and particularly useful for neophyte nanofabricators and nanofluidicists. PMID:26958449

Device research task (processing and high-efficiency solar cells)

NASA Technical Reports Server (NTRS)

1986-01-01

This task has been expanded since the last 25th Project Integration Meeting (PIM) to include process research in addition to device research. The objective of this task is to assist the Flat-plate Solar Array (FSA) Project in meeting its near- and long-term goals by identifying and implementing research in the areas of device physics, device structures, measurement techniques, material-device interactions, and cell processing. The research efforts of this task are described and reflect the deversity of device research being conducted. All of the contracts being reported are either completed or near completion and culminate the device research efforts of the FSA Project. Optimazation methods and silicon solar cell numerical models, carrier transport and recombination parameters in heavily doped silicon, development and analysis of silicon solar cells of near 20% efficiency, and SiN sub x passivation of silicon surfaces are discussed.

Sputtered pin amorphous silicon semi-conductor device and method therefor

DOEpatents

Moustakas, Theodore D.; Friedman, Robert A.

1983-11-22

A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Sub-wavelength InAs quantum dot micro-disk lasers epitaxially grown on exact Si (001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Yating; Li, Qiang; Lau, Kei May, E-mail: eekmlau@ust.hk

Subwavelength micro-disk lasers (MDLs) as small as 1 μm in diameter on exact (001) silicon were fabricated using colloidal lithography. The micro-cavity gain medium incorporating five-stacked InAs quantum dot layers was grown on a high crystalline quality GaAs-on-V-grooved-Si template with no absorptive intermediate buffers. Under continuous-wave optical pumping, the MDLs on silicon exhibit lasing in the 1.2-μm wavelength range with low thresholds down to 35 μW at 10 K. The MDLs compare favorably with devices fabricated on native GaAs substrates and state-of-the-art work reported elsewhere. Feasibility of device miniaturization can be projected by size-dependent lasing characteristics. The results show a promising path towardsmore » dense integration of photonic components on the mainstream complementary metal–oxide–semiconductor platform.« less

N-Type delta Doping of High-Purity Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

2005-01-01

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including metallization. The success of the process depends on accurate temperature control, surface treatment, growth of high-quality crystalline silicon, and precise control of thicknesses of layers. MBE affords the necessary nanometer- scale control of the placement of atoms for delta doping. More specifically, the process consists of MBE deposition of a thin silicon buffer layer, the n-type delta doping layer, and a thin silicon cap layer. The n dopant selected for initial experiments was antimony, but other n dopants as (phosphorus or arsenic) could be used. All n-type dopants in silicon tend to surface-segregate during growth, leading to a broadened dopant-concentration- versus-depth profile. In order to keep the profile as narrow as possible, the substrate temperature is held below 300 C during deposition of the silicon cap layer onto the antimony delta layer. The deposition of silicon includes a silicon- surface-preparation step, involving H-termination, that enables the growth of high-quality crystalline silicon at the relatively low temperature with close to full electrical activation of donors in the surface layer.

Fabrication of Silica Ultra High Quality Factor Microresonators

PubMed Central

Maker, Ashley J.; Armani, Andrea M.

2012-01-01

Whispering gallery resonant cavities confine light in circular orbits at their periphery.1-2 The photon storage lifetime in the cavity, quantified by the quality factor (Q) of the cavity, can be in excess of 500ns for cavities with Q factors above 100 million. As a result of their low material losses, silica microcavities have demonstrated some of the longest photon lifetimes to date1-2. Since a portion of the circulating light extends outside the resonator, these devices can also be used to probe the surroundings. This interaction has enabled numerous experiments in biology, such as single molecule biodetection and antibody-antigen kinetics, as well as discoveries in other fields, such as development of ultra-low-threshold microlasers, characterization of thin films, and cavity quantum electrodynamics studies.3-7 The two primary silica resonant cavity geometries are the microsphere and the microtoroid. Both devices rely on a carbon dioxide laser reflow step to achieve their ultra-high-Q factors (Q>100 million).1-2,8-9 However, there are several notable differences between the two structures. Silica microspheres are free-standing, supported by a single optical fiber, whereas silica microtoroids can be fabricated on a silicon wafer in large arrays using a combination of lithography and etching steps. These differences influence which device is optimal for a given experiment. Here, we present detailed fabrication protocols for both types of resonant cavities. While the fabrication of microsphere resonant cavities is fairly straightforward, the fabrication of microtoroid resonant cavities requires additional specialized equipment and facilities (cleanroom). Therefore, this additional requirement may also influence which device is selected for a given experiment. Introduction An optical resonator efficiently confines light at specific wavelengths, known as the resonant wavelengths of the device. 1-2 The common figure of merit for these optical resonators is the quality factor or Q. This term describes the photon lifetime (τo) within the resonator, which is directly related to the resonator's optical losses. Therefore, an optical resonator with a high Q factor has low optical losses, long photon lifetimes, and very low photon decay rates (1/τo). As a result of the long photon lifetimes, it is possible to build-up extremely large circulating optical field intensities in these devices. This very unique property has allowed these devices to be used as laser sources and integrated biosensors.10 A unique sub-class of resonators is the whispering gallery mode optical microcavity. In these devices, the light is confined in circular orbits at the periphery. Therefore, the field is not completely confined within the device, but evanesces into the environment. Whispering gallery mode optical cavities have demonstrated some of the highest quality factors of any optical resonant cavity to date.9,11 Therefore, these devices are used throughout science and engineering, including in fundamental physics studies and in telecommunications as well as in biodetection experiments. 3-7,12 Optical microcavities can be fabricated from a wide range of materials and in a wide variety of geometries. A few examples include silica and silicon microtoroids, silicon, silicon nitride, and silica microdisks, micropillars, and silica and polymer microrings.13-17 The range in quality factor (Q) varies as dramatically as the geometry. Although both geometry and high Q are important considerations in any field, in many applications, there is far greater leverage in boosting device performance through Q enhancement. Among the numerous options detailed previously, the silica microsphere and the silica microtoroid resonator have achieved some of the highest Q factors to date.1,9 Additionally, as a result of the extremely low optical loss of silica from the visible through the near-IR, both microspheres and microtoroids are able to maintain their Q factors over a wide range of testing wavelengths.18 Finally, because silica is inherently biocompatible, it is routinely used in biodetection experiments. In addition to high material absorption, there are several other potential loss mechanisms, including surface roughness, radiation loss, and contamination loss.2 Through an optimization of the device size, it is possible to eliminate radiation losses, which arise from poor optical field confinement within the device. Similarly, by storing a device in an appropriately clean environment, contamination of the surface can be minimized. Therefore, in addition to material loss, surface scattering is the primary loss mechanism of concern.2,8 In silica devices, surface scattering is minimized by using a laser reflow technique, which melts the silica through surface tension induced reflow. While spherical optical resonators have been studied for many years, it is only with recent advances in fabrication technologies that researchers been able to fabricate high quality silica optical toroidal microresonators (Q>100 million) on a silicon substrate, thus paving the way for integration with microfluidics.1 The present series of protocols details how to fabricate both silica microsphere and microtoroid resonant cavities. While silica microsphere resonant cavities are well-established, microtoroid resonant cavities were only recently invented.1 As many of the fundamental methods used to fabricate the microsphere are also used in the more complex microtoroid fabrication procedure, by including both in a single protocol it will enable researchers to more easily trouble-shoot their experiments. PMID:22805153

Reproducible Growth of High-Quality Cubic-SiC Layers

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Powell, J. Anthony

2004-01-01

Semiconductor electronic devices and circuits based on silicon carbide (SiC) are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which devices made from conventional semiconductors cannot adequately perform. The ability of SiC-based devices to function under such extreme conditions is expected to enable significant improvements in a variety of applications and systems. These include greatly improved high-voltage switching for saving energy in public electric power distribution and electric motor drives; more powerful microwave electronic circuits for radar and communications; and sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines.

Whatever happened to silicon carbide. [semiconductor devices

NASA Technical Reports Server (NTRS)

Campbell, R. B.

1981-01-01

The progress made in silicon carbide semiconductor devices in the 1955 to 1975 time frame is examined and reasons are given for the present lack of interest in the material. Its physical and chemical properties and methods of preparation are discussed. Fabrication techniques and the characteristics of silicon carbide devices are reviewed. It is concluded that a combination of economic factors and the lack of progress in fabrication techniques leaves no viable market for SiC devices in the near future.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

The role of the substrate in Graphene/Silicon photodiodes

NASA Astrophysics Data System (ADS)

Luongo, G.; Giubileo, F.; Iemmo, L.; Di Bartolomeo, A.

2018-01-01

The Graphene/Silicon (Gr/Si) junction can function as a Schottky diode with performances strictly related to the quality of the interface. Here, we focus on the substrate geometry and on its effects on Gr/Si junction physics. We fabricate and study the electrical and optical behaviour of two types of devices: one made of a Gr/Si planar junction, the second realized with graphene on an array of Si nanotips. We show that the Gr/Si flat device exhibits a reverse photocurrent higher than the forward current and achieves a photoresponsivity of 2.5 A/W. The high photoresponse is due to the charges photogenerated in Si below a parasitic graphene/SiO2/Si structure, which are injected into the Gr/Si junction region. The other device with graphene on Si-tips displays a reverse current that grows exponentially with the bias. We explain this behaviour by taking into account the tip geometry of the substrate, which magnifies the electric field and shifts the Fermi level of graphene, thus enabling fine-tuning of the Schottky barrier height. The Gr/Si-tip device achieves a higher photoresponsivity, up to 3 A/W, likely due to photocharge internal multiplication.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology.

PubMed

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-12-03

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm(2), and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p(+-)n homojunction through the formation of re-grown crystalline silicon layer (~5-10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method.

Analysis and optimization of acoustic wave micro-resonators integrating piezoelectric zinc oxide layers

NASA Astrophysics Data System (ADS)

Mortada, O.; Zahr, A. H.; Orlianges, J.-C.; Crunteanu, A.; Chatras, M.; Blondy, P.

2017-02-01

This paper reports on the design, simulation, fabrication, and test results of ZnO-based contour-mode micro-resonators integrating piezoelectric zinc oxide (ZnO) layers. The inter-digitated (IDT) type micro-resonators are fabricated on ZnO films and suspended top of 2 μm thick silicon membranes using silicon-on insulator technology. We analyze several possibilities of increasing the quality factor (Q) and the electromechanical coupling coefficient (kt2) of the devices by varying the numbers and lengths of the IDT electrodes and using different thicknesses of the ZnO layer. We designed and fabricated IDTs of different finger numbers (n = 25, 40, 50, and 80) and lengths (L = 100/130/170/200 μm) for three different thicknesses of ZnO films (200, 600, and 800 nm). The measured Q factor confirms that reducing the length and the number of IDT fingers enables us to reach better electrical performances at resonant frequencies around 700 MHz. The extracted results for an optimized micro-resonator device having an IDT length of 100 μm and 40 finger electrodes show a Q of 1180 and a kt2 of 7.4%. We demonstrate also that the reduction of the ZnO thickness from 800 nm to 200 nm increases the quality factor from 430 to 1600, respectively, around 700 MHz. Experimental data are in very good agreement with theoretical simulations of the fabricated devices

Silicon superlattices: Theory and application to semiconductor devices

NASA Technical Reports Server (NTRS)

Moriarty, J. A.

1981-01-01

Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

Deuterated silicon nitride photonic devices for broadband optical frequency comb generation

NASA Astrophysics Data System (ADS)

Chiles, Jeff; Nader, Nima; Hickstein, Daniel D.; Yu, Su Peng; Briles, Travis Crain; Carlson, David; Jung, Hojoong; Shainline, Jeffrey M.; Diddams, Scott; Papp, Scott B.; Nam, Sae Woo; Mirin, Richard P.

2018-04-01

We report and characterize low-temperature, plasma-deposited deuterated silicon nitride thin films for nonlinear integrated photonics. With a peak processing temperature less than 300$^\\circ$C, it is back-end compatible with pre-processed CMOS substrates. We achieve microresonators with a quality factor of up to $1.6\\times 10^6 $ at 1552 nm, and $>1.2\\times 10^6$ throughout $\\lambda$ = 1510 -- 1600 nm, without annealing or stress management. We then demonstrate the immediate utility of this platform in nonlinear photonics by generating a 1 THz free spectral range, 900-nm-bandwidth modulation-instability microresonator Kerr comb and octave-spanning, supercontinuum-broadened spectra.

Thermal and bias cycling stabilizes planar silicon devices

NASA Technical Reports Server (NTRS)

Harris, R. E.; Meinhard, J. E.

1967-01-01

Terminal burn-in or baking step time in the processing of planar silicon devices is extended to reduce their inversion tendencies. The collector-base junction of the device is also cyclically biased during the burn-in.

Polymer taper bridge for silicon waveguide to single mode waveguide coupling

NASA Astrophysics Data System (ADS)

Kruse, Kevin; Middlebrook, Christopher T.

2016-03-01

Coupling of optical power from high-density silicon waveguides to silica optical fibers for signal routing can incur high losses and often requires complex end-face preparation/processing. Novel coupling device taper structures are proposed for low coupling loss between silicon photonic waveguides and single mode fibers are proposed and devices are fabricated and measured in terms of performance. Theoretical mode conversion models for waveguide tapers are derived for optimal device structure design and performance. Commercially viable vertical and multi-layer taper designs using polymer waveguide materials are proposed as innovative, cost-efficient, and mass-manufacturable optical coupling devices. The coupling efficiency for both designs is determined to evaluate optimal device dimensions and alignment tolerances with both silicon rib waveguides and silicon nanowire waveguides. Propagation loss as a function of waveguide roughness and metallic loss are determined and correlated to waveguide dimensions to obtain total insertion loss for the proposed taper designs. Multi-layer tapers on gold-sputtered substrates are fabricated through photolithography as proof-of-concept devices and evaluated for device loss optimization. Tapered waveguide coupling loss with Si WGs (2.74 dB) was experimentally measured with high correlation to theoretical results.

Wavelength dependent vertical integration of nanoplasmonic circuits utilizing coupled ring resonators

NASA Astrophysics Data System (ADS)

Nielsen, M.; Elezzabi, A. Y.

2013-03-01

To become a competitor to replace CMOS-electronics for next-generation data processing, signal routing, and computing, nanoplasmonic circuits will require an analogue to electrical vias in order to enable vertical connections between device layers. Vertically stacked nanoplasmonic nanoring resonators formed of Ag/Si/Ag gap plasmon waveguides were studied as a novel 3-D coupling scheme that could be monolithically integrated on a silicon platform. The vertically coupled ring resonators were evanescently coupled to 100 nm x 100 nm Ag/Si/Ag input and output waveguides and the whole device was submerged in silicon dioxide. 3-D finite difference time domain simulations were used to examine the transmission spectra of the coupling device with varying device sizes and orientations. By having the signal coupling occur over multiple trips around the resonator, coupling efficiencies as high as 39% at telecommunication wavelengths between adjacent layers were present with planar device areas of only 1.00 μm2. As the vertical signal transfer was based on coupled ring resonators, the signal transfer was inherently wavelength dependent. Changing the device size by varying the radii of the nanorings allowed for tailoring the coupled frequency spectra. The plasmonic resonator based coupling scheme was found to have quality (Q) factors of upwards of 30 at telecommunication wavelengths. By allowing different device layers to operate on different wavelengths, this coupling scheme could to lead to parallel processing in stacked independent device layers.

Photonic crystal ring resonator-based four-channel dense wavelength division multiplexing demultiplexer on silicon on insulator platform: design and analysis

NASA Astrophysics Data System (ADS)

Sreenivasulu, Tupakula; Bhowmick, Kaustav; Samad, Shafeek A.; Yadunath, Thamerassery Illam R.; Badrinarayana, Tarimala; Hegde, Gopalkrishna; Srinivas, Talabattula

2018-04-01

A micro/nanofabrication feasible compact photonic crystal (PC) ring-resonator-based channel drop filter has been designed and analyzed for operation in C and L bands of communication window. The four-channel demultiplexer consists of ring resonators of holes in two-dimensional PC slab. The proposed assembly design of dense wavelength division multiplexing setup is shown to achieve optimal quality factor, without altering the lattice parameters or resonator size or inclusion of scattering holes. Transmission characteristics are analyzed using the three-dimensional finite-difference time-domain simulation approach. The radiation loss of the ring resonator was minimized by forced cancelation of radiation fields by fine-tuning the air holes inside the ring resonator. An average cross talk of -34 dB has been achieved between the adjacent channels maintaining an average quality factor of 5000. Demultiplexing is achieved by engineering only the air holes inside the ring, which makes it a simple and tolerant design from the fabrication perspective. Also, the device footprint of 500 μm2 on silicon on insulator platform makes it easy to fabricate the device using e-beam lithography technique.

GaN and ZnO nanostructures

NASA Astrophysics Data System (ADS)

Fündling, Sönke; Sökmen, Ünsal; Behrends, Arne; Al-Suleiman, Mohamed Aid Mansur; Merzsch, Stephan; Li, Shunfeng; Bakin, Andrey; Wehmann, Hergo-Heinrich; Waag, Andreas; Lähnemann, Jonas; Jahn, Uwe; Trampert, Achim; Riechert, Henning

2010-07-01

GaN and ZnO are both wide band gap semiconductors with interesting properties concerning optoelectronic and sensor device applications. Due to the lack or the high costs of native substrates, alternatives like sapphire, silicon, or silicon carbide are taken, but the resulting lattice and thermal mismatches lead to increased defect densities which reduce the material quality. In contrast, nanostructures with high aspect ratio have lower defect densities as compared to layers. In this work, we give an overview on our results achieved on both ZnO as well as GaN based nanorods. ZnO nanostructures were grown by a wet chemical approach as well as by VPT on different substrates - even on flexible polymers. To compare the growth results we analyzed the structures by XRD and PL and show possible device applications. The GaN nano- and microstructures were grown by metal organic vapor phase epitaxy either in a self- organized process or by selective area growth for a better control of shape and material composition. Finally we take a look onto possible device applications, presenting our attempts, e.g., to build LEDs based on GaN nanostructures.

Polycrystalline silicon study: Low-cost silicon refining technology prospects and semiconductor-grade polycrystalline silicon availability through 1988

NASA Technical Reports Server (NTRS)

Costogue, E. N.; Ferber, R.; Lutwack, R.; Lorenz, J. H.; Pellin, R.

1984-01-01

Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.

Amorphous silicon photovoltaic devices

DOEpatents

Carlson, David E.; Lin, Guang H.; Ganguly, Gautam

2004-08-31

This invention is a photovoltaic device comprising an intrinsic or i-layer of amorphous silicon and where the photovoltaic device is more efficient at converting light energy to electric energy at high operating temperatures than at low operating temperatures. The photovoltaic devices of this invention are suitable for use in high temperature operating environments.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Silicon Carbide Solar Cells Investigated

NASA Technical Reports Server (NTRS)

Bailey, Sheila G.; Raffaelle, Ryne P.

2001-01-01

The semiconductor silicon carbide (SiC) has long been known for its outstanding resistance to harsh environments (e.g., thermal stability, radiation resistance, and dielectric strength). However, the ability to produce device-quality material is severely limited by the inherent crystalline defects associated with this material and their associated electronic effects. Much progress has been made recently in the understanding and control of these defects and in the improved processing of this material. Because of this work, it may be possible to produce SiC-based solar cells for environments with high temperatures, light intensities, and radiation, such as those experienced by solar probes. Electronics and sensors based on SiC can operate in hostile environments where conventional silicon-based electronics (limited to 350 C) cannot function. Development of this material will enable large performance enhancements and size reductions for a wide variety of systems--such as high-frequency devices, high-power devices, microwave switching devices, and high-temperature electronics. These applications would supply more energy-efficient public electric power distribution and electric vehicles, more powerful microwave electronics for radar and communications, and better sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. The 6H-SiC polytype is a promising wide-bandgap (Eg = 3.0 eV) semiconductor for photovoltaic applications in harsh solar environments that involve high-temperature and high-radiation conditions. The advantages of this material for this application lie in its extremely large breakdown field strength, high thermal conductivity, good electron saturation drift velocity, and stable electrical performance at temperatures as high as 600 C. This behavior makes it an attractive photovoltaic solar cell material for devices that can operate within three solar radii of the Sun.

Semiconductor to Metal Transition Characteristics of VO2/NiO Epitaxial Heterostructures Integrated with Si(100)

NASA Astrophysics Data System (ADS)

Molaei, Roya

The novel functionalities of Vanadium dioxide (VO2), such as, several orders of magnitude transition in resistivity and IR transmittance, provide the exciting opportunity for the development of next generation memory, sensor, and field-effect based devices. A critical issue in the development of practical devices based on metal oxides is the integration of high quality epitaxial oxide thin films with the existing silicon technology which is based on silicon (100) substrates. However, silicon is not suitable for epitaxial growth of oxides owing to its tendency to readily form an amorphous oxide layer or silicide at the film-substrate interface. The oxide films deposited directly on silicon exhibit poor crystallinity and are not suitable for device applications. To overcome this challenge, appropriate substrate templates must be developed for the growth of oxide thin films on silicon substrates. The primary objective of this dissertation was to develop an integration methodology of VO2 with Si (100) substrates so they could be used in "smart" sensor type of devices along with other multifunctional devices on the same silicon chip. This was achieved by using a NiO/c- YSZ template layer deposited in situ. It will be shown that if the deposition conditions are controlled properly. This approach was used to integrate VO 2 thin films with Si (100) substrates using pulsed laser deposition (PLD) technique. The deposition methodology of integrating VO2 thin films on silicon using various other template layers will also be discussed. Detailed epitaxial relationship of NiO/c-YSZ/Si(100) heterostructures as a template to growth of VO2 as well as were studied. We also were able to create a p-n junction within a single NiO epilayer through subsequent nanosecond laser annealing, as well as established a structure-property correlation in NiO/c-YSZ/Si(100) thin film epitaxial heterostructures with especial emphasis on the stoichiometry and crystallographic characteristics. NiO/c-YSZ/Si(100) heterostructures were used as template to grow fully relaxed VO2 thin films. The detailed x-ray diffraction, transmission electron microscopy (TEM), electrical characterization results for the deposited films will be presented. In the framework on domain matching epitaxy, epitaxial growth of VO2 (tetragonal crystal structure at growth temperature) on NiO has been explained. Our detailed phi-scan X-ray diffraction measurements corroborate our understanding of the epitaxial growth and in-plane atomic arrangements at the interface. It was observed that the transition characteristics (sharpness, over which electrical property changes are completed, amplitude, transition temperature, and hysteresis) are a strong function of microstructure, strain, and stoichiometry. We have shown that by the choosing the right template layer, strain in the VO2 thin films can be fully relaxed and near-bulk VO2 transition temperatures can be achieved. Finally, I will present my research work on modification of semiconductor-to-metal transition characteristics and effect on room temperature magnetic properties of VO2 thin films upon laser annealing. While the microstructure (epitaxy, crystalline quality etc.) and phase were preserved, we envisage these changes to occur as a result of introduction of oxygen vacancies upon laser treatment.

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

Fabrication of semiconductor-polymer compound nonlinear photonic crystal slab with highly uniform infiltration based on nano-imprint lithography technique.

PubMed

Qin, Fei; Meng, Zi-Ming; Zhong, Xiao-Lan; Liu, Ye; Li, Zhi-Yuan

2012-06-04

We present a versatile technique based on nano-imprint lithography to fabricate high-quality semiconductor-polymer compound nonlinear photonic crystal (NPC) slabs. The approach allows one to infiltrate uniformly polystyrene materials that possess large Kerr nonlinearity and ultrafast nonlinear response into the cylindrical air holes with diameter of hundred nanometers that are perforated in silicon membranes. Both the structural characterization via the cross-sectional scanning electron microscopy images and the optical characterization via the transmission spectrum measurement undoubtedly show that the fabricated compound NPC samples have uniform and dense polymer infiltration and are of high quality in optical properties. The compound NPC samples exhibit sharp transmission band edges and nondegraded high quality factor of microcavities compared with those in the bare silicon PC. The versatile method can be expanded to make general semiconductor-polymer hybrid optical nanostructures, and thus it may pave the way for reliable and efficient fabrication of ultrafast and ultralow power all-optical tunable integrated photonic devices and circuits.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Epitaxial growth of silicon for layer transfer

DOEpatents

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Silicon-Germanium Films Grown on Sapphire for Ka-Band Communications Applications

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.

2004-01-01

NASA's vision in the space communications area is to develop a broadband data network in which there is a high degree of interconnectivity among the various satellite systems, ground stations, and wired systems. To accomplish this goal, we will need complex electronic circuits integrating analog and digital data handling at the Ka-band (26 to 40 GHz). The purpose of this project is to show the feasibility of a new technology for Ka-band communications applications, namely silicon germanium (SiGe) on sapphire. This new technology will have several advantages in comparison to the existing silicon-substrate- based circuits. The main advantages are extremely low parasitic reactances that enable much higher quality active and passive components, better device isolation, higher radiation tolerance, and the integration of digital and analog circuitry on a single chip.

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization.

PubMed

Tran, Duy Phu; Pham, Thuy Thi Thanh; Wolfrum, Bernhard; Offenhäusser, Andreas; Thierry, Benjamin

2018-05-11

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs' promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M.A.; Yu, C.M.; Raley, N.F.

1999-03-16

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gases in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters. 9 figs.

Porous silicon structures with high surface area/specific pore size

DOEpatents

Northrup, M. Allen; Yu, Conrad M.; Raley, Norman F.

1999-01-01

Fabrication and use of porous silicon structures to increase surface area of heated reaction chambers, electrophoresis devices, and thermopneumatic sensor-actuators, chemical preconcentrates, and filtering or control flow devices. In particular, such high surface area or specific pore size porous silicon structures will be useful in significantly augmenting the adsorption, vaporization, desorption, condensation and flow of liquids and gasses in applications that use such processes on a miniature scale. Examples that will benefit from a high surface area, porous silicon structure include sample preconcentrators that are designed to adsorb and subsequently desorb specific chemical species from a sample background; chemical reaction chambers with enhanced surface reaction rates; and sensor-actuator chamber devices with increased pressure for thermopneumatic actuation of integrated membranes. Examples that benefit from specific pore sized porous silicon are chemical/biological filters and thermally-activated flow devices with active or adjacent surfaces such as electrodes or heaters.

GaN-on-Silicon - Present capabilities and future directions

NASA Astrophysics Data System (ADS)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Atomic-scale characterization of hydrogenated amorphous-silicon films and devices. Annual subcontract report, 14 February 1994--14 April 1995

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gallagher, A.; Tanenbaum, D.; Laracuente, A.

1995-08-01

Properties of the hydrogenated amorphous silicon (a-Si:H) films used in photovoltaic (PV) panels are reported. The atomic-scale topology of the surface of intrinsic a-Si:H films, measured by scanning tunneling microscopy (STM) as a function of film thickness, are reported and diagnosed. For 1-500-nm-thick films deposited under normal device-quality conditions from silane discharges, most portions of these surfaces are uniformly hilly without indications of void regions. However, the STM images indicate that 2-6-nm silicon particulates are continuously deposited into the growing film from the discharge and fill approximately 0.01% of the film volume. Although the STM data are not sensitive tomore » the local electronic properties near these particulates, it is very likely that the void regions grow around them and have a deleterious effect on a-Si:H photovoltaics. Preliminary observations of particulates in the discharge, based on light scattering, confirm that particulates are present in the discharge and that many collect and agglomerate immediately downstream of the electrodes. Progress toward STM measurements of the electronic properties of cross-sectioned a-Si:H PV cells is also reported.« less

Improved PECVD Si x N y film as a mask layer for deep wet etching of the silicon

NASA Astrophysics Data System (ADS)

Han, Jianqiang; Yin, Yi Jun; Han, Dong; Dong, LiZhen

2017-09-01

Although plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si x N y ) films have been extensively investigated by many researchers, requirements of film properties vary from device to device. For some applications utilizing Si x N y film as the mask Layer for deep wet etching of the silicon, it is very desirable to obtain a high quality film. In this study, Si x N y films were deposited on silicon substrates by PECVD technique from the mixtures of NH3 and 5% SiH4 diluted in Ar. The deposition temperature and RF power were fixed at 400 °C and 20 W, respectively. By adjusting the SiH4/NH3 flow ratio, Si x N y films of different compositions were deposited on silicon wafers. The stoichiometry, residual stress, etch rate in 1:50 HF, BHF solution and 40% KOH solution of deposited Si x N y films were measured. The experimental results show that the optimum SiH4/NH3 flow ratio at which deposited Si x N y films can perfectly protect the polysilicon resistors on the front side of wafers during KOH etching is between 1.63 and 2.24 under the given temperature and RF power. Polysilicon resistors protected by the Si x N y films can withstand 6 h 40% KOH double-side etching at 80 °C. At the range of SiH4/NH3 flow ratios, the Si/N atom ratio of films ranges from 0.645 to 0.702, which slightly deviate the ideal stoichiometric ratio of LPCVD Si3N4 film. In addition, the silicon nitride films with the best protection effect are not the films of minimum etch rate in KOH solution.

MicroElectroMechanical devices and fabrication technologies for radio-frequency analog signal processing

NASA Astrophysics Data System (ADS)

Young, Darrin Jun

The proliferation of wireless services creates a pressing need for compact and low cost RF transceivers. Modern sub-micron technologies provide the active components needed for miniaturization but fail to deliver high quality passives needed in oscillators and filters. This dissertation demonstrates procedures for adding high quality inductors and tunable capacitors to a standard silicon integrated circuits. Several voltage-controlled oscillators operating in the low Giga-Hertz range demonstrate the suitability of these components for high performance RF building blocks. Two low-temperature processes are described to add inductors and capacitors to silicon ICs. A 3-D coil geometry is used for the inductors rather than the conventional planar spiral to substantially reduce substrate loss and hence improve the quality factor and self-resonant frequency. Measured Q-factors at 1 GHz are 30 for a 4.8 nH device, 16 for 8.2 nH and 13.8 nH inductors. Several enhancements are proposed that are expected to result in a further improvement of the achievable Q-factor. This research investigates the design and fabrication of silicon-based IC-compatible high-Q tunable capacitors and inductors. The goal of this investigation is to develop a monolithic low phase noise radio-frequency voltage-controlled oscillator using these high-performance passive components for wireless communication applications. Monolithic VCOs will help the miniaturization of current radio transceivers, which offers a potential solution to achieve a single hand-held wireless phone with multistandard capabilities. IC-compatible micromachining fabrication technologies have been developed to realize on-chip high-Q RF tunable capacitors and 3-D coil inductors. The capacitors achieve a nominal capacitance value of 2 pF and can be tuned over 15% with 3 V. A quality factor over 60 has been measured at 1 GHz. 3-D coil inductors obtain values of 4.8 nH, 8.2 nH and 13.8 nH. At 1 GHz a Q factor of 30 has been achieved for a 4.8 nH device and a Q of 16 for 8.2 nH and 13.8 nH inductors. A prototype RF voltage-controlled oscillator has been implemented employing the micromachined tunable capacitors and a 8.2 nH 3-D coil inductor. The active electronics, tunable capacitors and inductor are fabricated on separated silicon substrates and wire bonded to form the VCO. This hybrid approach is used to avoid the complexity of building the prototype oscillator. Both passive components are fabricated on silicon substrates and thus amenable to monolithic integration with standard IC process. The VCO achieves a -136 dBc/Hz phase noise at a 3 MHz offset frequency from the carrier, suitable for most wireless communication applications and is tunable from 855 MHz to 863 MHz with 3 V.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Memory device using movement of protons

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

1998-11-03

An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

1998-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

2000-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Effect of ultraviolet illumination and ambient gases on the photoluminescence and electrical properties of nanoporous silicon layer for organic vapor sensor.

PubMed

Atiwongsangthong, Narin

2012-08-01

The purpose of this research, the nanoporous silicon layer were fabricated and investigated the physical properties such as photoluminescence and the electrical properties in order to develop organic vapor sensor by using nanoporous silicon. The Changes in the photoluminescence intensity of nanoporous silicon samples are studied during ultraviolet illumination in various ambient gases such as nitrogen, oxigen and vacuum. In this paper, the nanoporous silicon layer was used as organic vapor adsorption and sensing element. The advantage of this device are simple process compatible in silicon technology and usable in room temperature. The structure of this device consists of nanoporous silicon layer which is formed by anodization of silicon wafer in hydrofluoric acid solution and aluminum electrode which deposited on the top of nanoporous silicon layer by evaporator. The nanoporous silicon sensors were placed in a gas chamber with various organic vapor such as ethanol, methanol and isopropyl alcohol. From studying on electrical characteristics of this device, it is found that the nanoporous silicon layer can detect the different organic vapor. Therefore, the nanoporous silicon is important material for organic vapor sensor and it can develop to other applications about gas sensors in the future.

Neutron radiation tolerance of Au-activated silicon

NASA Technical Reports Server (NTRS)

Joyner, W. T.

1987-01-01

Double injection devices prepared by the introduction of deep traps, using the Au activation method have been found to tolerate gamma irradiation into the Gigarad (Si) region without significant degradation of operating characteristics. Silicon double injection devices, using deep levels creacted by Au diffusion, can tolerate fast neutron irradiation up to 10 to the 15th n/sq cm. Significant parameter degradation occurs at 10 to the 16th n/sq cm. However, since the actual doping of the basic material begins to change as a result of the transmutation of silicon into phosphorus for neutron fluences greater than 10 to the 17th/sq cm, the radiation tolerance of these devices is approaching the limit possible for any device based on initially doped silicon.

Aluminium alloyed iron-silicide/silicon solar cells: A simple approach for low cost environmental-friendly photovoltaic technology

PubMed Central

Kumar Dalapati, Goutam; Masudy-Panah, Saeid; Kumar, Avishek; Cheh Tan, Cheng; Ru Tan, Hui; Chi, Dongzhi

2015-01-01

This work demonstrates the fabrication of silicide/silicon based solar cell towards the development of low cost and environmental friendly photovoltaic technology. A heterostructure solar cells using metallic alpha phase (α-phase) aluminum alloyed iron silicide (FeSi(Al)) on n-type silicon is fabricated with an efficiency of 0.8%. The fabricated device has an open circuit voltage and fill-factor of 240 mV and 60%, respectively. Performance of the device was improved by about 7 fold to 5.1% through the interface engineering. The α-phase FeSi(Al)/silicon solar cell devices have promising photovoltaic characteristic with an open circuit voltage, short-circuit current and a fill factor (FF) of 425 mV, 18.5 mA/cm2, and 64%, respectively. The significant improvement of α-phase FeSi(Al)/n-Si solar cells is due to the formation p+−n homojunction through the formation of re-grown crystalline silicon layer (~5–10 nm) at the silicide/silicon interface. Thickness of the regrown silicon layer is crucial for the silicide/silicon based photovoltaic devices. Performance of the α-FeSi(Al)/n-Si solar cells significantly depends on the thickness of α-FeSi(Al) layer and process temperature during the device fabrication. This study will open up new opportunities for the Si based photovoltaic technology using a simple, sustainable, and los cost method. PMID:26632759

Evolution and update on current devices for prosthetic breast reconstruction

PubMed Central

2015-01-01

Over the past decade, the leading breast reconstruction modality has shifted from autologous tissue to implants. This trend reversal is multi-factorial but includes increasing bilateral mastectomies and the more widespread acceptance of implants due to stringent quality and safety regulatory surveillance by the US Food and Drug Administration (FDA). Since 2012, the US FDA has approved several new implant styles, shapes and textures, increasing the choices for patients and surgeons. Predictable, superior aesthetic results after prosthetic breast reconstruction are attainable, but require thoughtful planning, precise surgical technique and appropriate device selection based on several different patient and surgeon parameters, such as patient desires, body mass index, breast shape, mastectomy flap quality and tissue based bio-dimensional assessment. This article briefly reviews historic devices used in prosthetic breast reconstruction beginning in the 1960s through the modern generation devices used today. We reflect on the rigorous hurdles endured over the last several decades leading to the approval of silicone gel devices, along with their well-established safety and efficacy. The various implant characteristics can affect feel and performance of the device. The many different styles and features of implants and expanders are described emphasizing surgical indications, advantages and disadvantages of each device. PMID:26005642

Organic printed photonics: From microring lasers to integrated circuits

PubMed Central

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-01-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

Organic printed photonics: From microring lasers to integrated circuits.

PubMed

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-09-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

A phononic crystal strip based on silicon for support tether applications in silicon-based MEMS resonators and effects of temperature and dopant on its band gap characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ha, Thi Dep, E-mail: hathidep@yahoo.com; Faculty of Electronic Technology, Industrial University of Ho Chi Minh City, Hochiminh City; Bao, JingFu, E-mail: baojingfu@uestc.edu.cn

Phononic crystals (PnCs) and n-type doped silicon technique have been widely employed in silicon-based MEMS resonators to obtain high quality factor (Q) as well as temperature-induced frequency stability. For the PnCs, their band gaps play an important role in the acoustic wave propagation. Also, the temperature and dopant doped into silicon can cause the change in its material properties such as elastic constants, Young’s modulus. Therefore, in order to design the simultaneous high Q and frequency stability silicon-based MEMS resonators by two these techniques, a careful design should study effects of temperature and dopant on the band gap characteristics tomore » examine the acoustic wave propagation in the PnC. Based on these, this paper presents (1) a proposed silicon-based PnC strip structure for support tether applications in low frequency silicon-based MEMS resonators, (2) influences of temperature and dopant on band gap characteristics of the PnC strips. The simulation results show that the largest band gap can achieve up to 33.56 at 57.59 MHz and increase 1280.13 % (also increase 131.89 % for ratio of the widest gaps) compared with the counterpart without hole. The band gap properties of the PnC strips is insignificantly effected by temperature and electron doping concentration. Also, the quality factor of two designed length extensional mode MEMS resonators with proposed PnC strip based support tethers is up to 1084.59% and 43846.36% over the same resonators with PnC strip without hole and circled corners, respectively. This theoretical study uses the finite element analysis in COMSOL Multiphysics and MATLAB softwares as simulation tools. This findings provides a background in combination of PnC and dopant techniques for high performance silicon-based MEMS resonators as well as PnC-based MEMS devices.« less

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Silicon Carbide Power Devices and Integrated Circuits

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie; Casey, Megan; Samsel, Isaak; LaBel, Ken; Chen, Yuan; Ikpe, Stanley; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

2017-01-01

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

Silicon nanowire device and method for its manufacture

DOEpatents

Okandan, Murat; Draper, Bruce L.; Resnick, Paul J.

2017-01-03

There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 .mu.m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.

Simple and inexpensive micromachined aluminum microfluidic devices for acoustic focusing of particles and cells.

PubMed

Gautam, Gayatri P; Burger, Tobias; Wilcox, Andrew; Cumbo, Michael J; Graves, Steven W; Piyasena, Menake E

2018-05-01

We introduce a new method to construct microfluidic devices especially useful for bulk acoustic wave (BAW)-based manipulation of cells and microparticles. To obtain efficient acoustic focusing, BAW devices require materials that have high acoustic impedance mismatch relative to the medium in which the cells/microparticles are suspended and materials with a high-quality factor. To date, silicon and glass have been the materials of choice for BAW-based acoustofluidic channel fabrication. Silicon- and glass-based fabrication is typically performed in clean room facilities, generates hazardous waste, and can take several hours to complete the microfabrication. To address some of the drawbacks in fabricating conventional BAW devices, we explored a new approach by micromachining microfluidic channels in aluminum substrates. Additionally, we demonstrate plasma bonding of poly(dimethylsiloxane) (PDMS) onto micromachined aluminum substrates. Our goal was to achieve an approach that is both low cost and effective in BAW applications. To this end, we micromachined aluminum 6061 plates and enclosed the systems with a thin PDMS cover layer. These aluminum/PDMS hybrid microfluidic devices use inexpensive materials and are simply constructed outside a clean room environment. Moreover, these devices demonstrate effectiveness in BAW applications as demonstrated by efficient acoustic focusing of polystyrene microspheres, bovine red blood cells, and Jurkat cells and the generation of multiple focused streams in flow-through systems. Graphical abstract The aluminum acoustofluidic device and the generation of multinode focusing of particles.

Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Browning, Robert

In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the same qualities as those of the mechanically exfoliated films. Back-gated field effect transistors were created and electrical characterization was performed to determine if ALD grown films possess the same electronic properties as films produced from other methods. The tests revealed that the ALD grown films have high field effect mobility and high current on/off ratios. The WSe2 films also exhibited ambipolar electrical behavior making them a possible candidate for complementary metal-oxide semiconductor (CMOS) technology. Ab-initio density functional theory calculations were performed and compared to experimental properties of MoS2 and WSe2 films, which show that the ALD films grown in this research match theoretical predictions. The transconductance measurements from the WSe2 devices used, matched very well with the theoretical calculations, bridging the gap between experimental data and theoretical predictions. Based upon this research, ALD growth of TMD films proves to be a viable alternative for silicon based digital electronics.

Silicone pressure-reducing pads for the prevention and treatment of pressure ulcers.

PubMed

Hughes, Maria A

2014-06-01

Pressure ulcers, a key quality of care indicator, cause emotional distress to the patient, affecting quality of life. They also have significant financial implications for the NHS. Pressure ulcer prevention and management are fundamental aspects of nursing. This article reports on the Wirral Community Trust's policy and guidelines for the maintenance of skin integrity. Tissue viability nurses have a duty to review and assess new prevention devices and dressings as they become available to ensure a high standard of care is provided. A report of an evaluation of the use of KerraPro in combination with current best practice guidelines for the prevention or treatment of pressure ulcers is provided. The author concludes that silicone pressure-reducing pads are a valuable tool in the prevention and treatment of pressure ulcers when used in combination with recommendations from the latest guidelines.

Materials and processing approaches for foundry-compatible transient electronics.

PubMed

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A; Song, Enming; Yu, Xinge; Rogers, John A

2017-07-11

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for "green" electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are ( i ) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, ( ii ) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and ( iii ) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Materials and processing approaches for foundry-compatible transient electronics

NASA Astrophysics Data System (ADS)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

Single-Crystalline InGaAs/InP Dense Micro-Pillar Forest on Poly-Silicon Substrates for Low-Cost High-Efficiency Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang-Hasnain, Constance

2015-05-04

The ultimate goal of this project is to develop a photovoltaic system high conversion efficiency (>20%) using high quality III-V compound-based three-dimensional micro-structures on silicon and poly-silicon. Such a PV-system could be of very low cost due to minimum usages of III-V materials. This project will address the barriers that currently hamper the performance of solar cells based on three-dimensional micro-structures. To accomplish this goal the project is divided into 4 tasks, each dealing with a different aspect of the project: materials quality, micropillar growth control, light management, and pillar based solar cells. Materials Quality: the internal quantum efficiency (IQE)more » - by which is meant here the internal fluorescence yield - of the micro-pillars has to be increased. We aim at achieving an IQE of 45% by the end of the first year. By the end of the second year there will be a go-no-go milestone of 65% IQE. By the end of year 3 and 4 we aim to achieve 75% and 90% IQE, respectively. Micropillar growth control: dense forests of micropillars with high fill ratios need to be grown. Pillars within forests should show minimum variations in size. We aim at achieving fill ratios of 2%, 10%, >15%, >20% in years 1, 2, 3, and 4, respectively. Variations in dimension should be minimized by site-controlled growth of pillars. By the end of year 1 we will aim at achieving site-controlled growth with > 15% yield. By end of year 2 the variation of critical pillar dimensions should be less than 25%. Light management: high light absorption in the spectral range of the sun has been to be demonstrated for the micropillar forests. By the end of year 1 we will employ FDTD simulation techniques to demonstrate that pillar forests with fill ratios <20% can achieve 99% light absorption. By end of year 2 our original goal was to demonstrate >85% absorption. By end of year 3 > 90% absorption should be demonstrated. Pillar based solar cells: devices will be studied to explore ways to achieve high open-circuit voltages which will lead to high efficiency micropillar-based solar cells. We will start on single pillar devices and the findings in these studies should pave the way for devices based on forests/ arrays of pillars. By the end of the second year we aim to demonstrate a single pillar device with an open-circuit voltage of 0.7 V, as well as a pillar-forest based device with 8% conversion efficiency. By the end of year 3 these numbers should be improved to 0.9 V open-circuit voltage for single pillar devices and >15% efficiency for forest/array-based devices. We will aim to realize a device with 20% efficiency by the end of the project period.« less

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Additives to silane for thin film silicon photovoltaic devices

DOEpatents

Hurley, Patrick Timothy; Ridgeway, Robert Gordon; Hutchison, Katherine Anne; Langan, John Giles

2013-09-17

Chemical additives are used to increase the rate of deposition for the amorphous silicon film (.alpha.Si:H) and/or the microcrystalline silicon film (.mu.CSi:H). The electrical current is improved to generate solar grade films as photoconductive films used in the manufacturing of Thin Film based Photovoltaic (TFPV) devices.

Ultra-Sensitive Magnetoresistive Displacement Sensing Device

NASA Technical Reports Server (NTRS)

Olivas, John D. (Inventor); Lairson, Bruce M. (Inventor); Ramesham, Rajeshuni (Inventor)

2003-01-01

An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers. Other approaches include reactive ion etching of silicon on insulator (SOI), or Low Pressure Chemical Vapor Deposition of silicon nitride films over silicon substrates. The device is found to be improved with the use of giant magnetoresistive elements to detect changes in the local magnetic field.

Transfer of micro and nano-photonic silicon nanomembrane waveguide devices on flexible substrates.

PubMed

Ghaffari, Afshin; Hosseini, Amir; Xu, Xiaochuan; Kwong, David; Subbaraman, Harish; Chen, Ray T

2010-09-13

This paper demonstrates transfer of optical devices without extra un-patterned silicon onto low-cost, flexible plastic substrates using single-crystal silicon nanomembranes. Employing this transfer technique, stacking two layers of silicon nanomembranes with photonic crystal waveguide in the first layer and multi mode interference couplers in the second layer is shown, respectively. This technique is promising to realize high density integration of multilayer hybrid structures on flexible substrates.

Effects of 22 MeV protons on single junction and silicon controlled rectifiers

NASA Technical Reports Server (NTRS)

Beatty, M. E., III

1972-01-01

The effects of 22-MeV protons on various types of silicon single junction and silicon controlled rectifiers were investigated. The results show that low-leakage devices and silicon controlled rectifiers are the most susceptable to radiation damage. There are also differences noted between single junction rectifiers of the same type made by different manufacturers, which emphasizes the need for better selection of devices used in spacecraft.

Vertical waveguides integrated with silicon photodetectors: Towards high efficiency and low cross-talk image sensors

NASA Astrophysics Data System (ADS)

Tut, Turgut; Dan, Yaping; Duane, Peter; Yu, Young; Wober, Munib; Crozier, Kenneth B.

2012-01-01

We describe the experimental realization of vertical silicon nitride waveguides integrated with silicon photodetectors. The waveguides are embedded in a silicon dioxide layer. Scanning photocurrent microscopy is performed on a device containing a waveguide, and on a device containing the silicon dioxide layer, but without the waveguide. The results confirm the waveguide's ability to guide light onto the photodetector with high efficiency. We anticipate that the use of these structures in image sensors, with one waveguide per pixel, would greatly improve efficiency and significantly reduce inter-pixel crosstalk.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M.; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2015-09-08

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the gap region between the first electrical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof

DOEpatents

Tour, James M; Yao, Jun; Natelson, Douglas; Zhong, Lin; He, Tao

2013-11-26

In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed on a substrate to define a gap region therebetween. A switching layer containing a switchably conductive silicon oxide resides in the the gap region between the first electical contact and the second electrical contact. The electronic devices exhibit hysteretic current versus voltage properties, enabling their use in switching and memory applications. Methods for configuring, operating and constructing the electronic devices are also presented herein.

An "artificial retina" processor for track reconstruction at the full LHC crossing rate

NASA Astrophysics Data System (ADS)

Abba, A.; Bedeschi, F.; Caponio, F.; Cenci, R.; Citterio, M.; Cusimano, A.; Fu, J.; Geraci, A.; Grizzuti, M.; Lusardi, N.; Marino, P.; Morello, M. J.; Neri, N.; Ninci, D.; Petruzzo, M.; Piucci, A.; Punzi, G.; Ristori, L.; Spinella, F.; Stracka, S.; Tonelli, D.; Walsh, J.

2016-07-01

We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.

An "artificial retina" processor for track reconstruction at the full LHC crossing rate

DOE PAGES

Abba, A.; F. Bedeschi; Caponio, F.; ...

2015-10-23

Here, we present the latest results of an R&D; study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.

Silicon MOS inductor

DOEpatents

Balberg, Isaac

1981-01-01

A device made of amorphous silicon which exhibits inductive properties at certain voltage biases and in certain frequency ranges in described. Devices of the type described can be made in integrated circuit form.

The study of surface acoustic wave charge transfer device

NASA Technical Reports Server (NTRS)

Papanicolaou, N.; Lin, H. C.

1978-01-01

A surface acoustic wave-charge transfer device, consisting of an n-type silicon substrate, a thermally grown silicon dioxide layer, and a sputtered film of piezoelectric zinc oxide is proposed as a means of circumventing problems associated with charge-coupled device (CCD) applications in memory, signal processing, and imaging. The proposed device creates traveling longitudinal electric fields in the silicon and replaces the multiphase clocks in CCD's. The traveling electric fields create potential wells which carry along charges stored there. These charges may be injected into the wells by light or by using a p-n junction as in conventional CCD's.

Nonlinear silicon photonics

NASA Astrophysics Data System (ADS)

Borghi, M.; Castellan, C.; Signorini, S.; Trenti, A.; Pavesi, L.

2017-09-01

Silicon photonics is a technology based on fabricating integrated optical circuits by using the same paradigms as the dominant electronics industry. After twenty years of fervid development, silicon photonics is entering the market with low cost, high performance and mass-manufacturable optical devices. Until now, most silicon photonic devices have been based on linear optical effects, despite the many phenomenologies associated with nonlinear optics in both bulk materials and integrated waveguides. Silicon and silicon-based materials have strong optical nonlinearities which are enhanced in integrated devices by the small cross-section of the high-index contrast silicon waveguides or photonic crystals. Here the photons are made to strongly interact with the medium where they propagate. This is the central argument of nonlinear silicon photonics. It is the aim of this review to describe the state-of-the-art in the field. Starting from the basic nonlinearities in a silicon waveguide or in optical resonator geometries, many phenomena and applications are described—including frequency generation, frequency conversion, frequency-comb generation, supercontinuum generation, soliton formation, temporal imaging and time lensing, Raman lasing, and comb spectroscopy. Emerging quantum photonics applications, such as entangled photon sources, heralded single-photon sources and integrated quantum photonic circuits are also addressed at the end of this review.

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Circuit quantum electrodynamics architecture for gate-defined quantum dots in silicon

NASA Astrophysics Data System (ADS)

Mi, X.; Cady, J. V.; Zajac, D. M.; Stehlik, J.; Edge, L. F.; Petta, J. R.

2017-01-01

We demonstrate a hybrid device architecture where the charge states in a double quantum dot (DQD) formed in a Si/SiGe heterostructure are read out using an on-chip superconducting microwave cavity. A quality factor Q = 5400 is achieved by selectively etching away regions of the quantum well and by reducing photon losses through low-pass filtering of the gate bias lines. Homodyne measurements of the cavity transmission reveal DQD charge stability diagrams and a charge-cavity coupling rate g c / 2 π = 23 MHz. These measurements indicate that electrons trapped in a Si DQD can be effectively coupled to microwave photons, potentially enabling coherent electron-photon interactions in silicon.

Influence of polarized bias and porous silicon morphology on the electrical behavior of Au-porous silicon contacts*

PubMed Central

Zhao, Yue; Li, Dong-sheng; Xing, Shou-xiang; Yang, De-ren; Jiang, Min-hua

2005-01-01

This paper reports the surface morphology and I-V curves of porous silicon (PS) samples and related devices. The observed fabrics on the PS surface were found to affect the electrical property of PS devices. When the devices were operated under different external bias (10 V or 3 V) for 10 min, their observed obvious differences in electrical properties may be due to the different control mechanisms in the Al/PS interface and PS matrix morphology. PMID:16252350

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

PubMed Central

Wolfrum, Bernhard; Thierry, Benjamin

2018-01-01

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs’ promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology. PMID:29751688

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE PAGES

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff; ...

2015-08-20

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Proceedings of the Flat-Plate Solar Array Project Workshop on Crystal Gowth for High-Efficiency Silicon Solar Cells

NASA Technical Reports Server (NTRS)

Dumas, K. A. (Editor)

1985-01-01

A Workshop on Crystal Growth for High-Efficiency Silicon Solar Cells was held December 3 and 4, 1984, in San Diego, California. The Workshop offered a day and a half of technical presentations and discussions and an afternoon session that involved a panel discussion and general discussion of areas of research that are necessary to the development of materials for high-efficiency solar cells. Topics included the theoretical and experimental aspects of growing high-quality silicon crystals, the effects of growth-process-related defects on photovoltaic devices, and the suitability of various growth technologies as cost-effective processes. Fifteen invited papers were presented, with a discussion period following each presentation. The meeting was organized by the Flat-Plate Solar Array Project of the Jet Propulsion Laboratory. These Proceedings are a record of the presentations and discussions, edited for clarity and continuity.

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Growth of magnesium diboride thin films on boron buffered Si and silicon-on-insulator substrates by hybrid physical chemical vapor deposition

NASA Astrophysics Data System (ADS)

Withanage, Wenura K.; Penmatsa, Sashank V.; Acharya, Narendra; Melbourne, Thomas; Cunnane, D.; Karasik, B. S.; Xi, X. X.

2018-07-01

We report on the growth of high quality MgB2 thin films on silicon and silicon-on-insulator substrates by hybrid physical chemical vapor deposition. A boron buffer layer was deposited on all sides of the Si substrate to prevent the reaction of Mg vapor and Si. Ar ion milling at a low angle of 1° was used to reduce the roughness of the boron buffer layer before the MgB2 growth. An Ar ion milling at low angle of 1° was also applied to the MgB2 surface to reduce its roughness. The resultant MgB2 films showed excellent superconducting properties and a smooth surface. The process produces thin MgB2 films suitable for waveguide-based superconducting hot electron bolometers and other MgB2-based electronic devices.

Silicon-on-ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

Significant progress is reported in fabricating a 4 sq cm cell having a 10.1 percent conversion efficiency and a 10 sq cm cell having a 9.2 percent conversion efficiency. The continuous (SCIM) coater succeeded in producing a 16 sq cm coating exhibiting unidirectional solidification and large grain size. A layer was grown at 0.2 cm/sec in the experimental coater which was partially dendritic but also contained a large smooth area approximately 100 micron m thick. The dark characteristic measurements of a typical SCC solar cell yield shunt resistance values of 10K ohms and series resistance values and 0.4 ohm. The production dip-coater is operating at over 50 percent yield in terms of good cell quality material. The most recent run yielded 13 good substrates out of 15.

Review Application of Nanostructured Black Silicon

NASA Astrophysics Data System (ADS)

Lv, Jian; Zhang, Ting; Zhang, Peng; Zhao, Yingchun; Li, Shibin

2018-04-01

As a widely used semiconductor material, silicon has been extensively used in many areas, such as photodiode, photodetector, and photovoltaic devices. However, the high surface reflectance and large bandgap of traditional bulk silicon restrict the full use of the spectrum. To solve this problem, many methods have been developed. Among them, the surface nanostructured silicon, namely black silicon, is the most efficient and widely used. Due to its high absorption in the wide range from UV-visible to infrared, black silicon is very attractive for using as sensitive layer of photodiodes, photodetector, solar cells, field emission, luminescence, and other photoelectric devices. Intensive study has been performed to understand the enhanced absorption of black silicon as well as the response extended to infrared spectrum range. In this paper, the application of black silicon is systematically reviewed. The limitations and challenges of black silicon material are also discussed. This article will provide a meaningful introduction to black silicon and its unique properties.

Technology computer aided design of 29.5% efficient perovskite/interdigitated back contact silicon heterojunction mechanically stacked tandem solar cell for energy-efficient applications

NASA Astrophysics Data System (ADS)

Pandey, Rahul; Chaujar, Rishu

2017-04-01

A 29.5% efficient perovskite/SiC passivated interdigitated back contact silicon heterojunction (IBC-SiHJ) mechanically stacked tandem solar cell device has been designed and simulated. This is a substantial improvement of 40% and 15%, respectively, compared to the transparent perovskite solar cell (21.1%) and Si solar cell (25.6%) operated individually. The perovskite solar cell has been used as a top subcell, whereas 250- and 25-μm-thick IBC-SiHJ solar cells have been used as bottom subcells. The realistic technology computer aided design analysis has been performed to understand the physical processes in the device and to make reliable predictions of the behavior. The performance of the top subcell has been obtained for different acceptor densities and hole mobility in Spiro-MeOTAD along with the impact of counter electrode work function. To incorporate the effect of material quality, the influence of carrier lifetimes has also been studied for perovskite top and IBC-SiHJ bottom subcells. The optical and electrical behavior of the devices has been obtained for both standalone as well as tandem configuration. Results reported in this study reveal that the proposed four-terminal tandem device may open a new door for cost-effective and energy-efficient applications.

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide.

PubMed

Min Lee, Seung; Hwan Yum, Jung; Larsen, Eric S; Chul Lee, Woo; Keun Kim, Seong; Bielawski, Christopher W; Oh, Jungwoo

2017-10-16

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

Metalorganic chemical vapor deposition of gallium nitride on sacrificial substrates

NASA Astrophysics Data System (ADS)

Fenwick, William Edward

GaN-based light emitting diodes (LEDs) face several challenges if the technology is to continue to make a significant impact in general illumination, and on technology that has become known as solid state lighting (SSL). Two of the most pressing challenges for the continued penetration of SSL into traditional lighting applications are efficacy and total lumens from the device, and their related cost. The development of alternative substrate technologies is a promising avenue toward addressing both of these challenges, as both GaN-based device technology and the associated metalorganic chemical vapor deposition (MOCVD) technology are already relatively mature technologies with a well-understood cost base. Zinc oxide (ZnO) and silicon (Si) are among the most promising alternative substrates for GaN epitaxy. These substrates offer the ability to access both higher efficacy and lumen devices (ZnO) at a much reduced cost. This work focuses on the development of MOCVD growth processes to yield high quality GaN-based materials and devices on both ZnO and Si. ZnO is a promising substrate for growth of low defect-density GaN because of its similar lattice constant and thermal expansion coefficient. The major hurdles for GaN growth on ZnO are the instability of the substrate in a hydrogen atmosphere, which is typical of nitride growth conditions, and the inter-diffusion of zinc and oxygen from the substrate into the GaN-based epitaxial layer. A process was developed for the MOCVD growth of GaN and InxGa 1-xN on ZnO that attempted to address these issues. The structural and optical properties of these films were studied using various techniques. X-ray diffraction (XRD) showed the growth of wurtzite GaN on ZnO, and room-temperature photoluminescence (RT-PL) showed near band-edge luminescence from the GaN and InxGa1-xN layers. However, high zinc and oxygen concentrations due to interdiffusion near the ZnO substrate remained an issue; therefore, the diffusion of zinc and oxygen into the subsequent GaN layer was studied in more detail. Several approaches were investigated---for example, transition layers such as Al2O3 and Al xGa1-xN/GaN---to minimize diffusion of these impurities into the GaN layer. Silicon, due to its prevalence, is the most promising material for the development of an inexpensive, large-area substrate technology. The challenge in MOCVD growth of GaN on Si is the tensile strain induced by the lattice and thermal mismatch between GaN and Si and the formation of anti-phase boundaries. Typical approaches to solve these problems involve complicated and multiple buffer layer structures, which lead to relatively slow growth rates. In this work, a thin atomic layer deposition (ALD)-grown Al2O3 interlayer was employed to relieve strain and increase material quality while also simplifying the growth process. While some residual strain was still observed in the GaN material by XRD and PL, the use of this oxide interlayer leads to an improvement in thin film quality as seen by a reduction in both crack density (<1 mm-2) on ALD-Al2O3/Si) and screw dislocation density (from 3x109cm-2 on bare Si to 2x108cm-2 on ALD-Al 2O3/Si) in the GaN films. A side-by-side comparison of GaN-based multiple quantum well LEDs grown on sapphire and on Al2O3/Si shows similar performance characteristic for both device structures. A redshift in peak emission wavelength was also observed on silicon compared to sapphire, and this is attributed to higher indium content due to the slight tensile strain in the layers on silicon. IQE of the devices on silicon is ˜32% as measured by LT-PL, compared to ˜37% on sapphire, but this difference can be assigned to the difference in indium compositions. These results show a great promise toward an inexpensive, large-area, silicon-based substrate technology for MOCVD growth of the next generation of GaN-based optoelectronic devices for SSL and other applications.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

NASA Astrophysics Data System (ADS)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes

NASA Astrophysics Data System (ADS)

Ho, Hsiang-Hsi; Lin, Chun-Lung; Tsai, Wei-Che; Hong, Liang-Zheng; Lyu, Cheng-Han; Hsu, Hsun-Feng

2018-01-01

We demonstrate the fabrication and characterization of silicon nanowire-based devices in metal-nanowire-metal configuration using direct current dielectrophoresis. The current-voltage characteristics of the devices were found rectifying, and their direction of rectification could be determined by voltage sweep direction due to the asymmetric Joule heating effect that occurred in the electrical measurement process. The photosensing properties of the rectifying devices were investigated. It reveals that when the rectifying device was in reverse-biased mode, the excellent photoresponse was achieved due to the strong built-in electric field at the junction interface. It is expected that rectifying silicon nanowire-based devices through this novel and facile method can be potentially applied to other applications such as logic gates and sensors.

Nanostructure iron-silicon thin film deposition using plasma focus device

NASA Astrophysics Data System (ADS)

Kotb, M.; Saudy, A. H.; Hassaballa, S.; Eloker, M. M.

2013-03-01

The presented study in this paper reports the deposition of nano-structure iron-silicon thin film on a glass substrate using 3.3 KJ Mather-type plasma focus device. The iron-silicon powder was put on the top of hollow copper anode electrode. The deposition was done under different experimental conditions such as numbers of electric discharge shots and angular position of substrate. The film samples were exposed to energetic argon ions generated by plasma focus device at different distances from the top of the central electrode. The exposed samples were then analyzed for their structure and optical properties using X-ray diffraction (XRD) and UV-visible spectroscopy. The structure of iron-silicon thin films deposited using plasma focus device depends on the distance from the anode, the number of focus deposition shots and the angular position of the sample

Silicon carbide, an emerging high temperature semiconductor

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony

1991-01-01

In recent years, the aerospace propulsion and space power communities have expressed a growing need for electronic devices that are capable of sustained high temperature operation. Applications for high temperature electronic devices include development instrumentation within engines, engine control, and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Other earth-based applications include deep-well drilling instrumentation, nuclear reactor instrumentation and control, and automotive sensors. To meet the needs of these applications, the High Temperature Electronics Program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. Research is focussed on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of silicon carbide electronic devices and integrated sensors. The progress made in developing silicon carbide is presented, and the challenges that lie ahead are discussed.

Silicone metalization

DOEpatents

Maghribi, Mariam N [Livermore, CA; Krulevitch, Peter [Pleasanton, CA; Hamilton, Julie [Tracy, CA

2006-12-05

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Silicone metalization

DOEpatents

Maghribi, Mariam N.; Krulevitch, Peter; Hamilton, Julie

2008-12-09

A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Materials and processing approaches for foundry-compatible transient electronics

PubMed Central

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-01-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries. PMID:28652373

A Silicon-Chip Source of Bright Photon-Pair Comb

DTIC Science & Technology

2012-10-16

A silicon -chip source of bright photon-pair comb Wei C. Jiang,1, ∗ Xiyuan Lu,2, ∗ Jidong Zhang,3 Oskar Painter,4 and Qiang Lin1, 3, † 1Institute of...efficient monolithic photon-pair source for on-chip application. Here we report a device on the silicon -on-insulator platform that utilizes dramatic cavity...enhanced four-wave mixing in a high-Q silicon microdisk resonator. The device is able to produce high-purity photon pairs in a comb fashion, with an

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

Thermally tunable silicon racetrack resonators with ultralow tuning power.

PubMed

Dong, Po; Qian, Wei; Liang, Hong; Shafiiha, Roshanak; Feng, Dazeng; Li, Guoliang; Cunningham, John E; Krishnamoorthy, Ashok V; Asghari, Mehdi

2010-09-13

We present thermally tunable silicon racetrack resonators with an ultralow tuning power of 2.4 mW per free spectral range. The use of free-standing silicon racetrack resonators with undercut structures significantly enhances the tuning efficiency, with one order of magnitude improvement of that for previously demonstrated thermo-optic devices without undercuts. The 10%-90% switching time is demonstrated to be ~170 µs. Such low-power tunable micro-resonators are particularly useful as multiplexing devices and wavelength-tunable silicon microcavity modulators.

Opening the band gap of graphene through silicon doping for the improved performance of graphene/GaAs heterojunction solar cells.

PubMed

Zhang, S J; Lin, S S; Li, X Q; Liu, X Y; Wu, H A; Xu, W L; Wang, P; Wu, Z Q; Zhong, H K; Xu, Z J

2016-01-07

Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications.

Choice of Substrate Material for Epitaxial CdTe Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Tao; Kanevce, Ana; Sites, James R.

2015-06-14

Epitaxial CdTe with high quality, low defect density, and high carrier concentration should in principle yield high-efficiency photovoltaic devices. However, insufficient effort has been given to explore the choice of substrate for high-efficiency epitaxial CdTe solar cells. In this paper, we use numerical simulations to investigate three crystalline substrates: silicon (Si), InSb, and CdTe each substrate material are generally discussed.

Silicon photonics and challenges for fabrication

NASA Astrophysics Data System (ADS)

Feilchenfeld, N. B.; Nummy, K.; Barwicz, T.; Gill, D.; Kiewra, E.; Leidy, R.; Orcutt, J. S.; Rosenberg, J.; Stricker, A. D.; Whiting, C.; Ayala, J.; Cucci, B.; Dang, D.; Doan, T.; Ghosal, M.; Khater, M.; McLean, K.; Porth, B.; Sowinski, Z.; Willets, C.; Xiong, C.; Yu, C.; Yum, S.; Giewont, K.; Green, W. M. J.

2017-03-01

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Ultra-low energy photoreceivers for optical interconnects

NASA Astrophysics Data System (ADS)

Going, Ryan Wayne

Optical interconnects are increasingly important for our communication and data center systems, and are forecasted to be an essential component of future computers. In order to meet these future demands, optical interconnects must be improved to consume less power than they do today. To do this, both more efficient transmitters and more sensitive receivers must be developed. This work addresses the latter, focusing on device level improvements to tightly couple a low capacitance photodiode with the first stage transistor of the receiver as a single phototransistor device. First I motivate the need for a coupled phototransistor using a simple circuit model which shows how receiver sensitivity is determined by photodiode capacitance and the length of wire connecting it to the first transistor in a receiver amplifier. Then I describe our use of the unique rapid melt growth technique, which is used to integrate crystalline germanium on silicon photonics substrates without an epitaxial reactor. The resulting material quality is demonstrated with high quality (0.95 A/W, 40+ GHz) germanium photodiodes on silicon waveguides. Next I describe two germanium phototransistors I have developed. One is a germanium- gated MOSFET on silicon photonics which has up to 18 A/W gate-controlled responsivity at 1550 nm. Simulations show how MOSFET scaling rules can be easily applied to increase both speed and sensitivity. The second is a floating base germanium bipolar phototransistor on silicon photonics with a 15 GHz gain x bandwidth product. The photoBJT also has a clear scaling path, and it is proposed to create a separate gain and absorption region photoBJT to realize the maximum benefit of scaling the BJT without negatively affecting its absorption and photocarrier collection. Following this design a 120 GHz gain x bandwidth photoBJT is simulated. Finally I present a metal-cavity, which can have over 50% quantum efficiency absorption in sub-100 aF germanium photodiodes, which addresses the issue of absorption in photodiodes which have been scaled to near sub-wavelength dimensions.

Silicon insulator-based dielectrophoresis devices for minimized heating effects.

PubMed

Zellner, Phillip; Agah, Masoud

2012-08-01

Concentration of biological specimens that are extremely dilute in a solution is of paramount importance for their detection. Microfluidic chips based on insulator-based DEP (iDEP) have been used to selectively concentrate bacteria and viruses. iDEP biochips are currently fabricated with glass or polymer substrates to allow for high electric fields within the channels. Joule heating is a well-known problem in these substrates and can lead to decreased throughput and even device failure. In this work, we present, for the first time, highly efficient trapping and separation of particles in DC iDEP devices that are fabricated on silicon using a single-etch-step three-dimensional microfabrication process with greatly improved heat dissipation properties. Fabrication in silicon allows for greater heat dissipation for identical geometries and operating conditions. The 3D fabrication allows for higher performance at lower applied potentials. Thermal measurements were performed on both the presented silicon chips and previously published PDMS devices comprised of microposts. Trapping and separation of 1 and 2 μm polystyrene particles was demonstrated. These results demonstrate the feasibility of high-performance silicon iDEP devices for the next generation of sorting and concentration microsystems. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexural plate wave devices fabricated from silicon carbide membrane

NASA Astrophysics Data System (ADS)

Diagne, Ndeye Fama

Flexural Plate Wave (FPW) devices fabricated from Silicon Carbide (SiC) membranes are presented here which exhibit electrical and mechanical characteristics in its transfer functions that makes it very useful as a low voltage probe device capable of functioning in small areas that are commonly inaccessible to ordinary devices. The low input impedance characteristic of this current driven device makes it possible for it to operate at very low voltages, thereby reducing the hazards for flammable or explosive areas to be probed. The Flexural Plate Wave (FPW) devices are of a family of gravimetric type sensors that permit direct measurements of the mass of the vibrating element. The primary objective was to study the suitability of Silicon Carbide (SiC) membranes as a replacement of Silicon Nitride (SiN) membrane in flexural plate wave devices developed by Sandia National Laboratories. Fabrication of the Flexural Plate Wave devices involves the overlaying a silicon wafer with membranes of 3C-SiC thin film upon which conducting meander lines are placed. The input excitation energy is in the form of an input current. The lines of current along the direction of the conducting Meander Lines Transducer (MLTs) and the applied perpendicular external magnetic field set up a mechanical wave perpendicular to both, exciting the membrane by means of a Lorentz force, which in turn sets up flexural waves that propagate along the thin membrane. The physical dimensions, the mass density, the tension in the membrane and the meander spacing are physical characteristics that determine resonance frequency of the Flexural Plate Wave (FPW) device. Of primary interest is the determination of the resonant frequency of the silicon carbide membrane as functions of the device physical characteristic parameters. The appropriate transduction scheme with Meander Line Transducers (IDTs) are used to excite the membrane. Equivalent circuit models characterizing the reflection response S11 (amplitude and phase) for a one-port Flexural PlateWave device and the transmission response S21 of a two-port device are used for the development of the equivalent mechanical characteristics.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

PubMed Central

Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ömer

2017-01-01

Silicon is an excellent material for microelectronics and integrated photonics1–3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e., “in-chip” microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances. PMID:28983323

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

NASA Astrophysics Data System (ADS)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

Heavily Boron-Doped Silicon Layer for the Fabrication of Nanoscale Thermoelectric Devices

PubMed Central

Liu, Yang; Deng, Lingxiao; Zhang, Mingliang; Zhang, Shuyuan; Ma, Jing; Song, Peishuai; Liu, Qing; Ji, An; Yang, Fuhua; Wang, Xiaodong

2018-01-01

Heavily boron-doped silicon layers and boron etch-stop techniques have been widely used in the fabrication of microelectromechanical systems (MEMS). This paper provides an introduction to the fabrication process of nanoscale silicon thermoelectric devices. Low-dimensional structures such as silicon nanowire (SiNW) have been considered as a promising alternative for thermoelectric applications in order to achieve a higher thermoelectric figure of merit (ZT) than bulk silicon. Here, heavily boron-doped silicon layers and boron etch-stop processes for the fabrication of suspended SiNWs will be discussed in detail, including boron diffusion, electron beam lithography, inductively coupled plasma (ICP) etching and tetramethylammonium hydroxide (TMAH) etch-stop processes. A 7 μm long nanowire structure with a height of 280 nm and a width of 55 nm was achieved, indicating that the proposed technique is useful for nanoscale fabrication. Furthermore, a SiNW thermoelectric device has also been demonstrated, and its performance shows an obvious reduction in thermal conductivity. PMID:29385759

A strong electro-optically active lead-free ferroelectric integrated on silicon

NASA Astrophysics Data System (ADS)

Abel, Stefan; Stöferle, Thilo; Marchiori, Chiara; Rossel, Christophe; Rossell, Marta D.; Erni, Rolf; Caimi, Daniele; Sousa, Marilyne; Chelnokov, Alexei; Offrein, Bert J.; Fompeyrine, Jean

2013-04-01

The development of silicon photonics could greatly benefit from the linear electro-optical properties, absent in bulk silicon, of ferroelectric oxides, as a novel way to seamlessly connect the electrical and optical domain. Of all oxides, barium titanate exhibits one of the largest linear electro-optical coefficients, which has however not yet been explored for thin films on silicon. Here we report on the electro-optical properties of thin barium titanate films epitaxially grown on silicon substrates. We extract a large effective Pockels coefficient of reff=148 pm V-1, which is five times larger than in the current standard material for electro-optical devices, lithium niobate. We also reveal the tensor nature of the electro-optical properties, as necessary for properly designing future devices, and furthermore unambiguously demonstrate the presence of ferroelectricity. The integration of electro-optical active films on silicon could pave the way towards power-efficient, ultra-compact integrated devices, such as modulators, tuning elements and bistable switches.

Packaging of silicon photonic devices: from prototypes to production

NASA Astrophysics Data System (ADS)

Morrissey, Padraic E.; Gradkowski, Kamil; Carroll, Lee; O'Brien, Peter

2018-02-01

The challenges associated with the photonic packaging of silicon devices is often underestimated and remains technically challenging. In this paper, we review some key enabling technologies that will allow us to overcome the current bottleneck in silicon photonic packaging; while also describing the recent developments in standardisation, including the establishment of PIXAPP as the worlds first open-access PIC packaging and assembly Pilot Line. These developments will allow the community to move from low volume prototype photonic packaged devices to large scale volume manufacturing, where the full commercialisation of PIC technology can be realised.

Gas-phase synthesis of semiconductor nanocrystals and its applications

NASA Astrophysics Data System (ADS)

Mandal, Rajib

Luminescent nanomaterials is a newly emerging field that provides challenges not only to fundamental research but also to innovative technology in several areas such as electronics, photonics, nanotechnology, display, lighting, biomedical engineering and environmental control. These nanomaterials come in various forms, shapes and comprises of semiconductors, metals, oxides, and inorganic and organic polymers. Most importantly, these luminescent nanomaterials can have different properties owing to their size as compared to their bulk counterparts. Here we describe the use of plasmas in synthesis, modification, and deposition of semiconductor nanomaterials for luminescence applications. Nanocrystalline silicon is widely known as an efficient and tunable optical emitter and is attracting great interest for applications in several areas. To date, however, luminescent silicon nanocrystals (NCs) have been used exclusively in traditional rigid devices. For the field to advance towards new and versatile applications for nanocrystal-based devices, there is a need to investigate whether these NCs can be used in flexible and stretchable devices. We show how the optical and structural/morphological properties of plasma-synthesized silicon nanocrystals (Si NCs) change when they are deposited on stretchable substrates made of polydimethylsiloxane (PDMS). Synthesis of these NCs was performed in a nonthermal, low-pressure gas phase plasma reactor. To our knowledge, this is the first demonstration of direct deposition of NCs onto stretchable substrates. Additionally, in order to prevent oxidation and enhance the luminescence properties, a silicon nitride shell was grown around Si NCs. We have demonstrated surface nitridation of Si NCs in a single step process using non?thermal plasma in several schemes including a novel dual-plasma synthesis/shell growth process. These coated NCs exhibit SiNx shells with composition depending on process parameters. While measurements including photoluminescence (PL), surface analysis, and defect identification indicate the shell is protective against oxidation compared to Si NCs without any shell growth. Gallium Nitride (GaN) is one of the most well-known semiconductor material and the industry standard for fabricating LEDs. The problem is that epitaxial growth of high-quality GaN requires costly substrates (e.g. sapphire), high temperatures, and long processing times. Synthesizing freestanding NCs of GaN, on the other hand, could enable these novel device morphologies, as the NCs could be incorporated into devices without the requirements imposed by epitaxial GaN growth. Synthesis of GaN NCs was performed using a fully gas-phase process. Different sizes of crystalline GaN nanoparticles were produced indicating versatility of this gas-phase process. Elemental analysis using X-ray photoelectron spectroscopy (XPS) indicated a possible nitrogen deficiency in the NCs; addition of secondary plasma for surface treatment indicates improving stoichiometric ratio and points towards a unique method for creating high-quality GaN NCs with ultimate alloying and doping for full-spectrum luminescence.

Photoluminescence microscopy on air-suspended carbon nanotubes coupled to photonic crystal nanobeam cavities

NASA Astrophysics Data System (ADS)

Miura, R.; Imamura, S.; Shimada, T.; Ohta, R.; Iwamoto, S.; Arakawa, Y.; Kato, Y. K.

2014-03-01

Because carbon nanotubes are room-temperature telecom-band emitters and can be grown on silicon substrates, they are ideal for coupling to silicon photonic cavities.[2,3 In particular, as-grown air-suspended carbon nanotubes show excellent optical properties, but cavity modes with large fields in the air are needed in order to achieve efficient coupling. Here we investigate individual air-suspended nanotubes coupled to photonic crystal nanobeam cavities. We utilize cavities that confine air-band modes which have large fields in the air. Dielectric mode cavities are also prepared for comparison. We fabricate the devices from silicon-on-insulator substrates by using electron beam lithography and dry etching to form the nanobeam structure. The buried oxide layer is removed by wet etching, and carbon nanotubes are grown onto the cavities by chemical vapor deposition. We perform photoluminescence imaging and excitation spectroscopy to find the positions of the nanotubes and identify their chiralities. For both types of devices, cavity modes with quality factors of ~3000 are observed within the nanotube emission peak. Work supported by SCOPE, KAKENHI, The Telecommunications Advancement Foundation, The Toyota Physical and Chemical Research Institute, Project for Developing Innovation Systems of MEXT, Japan and the Photon Frontier Network Program of MEXT, Japan.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Silicon Carbide Diodes Performance Characterization and Comparison With Silicon Devices

NASA Technical Reports Server (NTRS)

Lebron-Velilla, Ramon C.; Schwarze, Gene E.; Trapp, Scott

2003-01-01

Commercially available silicon carbide (SiC) Schottky diodes from different manufacturers were electrically tested and characterized at room temperature. Performed electrical tests include steady state forward and reverse I-V curves, as well as switching transient tests performed with the diodes operating in a hard switch dc-to-dc buck converter. The same tests were performed in current state of the art silicon (Si) and gallium arsenide (GaAs) Schottky and pn junction devices for evaluation and comparison purposes. The SiC devices tested have a voltage rating of 200, 300, and 600 V. The comparison parameters are forward voltage drop at rated current, reverse current at rated voltage and peak reverse recovery currents in the dc to dc converter. Test results show that steady state characteristics of the tested SiC devices are not superior to the best available Si Schottky and ultra fast pn junction devices. Transient tests reveal that the tested SiC Schottky devices exhibit superior transient behavior. This is more evident at the 300 and 600 V rating where SiC Schottky devices showed drastically lower reverse recovery currents than Si ultra fast pn diodes of similar rating.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics.

PubMed

Rao, Sandro; Pangallo, Giovanni; Della Corte, Francesco Giuseppe

2016-01-06

Hydrogenated amorphous silicon (a-Si:H) shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34-40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

Plastic-Syringe Induced Silicone Contamination in Organic Photvoltaic Fabrication: Implications for Small-Volume Additives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carr, John A.; Nalwa, Kanwar S.; Mahadevapuram, Rakesh

Herein, the implications of silicone contamination found in solution-processed conjugated polymer solar cells are explored. Similar to a previous work based on molecular cells, we find this contamination as a result of the use of plastic syringes during fabrication. However, in contrast to the molecular case, we find that glass-syringe fabricated devices give superior performance than plastic-syringe fabricated devices in poly(3-hexylthiophene)-based cells. We find that the unintentional silicone addition alters the solution’s wettability, which translates to a thinner, less absorbent film on spinning. With many groups studying the effects of small-volume additives, this work should be closely considered as manymore » of these additives may also directly alter the solutions’ wettability, or the amount of silicone dissolved off the plastic syringes, or both. Thereby, film thickness, which generally is not reported in detail, can vary significantly from device to device.« less

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Core-shell silicon nanowire solar cells

PubMed Central

Adachi, M. M.; Anantram, M. P.; Karim, K. S.

2013-01-01

Silicon nanowires can enhance broadband optical absorption and reduce radial carrier collection distances in solar cell devices. Arrays of disordered nanowires grown by vapor-liquid-solid method are attractive because they can be grown on low-cost substrates such as glass, and are large area compatible. Here, we experimentally demonstrate that an array of disordered silicon nanowires surrounded by a thin transparent conductive oxide has both low diffuse and specular reflection with total values as low as < 4% over a broad wavelength range of 400 nm < λ < 650 nm. These anti-reflective properties together with enhanced infrared absorption in the core-shell nanowire facilitates enhancement in external quantum efficiency using two different active shell materials: amorphous silicon and nanocrystalline silicon. As a result, the core-shell nanowire device exhibits a short-circuit current enhancement of 15% with an amorphous Si shell and 26% with a nanocrystalline Si shell compared to their corresponding planar devices. PMID:23529071

High-speed all-optical logic inverter based on stimulated Raman scattering in silicon nanocrystal.

PubMed

Sen, Mrinal; Das, Mukul K

2015-11-01

In this paper, we propose a new device architecture for an all-optical logic inverter (NOT gate), which is cascadable with a similar device. The inverter is based on stimulated Raman scattering in silicon nanocrystal waveguides, which are embedded in a silicon photonic crystal structure. The Raman response function of silicon nanocrystal is evaluated to explore the transfer characteristic of the inverter. A maximum product criterion for the noise margin is taken to analyze the cascadability of the inverter. The time domain response of the inverter, which explores successful inversion operation at 100 Gb/s, is analyzed. Propagation delay of the inverter is on the order of 5 ps, which is less than the delay in most of the electronic logic families as of today. Overall dimension of the device is around 755  μm ×15  μm, which ensures integration compatibility with the matured silicon industry.

Gold-based electrical interconnections for microelectronic devices

DOEpatents

Peterson, Kenneth A.; Garrett, Stephen E.; Reber, Cathleen A.; Watson, Robert D.

2002-01-01

A method of making an electrical interconnection from a microelectronic device to a package, comprising ball or wedge compression bonding a gold-based conductor directly to a silicon surface, such as a polysilicon bonding pad in a MEMS or IMEMS device, without using layers of aluminum or titanium disposed in-between the conductor and the silicon surface. After compression bonding, optional heating of the bond above 363 C. allows formation of a liquid gold-silicon eutectic phase containing approximately 3% (by weight) silicon, which significantly improves the bond strength by reforming and enhancing the initial compression bond. The same process can be used for improving the bond strength of Au--Ge bonds by forming a liquid Au-12Ge eutectic phase.

Anisotropy-based crystalline oxide-on-semiconductor material

DOEpatents

McKee, Rodney Allen; Walker, Frederick Joseph

2000-01-01

A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.

Method of making a silicon nanowire device

DOEpatents

None, None

2017-05-23

There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 .mu.m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation. The method, in examples, includes thinning the nanowire through iterative oxidation and etching of the oxidized portion.

Hybrid method of making an amorphous silicon P-I-N semiconductor device

DOEpatents

Moustakas, Theodore D.; Morel, Don L.; Abeles, Benjamin

1983-10-04

The invention is directed to a hydrogenated amorphous silicon PIN semiconductor device of hybrid glow discharge/reactive sputtering fabrication. The hybrid fabrication method is of advantage in providing an ability to control the optical band gap of the P and N layers, resulting in increased photogeneration of charge carriers and device output.

Al transmon qubits on silicon-on-insulator for quantum device integration

NASA Astrophysics Data System (ADS)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Semi-transparent perovskite solar cells for tandems with silicon and CIGS

DOE PAGES

Bailie, Colin D.; Christoforo, M. Greyson; Mailoa, Jonathan P.; ...

2014-12-23

A promising approach for upgrading the performance of an established low-bandgap solar technology without adding much cost is to deposit a high bandgap polycrystalline semiconductor on top to make a tandem solar cell. We use a transparent silver nanowire electrode on perovskite solar cells to achieve a semi-transparent device. We place the semi-transparent cell in a mechanically-stacked tandem configuration onto copper indium gallium diselenide (CIGS) and low-quality multicrystalline silicon (Si) to achieve solid-state polycrystalline tandem solar cells with a net improvement in efficiency over the bottom cell alone. Furthermore, this work paves the way for integrating perovskites into a low-costmore » and high-efficiency (>25%) tandem cell.« less

Plasma Properties of an Exploding Semiconductor Igniter

NASA Astrophysics Data System (ADS)

McGuirk, J. S.; Thomas, K. A.; Shaffer, E.; Malone, A. L.; Baginski, T.; Baginski, M. E.

1997-11-01

Requirements by the automotive industry for low-cost, pyrotechnic igniters for automotive airbags have led to the development of several semiconductor devices. The properties of the plasma produced by the vaporization of an exploding semiconductor are necessary in order to minimize the electrical energy requirements. This work considers two silicon-based semiconductor devices: the semiconductor bridge (SCB) and the semiconductor junction igniter both consisting of etched silicon with vapor deposited aluminum structures. Electrical current passing through the device heats a narrow junction region to the point of vaporization creating an aluminum and silicon low-temperature plasma. This work will investigate the electrical characteristics of both devices and infer the plasma properties. Furthermore optical spectral measurements will be taken of the exploding devices to estimate the temperature and density of the plasma.

Conformable large-area position-sensitive photodetectors based on luminescence-collecting silicone waveguides

NASA Astrophysics Data System (ADS)

Bartu, Petr; Koeppe, Robert; Arnold, Nikita; Neulinger, Anton; Fallon, Lisa; Bauer, Siegfried

2010-06-01

Position sensitive detection schemes based on the lateral photoeffect rely on inorganic semiconductors. Such position sensitive devices (PSDs) are reliable and robust, but preparation with large active areas is expensive and use on curved substrates is impossible. Here we present a novel route for the fabrication of conformable PSDs which allows easy preparation on large areas, and use on curved surfaces. Our device is based on stretchable silicone waveguides with embedded fluorescent dyes, used in conjunction with small silicon photodiodes. Impinging laser light (e.g., from a laser pointer) is absorbed by the dye in the PSD and re-emitted as fluorescence light at a larger wavelength. Due to the isotropic emission from the fluorescent dye molecules, most of the re-emitted light is coupled into the planar silicone waveguide and directed to the edges of the device. Here the light signals are detected via embedded small silicon photodiodes arranged in a regular pattern. Using a mathematical algorithm derived by extensive using of models from global positioning system (GPS) systems and human activity monitoring, the position of light spots is easily calculated. Additionally, the device shows high durability against mechanical stress, when clamped in an uniaxial stretcher and mechanically loaded up to 15% strain. The ease of fabrication, conformability, and durability of the device suggests its use as interface devices and as sensor skin for future robots.

Optomechanical trampoline resonators.

PubMed

Kleckner, Dustin; Pepper, Brian; Jeffrey, Evan; Sonin, Petro; Thon, Susanna M; Bouwmeester, Dirk

2011-09-26

We report on the development of optomechanical "trampoline" resonators composed of a tiny SiO(2)/Ta(2)O(5) dielectric mirror on a silicon nitride micro-resonator. We observe optical finesses of up to 4 × 10(4) and mechanical quality factors as high as 9 × 10(5) in relatively massive (~100 ng) and low frequency (10-200 kHz) devices. This results in a photon-phonon coupling efficiency considerably higher than previous Fabry-Perot-type optomechanical systems. These devices are well suited to ultra-sensitive force detection, ground-state optical cooling experiments, and demonstrations of quantum dynamics for such systems. © 2011 Optical Society of America

Temperature Compensation of Aluminum Nitride Lamb Wave Resonators Utilizing the Lowest-Order Symmetric Mode

DTIC Science & Technology

2012-12-14

PZT ceramic plate [40]. Since then Lamb wave devices utilizing the lowest-order antisymmetric (A0) mode propagation in ZnO thin plate were widely...Million Pt Platinum PVDF Polyvinylidene Flouride PZT Lead Zirconium Titanate Q Quality Factor R Resistor RIE Reactive Ion Etching Rm Motional...GaAs), silicon carbide (SiC), langasite (LGS), lead zirconium titanate ( PZT ), and polyvinylidene flouride (PVDF). Each piezoelectric material has

Extracting Silicon From Sodium-Process Products

NASA Technical Reports Server (NTRS)

Kapur, V.; Sanjurjo, A.; Sancier, K. M.; Nanis, L.

1982-01-01

New acid leaching process purifies silicon produced in reaction between silicon fluoride and sodium. Concentration of sodium fluoride and other impurities and byproducts remaining in silicon are within acceptable ranges for semi-conductor devices. Leaching process makes sodium reduction process more attractive for making large quantities of silicon for solar cells.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Storage Reliability of Missile Materiel Program, Monolithic Bipolar SSI/ MSI Digital and Linear Integrated Circuit Analysis

DTIC Science & Technology

1978-01-01

Beam Lead Sealed Junction (ELSJ) devices, the silicon nitride seals the devices from sodium and since the platinum silicide and titanium metals also...improve the surface stability of bipolar devices. These materials act as gettering agents for sodium ions, thus making the contamination far less...electric field, can cause appreciable device parameter instability. Silicon nitride has been shown to be an effective barrier to sodium migration. In

Silicon-on-insulator polarization splitting and rotating device for polarization diversity circuits.

PubMed

Liu, Liu; Ding, Yunhong; Yvind, Kresten; Hvam, Jørn M

2011-06-20

A compact and efficient polarization splitting and rotating device built on the silicon-on-insulator platform is introduced, which can be readily used for the interface section of a polarization diversity circuit. The device is compact, with a total length of a few tens of microns. It is also simple, consisting of only two parallel silicon-on-insulator wire waveguides with different widths, and thus requiring no additional and nonstandard fabrication steps. A total insertion loss of -0.6 dB and an extinction ratio of 12 dB have been obtained experimentally in the whole C-band.

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

NASA Astrophysics Data System (ADS)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Near-self-imaging cavity for three-mode optoacoustic parametric amplifiers using silicon microresonators.

PubMed

Liu, Jian; Torres, F A; Ma, Yubo; Zhao, C; Ju, L; Blair, D G; Chao, S; Roch-Jeune, I; Flaminio, R; Michel, C; Liu, K-Y

2014-02-10

Three-mode optoacoustic parametric amplifiers (OAPAs), in which a pair of photon modes are strongly coupled to an acoustic mode, provide a general platform for investigating self-cooling, parametric instability and very sensitive transducers. Their realization requires an optical cavity with tunable transverse modes and a high quality-factor mirror resonator. This paper presents the design of a table-top OAPA based on a near-self-imaging cavity design, using a silicon torsional microresonator. The design achieves a tuning coefficient for the optical mode spacing of 2.46  MHz/mm. This allows tuning of the mode spacing between amplification and self-cooling regimes of the OAPA device. Based on demonstrated resonator parameters (frequencies ∼400  kHz and quality-factors ∼7.5×10(5) we predict that the OAPA can achieve parametric instability with 1.6 μW of input power and mode cooling by a factor of 1.9×10(4) with 30 mW of input power.

Opening the band gap of graphene through silicon doping for the improved performance of graphene/GaAs heterojunction solar cells

NASA Astrophysics Data System (ADS)

Zhang, S. J.; Lin, S. S.; Li, X. Q.; Liu, X. Y.; Wu, H. A.; Xu, W. L.; Wang, P.; Wu, Z. Q.; Zhong, H. K.; Xu, Z. J.

2015-12-01

Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications.Graphene has attracted increasing interest due to its remarkable properties. However, the zero band gap of monolayered graphene limits it's further electronic and optoelectronic applications. Herein, we have synthesized monolayered silicon-doped graphene (SiG) with large surface area using a chemical vapor deposition method. Raman and X-ray photoelectron spectroscopy measurements demonstrate that the silicon atoms are doped into graphene lattice at a doping level of 2.7-4.5 at%. Electrical measurements based on a field effect transistor indicate that the band gap of graphene has been opened via silicon doping without a clear degradation in carrier mobility, and the work function of SiG, deduced from ultraviolet photoelectron spectroscopy, was 0.13-0.25 eV larger than that of graphene. Moreover, when compared with the graphene/GaAs heterostructure, SiG/GaAs exhibits an enhanced performance. The performance of 3.4% silicon doped SiG/GaAs solar cell has been improved by 33.7% on average, which was attributed to the increased barrier height and improved interface quality. Our results suggest that silicon doping can effectively engineer the band gap of monolayered graphene and SiG has great potential in optoelectronic device applications. Electronic supplementary information (ESI) available: Synthetic process of the SiG sheet; UPS spectra of SiG and graphene; J-V curves for the SiG/GaAs and graphene/GaAs solar cells under dark conditions and AM1.5 illumination at 100 mW cm-2, respectively; Statistic PCE of SiG/GaAs solar cells with different Si doping levels; EQE of SiG/GaAs and graphene/GaAs solar cells; a comparison of the parameters between the SiG and graphene/GaAs solar cells. See DOI: 10.1039/c5nr06345k

Ultralow-frequency PiezoMEMS energy harvester using thin-film silicon and parylene substrates

NASA Astrophysics Data System (ADS)

Jackson, Nathan; Olszewski, Oskar Z.; O'Murchu, Cian; Mathewson, Alan

2018-01-01

Developing a self-sustained leadless pacemaker requires the development of an ultralow-frequency energy harvesting system that can fit within the required dimensions. This paper reports on the design and development of two types of PiezoMEMS energy harvesters that fit within the capsule dimensions and have a low resonant frequency between 20 to 30 Hz, which is required for the application. A bullet-shaped mass was designed to maximize the displacement and enhance power density of the devices. In addition, two types of devices were fabricated and compared (i) a silicon-based cantilever and (ii) a parylene-C-based cantilever with a thin aluminum nitride layer. The silicon device demonstrated higher peak power of 29.8 μW compared with the 6.4 μW for the parylene device. However, due to the low duty cycle of the heart rate and the damping factors of the two materials the average power was significantly higher for the parylene device (2.71 μW) compared with the silicon device (1.22 μW) per cantilever. The results demonstrate that a polymer-based energy harvester can increase the average power due to low damping for an impulse-based vibration application.

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

NASA Technical Reports Server (NTRS)

Finkbeiner, F. m.; Chervenak, J. A.; Bandler, S. R.; Brekosky, R.; Brown, A. D.; Figueroa-Feliciano, E.; Iyomoto, N.; Kelley, R. L.; Kilbourne, C. A.; Porter, F. S.;

Stability of the tungsten diselenide and silicon carbide heterostructure against high energy proton exposure

NASA Astrophysics Data System (ADS)

Walker, Roger C.; Shi, Tan; Jariwala, Bhakti; Jovanovic, Igor; Robinson, Joshua A.

2017-10-01

Single layers of tungsten diselenide (WSe2) can be used to construct ultra-thin, high-performance electronics. Additionally, there has been considerable progress in controlled and direct growth of single layers on various substrates. Based on these results, high-quality WSe2-based devices that approach the limit of physical thickness are now possible. Such devices could be useful for space applications, but understanding how high-energy radiation impacts the properties of WSe2 and the WSe2/substrate interface has been lacking. In this work, we compare the stability against high energy proton radiation of WSe2 and silicon carbide (SiC) heterostructures generated by mechanical exfoliation of WSe2 flakes and by direct growth of WSe2 via metal-organic chemical vapor deposition (MOCVD). These two techniques produce WSe2/SiC heterostructures with distinct differences due to interface states generated during the MOCVD growth process. This difference carries over to differences in band alignment from interface states and the ultra-thin nature of the MOCVD-grown material. Both heterostructures are not susceptible to proton-induced charging up to a dose of 1016 protons/cm2, as measured via shifts in the binding energy of core shell electrons and a decrease in the valence band offset. Furthermore, the MOCVD-grown material is less affected by the proton exposure due to its ultra-thin nature and a greater interaction with the substrate. These combined effects show that the directly grown material is suitable for multi-year use in space, provided that high quality devices can be fabricated from it.

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Embedding solar cell materials with on-board integrated energy storage for load-leveling and dark power delivery (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pint, Cary L.; Westover, Andrew S.; Cohn, Adam P.; Erwin, William R.; Share, Keith; Metke, Thomas; Bardhan, Rizia

2015-10-01

This work will discuss our recent advances focused on integrating high power energy storage directly into the native materials of both conventional photovoltaics (PV) and dye-sensitized solar cells (DSSCs). In the first case (PV), we demonstrate the ability to etch high surface-area porous silicon charge storage interfaces directly into the backside of a conventional polycrystalline silicon photovoltaic device exhibiting over 14% efficiency. These high surface area materials are then coupled with solid-state ionic liquid-polymer electrolytes to produce solid-state fully integrated devices where the PV device can directly inject charge into an on-board supercapacitor that can be separately discharged under dark conditions with a Coulombic efficiency of 84%. In a similar manner, we further demonstrate that surface engineered silicon materials can be utilized to replace Pt counterelectrodes in conventional DSSC energy conversion devices. As the silicon counterelectrodes rely strictly on surface Faradaic chemical reactions with the electrolyte on one side of the wafer electrode, we demonstrate double-sided processing of electrodes that enables dual-function of the material for simultaneous energy storage and conversion, each on opposing sides. In both of these devices, we demonstrate the ability to produce an all-silicon coupled energy conversion and storage system through the common ability to convert unused silicon in solar cells into high power silicon-based supercapacitors. Beyond the proof-of-concept design and performance of this integrated solar-storage system, this talk will conclude with a brief discussion of the hurdles and challenges that we envision for this emerging area both from a fundamental and technological viewpoint.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Hybrid Integrated Silicon Microfluidic Platform for Fluorescence Based Biodetection.

PubMed

Chandrasekaran, Arvind; Acharya, Ashwin; You, Jian Liang; Soo, Kim Young; Packirisamy, Muthukumaran; Stiharu, Ion; Darveau, André

2007-09-11

The desideratum to develop a fully integrated Lab-on-a-chip device capable ofrapid specimen detection for high throughput in-situ biomedical diagnoses and Point-of-Care testing applications has called for the integration of some of the novel technologiessuch as the microfluidics, microphotonics, immunoproteomics and Micro ElectroMechanical Systems (MEMS). In the present work, a silicon based microfluidic device hasbeen developed for carrying out fluorescence based immunoassay. By hybrid attachment ofthe microfluidic device with a Spectrometer-on-chip, the feasibility of synthesizing anintegrated Lab-on-a-chip type device for fluorescence based biosensing has beendemonstrated. Biodetection using the microfluidic device has been carried out usingantigen sheep IgG and Alexafluor-647 tagged antibody particles and the experimentalresults prove that silicon is a compatible material for the present application given thevarious advantages it offers such as cost-effectiveness, ease of bulk microfabrication,superior surface affinity to biomolecules, ease of disposability of the device etc., and is thussuitable for fabricating Lab-on-a-chip type devices.

Alternative Solder Bond Packaging Approach for High-Voltage (HV) Pulsed Power Devices

DTIC Science & Technology

2016-09-01

DISTRIBUTION/AVAILABILITY STATEMENT Approved for public release; distribution unlimited. 13. SUPPLEMENTARY NOTES 14. ABSTRACT The silicon carbide...the pulse evaluation circuit used to evaluate a SiC SGTO device under extreme pulsed current switching conditions. 15. SUBJECT TERMS silicon carbide...development effort. We would also like to thank Dr Sei-Hyung Ryu and Dr Jon Zhang of Cree, Inc., for providing the silicon carbide “super” gate-turn

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Gu, Jian

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of Ṯhin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Silicon carbide semiconductor technology for high temperature and radiation environments

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.

1993-01-01

Viewgraphs on silicon carbide semiconductor technology and its potential for enabling electronic devices to function in high temperature and high radiation environments are presented. Topics covered include silicon carbide; sublimation growth of 6H-SiC boules; SiC chemical vapor deposition reaction system; 6H silicon carbide p-n junction diode; silicon carbide MOSFET; and silicon carbide JFET radiation response.

Silicon coupled with plasmon nanocavities generates bright visible hot luminescence

NASA Astrophysics Data System (ADS)

Cho, Chang-Hee; Aspetti, Carlos O.; Park, Joohee; Agarwal, Ritesh

2013-04-01

To address the limitations in device speed and performance in silicon-based electronics, there have been extensive studies on silicon optoelectronics with a view to achieving ultrafast optical data processing. The biggest challenge has been to develop an efficient silicon-based light source, because the indirect bandgap of silicon gives rise to extremely low emission efficiencies. Although light emission in quantum-confined silicon at sub-10 nm length scales has been demonstrated, there are difficulties in integrating quantum structures with conventional electronics. It is desirable to develop new concepts to obtain emission from silicon at length scales compatible with current electronic devices (20-100 nm), which therefore do not utilize quantum-confinement effects. Here, we demonstrate an entirely new method to achieve bright visible light emission in `bulk-sized' silicon coupled with plasmon nanocavities at room temperature, from non-thermalized carrier recombination. The highly enhanced emission (internal quantum efficiency of >1%) in plasmonic silicon, together with its size compatibility with current silicon electronics, provides new avenues for developing monolithically integrated light sources on conventional microchips.

Self-organized, effective medium black silicon antireflection structures for silicon optics in the mid-infrared

NASA Astrophysics Data System (ADS)

Steglich, Martin; Käsebier, Thomas; Kley, Ernst-Bernhard; Tünnermann, Andreas

2016-09-01

Thanks to its high quality and low cost, silicon is the material of choice for optical devices operating in the mid-infrared (MIR; 2 μm to 6 μm wavelength). Unfortunately in this spectral region, the refractive index is comparably high (about 3.5) and leads to severe reflection losses of about 30% per interface. In this work, we demonstrate that self-organized, statistical Black Silicon structures, fabricated by Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE), can be used to effectively suppress interface reflection. More importantly, it is shown that antireflection can be achieved in an image-preserving, non-scattering way. This enables Black Silicon antireflection structures (ARS) for imaging applications in the MIR. It is demonstrated that specular transmittances of 97% can be easily achieved on both flat and curved substrates, e.g. lenses. Moreover, by a combined optical and morphological analysis of a multitude of different Black Silicon ARS, an effective medium criterion for the examined structures is derived that can also be used as a design rule for maximizing sample transmittance in a desired wavelength range. In addition, we show that the mechanical durability of the structures can be greatly enhanced by coating with hard dielectric materials like diamond-like carbon (DLC), hence enabling practical applications. Finally, the distinct advantages of statistical Black Silicon ARS over conventional AR layer stacks are discussed: simple applicability to topological substrates, absence of thermal stress and cost-effectiveness.

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Growth of High-Quality GaAs on Ge by Controlling the Thickness and Growth Temperature of Buffer Layer

NASA Astrophysics Data System (ADS)

Zhou, Xu-Liang; Pan, Jiao-Qing; Yu, Hong-Yan; Li, Shi-Yan; Wang, Bao-Jun; Bian, Jing; Wang, Wei

2014-12-01

High-quality GaAs thin films grown on miscut Ge substrates are crucial for GaAs-based devices on silicon. We investigate the effect of different thicknesses and temperatures of GaAs buffer layers on the crystal quality and surface morphology of GaAs on Ge by metal-organic chemical vapor deposition. Through high resolution x-ray diffraction measurements, it is demonstrated that the full width at half maximum for the GaAs epilayer (Ge substrate) peak could achieve 19.3 (11.0) arcsec. The value of etch pit density could be 4×104 cm-2. At the same time, GaAs surfaces with no pyramid-shaped pits are obtained when the buffer layer growth temperature is lower than 360°C, due to effective inhibition of initial nucleation at terraces of the Ge surface. In addition, it is shown that large island formation at the initial stage of epitaxial growth is a significant factor for the final rough surface and that this initial stage should be carefully controlled when a device quality GaAs surface is desired.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Relative Fluxes of Primary Particles in B-C-N-O Group from the ATIC Experiment (Science Flight)

NASA Technical Reports Server (NTRS)

Panov, A. D.; Adams, J. H., Jr.; Ahn, H. S.; Bashindzhagyan, G. L.; Chang, J.; Christl, M.; Fazely, A. R.; Ganel, O.; Gunashingha, R. M.; Guzik, T. G.;

Method for forming p-n junctions and solar-cells by laser-beam processing

DOEpatents

Narayan, Jagdish; Young, Rosa T.

1979-01-01

This invention is an improved method for preparing p-n junction devices, such as diodes and solar cells. High-quality junctions are prepared by effecting laser-diffusion of a selected dopant into silicon by means of laser pulses having a wavelength of from about 0.3 to 1.1 .mu.m, an energy area density of from about 1.0 to 2.0 J/cm.sup.2, and a duration of from about 20 to 60 nanoseconds. Initially, the dopant is deposited on the silicon as a superficial layer, preferably one having a thickness in the range of from about 50 to 100 A. Depending on the application, the values for the above-mentioned pulse parameters are selected to produce melting of the silicon to depths in the range from about 1000 A to 1 .mu.m. The invention has been used to produce solar cells having a one-sun conversion efficiency of 10.6%, these cells having no antireflective coating or back-surface fields.

Conformal coating of amorphous silicon and germanium by high pressure chemical vapor deposition for photovoltaic fabrics

NASA Astrophysics Data System (ADS)

Ji, Xiaoyu; Cheng, Hiu Yan; Grede, Alex J.; Molina, Alex; Talreja, Disha; Mohney, Suzanne E.; Giebink, Noel C.; Badding, John V.; Gopalan, Venkatraman

2018-04-01

Conformally coating textured, high surface area substrates with high quality semiconductors is challenging. Here, we show that a high pressure chemical vapor deposition process can be employed to conformally coat the individual fibers of several types of flexible fabrics (cotton, carbon, steel) with electronically or optoelectronically active materials. The high pressure (˜30 MPa) significantly increases the deposition rate at low temperatures. As a result, it becomes possible to deposit technologically important hydrogenated amorphous silicon (a-Si:H) from silane by a simple and very practical pyrolysis process without the use of plasma, photochemical, hot-wire, or other forms of activation. By confining gas phase reactions in microscale reactors, we show that the formation of undesired particles is inhibited within the microscale spaces between the individual wires in the fabric structures. Such a conformal coating approach enables the direct fabrication of hydrogenated amorphous silicon-based Schottky junction devices on a stainless steel fabric functioning as a solar fabric.

A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

NASA Astrophysics Data System (ADS)

Bartsch, Sebastian T.; Rusu, A.; Ionescu, Adrian M.

2012-06-01

Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption.

Passively aligned multichannel fiber-pigtailing of planar integrated optical waveguides

NASA Astrophysics Data System (ADS)

Kremmel, Johannes; Lamprecht, Tobias; Crameri, Nino; Michler, Markus

2017-02-01

A silicon device to simplify the coupling of multiple single-mode fibers to embedded single-mode waveguides has been developed. The silicon device features alignment structures that enable a passive alignment of fibers to integrated waveguides. For passive alignment, precisely machined V-grooves on a silicon device are used and the planar lightwave circuit board features high-precision structures acting as a mechanical stop. The approach has been tested for up to eight fiber-to-waveguide connections. The alignment approach, the design, and the fabrication of the silicon device as well as the assembly process are presented. The characterization of the fiber-to-waveguide link reveals total coupling losses of (0.45±0.20 dB) per coupling interface, which is significantly lower than the values reported in earlier works. Subsequent climate tests reveal that the coupling losses remain stable during thermal cycling but increases significantly during an 85°C/85 Rh-test. All applied fabrication and bonding steps have been performed using standard MOEMS fabrication and packaging processes.

A computational workflow for designing silicon donor qubits

DOE PAGES

Humble, Travis S.; Ericson, M. Nance; Jakowski, Jacek; ...

2016-09-19

Developing devices that can reliably and accurately demonstrate the principles of superposition and entanglement is an on-going challenge for the quantum computing community. Modeling and simulation offer attractive means of testing early device designs and establishing expectations for operational performance. However, the complex integrated material systems required by quantum device designs are not captured by any single existing computational modeling method. We examine the development and analysis of a multi-staged computational workflow that can be used to design and characterize silicon donor qubit systems with modeling and simulation. Our approach integrates quantum chemistry calculations with electrostatic field solvers to performmore » detailed simulations of a phosphorus dopant in silicon. We show how atomistic details can be synthesized into an operational model for the logical gates that define quantum computation in this particular technology. In conclusion, the resulting computational workflow realizes a design tool for silicon donor qubits that can help verify and validate current and near-term experimental devices.« less

The immediate use of a silicone sheet wound closure device in scar reduction and prevention.

PubMed

Parry, James R; Stupak, Howard D; Johnson, Calvin M

2016-02-01

Silicone has been used successfully postoperatively in the prevention of hypertrophic and other types of adverse scars. The Silicone Suture Plate (SSP) is a new, minimally invasive, sterile wound closure device that is applied intraoperatively to prevent adverse scarring. The SSP device permits immediate application of silicone while concurrently allowing for wound-edge tension redistribution. In this prospective, controlled, single-blinded clinical study, 8 consecutive patients undergoing deep-plane rhytidectomy were selected. SSP devices were placed on the patients' posterior rhytidectomy hairline incision; the mirror-image control site underwent standard suturing techniques. Three blinded, independent raters assessed the treatment and control sides at 6-week and 4-month follow-up visits, using the Objective Scar Assessment Scale (OSAS), a validated scar assessment tool. The 6-week OSAS scores revealed an 18.4% improvement on the side with the SSP device (13.3) when compared to the control side (16.3). The 4-month OSAS scores showed a 27.3% improvement on the treatment side from 12.7 (control) to 9.2 (SSP). These OSAS results were found to be statistically significant when taken as an aggregate of the observers' scores, but not when observers' scores were measured individually (p < 0.05). In our series of patients, we showed promising results with the use of the SSP device. Early silicone application and tissue tension distribution contributed to an overall more aesthetically pleasing scar compared to those seen with standard suturing techniques, although more testing is required.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Robustness up to 400°C of the passivation of c-Si by p-type a-Si:H thanks to ion implantation

NASA Astrophysics Data System (ADS)

Defresne, A.; Plantevin, O.; Roca i Cabarrocas, Pere

2016-12-01

Heterojunction solar cells based on crystalline silicon (c-Si) passivated by hydrogenated amorphous silicon (a-Si:H) thin films are one of the most promising architectures for high energy conversion efficiency. Indeed, a-Si:H thin films can passivate both p-type and n-type wafers and can be deposited at low temperature (<200°C) using PECVD. However, such passivation layers, in particular p-type a-Si:H, show a dramatic degradation in passivation quality above 200°C. Yet, annealing at 300 - 400°C the TCO layer and metallic contacts is highly desirable to reduce the contact resistance as well as the TCO optical absorption. In this work, we show that as expected, ion implantation (5 - 30 keV) introduces defects at the c-Si/a-Si:H interface which strongly degrade the effective lifetime, down to a few micro-seconds. However, the passivation quality can be restored and lifetime values can be improved up to 2 ms over the initial value with annealing. We show here that effective lifetimes above 1 ms can be maintained up to 380°C, opening up the possibility for higher process temperatures in silicon heterojunction device fabrication.

Method of fabricating germanium and gallium arsenide devices

NASA Technical Reports Server (NTRS)

Jhabvala, Murzban (Inventor)

1990-01-01

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

High-temperature electronics

NASA Technical Reports Server (NTRS)

Seng, Gary T.

1987-01-01

In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

A Study on Organic-Metal Halide Perovskite Film Morphology, Interfacial Layers, Tandem Applications, and Encapsulation

NASA Astrophysics Data System (ADS)

Fisher, Dallas A.

Organic-metal halide perovskites have brought about a new wave of research in the photovoltaic community due to their ideally suited optical and electronic parameters. In less than a decade, perovskite solar cell performance has skyrocketed to unprecedented efficiencies with numerous reported methodologies. Perovskites face many challenges with high-quality film morphology, interfacial layers, and long-term stability. In this work, these active areas are explored through a combination of studies. First, the importance of perovskite film precursor ratios is explored with an in-depth study of carrier lifetime and solvent-grain effects. It was found that excess lead iodide precursor greatly improves the film morphology by reducing pinholes in the solar absorber. Dimethyl sulfoxide (DMSO) solvent was found to mend grains, as well as improve carrier lifetime and device performance, possibly by passivation of grain boundary traps. Second, applications of perovskite with tandem cells is investigated, with an emphasis for silicon devices. Perovskites can easily be integrated with silicon, which already has strong market presence. Additionally, both materials' bandgaps are ideally suited for maximum tandem efficiency. The silicon/perovskite tandem device structure necessitated the optimization of inverted (p-i-n) structure devices. PEDOT:PSS, copper oxide, and nickel oxide p-type layers were explored through a combination of photoluminescent, chemical reactivity, and solar simulation results. Results were hindered due to resistive ITO and rough silicon substrates, but tandem devices displayed Voc indicative of proper monolithic performance. Third, replacement of titanium dioxide n-type layer with iron oxide (Fe 2O3, common rust) was studied. Iron oxide experiences less ultraviolet instability than that of titanium dioxide under solar illumination. It was found that current density slightly decreased due to parasitic absorption from the rust, but that open circuit voltage decreased drastically due to poor band alignment. Fe2O3 appears to be better suited to a narrower band gap material than methylammonium lead iodide perovskite. Finally, encapsulation of perovskite devices with epoxy coatings is explored as a method to improve long-term stability. Perovskites are sensitive to a variety of conditions, but most importantly water and polar molecules. Encapsulants act as a moisture/oxygen barrier, but also prevent outgassing of the organic components. Three epoxies were tested in high heat and high humidity conditions. Important factors in the curing process were uncovered such as the sensitivity of UV-epoxies to amine functional groups found in common p-type dopants and perovskite layers. Moisture ingress was the failure point for high-humidity/heat devices which was confirmed through conversion to yellow lead iodide. A revised device fabrication method is proposed to reduce moisture ingress for future experiments.

Vacuum Microelectronic Field Emission Array Devices for Microwave Amplification.

NASA Astrophysics Data System (ADS)

Mancusi, Joseph Edward

This dissertation presents the design, analysis, and measurement of vacuum microelectronic devices which use field emission to extract an electron current from arrays of silicon cones. The arrays of regularly-spaced silicon cones, the field emission cathodes or emitters, are fabricated with an integrated gate electrode which controls the electric field at the tip of the cone, and thus the electron current. An anode or collector electrode is placed above the array to collect the emission current. These arrays, which are fabricated in a standard silicon processing facility, are developed for use as high power microwave amplifiers. Field emission has been studied extensively since it was first characterized in 1928, however due to the large electric fields required practical field emission devices are difficult to make. With the development of the semiconductor industry came the development of fabrication equipment and techniques which allow for the manufacture of the precision micron-scale structures necessary for practical field emission devices. The active region of a field emission device is a vacuum, therefore the electron travel is ballistic. This analysis of field emission devices includes electric field and electron emission modeling, development of a device equivalent circuit, analysis of the parameters in the equivalent circuit, and device testing. Variations in device structure are taken into account using a statistical model based upon device measurements. Measurements of silicon field emitter arrays at DC and RF are presented and analyzed. In this dissertation, the equivalent circuit is developed from the analysis of the device structure. The circuit parameters are calculated from geometrical considerations and material properties, or are determined from device measurements. It is necessary to include the emitter resistance in the equivalent circuit model since relatively high resistivity silicon wafers are used. As is demonstrated, the circuit model accurately predicts the magnitude of the emission current at a number of typical bias current levels when the device is operating at frequencies within the range of 10 MHz to 1 GHz. At low frequencies and at high frequencies within this range, certain parameters are negligible, and simplifications may be made in the equivalent circuit model.

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

PubMed

Horst, Folkert; Green, William M J; Assefa, Solomon; Shank, Steven M; Vlasov, Yurii A; Offrein, Bert Jan

2013-05-20

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.

A Silicon Nanocrystal Schottky Junction Solar Cell produced from Colloidal Silicon Nanocrystals

PubMed Central

2010-01-01

Solution-processed semiconductors are seen as a promising route to reducing the cost of the photovoltaic device manufacture. We are reporting a single-layer Schottky photovoltaic device that was fabricated by spin-coating intrinsic silicon nanocrystals (Si NCs) from colloidal suspension. The thin-film formation process was based on Si NCs without any ligand attachment, exchange, or removal reactions. The Schottky junction device showed a photovoltaic response with a power conversion efficiency of 0.02%, a fill factor of 0.26, short circuit-current density of 0.148 mA/cm2, and open-circuit voltage of 0.51 V. PMID:20676200

Miniature spectrometer and beam splitter for an optical coherence tomography on a silicon chip.

PubMed

Akca, B I; Považay, B; Alex, A; Wörhoff, K; de Ridder, R M; Drexler, W; Pollnau, M

2013-07-15

Optical coherence tomography (OCT) has enabled clinical applications that revolutionized in vivo medical diagnostics. Nevertheless, its current limitations owing to cost, size, complexity, and the need for accurate alignment must be overcome by radically novel approaches. Exploiting integrated optics, we assemble the central components of a spectral-domain OCT system on a silicon chip. The spectrometer comprises an arrayed-waveguide grating with 136-nm free spectral range and 0.21-nm wavelength resolution. The beam splitter is realized by a non-uniform adiabatic coupler with its 3-dB splitting ratio being nearly constant over 150 nm. With this device whose overall volume is 0.36 cm(3) we demonstrate high-quality in vivo imaging in human skin with 1.4-mm penetration depth, 7.5-µm axial resolution, and a signal-to-noise ratio of 74 dB. Considering the reasonable performance of this early OCT on-a-chip system and the anticipated improvements in this technology, a completely different range of devices and new fields of applications may become feasible.

Ultra-thin distributed Bragg reflectors via stacked single-crystal silicon nanomembranes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Minkyu; Seo, Jung-Hun; Lee, Jaeseong

2015-05-04

In this paper, we report ultra-thin distributed Bragg reflectors (DBRs) via stacked single-crystal silicon (Si) nanomembranes (NMs). Mesh hole-free single-crystal Si NMs were released from a Si-on-insulator substrate and transferred to quartz and Si substrates. Thermal oxidation was applied to the transferred Si NM to form high-quality SiO{sub 2} and thus a Si/SiO{sub 2} pair with uniform and precisely controlled thicknesses. The Si/SiO{sub 2} layers, as smooth as epitaxial grown layers, minimize scattering loss at the interface and in between the layers. As a result, a reflection of 99.8% at the wavelength range from 1350 nm to 1650 nm can be measuredmore » from a 2.5-pair DBR on a quartz substrate and 3-pair DBR on a Si substrate with thickness of 0.87 μm and 1.14 μm, respectively. The high reflection, ultra-thin DBRs developed here, which can be applied to almost any devices and materials, holds potential for application in high performance optoelectronic devices and photonics applications.« less

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

NASA Technical Reports Server (NTRS)

Speer, Kevin M.

2004-01-01

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Vacuum-free laminated top electrode with conductive tapes for scalable manufacturing of efficient perovskite solar cells

DOE PAGES

Shao, Yuchuan; Wang, Qi; Dong, Qingfeng; ...

2015-06-25

The efficiency of organometal trihalide perovskites (OTP) solar cells have reached that parity of single crystal silicon, and its nature abundant raw material and solution-process capability promise a bright future for commercialization. However, the vacuum based techniques for metal electrode deposition and additional encapsulation layer increase the cost of the perovskite solar cells dramatically and impede their commercialization process. Here, we report a vacuum-free low temperature lamination technique to fabricate the top electrode by commercial conductive tapes (C-tape). The simple fabrication method yields good quality contact and high efficiency device of 12.7%. The C-tapes also encapsulated the devices effectively, resultingmore » in greatly improved device stability. As a result, the combination of lamination of electrodes and encapsulation layers into a single step significantly reduce the cost of device fabrication.« less

Silicon Nitride Deposition for Flexible Organic Electronic Devices by VHF (162 MHz)-PECVD Using a Multi-Tile Push-Pull Plasma Source.

PubMed

Kim, Ki Seok; Kim, Ki Hyun; Ji, You Jin; Park, Jin Woo; Shin, Jae Hee; Ellingboe, Albert Rogers; Yeom, Geun Young

2017-10-19

Depositing a barrier film for moisture protection without damage at a low temperature is one of the most important steps for organic-based electronic devices. In this study, the authors investigated depositing thin, high-quality SiN x film on organic-based electronic devices, specifically, very high-frequency (162 MHz) plasma-enhanced chemical vapor deposition (VHF-PECVD) using a multi-tile push-pull plasma source with a gas mixture of NH 3 /SiH 4 at a low temperature of 80 °C. The thin deposited SiN x film exhibited excellent properties in the stoichiometry, chemical bonding, stress, and step coverage. Thin film quality and plasma damage were investigated by the water vapor transmission rate (WVTR) and by electrical characteristics of organic light-emitting diode (OLED) devices deposited with SiN x , respectively. The thin deposited SiN x film exhibited a low WVTR of 4.39 × 10 -4  g (m 2 · day) -1 for a single thin (430 nm thick) film SiN x and the electrical characteristics of OLED devices before and after the thin SiN x film deposition on the devices did not change, which indicated no electrical damage during the deposition of SiN x on the OLED device.

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

PubMed Central

Marrs, Michael A.; Raupp, Gregory B.

2016-01-01

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm2 and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate. PMID:27472329

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

PubMed

Marrs, Michael A; Raupp, Gregory B

2016-07-26

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm² and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Controlled assembly of graphene-capped nickel, cobalt and iron silicides

PubMed Central

Vilkov, O.; Fedorov, A.; Usachov, D.; Yashina, L. V.; Generalov, A. V.; Borygina, K.; Verbitskiy, N. I.; Grüneis, A.; Vyalikh, D. V.

2013-01-01

The unique properties of graphene have raised high expectations regarding its application in carbon-based nanoscale devices that could complement or replace traditional silicon technology. This gave rise to the vast amount of researches on how to fabricate high-quality graphene and graphene nanocomposites that is currently going on. Here we show that graphene can be successfully integrated with the established metal-silicide technology. Starting from thin monocrystalline films of nickel, cobalt and iron, we were able to form metal silicides of high quality with a variety of stoichiometries under a Chemical Vapor Deposition grown graphene layer. These graphene-capped silicides are reliably protected against oxidation and can cover a wide range of electronic materials/device applications. Most importantly, the coupling between the graphene layer and the silicides is rather weak and the properties of quasi-freestanding graphene are widely preserved. PMID:23835625

Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits

DTIC Science & Technology

1995-08-01

common dimensions are given in Table 1. Almost all of the device power is dissipated in the channel. The electri- cally insulating implanted layer...data. Region or Component substrate Material SOI implanted insulating layers single-crystal silicon, 3 x 1015 boron atoms cm -3 Thermal... implanted silicon-dioxide layer in SOI wafers. The data for each device for varying powers fall near a line originating at P = 0 and T0 = 303 K

Wave-aberration control with a liquid crystal on silicon (LCOS) spatial phase modulator.

PubMed

Fernández, Enrique J; Prieto, Pedro M; Artal, Pablo

2009-06-22

Liquid crystal on Silicon (LCOS) spatial phase modulators offer enhanced possibilities for adaptive optics applications in terms of response velocity and fidelity. Unlike deformable mirrors, they present a capability for reproducing discontinuous phase profiles. This ability also allows an increase in the effective stroke of the device by means of phase wrapping. The latter is only limited by the diffraction related effects that become noticeable as the number of phase cycles increase. In this work we estimated the ranges of generation of the Zernike polynomials as a means for characterizing the performance of the device. Sets of images systematically degraded with the different Zernike polynomials generated using a LCOS phase modulator have been recorded and compared with their theoretical digital counterparts. For each Zernike mode, we have found that image degradation reaches a limit for a certain coefficient value; further increase in the aberration amount has no additional effect in image quality. This behavior is attributed to the intensification of the 0-order diffraction. These results have allowed determining the usable limits of the phase modulator virtually free from diffraction artifacts. The results are particularly important for visual simulation and ophthalmic testing applications, although they are equally interesting for any adaptive optics application with liquid crystal based devices.

Spike-Timing Dependent Plasticity in Unipolar Silicon Oxide RRAM Devices

PubMed Central

Zarudnyi, Konstantin; Mehonic, Adnan; Montesi, Luca; Buckwell, Mark; Hudziak, Stephen; Kenyon, Anthony J.

2018-01-01

Resistance switching, or Resistive RAM (RRAM) devices show considerable potential for application in hardware spiking neural networks (neuro-inspired computing) by mimicking some of the behavior of biological synapses, and hence enabling non-von Neumann computer architectures. Spike-timing dependent plasticity (STDP) is one such behavior, and one example of several classes of plasticity that are being examined with the aim of finding suitable algorithms for application in many computing tasks such as coincidence detection, classification and image recognition. In previous work we have demonstrated that the neuromorphic capabilities of silicon-rich silicon oxide (SiOx) resistance switching devices extend beyond plasticity to include thresholding, spiking, and integration. We previously demonstrated such behaviors in devices operated in the unipolar mode, opening up the question of whether we could add plasticity to the list of features exhibited by our devices. Here we demonstrate clear STDP in unipolar devices. Significantly, we show that the response of our devices is broadly similar to that of biological synapses. This work further reinforces the potential of simple two-terminal RRAM devices to mimic neuronal functionality in hardware spiking neural networks. PMID:29472837

Workshop proceedings: Photovoltaic conversion of solar energy for terrestrial applications. Volume 2: Invited papers

NASA Technical Reports Server (NTRS)

1973-01-01

A photovoltaic device development plan is reported that considers technological as well as economical aspects of single crystal silicon, polycrystal silicon, cadmium sulfide/copper sulfide thin films, as well as other materials and devices for solar cell energy conversion systems.

Storage Reliability of Missile Materiel Program. Storage Reliability Analysis Summary Report. Volume 1. Electrical and Electronic Devices

DTIC Science & Technology

1978-01-01

silicon nitride seals the devices from sodium and since the platinum silicide and titanium metals also offer very low mobility to the alkaline ions, the...of bipolar devices. These materials act as gettering agents for sodium ions, thus making the contamination far less mobile. The stability of the...parameter instability. Silicon nitride has been shown to be an effective barrier to sodium migration. In Beam Lead Sealed Junction (BLSJ) devices, the

Silicon based multilayer photoelectrodes for photoelectrolysis of water to produce hydrogen from the sun

NASA Astrophysics Data System (ADS)

Faruque, Faisal

The main objective of this work is to study different materials for the direct photosynthesis of hydrogen from water. A variety of photocatalysts such as titanium dioxide, titanium oxy-nitride, silicon carbide, and gallium nitride are being investigated by others for the clean production of hydrogen for fuel cells and hydrogen economy. Our approach was to deposit suitable metallic regions on photocatalyst nanoparticles to direct the efficient synthesis of hydrogen to a particular site for convenient collection. We studied different electrode metals such as gold, platinum, titanium, palladium, and tungsten. We also studied different solar cell materials such as silicon (p- and n-types), silicon carbide and titanium dioxide semiconductors in order to efficiently generate electrons under illumination. We introduced a novel silicon-based multilayer photosynthesis device to take advantage of suitable properties of silicon and tungsten to efficiently produce hydrogen. The device consisted of a silicon (0.5mm) substrate, a deposited atomic layer of Al2O 3 (1nm), a doped polysilicon (0.1microm), and finally a tungsten nanoporous (5-10nm) layer acting as an interface electrode with water. The Al2O 3 layer was introduced to reduce leakage current and to prevent the spreading of the diffused p-n junction layer between the silicon and doped polysilicon layers. The surface of the photoelectrode was coated with nanotextured tungsten nanopores (TNP), which increased the surface area of the electrodes to the electrolyte, assisting in electron-hole mobility, and acting as a photocatalyst. The reported device exhibited a fill factor (%FF) of 27.22% and solar-to-hydrogen conversion efficiency of 0.03174%. This thesis describes the structures of the device, and offers a characterization and comparison between different photoelectrodes.

Crystal growth for high-efficiency silicon solar cells workshop: Summary

NASA Technical Reports Server (NTRS)

Dumas, K. A.

1985-01-01

The state of the art in the growth of silicon crystals for high-efficiency solar cells are reviewed, sheet requirements are defined, and furture areas of research are identified. Silicon sheet material characteristics that limit cell efficiencies and yields were described as well as the criteria for the ideal sheet-growth method. The device engineers wish list to the material engineer included: silicon sheet with long minority carrier lifetime that is uniform throughout the sheet, and which doesn't change during processing; and sheet material that stays flat throughout device processing, has uniform good mechanical strength, and is low cost. Impurities in silicon solar cells depreciate cell performance by reducing diffusion length and degrading junctions. The impurity behavior, degradation mechanisms, and variations in degradation threshold with diffusion length for silicon solar cells were described.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

Silicon nanocrystal inks, films, and methods

DOEpatents

Wheeler, Lance Michael; Kortshagen, Uwe Richard

2015-09-01

Silicon nanocrystal inks and films, and methods of making and using silicon nanocrystal inks and films, are disclosed herein. In certain embodiments the nanocrystal inks and films include halide-terminated (e.g., chloride-terminated) and/or halide and hydrogen-terminated nanocrystals of silicon or alloys thereof. Silicon nanocrystal inks and films can be used, for example, to prepare semiconductor devices.

A study on measuring occlusal contact area using silicone impression materials: an application of this method to the bite force measurement system using the pressure-sensitive sheet.

PubMed

Ando, Katsuya; Kurosawa, Masahiro; Fuwa, Yuji; Kondo, Takamasa; Goto, Shigemi

2007-11-01

The aim of this study was to establish an objective and quantitative method of measuring occlusal contact areas. To this end, bite records were taken with a silicone impression material and a light transmission device was used to read the silicone impression material. To examine the effectiveness of this novel method, the occlusal contact area of the silicone impression material and its thickness limit of readable range were measured. Results of this study suggested that easy and highly accurate measurements of occlusal contact area could be obtained by selecting an optimal applied voltage of the light transmission device and an appropriate color of the silicone impression material.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

High-Bandgap Silicon Nanocrystal Solar Cells: Device Fabrication, Characterization, and Modeling

NASA Astrophysics Data System (ADS)

Löper, Philipp; Canino, Mariaconcetta; Schnabel, Manuel; Summonte, Caterina; Janz, Stefan; Zacharias, Margit

Silicon nanocrystals (Si NCs) embedded in Si-based dielectrics provide a Si-based high-bandgap material (1.7 eV) and enable the construction of crystalline Si tandem solar cells. This chapter focusses on Si NC embedded in silicon carbide, because silicon carbide offers electrical conduction through the matrix material. The material development is reviewed, and optical modeling is introduced as a powerful method to monitor the four material components, amorphous and crystalline silicon as well as amorphous and crystalline silicon carbide. In the second part of this chapter, recent device developments for the photovoltaic characterization of Si NCs are examined. The controlled growth of Si NCs involves high-temperature annealing which deteriorates the properties of any previously established selective contacts. A membrane-based device is presented to overcome these limitations. In this approach, the formation of both selective contacts is carried out after high-temperature annealing and is therefore not affected by the latter. We examine p-i-n solar cells with an intrinsic region made of Si NCs embedded in silicon carbide. Device failure due to damaged insulation layers is analyzed by light beam-induced current measurements. An optical model of the device is presented for improving the cell current. A characterization scheme for Si NC p-i-n solar cells is presented which aims at determining the fundamental transport and recombination properties, i.e., the effective mobility lifetime product, of the nanocrystal layer at device level. For this means, an illumination-dependent analysis of Si NC p-i-n solar cells is carried out within the framework of the constant field approximation. The analysis builds on an optical device model, which is used to assess the photogenerated current in each of the device layers. Illumination-dependent current-voltage curves are modelled with a voltage-dependent current collection function with only two free parameters, and excellent agreement is found between theory and experiment. An effective mobility lifetime product of 10-10 cm2/V is derived and confirmed independently from an alternative method. The procedure discussed in this chapter is proposed as a characterization scheme for further material development, providing an optimization parameter (the effective mobility lifetime product) relevant for the photovoltaic performance of Si NC films.

Identifying suitable substrates for high-quality graphene-based heterostructures

NASA Astrophysics Data System (ADS)

Banszerus, L.; Janssen, H.; Otto, M.; Epping, A.; Taniguchi, T.; Watanabe, K.; Beschoten, B.; Neumaier, D.; Stampfer, C.

2017-06-01

We report on a scanning confocal Raman spectroscopy study investigating the strain-uniformity and the overall strain and doping of high-quality chemical vapour deposited (CVD) graphene-based heterostuctures on a large number of different substrate materials, including hexagonal boron nitride (hBN), transition metal dichalcogenides, silicon, different oxides and nitrides, as well as polymers. By applying a hBN-assisted, contamination free, dry transfer process for CVD graphene, high-quality heterostructures with low doping densities and low strain variations are assembled. The Raman spectra of these pristine heterostructures are sensitive to substrate-induced doping and strain variations and are thus used to probe the suitability of the substrate material for potential high-quality graphene devices. We find that the flatness of the substrate material is a key figure for gaining, or preserving high-quality graphene.

Composition Comprising Silicon Carbide

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2012-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Progress in silicon carbide semiconductor technology

NASA Technical Reports Server (NTRS)

Powell, J. A.; Neudeck, P. G.; Matus, L. G.; Petit, J. B.

1992-01-01

Silicon carbide semiconductor technology has been advancing rapidly over the last several years. Advances have been made in boule growth, thin film growth, and device fabrication. This paper wi11 review reasons for the renewed interest in SiC, and will review recent developments in both crystal growth and device fabrication.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, D.R.

1988-04-20

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon.

PubMed

Ben Slama, Sonia; Hajji, Messaoud; Ezzaouia, Hatem

2012-08-17

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon

PubMed Central

2012-01-01

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications. PMID:22901341

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Top-Down Nanofabrication and Characterization of 20 nm Silicon Nanowires for Biosensing Applications

PubMed Central

M. N, M. Nuzaihan; Hashim, U.; Md Arshad, M. K.; Ruslinda, A. Rahim; Rahman, S. F. A.; Fathil, M. F. M.; Ismail, Mohd. H.

2016-01-01

A top-down nanofabrication approach is used to develop silicon nanowires from silicon-on-insulator (SOI) wafers and involves direct-write electron beam lithography (EBL), inductively coupled plasma-reactive ion etching (ICP-RIE) and a size reduction process. To achieve nanometer scale size, the crucial factors contributing to the EBL and size reduction processes are highlighted. The resulting silicon nanowires, which are 20 nm in width and 30 nm in height (with a triangular shape) and have a straight structure over the length of 400 μm, are fabricated precisely at the designed location on the device. The device is applied in biomolecule detection based on the changes in drain current (Ids), electrical resistance and conductance of the silicon nanowires upon hybridization to complementary target deoxyribonucleic acid (DNA). In this context, the scaled-down device exhibited superior performances in terms of good specificity and high sensitivity, with a limit of detection (LOD) of 10 fM, enables for efficient label-free, direct and higher-accuracy DNA molecules detection. Thus, this silicon nanowire can be used as an improved transducer and serves as novel biosensor for future biomedical diagnostic applications. PMID:27022732

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE PAGES

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine; ...

2016-08-01

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation ofmore » such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

DTIC Science & Technology

2016-08-19

in a dielectric matrix. This paper explores the electronic device applications of dense arrays of silicon nanowires that are embedded in Nanotechnology ... Nanotechnology 27 (2016) 295302 (11pp) doi:10.1088/0957-4484/27/29/295302 Original content from this work may be used under the terms of the Creative...compared 2 Nanotechnology 27 (2016) 295302 S A Guerrera and A I Akinwande to the device reported by Velasquez-Garcia et al, but it also reduces the

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Photovoltaic Device Including A Boron Doping Profile In An I-Type Layer

DOEpatents

Yang, Liyou

1993-10-26

A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.

Amorphous Silicon Based Neutron Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Liwei

2004-12-12

Various large-scale neutron sources already build or to be constructed, are important for materials research and life science research. For all these neutron sources, neutron detectors are very important aspect. However, there is a lack of a high-performance and low-cost neutron beam monitor that provides time and temporal resolution. The objective of this SBIR Phase I research, collaboratively performed by Midwest Optoelectronics, LLC (MWOE), the University of Toledo (UT) and Oak Ridge National Laboratory (ORNL), is to demonstrate the feasibility for amorphous silicon based neutron beam monitors that are pixilated, reliable, durable, fully packaged, and fabricated with high yield usingmore » low-cost method. During the Phase I effort, work as been focused in the following areas: 1) Deposition of high quality, low-defect-density, low-stress a-Si films using very high frequency plasma enhanced chemical vapor deposition (VHF PECVD) at high deposition rate and with low device shunting; 2) Fabrication of Si/SiO2/metal/p/i/n/metal/n/i/p/metal/SiO2/ device for the detection of alpha particles which are daughter particles of neutrons through appropriate nuclear reactions; and 3) Testing of various devices fabricated for alpha and neutron detection; As the main results: · High quality, low-defect-density, low-stress a-Si films have been successfully deposited using VHF PECVD on various low-cost substrates; · Various single-junction and double junction detector devices have been fabricated; · The detector devices fabricated have been systematically tested and analyzed. · Some of the fabricated devices are found to successfully detect alpha particles. Further research is required to bring this Phase I work beyond the feasibility demonstration toward the final prototype devices. The success of this project will lead to a high-performance, low-cost, X-Y pixilated neutron beam monitor that could be used in all of the neutron facilities worldwide. In addition, the technologies developed here could be used to develop X-ray and neutron monitors that could be used in the future for security checks at the airports and other critical facilities. The project would lead to devices that could significantly enhance the performance of multi-billion dollar neutron source facilities in the US and bring our nation to the forefront of neutron beam sciences and technologies which have enormous impact to materials, life science and military research and applications.« less

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2006-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2007-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Fabrication of transition metal-containing nanostructures via polymer templates for a multitude of applications

NASA Astrophysics Data System (ADS)

Lu, Jennifer Qing

Nanostructures such as carbon nanotubes and semiconducting nanowires offer great technological promise due to their remarkable properties. The lack of a rational synthesis method prevents fabricating these nanostructures with desirable and consistent properties at predefined locations for device applications. In this thesis, employing polymer templates, a variety of highly ordered catalytically active transition metal nanostructures, ranging from single metallic nanoparticles of Fe, Co, Ni, Au and bimetallic nanoparticles of Ni/Fe and Co/Mo to Fe-rich silicon oxide nanodomains with uniform and tunable size and spacing have been successfully synthesized. These nanostructures have been demonstrated to be excellent catalyst systems for the synthesis of carbon nanotube and silicon nanowire. High quality, small diameter carbon nanotubes and nanowires with narrow size distribution have been successfully attained. Because these catalytically active nanostructures are uniformly distributed and do not agglomerate at the growth temperatures, uniform, high density and high quality carbon nanotube mats have been obtained. Since this polymer template approach is fully compatible with conventional top-down photolithography, lithographically selective growth of carbon nanotubes on a surface or suspended carbon nanotubes across trenches have been produced by using existing semiconductor processing. We have also shown the feasibility of producing carbon nanotubes and silicon nanowires at predefined locations on a wafer format and established a wafer-level carbon nanotube based device fabrication process. The ability of the polymer template approach to control catalyst systems at the nano-, micro- and macro-scales paves a pathway for commercialization of these 1D nanostructure-enabled devices. Beside producing well-defined, highly ordered discrete catalytically active metal-containing nanostructures by the polymer template approach, Au and Ag nanotextured surfaces have also been attained by using a self-assembled ferrocenylsilane-based inorganic block copolymer template. These Au and Ag nanotextured surfaces exhibit different surface plasmon behavior than the nanotextured surface. Greatly enhanced and uniform Raman scattering have been observed on Ag nanotextured surfaces. Highly sensitive Au nanotextured surfaces suggest their potential application as sensing surfaces for SPR-based biodetection. This simple fabrication technique of producing inorganic nanostructures with adjustable properties such as size, spacing and composition offers great promise for both fundamental research and technological development.

Silicon Carbide Technology

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2006-01-01

Silicon carbide based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be widely realized in commercially available SiC devices, primarily owing to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and the well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high-temperature and high-power SiC electronics are identified.

Amorphous/crystalline silicon interface passivation: Ambient-temperature dependence and implications for solar cell performance

DOE PAGES

Seif, Johannes P.; Krishnamani, Gopal; Demaurex, Benedicte; ...

2015-03-02

Silicon heterojunction (SHJ) solar cells feature amorphous silicon passivation films, which enable very high voltages. We report how such passivation increases with operating temperature for amorphous silicon stacks involving doped layers and decreases for intrinsic-layer-only passivation. We discuss the implications of this phenomenon on the solar cell's temperature coefficient, which represents an important figure-of-merit for the energy yield of devices deployed in the field. We show evidence that both open-circuit voltage (Voc) and fill factor (FF) are affected by these variations in passivation and quantify these temperature-mediated effects, compared with those expected from standard diode equations. We confirm that devicesmore » with high Voc values at 25°C show better high-temperature performance. Thus, we also argue that the precise device architecture, such as the presence of charge-transport barriers, may affect the temperature-dependent device performance as well.« less

Hybrid Silicon Nanocrystal/Poly(3-hexylthiophene-2,5-diyl) Solar Cells from a Chlorinated Silicon Precursor

NASA Astrophysics Data System (ADS)

Ding, Yi; Gresback, Ryan; Yamada, Riku; Okazaki, Ken; Nozaki, Tomohiro

2013-11-01

Freestanding silicon nanocrystals (Si NCs) synthesized by a nonthermal plasma from silicon tetrachloride (SiCl4) were successfully employed in hybrid Si NC/poly(3-hexylthiophene-2,5-diyl) (P3HT) bulk-hetrojunction (BHJ) solar cells. The weight fraction of Si NCs in P3HT greatly influences device performance. As the weight fraction increases up to 50 wt %, short-circuit current dramatically increases, while open-circuit voltage (Voc) and fill factor (FF) do not change significantly. The improvement in device performance is attributed to both increased probability of exciton dissociation in P3HT and an enhancement in the light conversion of wavelengths where P3HT is a poor absorber. These results demonstrate an alternative approach to synthesizing Si NCs from SiCl4 instead of silane (SiH4) for optoelectronic devices.

Development of Si(1-x)Ge(x) technology for microwave sensing applications

NASA Technical Reports Server (NTRS)

Mena, Rafael A.; Taub, Susan R.; Alterovitz, Samuel A.; Young, Paul E.; Simons, Rainee N.; Rosenfeld, David

1993-01-01

The progress for the first year of the work done under the Director's Discretionary Fund (DDF) research project entitled, 'Development of Si(1-x)Ge(x) Technology for Microwave Sensing Applications.' This project includes basic material characterization studies of silicon-germanium (SiGe), device processing on both silicon (Si) and SiGe substrates, and microwave characterization of transmission lines on silicon substrates. The material characterization studies consisted of ellipsometric and magneto-transport measurements and theoretical calculations of the SiGe band-structure. The device fabrication efforts consisted of establishing SiGe device processing capabilities in the Lewis cleanroom. The characterization of microwave transmission lines included studying the losses of various coplanar transmission lines and the development of transitions on silicon. Each part of the project is discussed individually and the findings for each part are presented. Future directions are also discussed.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

NASA Astrophysics Data System (ADS)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Varying potential silicon carbide gas sensor

NASA Technical Reports Server (NTRS)

Shields, Virgil B. (Inventor); Ryan, Margaret A. (Inventor); Williams, Roger M. (Inventor)

1997-01-01

A hydrocarbon gas detection device operates by dissociating or electro-chemically oxidizing hydrocarbons adsorbed to a silicon carbide detection layer. Dissociation or oxidation are driven by a varying potential applied to the detection layer. Different hydrocarbon species undergo reaction at different applied potentials so that the device is able to discriminate among various hydrocarbon species. The device can operate at temperatures between 100.degree. C. and at least 650.degree. C., allowing hydrocarbon detection in hot exhaust gases. The dissociation reaction is detected either as a change in a capacitor or, preferably, as a change of current flow through an FET which incorporates the silicon carbide detection layers. The silicon carbide detection layer can be augmented with a pad of catalytic material which provides a signal without an applied potential. Comparisons between the catalytically produced signal and the varying potential produced signal may further help identify the hydrocarbon present.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Ion implantation reduces radiation sensitivity of metal oxide silicon /MOS/ devices

NASA Technical Reports Server (NTRS)

1971-01-01

Implanting nitrogen ions improves hardening of silicon oxides 30 percent to 60 percent against ionizing radiation effects. Process reduces sensitivity, but retains stability normally shown by interfaces between silicon and thermally grown oxides.

Amorphous silicon radiation detectors

DOEpatents

Street, Robert A.; Perez-Mendez, Victor; Kaplan, Selig N.

1992-01-01

Hydrogenated amorphous silicon radiation detector devices having enhanced signal are disclosed. Specifically provided are transversely oriented electrode layers and layered detector configurations of amorphous silicon, the structure of which allow high electric fields upon application of a bias thereby beneficially resulting in a reduction in noise from contact injection and an increase in signal including avalanche multiplication and gain of the signal produced by incoming high energy radiation. These enhanced radiation sensitive devices can be used as measuring and detection means for visible light, low energy photons and high energy ionizing particles such as electrons, x-rays, alpha particles, beta particles and gamma radiation. Particular utility of the device is disclosed for precision powder crystallography and biological identification.

Amorphous silicon radiation detectors

DOEpatents

Street, R.A.; Perez-Mendez, V.; Kaplan, S.N.

1992-11-17

Hydrogenated amorphous silicon radiation detector devices having enhanced signal are disclosed. Specifically provided are transversely oriented electrode layers and layered detector configurations of amorphous silicon, the structure of which allow high electric fields upon application of a bias thereby beneficially resulting in a reduction in noise from contact injection and an increase in signal including avalanche multiplication and gain of the signal produced by incoming high energy radiation. These enhanced radiation sensitive devices can be used as measuring and detection means for visible light, low energy photons and high energy ionizing particles such as electrons, x-rays, alpha particles, beta particles and gamma radiation. Particular utility of the device is disclosed for precision powder crystallography and biological identification. 13 figs.

Postfabrication Phase Error Correction of Silicon Photonic Circuits by Single Femtosecond Laser Pulses

DOE PAGES

Bachman, Daniel; Chen, Zhijiang; Wang, Christopher; ...

2016-11-29

Phase errors caused by fabrication variations in silicon photonic integrated circuits are an important problem, which negatively impacts device yield and performance. This study reports our recent progress in the development of a method for permanent, postfabrication phase error correction of silicon photonic circuits based on femtosecond laser irradiation. Using beam shaping technique, we achieve a 14-fold enhancement in the phase tuning resolution of the method with a Gaussian-shaped beam compared to a top-hat beam. The large improvement in the tuning resolution makes the femtosecond laser method potentially useful for very fine phase trimming of silicon photonic circuits. Finally, wemore » also show that femtosecond laser pulses can directly modify silicon photonic devices through a SiO 2 cladding layer, making it the only permanent post-fabrication method that can tune silicon photonic circuits protected by an oxide cladding.« less

Optical silicones for use in harsh operating environments

NASA Astrophysics Data System (ADS)

Riegler, Bill; Bruner, Stephen J.; Elgin, Randall

2004-12-01

The optics industry widely uses silcones for various fiber optic cable potting applications and light emitting diode protection. Optics manufacturers know traditional silicone elastomers, gels, thixotropic gels, and fluids not only perform extremely well in high temperature applications, but also offer refractive index matching so that silicones can transmit light with admirable efficiency. However, because environmental conditions may affect a material's performance over time, one must also consider the conditions the device operates in to ensure long-term reliability. External environments may include exposure to a combination of UV light and temperature, while other environments may expose devices to hydrocarbon based fuels. This paper will delve into the chemistry of silicones and functional groups that lend themselves to properties such as temperature, fuel, and radiation resistance to show shy silicone is the material of choice for optic applications under normally harmful forms of exposure. Data will be presented to examine silicone's performance in these environment.

Molecular Monolayers for Electrical Passivation and Functionalization of Silicon-Based Solar Energy Devices.

PubMed

Veerbeek, Janneke; Firet, Nienke J; Vijselaar, Wouter; Elbersen, Rick; Gardeniers, Han; Huskens, Jurriaan

2017-01-11

Silicon-based solar fuel devices require passivation for optimal performance yet at the same time need functionalization with (photo)catalysts for efficient solar fuel production. Here, we use molecular monolayers to enable electrical passivation and simultaneous functionalization of silicon-based solar cells. Organic monolayers were coupled to silicon surfaces by hydrosilylation in order to avoid an insulating silicon oxide layer at the surface. Monolayers of 1-tetradecyne were shown to passivate silicon micropillar-based solar cells with radial junctions, by which the efficiency increased from 8.7% to 9.9% for n + /p junctions and from 7.8% to 8.8% for p + /n junctions. This electrical passivation of the surface, most likely by removal of dangling bonds, is reflected in a higher shunt resistance in the J-V measurements. Monolayers of 1,8-nonadiyne were still reactive for click chemistry with a model catalyst, thus enabling simultaneous passivation and future catalyst coupling.

Silicon Sheet Quality is Improved By Meniscus Control

NASA Technical Reports Server (NTRS)

Yates, D. A.; Hatch, A. E.; Goldsmith, J. M.

1983-01-01

Better quality silicon crystals for solar cells are possible with instrument that monitors position of meniscus as sheet of solid silicon is drawn from melt. Using information on meniscus height, instrument generates feedback signal to control melt temperature. Automatic control ensures more uniform silicon sheets.

High Sensitivity, Low Power Nano Sensors and Devices for Chemical Sensing

NASA Technical Reports Server (NTRS)

Li, Jing; Powell, Dan; Getty, Stephanie; Lu, Yi-Jiang

2004-01-01

The chemical sensor market has been projected to grow to better than $40 billion dollars worldwide within the next 10 years. Some of the primary motivations to develop nanostructured chemical sensors are monitoring and control of environmental pollution; improved diagnostics for consumption; improvement in measurement precision and accuracy; and improved detection limits for Homeland security, battlefield environments, and process and quality control of industrial applications. In each of these applications, there is demand for sensitivity, selectivity and stability of environmental and biohazard detection and capture beyond what is currently commercially available. Nanotechnology offers the ability to work at the molecular level, atom by atom, to create large structures with fundamentally new molecular organization. It is essentially concerned with materials, devices, and systems whose structures and components exhibit novel and significantly improved physical, chemical and biological properties, phenomena, and process control due to their nanoscale size. One such nanotechnology-enabled chemical sensor has been developed at NASA Ames leveraging nanostructures, such as single walled carbon nanotubes (SWNTs) and metal oxide nanobelts or nanowires, as a sensing medium bridging a pair of interdigitated electrodes (IDE) realized through a silicon-based microfabrication and micromachining technique. The DE fingers are fabricated on a silicon substrate using standard photolithography and thin film metallization techniques. It is noteworthy that the fabrication techniques employed are not confined to the silicon substrate. Through spin casting and careful substrate selection (i.e. clothing, glass, polymer, etc.), additional degrees of freedom can be exploited to enhance sensitivity or to conform to unique applications. Both in-situ growth of nanostructured materials and casting of nanostructured dispersions were used to produce analogous chemical sensing devices.

A two-axis micromachined silicon actuator with micrometer range electrostatic actuation and picometer sensitive capacitive detection

NASA Astrophysics Data System (ADS)

Ayela, F.; Bret, J. L.; Chaussy, J.; Fournier, T.; Ménégaz, E.

2000-05-01

This article presents an innovative micromachined silicon actuator. A 50-μm-thick silicon foil is anodically bonded onto a broached Pyrex substrate. A free standing membrane and four coplanar electrodes in close proximity are then lithographied and etched. The use of phosphorus doped silicon with low electrical resistivity allows the application of an electrostatic force between one electrode and the moving diaphragm. This plane displacement and the induced interelectrode variation are capacitively detected. Due to the very low electrical resistivity of the doped silicon, there is no need to metallize the vertical trenches of the device. No piezoelectric transducer takes place so that the mechanical device is free from any hysteretic or temperature dependance. The range of the possible actuation along the x and y axis is around 5 μm. The actual sensitivity is xn=0.54 Å/Hz1/2 and yn=0.14 Å/Hz1/2. The microengineering steps and the electronic setup devoted to design the actuator and to perform relative capacitive measurements ΔC/C=10-6 from an initial value C≈10-13 F are described. The elaborated tests and performances of the device are presented. As a conclusion, some experimental projects using this subnanometric sensitive device are mentioned.

3D-FBK Pixel Sensors: Recent Beam Tests Results with Irradiated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Micelli, A.; /INFN, Trieste /Udine U.; Helle, K.

2012-04-30

The Pixel Detector is the innermost part of the ATLAS experiment tracking device at the Large Hadron Collider, and plays a key role in the reconstruction of the primary vertices from the collisions and secondary vertices produced by short-lived particles. To cope with the high level of radiation produced during the collider operation, it is planned to add to the present three layers of silicon pixel sensors which constitute the Pixel Detector, an additional layer (Insertable B-Layer, or IBL) of sensors. 3D silicon sensors are one of the technologies which are under study for the IBL. 3D silicon technology ismore » an innovative combination of very-large-scale integration and Micro-Electro-Mechanical-Systems where electrodes are fabricated inside the silicon bulk instead of being implanted on the wafer surfaces. 3D sensors, with electrodes fully or partially penetrating the silicon substrate, are currently fabricated at different processing facilities in Europe and USA. This paper reports on the 2010 June beam test results for irradiated 3D devices produced at FBK (Trento, Italy). The performance of these devices, all bump-bonded with the ATLAS pixel FE-I3 read-out chip, is compared to that observed before irradiation in a previous beam test.« less

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Effects of geared motor characteristics on tactile perception of tissue stiffness.

PubMed

Longnion, J; Rosen, J; Sinanan, M; Hannaford, B

2001-01-01

Endoscopic haptic surgical devices have shown promise in addressing the loss of tactile sensation associated with minimally invasive surgery. However, these devices must be capable of generating forces and torques similar to those applied on the tissue with a standard endoscopic tool. Geared motors are a possible solution for actuation; however, they possess mechanical characteristics that could potentially interfere with tactile perception of tissue qualities. The aim of the current research was to determine how the characteristics of a geared motor suitable for a haptic surgical device affect a user's perception of stiffness. The experiment involved six blindfolded subjects who were asked to discriminate the stiffness of six distinct silicone rubber samples whose mechanical properties are similar to those of soft tissue. Using a novel testing device whose dimensions approximated those of an endoscopic grasper, each subject palpated 30 permutations of sample pairs for each of three types of mechanical loads; the motor (friction and inertia), a flywheel (with the same inertia as motor), and a control (no significant mechanical interference). One factor ANOVA of the error scores and palpation time showed that no significant difference existed among error scores, but mean palpation time for the control was significantly less than for the other two methods. These results indicated that the mechanical characteristics of a geared motor chosen for application in a haptic surgical device did not interfere with the subjects' perception of the silicone samples' stiffness, but these characteristics may significantly affect the energy expenditure and time required for tissue palpation. Therefore, before geared motors can be considered for use in haptic surgical devices, consideration should be given to factors such as palpation speed and fatigue.

THz-wave generation via difference frequency mixing in strained silicon based waveguide utilizing its second order susceptibility χ((2)).

PubMed

Saito, Kyosuke; Tanabe, Tadao; Oyama, Yutaka

2014-07-14

Terahertz (THz) wave generation via difference frequency mixing (DFM) process in strain silicon membrane waveguides by introducing the straining layer is theoretically investigated. The Si(3)N(4) straining layer induces anisotropic compressive strain in the silicon core and results in the appearance of the bulk second order nonlinear susceptibility χ((2)) by breaking the crystal symmetry. We have proposed waveguide structures for THz wave generation under the DFM process by .using the modal birefringence in the waveguide core. Our simulations show that an output power of up to 0.95 mW can be achieved at 9.09 THz. The strained silicon optical device may open a widow in the field of the silicon-based active THz photonic device applications.

Optically tuned terahertz modulator based on annealed multilayer MoS2.

PubMed

Cao, Yapeng; Gan, Sheng; Geng, Zhaoxin; Liu, Jian; Yang, Yuping; Bao, Qiaoling; Chen, Hongda

2016-03-08

Controlling the propagation properties of terahertz waves is very important in terahertz technologies applied in high-speed communication. Therefore a new-type optically tuned terahertz modulator based on multilayer-MoS2 and silicon is experimentally demonstrated. The terahertz transmission could be significantly modulated by changing the power of the pumping laser. With an annealing treatment as a p-doping method, MoS2 on silicon demonstrates a triple enhancement of terahertz modulation depth compared with the bare silicon. This MoS2-based device even exhibited much higher modulation efficiency than the graphene-based device. We also analyzed the mechanism of the modulation enhancement originated from annealed MoS2, and found that it is different from that of graphene-based device. The unique optical modulating properties of the device exhibit tremendous promise for applications in terahertz switch.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Accomplishments include the determination of the reasons for differences in measurements of transistor delay time, identification of an energy level model for gold-doped silicon, and the finding of evidence that it does not appear to be necessary for an ultrasonic bonding tool to grip the wire and move it across the substrate metallization to make the bond. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; measurement of thermal properties of semiconductor devices, delay time, and related carrier transport properties in junction devices, and noise properties of microwave diodes; and characterization of silicon nuclear radiation detectors.

Fabrication of a Cryogenic Terahertz Emitter for Bolometer Focal Plane Calibrations

NASA Technical Reports Server (NTRS)

Chervenak, James; Brown, Ari; Wollack, Edward

2012-01-01

A fabrication process is reported for prototype emitters of THz radiation, which operate cryogenically, and should provide a fast, stable blackbody source suitable for characterization of THz devices. The fabrication has been demonstrated and, at the time of this reporting, testing was underway. The emitter is similar to a monolithic silicon bolometer in design, using both a low-noise thermometer and a heater element on a thermally isolated stage. An impedance-matched, high-emissivity coat ing is also integrated to tune the blackbody properties. This emitter is designed to emit a precise amount of power as a blackbody spectrum centered on terahertz frequencies. The emission is a function of the blackbody temperature. An integrated resistive heater and thermometer system can control the temperature of the blackbody with greater precision than previous incarnations of calibration sources that relied on blackbody emission. The emitter is fabricated using a silicon- on-insulator substrate wafer. The buried oxide is chosen to be less than 1 micron thick, and the silicon device thickness is 1-2 microns. Layers of phosphorus compensated with boron are implanted into and diffused throughout the full thickness of the silicon device layer to create the thermometer and heater components. Degenerately doped wiring is implanted to connect the devices to wire-bondable contact pads at the edge of the emitter chip. Then the device is micromachined to remove the thick-handle silicon behind the thermometer and heater components, and to thermally isolate it on a silicon membrane. An impedance- matched emissive coating (ion assisted evaporated Bi) is applied to the back of the membrane to enable high-efficiency emission of the blackbody spectrum.

Hot Electron Effects of Importance for Micron and Submicron Devices.

DTIC Science & Technology

1981-09-01

pair injected into the active region. That g(E) tron energy loss (in units of LO phonons do modify laser action has been shown in the 4 ,) stevia ...and x,) far away from the silicon-silicon-dioxide inter- Evoluton of the size of electronic devices. (a) Original transistor patent of John Bardeen face

A low cost X-ray imaging device based on BPW-34 Si-PIN photodiode

NASA Astrophysics Data System (ADS)

Emirhan, E.; Bayrak, A.; Yücel, E. Barlas; Yücel, M.; Ozben, C. S.

2016-05-01

A low cost X-ray imaging device based on BPW-34 silicon PIN photodiode was designed and produced. X-rays were produced from a CEI OX/70-P dental tube using a custom made ±30 kV power supply. A charge sensitive preamplifier and a shaping amplifier were built for the amplification of small signals produced by photons in the depletion layer of Si-PIN photodiode. A two dimensional position control unit was used for moving the detector in small steps to measure the intensity of X-rays absorbed in the object to be imaged. An Aessent AES220B FPGA module was used for transferring the image data to a computer via USB. Images of various samples were obtained with acceptable image quality despite of the low cost of the device.

ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

NASA Astrophysics Data System (ADS)

Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

Efficient semitransparent perovskite solar cells for 23.0%-efficiency perovskite/silicon four-terminal tandem cells

DOE PAGES

Chen, Bo; Bai, Yang; Yu, Zhengshan; ...

2016-07-19

Here, we have investigated semi-transparent perovskite solar cells and infrared enhanced silicon heterojunction cells for high-efficiency tandem devices. A semi-transparent metal electrode with good electrical conductivity and optical transparency has been fabricated by thermal evaporation of 7 nm of Au onto a 1-nm-thick Cu seed layer. For this electrode to reach its full potential, MAPbI3 thin films were formed by a modified one-step spin-coating method, resulting in a smooth layer that allowed the subsequent metal thin film to remain continuous. The fabricated semi-transparent perovskite solar cells demonstrated 16.5% efficiency under one-sun illumination, and were coupled with infrared-enhanced silicon heterojunction cellsmore » tuned specifically for perovskite/Si tandem devices. A double-layer antireflection coating at the front side and MgF2 reflector at rear side of the silicon heterojunction cells reduced parasitic absorption of near-infrared light, leading to 6.5% efficiency after filtering with a perovskite device and 23.0% summed efficiency for the perovskite/Si tandem device.« less

Efficient semitransparent perovskite solar cells for 23.0%-efficiency perovskite/silicon four-terminal tandem cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Bo; Bai, Yang; Yu, Zhengshan

Here, we have investigated semi-transparent perovskite solar cells and infrared enhanced silicon heterojunction cells for high-efficiency tandem devices. A semi-transparent metal electrode with good electrical conductivity and optical transparency has been fabricated by thermal evaporation of 7 nm of Au onto a 1-nm-thick Cu seed layer. For this electrode to reach its full potential, MAPbI3 thin films were formed by a modified one-step spin-coating method, resulting in a smooth layer that allowed the subsequent metal thin film to remain continuous. The fabricated semi-transparent perovskite solar cells demonstrated 16.5% efficiency under one-sun illumination, and were coupled with infrared-enhanced silicon heterojunction cellsmore » tuned specifically for perovskite/Si tandem devices. A double-layer antireflection coating at the front side and MgF2 reflector at rear side of the silicon heterojunction cells reduced parasitic absorption of near-infrared light, leading to 6.5% efficiency after filtering with a perovskite device and 23.0% summed efficiency for the perovskite/Si tandem device.« less

Silicone Migration From Baked-on Silicone Layers. Particle Characterization in Placebo and Protein Solutions.

PubMed

Funke, Stefanie; Matilainen, Julia; Nalenz, Heiko; Bechtold-Peters, Karoline; Mahler, Hanns-Christian; Friess, Wolfgang

2016-12-01

A significant number of therapeutic proteins are marketed as pre-filled syringes or other drug/device combination products and have been safely used in these formats for years. Silicone oil, which is used as lubricant, can migrate into the drug product and may interact with therapeutic proteins. In this study, particles in the size range of 0.2-5 μm and ≥1 μm as determined by resonant mass measurement and micro-flow imaging/light obscuration, respectively, resulted from silicone sloughing off the container barrel after agitation. The degree of droplet formation correlated well with the applied baked-on silicone levels of 13 μg and 94 μg per cartridge. Silicone migration was comparable in placebo, 2 mg/mL and 33 mg/mL IgG1 formulations containing 0.04% (w/v) polysorbate 20. Headspace substantially increased the formation of silicone droplets during agitation. The highest particle concentrations reached, however, were still very low compared to numbers described for spray-on siliconized containers. When applying adequate baked-on silicone levels below 100 μg, bake-on siliconization efficiently limits silicone migration into the drug product without compromising device functionality. Copyright © 2016 American Pharmacists Association®. Published by Elsevier Inc. All rights reserved.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2004-12-07

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process For Direct Integration Of A Thin-Film Silicon P-N Junction Diode With A Magnetic Tunnel Junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2005-08-23

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2003-01-01

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

III-V-on-silicon solar cells reaching 33% photoconversion efficiency in two-terminal configuration

NASA Astrophysics Data System (ADS)

Cariou, Romain; Benick, Jan; Feldmann, Frank; Höhn, Oliver; Hauser, Hubert; Beutel, Paul; Razek, Nasser; Wimplinger, Markus; Bläsi, Benedikt; Lackner, David; Hermle, Martin; Siefer, Gerald; Glunz, Stefan W.; Bett, Andreas W.; Dimroth, Frank

2018-04-01

Silicon dominates the photovoltaic industry but the conversion efficiency of silicon single-junction solar cells is intrinsically constrained to 29.4%, and practically limited to around 27%. It is possible to overcome this limit by combining silicon with high-bandgap materials, such as III-V semiconductors, in a multi-junction device. Significant challenges associated with this material combination have hindered the development of highly efficient III-V/Si solar cells. Here, we demonstrate a III-V/Si cell reaching similar performances to standard III-V/Ge triple-junction solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell. The key issues of III-V/Si interface recombination and silicon's weak absorption are addressed using poly-silicon/SiOx passivating contacts and a novel rear-side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a two-terminal GaInP/GaAs//Si solar cell reaching a 1-sun AM1.5G conversion efficiency of 33.3%.

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Towards nanometer-spaced silicon contacts to proteins.

PubMed

Schukfeh, Muhammed I; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-18

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p(+) silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices' electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes' edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions' conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein's denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Medicine Delivery Device with Integrated Sterilization and Detection

NASA Technical Reports Server (NTRS)

Sheam, Michael J.; Greer, Harold F.; Manohara, Harish

2013-01-01

Sterile delivery devices can be created by integrating a medicine delivery instrument with surfaces that are coated with germicidal and anti-fouling material. This requires that a large-surface-area template be developed within a constrained volume to ensure good contact between the delivered medicine and the germicidal material. Both of these can be integrated using JPL-developed silicon nanotip or cryo-etch black silicon technologies with atomic layer deposition (ALD) coating of specific germicidal layers. Nanofabrication techniques that are used to produce a microfluidics device are also capable of synthesizing extremely hig-hsurface-area templates in precise locations, and coating those surfaces with conformal films to manipulate their surface properties. This methodology has been successfully applied at JPL to produce patterned and coated silicon nanotips (also known as black silicon) to manipulate the hydrophilicity of surfaces to direct the spreading of fluids in microdevices. JPL s ALD technique is an ideal method to produce the highly conformal coatings required for this type of application. Certain materials, such as TiO2, have germicidal and anti-fouling properties when they are illuminated with UV light. The proposed delivery device contacts medicine with this high-surface-area black silicon surface coated with a thin-film germicidal deposited conformally with ALD. The coating can also be illuminated with ultraviolet light for the purpose of sterilization or identification of the medicine itself. This constrained volume that is located immediately prior to delivery into a patient, ensures that the medicine delivery device is inherently sterile.

Thermal ink-jet device using single-chip silicon microchannels

NASA Astrophysics Data System (ADS)

Wuu, DongSing; Cheng, Chen-Yue; Horng, RayHua; Chan, G. C.; Chiu, Sao-Ling; Wu, Yi-Yung

1998-06-01

We present a new method to fabricate silicon microfluidic channels by through-hole etching with subsequent planarization. The method is based on etching out the deep grooves through a perforated silicon carbide membrane, followed by sealing the membrane with plasma-enhanced chemical vapor deposition (PECVD). Low-pressure-chemical-vapor- deposited (LPCVD) polysilicon was used as a sacrificial layer to define the channel structure and only one etching step is required. This permits the realization of planarization after a very deep etching step in silicon and offers the possibility for film deposition, resist spinning and film patterning across deep grooves. The process technology was demonstrated on the fabrication of a monolithic silicon microchannel structure for thermal inkjet printing. The Ta-Al heater arrays are integrated on the top of each microchannel, which connect to a common on-chip front-end ink reservoir. The fabrication of this device requires six masks and no active nozzle-to-chip alignment. Moreover, the present micromachining process is compatible with the addition of on-chip circuitry for multiplexing the heater control signals. Heat transfer efficiency to the ink is enhanced by the high thermal conductivity of the silicon carbide in the channel ceiling, while the bulk silicon maintains high interchannel isolation. The fabricated inkjet devices show the droplet sizes of 20 - 50 micrometer in diameter with various channel dimensions and stable ejection of ink droplets more than 1 million.

Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers

DOEpatents

Moustakas, Theodore D.; Maruska, H. Paul

1985-07-09

A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

PubMed

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Epitaxial growth of high quality InP on Si substrates: The role of InAs/InP quantum dots as effective dislocation filters

NASA Astrophysics Data System (ADS)

Shi, Bei; Li, Qiang; Lau, Kei May

2018-05-01

Monolithic integration of InP on a Si platform ideally facilitates on-chip light sources in silicon photonic applications. In addition to the well-developed hybrid bonding techniques, the direct epitaxy method is spawning as a more strategic and potentially cost-effective approach to monolithically integrate InP-based telecom lasers. To minimize the unwanted defects within the InP crystal, we explore multiple InAs/InP quantum dots as dislocation filters. The high quality InP buffer is thus obtained, and the dislocation filtering effects of the quantum dots are directly examined via both plan-view and cross-sectional transmission electron microscopy, along with room-temperature photoluminescence. The defect density on the InP surface was reduced to 3 × 108/cm2, providing an improved optical property of active photonic devices on Si substrates. This work offers a novel solution to advance large-scale integration of InP on Si, which is beneficial to silicon-based long-wavelength lasers in telecommunications.

Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

Multi-junction solar cell device

DOEpatents

Friedman, Daniel J.; Geisz, John F.

2007-12-18

A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p. The present invention further includes a method for substantially lattice matching single-crystal III-V semiconductor layers with the silicon substrate (22) by including boron and/or nitrogen in the chemical structure of these layers.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2007-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy (Inventor)

2011-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Impact of Total Ionizing Dose Radiation Testing and Long-Term Thermal Cycling on the Operation of CMF20120D Silicon Carbide Power MOSFET

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Scheidegger, Robert J.; Lauenstein, Jean-Marie; Casey, Megan; Scheick, Leif; Hammoud, Ahmad

2013-01-01

Power systems designed for use in NASA space missions are required to work reliably under harsh conditions including radiation, thermal cycling, and extreme temperature exposures. Silicon carbide devices show great promise for use in future power electronics systems, but information pertaining to performance of the devices in the space environment is very scarce. A silicon carbide N-channel enhancement-mode power MOSFET called the CMF20120 is of interest for use in space environments. Samples of the device were exposed to radiation followed by long-term thermal cycling to address their reliability for use in space applications. The results of the experimental work are presentd and discussed.

A physically transient form of silicon electronics.

PubMed

Hwang, Suk-Won; Tao, Hu; Kim, Dae-Hyeong; Cheng, Huanyu; Song, Jun-Kyul; Rill, Elliott; Brenckle, Mark A; Panilaitis, Bruce; Won, Sang Min; Kim, Yun-Soung; Song, Young Min; Yu, Ki Jun; Ameen, Abid; Li, Rui; Su, Yewang; Yang, Miaomiao; Kaplan, David L; Zakin, Mitchell R; Slepian, Marvin J; Huang, Yonggang; Omenetto, Fiorenzo G; Rogers, John A

2012-09-28

A remarkable feature of modern silicon electronics is its ability to remain physically invariant, almost indefinitely for practical purposes. Although this characteristic is a hallmark of applications of integrated circuits that exist today, there might be opportunities for systems that offer the opposite behavior, such as implantable devices that function for medically useful time frames but then completely disappear via resorption by the body. We report a set of materials, manufacturing schemes, device components, and theoretical design tools for a silicon-based complementary metal oxide semiconductor (CMOS) technology that has this type of transient behavior, together with integrated sensors, actuators, power supply systems, and wireless control strategies. An implantable transient device that acts as a programmable nonantibiotic bacteriocide provides a system-level example.

Bathed, Strained, Attenuated, Annihilated: Towards Quantum Optomechanics

NASA Astrophysics Data System (ADS)

Pepper, Brian Jeffrey

The field of optomechanics studies tiny devices that can be pushed mechanically by light. It is an extremely promising avenue towards tests of quantum mechanics on a macroscopic scale, by transferring quantum states of light to nano- or micromechanical objects. This dissertation concerns a long term research program to create quantum superpositions of a macroscopic mirror in an optomechanical cavity. This dissertation has two broad thrusts. The first focuses on microfabrication of a new type of device called optomechanical trampoline resonators, consisting of a small mirror on a cross-shaped tensed silicon nitride membrane. Devices have been fabricated with high mechanical and optical quality, including a 300 kHz device with quality factor 480,000, as well as a device of optical finesse 107,000. These devices are well into the sideband-resolved regime and suitable for optical cooling to the quantum ground state. One such device has been optically cooled to approximately 10 phonons. The second major thrust is theoretical. Creating a macroscopic superposition is a challenging problem, requiring optical cooling to the ground state, strong coupling, extremely high optical finesse and extremely low frequency. A realistic assessment of achievable parameters indicates that it is possible to achieve ground state cooling or strong coupling, but not both. This dissertation proposes a new technique using postselection to achieve macroscopic superpositions with only weak coupling. This relaxes some of the required parameters by orders of magnitude. Prospects for observing hypothetical novel decoherence mechanisms are also discussed.

Manufacture of patient-specific vascular replicas for endovascular simulation using fast, low-cost method

NASA Astrophysics Data System (ADS)

Kaneko, Naoki; Mashiko, Toshihiro; Ohnishi, Taihei; Ohta, Makoto; Namba, Katsunari; Watanabe, Eiju; Kawai, Kensuke

2016-12-01

Patient-specific vascular replicas are essential to the simulation of endovascular treatment or for vascular research. The inside of silicone replica is required to be smooth for manipulating interventional devices without resistance. In this report, we demonstrate the fabrication of patient-specific silicone vessels with a low-cost desktop 3D printer. We show that the surface of an acrylonitrile butadiene styrene (ABS) model printed by the 3D printer can be smoothed by a single dipping in ABS solvent in a time-dependent manner, where a short dip has less effect on the shape of the model. The vascular mold is coated with transparent silicone and then the ABS mold is dissolved after the silicone is cured. Interventional devices can pass through the inside of the smoothed silicone vessel with lower pushing force compared to the vessel without smoothing. The material cost and time required to fabricate the silicone vessel is about USD $2 and 24 h, which is much lower than the current fabrication methods. This fast and low-cost method offers the possibility of testing strategies before attempting particularly difficult cases, while improving the training of endovascular therapy, enabling the trialing of new devices, and broadening the scope of vascular research.

Optimization of hybrid organic/inorganic poly(3-hexylthiophene-2,5-diyl)/silicon solar cells

NASA Astrophysics Data System (ADS)

Weingarten, Martin; Sanders, Simon; Stümmler, Dominik; Pfeiffer, Pascal; Vescan, Andrei; Kalisch, Holger

2016-04-01

In the last years, hybrid organic/silicon solar cells have attracted great interest in photovoltaic research due to their potential to become a low-cost alternative for the conventionally used silicon pn-junction solar cells. This work is focused on hybrid solar cells based on the polymer poly(3-hexylthiophene-2,5-diyl), which was deposited on n-doped crystalline silicon via spin-coating under ambient conditions. By employing an anisotropic etching step with potassium hydroxide (KOH), the reflection losses at the silicon surface were reduced. Hereby, the short-circuit current density of the hybrid devices was increased by 31%, leading to a maximum power conversion efficiency (PCE) of 13.1% compared to a PCE of 10.7% for the devices without KOH etching. In addition, the contacts were improved by replacing gold with the more conductive silver as top grid material to reduce the contact resistance and by introducing a thin (˜0.5 nm) lithium fluoride layer between the silicon and the aluminum backside contact to improve electron collection and hole blocking. Hereby, the open-circuit voltage and the fill factor of the hybrid solar cells were further improved and devices with very high PCE up to 14.2% have been realized.

Review of silicon photonics: history and recent advances

NASA Astrophysics Data System (ADS)

Ye, Winnie N.; Xiong, Yule

2013-09-01

Silicon photonics has attracted tremendous attention and research effort as a promising technology in optoelectronic integration for computing, communications, sensing, and solar harvesting. Mainly due to the combination of its excellent material properties and the complementary metal-oxide semiconductor (CMOS) fabrication processing technology, silicon has becoming the material choice for photonic and optoelectronic circuits with low cost, ultra-compact device footprint, and high-density integration. This review paper provides an overview on silicon photonics, by highlighting the early work from the mid-1980s on the fundamental building blocks such as silicon platforms and waveguides, and the main milestones that have been achieved so far in the field. A summary of reported work on functional elements in both passive and active devices, as well as the applications of the technology in interconnect, sensing, and solar cells, is identified.

FABRICATION OF A RETINAL PROSTHETIC TEST DEVICE USING ELECTRODEPOSITED SILICON OVER POLYPYRROLE PATTERNED WITH SU-8 PHOTORESIST

PubMed Central

Miller, Eric; Ellis, Daniel; Charles, Duran; McKenzie, Jason

2016-01-01

A materials fabrication study of a photodiode array for possible application of retina prosthesis was undertaken. A test device was fabricated using a glassy carbon electrode patterned with SU-8 photoresist. In the openings, p-type polypyrrole was first electrodeposited using 1-butyl-1-methylpyridinium bis(trifluoromethylsulfonyl)imide ionic liquid. The polypyrrole was self-doped with imide ion at ~1.5 mole %, was verified as p-type, and had a resistivity of ~20 Ωcm. N-type Silicon was then electrodeposited over this layer using silicon tetrachloride / phosphorus trichloride in acetonitrile and passivated in a second electrodeposition using trimethylchlorosilane. Electron microscopy revealed the successful electrodeposition of silicon over patterned polypyrrole. Rudimentary photodiode behavior was observed. The passivation improved but did not completely protect the electrodeposited silicon from oxidation by air. PMID:27616940

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bachman, Daniel; Chen, Zhijiang; Wang, Christopher

Phase errors caused by fabrication variations in silicon photonic integrated circuits are an important problem, which negatively impacts device yield and performance. This study reports our recent progress in the development of a method for permanent, postfabrication phase error correction of silicon photonic circuits based on femtosecond laser irradiation. Using beam shaping technique, we achieve a 14-fold enhancement in the phase tuning resolution of the method with a Gaussian-shaped beam compared to a top-hat beam. The large improvement in the tuning resolution makes the femtosecond laser method potentially useful for very fine phase trimming of silicon photonic circuits. Finally, wemore » also show that femtosecond laser pulses can directly modify silicon photonic devices through a SiO 2 cladding layer, making it the only permanent post-fabrication method that can tune silicon photonic circuits protected by an oxide cladding.« less

Light Absorption Enhancement of Silicon-Based Photovoltaic Devices with Multiple Bandgap Structures of Porous Silicon

PubMed Central

Wu, Kuen-Hsien; Li, Chong-Wei

2015-01-01

Porous-silicon (PS) multi-layered structures with three stacked PS layers of different porosity were prepared on silicon (Si) substrates by successively tuning the electrochemical-etching parameters in an anodization process. The three PS layers have different optical bandgap energy and construct a triple-layered PS (TLPS) structure with multiple bandgap energy. Photovoltaic devices were fabricated by depositing aluminum electrodes of Schottky contacts on the surfaces of the developed TLPS structures. The TLPS-based devices exhibit broadband photoresponses within the spectrum of the solar irradiation and get high photocurrent for the incident light of a tungsten lamp. The improved spectral responses of devices are owing to the multi-bandgap structures of TLPS, which are designed with a layered configuration analog to a tandem cell for absorbing a wider energy range of the incidental sun light. The large photocurrent is mainly ascribed to an enhanced light-absorption ability as a result of applying nanoporous-Si thin films as the surface layers to absorb the short-wavelength light and to improve the Schottky contacts of devices. Experimental results reveal that the multi-bandgap PS structures produced from electrochemical-etching of Si wafers are potentially promising for development of highly efficient Si-based solar cells. PMID:28793542

Method for selective CMP of polysilicon

NASA Technical Reports Server (NTRS)

Babu, Suryadevara V. (Inventor); Natarajan, Anita (Inventor); Hegde, Sharath (Inventor)

2010-01-01

A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable for use in the fabrication of MEMS devices.

High Performance MgO-barrier Magnetic Tunnel Junctions for Flexible and Wearable Spintronic Applications.

PubMed

Chen, Jun-Yang; Lau, Yong-Chang; Coey, J M D; Li, Mo; Wang, Jian-Ping

2017-02-02

The magnetic tunnel junction (MTJ) using MgO barrier is one of most important building blocks for spintronic devices and has been widely utilized as miniaturized magentic sensors. It could play an important role in wearable medical devices if they can be fabricated on flexible substrates. The required stringent fabrication processes to obtain high quality MgO-barrier MTJs, however, limit its integration with flexible electronics devices. In this work, we have developed a method to fabricate high-performance MgO-barrier MTJs directly onto ultrathin flexible silicon membrane with a thickness of 14 μm and then transfer-and-bond to plastic substrates. Remarkably, such flexible MTJs are fully functional, exhibiting a TMR ratio as high as 190% under bending radii as small as 5 mm. The devices' robustness is manifested by its retained excellent performance and unaltered TMR ratio after over 1000 bending cycles. The demonstrated flexible MgO-barrier MTJs opens the door to integrating high-performance spintronic devices in flexible and wearable electronics devices for a plethora of biomedical sensing applications.

Finite Element Study of a Lumbar Intervertebral Disc Nucleus Replacement Device.

PubMed

Coogan, Jessica S; Francis, W Loren; Eliason, Travis D; Bredbenner, Todd L; Stemper, Brian D; Yoganandan, Narayan; Pintar, Frank A; Nicolella, Daniel P

2016-01-01

Nucleus replacement technologies are a minimally invasive alternative to spinal fusion and total disc replacement that have the potential to reduce pain and restore motion for patients with degenerative disc disease. Finite element modeling can be used to determine the biomechanics associated with nucleus replacement technologies. The current study focuses on a new nucleus replacement device designed as a conforming silicone implant with an internal void. A validated finite element model of the human lumbar L3-L4 motion segment was developed and used to investigate the influence of the nucleus replacement device on spine biomechanics. In addition, the effect of device design changes on biomechanics was determined. A 3D, L3-L4 finite element model was constructed from medical imaging data. Models were created with the normal intact nucleus, the nucleus replacement device, and a solid silicone implant. Probabilistic analysis was performed on the normal model to provide quantitative validation metrics. Sensitivity analysis was performed on the silicone Shore A durometer of the device. Models were loaded under axial compression followed by flexion/extension, lateral bending, or axial rotation. Compressive displacement, endplate stresses, reaction moment, and annulus stresses were determined and compared between the different models. The novel nucleus replacement device resulted in similar compressive displacement, endplate stress, and annulus stress and slightly higher reaction moment compared with the normal nucleus. The solid implant resulted in decreased displacement, increased endplate stress, decreased annulus stress, and decreased reaction moment compared with the novel device. With increasing silicone durometer, compressive displacement decreased, endplate stress increased, reaction moment increased, and annulus stress decreased. Finite element analysis was used to show that the novel nucleus replacement device results in similar biomechanics compared with the normal intact nucleus.

Finite Element Study of a Lumbar Intervertebral Disc Nucleus Replacement Device

PubMed Central

Coogan, Jessica S.; Francis, W. Loren; Eliason, Travis D.; Bredbenner, Todd L.; Stemper, Brian D.; Yoganandan, Narayan; Pintar, Frank A.; Nicolella, Daniel P.

2016-01-01

Nucleus replacement technologies are a minimally invasive alternative to spinal fusion and total disc replacement that have the potential to reduce pain and restore motion for patients with degenerative disc disease. Finite element modeling can be used to determine the biomechanics associated with nucleus replacement technologies. The current study focuses on a new nucleus replacement device designed as a conforming silicone implant with an internal void. A validated finite element model of the human lumbar L3–L4 motion segment was developed and used to investigate the influence of the nucleus replacement device on spine biomechanics. In addition, the effect of device design changes on biomechanics was determined. A 3D, L3–L4 finite element model was constructed from medical imaging data. Models were created with the normal intact nucleus, the nucleus replacement device, and a solid silicone implant. Probabilistic analysis was performed on the normal model to provide quantitative validation metrics. Sensitivity analysis was performed on the silicone Shore A durometer of the device. Models were loaded under axial compression followed by flexion/extension, lateral bending, or axial rotation. Compressive displacement, endplate stresses, reaction moment, and annulus stresses were determined and compared between the different models. The novel nucleus replacement device resulted in similar compressive displacement, endplate stress, and annulus stress and slightly higher reaction moment compared with the normal nucleus. The solid implant resulted in decreased displacement, increased endplate stress, decreased annulus stress, and decreased reaction moment compared with the novel device. With increasing silicone durometer, compressive displacement decreased, endplate stress increased, reaction moment increased, and annulus stress decreased. Finite element analysis was used to show that the novel nucleus replacement device results in similar biomechanics compared with the normal intact nucleus. PMID:27990418

Negative differential conductance in doped-silicon nanoscale devices with superconducting electrodes

NASA Astrophysics Data System (ADS)

Shapovalov, A.; Shaternik, V.; Suvorov, O.; Zhitlukhina, E.; Belogolovskii, M.

2018-02-01

We present a proof-of-concept nanoelectronics device with a negative differential conductance, an attractive from the applied viewpoint functionality. The device, characterized by the decreasing current with increasing voltage in a certain voltage region above a threshold bias of about several hundred millivolts, consists of two superconducting electrodes with an amorphous 10-nm-thick silicon interlayer doped by tungsten nano-inclusions. We show that small changes in the W content radically modify the shape of the trilayer current-voltage dependence and identify sudden conductance switching at a threshold voltage as an effect of Andreev fluctuators. The latter entities are two-level systems at the superconductor-doped silicon interface where a Cooper pair tunnels from a superconductor and occupies a pair of localized electronic states. We argue that in contrast to previously proposed devices, our samples permit very large-scale integration and are practically feasible.

Temperature-dependent mechanical behavior of silicon dioxide, gold and gold-vanadium thin films for VLSI integrated circuits and MicroElectroMechanical systems (MEMs)

NASA Astrophysics Data System (ADS)

Lin, Ming-Tzer

The Semiconductor Industry has grown rapidly in the last twenty years. The national technology roadmap for semiconductors plans for developing the complexity and packing density of semiconductor devices into the next decade, allowing ever smaller and more densely packed structures to be fabricated. Recently, MEMS (Micro-Electro-Mechanical Systems) have become important in modern technology. The goal of MEMs is to integrate many types of miniature devices on a single chip, creating a new micro-world. The oxidation of silicon is one of the most important processes in semiconductor technology. Producing high-quality IC's and MEMS devices requires an understanding of the basic oxidation mechanism. In addition, for the reliability of IC's and MEMS devices, the mechanical properties of the oxide play a critical role. There has been an apparent convergence of opinion on the relevant mechanism leading to the "standard computational model" for stress effects on silicon oxidation. This model has recently become suspect. Most of the reasonably direct experimental data on the flow properties of SiO 2 thin film do not support a stress-dependent viscosity of the sort envisioned by the model. Gold and gold vanadium alloys are used in electrical interconnections and in radio frequency switch contacts for the semiconductor industry, MEMs sensors for the aerospace industry and also in brain probes by the bioelectronics mechanical industry. Despite the strong potential usage of gold and gold vanadium thin films at the small scale, very little is known about their mechanical properties. Our goal was to experimentally investigate stress and its influence on SiO2 thin films and the mechanical properties of gold and gold vanadium thin films at room temperature and at elevated temperature of different vanadium concentration. We found that the application of relatively small amounts of bending to an oxidizing silicon substrate leads to significant decreases in oxide thickness in the ultrathin oxide regime. Both tensile and compressive bending retard oxide growth, although compressive bending results in somewhat thinner oxides than does tensile bending. We also determined the modulus of gold and gold vanadium, and discovered that there is some evidence for a vanadium concentration dependence of the mechanical properties.

Hollow Microtube Resonators via Silicon Self-Assembly toward Subattogram Mass Sensing Applications.

PubMed

Kim, Joohyun; Song, Jungki; Kim, Kwangseok; Kim, Seokbeom; Song, Jihwan; Kim, Namsu; Khan, M Faheem; Zhang, Linan; Sader, John E; Park, Keunhan; Kim, Dongchoul; Thundat, Thomas; Lee, Jungchul

2016-03-09

Fluidic resonators with integrated microchannels (hollow resonators) are attractive for mass, density, and volume measurements of single micro/nanoparticles and cells, yet their widespread use is limited by the complexity of their fabrication. Here we report a simple and cost-effective approach for fabricating hollow microtube resonators. A prestructured silicon wafer is annealed at high temperature under a controlled atmosphere to form self-assembled buried cavities. The interiors of these cavities are oxidized to produce thin oxide tubes, following which the surrounding silicon material is selectively etched away to suspend the oxide tubes. This simple three-step process easily produces hollow microtube resonators. We report another innovation in the capping glass wafer where we integrate fluidic access channels and getter materials along with residual gas suction channels. Combined together, only five photolithographic steps and one bonding step are required to fabricate vacuum-packaged hollow microtube resonators that exhibit quality factors as high as ∼ 13,000. We take one step further to explore additionally attractive features including the ability to tune the device responsivity, changing the resonator material, and scaling down the resonator size. The resonator wall thickness of ∼ 120 nm and the channel hydraulic diameter of ∼ 60 nm are demonstrated solely by conventional microfabrication approaches. The unique characteristics of this new fabrication process facilitate the widespread use of hollow microtube resonators, their translation between diverse research fields, and the production of commercially viable devices.

Thin film photovoltaic device with multilayer substrate

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1984-01-01

A thin film photovoltaic device which utilizes at least one compound semiconductor layer chosen from Groups IIB and VA of the Periodic Table is formed on a multilayer substrate The substrate includes a lowermost support layer on which all of the other layers of the device are formed. Additionally, an uppermost carbide or silicon layer is adjacent to the semiconductor layer. Below the carbide or silicon layer is a metal layer of high conductivity and expansion coefficient equal to or slightly greater than that of the semiconductor layer.

Atomically Precise Surface Engineering for Producing Imagers

NASA Technical Reports Server (NTRS)

Nikzad, Shouleh (Inventor); Hoenk, Michael E. (Inventor); Greer, Frank (Inventor); Jones, Todd J. (Inventor)

2015-01-01

High-quality surface coatings, and techniques combining the atomic precision of molecular beam epitaxy and atomic layer deposition, to fabricate such high-quality surface coatings are provided. The coatings made in accordance with the techniques set forth by the invention are shown to be capable of forming silicon CCD detectors that demonstrate world record detector quantum efficiency (>50%) in the near and far ultraviolet (155 nm-300 nm). The surface engineering approaches used demonstrate the robustness of detector performance that is obtained by achieving atomic level precision at all steps in the coating fabrication process. As proof of concept, the characterization, materials, and exemplary devices produced are presented along with a comparison to other approaches.

Alternatives for joining Si wafers to strain-accommodating Cu for high-power electronics

NASA Astrophysics Data System (ADS)

Faust, Nicholas; Messler, Robert W.; Khatri, Subhash

2001-10-01

Differences in the coefficients of thermal expansion (CTE) between silicon wafers and underlying copper electrodes have led to the use of purely mechanical dry pressure contacts for primary electrical and thermal connections in high-power solid-state electronic devices. These contacts are limited by their ability to dissipate I2R heat from within the device and by their thermal fatigue life. To increase heat dissipation and effectively deal with the CTE mismatch, metallurgical bonding of the silicon to a specially-structured, strain-accommodating copper electrode has been proposed. This study was intended to seek alternative methods for and demonstrate the feasibility of bonding Si to structured Cu in high-power solid-state devices. Three different but fundamentally related fluxless approaches identified and preliminarily assessed were: (1) conventional Sn-Ag eutectic solder; (2) a new, commercially-available active solder based on the Sn-Ag eutectic; and (3) solid-liquid interdiffusion bonding using the Au-In system. Metallurgical joints were made with varying quality levels (according to nonde-structive ultrasonic C-scan mapping, SEM, and electron microprobe) using each approach. Mechanical shear testing resulted in cohesive failure within the Si or the filler alloys. The best approach, in which eutectic Sn-Ag solder in pre-alloyed foil form was employed on Si and Cu substrates metallized (from the substrate outward) with Ti, Ni and Au, exhibited joint thermal conduction 74% better than dry pressure contacts.

Enhancement of Light Absorption in Silicon Nanowire Photovoltaic Devices with Dielectric and Metallic Grating Structures.

PubMed

Park, Jin-Sung; Kim, Kyoung-Ho; Hwang, Min-Soo; Zhang, Xing; Lee, Jung Min; Kim, Jungkil; Song, Kyung-Deok; No, You-Shin; Jeong, Kwang-Yong; Cahoon, James F; Kim, Sun-Kyung; Park, Hong-Gyu

2017-12-13

We report the enhancement of light absorption in Si nanowire photovoltaic devices with one-dimensional dielectric or metallic gratings that are fabricated by a damage-free, precisely aligning, polymer-assisted transfer method. Incorporation of a Si 3 N 4 grating with a Si nanowire effectively enhances the photocurrents for transverse-electric polarized light. The wavelength at which a maximum photocurrent is generated is readily tuned by adjusting the grating pitch. Moreover, the electrical properties of the nanowire devices are preserved before and after transferring the Si 3 N 4 gratings onto Si nanowires, ensuring that the quality of pristine nanowires is not degraded during the transfer. Furthermore, we demonstrate Si nanowire photovoltaic devices with Ag gratings using the same transfer method. Measurements on the fabricated devices reveal approximately 27.1% enhancement in light absorption compared to that of the same devices without the Ag gratings without any degradation of electrical properties. We believe that our polymer-assisted transfer method is not limited to the fabrication of grating-incorporated nanowire photovoltaic devices but can also be generically applied for the implementation of complex nanoscale structures toward the development of multifunctional optoelectronic devices.

3D active edge silicon sensors: Device processing, yield and QA for the ATLAS-IBL production

DOE Office of Scientific and Technical Information (OSTI.GOV)

Da Vià, Cinzia; Boscardil, Maurizio; Dalla Betta, GianFranco

2013-01-01

3D silicon sensors, where plasma micromachining is used to etch deep narrow apertures in the silicon substrate to form electrodes of PIN junctions, were successfully manufactured in facilities in Europe and USA. In 2011 the technology underwent a qualification process to establish its maturity for a medium scale production for the construction of a pixel layer for vertex detection, the Insertable B-Layer (IBL) at the CERN-LHC ATLAS experiment. The IBL collaboration, following that recommendation from the review panel, decided to complete the production of planar and 3D sensors and endorsed the proposal to build enough modules for a mixed IBLmore » sensor scenario where 25% of 3D modules populate the forward and backward part of each stave. The production of planar sensors will also allow coverage of 100% of the IBL, in case that option was required. This paper will describe the processing strategy which allowed successful 3D sensor production, some of the Quality Assurance (QA) tests performed during the pre-production phase and the production yield to date.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moreno, Gilbert

The objective for this project is to develop thermal management strategies to enable efficient and high-temperature wide-bandgap (WBG)-based power electronic systems (e.g., emerging inverter and DC-DC converter). Device- and system-level thermal analyses are conducted to determine the thermal limitations of current automotive power modules under elevated device temperature conditions. Additionally, novel cooling concepts and material selection will be evaluated to enable high-temperature silicon and WBG devices in power electronics components. WBG devices (silicon carbide [SiC], gallium nitride [GaN]) promise to increase efficiency, but will be driven as hard as possible. This creates challenges for thermal management and reliability.

Pseudo-direct bandgap transitions in silicon nanocrystals: effects on optoelectronics and thermoelectrics

NASA Astrophysics Data System (ADS)

Singh, Vivek; Yu, Yixuan; Sun, Qi-C.; Korgel, Brian; Nagpal, Prashant

2014-11-01

While silicon nanostructures are extensively used in electronics, the indirect bandgap of silicon poses challenges for optoelectronic applications like photovoltaics and light emitting diodes (LEDs). Here, we show that size-dependent pseudo-direct bandgap transitions in silicon nanocrystals dominate the interactions between (photoexcited) charge carriers and phonons, and hence the optoelectronic properties of silicon nanocrystals. Direct measurements of the electronic density of states (DOS) for different sized silicon nanocrystals reveal that these pseudo-direct transitions, likely arising from the nanocrystal surface, can couple with the quantum-confined silicon states. Moreover, we demonstrate that since these transitions determine the interactions of charge carriers with phonons, they change the light emission, absorption, charge carrier diffusion and phonon drag (Seebeck coefficient) in nanoscaled silicon semiconductors. Therefore, these results can have important implications for the design of optoelectronics and thermoelectric devices based on nanostructured silicon.While silicon nanostructures are extensively used in electronics, the indirect bandgap of silicon poses challenges for optoelectronic applications like photovoltaics and light emitting diodes (LEDs). Here, we show that size-dependent pseudo-direct bandgap transitions in silicon nanocrystals dominate the interactions between (photoexcited) charge carriers and phonons, and hence the optoelectronic properties of silicon nanocrystals. Direct measurements of the electronic density of states (DOS) for different sized silicon nanocrystals reveal that these pseudo-direct transitions, likely arising from the nanocrystal surface, can couple with the quantum-confined silicon states. Moreover, we demonstrate that since these transitions determine the interactions of charge carriers with phonons, they change the light emission, absorption, charge carrier diffusion and phonon drag (Seebeck coefficient) in nanoscaled silicon semiconductors. Therefore, these results can have important implications for the design of optoelectronics and thermoelectric devices based on nanostructured silicon. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr04688a

Silicide/Silicon Hetero-Junction Structure for Thermoelectric Applications.

PubMed

Jun, Dongsuk; Kim, Soojung; Choi, Wonchul; Kim, Junsoo; Zyung, Taehyoung; Jang, Moongyu

2015-10-01

We fabricated silicide/silicon hetero-junction structured thermoelectric device by CMOS process for the reduction of thermal conductivity with the scatterings of phonons at silicide/silicon interfaces. Electrical conductivities, Seebeck coefficients, power factors, and temperature differences are evaluated using the steady state analysis method. Platinum silicide/silicon multilayered structure showed an enhanced Seebeck coefficient and power factor characteristics, which was considered for p-leg element. Also, erbium silicide/silicon structure showed an enhanced Seebeck coefficient, which was considered for an n-leg element. Silicide/silicon multilayered structure is promising for thermoelectric applications by reducing thermal conductivity with an enhanced Seebeck coefficient. However, because of the high thermal conductivity of the silicon packing during thermal gradient is not a problem any temperature difference. Therefore, requires more testing and analysis in order to overcome this problem. Thermoelectric generators are devices that based on the Seebeck effect, convert temperature differences into electrical energy. Although thermoelectric phenomena have been used for heating and cooling applications quite extensively, it is only in recent years that interest has increased in energy generation.

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

PubMed

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitancemore » behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.« less

Self-formed cylindrical microcapillaries through surface migration of silicon and their application to single-cell analysis

NASA Astrophysics Data System (ADS)

Zeng, Fan; Luo, Yuan; Yobas, Levent; Wong, Man

2013-05-01

Surface migration of monocrystalline silicon has been applied to demonstrate self-formed cylindrical microcapillaries with diameters from 0.8 to 2.8 µm based on the microstructured substrate topography. The microcapillaries are entirely enclosed in silicon and can be conveniently etched to create fluidic access ports and microchannels for their subsequent integration into functional microfluidic devices. Moreover, the microcapillaries can be thermally oxidized through their access ports with silica walls remain intact upon release from surrounding silicon in an effort to enhance optical clarity. Straight microcapillaries and microcapillaries with perpendicular turns and crossings (junctions) have all been fabricated and validated for fluidic continuity with a fluorescein solution pumped through. The utility of the microcapillaries has been showcased on particle traps in which biological cells are probed for single-cell impedance spectroscopy. The approach disclosed, given its full compatibility with semiconductor device fabrication, offers great potential towards intelligent cell and molecule-based devices merging microelectronics and microfluidics.

A Physically Transient Form of Silicon Electronics, With Integrated Sensors, Actuators and Power Supply

PubMed Central

Hwang, Suk-Won; Tao, Hu; Kim, Dae-Hyeong; Cheng, Huanyu; Song, Jun-Kyul; Rill, Elliott; Brenckle, Mark A.; Panilaitis, Bruce; Won, Sang Min; Kim, Yun-Soung; Yu, Ki Jun; Ameen, Abid; Li, Rui; Su, Yewang; Yang, Miaomiao; Kaplan, David L.; Zakin, Mitchell R.; Slepian, Marvin J.; Huang, Yonggang; Omenetto, Fiorenzo G.; Rogers, John A.

2013-01-01

A remarkable feature of modern silicon electronics is its ability to remain functionally and physically invariant, almost indefinitely for many practical purposes. Here, we introduce a silicon-based technology that offers the opposite behavior: it gradually vanishes over time, in a well-controlled, programmed manner. Devices that are ‘transient’ in this sense create application possibilities that cannot be addressed with conventional electronics, such as active implants that exist for medically useful timeframes, but then completely dissolve and disappear via resorption by the body. We report a comprehensive set of materials, manufacturing schemes, device components and theoretical design tools for a complementary metal oxide semiconductor (CMOS) electronics of this type, together with four different classes of sensors and actuators in addressable arrays, two options for power supply and a wireless control strategy. A transient silicon device capable of delivering thermal therapy in an implantable mode and its demonstration in animal models illustrate a system-level example of this technology. PMID:23019646

Resonator-Based Silicon Electro-Optic Modulator with Low Power Consumption

NASA Astrophysics Data System (ADS)

Xin, Maoqing; Danner, Aaron J.; Eng Png, Ching; Thor Lim, Soon

2009-04-01

This paper demonstrates, via simulation, an electro-optic modulator based on a subwavelength Fabry-Perot resonator cavity with low power consumption of 86 µW/µm. This is, to the best of our knowledge, the lowest power reported for silicon photonic bandgap modulators. The device is modulated at a doped p-i-n junction overlapping the cavity in a silicon waveguide perforated with etched holes, with the doping area optimized for minimum power consumption. The surface area of the entire device is only 2.1 µm2, which compares favorably to other silicon-based modulators. A modulation speed of at least 300 MHz is detected from the electrical simulator after sidewall doping is introduced which is suitable for sensing or fiber to the home (FTTH) technologies, where speed can be traded for low cost and power consumption. The device does not rely on ultra-high Q, and could serve as a sensor, modulator, or passive filter with built-in calibration.

Next-generation digital camera integration and software development issues

NASA Astrophysics Data System (ADS)

Venkataraman, Shyam; Peters, Ken; Hecht, Richard

1998-04-01

This paper investigates the complexities associated with the development of next generation digital cameras due to requirements in connectivity and interoperability. Each successive generation of digital camera improves drastically in cost, performance, resolution, image quality and interoperability features. This is being accomplished by advancements in a number of areas: research, silicon, standards, etc. As the capabilities of these cameras increase, so do the requirements for both hardware and software. Today, there are two single chip camera solutions in the market including the Motorola MPC 823 and LSI DCAM- 101. Real time constraints for a digital camera may be defined by the maximum time allowable between capture of images. Constraints in the design of an embedded digital camera include processor architecture, memory, processing speed and the real-time operating systems. This paper will present the LSI DCAM-101, a single-chip digital camera solution. It will present an overview of the architecture and the challenges in hardware and software for supporting streaming video in such a complex device. Issues presented include the development of the data flow software architecture, testing and integration on this complex silicon device. The strategy for optimizing performance on the architecture will also be presented.

Application of MEMS-based x-ray optics as tuneable nanosecond choppers

NASA Astrophysics Data System (ADS)

Chen, Pice; Walko, Donald A.; Jung, Il Woong; Li, Zhilong; Gao, Ya; Shenoy, Gopal K.; Lopez, Daniel; Wang, Jin

2017-08-01

Time-resolved synchrotron x-ray measurements often rely on using a mechanical chopper to isolate a set of x-ray pulses. We have started the development of micro electromechanical systems (MEMS)-based x-ray optics, as an alternate method to manipulate x-ray beams. In the application of x-ray pulse isolation, we recently achieved a pulse-picking time window of half a nanosecond, which is more than 100 times faster than mechanical choppers can achieve. The MEMS device consists of a comb-drive silicon micromirror, designed for efficiently diffracting an x-ray beam during oscillation. The MEMS devices were operated in Bragg geometry and their oscillation was synchronized to x-ray pulses, with a frequency matching subharmonics of the cycling frequency of x-ray pulses. The microscale structure of the silicon mirror in terms of the curvature and the quality of crystallinity ensures a narrow angular spread of the Bragg reflection. With the discussion of factors determining the diffractive time window, this report showed our approaches to narrow down the time window to half a nanosecond. The short diffractive time window will allow us to select single x-ray pulse out of a train of pulses from synchrotron radiation facilities.

Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

PubMed

Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

2017-04-03

We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

Efficient thermoelectric device

NASA Technical Reports Server (NTRS)

Ila, Daryush (Inventor)

2010-01-01

A high efficiency thermo electric device comprising a multi nanolayer structure of alternating insulator and insulator/metal material that is irradiated across the plane of the layer structure with ionizing radiation. The ionizing radiation produces nanocrystals in the layered structure that increase the electrical conductivity and decrease the thermal conductivity thereby increasing the thermoelectric figure of merit. Figures of merit as high as 2.5 have been achieved using layers of co-deposited gold and silicon dioxide interspersed with layers of silicon dioxide. The gold to silicon dioxide ratio was 0.04. 5 MeV silicon ions were used to irradiate the structure. Other metals and insulators may be substituted. Other ionizing radiation sources may be used. The structure tolerates a wide range of metal to insulator ratio.

Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

DTIC Science & Technology

2016-08-01

APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...mechanism on which to base on-chip nonlinear optical devices compatible with a rapidly growing silicon photonics toolbox.3–9 While silicon on insulator

Porous silicon with embedded tritium as a stand-alone prime power source for optoelectronic applications

DOEpatents

Tam, Shiu-Wing

1997-01-01

An illumination source comprising a porous silicon having a source of electrons on the surface and/or interticies thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon.

Porous silicon with embedded tritium as a stand-alone prime power source for optoelectronic applications

DOEpatents

Tam, Shiu-Wing

1998-01-01

An illumination source comprising a porous silicon having a source of electrons on the surface and/or interticies thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon.

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

NASA Astrophysics Data System (ADS)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Improvement of screening methods for silicon planar semiconductor devices

NASA Technical Reports Server (NTRS)

Berger, W. M.

1972-01-01

The results of the program for the development of a more sensitive method for selecting silicon planar semiconductor devices for long life applications are reported. The manufacturing technologies (MOS and Bipolar) are discussed along with the screening procedures developed as a result of the tests and evaluations, and the effectiveness of the MOS and Bilayer screening procedures are evaluated.

High-Temperature Electronics: A Role for Wide Bandgap Semiconductors?

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Okojie, Robert S.; Chen, Liang-Yu

2002-01-01

It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Si/Ge elatform for lasers, amplifiers, and nonlinear optical devices based on the Raman Effect

NASA Astrophysics Data System (ADS)

Claps, Ricardo; Dimitropoulos, Dimitrios; Raghunathan, Varun; Fathpour, Sasan; Jalali, Bahram; Jusserand, Bernard

2007-02-01

The use of a silicon-germanium platform for the development of optically active devices will be discussed in this paper, from the perspective of Raman and Brillouin scattering phenomena. Silicon-Germanium is becoming a prevalent technology for the development of high speed CMOS transistors, with advances in several key parameters as high carrier mobility, low cost, and reduced manufacturing logistics. Traditionally, Si-Ge structures have been used in the optoelectronics arena as photodetectors, due to the enhanced absorption of Ge in the telecommunications band. Recent developments in Raman-based nonlinearities for devices based on a silicon-on-insulator platform have shed light on the possibility of using these effects in Si-Ge architectures. Lasing and amplification have been demonstrated using a SiGe alloy structure, and Brillouin/Raman activity from acoustic phonon modes in SiGe superlattices has been predicted. Moreover, new Raman-active branches and inhomogeneously broadened spectra result from optical phonon modes, offering new perspectives for optical device applications. The possibilities for an electrically-pumped Raman laser will be outlined, and the potential for design and development of silicon-based, Tera-Hertz wave emitters and/or receivers.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Tungsten bridge for the low energy ignition of explosive and energetic materials

DOEpatents

Benson, David A.; Bickes, Jr., Robert W.; Blewer, Robert S.

1990-01-01

A tungsten bridge device for the low energy ignition of explosive and energetic materials is disclosed. The device is fabricated on a silicon-on-sapphire substrate which has an insulating bridge element defined therein using standard integrated circuit fabrication techniques. Then, a thin layer of tungsten is selectively deposited on the silicon bridge layer using chemical vapor deposition techniques. Finally, conductive lands are deposited on each end of the tungsten bridge layer to form the device. It has been found that this device exhibits substantially shorter ignition times than standard metal bridges and foil igniting devices. In addition, substantially less energy is required to cause ignition of the tungsten bridge device of the present invention than is required for common metal bridges and foil devices used for the same purpose.

Functionalized ZnO nanowires for microcantilever biosensors with enhanced binding capability.

PubMed

Stassi, Stefano; Chiadò, Alessandro; Cauda, Valentina; Palmara, Gianluca; Canavese, Giancarlo; Laurenti, Marco; Ricciardi, Carlo

2017-04-01

An efficient way to increase the binding capability of microcantilever biosensors is here demonstrated by growing zinc oxide nanowires (ZnO NWs) on their active surface. A comprehensive evaluation of the chemical compatibility of ZnO NWs brought to the definition of an innovative functionalization method able to guarantee the proper immobilization of biomolecules on the nanostructured surface. A noteworthy higher amount of grafted molecules was evidenced with colorimetric assays on ZnO NWs-coated devices, in comparison with functionalized and activated silicon flat samples. ZnO NWs grown on silicon microcantilever arrays and activated with the proposed immobilization strategy enhanced the sensor binding capability (and thus the dynamic range) of nearly 1 order of magnitude, with respect to the commonly employed flat functionalized silicon devices. Graphical Abstract An efficient way to increase the binding capability of microcantilever biosensors is represented by growing zinc oxide nanowires (ZnO NWs) on their active surface. ZnO NWs grown on silicon microcantilever arrays and activated with an innovative immobilization strategy enhanced the sensor binding capability of nearly 1 order of magnitude, with respect to the commonly employed flat functionalized silicon devices.

Black silicon significantly enhances phosphorus diffusion gettering.

PubMed

Pasanen, Toni P; Laine, Hannu S; Vähänissi, Ville; Schön, Jonas; Savin, Hele

2018-01-31

Black silicon (b-Si) is currently being adopted by several fields of technology, and its potential has already been demonstrated in various applications. We show here that the increased surface area of b-Si, which has generally been considered as a drawback e.g. in applications that require efficient surface passivation, can be used as an advantage: it enhances gettering of deleterious metal impurities. We demonstrate experimentally that interstitial iron concentration in intentionally contaminated silicon wafers reduces from 1.7 × 10 13  cm -3 to less than 10 10  cm -3 via b-Si gettering coupled with phosphorus diffusion from a POCl 3 source. Simultaneously, the minority carrier lifetime increases from less than 2 μs of a contaminated wafer to more than 1.5 ms. A series of different low temperature anneals suggests segregation into the phosphorus-doped layer to be the main gettering mechanism, a notion which paves the way of adopting these results into predictive process simulators. This conclusion is supported by simulations which show that the b-Si needles are entirely heavily-doped with phosphorus after a typical POCl 3 diffusion process, promoting iron segregation. Potential benefits of enhanced gettering by b-Si include the possibility to use lower quality silicon in high-efficiency photovoltaic devices.

Deoxyribonucleic acid (DNA) cladding layers for nonlinear-optic-polymer-based electro-optic devices

NASA Astrophysics Data System (ADS)

Grote, James G.; Ogata, Naoya; Diggs, Darnell E.; Hopkins, Frank K.

2003-07-01

Nonlinear optic (NLO) polymer based electro-optic devices have been achieving world record low half wave voltages and high frequencies over the last 2-3 years. Part of the advancement is through the use of relatively more conductive polymers for the cladding layers. Based on the current materials available for these cladding materials, however, the desired optical and electromagnetic properites are being balanced for materials processability. One does not want the solvent present in one layer to dissovle the one deposited underneath, or be dissolved by the one being deposited on top. Optimized polymer cladding materials, to further enhance device performance, are continuing to be investigated. Thin films of deoxyribonucleic acid (DNA), derived from salmon sperm, show promise in providing both the desired optical and magnetic properties, as well as the desired resistance to various solvents used for NLO polymer device fabrication. Thin films of DNA were deposited on glass and silicon substrates and the film quality, optical and electromagnetic properties and resistance to various solvents were characterized.

Modified laser-annealing process for improving the quality of electrical P-N junctions and devices

DOEpatents

Wood, Richard F.; Young, Rosa T.

1984-01-01

The invention is a process for producing improved electrical-junction devices. The invention is applicable, for example, to a process in which a light-sensitive electrical-junction device is produced by (1) providing a body of crystalline semiconductor material having a doped surface layer, (2) irradiating the layer with at least one laser pulse to effect melting of the layer, (3) permitting recrystallization of the melted layer, and (4) providing the resulting body with electrical contacts. In accordance with the invention, the fill-factor and open-circuit-voltage parameters of the device are increased by conducting the irradiation with the substrate as a whole at a selected elevated temperature, the temperature being selected to effect a reduction in the rate of the recrystallization but insufficient to effect substantial migration of impurities within the body. In the case of doped silicon substrates, the substrate may be heated to a temperature in the range of from about 200.degree. C. to 500.degree. C.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Iodine enhanced focused-ion-beam etching of silicon for photonic applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schrauwen, Jonathan; Thourhout, Dries van; Baets, Roel

Focused-ion-beam etching of silicon enables fast and versatile fabrication of micro- and nanophotonic devices. However, large optical losses due to crystal damage and ion implantation make the devices impractical when the optical mode is confined near the etched region. These losses are shown to be reduced by the local implantation and etching of silicon waveguides with iodine gas enhancement, followed by baking at 300 deg. C. The excess optical loss in the silicon waveguides drops from 3500 to 1700 dB/cm when iodine gas is used, and is further reduced to 200 dB/cm after baking at 300 deg. C. We presentmore » elemental and chemical surface analyses supporting that this is caused by the desorption of iodine from the silicon surface. Finally we present a model to extract the absorption coefficient from the measurements.« less

Viscoelastic properties of a spinal posterior dynamic stabilisation device.

PubMed

Lawless, Bernard M; Barnes, Spencer C; Espino, Daniel M; Shepherd, Duncan E T

2016-06-01

The purpose of this study was to quantify the frequency dependent viscoelastic properties of two types of spinal posterior dynamic stabilisation devices. In air at 37°C, the viscoelastic properties of six BDyn 1 level, six BDyn 2 level posterior dynamic stabilisation devices (S14 Implants, Pessac, France) and its elastomeric components (polycarbonate urethane and silicone) were measured using Dynamic Mechanical Analysis. The viscoelastic properties were measured over the frequency range 0.01-30Hz. The BDyn devices and its components were viscoelastic throughout the frequency range tested. The mean storage stiffness and mean loss stiffness of the BDyn 1 level device, BDyn 2 level device, silicone component and polycarbonate urethane component all presented a logarithmic relationship with respect to frequency. The storage stiffness of the BDyn 1 level device ranged from 95.56N/mm to 119.29N/mm, while the BDyn 2 level storage stiffness ranged from 39.41N/mm to 42.82N/mm. BDyn 1 level device and BDyn 2 level device loss stiffness ranged from 10.72N/mm to 23.42N/mm and 4.26N/mm to 9.57N/mm, respectively. No resonant frequencies were recorded for the devices or its components. The elastic property of BDyn 1 level device is influenced by the PCU and silicone components, in the physiological frequency range. The viscoelastic properties calculated in this study may be compared to spinal devices and spinal structures. Copyright © 2016 Elsevier Ltd. All rights reserved.

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Broadband transverse magnetic pass polarizer with low insertion loss based on silicon nitride waveguide

NASA Astrophysics Data System (ADS)

Sharma, Tarun Kumar; Ranganath, Praveen; Nambiar, Siddharth; Selvaraja, Shankar Kumar

2018-03-01

A horizontally asymmetric transverse magnetic (TM) pass polarizer is presented. The device passes only TM mode and rejects transverse electric (TE) mode. The proposed device has an asymmetricity in the horizontal direction comprising a direction coupler region with a silicon waveguide, silicon nitride waveguide, and an air gap, all residing on silica. Between three equal width Si waveguides, we have one region filled with air and the other with SiN with unequal optimized widths. The device with its optimal dimensions yields an extremely low insertion loss (IL) of 0.16 dB for TM→TM, while TE is rejected by an IL of >48 dB. The proposed polarizer is operated between C&L bands with a high extinction ratio and broadband width of about 110 nm.

Energy correlations of photon pairs generated by a silicon microring resonator probed by Stimulated Four Wave Mixing.

PubMed

Grassani, Davide; Simbula, Angelica; Pirotta, Stefano; Galli, Matteo; Menotti, Matteo; Harris, Nicholas C; Baehr-Jones, Tom; Hochberg, Michael; Galland, Christophe; Liscidini, Marco; Bajoni, Daniele

2016-04-01

Compact silicon integrated devices, such as micro-ring resonators, have recently been demonstrated as efficient sources of quantum correlated photon pairs. The mass production of integrated devices demands the implementation of fast and reliable techniques to monitor the device performances. In the case of time-energy correlations, this is particularly challenging, as it requires high spectral resolution that is not currently achievable in coincidence measurements. Here we reconstruct the joint spectral density of photons pairs generated by spontaneous four-wave mixing in a silicon ring resonator by studying the corresponding stimulated process, namely stimulated four wave mixing. We show that this approach, featuring high spectral resolution and short measurement times, allows one to discriminate between nearly-uncorrelated and highly-correlated photon pairs.

Sustained prevention of biofilm formation on a novel silicone matrix suitable for medical devices.

PubMed

Steffensen, Søren Langer; Vestergaard, Merete Hedemark; Groenning, Minna; Alm, Martin; Franzyk, Henrik; Nielsen, Hanne Mørck

2015-08-01

Bacterial colonization and biofilm formation on medical devices constitute major challenges in clinical long-term use of e.g. catheters due to the risk of (re)infection of patients, which would result in additional use of antibiotics risking bacterial resistance development. The aim of the present project was to introduce a novel antibacterial approach involving an advanced composite material applicable for medical devices. The polymeric composites investigated consisted of a hydrogel network of cross-linked poly(2-hydroxyethyl methacrylate) (PHEMA) embedded in a poly(dimethylsiloxane) (PDMS) silicone elastomer produced using supercritical carbon dioxide (scCO2). In these materials, the hydrogel may contain an active pharmaceutical ingredient while the silicone elastomer provides the sufficient mechanical stability of the material. In these conceptual studies, the antimicrobial agent ciprofloxacin was loaded into the polymer matrix by a post-polymerization loading procedure. Sustained release of ciprofloxacin was demonstrated, and the release could be controlled by varying the hydrogel content in the range 13-38% (w/w) and by changing the concentration of ciprofloxacin during loading in the range of 1-20mg/mL. Devices containing 25% (w/w) hydrogel and loaded with ciprofloxacin displayed a strong antibacterial effect against Staphylococcus aureus bacterial colonization and subsequent biofilm formation on the device material was inhibited for 29days. In conclusion, the hydrogel/silicone composite represents a promising candidate material for medical devices that prevent bacterial colonization during long-term use. Copyright © 2015 Elsevier B.V. All rights reserved.

Recent advances in small molecule OLED-on-silicon microdisplays

NASA Astrophysics Data System (ADS)

Ghosh, Amalkumar P.; Ali, Tariq A.; Khayrullin, Ilyas; Vazan, Fridrich; Prache, Olivier F.; Wacyk, Ihor

2009-08-01

High resolution OLED-on-silicon microdisplay technology is unique and challenging since it requires very small subpixel dimensions (~ 2-5 microns). eMagin's OLED microdisplay is based on white top emitter architecture using small molecule organic materials. The devices are fabricated using high Tg materials. The devices are hermetically sealed with vacuum deposited thin film layers. LCD-type color filters are patterned using photolithography methods to generate primary R, G, B colors. Results of recent improvements in the OLED-on-silicon microdisplay technology, with emphasis on efficiencies, lifetimes, grey scale and CIE color coordinates for SVGA and SXGA resolution microdisplays is presented.

A MEMS Infrared Thermopile Fabricated from Silicon-On-Insulator with Phononic Crystal Structures and Carbon Nanotube Absorption Layer

NASA Astrophysics Data System (ADS)

Gray, Kory Forrest

The goal of this project was to examine the possibility of creating a novel thermal infrared detector based on silicon CMOS technology that has been enhanced by the latest nano-engineering discoveries. Silicon typically is not thought as an efficient thermoelectric material. However recent advancements in nanotechnology have improved the potential for a highly sensitive infrared detector based on nano-structured silicon. The thermal conductivity of silicon has been shown to be reduced from 150 W/mK down to 60 W/mK just by decreasing the scale of the silicon from bulk down to the sub-micron scale. Further reduction of the thermal conductivity has been shown by patterning silicon with a phonon crystal structure which has been reported to have thermal conductivities down to 10 W/mK. The phonon crystal structure consists of a 2D array of holes that are etched into the silicon. The size and pitch of the holes are on the order of the mean free path of the phonons in silicon which is approximately 200-500nm. This particular device had 200nm holes on a 400nm pitch. The Seebeck coefficient of silicon can also be enhanced by the reduction of the material from the bulk to sub-micron scale and with degenerate level doping. The combination of decreased thermal conductivity and increased Seebeck coefficient allow silicon to be a promising material for thermoelectric infrared detectors. The highly doped silicon is desired to reduce the electrical resistance of the device. The low electrical resistance is required to reduce the Johnson noise of the device which is the dominant noise source for most thermal detectors. This project designed a MEMS thermopile using a silicon-on-insulator substrate, and a CMOS compatible process. The basic thermopile consists of a silicon dioxide membrane with phononic crystal patterned silicon thermocouples around the edges of the membrane. Vertical aligned, multi-walled, carbon nanotubes were used as the infrared absorption layer. A MEMS thermoelectric detector with a D* of 3 * 107 cm Hz 0.5/W was demonstrated with a time response of 3-10 milliseconds. With this initial research, it is possible to improve the D* to the high 108 cm Hz 0.5/W range by slightly changing the design of the thermopile and patterning the absorption layer.

Ion beam figuring of silicon aspheres

NASA Astrophysics Data System (ADS)

Demmler, Marcel; Zeuner, Michael; Luca, Alfonz; Dunger, Thoralf; Rost, Dirk; Kiontke, Sven; Krüger, Marcus

2011-03-01

Silicon lenses are widely used for infrared applications. Especially for portable devices the size and weight of the optical system are very important factors. The use of aspherical silicon lenses instead of spherical silicon lenses results in a significant reduction of weight and size. The manufacture of silicon lenses is more challenging than the manufacture of standard glass lenses. Typically conventional methods like diamond turning, grinding and polishing are used. However, due to the high hardness of silicon, diamond turning is very difficult and requires a lot of experience. To achieve surfaces of a high quality a polishing step is mandatory within the manufacturing process. Nevertheless, the required surface form accuracy cannot be achieved through the use of conventional polishing methods because of the unpredictable behavior of the polishing tools, which leads to an unstable removal rate. To overcome these disadvantages a method called Ion Beam Figuring can be used to manufacture silicon lenses with high surface form accuracies. The general advantage of the Ion Beam Figuring technology is a contactless polishing process without any aging effects of the tool. Due to this an excellent stability of the removal rate without any mechanical surface damage is achieved. The related physical process - called sputtering - can be applied to any material and is therefore also applicable to materials of high hardness like Silicon (SiC, WC). The process is realized through the commercially available ion beam figuring system IonScan 3D. During the process, the substrate is moved in front of a focused broad ion beam. The local milling rate is controlled via a modulated velocity profile, which is calculated specifically for each surface topology in order to mill the material at the associated positions to the target geometry. The authors will present aspherical silicon lenses with very high surface form accuracies compared to conventionally manufactured lenses.

System and method for liquid silicon containment

DOEpatents

Cliber, James A; Clark, Roger F; Stoddard, Nathan G; Von Dollen, Paul

2013-05-28

This invention relates to a system and a method for liquid silicon containment, such as during the casting of high purity silicon used in solar cells or solar modules. The containment apparatus includes a shielding member adapted to prevent breaching molten silicon from contacting structural elements or cooling elements of a casting device, and a volume adapted to hold a quantity of breaching molten silicon with the volume formed by a bottom and one or more sides.

System and method for liquid silicon containment

DOEpatents

Cliber, James A; Clark, Roger F; Stoddard, Nathan G; Von Dollen, Paul

2014-06-03

This invention relates to a system and a method for liquid silicon containment, such as during the casting of high purity silicon used in solar cells or solar modules. The containment apparatus includes a shielding ember adapted to prevent breaching molten silicon from contacting structural elements or cooling elements of a casting device, and a volume adapted to hold a quantity of breaching molten silicon with the volume formed by a bottom and one or more sides.

Forward-bias diode parameters, electronic noise, and photoresponse of graphene/silicon Schottky junctions with an interfacial native oxide layer

NASA Astrophysics Data System (ADS)

An, Yanbin; Behnam, Ashkan; Pop, Eric; Bosman, Gijs; Ural, Ant

2015-09-01

Metal-semiconductor Schottky junction devices composed of chemical vapor deposition grown monolayer graphene on p-type silicon substrates are fabricated and characterized. Important diode parameters, such as the Schottky barrier height, ideality factor, and series resistance, are extracted from forward bias current-voltage characteristics using a previously established method modified to take into account the interfacial native oxide layer present at the graphene/silicon junction. It is found that the ideality factor can be substantially increased by the presence of the interfacial oxide layer. Furthermore, low frequency noise of graphene/silicon Schottky junctions under both forward and reverse bias is characterized. The noise is found to be 1/f dominated and the shot noise contribution is found to be negligible. The dependence of the 1/f noise on the forward and reverse current is also investigated. Finally, the photoresponse of graphene/silicon Schottky junctions is studied. The devices exhibit a peak responsivity of around 0.13 A/W and an external quantum efficiency higher than 25%. From the photoresponse and noise measurements, the bandwidth is extracted to be ˜1 kHz and the normalized detectivity is calculated to be 1.2 ×109 cm Hz1/2 W-1. These results provide important insights for the future integration of graphene with silicon device technology.

Obstacles using amorphous materials for volume applications

NASA Astrophysics Data System (ADS)

Kiessling, Albert; Reininger, Thomas

2012-10-01

This contribution is especially focussed on the attempt to use amorphous or nanocrystalline metals in position sensor applications and to describe the difficulties and obstacles encountered in coherence with the development of appropriate industrial high volume series products in conjunction with the related quality requirements. The main motivation to do these investigations was to beat the generally known sensors especially silicon based Hall-sensors as well as AMR- and GMR-sensors - well known from mobile phones and electronic storage devices like hard discs and others - in terms of cost-effectiveness and functionality.

Complementary metal-oxide semiconductor compatible source of single photons at near-visible wavelengths

NASA Astrophysics Data System (ADS)

Cernansky, Robert; Martini, Francesco; Politi, Alberto

2018-02-01

We demonstrate on chip generation of correlated pairs of photons in the near-visible spectrum using a CMOS compatible PECVD Silicon Nitride photonic device. Photons are generated via spontaneous four wave mixing enhanced by a ring resonator with high quality Q-factor of 320,000 resulting in a generation rate of 950,000 $\\frac{pairs}{mW}$. The high brightness of this source offers the opportunity to expand photonic quantum technologies over a broad wavelength range and provides a path to develop fully integrated quantum chips working at room temperature.

Planarised optical fiber composite using flame hydrolysis deposition demonstrating an integrated FBG anemometer.

PubMed

Holmes, Christopher; Gates, James C; Smith, Peter G R

2014-12-29

This paper reports for the first time a planarised optical fiber composite formed using Flame Hydrolysis Deposition (FHD). As a way of format demonstration a Micro-Opto-Electro-Mechanical (MOEMS) hot wire anemometer is formed using micro-fabrication processing. The planarised device is rigidly secured to a silicon wafer using optical quality doped silica that has been deposited using flame hydrolysis and consolidated at high temperature. The resulting structure can withstand temperatures exceeding 580K and is sensitive enough to resolve free and forced convection interactions at low fluid velocity.

Modeling and characterization of shielded low loss CPWs on 65 nm node silicon

NASA Astrophysics Data System (ADS)

Hongrui, Wang; Dongxu, Yang; Li, Zhang; Lei, Zhang; Zhiping, Yu

2011-06-01

Coplanar waveguides (CPWs) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65 nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R and G parameters. Starting with a basic CPW structure, the slow-wave effect and ground-shield influence have been analyzed and incorporated into the general model. The accuracy of the model is confirmed by experimental results.

Wavelength dispersion characteristics of integrated silicon avalanche LEDs: potential applications in futuristic on-chip micro- and nano-biosensors

NASA Astrophysics Data System (ADS)

Okhai, Timothy A.; Snyman, Lukas W.; Polleux, Jean-Luc

2016-02-01

Si Av LEDs are easily integrated in on-chip integrated circuitry. They have high modulation frequencies into the GHz range and can be fabricated to sub-micron dimensions. Due to subsurface light generation in the silicon device itself, and the high refractive index differences between silicon and the device environment, the exiting light radiation has interesting dispersion characteristics. Three junction micro p+-np+ Silicon Avalanche based Light Emitting Devices (Si Av LEDs) have been analyzed in terms of dispersion characteristics, generally resulting in different wavelengths of light (colors) being emitted at different angles and solid angles from the surfaces of these devices. The emission wavelength is in the 450 - 850 nm range. The devices are of micron dimension and operate at 8 - 10V, 1μA - 2mA. The emission spot sizes are about 1 micron square. Emission intensities are up to 500 nW.μm-2. The observed dispersion characteristics range from 0.05 degrees per nm per degree at emission angle of 5 degrees, to 0.15 degrees per nm at emission angles of 30 degrees. It is believed that the dispersion characteristics can find interesting and futuristic on-chip electro-optic applications involving particularly a ranging from on chip micro optical wavelength dispersers, communication de-multiplexers, and novel bio-sensor applications. All of these could penetrate into the nanoscale dimensions.

A flexible piezoresistive carbon black network in silicone rubber for wide range deformation and strain sensing

NASA Astrophysics Data System (ADS)

Zhu, Jianxiong; Wang, Hai; Zhu, Yali

2018-01-01

This work presents the design, fabrication, and measurement of a piezoresistive device with a carbon black (CB) particle network in a highly flexible silicone rubber for large deformation and wide range strain sensing. The piezoresistive composite film was fabricated with a mixture of silicone rubber and CB filler particles. The test results showed that the CB particle network in the silicone rubber strongly affected the resistance of the device during the process of drawing and its recovery. We found that the 50% volume ratio of CB filler particles showed a lower relative resistance than the 33.3% volume ratio of CB filler particles, but with an advantage of good resistance recovery stability and a smaller perturbation error (smaller changed resistance) during the periodic back and forth linear motor test. With both having a 50% volume ratio of CB filler particles and a 33.3% volume ratio of CB filler particles, one can reach up to 200% strain with resistances 18 kΩ and 110 kΩ, respectively. We also found that the relative resistance increased in an approximately linear relationship corresponding to the value of step-increased instantaneous length for the reported device. Moreover, an application test through hand drawing was used to demonstrate the piezoresistive performance of the device, which showed that the reported device was capable of measuring the instantaneous length with large deformation.

Cleaning up Silicon

NASA Technical Reports Server (NTRS)

2000-01-01

A development program that started in 1975 between Union Carbide and JPL, led to Advanced Silicon Materials LLC's, formerly ASiMI, commercial process for producing silane in viable quantities. The process was expanded to include the production of high-purity polysilicon for electronic devices. The technology came out of JPL's Low Cost Silicon Array Project.

Area Reports. Advanced materials and devices research area. Silicon materials research task, and advanced silicon sheet task

NASA Technical Reports Server (NTRS)

1986-01-01

The objectives of the Silicon Materials Task and the Advanced Silicon Sheet Task are to identify the critical technical barriers to low-cost silicon purification and sheet growth that must be overcome to produce a PV cell substrate material at a price consistent with Flat-plate Solar Array (FSA) Project objectives and to overcome these barriers by performing and supporting appropriate R&D. Progress reports are given on silicon refinement using silane, a chemical vapor transport process for purifying metallurgical grade silicon, silicon particle growth research, and modeling of silane pyrolysis in fluidized-bed reactors.

Method for fabricating pixelated silicon device cells

DOEpatents

Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis; Nelson, Jeffrey S.; Anderson, Benjamin John

2015-08-18

A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps.

Porous silicon with embedded tritium as a stand-alone prime power source for optoelectronic applications

DOEpatents

Tam, S.W.

1998-06-16

An illumination source is disclosed comprising a porous silicon having a source of electrons on the surface and/or interstices thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon. 1 fig.

Porous silicon with embedded tritium as a stand-alone prime power source for optoelectronic applications

DOEpatents

Tam, S.W.

1997-02-25

Disclosed is an illumination source comprising a porous silicon having a source of electrons on the surface and/or interstices thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon. 1 fig.

Silicon Schottky Diode Safe Operating Area

NASA Technical Reports Server (NTRS)

Casey, Megan C.; Campola, Michael J.; Lauenstein, Jean-Marie; Wilcox, Edward P.; Phan, Anthony M.; LaBel, Kenneth A.

2016-01-01

Vulnerability of a variety of candidate spacecraft electronics to total ionizing dose and displacement damage is studied. Devices tested include optoelectronics, digital, analog, linear bipolar devices, and hybrid devices.

A Theoretical Search for Supervelocity Semiconductors

DTIC Science & Technology

1992-10-01

interfaces, doping control and compositional uniformity with atomic level dimensions. The development of ALE may very well prove to be the ultimate growth...pseudomorphic or strained-layer devices. These structures permit extended compositional ranges and, thus, have a number of potential advantages such as...in silicon devices For the past fifteen years, the silicon MOSFET industry has been dealing increasingly with prob- lems related to hot electron

Radiation Effects on the Electrical Properties of Hafnium Oxide Based MOS Capacitors

DTIC Science & Technology

2011-03-01

Figures Figure Page 1. Conceptual illustration of the creation of electron-hole pairs and displacement damage in a n -type silicon metal-oxide-silicon...Illustration of the effect, in a CV plot, of oxide trapped charge for a hypothetical n -type device...8 5. Illustration of the effect, in a CV plot, of interface trapped charge for a hypothetical n -type device

Proceedings of the Flat-plate Solar Array Project Research Forum on High-efficiency Crystalline Silicon Solar Cells

NASA Technical Reports Server (NTRS)

Kachare, R.

1985-01-01

The high-efficiency crystalline silicon solar cells research forum addressed high-efficiency concepts, surface-interface effects, bulk effects, modeling and device processing. The topics were arranged into six interactive sessions, which focused on the state-of-the-art of device structures, identification of barriers to achieve high-efficiency cells and potential ways to overcome these barriers.

R&D issues in scale-up and manufacturing of amorphous silicon tandem modules

NASA Astrophysics Data System (ADS)

Arya, R. R.; Carlson, D. E.; Chen, L. F.; Ganguly, G.; He, M.; Lin, G.; Middya, R.; Wood, G.; Newton, J.; Bennett, M.; Jackson, F.; Willing, F.

1999-03-01

R & D on amorphous silicon based tandem junction devices has improved the throughtput, the material utilization, and the performance of devices on commercial tin oxide coated glass. The tandem junction technology has been scaled-up to produce 8.6 Ft2 monolithically integrated modules in manufacturing at the TF1 plant. Optimization of performance and stability of these modules is ongoing.

New ways to develop biosensors towards addressing practical problems

NASA Astrophysics Data System (ADS)

Starodub, N. F.

2013-11-01

The main modern approaches which were realized at the development of new generation of biosensors intended for application in field of diagnostics, food quality control and environmental monitoring are presented. The main attention was paid to creation of the multi-parametrical and multi-functional enzymatic and immune biosensors which were realized for the complex diagnostics of diabetes, autoimmune state and for the control of process of sugar production. The label-free bioaffine devices based on the nano-porouse silicon (NPS) with the registration of specific formed signal by chemiluminescence (ChL) and photoresistivity and intended for the determination mycotoxins and diagnostics of retroviral bovine leukemia (RBL) are analyzed too. Improving of ion sensitive field effect transistors (ISFETs) through changing silicon nitride on the cerium oxide is discussed as perspective approach in case of micotoxins and Salmonella control. In the conclusion the possibility to replace biological sensitive elements by artificial ones is considered.

Alpha Radiation Effects on Silicon Oxynitride Waveguides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morichetti, Francesco; Grillanda, Stefano; Manandhar, Sandeep

2016-09-21

Photonic technologies are today of great interest for use in harsh environments, such as outer space, where they can potentially replace current communication systems based on radiofrequency components. However, very much alike to electronic devices, the behavior of optical materials and circuits can be strongly altered by high-energy and high-dose ionizing radiations. Here, we investigate the effects of alpha () radiation with MeV-range energy on silicon oxynitride (SiON) optical waveguides. Irradiation with a dose of 5×1015 cm-2 increases the refractive index of the SiON core by nearly 10-2, twice as much that of the surrounding silica cladding, leading to amore » significant increase of the refractive index contrast of the waveguide. The higher mode confinement induced by -radiation reduces the loss of tightly bent waveguides. We show that this increases the quality factor of microring resonators by 20%, with values larger than 105 after irradiation.« less

Core-shell heterojunction of silicon nanowire arrays and carbon quantum dots for photovoltaic devices and self-driven photodetectors.

PubMed

Xie, Chao; Nie, Biao; Zeng, Longhui; Liang, Feng-Xia; Wang, Ming-Zheng; Luo, Linbao; Feng, Mei; Yu, Yongqiang; Wu, Chun-Yan; Wu, Yucheng; Yu, Shu-Hong

2014-04-22

Silicon nanostructure-based solar cells have lately intrigued intensive interest because of their promising potential in next-generation solar energy conversion devices. Herein, we report a silicon nanowire (SiNW) array/carbon quantum dot (CQD) core-shell heterojunction photovoltaic device by directly coating Ag-assisted chemical-etched SiNW arrays with CQDs. The heterojunction with a barrier height of 0.75 eV exhibited excellent rectifying behavior with a rectification ratio of 10(3) at ±0.8 V in the dark and power conversion efficiency (PCE) as high as 9.10% under AM 1.5G irradiation. It is believed that such a high PCE comes from the improved optical absorption as well as the optimized carrier transfer and collection capability. Furthermore, the heterojunction could function as a high-performance self-driven visible light photodetector operating in a wide switching wavelength with good stability, high sensitivity, and fast response speed. It is expected that the present SiNW array/CQD core-shell heterojunction device could find potential applications in future high-performance optoelectronic devices.

A conformal, bio-interfaced class of silicon electronics for mapping cardiac electrophysiology.

PubMed

Viventi, Jonathan; Kim, Dae-Hyeong; Moss, Joshua D; Kim, Yun-Soung; Blanco, Justin A; Annetta, Nicholas; Hicks, Andrew; Xiao, Jianliang; Huang, Younggang; Callans, David J; Rogers, John A; Litt, Brian

2010-03-24

In all current implantable medical devices such as pacemakers, deep brain stimulators, and epilepsy treatment devices, each electrode is independently connected to separate control systems. The ability of these devices to sample and stimulate tissues is hindered by this configuration and by the rigid, planar nature of the electronics and the electrode-tissue interfaces. Here, we report the development of a class of mechanically flexible silicon electronics for multiplexed measurement of signals in an intimate, conformal integrated mode on the dynamic, three-dimensional surfaces of soft tissues in the human body. We demonstrate this technology in sensor systems composed of 2016 silicon nanomembrane transistors configured to record electrical activity directly from the curved, wet surface of a beating porcine heart in vivo. The devices sample with simultaneous submillimeter and submillisecond resolution through 288 amplified and multiplexed channels. We use this system to map the spread of spontaneous and paced ventricular depolarization in real time, at high resolution, on the epicardial surface in a porcine animal model. This demonstration is one example of many possible uses of this technology in minimally invasive medical devices.

High Performance MgO-barrier Magnetic Tunnel Junctions for Flexible and Wearable Spintronic Applications

PubMed Central

Chen, Jun-Yang; Lau, Yong-Chang; Coey, J. M. D.; Li, Mo; Wang, Jian-Ping

2017-01-01

The magnetic tunnel junction (MTJ) using MgO barrier is one of most important building blocks for spintronic devices and has been widely utilized as miniaturized magentic sensors. It could play an important role in wearable medical devices if they can be fabricated on flexible substrates. The required stringent fabrication processes to obtain high quality MgO-barrier MTJs, however, limit its integration with flexible electronics devices. In this work, we have developed a method to fabricate high-performance MgO-barrier MTJs directly onto ultrathin flexible silicon membrane with a thickness of 14 μm and then transfer-and-bond to plastic substrates. Remarkably, such flexible MTJs are fully functional, exhibiting a TMR ratio as high as 190% under bending radii as small as 5 mm. The devices‘ robustness is manifested by its retained excellent performance and unaltered TMR ratio after over 1000 bending cycles. The demonstrated flexible MgO-barrier MTJs opens the door to integrating high-performance spintronic devices in flexible and wearable electronics devices for a plethora of biomedical sensing applications. PMID:28150807

Cost-effective rapid prototyping and assembly of poly(methyl methacrylate) microfluidic devices.

PubMed

Matellan, Carlos; Del Río Hernández, Armando E

2018-05-03

The difficulty in translating conventional microfluidics from laboratory prototypes to commercial products has shifted research efforts towards thermoplastic materials for their higher translational potential and amenability to industrial manufacturing. Here, we present an accessible method to fabricate and assemble polymethyl methacrylate (PMMA) microfluidic devices in a "mask-less" and cost-effective manner that can be applied to manufacture a wide range of designs due to its versatility. Laser micromachining offers high flexibility in channel dimensions and morphology by controlling the laser properties, while our two-step surface treatment based on exposure to acetone vapour and low-temperature annealing enables improvement of the surface quality without deformation of the device. Finally, we demonstrate a capillarity-driven adhesive delivery bonding method that can produce an effective seal between PMMA devices and a variety of substrates, including glass, silicon and LiNbO 3 . We illustrate the potential of this technique with two microfluidic devices, an H-filter and a droplet generator. The technique proposed here offers a low entry barrier for the rapid prototyping of thermoplastic microfluidics, enabling iterative design for laboratories without access to conventional microfabrication equipment.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

10 μ m-thick four-quadrant transmissive silicon photodiodes for beam position monitor application: electrical characterization and gamma irradiation effects

NASA Astrophysics Data System (ADS)

Rafí, J. M.; Pellegrini, G.; Quirion, D.; Hidalgo, S.; Godignon, P.; Matilla, O.; Juanhuix, J.; Fontserè, A.; Molas, B.; Pothin, D.; Fajardo, P.

2017-01-01

Silicon photodiodes are very useful devices as X-ray beam monitors in synchrotron radiation beamlines. Owing to Si absorption, devices thinner than 10 μ m are needed to achieve transmission over 90% for energies above 10 keV . In this work, new segmented four-quadrant diodes for beam alignment purposes are fabricated on both ultrathin (10 μ m-thick) and bulk silicon substrates. Four-quadrant diodes implementing different design parameters as well as auxiliary test structures (single diodes and MOS capacitors) are studied. An extensive electrical characterization, including current-voltage (I-V) and capacitance-voltage (C-V) techniques, is carried out on non-irradiated and gamma-irradiated devices up to 100 Mrad doses. Special attention is devoted to the study of radiation-induced charge build-up in diode interquadrant isolation dielectric, as well as its impact on device interquadrant resistance. Finally, the devices have been characterized with an 8 keV laboratory X-ray source at 108 ph/s and in BL13-XALOC ALBA Synchroton beamline with 1011 ph/s and energies from 6 to 16 keV . Sensitivity, spatial resolution and uniformity of the devices have been evaluated.

Multijunction photovoltaic device and fabrication method

DOEpatents

Arya, Rajeewa R.; Catalano, Anthony W.

1993-09-21

A multijunction photovoltaic device includes first and second amorphous silicon PIN photovoltaic cells in a stacked arrangement. An interface layer, composed of a doped silicon compound, is disposed between the two cells and has a lower bandgap than the respective n- and p-type adjacent layers of the first and second cells. The interface layer forms an ohmic contact with the one or the adjacent cell layers of the same conductivity type, and a tunnel junction with the other of the adjacent cell layers. The disclosed device is fabricated by a glow discharge process.

Silicon Carbide (SiC) Device and Module Reliability, Performance of a Loop Heat Pipe Subjected to a Phase-Coupled Heat Input to an Acceleration Field

DTIC Science & Technology

2016-05-01

AFRL-RQ-WP-TR-2016-0108 SILICON CARBIDE (SiC) DEVICE AND MODULE RELIABILITY Performance of a Loop Heat Pipe Subjected to a Phase-Coupled... Heat Input to an Acceleration Field Kirk L. Yerkes (AFRL/RQQI) and James D. Scofield (AFRL/RQQE) Flight Systems Integration Branch (AFRL/RQQI...CARBIDE (SiC) DEVICE AND MODULE RELIABILITY Performance of a Loop Heat Pipe Subjected to a Phase-Coupled Heat Input to an Acceleration Field 5a

Multiple wavelength silicon photonic 200 mm R+D platform for 25Gb/s and above applications

NASA Astrophysics Data System (ADS)

Szelag, B.; Blampey, B.; Ferrotti, T.; Reboud, V.; Hassan, K.; Malhouitre, S.; Grand, G.; Fowler, D.; Brision, S.; Bria, T.; Rabillé, G.; Brianceau, P.; Hartmann, J. M.; Hugues, V.; Myko, A.; Elleboode, F.; Gays, F.; Fédéli, J. M.; Kopp, C.

2016-05-01

A silicon photonics platform that uses a CMOS foundry line is described. Fabrication process is following a modular integration scheme which leads to a flexible platform, allowing different device combinations. A complete device library is demonstrated for 1310 nm applications with state of the art performances. A PDK which includes specific photonic features and which is compatible with commercial EDA tools has been developed allowing an MPW shuttle service. Finally platform evolutions such as device offer extension to 1550 nm or new process modules introduction are presented.

Growth of a delta-doped silicon layer by molecular beam epitaxy on a charge-coupled device for reflection-limited ultraviolet quantum efficiency

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Grunthaner, Paula J.; Grunthaner, Frank J.; Terhune, R. W.; Fattahi, Masoud; Tseng, Hsin-Fu

1992-01-01

Low-temperature silicon molecular beam epitaxy is used to grow a delta-doped silicon layer on a fully processed charge-coupled device (CCD). The measured quantum efficiency of the delta-doped backside-thinned CCD is in agreement with the reflection limit for light incident on the back surface in the spectral range of 260-600 nm. The 2.5 nm silicon layer, grown at 450 C, contained a boron delta-layer with surface density of about 2 x 10 exp 14/sq cm. Passivation of the surface was done by steam oxidation of a nominally undoped 1.5 nm Si cap layer. The UV quantum efficiency was found to be uniform and stable with respect to thermal cycling and illumination conditions.

Full-color OLED on silicon microdisplay

NASA Astrophysics Data System (ADS)

Ghosh, Amalkumar P.

2002-02-01

eMagin has developed numerous enhancements to organic light emitting diode (OLED) technology, including a unique, up- emitting structure for OLED-on-silicon microdisplay devices. Recently, eMagin has fabricated full color SVGA+ resolution OLED microdisplays on silicon, with over 1.5 million color elements. The display is based on white light emission from OLED followed by LCD-type red, green and blue color filters. The color filters are patterned directly on OLED devices following suitable thin film encapsulation and the drive circuits are built directly on single crystal silicon. The resultant color OLED technology, with hits high efficiency, high brightness, and low power consumption, is ideally suited for near to the eye applications such as wearable PCS, wireless Internet applications and mobile phone, portable DVD viewers, digital cameras and other emerging applications.

Small area silicon diffused junction X-ray detectors

NASA Technical Reports Server (NTRS)

Walton, J. T.; Pehl, R. H.; Larsh, A. E.

1982-01-01

The low-temperature performance of silicon diffused junction detectors in the measurement of low energy X-rays is reported. The detectors have an area of 0.04 sq cm and a thickness of 100 microns. The spectral resolutions of these detectors were found to be in close agreement with expected values, indicating that the defects introduced by the high-temperature processing required in the device fabrication were not deleteriously affecting the detection of low-energy X-rays. Device performance over a temperature range of 77 K to 150 K is given. These detectors were designed to detect low-energy X-rays in the presence of minimum ionizing electrons. The successful application of silicon-diffused junction technology to X-ray detector fabrication may facilitate the development of other novel silicon X-ray detector designs.

Tungsten bridge for the low energy ignition of explosive and energetic materials

DOEpatents

Benson, D.A.; Bickes, R.W. Jr.; Blewer, R.S.

1990-12-11

A tungsten bridge device for the low energy ignition of explosive and energetic materials is disclosed. The device is fabricated on a silicon-on-sapphire substrate which has an insulating bridge element defined therein using standard integrated circuit fabrication techniques. Then, a thin layer of tungsten is selectively deposited on the silicon bridge layer using chemical vapor deposition techniques. Finally, conductive lands are deposited on each end of the tungsten bridge layer to form the device. It has been found that this device exhibits substantially shorter ignition times than standard metal bridges and foil igniting devices. In addition, substantially less energy is required to cause ignition of the tungsten bridge device of the present invention than is required for common metal bridges and foil devices used for the same purpose. 2 figs.

Towards nanometer-spaced silicon contacts to proteins

NASA Astrophysics Data System (ADS)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Optoelectronic Devices and Materials

NASA Astrophysics Data System (ADS)

Sweeney, Stephen; Adams, Alfred

Unlike the majority of electronic devices, which are silicon based, optoelectronic devices are predominantly made using III-V semiconductor compounds such as GaAs, InP, GaN and GaSb and their alloys due to their direct band gap. Understanding the properties of these materials has been of vital importance in the development of optoelectronic devices. Since the first demonstration of a semiconductor laser in the early 1960s, optoelectronic devices have been produced in their millions, pervading our everyday lives in communications, computing, entertainment, lighting and medicine. It is perhaps their use in optical-fibre communications that has had the greatest impact on humankind, enabling high-quality and inexpensive voice and data transmission across the globe. Optical communications spawned a number of developments in optoelectronics, leading to devices such as vertical-cavity surface-emitting lasers, semiconductor optical amplifiers, optical modulators and avalanche photodiodes. In this chapter we discuss the underlying theory of operation of the most important optoelectronic devices. The influence of carrier-photon interactions is discussed in the context of producing efficient emitters and detectors. Finally we discuss how the semiconductor band structure can be manipulated to enhance device properties using quantum confinement and strain effects, and how the addition of dilute amounts of elements such as nitrogen is having a profound effect on the next generation of optoelectronic devices.

Polishing of silicon based advanced ceramics

NASA Astrophysics Data System (ADS)

Klocke, Fritz; Dambon, Olaf; Zunke, Richard; Waechter, D.

2009-05-01

Silicon based advanced ceramics show advantages in comparison to other materials due to their extreme hardness, wear and creep resistance, low density and low coefficient of thermal expansion. As a matter of course, machining requires high efforts. In order to reach demanded low roughness for optical or tribological applications a defect free surface is indispensable. In this paper, polishing of silicon nitride and silicon carbide is investigated. The objective is to elaborate scientific understanding of the process interactions. Based on this knowledge, the optimization of removal rate, surface quality and form accuracy can be realized. For this purpose, fundamental investigations of polishing silicon based ceramics are undertaken and evaluated. Former scientific publications discuss removal mechanisms and wear behavior, but the scientific insight is mainly based on investigations in grinding and lapping. The removal mechanisms in polishing are not fully understood due to complexity of interactions. The role of, e.g., process parameters, slurry and abrasives, and their influence on the output parameters is still uncertain. Extensive technological investigations demonstrate the influence of the polishing system and the machining parameters on the stability and the reproducibility. It is shown that the interactions between the advanced ceramics and the polishing systems is of great relevance. Depending on the kind of slurry and polishing agent the material removal mechanisms differ. The observed effects can be explained by dominating mechanical or chemo-mechanical removal mechanisms. Therefore, hypotheses to state adequate explanations are presented and validated by advanced metrology devices, such as SEM, AFM and TEM.