Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2012-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Steady-state probability density function of the phase error for a DPLL with an integrate-and-dump device

NASA Technical Reports Server (NTRS)

Simon, M.; Mileant, A.

1986-01-01

The steady-state behavior of a particular type of digital phase-locked loop (DPLL) with an integrate-and-dump circuit following the phase detector is characterized in terms of the probability density function (pdf) of the phase error in the loop. Although the loop is entirely digital from an implementation standpoint, it operates at two extremely different sampling rates. In particular, the combination of a phase detector and an integrate-and-dump circuit operates at a very high rate whereas the loop update rate is very slow by comparison. Because of this dichotomy, the loop can be analyzed by hybrid analog/digital (s/z domain) techniques. The loop is modeled in such a general fashion that previous analyses of the Real-Time Combiner (RTC), Subcarrier Demodulator Assembly (SDA), and Symbol Synchronization Assembly (SSA) fall out as special cases.

A Digitally Programmable Cytomorphic Chip for Simulation of Arbitrary Biochemical Reaction Networks.

PubMed

Woo, Sung Sik; Kim, Jaewook; Sarpeshkar, Rahul

2018-04-01

Prior work has shown that compact analog circuits can faithfully represent and model fundamental biomolecular circuits via efficient log-domain cytomorphic transistor equivalents. Such circuits have emphasized basis functions that are dominant in genetic transcription and translation networks and deoxyribonucleic acid (DNA)-protein binding. Here, we report a system featuring digitally programmable 0.35 μm BiCMOS analog cytomorphic chips that enable arbitrary biochemical reaction networks to be exactly represented thus enabling compact and easy composition of protein networks as well. Since all biomolecular networks can be represented as chemical reaction networks, our protein networks also include the former genetic network circuits as a special case. The cytomorphic analog protein circuits use one fundamental association-dissociation-degradation building-block circuit that can be configured digitally to exactly represent any zeroth-, first-, and second-order reaction including loading, dynamics, nonlinearity, and interactions with other building-block circuits. To address a divergence issue caused by random variations in chip fabrication processes, we propose a unique way of performing computation based on total variables and conservation laws, which we instantiate at both the circuit and network levels. Thus, scalable systems that operate with finite error over infinite time can be built. We show how the building-block circuits can be composed to form various network topologies, such as cascade, fan-out, fan-in, loop, dimerization, or arbitrary networks using total variables. We demonstrate results from a system that combines interacting cytomorphic chips to simulate a cancer pathway and a glycolysis pathway. Both simulations are consistent with conventional software simulations. Our highly parallel digitally programmable analog cytomorphic systems can lead to a useful design, analysis, and simulation tool for studying arbitrary large-scale biological networks in systems and synthetic biology.

Digitized adiabatic quantum computing with a superconducting circuit.

PubMed

Barends, R; Shabani, A; Lamata, L; Kelly, J; Mezzacapo, A; Las Heras, U; Babbush, R; Fowler, A G; Campbell, B; Chen, Yu; Chen, Z; Chiaro, B; Dunsworth, A; Jeffrey, E; Lucero, E; Megrant, A; Mutus, J Y; Neeley, M; Neill, C; O'Malley, P J J; Quintana, C; Roushan, P; Sank, D; Vainsencher, A; Wenner, J; White, T C; Solano, E; Neven, H; Martinis, John M

2016-06-09

Quantum mechanics can help to solve complex problems in physics and chemistry, provided they can be programmed in a physical device. In adiabatic quantum computing, a system is slowly evolved from the ground state of a simple initial Hamiltonian to a final Hamiltonian that encodes a computational problem. The appeal of this approach lies in the combination of simplicity and generality; in principle, any problem can be encoded. In practice, applications are restricted by limited connectivity, available interactions and noise. A complementary approach is digital quantum computing, which enables the construction of arbitrary interactions and is compatible with error correction, but uses quantum circuit algorithms that are problem-specific. Here we combine the advantages of both approaches by implementing digitized adiabatic quantum computing in a superconducting system. We tomographically probe the system during the digitized evolution and explore the scaling of errors with system size. We then let the full system find the solution to random instances of the one-dimensional Ising problem as well as problem Hamiltonians that involve more complex interactions. This digital quantum simulation of the adiabatic algorithm consists of up to nine qubits and up to 1,000 quantum logic gates. The demonstration of digitized adiabatic quantum computing in the solid state opens a path to synthesizing long-range correlations and solving complex computational problems. When combined with fault-tolerance, our approach becomes a general-purpose algorithm that is scalable.

Hierarchical CAD Tools for Radiation Hardened Mixed Signal Electronic Circuits

DTIC Science & Technology

2005-01-28

11 Figure 3: Schematic of Analog and Digital Components 12 Figure 4: Dose Rate Syntax 14 Figure 5: Single Event Effects (SEE) Syntax 15 Figure 6...Harmony-AMS simulation of a Digital Phase Locked Loop 19 Figure 10: SEE results from DPLL Simulation 20 Figure 11: Published results used for validation...analog and digital circuitry. Combining the analog and digital elements onto a single chip has several advantages, but also creates unique challenges

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

1997-01-01

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

1997-11-04

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Video signal processing system uses gated current mode switches to perform high speed multiplication and digital-to-analog conversion

NASA Technical Reports Server (NTRS)

Gilliland, M. G.; Rougelot, R. S.; Schumaker, R. A.

1966-01-01

Video signal processor uses special-purpose integrated circuits with nonsaturating current mode switching to accept texture and color information from a digital computer in a visual spaceflight simulator and to combine these, for display on color CRT with analog information concerning fading.

USSR and Eastern Europe Scientific Abstracts, Electronics and Electrical Engineering, Number 24.

DTIC Science & Technology

1976-11-12

GERMANY DUMMER, Joachim, graduate mathematician, and KLEIN, Richard, graduate engineer, Radio Works Combine State Enterprise, Erfurt DIGITAL FRONT PANEL ...operation, performance, and applications of a digital front panel display instrument was described and illustrated with circuit diagrams, block diagrams...technics, various digital and alphabetic panels , holography, and possibly the screens of cathode-ray tubes. One of the chief merits of "ftiros" is the

Digitally gain controlled linear high voltage amplifier for laboratory applications.

PubMed

Koçum, C

2011-08-01

The design of a digitally gain controlled high-voltage non-inverting bipolar linear amplifier is presented. This cost efficient and relatively simple circuit has stable operation range from dc to 90 kHz under the load of 10 kΩ and 39 pF. The amplifier can swing up to 360 V(pp) under these conditions and it has 2.5 μs rise time. The gain can be changed by the aid of JFETs. The amplifiers have been realized using a combination of operational amplifiers and high-voltage discrete bipolar junction transistors. The circuit details and performance characteristics are discussed.

Digital logic circuit based on two component molecular systems of BSA and salen

NASA Astrophysics Data System (ADS)

Hai-Bin, Lin; Feng, Chen; Hong-Xu, Guo

2018-02-01

A new fluorescent molecular probe 1 was designed and constructed by combining bovine serum albumin (BSA) and N,N‧-bis(salicylidene)ethylenediamine (salen). Stimulated by Zn2 +, tris, or EDTAH2Na2, the distance between BSA and salen was regulated, which was accompanied by an obvious change in the fluorescence intensity at 350 or 445 nm based on Förster resonance energy transfer. Moreover, based on the encoding binary digits in these inputs and outputs applying positive logic conventions, a monomolecular circuit integrating one OR, three NOT, and three YES gates, was successfully achieved.

Digital circuits for computer applications: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

Parallel reduced-instruction-set-computer architecture for real-time symbolic pattern matching

NASA Astrophysics Data System (ADS)

Parson, Dale E.

1991-03-01

This report discusses ongoing work on a parallel reduced-instruction- set-computer (RISC) architecture for automatic production matching. The PRIOPS compiler takes advantage of the memoryless character of automatic processing by translating a program's collection of automatic production tests into an equivalent combinational circuit-a digital circuit without memory, whose outputs are immediate functions of its inputs. The circuit provides a highly parallel, fine-grain model of automatic matching. The compiler then maps the combinational circuit onto RISC hardware. The heart of the processor is an array of comparators capable of testing production conditions in parallel, Each comparator attaches to private memory that contains virtual circuit nodes-records of the current state of nodes and busses in the combinational circuit. All comparator memories hold identical information, allowing simultaneous update for a single changing circuit node and simultaneous retrieval of different circuit nodes by different comparators. Along with the comparator-based logic unit is a sequencer that determines the current combination of production-derived comparisons to try, based on the combined success and failure of previous combinations of comparisons. The memoryless nature of automatic matching allows the compiler to designate invariant memory addresses for virtual circuit nodes, and to generate the most effective sequences of comparison test combinations. The result is maximal utilization of parallel hardware, indicating speed increases and scalability beyond that found for course-grain, multiprocessor approaches to concurrent Rete matching. Future work will consider application of this RISC architecture to the standard (controlled) Rete algorithm, where search through memory dominates portions of matching.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Frequency Domain Multiplexing for Use With NaI[Tl] Detectors

NASA Astrophysics Data System (ADS)

Belling, Samuel; Coherent Collaboration

2017-09-01

A process used in many forms of signal communication known as multiplexing is adapted for the purpose of combining signals from NaI[Tl] detectors so that fewer digitizer channels can be used to process the signal information from large experiments within the COHERENT collaboration. Each signal is passed through a ringing circuit to modulate it with a characteristic frequency. Information about the signal can be extracted from its amplitude, frequency, and phase. Simulations in LTSpice show that an operational amplifier circuit with a parallel LRC feedback loop can serve as the modulating circuit. Several such circuits can be constructed and housed compactly in a unit, and fed to an inverting, summing amplifier with tunable gain, such that the signals are carried by one cable. The signals are analyzed based on a Fourier transform after being digitized. The results show that the energy, channel, and time of the original interaction can be recovered by this process. In some cases it is possible through filtering and deconvolution to recover the shape of the original signal. The effort is ongoing, but with the design presented it is possible to multiplex 10 detectors into a single digitizer channel. NSF REU Program at Duke University.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Digital model of a vacuum circuit breaker for the analysis of switching waveforms in electrical circuits

NASA Astrophysics Data System (ADS)

Budzisz, Joanna; Wróblewski, Zbigniew

2016-03-01

The article presents a method of modelling a vaccum circuit breaker in the ATP/EMTP package, the results of the verification of the correctness of the developed digital circuit breaker model operation and its practical usefulness for analysis of overvoltages and overcurrents occurring in commutated capacitive electrical circuits and also examples of digital simulations of overvoltages and overcurrents in selected electrical circuits.

An evaluation of the Intel 2920 digital signal processing integrated circuit

NASA Technical Reports Server (NTRS)

Heller, J.

1981-01-01

The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

Auto-programmable impulse neural circuits

NASA Technical Reports Server (NTRS)

Watula, D.; Meador, J.

1990-01-01

Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.

A CCD Monolithic LMS Adaptive Analog Signal Processor Integrated Circuit.

DTIC Science & Technology

1980-03-01

adaptive filter with electrically- reprogrammable MOS analog conductance weights. I The analog and digital peripheral MOS on-chip circuits are provided with...electrically reprogrammable analog weights at tap positions along a CCD analog delay line in order to form a basic linear combiner for adaptive filtering...electrically reprogrammable analog conductance weights was introduced with the use of non-volatile MNOS memory 6-7 transistors biased in their triode

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

Analog current mode analog/digital converter

NASA Technical Reports Server (NTRS)

Hadidi, Khayrollah (Inventor)

1996-01-01

An improved subranging or comparator circuit is provided for an analog-to-digital converter. As a subranging circuit, the circuit produces a residual signal representing the difference between an analog input signal and an analog of a digital representation. This is achieved by subdividing the digital representation into two or more parts and subtracting from the analog input signal analogs of each of the individual digital portions. In another aspect of the present invention, the subranging circuit comprises two sets of differential input pairs in which the transconductance of one differential input pair is scaled relative to the transconductance of the other differential input pair. As a consequence, the same resistor string may be used for two different digital-to-analog converters of the subranging circuit.

MiniDSS: a low-power and high-precision miniaturized digital sun sensor

NASA Astrophysics Data System (ADS)

de Boer, B. M.; Durkut, M.; Laan, E.; Hakkesteegt, H.; Theuwissen, A.; Xie, N.; Leijtens, J. L.; Urquijo, E.; Bruins, P.

2017-11-01

A high-precision and low-power miniaturized digital sun sensor has been developed at TNO. The single-chip sun sensor comprises an application specific integrated circuit (ASIC) on which an active pixel sensor (APS), read-out and processing circuitry as well as communication circuitry are combined. The design was optimized for low recurrent cost. The sensor is albedo insensitive and the prototype combines an accuracy in the order of 0.03° with a mass of just 72 g and a power consumption of only 65 mW.

A Two-Color Fourier Transform Mm-Wave Spectrometer for Gas Analysis Operating from 260-295 GHZ

NASA Astrophysics Data System (ADS)

Steber, Amanda L.; Harris, Brent J.; Lehmann, Kevin K.; Pate, Brooks H.

2013-06-01

We have designed a two-color mm-wave spectrometer for Fourier transform mm-wave spectroscopy that uses consumer level components for the tunable synthesizers, digital control of the pulse modulators, and digitization of the coherent free induction decay (FID). The excitation pulses are generated using an x24 active multiplier chain (AMC) that produces a peak power of 30 mW. The microwave input to the AMC is generated in a frequency up conversion circuit that accepts a microwave input frequency from about 2-4 GHz. This circuit also generates the input to the mm-wave subhamonic mixer that creates the local oscillator from a separate 2-4 GHz microwave input. Excitation pulses at two independently tunable frequencies are generated using a dual-channel source based on a low-cost, wideband synthesizer integrated circuit (Valon Technology Model 5008). The outputs of the synthesizer are pulse modulated using a PIN diode switch that is driven using the arbitrary waveform generator (AWG) output of a USB-controlled high-speed digitizer / arbitrary waveform generator combination unit (Tie Pie HS-5 530 XM). The two pulses are combined using a Wilkinson power divider before input to the up conversion circuit. The FID frequency is down converted in a two-stage mixing process to 65 MHz. The two LO frequencies used in the receiver are provided by a second Valon 5008. The FID is digitized at 200 MSamples/s using the 12-bit Tie Pie digitizer. The digital oscilloscope (and its AWG channel) and the two synthesizers use a 10 MHz reference signal from a Rubidium clock to permit time-domain signal averaging. A key feature of the digital oscilloscope is its deep memory of 32 Mpts (complemented by the 64 Mpt memory in the 240 MS/s AWG). This makes it possible to perform several one- and two-color coherent measurements, including pulse echoes and double-resonance spectroscopy, in a single "readout" experiment to speed the analysis of mm-wave rotational spectra. The spectrometer sensitivity and frequency accuracy are illustrated by high-speed measurements of OCS rotational transitions for low-abundance isotopes. Examples of pulse echo measurements to determine the collisional relaxation rate and two-color double-resonance measurements to confirm the presence of a molecular species will be illustrated using OCS as the room-temperature gas sample.

Flexible circuits with integrated switches for robotic shape sensing

NASA Astrophysics Data System (ADS)

Harnett, C. K.

2016-05-01

Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Formal hardware verification of digital circuits

NASA Technical Reports Server (NTRS)

Joyce, J.; Seger, C.-J.

1991-01-01

The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Sayyah, Rana; Ho, Fat D.

2009-01-01

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

ADDER CIRCUIT

DOEpatents

Jacobsohn, D.H.; Merrill, L.C.

1959-01-20

An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

Applied digital signal processing systems for vortex flowmeter with digital signal processing.

PubMed

Xu, Ke-Jun; Zhu, Zhi-Hai; Zhou, Yang; Wang, Xiao-Fen; Liu, San-Shan; Huang, Yun-Zhi; Chen, Zhi-Yuan

2009-02-01

The spectral analysis is combined with digital filter to process the vortex sensor signal for reducing the effect of disturbance at low frequency from pipe vibrations and increasing the turndown ratio. Using digital signal processing chip, two kinds of digital signal processing systems are developed to implement these algorithms. One is an integrative system, and the other is a separated system. A limiting amplifier is designed in the input analog condition circuit to adapt large amplitude variation of sensor signal. Some technique measures are taken to improve the accuracy of the output pulse, speed up the response time of the meter, and reduce the fluctuation of the output signal. The experimental results demonstrate the validity of the digital signal processing systems.

Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

NASA Astrophysics Data System (ADS)

Chang, S. S. L.

State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

CMOL: A New Concept for Nanoelectronics

NASA Astrophysics Data System (ADS)

Likharev, Konstantin

2005-03-01

I will review the recent work on devices and architectures for future hybrid semiconductor/molecular integrated circuits, in particular those of ``CMOL'' variety [1]. Such circuits would combine an advanced CMOS subsystem fabricated by the usual lithographic patterning, two layers of parallel metallic nanowires formed, e.g., by nanoimprint, and two-terminal molecular devices self-assembled on the nanowire crosspoints. Estimates show that this powerful combination may allow CMOL circuits to reach an unparalleled density (up to 10^12 functions per cm^2) and ultrahigh rate of information processing (up to 10^20 operations per second on a single chip), at acceptable power dissipation. The main challenges on the way toward practical CMOL technology are: (i) reliable chemically-directed self-assembly of mid-size organic molecules, and (ii) the development of efficient defect-tolerant architectures for CMOL circuits. Our recent work has shown that such architectures may be developed not only for terabit-scale memories and naturally defect-tolerant mixed-signal neuromorphic networks, but (rather unexpectedly) also for FPGA-style digital Boolean circuits. [1] For details, see http://rsfq1.physics.sunysb.edu/˜likharev/nano/Springer04.pdf

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

Simulated Laboratory in Digital Logic.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

Analog circuit for controlling acoustic transducer arrays

DOEpatents

Drumheller, Douglas S.

1991-01-01

A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

Industrial Electronics II for ICT. Student's Manual.

ERIC Educational Resources Information Center

Snider, Bob

This student manual contains the following six units for classroom and laboratory experiences in high school industrial electronics: (1) introduction and review of DC and AC circuits; (2) semiconductors; (3) integrated circuits; (4) digital basics; (5) complex digital circuits; and (6) computer circuits. The units include unit objectives, specific…

Effective algorithm for routing integral structures with twolayer switching

NASA Astrophysics Data System (ADS)

Nazarov, A. V.; Shakhnov, V. A.; Vlasov, A. I.; Novikov, A. N.

2018-05-01

The paper presents an algorithm for routing switching objects such as large-scale integrated circuits (LSICs) with two layers of metallization, embossed printed circuit boards, microboards with pairs of wiring layers on each side, and other similar constructs. The algorithm allows eliminating the effect of mutual blocking of routes in the classical wave algorithm by implementing a special circuit of digital wave motion in two layers of metallization, allowing direct intersections of all circuit conductors in a combined layer. However, information about the belonging of the topology elements to the circuits is sufficient for layering and minimizing the number of contact holes. In addition, the paper presents a specific example which shows that, in contrast to the known routing algorithms using a wave model, just one byte of memory per discrete of the work field is sufficient to implement the proposed algorithm.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

PubMed Central

Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

2017-01-01

Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

Another Nulling Hall-Effect Current-Measuring Circuit

NASA Technical Reports Server (NTRS)

Thibodeau, Phillip E.; Sullender, Craig C.

1993-01-01

Lightweight, low-power circuit provides noncontact measurement of alternating or direct current of many ampheres in main conductor. Advantages of circuit over other nulling Hall-effect current-measuring circuits is stability and accuracy increased by putting both analog-to-digital and digital-to-analog converters in nulling feedback loop. Converters and rest of circuit designed for operation at sampling rate of 100 kHz, but rate changed to alter time or frequency response of circuit.

Complex logic functions implemented with quantum dot bionanophotonic circuits.

PubMed

Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2014-03-26

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

PubMed

Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

2018-02-01

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

Digital correlator with fewer IC's

NASA Technical Reports Server (NTRS)

Apple, G. G.; Rubin, L.

1979-01-01

Digital correlator requires only few integrated circuits to determine synchronization of two 24-bit digital words. Circuit is easily reduced or expanded to accommodate shorter or longer words and can be utilized in industrial and commercial data processing and telecommunications.

An infrastructure for accurate characterization of single-event transients in digital circuits.

PubMed

Savulimedu Veeravalli, Varadan; Polzer, Thomas; Schmid, Ulrich; Steininger, Andreas; Hofbauer, Michael; Schweiger, Kurt; Dietrich, Horst; Schneider-Hornstein, Kerstin; Zimmermann, Horst; Voss, Kay-Obbe; Merk, Bruno; Hajek, Michael

2013-11-01

We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.

Probabilistic switching circuits in DNA

PubMed Central

Wilhelm, Daniel; Bruck, Jehoshua

2018-01-01

A natural feature of molecular systems is their inherent stochastic behavior. A fundamental challenge related to the programming of molecular information processing systems is to develop a circuit architecture that controls the stochastic states of individual molecular events. Here we present a systematic implementation of probabilistic switching circuits, using DNA strand displacement reactions. Exploiting the intrinsic stochasticity of molecular interactions, we developed a simple, unbiased DNA switch: An input signal strand binds to the switch and releases an output signal strand with probability one-half. Using this unbiased switch as a molecular building block, we designed DNA circuits that convert an input signal to an output signal with any desired probability. Further, this probability can be switched between 2n different values by simply varying the presence or absence of n distinct DNA molecules. We demonstrated several DNA circuits that have multiple layers and feedback, including a circuit that converts an input strand to an output strand with eight different probabilities, controlled by the combination of three DNA molecules. These circuits combine the advantages of digital and analog computation: They allow a small number of distinct input molecules to control a diverse signal range of output molecules, while keeping the inputs robust to noise and the outputs at precise values. Moreover, arbitrarily complex circuit behaviors can be implemented with just a single type of molecular building block. PMID:29339484

Dimension scaling effects on the yield sensitivity of HEMT digital circuits

NASA Technical Reports Server (NTRS)

Sarker, Jogendra C.; Purviance, John E.

1992-01-01

In our previous works, using a graphical tool, yield factor histograms, we studied the yield sensitivity of High Electron Mobility Transistors (HEMT) and HEMT circuit performance with the variation of process parameters. This work studies the scaling effects of process parameters on yield sensitivity of HEMT digital circuits. The results from two HEMT circuits are presented.

Design on the x-ray oral digital image display card

NASA Astrophysics Data System (ADS)

Wang, Liping; Gu, Guohua; Chen, Qian

2009-10-01

According to the main characteristics of X-ray imaging, the X-ray display card is successfully designed and debugged using the basic principle of correlated double sampling (CDS) and combined with embedded computer technology. CCD sensor drive circuit and the corresponding procedures have been designed. Filtering and sampling hold circuit have been designed. The data exchange with PC104 bus has been implemented. Using complex programmable logic device as a device to provide gating and timing logic, the functions which counting, reading CPU control instructions, corresponding exposure and controlling sample-and-hold have been completed. According to the image effect and noise analysis, the circuit components have been adjusted. And high-quality images have been obtained.

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

NASA Astrophysics Data System (ADS)

Lamata, Lucas

2017-03-01

We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi- Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits.

Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

PubMed Central

Lamata, Lucas

2017-01-01

We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi- Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits. PMID:28256559

47 CFR 32.2212 - Digital electronic switching.

Code of Federal Regulations, 2012 CFR

2012-10-01

... shall include the original cost of digital electronic switching equipment used to provide circuit... electronic switching equipment used to provide both circuit and packet switching shall be recorded in the... 47 Telecommunication 2 2012-10-01 2012-10-01 false Digital electronic switching. 32.2212 Section...

47 CFR 32.2212 - Digital electronic switching.

Code of Federal Regulations, 2014 CFR

2014-10-01

... shall include the original cost of digital electronic switching equipment used to provide circuit... electronic switching equipment used to provide both circuit and packet switching shall be recorded in the... 47 Telecommunication 2 2014-10-01 2014-10-01 false Digital electronic switching. 32.2212 Section...

47 CFR 32.2212 - Digital electronic switching.

Code of Federal Regulations, 2011 CFR

2011-10-01

... shall include the original cost of digital electronic switching equipment used to provide circuit... electronic switching equipment used to provide both circuit and packet switching shall be recorded in the... 47 Telecommunication 2 2011-10-01 2011-10-01 false Digital electronic switching. 32.2212 Section...

47 CFR 32.2212 - Digital electronic switching.

Code of Federal Regulations, 2010 CFR

2010-10-01

... shall include the original cost of digital electronic switching equipment used to provide circuit... electronic switching equipment used to provide both circuit and packet switching shall be recorded in the... 47 Telecommunication 2 2010-10-01 2010-10-01 false Digital electronic switching. 32.2212 Section...

47 CFR 32.2212 - Digital electronic switching.

Code of Federal Regulations, 2013 CFR

2013-10-01

... shall include the original cost of digital electronic switching equipment used to provide circuit... electronic switching equipment used to provide both circuit and packet switching shall be recorded in the... 47 Telecommunication 2 2013-10-01 2013-10-01 false Digital electronic switching. 32.2212 Section...

7 CFR 1770.15 - Supplementary accounts required of all borrowers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... Switching—Circuit. 2212.2 2212.2 Digital Electronic Switching—Packet. 2230.11 Central Office Transmission... Retirement Work in Progress. Current Liabilities 2232.1 2232.1 Circuit Equipment—Electronic. 2232.2 2232.2... Expense—Circuit. 6212.2 6212.2 Digital Electronic Switching Expense—Packet. 6230.11 Radio Systems Expense...

7 CFR 1770.15 - Supplementary accounts required of all borrowers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... Switching—Circuit. 2212.2 2212.2 Digital Electronic Switching—Packet. 2230.11 Central Office Transmission... Retirement Work in Progress. Current Liabilities 2232.1 2232.1 Circuit Equipment—Electronic. 2232.2 2232.2... Expense—Circuit. 6212.2 6212.2 Digital Electronic Switching Expense—Packet. 6230.11 Radio Systems Expense...

7 CFR 1770.15 - Supplementary accounts required of all borrowers.

Code of Federal Regulations, 2011 CFR

2011-01-01

... Switching—Circuit. 2212.2 2212.2 Digital Electronic Switching—Packet. 2230.11 Central Office Transmission... Retirement Work in Progress. Current Liabilities 2232.1 2232.1 Circuit Equipment—Electronic. 2232.2 2232.2... Expense—Circuit. 6212.2 6212.2 Digital Electronic Switching Expense—Packet. 6230.11 Radio Systems Expense...

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

VHDL Modeling and Simulation of a Digital Image Synthesizer for Countering ISAR

DTIC Science & Technology

2003-06-01

This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer...necessary for a given application . With such a digital method, it is possible for a small ship to appear as large as an aircraft carrier or any high...INTRODUCTION TO DIGITAL IMAGE SYNTHESIZER (DIS) A. BACKGROUND The Digital Image Synthesizer (DIS) is an Application Specific Integrated Circuit

A molecular-sized optical logic circuit for digital modulation of a fluorescence signal

NASA Astrophysics Data System (ADS)

Nishimura, Takahiro; Tsuchida, Karin; Ogura, Yusuke; Tanida, Jun

2018-03-01

Fluorescence measurement allows simultaneous detection of multiple molecular species by using spectrally distinct fluorescence probes. However, due to the broad spectra of fluorescence emission, the multiplicity of fluorescence measurement is generally limited. To overcome this limitation, we propose a method to digitally modulate fluorescence output signals with a molecular-sized optical logic circuit by using optical control of fluorescence resonance energy transfer (FRET). The circuit receives a set of optical inputs represented with different light wavelengths, and then it switches high and low fluorescence intensity from a reporting molecule according to the result of the logic operation. By using combinational optical inputs in readout of fluorescence signals, the number of biomolecular species that can be identified is increased. To implement the FRET-based circuits, we designed two types of basic elements, YES and NOT switches. An YES switch produces a high-level output intensity when receiving a designated light wavelength input and a low-level intensity without the light irradiation. A NOT switch operates inversely to the YES switch. In experiments, we investigated the operation of the YES and NOT switches that receive a 532-nm light input and modulate the fluorescence intensity of Alexa Fluor 488. The experimental result demonstrates that the switches can modulate fluorescence signals according to the optical input.

Electro-optic Mach-Zehnder Interferometer based Optical Digital Magnitude Comparator and 1's Complement Calculator

NASA Astrophysics Data System (ADS)

Kumar, Ajay; Raghuwanshi, Sanjeev Kumar

2016-06-01

The optical switching activity is one of the most essential phenomena in the optical domain. The electro-optic effect-based switching phenomena are applicable to generate some effective combinational and sequential logic circuits. The processing of digital computational technique in the optical domain includes some considerable advantages of optical communication technology, e.g. immunity to electro-magnetic interferences, compact size, signal security, parallel computing and larger bandwidth. The paper describes some efficient technique to implement single bit magnitude comparator and 1's complement calculator using the concepts of electro-optic effect. The proposed techniques are simulated on the MATLAB software. However, the suitability of the techniques is verified using the highly reliable Opti-BPM software. It is interesting to analyze the circuits in order to specify some optimized device parameter in order to optimize some performance affecting parameters, e.g. crosstalk, extinction ratio, signal losses through the curved and straight waveguide sections.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Synthetic mixed-signal computation in living cells

PubMed Central

Rubens, Jacob R.; Selvaggio, Gianluca; Lu, Timothy K.

2016-01-01

Living cells implement complex computations on the continuous environmental signals that they encounter. These computations involve both analogue- and digital-like processing of signals to give rise to complex developmental programs, context-dependent behaviours and homeostatic activities. In contrast to natural biological systems, synthetic biological systems have largely focused on either digital or analogue computation separately. Here we integrate analogue and digital computation to implement complex hybrid synthetic genetic programs in living cells. We present a framework for building comparator gene circuits to digitize analogue inputs based on different thresholds. We then demonstrate that comparators can be predictably composed together to build band-pass filters, ternary logic systems and multi-level analogue-to-digital converters. In addition, we interface these analogue-to-digital circuits with other digital gene circuits to enable concentration-dependent logic. We expect that this hybrid computational paradigm will enable new industrial, diagnostic and therapeutic applications with engineered cells. PMID:27255669

Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

NASA Technical Reports Server (NTRS)

Baranauskas, Gytis (Inventor); Lim, Boon H. (Inventor); Baranauskas, Dalius (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor)

2017-01-01

According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

2017-02-01

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

Circuit for echo and noise suppression of accoustic signals transmitted through a drill string

DOEpatents

Drumheller, Douglas S.; Scott, Douglas D.

1993-01-01

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output.

Phase-lock-loop application for fiber optic receiver

NASA Astrophysics Data System (ADS)

Ruggles, Stephen L.; Wills, Robert W.

1991-02-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Phase-lock-loop application for fiber optic receiver

NASA Technical Reports Server (NTRS)

Ruggles, Stephen L.; Wills, Robert W.

1991-01-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Comparing Online to Face-To-Face Delivery of Undergraduate Digital Circuits Content

ERIC Educational Resources Information Center

LaMeres, Brock J.; Plumb, Carolyn

2014-01-01

This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of…

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Experiences in Digital Circuit Design Courses: A Self-Study Platform for Learning Support

ERIC Educational Resources Information Center

Bañeres, David; Clarisó, Robert; Jorba, Josep; Serra, Montse

2014-01-01

The synthesis of digital circuits is a basic skill in all the bachelor programmes around the ICT area of knowledge, such as Computer Science, Telecommunication Engineering or Electrical Engineering. An important hindrance in the learning process of this skill is that the existing educational tools for the design of circuits do not allow the…

Flexible Simulation E-Learning Environment for Studying Digital Circuits and Possibilities for It Deployment as Semantic Web Service

ERIC Educational Resources Information Center

Radoyska, P.; Ivanova, T.; Spasova, N.

2011-01-01

In this article we present a partially realized project for building a distributed learning environment for studying digital circuits Test and Diagnostics at TU-Sofia. We describe the main requirements for this environment, substantiate the developer platform choice, and present our simulation and circuit parameter calculation tools.…

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

NASA Technical Reports Server (NTRS)

Seefeldt, James (Inventor); Feng, Xiaoxin (Inventor); Roper, Weston (Inventor)

2013-01-01

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Circuit for echo and noise suppression of acoustic signals transmitted through a drill string

DOEpatents

Drumheller, D.S.; Scott, D.D.

1993-12-28

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output. 20 figures.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

An infrastructure for accurate characterization of single-event transients in digital circuits☆

PubMed Central

Savulimedu Veeravalli, Varadan; Polzer, Thomas; Schmid, Ulrich; Steininger, Andreas; Hofbauer, Michael; Schweiger, Kurt; Dietrich, Horst; Schneider-Hornstein, Kerstin; Zimmermann, Horst; Voss, Kay-Obbe; Merk, Bruno; Hajek, Michael

2013-01-01

We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure. PMID:24748694

Parallel pulse processing and data acquisition for high speed, low error flow cytometry

DOEpatents

van den Engh, Gerrit J.; Stokdijk, Willem

1992-01-01

A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate.

Fast collimated neutron flux measurement using stilbene scintillator and flashy analog-to-digital converter in JT-60U

NASA Astrophysics Data System (ADS)

Ishikawa, M.; Itoga, T.; Okuji, T.; Nakhostin, M.; Shinohara, K.; Hayashi, T.; Sukegawa, A.; Baba, M.; Nishitani, T.

2006-10-01

A line-integrated neutron emission profile is routinely measured using the radial neutron collimator system in JT-60U tokamak. Stilbene neuron detectors (SNDs), which combine a stilbene organic crystal scintillation detector (SD) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure collimated neutron flux. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to ˜1×105counts/s due to the analog PSD circuit. To overcome this issue, a digital signal processing system (DSPS) using a flash analog-to-digital converter (Acqiris DC252, 8GHz, 10bits) has been developed at Cyclotron and Radioisotope Center in Tohoku University. In this system anode signals from photomultiplier of the SD are directory stored and digitized. Then, the PSD between neutrons and gamma rays is performed using software. The DSPS has been installed in the vertical neutron collimator system in JT-60U and applied to deuterium experiments. It is confirmed that the PSD is sufficiently performed and collimated neutron flux is successfully measured with count rate up to ˜5×105counts/s without the effect of pileup of detected pulses. The performance of the DSPS as a neutron detector, which supersedes the SND, is demonstrated.

The Light-Emitting Diode as a Light Detector

ERIC Educational Resources Information Center

Baird, William H.; Hack, W. Nathan; Tran, Kiet; Vira, Zeeshan; Pickett, Matthew

2011-01-01

A light-emitting diode (LED) and operational amplifier can be used as an affordable method to provide a digital output indicating detection of an intense light source such as a laser beam or high-output LED. When coupled with a microcontroller, the combination can be used as a multiple photogate and timer for under $50. A similar circuit is used…

Digital rotation measurement unit

DOEpatents

Sanderson, S.N.

1983-09-30

A digital rotation indicator is disclosed for monitoring the position of a valve member having a movable actuator. The indicator utilizes mercury switches adapted to move in cooperation with the actuator. Each of the switches produces an output as it changes state when the actuator moves. A direction detection circuit is connected to the switches to produce a first digital signal indicative of the direction of rotation of the actuator. A count pulse generating circuit is also connected to the switches to produce a second digital pulse signal having count pulses corresponding to a change of state of any of the mercury switches. A reset pulse generating circuit is provided to generate a reset pulse each time a count pulse is generated. An up/down counter is connected to receive the first digital pulse signal and the second digital pulse signal and to count the pulses of the second digital pulse signal either up or down depending upon the instantaneous digital value of the first digital signal whereby a running count indicative of the movement of the actuator is maintained.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging.

PubMed

Attarzadeh, Hourieh; Xu, Ye; Ytterdal, Trond

2017-10-01

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

Formal development of a clock synchronization circuit

NASA Technical Reports Server (NTRS)

Miner, Paul S.

1995-01-01

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Sunlight and Solar Cells: Teaching Digital Design and Communication through the Development of a Simple Monitoring Station

ERIC Educational Resources Information Center

Downs, Nathan; Parisi, Alfio

2010-01-01

A method is described for building a cost effective digital circuit capable of monitoring the solar radiation incident upon a remote solar cell. The circuit is built in two sections, the first, digitises the analogue voltage produced by the solar cell at a remote location and transmits the received signal to the second receiver circuit which…

Electronics design of the airborne stabilized platform attitude acquisition module

NASA Astrophysics Data System (ADS)

Xu, Jiang; Wei, Guiling; Cheng, Yong; Li, Baolin; Bu, Hongyi; Wang, Hao; Zhang, Zhanwei; Li, Xingni

2014-02-01

We present an attitude acquisition module electronics design for the airborne stabilized platform. The design scheme, which is based on Integrated MEMS sensor ADIS16405, develops the attitude information processing algorithms and the hardware circuit. The hardware circuits with a small volume of only 44.9 x 43.6 x 24.6 mm3, has the characteristics of lightweight, modularization and digitalization. The interface design of the PC software uses the combination plane chart with track line to receive the attitude information and display. Attitude calculation uses the Kalman filtering algorithm to improve the measurement accuracy of the module in the dynamic environment.

System Control for the Transitional DCS. Appendices.

DTIC Science & Technology

1978-12-01

the deployment of the AN/TTC-39 circuit switch. This is a hybrid analog/digital switch providing the following services: o Non- secure analog telephone...service. o Non- secure 16 Kb/s digital telephone service. o Secure 16 Kb/s digital telephone service with automatic key distribution and end to end... security . o Analog circuits to support current inventory 50 Kb/sec and 9.6 Kb/sec secure digital communications. In the deployment model for this study

Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

NASA Astrophysics Data System (ADS)

Lamata, Lucas

We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi-Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits. The author wishes to acknowledge discussions with I. Arrazola, A. Mezzacapo, J. S. Pedernales, and E. Solano, and support from Ramon y Cajal Grant RYC-2012-11391, Spanish MINECO/FEDER FIS2015-69983-P, UPV/EHU UFI 11/55 and Project EHUA14/04.

Synthetic Analog and Digital Circuits for Cellular Computation and Memory

PubMed Central

Purcell, Oliver; Lu, Timothy K.

2014-01-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene circuits that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. PMID:24794536

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

NASA Astrophysics Data System (ADS)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

Design, Simulation and Characteristics Research of the Interface Circuit based on nano-polysilicon thin films pressure sensor

NASA Astrophysics Data System (ADS)

Zhao, Xiaosong; Zhao, Xiaofeng; Yin, Liang

2018-03-01

This paper presents a interface circuit for nano-polysilicon thin films pressure sensor. The interface circuit includes consist of instrument amplifier and Analog-to-Digital converter (ADC). The instrumentation amplifier with a high common mode rejection ratio (CMRR) is implemented by three stages current feedback structure. At the same time, in order to satisfy the high precision requirements of pressure sensor measure system, the 1/f noise corner of 26.5 mHz can be achieved through chopping technology at a noise density of 38.2 nV/sqrt(Hz).Ripple introduced by chopping technology adopt continuous ripple reduce circuit (RRL), which achieves the output ripple level is lower than noise. The ADC achieves 16 bits significant digit by adopting sigma-delta modulator with fourth-order single-bit structure and digital decimation filter, and finally achieves high precision integrated pressure sensor interface circuit.

Repeater For A Digital-Communication Bus

NASA Technical Reports Server (NTRS)

Torres-Guzman, Esteban; Olson, Stephen; Heaps, Tim

1993-01-01

Digital repeater circuit designed to extend range of communication on MIL-STD-1553 bus beyond original maximum allowable length of 300 ft. Circuit provides two-way communication, one way at time, and conforms to specifications of MIL-STD-1553. Crosstalk and instability eliminated.

Parallel pulse processing and data acquisition for high speed, low error flow cytometry

DOEpatents

Engh, G.J. van den; Stokdijk, W.

1992-09-22

A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate. 17 figs.

CMOS based capacitance to digital converter circuit for MEMS sensor

NASA Astrophysics Data System (ADS)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

Microelectromechanical accelerometer with resonance-cancelling control circuit including an idle state

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.; Campbell, David V.

2001-01-01

A digital feedback control circuit is disclosed for use in an accelerometer (e.g. a microelectromechanical accelerometer). The digital feedback control circuit, which periodically re-centers a proof mass in response to a sensed acceleration, is based on a sigma-delta (.SIGMA..DELTA.) configuration that includes a notch filter (e.g. a digital switched-capacitor filter) for rejecting signals due to mechanical resonances of the proof mass and further includes a comparator (e.g. a three-level comparator). The comparator generates one of three possible feedback states, with two of the feedback states acting to re-center the proof mass when that is needed, and with a third feedback state being an "idle" state which does not act to move the proof mass when no re-centering is needed. Additionally, the digital feedback control system includes an auto-zero trim capability for calibration of the accelerometer for accurate sensing of acceleration. The digital feedback control circuit can be fabricated using complementary metal-oxide semiconductor (CMOS) technology, bi-CMOS technology or bipolar technology and used in single- and dual-proof-mass accelerometers.

An Electronics Course Emphasizing Circuit Design

ERIC Educational Resources Information Center

Bergeson, Haven E.

1975-01-01

Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System

PubMed Central

Milde, Moritz B.; Blum, Hermann; Dietmüller, Alexander; Sumislawska, Dora; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

2017-01-01

Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware. PMID:28747883

Integrated digital printing of flexible circuits for wireless sensing (Conference Presentation)

NASA Astrophysics Data System (ADS)

Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Ng, Tse Nga; Krusor, Brent S.; Ready, Steve E.; Daniel, George; Veres, Janos; Street, Bob

2016-09-01

Wireless sensing has broad applications in a wide variety of fields such as infrastructure monitoring, chemistry, environmental engineering and cold supply chain management. Further development of sensing systems will focus on achieving light weight, flexibility, low power consumption and low cost. Fully printed electronics provide excellent flexibility and customizability, as well as the potential for low cost and large area applications, but lack solutions for high-density, high-performance circuitry. Conventional electronics mounted on flexible printed circuit boards provide high performance but are not digitally fabricated or readily customizable. Incorporation of small silicon dies or packaged chips into a printed platform enables high performance without compromising flexibility or cost. At PARC, we combine high functionality c-Si CMOS and digitally printed components and interconnects to create an integrated platform that can read and process multiple discrete sensors. Our approach facilitates customization to a wide variety of sensors and user interfaces suitable for a broad range of applications including remote monitoring of health, structures and environment. This talk will describe several examples of printed wireless sensing systems. The technologies required for these sensor systems are a mix of novel sensors, printing processes, conventional microchips, flexible substrates and energy harvesting power solutions.

Obstacle Avoidance and Target Acquisition for Robot Navigation Using a Mixed Signal Analog/Digital Neuromorphic Processing System.

PubMed

Milde, Moritz B; Blum, Hermann; Dietmüller, Alexander; Sumislawska, Dora; Conradt, Jörg; Indiveri, Giacomo; Sandamirskaya, Yulia

2017-01-01

Neuromorphic hardware emulates dynamics of biological neural networks in electronic circuits offering an alternative to the von Neumann computing architecture that is low-power, inherently parallel, and event-driven. This hardware allows to implement neural-network based robotic controllers in an energy-efficient way with low latency, but requires solving the problem of device variability, characteristic for analog electronic circuits. In this work, we interfaced a mixed-signal analog-digital neuromorphic processor ROLLS to a neuromorphic dynamic vision sensor (DVS) mounted on a robotic vehicle and developed an autonomous neuromorphic agent that is able to perform neurally inspired obstacle-avoidance and target acquisition. We developed a neural network architecture that can cope with device variability and verified its robustness in different environmental situations, e.g., moving obstacles, moving target, clutter, and poor light conditions. We demonstrate how this network, combined with the properties of the DVS, allows the robot to avoid obstacles using a simple biologically-inspired dynamics. We also show how a Dynamic Neural Field for target acquisition can be implemented in spiking neuromorphic hardware. This work demonstrates an implementation of working obstacle avoidance and target acquisition using mixed signal analog/digital neuromorphic hardware.

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

A Hearing Aid Primer 1

ERIC Educational Resources Information Center

Yetter, Carol J.

2009-01-01

This hearing aid primer is designed to define the differences among the three levels of hearing instrument technology: conventional analog circuit technology (most basic), digitally programmable/analog circuit technology (moderately advanced), and fully digital technology (most advanced). Both moderate and advanced technologies mean that hearing…

47 CFR 36.121 - General.

Code of Federal Regulations, 2013 CFR

2013-10-01

...: Central Office Switching Account 2210. Non-digital Switching Account 2211. Digital Electronic Switching... Account 2231. Circuit Equipment Account 2232. (b) Records of the cost of central office equipment are... directly to that category, e.g., 130 volt power supply provided for circuit equipment. The cost of...

47 CFR 36.121 - General.

Code of Federal Regulations, 2014 CFR

2014-10-01

...: Central Office Switching Account 2210. Non-digital Switching Account 2211. Digital Electronic Switching... Account 2231. Circuit Equipment Account 2232. (b) Records of the cost of central office equipment are... directly to that category, e.g., 130 volt power supply provided for circuit equipment. The cost of...

47 CFR 36.121 - General.

Code of Federal Regulations, 2011 CFR

2011-10-01

...: Central Office Switching Account 2210. Non-digital Switching Account 2211. Digital Electronic Switching... Account 2231. Circuit Equipment Account 2232. (b) Records of the cost of central office equipment are... directly to that category, e.g., 130 volt power supply provided for circuit equipment. The cost of...

47 CFR 36.121 - General.

Code of Federal Regulations, 2010 CFR

2010-10-01

...: Central Office Switching Account 2210. Non-digital Switching Account 2211. Digital Electronic Switching... Account 2231. Circuit Equipment Account 2232. (b) Records of the cost of central office equipment are... directly to that category, e.g., 130 volt power supply provided for circuit equipment. The cost of...

47 CFR 36.121 - General.

Code of Federal Regulations, 2012 CFR

2012-10-01

...: Central Office Switching Account 2210. Non-digital Switching Account 2211. Digital Electronic Switching... Account 2231. Circuit Equipment Account 2232. (b) Records of the cost of central office equipment are... directly to that category, e.g., 130 volt power supply provided for circuit equipment. The cost of...

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

"Glitch Logic" and Applications to Computing and Information Security

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Katkoori, Srinivas

2009-01-01

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

About problematic peculiarities of Fault Tolerance digital regulation organization

NASA Astrophysics Data System (ADS)

Rakov, V. I.; Zakharova, O. V.

2018-05-01

The solution of problems concerning estimation of working capacity of regulation chains and possibilities of preventing situations of its violation in three directions are offered. The first direction is working out (creating) the methods of representing the regulation loop (circuit) by means of uniting (combining) diffuse components and forming algorithmic tooling for building predicates of serviceability assessment separately for the components and the for regulation loops (circuits, contours) in general. The second direction is creating methods of Fault Tolerance redundancy in the process of complex assessment of current values of control actions, closure errors and their regulated parameters. The third direction is creating methods of comparing the processes of alteration (change) of control actions, errors of closure and regulating parameters with their standard models or their surroundings. This direction allows one to develop methods and algorithmic tool means, aimed at preventing loss of serviceability and effectiveness of not only a separate digital regulator, but also the whole complex of Fault Tolerance regulation.

Substrate noise coupling: a pain for mixed-signal systems (Keynote Address)

NASA Astrophysics Data System (ADS)

Wambacq, Piet; Van der Plas, Geert; Donnay, Stephane; Badaroglu, Mustafa; Soens, Charlotte

2005-06-01

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

The development of learning material using learning goal orientation approach in digital electronics

NASA Astrophysics Data System (ADS)

Puspitaningayu, P.; Anifah, L.; Kholis, N.

2018-01-01

Mastery of digital electronics principles is essential for future engineers in the digital era. This article describes the use of simulations in an undergraduate electrical engineering course to promote the adoption of a learning-goal orientation. This study used experimental method. This was done by providing students with a simulation environment which students freely use to experiment with various circuit models. Students were then invited to reflect on how the simulation results compare with results from lab experiments. The module got 82% of positive rating from 28 students and all of them passed in the examination with 81.8 as the average score. Those majority students were motivated by the combination of two learning goals written in the module. Moreover, they also gain the ability to design more complex systems because of their combined experience. Additionally, the module also has been validated and got 83% of reliability. The final product of this research hereafter can be recommended to be used as teaching material.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Development of Boolean calculus and its applications. [digital systems design

NASA Technical Reports Server (NTRS)

Tapia, M. A.

1980-01-01

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

Wireless sensor platform for harsh environments

NASA Technical Reports Server (NTRS)

Garverick, Steven L. (Inventor); Yu, Xinyu (Inventor); Toygur, Lemi (Inventor); He, Yunli (Inventor)

2009-01-01

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna.

An Autonomous Circuit for the Measurement of Photovoltaic Devices Parameters.

DTIC Science & Technology

1986-09-01

Comparison Data, Gallium Arsenide ................ 80 A 7 A,. TABLE OF SYMBOLS A Curve Fitting Constant ADC Analog to Digital Converter AMO Air-Mass-Zero...in Radiation Fluence in the Logarithmic Region CMOS Complementary Metal-Oxide Semiconductor DAC Digital to Analog Converter DC Direct Current Dp Hole...characteristics of individual solar cells. A novel circuit is developed that uses a microprocessor controlled Digital to Analog Converter (DAC) to obtain

Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and Radio-Frequency Applications

DTIC Science & Technology

2012-02-07

circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The asobtained thin-film transistors ( TFTs ) exhibit... flexible substrates for digital, analog and radio frequency applications. The as- obtained thin-film transistors ( TFTs ) exhibit highly uniform device...LCD) and organic light- emitting diode ( OLED ) displays lack the transparency and flexibility and are thus unsuitable for flexible electronic

Superconductor Digital-RF Receiver Systems

NASA Astrophysics Data System (ADS)

Mukhanov, Oleg A.; Kirichenko, Dmitri; Vernik, Igor V.; Filippov, Timur V.; Kirichenko, Alexander; Webber, Robert; Dotsenko, Vladimir; Talalaevskii, Andrei; Tang, Jia Cao; Sahu, Anubhav; Shevchenko, Pavel; Miller, Robert; Kaplan, Steven B.; Sarwana, Saad; Gupta, Deepnarayan

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ˜30GHz clock frequencies.

Video rate morphological processor based on a redundant number representation

NASA Astrophysics Data System (ADS)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

PubMed

Li, Haitao; Boling, C Sam; Mason, Andrew J

2016-08-01

Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

Image-Enhancement Aid For The Partially Sighted

NASA Technical Reports Server (NTRS)

Lawton, T. A.; Gennery, D. B.

1989-01-01

Digital filtering enhances ability to read and to recognize objects. Possible to construct portable vision aid by combining miniature video equipment to observe scene and display images with very-large-scale integrated circuits to implement real-time digital image-data processing. Afflicted observer views scene through magnifier to shift spatial frequencies downward and thereby improves perceived image. However, less magnification needed, larger the scene observed. Thus, one measure of effectiveness of new system is amount of magnification required with and without it. In series of tests, found 27 to 70 percent more magnification needed for afflicted observers to recognize unfiltered words than to recognize filtered words.

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

A clocking discipline for two-phase digital integrated circuits

NASA Astrophysics Data System (ADS)

Noice, D. C.

1983-09-01

Sooner or later a designer of digital circuits must face the problem of timing verification so he can avoid errors caused by clock skew, critical races, and hazards. Unlike previous verification methods, such as timing simulation and timing analysis, the approach presented here guarantees correct operation despite uncertainty about delays in the circuit. The result is a clocking discipline that deals with timing abstractions only. It is not based on delay calculations; it is only concerned with the correct, synchronous operation at some clock rate. Accordingly, it may be used earlier in the design cycle, which is particularly important to integrated circuit designs. The clocking discipline consists of a notation of clocking types, and composition rules for using the types. Together, the notation and rules define a formal theory of two phase clocking. The notation defines the names and exact characteristics for different signals that are used in a two phase digital system. The notation makes it possible to develop rules for propagating the clocking types through particular circuits.

An Undergraduate Experiment in Alarm System Design.

ERIC Educational Resources Information Center

Martini, R. A.; And Others

1988-01-01

Describes an experiment involving data acquisition by a computer, digital signal transmission from the computer to a digital logic circuit and signal interpretation by this circuit. The system is being used at the Illinois Institute of Technology. Discusses the fundamental concepts involved. Demonstrates the alarm experiment as it is used in…

A Flipped First-Year Digital Circuits Course for Engineering and Technology Students

ERIC Educational Resources Information Center

Yelamarthi, Kumar; Drake, Eron

2015-01-01

This paper describes a flipped and improved first-year digital circuits (DC) course that incorporates several active learning strategies. With the primary objective of increasing student interest and learning, an integrated instructional design framework is proposed to provide first-year engineering and technology students with practical knowledge…

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E.

1974-01-01

Digital transmitter designed for Manchester coded signals (and all signals with ac waveforms) generated at a rate of one megabit per second includes efficient output isolation circuit. Transmitter consists of logic control section, amplifier, and output isolation section. Output isolation circuit provides dynamic impedance at terminals as function of amplifier output level.

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

Short circuit protection for a power distribution system

NASA Technical Reports Server (NTRS)

Owen, J. R., III

1969-01-01

Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

Upset susceptibility study employing circuit analysis and digital simulation. [digital systems and electromagnetic interference

NASA Technical Reports Server (NTRS)

Carreno, V. A.

1984-01-01

An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Correlation Between Analog Noise Measurements and the Expected Bit Error Rate of a Digital Signal Propagating Through Passive Components

NASA Technical Reports Server (NTRS)

Warner, Joseph D.; Theofylaktos, Onoufrios

2012-01-01

A method of determining the bit error rate (BER) of a digital circuit from the measurement of the analog S-parameters of the circuit has been developed. The method is based on the measurement of the noise and the standard deviation of the noise in the S-parameters. Once the standard deviation and the mean of the S-parameters are known, the BER of the circuit can be calculated using the normal Gaussian function.

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

PubMed

Aull, Brian

2016-04-08

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.

PubMed

Son, Hyunwoo; Cho, Hwasuk; Koo, Jahyun; Ji, Youngwoo; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2017-06-01

This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator, and a clocked comparator is followed for quantization. Without any continuous-time feedback circuit, the converter performs a first-order noise shaping of the quantization error. In order to minimize static power consumption, the proposed circuit employs a single-ended current-steering digital-to-analog converter which flows only the same current as the input. By adopting a switching noise averaging algorithm, our dynamic element matching not only mitigates mismatch of current sources in the current-steering DAC, but also makes the effect of dynamic switching noise become an input-independent constant. The implemented circuit in 0.35 μm CMOS converts the current input with a range of 2.8 μ A to 15 b digital output in about 4 ms, showing a DNL of +0.24/-0.25 LSB and an INL of + 1.98/-1.98 LSB while consuming 16.8 μW.

Results and Insights on the Impact of Smoke on Digital Instrumentation and Control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T. J.; Nowlen, S. P.

2001-01-31

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The major effect of smoke has been to increase leakage currents (through circuit bridging across contacts and leads) and tomore » cause momentary upsets and failures in digital systems. This report summarizes two previous reports and presents new results from conformal coating, memory chip, and hard drive tests. The report describes practices for mitigation of smoke damage through digital system design, fire barriers, ventilation, fire suppressants, and post fire procedures.« less

Synthetic analog and digital circuits for cellular computation and memory.

PubMed

Purcell, Oliver; Lu, Timothy K

2014-10-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene networks that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. Copyright © 2014 The Authors. Published by Elsevier Ltd.. All rights reserved.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata

2012-03-01

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Real-time emulation of neural images in the outer retinal circuit.

PubMed

Hasegawa, Jun; Yagi, Tetsuya

2008-12-01

We describe a novel real-time system that emulates the architecture and functionality of the vertebrate retina. This system reconstructs the neural images formed by the retinal neurons in real time by using a combination of analog and digital systems consisting of a neuromorphic silicon retina chip, a field-programmable gate array, and a digital computer. While the silicon retina carries out the spatial filtering of input images instantaneously, using the embedded resistive networks that emulate the receptive field structure of the outer retinal neurons, the digital computer carries out the temporal filtering of the spatially filtered images to emulate the dynamical properties of the outer retinal circuits. The emulations of the neural image, including 128 x 128 bipolar cells, are carried out at a frame rate of 62.5 Hz. The emulation of the response to the Hermann grid and a spot of light and an annulus of lights has demonstrated that the system responds as expected by previous physiological and psychophysical observations. Furthermore, the emulated dynamics of neural images in response to natural scenes revealed the complex nature of retinal neuron activity. We have concluded that the system reflects the spatiotemporal responses of bipolar cells in the vertebrate retina. The proposed emulation system is expected to aid in understanding the visual computation in the retina and the brain.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

The digital compensation technology system for automotive pressure sensor

NASA Astrophysics Data System (ADS)

Guo, Bin; Li, Quanling; Lu, Yi; Luo, Zai

2011-05-01

Piezoresistive pressure sensor be made of semiconductor silicon based on Piezoresistive phenomenon, has many characteristics. But since the temperature effect of semiconductor, the performance of silicon sensor is also changed by temperature, and the pressure sensor without temperature drift can not be produced at present. This paper briefly describe the principles of sensors, the function of pressure sensor and the various types of compensation method, design the detailed digital compensation program for automotive pressure sensor. Simulation-Digital mixed signal conditioning is used in this dissertation, adopt signal conditioning chip MAX1452. AVR singlechip ATMEGA128 and other apparatus; fulfill the design of digital pressure sensor hardware circuit and singlechip hardware circuit; simultaneously design the singlechip software; Digital pressure sensor hardware circuit is used to implementing the correction and compensation of sensor; singlechip hardware circuit is used to implementing to controll the correction and compensation of pressure sensor; singlechip software is used to implementing to fulfill compensation arithmetic. In the end, it implement to measure the output of sensor, and contrast to the data of non-compensation, the outcome indicates that the compensation precision of compensated sensor output is obviously better than non-compensation sensor, not only improving the compensation precision but also increasing the stabilization of pressure sensor.

The research of laser marking control technology

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong

2009-08-01

In the area of Laser marking, the general control method is insert control card to computer's mother board, it can not support hot swap, it is difficult to assemble or it. Moreover, the one marking system must to equip one computer. In the system marking, the computer can not to do the other things except to transmit marking digital information. Otherwise it can affect marking precision. Based on traditional control methods existed some problems, introduced marking graphic editing and digital processing by the computer finish, high-speed digital signal processor (DSP) control marking the whole process. The laser marking controller is mainly contain DSP2812, digital memorizer, DAC (digital analog converting) transform unit circuit, USB interface control circuit, man-machine interface circuit, and other logic control circuit. Download the marking information which is processed by computer to U disk, DSP read the information by USB interface on time, then processing it, adopt the DSP inter timer control the marking time sequence, output the scanner control signal by D/A parts. Apply the technology can realize marking offline, thereby reduce the product cost, increase the product efficiency. The system have good effect in actual unit markings, the marking speed is more quickly than PCI control card to 20 percent. It has application value in practicality.

Flywheel-Powered Mobile X-Ray Generator.

DTIC Science & Technology

1983-03-18

38 Circuit Description .. . . . . . . . .. 40 0. Digital Tachometer Purpose . . . . . . . . . . . . . . . 47 Operation...47 Circuit Description . . . . . . . . o 47 E. High Tension Transfoner Purpose . . . . . . . . . . . . . . . 51 Operation... Circuit Purpose . . . . . . . . . . . . . . . 54 Operation . . . . . . . . . . . . . . 54 G. Tube Rotor Control Purpose ........ . 57 Operation of Timer

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

Monitoring Digital Closed-Loop Feedback Systems

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

X-ray effects on pacemaker type circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blamires, N.G.; Myatt, J.

1982-03-01

Queries have been raised concerning the potential hazards of X-ray irradiation on patients using the new generation of heart pacemakers based on digital circuitry. The present study was undertaken to provide some answers to these queries. The work was conducted in two parts. First, a literature search was done and, second, circuits using current state of the art digital technology were irradiated with X-rays. Watch circuits were chosen because of their availability and built-in facilities by which their function could be tested. Doses up to 330 rads were administered to them using energies of 46, 114, and 141 KeV. Themore » conclusion drawn from both parts of the study was that X-rays used for diagnostic purposes were unlikely to affect the performance of this type of circuit in any way. It was accepted that for therapeutic purposes doses far in excess of this are administered and circuit malfunctions are likely to occur. To assess the probability of a digital pacemaker malfunctioning, samples of that particular type would have to be irradiated at the relevant dose.« less

47 CFR 32.6212 - Digital electronic switching expense.

Code of Federal Regulations, 2014 CFR

2014-10-01

... with digital electronic switching equipment used to provide circuit switching. (c) This subaccount 6212... 47 Telecommunication 2 2014-10-01 2014-10-01 false Digital electronic switching expense. 32.6212... Digital electronic switching expense. (a) This account shall include expenses associated with digital...

47 CFR 32.6212 - Digital electronic switching expense.

Code of Federal Regulations, 2011 CFR

2011-10-01

... with digital electronic switching equipment used to provide circuit switching. (c) This subaccount 6212... 47 Telecommunication 2 2011-10-01 2011-10-01 false Digital electronic switching expense. 32.6212... Digital electronic switching expense. (a) This account shall include expenses associated with digital...

47 CFR 32.6212 - Digital electronic switching expense.

Code of Federal Regulations, 2013 CFR

2013-10-01

... with digital electronic switching equipment used to provide circuit switching. (c) This subaccount 6212... 47 Telecommunication 2 2013-10-01 2013-10-01 false Digital electronic switching expense. 32.6212... Digital electronic switching expense. (a) This account shall include expenses associated with digital...

47 CFR 32.6212 - Digital electronic switching expense.

Code of Federal Regulations, 2010 CFR

2010-10-01

... with digital electronic switching equipment used to provide circuit switching. (c) This subaccount 6212... 47 Telecommunication 2 2010-10-01 2010-10-01 false Digital electronic switching expense. 32.6212... Digital electronic switching expense. (a) This account shall include expenses associated with digital...

47 CFR 32.6212 - Digital electronic switching expense.

Code of Federal Regulations, 2012 CFR

2012-10-01

... with digital electronic switching equipment used to provide circuit switching. (c) This subaccount 6212... 47 Telecommunication 2 2012-10-01 2012-10-01 false Digital electronic switching expense. 32.6212... Digital electronic switching expense. (a) This account shall include expenses associated with digital...

Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications

NASA Technical Reports Server (NTRS)

Adell, Philippe C. (Inventor); Bakkaloglu, Bertan (Inventor); Vermeire, Bert (Inventor); Liu, Tao (Inventor)

2015-01-01

A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.

Automatic Design of Digital Synthetic Gene Circuits

PubMed Central

Marchisio, Mario A.; Stelling, Jörg

2011-01-01

De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input–output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions. PMID:21399700

Digital optical processing of optical communications: towards an Optical Turing Machine

NASA Astrophysics Data System (ADS)

Touch, Joe; Cao, Yinwen; Ziyadi, Morteza; Almaiman, Ahmed; Mohajerin-Ariaei, Amirhossein; Willner, Alan E.

2017-01-01

Optical computing is needed to support Tb/s in-network processing in a way that unifies communication and computation using a single data representation that supports in-transit network packet processing, security, and big data filtering. Support for optical computation of this sort requires leveraging the native properties of optical wave mixing to enable computation and switching for programmability. As a consequence, data must be encoded digitally as phase (M-PSK), semantics-preserving regeneration is the key to high-order computation, and data processing at Tb/s rates requires mixing. Experiments have demonstrated viable approaches to phase squeezing and power restoration. This work led our team to develop the first serial, optical Internet hop-count decrement, and to design and simulate optical circuits for calculating the Internet checksum and multiplexing Internet packets. The current exploration focuses on limited-lookback computational models to reduce the need for permanent storage and hybrid nanophotonic circuits that combine phase-aligned comb sources, non-linear mixing, and switching on the same substrate to avoid the macroscopic effects that hamper benchtop prototypes.

An application specific integrated circuit based multi-anode microchannel array readout system

NASA Technical Reports Server (NTRS)

Smeins, Larry G.; Stechman, John M.; Cole, Edward H.

1991-01-01

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2017-05-01

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Neural Networks For Demodulation Of Phase-Modulated Signals

NASA Technical Reports Server (NTRS)

Altes, Richard A.

1995-01-01

Hopfield neural networks proposed for demodulating quadrature phase-shift-keyed (QPSK) signals carrying digital information. Networks solve nonlinear integral equations prior demodulation circuits cannot solve. Consists of set of N operational amplifiers connected in parallel, with weighted feedback from output terminal of each amplifier to input terminals of other amplifiers. Used to solve signal processing problems. Implemented as analog very-large-scale integrated circuit that achieves rapid convergence. Alternatively, implemented as digital simulation of such circuit. Also used to improve phase estimation performance over that of phase-locked loop.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Designing learning apparatus to promote twelfth grade students’ understanding of digital technology concept: A preliminary studies

NASA Astrophysics Data System (ADS)

Marlius; Kaniawati, I.; Feranie, S.

2018-05-01

A preliminary learning design using relay to promote twelfth grade student’s understanding of logic gates concept is implemented to see how well it’s to adopted by six high school students, three male students and three female students of twelfth grade. This learning design is considered for next learning of digital technology concept i.e. data digital transmition and analog. This work is a preliminary study to design the learning for large class. So far just a few researches designing learning design related to digital technology with relay. It may due to this concept inserted in Indonesian twelfth grade curriculum recently. This analysis is focus on student difficulties trough video analysis to learn the concept. Based on our analysis, the recommended thing for redesigning learning is: students understand first about symbols and electrical circuits; the Student Worksheet is made in more detail on the assembly steps to the project board; mark with symbols at points in certain places in the circuit for easy assembly; assembly using relays by students is enough until is the NOT’s logic gates and the others that have been assembled so that effective time. The design of learning using relays can make the relay a liaison between the abstract on the digital with the real thing of it, especially in the circuit of symbols and real circuits. Besides it is expected to also enrich the ability of teachers in classroom learning about digital technology.

A fast-locking PLL with all-digital locked-aid circuit

NASA Astrophysics Data System (ADS)

Kao, Shao-Ku; Hsieh, Fu-Jen

2013-02-01

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

Design of a 32-Channel EEG System for Brain Control Interface Applications

PubMed Central

Wang, Ching-Sung

2012-01-01

This study integrates the hardware circuit design and the development support of the software interface to achieve a 32-channel EEG system for BCI applications. Since the EEG signals of human bodies are generally very weak, in addition to preventing noise interference, it also requires avoiding the waveform distortion as well as waveform offset and so on; therefore, the design of a preamplifier with high common-mode rejection ratio and high signal-to-noise ratio is very important. Moreover, the friction between the electrode pads and the skin as well as the design of dual power supply will generate DC bias which affects the measurement signals. For this reason, this study specially designs an improved single-power AC-coupled circuit, which effectively reduces the DC bias and improves the error caused by the effects of part errors. At the same time, the digital way is applied to design the adjustable amplification and filter function, which can design for different EEG frequency bands. For the analog circuit, a frequency band will be taken out through the filtering circuit and then the digital filtering design will be used to adjust the extracted frequency band for the target frequency band, combining with MATLAB to design man-machine interface for displaying brain wave. Finally the measured signals are compared to the traditional 32-channel EEG signals. In addition to meeting the IFCN standards, the system design also conducted measurement verification in the standard EEG isolation room in order to demonstrate the accuracy and reliability of this system design. PMID:22778545

Design of a 32-channel EEG system for brain control interface applications.

PubMed

Wang, Ching-Sung

2012-01-01

This study integrates the hardware circuit design and the development support of the software interface to achieve a 32-channel EEG system for BCI applications. Since the EEG signals of human bodies are generally very weak, in addition to preventing noise interference, it also requires avoiding the waveform distortion as well as waveform offset and so on; therefore, the design of a preamplifier with high common-mode rejection ratio and high signal-to-noise ratio is very important. Moreover, the friction between the electrode pads and the skin as well as the design of dual power supply will generate DC bias which affects the measurement signals. For this reason, this study specially designs an improved single-power AC-coupled circuit, which effectively reduces the DC bias and improves the error caused by the effects of part errors. At the same time, the digital way is applied to design the adjustable amplification and filter function, which can design for different EEG frequency bands. For the analog circuit, a frequency band will be taken out through the filtering circuit and then the digital filtering design will be used to adjust the extracted frequency band for the target frequency band, combining with MATLAB to design man-machine interface for displaying brain wave. Finally the measured signals are compared to the traditional 32-channel EEG signals. In addition to meeting the IFCN standards, the system design also conducted measurement verification in the standard EEG isolation room in order to demonstrate the accuracy and reliability of this system design.

A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

NASA Astrophysics Data System (ADS)

Nasir, Z.; Ruslan, S. H.

2017-08-01

A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

A Simple Memristor Model for Circuit Simulations

NASA Astrophysics Data System (ADS)

Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team

This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.

A low-power small-area ADC array for IRFPA readout

NASA Astrophysics Data System (ADS)

Zhong, Shengyou; Yao, Libin

2013-09-01

The readout integrated circuit (ROIC) is a bridge between the infrared focal plane array (IRFPA) and image processing circuit in an infrared imaging system. The ROIC is the first part of signal processing circuit and connected to detectors directly, so its performance will greatly affect the detector or even the whole imaging system performance. With the development of CMOS technologies, it's possible to digitalize the signal inside the ROIC and develop the digital ROIC. Digital ROIC can reduce complexity of the whole system and improve the system reliability. More importantly, it can accommodate variety of digital signal processing techniques which the traditional analog ROIC cannot achieve. The analog to digital converter (ADC) is the most important building block in the digital ROIC. The requirements for ADCs inside the ROIC are low power, high dynamic range and small area. In this paper we propose an RC hybrid Successive Approximation Register (SAR) ADC as the column ADC for digital ROIC. In our proposed ADC structure, a resistor ladder is used to generate several voltages. The proposed RC hybrid structure not only reduces the area of capacitor array but also releases requirement for capacitor array matching. Theory analysis and simulation show RC hybrid SAR ADC is suitable for ADC array applications

Concept For Generation Of Long Pseudorandom Sequences

NASA Technical Reports Server (NTRS)

Wang, C. C.

1990-01-01

Conceptual very-large-scale integrated (VLSI) digital circuit performs exponentiation in finite field. Algorithm that generates unusually long sequences of pseudorandom numbers executed by digital processor that includes such circuits. Concepts particularly advantageous for such applications as spread-spectrum communications, cryptography, and generation of ranging codes, synthetic noise, and test data, where usually desirable to make pseudorandom sequences as long as possible.

DEAL annual report.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Misra, Shashank

2017-11-01

The digital electronics at the atomic limit (DEAL) project seeks to leverage Sandia's atomic-precision fabrication capability to realize the theorized orders-of-magnitude improvement in operating voltage for tunnel field effect transistors (TFETs) compared to CMOS. Not only are low-power digital circuits a critical element of many national security systems (e.g. satellites), TFETs can perform circuit functions inaccessible to CMOS (e.g. polymorphism).

Some Specifications for an Undergraduate Course in Digital Subsystems. An Interim Report of the Cosine Committee.

ERIC Educational Resources Information Center

Commission on Engineering Education, Washington, DC.

This report describes an undergraduate course in digital subsystems. The course is divided into two major parts. Part I is entitled Electronic Circuits and Functional Units. The material in this part of the course proceeds from simple understandings of circuits to the progressively more complex functional units. Early emphasis is placed on basic…

Upset susceptibility study employing circuit analysis and digital simulation

NASA Technical Reports Server (NTRS)

Carreno, V. A.

1984-01-01

This paper describes an approach to predicting the susceptibility of digital systems to signal disturbances. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, Electromagnetic Interference (EMI) and Electromagnetic Pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload will bring the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The Super-Sceptre (system for circuit evaluation of transient radiation effects) Program was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Spacelab, Spacehab, and Space Station Freedom payload interface projects

NASA Technical Reports Server (NTRS)

Smith, Dean Lance

1992-01-01

Contributions were made to several projects. Howard Nguyen was assisted in developing the Space Station RPS (Rack Power Supply). The RPS is a computer controlled power supply that helps test equipment used for experiments before the equipment is installed on Space Station Freedom. Ron Bennett of General Electric Government Services was assisted in the design and analysis of the Standard Interface Rack Controller hardware and software. An analysis was made of the GPIB (General Purpose Interface Bus), looking for any potential problems while transmitting data across the bus, such as the interaction of the bus controller with a data talker and its listeners. An analysis was made of GPIB bus communications in general, including any negative impact the bus may have on transmitting data back to Earth. A study was made of transmitting digital data back to Earth over a video channel. A report was written about the study and a revised version of the report will be submitted for publication. Work was started on the design of a PC/AT compatible circuit board that will combine digital data with a video signal. Another PC/AT compatible circuit board is being designed to recover the digital data from the video signal. A proposal was submitted to support the continued development of the interface boards after the author returns to Memphis State University in the fall. A study was also made of storing circuit board design software and data on the hard disk server of a LAN (Local Area Network) that connects several IBM style PCs. A report was written that makes several recommendations. A preliminary design review was started of the AIVS (Automatic Interface Verification System). The summer was over before any significant contribution could be made to this project.

Educational-research laboratory "electric circuits" on the base of digital technologies

NASA Astrophysics Data System (ADS)

Koroteyev, V. I.; Florentsev, V. V.; Florentseva, N. I.

2017-01-01

The problem of research activity of trainees' activation in the educational-research laboratory "Electric Circuits" using innovative methodological solutions and digital technologies is considered. The main task is in creation of the unified experimental research information-educational environment "Electrical Engineering". The problems arising during the developing and application of the modern software and hardware, experimental and research stands and digital control and measuring systems are presented. This paper presents the main stages of development and creation of educational-research laboratory "Electrical Circuits" at the Department of Electrical Engineering of NRNU MEPhI. The authors also consider the analogues of the described research complex offered by various educational institutions and companies. The analysis of their strengths and weaknesses, on which the advantages of the proposed solution are based, is held.

Encrypting Digital Camera with Automatic Encryption Key Deletion

NASA Technical Reports Server (NTRS)

Oakley, Ernest C. (Inventor)

2007-01-01

A digital video camera includes an image sensor capable of producing a frame of video data representing an image viewed by the sensor, an image memory for storing video data such as previously recorded frame data in a video frame location of the image memory, a read circuit for fetching the previously recorded frame data, an encryption circuit having an encryption key input connected to receive the previously recorded frame data from the read circuit as an encryption key, an un-encrypted data input connected to receive the frame of video data from the image sensor and an encrypted data output port, and a write circuit for writing a frame of encrypted video data received from the encrypted data output port of the encryption circuit to the memory and overwriting the video frame location storing the previously recorded frame data.

Miniature Housings for Electronics With Standard Interfaces

NASA Technical Reports Server (NTRS)

Howard, David E.; Smith, Dennis A.; Alhorn, Dean C.

2006-01-01

A family of general-purpose miniature housings has been designed to contain diverse sensors, actuators, and drive circuits plus associated digital electronic readout and control circuits. The circuits contained in the housings communicate with the external world via standard RS-485 interfaces.

Single Circuit Board Implementation of a Digitally Compensated SAW Oscillator (DCSO).

DTIC Science & Technology

1983-12-01

Through this project a design for a Digitally Compensated SAW Oscillator (DCSO) was developed and implemented on a single circuit board. The AFIT IC, which...is the heart of the design , did not function properly. Therefore, my work was halted after testing several of the subcircuits and assembling the...o.... -7 Standards ........ o..o....... -8 Approach-9 Sequence of Presentation .................. -10 II, Design

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Modeling from Local to Subsystem Level Effects in Analog and Digital Circuits Due to Space Induced Single Event Transients

NASA Technical Reports Server (NTRS)

Perez, Reinaldo J.

2011-01-01

Single Event Transients in analog and digital electronics from space generated high energetic nuclear particles can disrupt either temporarily and sometimes permanently the functionality and performance of electronics in space vehicles. This work first provides some insights into the modeling of SET in electronic circuits that can be used in SPICE-like simulators. The work is then directed to present methodologies, one of which was developed by this author, for the assessment of SET at different levels of integration in electronics, from the circuit level to the subsystem level.

Development of Fast Measurement System of Neutron Emission Profile Using a Digital Signal Processing Technique in JT-60U

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishikawa, M.; Shinohara, K.; Itoga, T.

2008-03-12

Neutron emission profiles are routinely measured in JT-60U Tokamak. Stinbene neuron detectors (SNDs), which combine a Stilbene organic crystal scintillation detector (Stilbene detector) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure neutron flux efficiently. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to {approx}1x 10{sup 5} counts/s due to the dead time of the analog PSD circuit. To overcome this issue, a digital signal processing (DSP) system using a Flash-ADC has been developed. In this system, anode signals from the photomultiplier of the Stilbene detectormore » are fed to the Flash ADC and digitized. Then, the PSD between neutrons and gamma-rays are performed using software. The photomultiplier tube is also modified to suppress and correct gain fluctuation of the photomultiplier. The DSP system has been installed in the center channel of the vertical neutron collimator system in JT-60U and applied to measurements of neutron flux in JT-60U experiments. Neutron flux are successfully measured with count rate up to {approx}1x 10{sup 6} counts/s without the effect of pile up of detected pulses. The performance of the DSP system as a neutron detector is demonstrated.« less

Designed cell consortia as fragrance-programmable analog-to-digital converters.

PubMed

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Simple photometer circuits using modular electronic components

NASA Technical Reports Server (NTRS)

Wampler, J. E.

1975-01-01

Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

General purpose computer programs for numerically analyzing linear ac electrical and electronic circuits for steady-state conditions

NASA Technical Reports Server (NTRS)

Egebrecht, R. A.; Thorbjornsen, A. R.

1967-01-01

Digital computer programs determine steady-state performance characteristics of active and passive linear circuits. The ac analysis program solves the basic circuit parameters. The compiler program solves these circuit parameters and in addition provides a more versatile program by allowing the user to perform mathematical and logical operations.

77 FR 64374 - Notification of Petition for Approval; Port Authority Trans-Hudson Product Safety Plan

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-19

... assigned the petition Docket Number FRA-2012-0075. PATH is upgrading some of its track circuits with Digicode microprocessor-based track circuits. The Digicode track circuit is part of Alstom's Smartway Digital Track Circuit product line and will be used by PATH for train detection and broken rail detection...

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Fast, High-Precision Readout Circuit for Detector Arrays

NASA Technical Reports Server (NTRS)

Rider, David M.; Hancock, Bruce R.; Key, Richard W.; Cunningham, Thomas J.; Wrigley, Chris J.; Seshadri, Suresh; Sander, Stanley P.; Blavier, Jean-Francois L.

2013-01-01

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers

NASA Astrophysics Data System (ADS)

Kondo, Hideaki; Sawada, Masaru; Murakami, Norio; Masui, Shoichi

This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than ±3.5% and lower a peaking in the passband filter characteristics. An experimental complex BPF using 0.18µm CMOS technology can successfully reduce the tuning error from an initial value of -20% to less than ±2.5% after tuning. The filter block dimensions are 1.22mm × 1.01mm; and in measurement results of the developed complex BPF with the automatic digital tuning circuit, current consumption is 705µA and the image rejection ratio is 40.3dB. Complete evaluation of the BPF indicates that this technique can be applied to low-power, low-cost transceivers.

The Effects of Space Radiation on Linear Integrated Circuit

NASA Technical Reports Server (NTRS)

Johnston, A.

2000-01-01

Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

47 CFR 32.2211 - Non-digital switching.

Code of Federal Regulations, 2010 CFR

2010-10-01

... switching. (a) This account shall include: (1) Original cost of stored program control analog circuit-switching and associated equipment. (2) Cost of remote analog electronic circuit switches. (3) Original cost of non-electronic circuit-switching equipment such as Step-by-Step, Crossbar, and Other Electro...

47 CFR 32.2211 - Non-digital switching.

Code of Federal Regulations, 2013 CFR

2013-10-01

... switching. (a) This account shall include: (1) Original cost of stored program control analog circuit-switching and associated equipment. (2) Cost of remote analog electronic circuit switches. (3) Original cost of non-electronic circuit-switching equipment such as Step-by-Step, Crossbar, and Other Electro...

47 CFR 32.2211 - Non-digital switching.

Code of Federal Regulations, 2012 CFR

2012-10-01

... switching. (a) This account shall include: (1) Original cost of stored program control analog circuit-switching and associated equipment. (2) Cost of remote analog electronic circuit switches. (3) Original cost of non-electronic circuit-switching equipment such as Step-by-Step, Crossbar, and Other Electro...

47 CFR 32.2211 - Non-digital switching.

Code of Federal Regulations, 2011 CFR

2011-10-01

... switching. (a) This account shall include: (1) Original cost of stored program control analog circuit-switching and associated equipment. (2) Cost of remote analog electronic circuit switches. (3) Original cost of non-electronic circuit-switching equipment such as Step-by-Step, Crossbar, and Other Electro...

47 CFR 32.2211 - Non-digital switching.

Code of Federal Regulations, 2014 CFR

2014-10-01

... switching. (a) This account shall include: (1) Original cost of stored program control analog circuit-switching and associated equipment. (2) Cost of remote analog electronic circuit switches. (3) Original cost of non-electronic circuit-switching equipment such as Step-by-Step, Crossbar, and Other Electro...

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

NASA Technical Reports Server (NTRS)

Schuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li; Madala, Shridhar

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

PubMed Central

Zatorre, Guillermo; Medrano, Nicolás; Sanz, María Teresa; Aldea, Concepción; Calvo, Belén; Celma, Santiago

2009-01-01

This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components. PMID:22412331

Impact of Smoke Exposure on Digital Instrumentation and Control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, Tina J.; Nowlen, Steven P.; Korsah, Kofi

2003-08-15

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke hasmore » been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers' IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.« less

Instrumented Glove Measures Positions Of Fingers

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1993-01-01

Glove instrumented with flat membrane potentiometers to obtain crude measurements of relative positions of fingers. Resistance of each potentiometer varies with position of associated finger; translator circuit connected to each potentiometer converts analog reading to 1 of 10 digital levels. Digitized outputs from all fingers fed to indicating, recording, and/or data-processing equipment. Gloves and circuits intended for use in biomedical research, training in critical manual tasks, and other specialized applications.

Proton irradiation effects on advanced digital and microwave III-V components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hash, G.L.; Schwank, J.R.; Shaneyfelt, M.R.

1994-09-01

A wide range of advanced III-V components suitable for use in high-speed satellite communication systems were evaluated for displacement damage and single-event effects in high-energy, high-fluence proton environments. Transistors and integrated circuits (both digital and MMIC) were irradiated with protons at energies from 41 to 197 MeV and at fluences from 10{sup 10} to 2 {times} 10{sup 14} protons/cm{sup 2}. Large soft-error rates were measured for digital GaAs MESFET (3 {times} 10{sup {minus}5} errors/bit-day) and heterojunction bipolar circuits (10{sup {minus}5} errors/bit-day). No transient signals were detected from MMIC circuits. The largest degradation in transistor response caused by displacement damage wasmore » observed for 1.0-{mu}m depletion- and enhancement-mode MESFET transistors. Shorter gate length MESFET transistors and HEMT transistors exhibited less displacement-induced damage. These results show that memory-intensive GaAs digital circuits may result in significant system degradation due to single-event upset in natural and man-made space environments. However, displacement damage effects should not be a limiting factor for fluence levels up to 10{sup 14} protons/cm{sup 2} [equivalent to total doses in excess of 10 Mrad(GaAs)].« less

Proton irradiation effects on advanced digital and microwave III-V components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hash, G.L.; Schwank, J.R.; Shaneyfelt, M.R.

1994-12-01

A wide range of advanced III-V components suitable for use in high-speed satellite communication systems were evaluated for displacement damage and single-event effects in high-energy, high-fluence proton environments. Transistors and integrated circuits (both digital and MMIC) were irradiated with protons at energies from 41 to 197 MeV and at fluences from 10[sup 10] to 2 [times] 10[sup 14] protons/cm[sup 2]. Large soft-error rates were measured for digital GaAs MESFET (3 [times] 10[sup [minus]5] errors/bit-day) and heterojunction bipolar circuits (10[sup [minus]5] errors/bit-day). No transient signals were detected from MMIC circuits. The largest degradation in transistor response caused by displacement damage wasmore » observed for 1.0-[mu]m depletion- and enhancement-mode MESFET transistors. Shorter gate length MESFET transistors and HEMT transistors exhibited less displacement-induced damage. These results show that memory-intensive GaAs digital circuits may result in significant system degradation due to single-event upset in natural and man-made space environments. However, displacement damage effects should not be a limiting factor for fluence levels up to 10[sup 14] protons/cm[sup 2] [equivalent to total doses in excess of 10 Mrad (GaAs)].« less

47 CFR 32.5999 - General.

Code of Federal Regulations, 2014 CFR

2014-10-01

... switching expense 6210 Non-digital switching expense 6211 Digital electronic switching expense 6212... Circuit equipment expense 6232 Information origination/termination expense 6310 Station apparatus expense...

47 CFR 32.5999 - General.

Code of Federal Regulations, 2012 CFR

2012-10-01

... switching expense 6210 Non-digital switching expense 6211 Digital electronic switching expense 6212... Circuit equipment expense 6232 Information origination/termination expense 6310 Station apparatus expense...

47 CFR 32.5999 - General.

Code of Federal Regulations, 2013 CFR

2013-10-01

... switching expense 6210 Non-digital switching expense 6211 Digital electronic switching expense 6212... Circuit equipment expense 6232 Information origination/termination expense 6310 Station apparatus expense...

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

CIRCUS--A digital computer program for transient analysis of electronic circuits

NASA Technical Reports Server (NTRS)

Moore, W. T.; Steinbert, L. L.

1968-01-01

Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

NASA Technical Reports Server (NTRS)

Harper, Michael; Miller, Joseph; Shen, Yuzhong

2011-01-01

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Low-power wireless ECG acquisition and classification system for body sensor networks.

PubMed

Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

2015-01-01

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

The research of PSD location method in micro laser welding fields

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong; Dong, Hua

2010-11-01

In the field of micro laser welding, besides the special requirement in the parameter of lasers, the locating in welding points accurately is very important. The article adopt position sensitive detector (PSD) as hard core, combine optic system, electric circuits and PC and software processing, confirm the location of welding points. The signal detection circuits adopt the special integrate circuit H-2476 to process weak signal. It is an integrated circuit for high-speed, high-sensitivity optical range finding, which has stronger noiseproof feature, combine digital filter arithmetic, carry out repair the any non-ideal factors, increasing the measure precision. The amplifier adopt programmable amplifier LTC6915. The system adapt two dimension stepping motor drive the workbench, computer and corresponding software processing, make sure the location of spot weld. According to different workpieces to design the clamps. The system on-line detect PSD 's output signal in the moving processing. At the workbench moves in the X direction, the filaments offset is detected dynamic. Analyze the X axes moving sampling signal direction could be estimate the Y axes moving direction, and regulate the Y axes moving values. The workbench driver adopt A3979, it is a stepping motor driver with insert transducer and operate easily. It adapts the requirement of location in micro laser welding fields, real-time control to adjust by computer. It can be content up 20 μm's laser micro welding requirement on the whole. Using laser powder cladding technology achieve inter-penetration welding of high quality and reliability.

Digital ac monitor

DOEpatents

Hart, George W.; Kern, Jr., Edward C.

1987-06-09

An apparatus and method is provided for monitoring a plurality of analog ac circuits by sampling the voltage and current waveform in each circuit at predetermined intervals, converting the analog current and voltage samples to digital format, storing the digitized current and voltage samples and using the stored digitized current and voltage samples to calculate a variety of electrical parameters; some of which are derived from the stored samples. The non-derived quantities are repeatedly calculated and stored over many separate cycles then averaged. The derived quantities are then calculated at the end of an averaging period. This produces a more accurate reading, especially when averaging over a period in which the power varies over a wide dynamic range. Frequency is measured by timing three cycles of the voltage waveform using the upward zero crossover point as a starting point for a digital timer.

Digital ac monitor

DOEpatents

Hart, G.W.; Kern, E.C. Jr.

1987-06-09

An apparatus and method is provided for monitoring a plurality of analog ac circuits by sampling the voltage and current waveform in each circuit at predetermined intervals, converting the analog current and voltage samples to digital format, storing the digitized current and voltage samples and using the stored digitized current and voltage samples to calculate a variety of electrical parameters; some of which are derived from the stored samples. The non-derived quantities are repeatedly calculated and stored over many separate cycles then averaged. The derived quantities are then calculated at the end of an averaging period. This produces a more accurate reading, especially when averaging over a period in which the power varies over a wide dynamic range. Frequency is measured by timing three cycles of the voltage waveform using the upward zero crossover point as a starting point for a digital timer. 24 figs.

Design of Efficient Mirror Adder in Quantum- Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Mishra, Prashant Kumar; Chattopadhyay, Manju K.

2018-03-01

Lower power consumption is an essential demand for portable multimedia system using digital signal processing algorithms and architectures. Quantum dot cellular automata (QCA) is a rising nano technology for the development of high performance ultra-dense low power digital circuits. QCA based several efficient binary and decimal arithmetic circuits are implemented, however important improvements are still possible. This paper demonstrate Mirror Adder circuit design in QCA. We present comparative study of mirror adder cells designed using conventional CMOS technique and mirror adder cells designed using quantum-dot cellular automata. QCA based mirror adders are better in terms of area by order of three.

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

NASA Technical Reports Server (NTRS)

Rao, Hariprasad Nannapaneni

1989-01-01

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.

Analysis and synthesis of distributed-lumped-active networks by digital computer

NASA Technical Reports Server (NTRS)

1973-01-01

The use of digital computational techniques in the analysis and synthesis of DLA (distributed lumped active) networks is considered. This class of networks consists of three distinct types of elements, namely, distributed elements (modeled by partial differential equations), lumped elements (modeled by algebraic relations and ordinary differential equations), and active elements (modeled by algebraic relations). Such a characterization is applicable to a broad class of circuits, especially including those usually referred to as linear integrated circuits, since the fabrication techniques for such circuits readily produce elements which may be modeled as distributed, as well as the more conventional lumped and active ones.

Advanced digital SAR processing study

NASA Technical Reports Server (NTRS)

Martinson, L. W.; Gaffney, B. P.; Liu, B.; Perry, R. P.; Ruvin, A.

1982-01-01

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

GaAs digital dynamic IC's for applications up to 10 GHz

NASA Astrophysics Data System (ADS)

Rocchi, M.; Gabillard, B.

1983-06-01

To evaluate the potentiality of GaAs MESFET's as transmitting gates, dynamic TT-bar flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

Fault Model Development for Fault Tolerant VLSI Design

DTIC Science & Technology

1988-05-01

0 % .%. . BEIDGING FAULTS A bridging fault in a digital circuit connects two or more conducting paths of the circuit. The resistance...Melvin Breuer and Arthur Friedman, "Diagnosis and Reliable Design of Digital Systems", Computer Science Press, Inc., 1976. 4. [Chandramouli,1983] R...2138 AEDC LIBARY (TECH REPORTS FILE) MS-O0 ARNOLD AFS TN 37389-9998 USAG1 Attn: ASH-PCA-CRT Ft Huachuca AZ 85613-6000 DOT LIBRARY/iQA SECTION - ATTN

Specifying and calibrating instrumentations for wideband electronic power measurements. [in switching circuits

NASA Technical Reports Server (NTRS)

Lesco, D. J.; Weikle, D. H.

1980-01-01

The wideband electric power measurement related topics of electronic wattmeter calibration and specification are discussed. Tested calibration techniques are described in detail. Analytical methods used to determine the bandwidth requirements of instrumentation for switching circuit waveforms are presented and illustrated with examples from electric vehicle type applications. Analog multiplier wattmeters, digital wattmeters and calculating digital oscilloscopes are compared. The instrumentation characteristics which are critical to accurate wideband power measurement are described.

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Synthesis of a fully-integrated digital signal source for communications from chaotic dynamics-based oscillations

NASA Astrophysics Data System (ADS)

Glenn, Chance Michael, Sr.

This work is the conceptualization, derivation, analysis, and fabrication of a fully practical digital signal source designed from a chaotic oscillator. In it we show how a simple electronic circuit based upon the Colpitts oscillator, can be made to produce highly complex signals capable of carrying digital information. We show a direct relationship between the continuous-time chaotic oscillations produced by the circuit and the logistic map, which is discrete-time, one-dimensional map that is a fundamental paradigm for the study of chaotic systems. We demonstrate the direct encoding of binary information into the oscillations of the chaotic circuit. We demonstrate a new concept in power amplification, called syncrodyne amplification , which uses fundamental properties of chaotic oscillators to provide high-efficiency, high gain amplification of standard communication waveforms as well as typical chaotic oscillations. We show modeling results of this system providing nearly 60-dB power gain and 80% PAE for communications waveforms conforming to GMSK modulation. Finally we show results from a fabricated syncrodyne amplifier circuit operating at 2 MHz, providing over 40-dB power gain and 72% PAE, and propose design criteria for an 824--850 MHz circuit utilizing heterojunction bipolar transistors (HBTs), providing the basis for microwave frequency realization.

Digital phase shifter synchronizes local oscillators

NASA Technical Reports Server (NTRS)

Ali, S. M.

1978-01-01

Digital phase-shifting network is used as synchronous frequency multiplier for applications such as phase-locking two signals that may differ in frequency. Circuit has various phase-shift capability. Possible applications include data-communication systems and hybrid digital/analog phase-locked loops.

The Art of Electronics - 2nd Edition

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

1989-09-01

This is the thoroughly revised and updated second edition of the hugely successful The Art of Electronics. Widely accepted as the single authoritative text and reference on electronic circuit design, both analog and digital, the original edition sold over 125,000 copies worldwide and was translated into eight languages. The book revolutionized the teaching of electronics by emphasizing the methods actually used by citcuit designers - a combination of some basic laws, rules to thumb, and a large nonmathematical treatment that encourages circuit values and performance. The new Art of Electronics retains the feeling of informality and easy access that helped make the first edition so successful and popular. It is an ideal first textbook on electronics for scientists and engineers and an indispensable reference for anyone, professional or amateur, who works with electronic circuits. The best self-teaching book and reference book in electronics Simply indispensable, packed with essential information for all scientists and engineers who build electronic circuits Totally rewritten chapters on microcomputers and microprocessors The first edition of this book has sold over 100,000 copies in seven years, it has a market in virtually all research centres where electronics is important

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Multi-resonant piezoelectric shunting induced by digital controllers for subwavelength elastic wave attenuation in smart metamaterial

NASA Astrophysics Data System (ADS)

Wang, Gang; Cheng, Jianqing; Chen, Jingwei; He, Yunze

2017-02-01

Instead of analog electronic circuits and components, digital controllers that are capable of active multi-resonant piezoelectric shunting are applied to elastic metamaterials integrated with piezoelectric patches. Thanks to recently introduced digital control techniques, shunting strategies are possible now with transfer functions that can hardly be realized with analog circuits. As an example, the ‘pole-zero’ method is developed to design single- or multi-resonant bandgaps by adjusting poles and zeros in the transfer function of piezoelectric shunting directly. Large simultaneous attenuations in up to three frequency bands at deep subwavelength scale (with normalized frequency as low as 0.077) are achieved. The underlying physical mechanism is attributable to the negative group velocity of the flexural wave within bandgaps. As digital controllers can be readily adapted via wireless broadcasting, the bandgaps can be tuned easily unlike the electric components in analog shunting circuits, which must be tuned one by one manually. The theoretical results are verified experimentally with the measured vibration transmission properties, where large insulations of up to 20 dB in low-frequency ranges are observed.

Gated high speed optical detector

NASA Technical Reports Server (NTRS)

Green, S. I.; Carson, L. M.; Neal, G. W.

1973-01-01

The design, fabrication, and test of two gated, high speed optical detectors for use in high speed digital laser communication links are discussed. The optical detectors used a dynamic crossed field photomultiplier and electronics including dc bias and RF drive circuits, automatic remote synchronization circuits, automatic gain control circuits, and threshold detection circuits. The equipment is used to detect binary encoded signals from a mode locked neodynium laser.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Signal to Noise Ratio SPICE Simulation Program with Integrated Circuit Emphasis TIFF Tagged Image File Format USC University of Southern California xvii...sources can create errors in digital circuits. These effects can be simulated using Simulation Program with Integrated Circuit Emphasis ( SPICE ) or...compute summary statistics. 4.1 Circuit Simulations Noisy analog circuits can be simulated in SPICE or Cadence SpectreTM software via noisy voltage

In-line Microwave Warmer for Blood and Intravenous Fluids.

DTIC Science & Technology

1989-12-14

circuit was designed and tested. This circuit uses a digitally controlled optically coupled Triac , a thyristor device, which acts as a switch to allow...three sites of the circuit : Inlet Port of Heating Chamber Interior Path of Heating Chamber Outlet Port of Heating Chamber 4) Feedback Control Mechanism...accomplished through use of a closed loop test circuit depicted in Figure 1-2. This test circuit can be used to heat iv fluids or blood on a continuous

Implementing neural nets with programmable logic

NASA Technical Reports Server (NTRS)

Vidal, Jacques J.

1988-01-01

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Digital lock-in amplifier based on soundcard interface for physics laboratory

NASA Astrophysics Data System (ADS)

Sinlapanuntakul, J.; Kijamnajsuk, P.; Jetjamnong, C.; Chotikaprakhan, S.

2017-09-01

The purpose of this paper is to develop a digital lock-in amplifier based on soundcard interface for undergraduate physics laboratory. Both series and parallel RLC circuit laboratory are tested because of its well-known, easy to understand and simple confirm. The sinusoidal signal at the frequency of 10 Hz - 15 kHz is generated to the circuits. The amplitude and phase of the voltage drop across the resistor, R are measured in 10 step decade. The signals from soundcard interface and lock-in amplifier are compared. The results give a good correlation. It indicates that the design digital lock-in amplifier is promising for undergraduate physic laboratory.

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

Closed circuit TV system automatically guides welding arc

NASA Technical Reports Server (NTRS)

Stephans, D. L.; Wall, W. A., Jr.

1968-01-01

Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

A novel CMOS transducer for giant magnetoresistance sensors.

PubMed

Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

2017-02-01

In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μm CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

Biological Signal Processing with a Genetic Toggle Switch

PubMed Central

Hillenbrand, Patrick; Fritz, Georg; Gerland, Ulrich

2013-01-01

Complex gene regulation requires responses that depend not only on the current levels of input signals but also on signals received in the past. In digital electronics, logic circuits with this property are referred to as sequential logic, in contrast to the simpler combinatorial logic without such internal memory. In molecular biology, memory is implemented in various forms such as biochemical modification of proteins or multistable gene circuits, but the design of the regulatory interface, which processes the input signals and the memory content, is often not well understood. Here, we explore design constraints for such regulatory interfaces using coarse-grained nonlinear models and stochastic simulations of detailed biochemical reaction networks. We test different designs for biological analogs of the most versatile memory element in digital electronics, the JK-latch. Our analysis shows that simple protein-protein interactions and protein-DNA binding are sufficient, in principle, to implement genetic circuits with the capabilities of a JK-latch. However, it also exposes fundamental limitations to its reliability, due to the fact that biological signal processing is asynchronous, in contrast to most digital electronics systems that feature a central clock to orchestrate the timing of all operations. We describe a seemingly natural way to improve the reliability by invoking the master-slave concept from digital electronics design. This concept could be useful to interpret the design of natural regulatory circuits, and for the design of synthetic biological systems. PMID:23874595

Ultrastable automatic frequency control

NASA Technical Reports Server (NTRS)

Sabourin, D. J.; Furiga, A.

1981-01-01

Center frequency of wideband AFC circuit drifts only hundredths of percent per day. Since circuit responds only to slow frequency drifts and modulation signal has high-pass characteristics, AFC does not interfere with normal FM operation. Stable oscillator, reset circuit, and pulse generator constitute time-averaging discriminator; digital counter in pulse generator replaces usual monostable multivibrator.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

Weather satellite picture receiving stations, APT digital scan converter

NASA Technical Reports Server (NTRS)

Vermillion, C. H.; Kamowski, J. C.

1975-01-01

The automatic picture transmission digital scan converter is used at ground stations to convert signals received from scanning radiometers to data compatible with ground equipment designed to receive signals from vidicons aboard operational meteorological satellites. Information necessary to understand the circuit theory, functional operation, general construction and calibration of the converter is provided. Brief and detailed descriptions of each of the individual circuits are included, accompanied by a schematic diagram contained at the end of each circuit description. Listings of integral parts and testing equipment required as well as an overall wiring diagram are included. This unit will enable the user to readily accept and process weather photographs from the operational meteorological satellites.

Area-efficient physically unclonable function circuit architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gurrieri, Thomas; Hamlet, Jason; Bauer, Todd

Generating a physically a physically unclonable function ("PUF") circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. Amore » PUF circuit value is generated from the digital bit values from each comparison made.« less

180-GHz Interferometric Imager

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Lim, Boon H.; O'Dwyer, Ian J.; Soria, Mary M.; Owen, Heather R.; Gaier, Todd C.; Lambrigtsen, Bjorn, H.; Tanner, Alan B.; Ruf, Christopher

2011-01-01

A 180-GHz interferometric imager uses compact receiver modules, combined high- and low-gain antennas, and ASIC (application specific integrated circuit) correlator technology, enabling continuous, all-weather observations of water vapor with 25-km resolution and 0.3-K noise in 15 minutes of observation for numerical weather forecasting and tropical storm prediction. The GeoSTAR-II prototype instrument is broken down into four major subsystems: the compact, low-noise receivers; sub-array modules; IF signal distribution; and the digitizer/correlator. Instead of the single row of antennas adopted in GeoSTAR, this version has four rows of antennas on a coarser grid. This dramatically improves the sensitivity in the desired field of view. The GeoSTAR-II instrument is a 48-element, synthetic, thinned aperture radiometer operating at 165-183 GHz. The instrument has compact receivers integrated into tiles of 16 elements in a 4x4 arrangement. These tiles become the building block of larger arrays. The tiles contain signal distribution for bias controls, IF signal, and local oscillator signals. The IF signals are digitized and correlated using an ASIC correlator to minimize power consumption. Previous synthetic aperture imagers have used comparatively large multichip modules, whereas this approach uses chip-scale modules mounted on circuit boards, which are in turn mounted on the distribution manifolds. This minimizes the number of connectors and reduces system mass. The use of ASIC technology in the digitizers and correlators leads to a power reduction close to an order of magnitude.

Energy-Efficient Neuromorphic Classifiers.

PubMed

Martí, Daniel; Rigotti, Mattia; Seok, Mingoo; Fusi, Stefano

2016-10-01

Neuromorphic engineering combines the architectural and computational principles of systems neuroscience with semiconductor electronics, with the aim of building efficient and compact devices that mimic the synaptic and neural machinery of the brain. The energy consumptions promised by neuromorphic engineering are extremely low, comparable to those of the nervous system. Until now, however, the neuromorphic approach has been restricted to relatively simple circuits and specialized functions, thereby obfuscating a direct comparison of their energy consumption to that used by conventional von Neumann digital machines solving real-world tasks. Here we show that a recent technology developed by IBM can be leveraged to realize neuromorphic circuits that operate as classifiers of complex real-world stimuli. Specifically, we provide a set of general prescriptions to enable the practical implementation of neural architectures that compete with state-of-the-art classifiers. We also show that the energy consumption of these architectures, realized on the IBM chip, is typically two or more orders of magnitude lower than that of conventional digital machines implementing classifiers with comparable performance. Moreover, the spike-based dynamics display a trade-off between integration time and accuracy, which naturally translates into algorithms that can be flexibly deployed for either fast and approximate classifications, or more accurate classifications at the mere expense of longer running times and higher energy costs. This work finally proves that the neuromorphic approach can be efficiently used in real-world applications and has significant advantages over conventional digital devices when energy consumption is considered.

Investigation of noise insensitive electronic circuits for automotive applications with particular regard to MOS circuits

NASA Astrophysics Data System (ADS)

Gorille, I.

1980-11-01

The application of MOS switching circuits of high complexity in essential automobile systems, such as ignition and injection, was investigated. A bipolar circuit technology, current hogging logic (CHL), was compared to MOS technologies for its competitiveness. The functional requirements of digital automotive systems can only be met by technologies allowing large packing densities and medium speeds. The properties of n-MOS and CMOS are promising whereas the electrical power needed by p-MOS circuits is in general prohibitively large.

47 CFR 15.103 - Exempted devices.

Code of Federal Regulations, 2011 CFR

2011-10-01

... exclusively as an electronic control or power system utilized by a public utility or in an industrial plant... circuit to convert the signal to the format required (e.g., an integrated circuit for analog to digital...

47 CFR 15.103 - Exempted devices.

Code of Federal Regulations, 2010 CFR

2010-10-01

... exclusively as an electronic control or power system utilized by a public utility or in an industrial plant... circuit to convert the signal to the format required (e.g., an integrated circuit for analog to digital...

47 CFR 15.103 - Exempted devices.

Code of Federal Regulations, 2013 CFR

2013-10-01

... exclusively as an electronic control or power system utilized by a public utility or in an industrial plant... circuit to convert the signal to the format required (e.g., an integrated circuit for analog to digital...

47 CFR 15.103 - Exempted devices.

Code of Federal Regulations, 2014 CFR

2014-10-01

... exclusively as an electronic control or power system utilized by a public utility or in an industrial plant... circuit to convert the signal to the format required (e.g., an integrated circuit for analog to digital...

47 CFR 15.103 - Exempted devices.

Code of Federal Regulations, 2012 CFR

2012-10-01

... exclusively as an electronic control or power system utilized by a public utility or in an industrial plant... circuit to convert the signal to the format required (e.g., an integrated circuit for analog to digital...

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

NASA Technical Reports Server (NTRS)

Athale, R. A.; Lee, S. H.

1978-01-01

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

VLSI Design Tools, Reference Manual, Release 2.0.

DTIC Science & Technology

1984-08-01

eder. 2.3 ITACV: Libary ofC readne. far oesumdg a layoit 1-,, tiling. V ~2.4 "QUILT: CeinS"Wbesa-i-M-8euar ray f atwok til 2.5 "TIL: Tockmeleff...8217patterns package was added so that complex and repetitive digital waveforms could be generated far more easily. The recently written program MTP (Multiple...circuit model to estimate timing delays through digital circuits. It also has a mode that allows it to be used as a switch (gate) level simulator

Graphical approach for multiple values logic minimization

NASA Astrophysics Data System (ADS)

Awwal, Abdul Ahad S.; Iftekharuddin, Khan M.

1999-03-01

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

Packet Controller For Wireless Headset

NASA Technical Reports Server (NTRS)

Christensen, Kurt K.; Swanson, Richard J.

1993-01-01

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1991-02-01

circuit depth and in circuit breadth. It appears, from initial studies by PhD students Gupta and Majidi using the newly modified tools, that a few irregular...Gupta, which is based on an earlier tool developed by Majidi . The tool allows logic gates to have fan-ins and fan-outs that vary, and allows circuits

Superconductive Microwave Single-Flux-Quantum Digital Circuits and Corresponding Opto-Electronic Interfaces: On-Going Studies and First Experimental Results

DTIC Science & Technology

2005-07-13

UHLMANN University of Technology Ilmenau– PO Box 105565 – D-98684 Ilmenau - Germany RESUME : Les circuits numériques supraconducteurs micro-ondes...circuits RSFQ. Ce banc de mesure comporte deux types d’interfaces opto-RSFQ, basées sur des matériaux semiconducteurs et supraconducteurs , respectivement

Performance of In-Pixel Circuits for Photon Counting Arrays (PCAs) Based on Polycrystalline Silicon TFTs

PubMed Central

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A.; Lu, Jeng Ping

2017-01-01

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si) — a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance — information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% FWHM at 70 keV; and the digital components should work well even in the presence of significant TFT variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm. PMID:26878107

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs.

PubMed

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-03-07

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)-a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance-information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm.

High-resolution mapping of bifurcations in nonlinear biochemical circuits

NASA Astrophysics Data System (ADS)

Genot, A. J.; Baccouche, A.; Sieskind, R.; Aubert-Kato, N.; Bredeche, N.; Bartolo, J. F.; Taly, V.; Fujii, T.; Rondelez, Y.

2016-08-01

Analog molecular circuits can exploit the nonlinear nature of biochemical reaction networks to compute low-precision outputs with fewer resources than digital circuits. This analog computation is similar to that employed by gene-regulation networks. Although digital systems have a tractable link between structure and function, the nonlinear and continuous nature of analog circuits yields an intricate functional landscape, which makes their design counter-intuitive, their characterization laborious and their analysis delicate. Here, using droplet-based microfluidics, we map with high resolution and dimensionality the bifurcation diagrams of two synthetic, out-of-equilibrium and nonlinear programs: a bistable DNA switch and a predator-prey DNA oscillator. The diagrams delineate where function is optimal, dynamics bifurcates and models fail. Inverse problem solving on these large-scale data sets indicates interference from enzymatic coupling. Additionally, data mining exposes the presence of rare, stochastically bursting oscillators near deterministic bifurcations.

Development of a digital solar simulator based on full-bridge converter

NASA Astrophysics Data System (ADS)

Liu, Chen; Feng, Jian; Liu, Zhilong; Tong, Weichao; Ji, Yibo

2014-02-01

With the development of solar photovoltaic, distribution schemes utilized in power grid had been commonly application, and photovoltaic (PV) inverter is an essential equipment in grid. In this paper, a digital solar simulator based on full-bridge structure is presented. The output characteristic curve of system is electrically similar to silicon solar cells, which can greatly simplify research methods of PV inverter, improve the efficiency of research and development. The proposed simulator consists on a main control board based on TM320F28335, phase-shifted zero-voltage-switching (ZVS) DC-DC full-bridge converter and voltage and current sampling circuit, that allows emulating the voltage-current curve with the open-circuit voltage (Voc) of 900V and the short-circuit current (Isc) of 18A .When the system connected to a PV inverter, the inverter can quickly track from the open-circuit to the maximum power point and keep stability.

Synthesizing genetic sequential logic circuit with clock pulse generator.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang

2014-05-28

Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

Optimization of digital designs

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor)

2009-01-01

An application specific integrated circuit is optimized by translating a first representation of its digital design to a second representation. The second representation includes multiple syntactic expressions that admit a representation of a higher-order function of base Boolean values. The syntactic expressions are manipulated to form a third representation of the digital design.

Fundamentals of Digital Logic.

ERIC Educational Resources Information Center

Noell, Monica L.

This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Analog synthetic biology.

PubMed

Sarpeshkar, R

2014-03-28

We analyse the pros and cons of analog versus digital computation in living cells. Our analysis is based on fundamental laws of noise in gene and protein expression, which set limits on the energy, time, space, molecular count and part-count resources needed to compute at a given level of precision. We conclude that analog computation is significantly more efficient in its use of resources than deterministic digital computation even at relatively high levels of precision in the cell. Based on this analysis, we conclude that synthetic biology must use analog, collective analog, probabilistic and hybrid analog-digital computational approaches; otherwise, even relatively simple synthetic computations in cells such as addition will exceed energy and molecular-count budgets. We present schematics for efficiently representing analog DNA-protein computation in cells. Analog electronic flow in subthreshold transistors and analog molecular flux in chemical reactions obey Boltzmann exponential laws of thermodynamics and are described by astoundingly similar logarithmic electrochemical potentials. Therefore, cytomorphic circuits can help to map circuit designs between electronic and biochemical domains. We review recent work that uses positive-feedback linearization circuits to architect wide-dynamic-range logarithmic analog computation in Escherichia coli using three transcription factors, nearly two orders of magnitude more efficient in parts than prior digital implementations.

Analog synthetic biology

PubMed Central

Sarpeshkar, R.

2014-01-01

We analyse the pros and cons of analog versus digital computation in living cells. Our analysis is based on fundamental laws of noise in gene and protein expression, which set limits on the energy, time, space, molecular count and part-count resources needed to compute at a given level of precision. We conclude that analog computation is significantly more efficient in its use of resources than deterministic digital computation even at relatively high levels of precision in the cell. Based on this analysis, we conclude that synthetic biology must use analog, collective analog, probabilistic and hybrid analog–digital computational approaches; otherwise, even relatively simple synthetic computations in cells such as addition will exceed energy and molecular-count budgets. We present schematics for efficiently representing analog DNA–protein computation in cells. Analog electronic flow in subthreshold transistors and analog molecular flux in chemical reactions obey Boltzmann exponential laws of thermodynamics and are described by astoundingly similar logarithmic electrochemical potentials. Therefore, cytomorphic circuits can help to map circuit designs between electronic and biochemical domains. We review recent work that uses positive-feedback linearization circuits to architect wide-dynamic-range logarithmic analog computation in Escherichia coli using three transcription factors, nearly two orders of magnitude more efficient in parts than prior digital implementations. PMID:24567476

[Digital acoustic burglar alarm system using infrared radio remote control].

PubMed

Wang, Song-De; Zhao, Yan; Yao, Li-Ping; Zhang, Shuan-Ji

2009-03-01

Using butt emission infrared sensors, radio receiving and sending modules, double function integrated circuit with code and code translation, LED etc, a digital acoustic burglar alarm system using infrared radio to realize remote control was designed. It uses infrared ray invisible to eyes, composing area of radio distance. Once people and objects shelter the infrared ray, a testing signal will be output by the tester, and the sender will be triggered to work. The radio coding signal that sender sent is received by the receiver, then processed by a serial circuit. The control signal is output to trigger the sounder to give out an alarm signal, and the operator will be cued to notice this variation. At the same time, the digital display will be lighted and the alarm place will be watched. Digital coding technology is used, and a number of sub alarm circuits can joint the main receiver, so a lot of places can be monitored. The whole system features a module structure, with the property of easy alignment, stable operation, debug free and so on. The system offers an alarm range reaching 1 000 meters in all directions, and can be widely used in family, shop, storehouse, orchard and so on.

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

NASA Astrophysics Data System (ADS)

Balali, Moslem; Rezai, Abdalhossein

2018-07-01

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

NASA Astrophysics Data System (ADS)

Balali, Moslem; Rezai, Abdalhossein

2018-03-01

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.

HYMOSS signal processing for pushbroom spectral imaging

NASA Technical Reports Server (NTRS)

Ludwig, David E.

1991-01-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

HYMOSS signal processing for pushbroom spectral imaging

NASA Astrophysics Data System (ADS)

Ludwig, David E.

1991-06-01

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

Method and apparatus for transfer function simulator for testing complex systems

NASA Technical Reports Server (NTRS)

Kavaya, M. J. (Inventor)

1985-01-01

A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.

Advanced 3-V semiconductor technology assessment

NASA Technical Reports Server (NTRS)

Nowogrodzki, M.

1983-01-01

Components required for extensions of currently planned space communications systems are discussed for large antennas, crosslink systems, single sideband systems, Aerostat systems, and digital signal processing. Systems using advanced modulation concepts and new concepts in communications satellites are included. The current status and trends in materials technology are examined with emphasis on bulk growth of semi-insulating GaAs and InP, epitaxial growth, and ion implantation. Microwave solid state discrete active devices, multigigabit rate GaAs digital integrated circuits, microwave integrated circuits, and the exploratory development of GaInAs devices, heterojunction devices, and quasi-ballistic devices is considered. Competing technologies such as RF power generation, filter structures, and microwave circuit fabrication are discussed. The fundamental limits of semiconductor devices and problems in implementation are explored.

100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing

NASA Astrophysics Data System (ADS)

Scheytt, J. Christoph; Javed, Abdul Rehman; Bammidi, Eswara Rao; KrishneGowda, Karthik; Kallfass, Ingmar; Kraemer, Rolf

2017-09-01

In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.

Apparatus for Teaching Physics

ERIC Educational Resources Information Center

Gottlieb, Herbert H., Ed.

1977-01-01

Describes an electronic digital counter, a speed-of-light experiment using a television, a simple out-of-circuit method for determining if a transistor is made of silicon or germanium, and the use of dry cells to power TTL integrated circuits. (MLH)

The research of digital circuit system for high accuracy CCD of portable Raman spectrometer

NASA Astrophysics Data System (ADS)

Yin, Yu; Cui, Yongsheng; Zhang, Xiuda; Yan, Huimin

2013-08-01

The Raman spectrum technology is widely used for it can identify various types of molecular structure and material. The portable Raman spectrometer has become a hot direction of the spectrometer development nowadays for its convenience in handheld operation and real-time detection which is superior to traditional Raman spectrometer with heavy weight and bulky size. But there is still a gap for its measurement sensitivity between portable and traditional devices. However, portable Raman Spectrometer with Shell-Isolated Nanoparticle-Enhanced Raman Spectroscopy (SHINERS) technology can enhance the Raman signal significantly by several orders of magnitude, giving consideration in both measurement sensitivity and mobility. This paper proposed a design and implementation of driver and digital circuit for high accuracy CCD sensor, which is core part of portable spectrometer. The main target of the whole design is to reduce the dark current generation rate and increase signal sensitivity during the long integration time, and in the weak signal environment. In this case, we use back-thinned CCD image sensor from Hamamatsu Corporation with high sensitivity, low noise and large dynamic range. In order to maximize this CCD sensor's performance and minimize the whole size of the device simultaneously to achieve the project indicators, we delicately designed a peripheral circuit for the CCD sensor. The design is mainly composed with multi-voltage circuit, sequential generation circuit, driving circuit and A/D transition parts. As the most important power supply circuit, the multi-voltage circuits with 12 independent voltages are designed with reference power supply IC and set to specified voltage value by the amplifier making up the low-pass filter, which allows the user to obtain a highly stable and accurate voltage with low noise. What's more, to make our design easy to debug, CPLD is selected to generate sequential signal. The A/D converter chip consists of a correlated double sampler; a digitally controlled variable gain amplifier and a 16-bit A/D converter which can help improve the data quality. And the acquired digital signals are transmitted into the computer via USB 2.0 data port. Our spectrometer with SHINERS technology can acquire the Raman spectrum signals efficiently in long time integration and weak signal environment, and the size of our system is well controlled for portable application.

Learning and optimization with cascaded VLSI neural network building-block chips

NASA Technical Reports Server (NTRS)

Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

1992-01-01

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

NASA Technical Reports Server (NTRS)

Kaplan, Steven B.; Pylov, Sergey V.; Pambianchi, Michael

2003-01-01

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Bistability in a complementary metal oxide semiconductor inverter circuit.

PubMed

Carroll, Thomas L

2005-09-01

Radiofrequency signals can disrupt the operation of low frequency circuits. A digital inverter circuit would seem to be immune to such disruption, because its output state usually jumps abruptly between 0 and 5 V. Nevertheless, when driven with a high frequency signal, the inverter can have two coexisting stable states (which are not at 0 and 5 V). Slow switching between these states (by changing the rf signal) will produce a low frequency signal. I demonstrate the bistability in a circuit experiment and in a simple model of the circuit.

Low-noise pulse conditioner

DOEpatents

Bird, David A.

1983-01-01

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits.

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

High-Accuracy, Compact Scanning Method and Circuit for Resistive Sensor Arrays.

PubMed

Kim, Jong-Seok; Kwon, Dae-Yong; Choi, Byong-Deok

2016-01-26

The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart.

Energy and Timing Measurement with Time-Based Detector Readout for PET Applications: Principle and Validation with Discrete Circuit Components

PubMed Central

Sun, Xishan; Lan, Allan K.; Bircher, Chad; Deng, Zhi; Liu, Yinong; Shao, Yiping

2011-01-01

A new signal processing method for PET application has been developed, with discrete circuit components to measure energy and timing of a gamma interaction based solely on digital timing processing without using an amplitude-to-digital convertor (ADC) or a constant fraction discriminator (CFD). A single channel discrete component time-based readout (TBR) circuit was implemented in a PC board. Initial circuit functionality and performance evaluations have been conducted. Accuracy and linearity of signal amplitude measurement were excellent, as measured with test pulses. The measured timing accuracy from test pulses reached to less than 300 ps, a value limited mainly by the timing jitter of the prototype electronics circuit. Both suitable energy and coincidence timing resolutions (~18% and ~1.0 ns) have been achieved with 3 × 3 × 20 mm3 LYSO scintillator and photomultiplier tube-based detectors. With its relatively simple circuit and low cost, TBR is expected to be a suitable front-end signal readout electronics for compact PET or other radiation detectors requiring the reading of a large number of detector channels and demanding high performance for energy and timing measurement. PMID:21743761

Utilizing the Digital Fingerprint Methodology for Secure Key Generation

DTIC Science & Technology

2010-03-01

circuits. 2.2.2. Arbiter PUF 2.2.1 Arbiter PUF Description Figure 3 represents the arbiter PUF circuitry designed by Suh and Devadas [4]. The D latch...Reliability The results of Suh and Devadas ‟s experiments on the arbiter PUF circuit showed that when the arbiter circuit output was measured for the...and Devada pointed out that this low percentage was the result of not laying out their circuit symmetrically as it appears in the idealized

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

NASA Technical Reports Server (NTRS)

Eldin, A. G.

1991-01-01

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices

PubMed Central

Gokmen, Tayfun; Onen, Murat; Haensch, Wilfried

2017-01-01

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm. We find that the noise and bound limitations imposed by the analog nature of the computations performed on the arrays significantly affect the training accuracy of the CNNs. Noise and bound management techniques are presented that mitigate these problems without introducing any additional complexity in the analog circuits and that can be addressed by the digital circuits. In addition, we discuss digitally programmable update management and device variability reduction techniques that can be used selectively for some of the layers in a CNN. We show that a combination of all those techniques enables a successful application of the RPU concept for training CNNs. The techniques discussed here are more general and can be applied beyond CNN architectures and therefore enables applicability of the RPU approach to a large class of neural network architectures. PMID:29066942

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices.

PubMed

Gokmen, Tayfun; Onen, Murat; Haensch, Wilfried

2017-01-01

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm. We find that the noise and bound limitations imposed by the analog nature of the computations performed on the arrays significantly affect the training accuracy of the CNNs. Noise and bound management techniques are presented that mitigate these problems without introducing any additional complexity in the analog circuits and that can be addressed by the digital circuits. In addition, we discuss digitally programmable update management and device variability reduction techniques that can be used selectively for some of the layers in a CNN. We show that a combination of all those techniques enables a successful application of the RPU concept for training CNNs. The techniques discussed here are more general and can be applied beyond CNN architectures and therefore enables applicability of the RPU approach to a large class of neural network architectures.

System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

NASA Technical Reports Server (NTRS)

Windyka, John A.; Zablocki, Ed G.

1997-01-01

This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

TECHNICAL DESIGN NOTE: Picosecond resolution programmable delay line

NASA Astrophysics Data System (ADS)

Suchenek, Mariusz

2009-11-01

The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.

Configurable analog-digital conversion using the neural engineering framework

PubMed Central

Mayr, Christian G.; Partzsch, Johannes; Noack, Marko; Schüffny, Rene

2014-01-01

Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF). It carries out a large fraction of the overall ADC process in the digital domain, i.e., it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic. PMID:25100933

Microsatellite Digital Magnetometer SMILE - Present State and Future Trends

NASA Astrophysics Data System (ADS)

Belyayev, Serhiy; Ivchenko, Nickolay

2010-05-01

The fluxgate magnetometers (FGM) are probably the most widespread instruments used onboard spacecrafts for both scientific and service purposes. The recent trend to decrease the weight and size of the spacecrafts requires creating as small as possible but enough sensitive FGM. A joint Swedish-Ukrainian team made the development of such a magnetometer and as the result the Small Magnetometer In Low mass Experiment (SMILE) - a digital fluxgate microsatellite magnetometer - was created [1]. Majority of electronic units of this FGM were combined in a digital integrated circuit - a Field Programmable Gate Array (FPGA). The FPGA provides full processing (determined by a digital correlation algorithm) of amplified and digitized fluxgate sensor output signals and provides both FGM output data and feedback signals. Such digital design makes the instrument very flexible, reduces power consumption and opens possibilities for customization of the operation modes. It allows miniaturizing the electronic unit and, together with the smallest in the world low noise three-component fluxgate sensor with the side dimension of 20 mm and weight about 20 grams only, the small but enough sensitive space qualified FGM is created. SMILE magnetometer was successfully flown onboard the NASA Cascades-2 sounding rocket, and is to fly in the LAPLander package onboard the ESA REXUS-8 student sounding rocket [2]. Unfortunately, such a design of electronic circuit does not allow us to realize all possibilities of the miniature sensor. The separate tests of the sensor with highest-class analog electronics showed that its noise level may be reduced to as low value as 10…15 picoTesla at 1 Hz. Also the use of volume compensation in the sensor provides high geometrical stability of the axes and improved performance compared to component compensated sensors. The measured parameters appear to be comparable or even better than these of best stationary FGM and, if realized in small enough volume and weight, such a sensitive but small FGM could be a good candidate for planned Lunar missions where the weight is the major restriction factor. This stimulated further research in the direction of the analysis and elimination of noise sources of digital design, as well as of the optimization of FGM electronic circuit structure. The description of the obtained results of the electronic unit upgrade and recent FGM model tests are given and future improvement directions are discussed. These works are partially supported by NSAU contract No. 1499. References: 1. Åke Forslund, Serhiy Belyayev, Nickolay Ivchenko, Göran Olsson, Terry Edberg and Andriy Marusenkov, Miniaturized digital fluxgate magnetometer for small spacecraft applications 2008 Meas. Sci. Technol. 19 2. T. Sundberg, N. Ivchenko, D. Borglund, P. Ahlen, M. Gustavsson, C. Jonsson, J. Juhlen, O. Neunet, J. Sandstrom, E. Sund, M. Wartelski, C. Westlund, L. Xin, Small Recoverable Payload for Deployable Sounding Rocket Experiments. ESA Special Publication SP671

Peak power ratio generator

DOEpatents

Moyer, Robert D.

1985-01-01

A peak power ratio generator is described for measuring, in combination with a conventional power meter, the peak power level of extremely narrow pulses in the gigahertz radio frequency bands. The present invention in a preferred embodiment utilizes a tunnel diode and a back diode combination in a detector circuit as the only high speed elements. The high speed tunnel diode provides a bistable signal and serves as a memory device of the input pulses for the remaining, slower components. A hybrid digital and analog loop maintains the peak power level of a reference channel at a known amount. Thus, by measuring the average power levels of the reference signal and the source signal, the peak power level of the source signal can be determined.

Peak power ratio generator

DOEpatents

Moyer, R.D.

A peak power ratio generator is described for measuring, in combination with a conventional power meter, the peak power level of extremely narrow pulses in the gigahertz radio frequency bands. The present invention in a preferred embodiment utilizes a tunnel diode and a back diode combination in a detector circuit as the only high speed elements. The high speed tunnel diode provides a bistable signal and serves as a memory device of the input pulses for the remaining, slower components. A hybrid digital and analog loop maintains the peak power level of a reference channel at a known amount. Thus, by measuring the average power levels of the reference signal and the source signal, the peak power level of the source signal can be determined.

Digital logic optimization using selection operators

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

Real-time demonstration hardware for enhanced DPCM video compression algorithm

NASA Technical Reports Server (NTRS)

Bizon, Thomas P.; Whyte, Wayne A., Jr.; Marcopoli, Vincent R.

1992-01-01

The lack of available wideband digital links as well as the complexity of implementation of bandwidth efficient digital video CODECs (encoder/decoder) has worked to keep the cost of digital television transmission too high to compete with analog methods. Terrestrial and satellite video service providers, however, are now recognizing the potential gains that digital video compression offers and are proposing to incorporate compression systems to increase the number of available program channels. NASA is similarly recognizing the benefits of and trend toward digital video compression techniques for transmission of high quality video from space and therefore, has developed a digital television bandwidth compression algorithm to process standard National Television Systems Committee (NTSC) composite color television signals. The algorithm is based on differential pulse code modulation (DPCM), but additionally utilizes a non-adaptive predictor, non-uniform quantizer and multilevel Huffman coder to reduce the data rate substantially below that achievable with straight DPCM. The non-adaptive predictor and multilevel Huffman coder combine to set this technique apart from other DPCM encoding algorithms. All processing is done on a intra-field basis to prevent motion degradation and minimize hardware complexity. Computer simulations have shown the algorithm will produce broadcast quality reconstructed video at an average transmission rate of 1.8 bits/pixel. Hardware implementation of the DPCM circuit, non-adaptive predictor and non-uniform quantizer has been completed, providing realtime demonstration of the image quality at full video rates. Video sampling/reconstruction circuits have also been constructed to accomplish the analog video processing necessary for the real-time demonstration. Performance results for the completed hardware compare favorably with simulation results. Hardware implementation of the multilevel Huffman encoder/decoder is currently under development along with implementation of a buffer control algorithm to accommodate the variable data rate output of the multilevel Huffman encoder. A video CODEC of this type could be used to compress NTSC color television signals where high quality reconstruction is desirable (e.g., Space Station video transmission, transmission direct-to-the-home via direct broadcast satellite systems or cable television distribution to system headends and direct-to-the-home).

Synthesizing genetic sequential logic circuit with clock pulse generator

PubMed Central

2014-01-01

Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Innovation Online Teaching Module Plus Digital Engineering Kit with Proteus Software through Hybrid Learning Method to Improve Student Skills

NASA Astrophysics Data System (ADS)

Kholis, Nur; Syariffuddien Zuhrie, Muhamad; Rahmadian, Reza

2018-04-01

Demands the competence (competence) needs of the industry today is a competent workforce to the field of work. However, during this lecture material Digital Engineering (Especially Digital Electronics Basics and Digital Circuit Basics) is limited to the delivery of verbal form of lectures (classical method) is dominated by the Lecturer (Teacher Centered). Though the subject of Digital Engineering requires learning tools and is required understanding of electronic circuits, digital electronics and high logic circuits so that learners can apply in the world of work. One effort to make it happen is by creating an online teaching module and educational aids (Kit) with the help of Proteus software that can improve the skills of learners. This study aims to innovate online teaching modules plus kits in Proteus-assisted digital engineering courses through hybrid learning approaches to improve the skills of learners. The process of innovation is done by considering the skills and mastery of the technology of students (students) Department of Electrical Engineering - Faculty of Engineering – Universitas Negeri Surabaya to produce quality graduates Use of online module plus Proteus software assisted kit through hybrid learning approach. In general, aims to obtain adequate results with affordable cost of investment, user friendly, attractive and interactive (easily adapted to the development of Information and Communication Technology). With the right design, implementation and operation, both in the form of software both in the form of Online Teaching Module, offline teaching module, Kit (Educational Viewer), and e-learning learning content (both online and off line), the use of the three tools of the expenditure will be able to adjust the standard needs of Information and Communication Technology world, both nationally and internationally.

A New Statistics-Based Online Baseline Restorer for a High Count-Rate Fully Digital System.

PubMed

Li, Hongdi; Wang, Chao; Baghaei, Hossain; Zhang, Yuxuan; Ramirez, Rocio; Liu, Shitao; An, Shaohui; Wong, Wai-Hoi

2010-04-01

The goal of this work is to develop a novel, accurate, real-time digital baseline restorer using online statistical processing for a high count-rate digital system such as positron emission tomography (PET). In high count-rate nuclear instrumentation applications, analog signals are DC-coupled for better performance. However, the detectors, pre-amplifiers and other front-end electronics would cause a signal baseline drift in a DC-coupling system, which will degrade the performance of energy resolution and positioning accuracy. Event pileups normally exist in a high-count rate system and the baseline drift will create errors in the event pileup-correction. Hence, a baseline restorer (BLR) is required in a high count-rate system to remove the DC drift ahead of the pileup correction. Many methods have been reported for BLR from classic analog methods to digital filter solutions. However a single channel BLR with analog method can only work under 500 kcps count-rate, and normally an analog front-end application-specific integrated circuits (ASIC) is required for the application involved hundreds BLR such as a PET camera. We have developed a simple statistics-based online baseline restorer (SOBLR) for a high count-rate fully digital system. In this method, we acquire additional samples, excluding the real gamma pulses, from the existing free-running ADC in the digital system, and perform online statistical processing to generate a baseline value. This baseline value will be subtracted from the digitized waveform to retrieve its original pulse with zero-baseline drift. This method can self-track the baseline without a micro-controller involved. The circuit consists of two digital counter/timers, one comparator, one register and one subtraction unit. Simulation shows a single channel works at 30 Mcps count-rate with pileup condition. 336 baseline restorer circuits have been implemented into 12 field-programmable-gate-arrays (FPGA) for our new fully digital PET system.

Multiple channel programmable coincidence counter

DOEpatents

Arnone, Gaetano J.

1990-01-01

A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

Digital Systems Validation Handbook. Volume 2

DTIC Science & Technology

1989-02-01

power. 2. A grid of wires, solid sheet, or foil. 3. A wire from circuit to grounding block or case. 4. A wire from circuit to structure. 5. Shield...RETURN. (11) 1. Structure, for power, fault, and "discrete" circuits. 2. A grid of wires, solid sheet, or foil. 3. A wire from circuit load back to...TV (14) Television TWTD (13) Thin Wire Time Domain TX (5) Transmit U.K. (13,141 United Kingdom U.S. (14) United States UART (15) Universal Asynchronous

Processing circuit with asymmetry corrector and convolutional encoder for digital data

NASA Technical Reports Server (NTRS)

Pfiffner, Harold J. (Inventor)

1987-01-01

A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission.

Comparison of digital controllers used in magnetic suspension and balance systems

NASA Technical Reports Server (NTRS)

Kilgore, William A.

1990-01-01

Dynamic systems that were once controlled by analog circuits are now controlled by digital computers. Presented is a comparison of the digital controllers presently used with magnetic suspension and balance systems. The overall responses of the systems are compared using a computer simulation of the magnetic suspension and balance system and the digital controllers. The comparisons include responses to both simulated force and position inputs. A preferred digital controller is determined from the simulated responses.

Design of a digital multiradian phase detector and its application in fusion plasma interferometry.

PubMed

Mlynek, A; Schramm, G; Eixenberger, H; Sips, G; McCormick, K; Zilker, M; Behler, K; Eheberg, J

2010-03-01

We discuss the circuit design of a digital multiradian phase detector that measures the phase difference between two 10 kHz square wave TTL signals and provides the result as a binary number. The phase resolution of the circuit is 1/64 period and its dynamic range is 256 periods. This circuit has been developed for fusion plasma interferometry with submillimeter waves on the ASDEX Upgrade tokamak. The results from interferometric density measurement are discussed and compared to those obtained with the previously used phase detectors, especially with respect to the occurrence of phase jumps. It is illustrated that the new phase measurement provides a powerful tool for automatic real-time validation of the measured density, which is important for feedback algorithms that are sensitive to spurious density signals.

Design of 4 to 2 line encoder using lithium niobate based Mach Zehnder Interferometers for high speed communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep; Raghuwanshi, Sanjeev K.

2016-04-01

Encoder is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using encoder and external gates. In this paper, 4 to 2 line encoder is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

Dynamic high-resolution patterning for biomedical, materials, and semiconductor research

NASA Astrophysics Data System (ADS)

Garner, Harold R.; Joshi, Amruta; Mitnala, Sandhya N.; Huebschman, Michael L.; Shandy, Surya; Wallek, Brandi; Wong, Season

2009-02-01

By combining unique light sources, a Texas Instruments DLP system and a microscope, a submicron dynamic patterning system has been created. This system has a resolution of 0.5 microns, and can illuminate with rapidly changing patterns of visible, UV or pulsed laser light. This system has been used to create digital masks for the production of micron scale electronic test circuits and has been used in biological applications. Specifically we have directed light on a sub-organelle scale to cells to control their morphology and motility with applications to tissue engineering, cell biology, drug discovery and neurology.

Noise-shaping gradient descent-based online adaptation algorithms for digital calibration of analog circuits.

PubMed

Chakrabartty, Shantanu; Shaga, Ravi K; Aono, Kenji

2013-04-01

Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.

Maximum Acceleration Recording Circuit

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Thermostatic system of sensor in NIR spectrometer based on PID control

NASA Astrophysics Data System (ADS)

Wang, Zhihong; Qiao, Liwei; Ji, Xufei

2016-11-01

Aiming at the shortcomings of the primary sensor thermostatic control system in the near infrared (NIR) spectrometer, a novel thermostatic control system based on proportional-integral-derivative (PID) control technology was developed to improve the detection precision of the NIR spectrometer. There were five parts including bridge amplifier circuit, analog-digital conversion (ADC) circuit, microcontroller, digital-analog conversion (DAC) circuit and drive circuit in the system. The five parts formed a closed-loop control system based on PID algorithm that was used to control the error between the temperature calculated by the sampling data of ADC and the designed temperature to ensure the stability of the spectrometer's sensor. The experimental results show that, when the operating temperature of sensor is -11°, compared with the original system, the temperature control precision of the new control system is improved from ±0.64° to ±0.04° and the spectrum signal to noise ratio (SNR) is improved from 4891 to 5967.

Qualitative-Modeling-Based Silicon Neurons and Their Networks

PubMed Central

Kohno, Takashi; Sekikawa, Munehisa; Li, Jing; Nanami, Takuya; Aihara, Kazuyuki

2016-01-01

The ionic conductance models of neuronal cells can finely reproduce a wide variety of complex neuronal activities. However, the complexity of these models has prompted the development of qualitative neuron models. They are described by differential equations with a reduced number of variables and their low-dimensional polynomials, which retain the core mathematical structures. Such simple models form the foundation of a bottom-up approach in computational and theoretical neuroscience. We proposed a qualitative-modeling-based approach for designing silicon neuron circuits, in which the mathematical structures in the polynomial-based qualitative models are reproduced by differential equations with silicon-native expressions. This approach can realize low-power-consuming circuits that can be configured to realize various classes of neuronal cells. In this article, our qualitative-modeling-based silicon neuron circuits for analog and digital implementations are quickly reviewed. One of our CMOS analog silicon neuron circuits can realize a variety of neuronal activities with a power consumption less than 72 nW. The square-wave bursting mode of this circuit is explained. Another circuit can realize Class I and II neuronal activities with about 3 nW. Our digital silicon neuron circuit can also realize these classes. An auto-associative memory realized on an all-to-all connected network of these silicon neurons is also reviewed, in which the neuron class plays important roles in its performance. PMID:27378842

A Compact Cosmic Ray Telescope using Silicon Photomultipliers for use in High Schools

NASA Astrophysics Data System (ADS)

Castro, Luis; Elizondo, Leonardo; Shelor, Mark; Cervantes, Omar; Fan, Sewan; Ritt, Stefan

2016-03-01

Over the years, the QuarkNet and the LBL Cosmic Ray Project have helped trained thousands of high school students and teachers to explore cosmic ray physics. To get high school students in the Salinas, CA area also excited about cosmic rays, we constructed a cosmic ray telescope as a physics outreach apparatus. Our apparatus includes a pair of plastic scintillators coupled to silicon photomultipliers (SiPM) and a coincidence circuit board. We designed and constructed custom circuit boards for mounting the SiPM detectors, the high voltage power supplies and coincidence AND circuit. The AND logic signals can be used for triggering data acquisition devices including an oscilloscope, a waveform digitizer or an Arduino microcontroller. To properly route the circuit wire traces, the circuit boards were layout in Eagle and fabricated in-house using a circuit board maker from LPKF LASER, model Protomat E33. We used a Raspberry Pi computer to control a fast waveform sampler, the DRS4 to digitize the SiPM signal waveforms. The CERN PAW software package was used to analyze the amplitude and time distributions of SiPM detector signals. At this conference, we present our SiPM experimental setup, circuit board fabrication procedures and the data analysis work flow. AIP Megger's Award, Dept. of Ed. Title V Grant PO31S090007.

Superconducting analog-to-digital converter with a triple-junction reversible flip-flop bidirectional counter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, G.S.

1993-07-13

A high-performance superconducting analog-to-digital converter is described, comprising: a bidirectional binary counter having n stages of triple-junction reversible flip-flops connected together in a cascade arrangement from the least significant bit (LSB) to the most significant bit (MSB) where n is the number of bits of the digital output, each triple-junction reversible flip-flop including first, second and third shunted Josephson tunnel junctions and a superconducting inductor connected in a bridge circuit, the Josephson junctions and the inductor forming upper and lower portions of the flip-flop, each reversible flip-flop being a bistable logic circuit in which the direction of the circulating currentmore » determines the state of the circuit; and means for applying an analog input current to the bidirectional counter; wherein the bidirectional counter algebraically counts incremental changes in the analog input current, increasing the binary count for positive incremental changes in the analog current and decreasing the binary count for negative incremental changes in the current, and wherein the counter does not require a gate bias, thus minimizing power dissipation.« less

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

Digital PCM bit synchronizer and detector

NASA Astrophysics Data System (ADS)

Moghazy, A. E.; Maral, G.; Blanchard, A.

1980-08-01

A theoretical analysis of a digital self-bit synchronizer and detector is presented and supported by the implementation of an experimental model that utilizes standard TTL logic circuits. This synchronizer is based on the generation of spectral line components by nonlinear filtering of the received bit stream, and extracting the line by a digital phase-locked loop (DPLL). The extracted reference signal instructs a digital matched filter (DMF) data detector. This realization features a short acquisition time and an all-digital structure.

Monolithic 3D CMOS Using Layered Semiconductors.

PubMed

Sachid, Angada B; Tosun, Mahmut; Desai, Sujay B; Hsu, Ching-Yi; Lien, Der-Hsien; Madhvapathy, Surabhi R; Chen, Yu-Ze; Hettick, Mark; Kang, Jeong Seuk; Zeng, Yuping; He, Jr-Hau; Chang, Edward Yi; Chueh, Yu-Lun; Javey, Ali; Hu, Chenming

2016-04-06

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

PubMed Central

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-01-01

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

High-Accuracy, Compact Scanning Method and Circuit for Resistive Sensor Arrays

PubMed Central

Kim, Jong-Seok; Kwon, Dae-Yong; Choi, Byong-Deok

2016-01-01

The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row driver. The other type is a row driver composed of operational amplifiers. It, very accurately, reads the sensor resistance, but it uses a large number of operational amplifiers to drive rows of the sensor array; therefore, it severely increases the power consumption, cost, and system complexity. To resolve the inaccuracy or high complexity problems founded in those previous circuits, we propose a new row driver which uses only one operational amplifier to drive all rows of a sensor array with high accuracy. The measurement results with the proposed circuit to drive a 4 × 4 resistor array show that the maximum error is only 0.1% which is remarkably reduced from 30.7% of the previous counterpart. PMID:26821029

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

PubMed

Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

2016-10-25

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

A Bidirectional Neural Interface IC with Chopper Stabilized BioADC Array and Charge Balanced Stimulator

PubMed Central

Greenwald, Elliot; So, Ernest; Wang, Qihong; Mollazadeh, Mohsen; Maier, Christoph; Etienne-Cummings, Ralph; Cauwenberghs, Gert; Thakor, Nitish

2016-01-01

We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order ΔΣ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5V supply, the analog and digital circuits in each recording channel draw on average 1.54 μA and 2.13 μA of supply current, respectively. The bioADCs achieve an SNR of 58 dB and a SFDR of >70 dB, for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo. Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications. PMID:27845676

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T.J.; Antonescu, C.

A program to assess the impact of smoke on digital instrumentation and control (I and C) safety systems began in 1994, funded by the US Nuclear Regulatory Commission Office of Research. Digital I and C safety systems are likely replacements for today`s analog systems. The nuclear industry has little experience in qualifying digital electronics for critical systems, part of which is understanding system performance during plant fires. The results of tests evaluating the performance of digital circuits and chip technologies exposed to the various smoke and humidity conditions representative of cable fires are discussed. Tests results show that low tomore » moderate smoke densities can cause intermittent failures of digital systems. Smoke increases leakage currents between biased contacts, leading to shorts. Chips with faster switching times, and thus higher output drive currents, are less sensitive to leakage currents and thus to smoke. Contact corrosion from acidic gases in smoke and inductance of stray capacitance are less important contributors to system upset. Transmission line coupling was increased because the smoke acted as a conductive layer between the lines. Permanent circuit damage was not obvious in the 24 hr of circuit monitoring. Test results also show that polyurethane, parylene, and acrylic conformal coatings are more effective in protecting against smoke than epoxy or silicone. Common-sense mitigation measures are discussed. Unfortunately the authors are a long way from standard tests for smoke exposure that capture the variations in smoke exposure possible in an actual fire.« less

An ADC Interface for the Apple II.

ERIC Educational Resources Information Center

Leiker, P. Steven

1990-01-01

Described is the construction of a simple analog-to-digital convertor circuit to interface an Apple II+ microcomputer to a light sensor used in conjunction with a holographic gear inspector. A list of parts, circuit diagram, and a simple BASIC program for the convertor are provided. (CW)

Assessing Design Activity in Complex CMOS Circuit Design.

ERIC Educational Resources Information Center

Biswas, Gautam; And Others

This report characterizes human problem solving in digital circuit design. Protocols of 11 different designers with varying degrees of training were analyzed by identifying the designers' problem solving strategies and discussing activity patterns that differentiate the designers. These methods are proposed as a tentative basis for assessing…

Fast Clock Recovery for Digital Communications

NASA Technical Reports Server (NTRS)

Tell, R. G.

1985-01-01

Circuit extracts clock signal from random non-return-to-zero data stream, locking onto clock within one bit period at 1-gigabitper-second data rate. Circuit used for synchronization in opticalfiber communications. Derives speed from very short response time of gallium arsenide metal/semiconductor field-effect transistors (MESFET's).

Carbon nanotube transistor based high-frequency electronics

NASA Astrophysics Data System (ADS)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks. Carbon nanotube transistor based high-frequency electronics.

Carbon nanotube transistor based high-frequency electronics

NASA Astrophysics Data System (ADS)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks.

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Radiation dosimeter

DOEpatents

Fox, Richard J.

1983-01-01

A radiation detector readout circuit is provided which produces a radiation dose-rate readout from a detector even though the detector output may be highly energy dependent. A linear charge amplifier including an output charge pump circuit amplifies the charge signal pulses from the detector and pumps the charge into a charge storage capacitor. The discharge rate of the capacitor through a resistor is controlled to provide a time-dependent voltage which when integrated provides an output proportional to the dose-rate of radiation detected by the detector. This output may be converted to digital form for readout on a digital display.

Radiation dosimeter

DOEpatents

Fox, R.J.

1981-09-01

A radiation detector readout circuit is provided which produces a radiation dose-rate readout from a detector even through the detector output may be highly energy dependent. A linear charge amplifier including an output charge pump circuit amplifies the charge signal pulses from the detector and pumps the charge into a charge storage capacitor. The discharge rate of the capacitor through a resistor is controlled to provide a time-dependent voltage which when integrated provides an output proportional to the dose-rate of radiation detected by the detector. This output may be converted to digital form for readout on a digital display.

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme

NASA Astrophysics Data System (ADS)

Shinya, A.; Ishihara, T.; Inoue, K.; Nozaki, K.; Kita, S.; Notomi, M.

2018-02-01

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors.

PubMed

Tremblay, Noah J; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E

2011-11-22

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards 'intelligent sensors' that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors

PubMed Central

Tremblay, Noah J.; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E.

2013-01-01

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards ‘intelligent sensors’ that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations. PMID:23754969

Low-noise pulse conditioner

DOEpatents

Bird, D.A.

1981-06-16

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits. This circuit may be used for conditioning the sensor signal from the Fidler coil in a gas centrifuge for separation of isotopic gaseous mixtures.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Robust motion artefact resistant circuit for calculation of Mean Arterial Pressure from pulse transit time.

PubMed

Bhattacharya, Tinish; Gupta, Ankesh; Singh, Salam ThoiThoi; Roy, Sitikantha; Prasad, Anamika

2017-07-01

Cuff-less and non-invasive methods of Blood Pressure (BP) monitoring have faced a lot of challenges like stability, noise, motion artefact and requirement for calibration. These factors are the major reasons why such devices do not get approval from the medical community easily. One such method is calculating Blood Pressure indirectly from pulse transit time (PTT) obtained from electrocardiogram (ECG) and Photoplethysmogram (PPG). In this paper we have proposed two novel analog signal conditioning circuits for ECG and PPG that increase stability, remove motion artefacts, remove the sinusoidal wavering of the ECG baseline due to respiration and provide consistent digital pulses corresponding to blood pulses/heart-beat. We have combined these two systems to obtain the PTT and then correlated it with the Mean Arterial Pressure (MAP). The aim was to perform major part of the processing in analog domain to decrease processing load over microcontroller so as to reduce cost and make it simple and robust. We have found from our experiments that the proposed circuits can calculate the Heart Rate (HR) with a maximum error of ~3.0% and MAP with a maximum error of ~2.4% at rest and ~4.6% in motion.

A low complexity, low spur digital IF conversion circuit for high-fidelity GNSS signal playback

NASA Astrophysics Data System (ADS)

Su, Fei; Ying, Rendong

2016-01-01

A low complexity high efficiency and low spur digital intermediate frequency (IF) conversion circuit is discussed in the paper. This circuit is key element in high-fidelity GNSS signal playback instrument. We analyze the spur performance of a finite state machine (FSM) based numerically controlled oscillators (NCO), by optimization of the control algorithm, a FSM based NCO with 3 quantization stage can achieves 65dB SFDR in the range of the seventh harmonic. Compare with traditional lookup table based NCO design with the same Spurious Free Dynamic Range (SFDR) performance, the logic resource require to implemented the NCO is reduced to 1/3. The proposed design method can be extended to the IF conversion system with good SFDR in the range of higher harmonic components by increasing the quantization stage.

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

NASA Astrophysics Data System (ADS)

1981-12-01

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

NASA Technical Reports Server (NTRS)

1981-01-01

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Improved Remapping Processor For Digital Imagery

NASA Technical Reports Server (NTRS)

Fisher, Timothy E.

1991-01-01

Proposed digital image processor improved version of Programmable Remapper, which performs geometric and radiometric transformations on digital images. Features include overlapping and variably sized preimages. Overcomes some of limitations of image-warping circuit boards implementing only those geometric tranformations expressible in terms of polynomials of limited order. Also overcomes limitations of existing Programmable Remapper and made to perform transformations at video rate.

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

NASA Astrophysics Data System (ADS)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators

NASA Astrophysics Data System (ADS)

Yuan, Zeshi; Li, Hongtao; Miao, Yunchi; Hu, Wen; Zhu, Xiaohua

2017-12-01

Practical random number generation (RNG) circuits are typically achieved with analog devices or digital approaches. Digital-based techniques, which use field programmable gate array (FPGA) and graphics processing units (GPU) etc. usually have better performances than analog methods as they are programmable, efficient and robust. However, digital realizations suffer from the effect of finite precision. Accordingly, the generated random numbers (RNs) are actually periodic instead of being real random. To tackle this limitation, in this paper we propose a novel digital-analog hybrid scheme that employs the digital unit as the main body, and minimum analog devices to generate physical RNs. Moreover, the possibility of realizing the proposed scheme with only one memory element is discussed. Without loss of generality, we use the capacitor and the memristor along with FPGA to construct the proposed hybrid system, and a chaotic true random number generator (TRNG) circuit is realized, producing physical RNs at a throughput of Gbit/s scale. These RNs successfully pass all the tests in the NIST SP800-22 package, confirming the significance of the scheme in practical applications. In addition, the use of this new scheme is not restricted to RNGs, and it also provides a strategy to solve the effect of finite precision in other digital systems.

Space shuttle main engine controller assembly, phase C-D. [with lagging system design and analysis

NASA Technical Reports Server (NTRS)

1973-01-01

System design and system analysis and simulation are slightly behind schedule, while design verification testing has improved. Input/output circuit design has improved, but digital computer unit (DCU) and mechanical design continue to lag. Part procurement was impacted by delays in printed circuit board, assembly drawing releases. These are the result of problems in generating suitable printed circuit artwork for the very complex and high density multilayer boards.

CMOS output buffer wave shaper

NASA Technical Reports Server (NTRS)

Albertson, L.; Whitaker, S.; Merrell, R.

1990-01-01

As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

Circuit For Control Of Electromechanical Prosthetic Hand

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Proposed circuit for control of electromechanical prosthetic hand derives electrical control signals from shoulder movements. Updated, electronic version of prosthesis, that includes two hooklike fingers actuated via cables from shoulder harness. Circuit built around favored shoulder harness, provides more dexterous movement, without incurring complexity of computer-controlled "bionic" or hydraulically actuated devices. Additional harness and potentiometer connected to similar control circuit mounted on other shoulder. Used to control stepping motor rotating hand about prosthetic wrist to one of number of angles consistent with number of digital outputs. Finger-control signals developed by circuit connected to first shoulder harness transmitted to prosthetic hand via sliprings at prosthetic wrist joint.

Functional test generation for digital circuits described with a declarative language: LUSTRE

NASA Astrophysics Data System (ADS)

Almahrous, Mazen

1990-08-01

A functional approach to the test generation problem starting from a high level description is proposed. The circuit tested is modeled, using the LUSTRE high level data flow description language. The different LUSTRE primitives are translated to a SATAN format graph in order to evaluate the testability of the circuit and to generate test sequences. Another method of testing the complex circuits comprising an operative part and a control part is defined. It consists of checking experiments for the control part observed through the operative part. It was applied to the automata generated from a LUSTRE description of the circuit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hopwood, J.E.; Affeldt, B.

An IBM personal computer (PC), a Gerber coordinate digitizer, and a collection of other instruments make up a system known as the Coordinate Digitizer Interactive Processor (CDIP). The PC extracts coordinate data from the digitizer through a special interface, and then, after reformatting, transmits the data to a remote VAX computer, a floppy disk, and a display terminal. This system has improved the efficiency of producing printed circuit-board artwork and extended the useful life of the Gerber GCD-1 Digitizer. 1 ref., 12 figs.

Army Medical Imaging System - ARMIS

DTIC Science & Technology

1992-08-08

modems , scanners, hard disk drives, dot matrix printers, erasable-optical disc drives, CD-ROM drives, WORM disc drives and tape drives are fully...can use 56K leased lines, TI links, digital data circuits, or public telephone lines. 3. ISDN The Integrated Services Digital Network, ISDN, is a

Efficient high-performance ultrasound beamforming using oversampling

NASA Astrophysics Data System (ADS)

Freeman, Steven R.; Quick, Marshall K.; Morin, Marc A.; Anderson, R. C.; Desilets, Charles S.; Linnenbrink, Thomas E.; O'Donnell, Matthew

1998-05-01

High-performance and efficient beamforming circuitry is very important in large channel count clinical ultrasound systems. Current state-of-the-art digital systems using multi-bit analog to digital converters (A/Ds) have matured to provide exquisite image quality with moderate levels of integration. A simplified oversampling beamforming architecture has been proposed that may a low integration of delta-sigma A/Ds onto the same chip as digital delay and processing circuitry to form a monolithic ultrasound beamformer. Such a beamformer may enable low-power handheld scanners for high-end systems with very large channel count arrays. This paper presents an oversampling beamformer architecture that generates high-quality images using very simple; digitization, delay, and summing circuits. Additional performance may be obtained with this oversampled system for narrow bandwidth excitations by mixing the RF signal down in frequency to a range where the electronic signal to nose ratio of the delta-sigma A/D is optimized. An oversampled transmit beamformer uses the same delay circuits as receive and eliminates the need for separate transmit function generators.

Noise isolation system for high-speed circuits

DOEpatents

McNeilly, D.R.

1983-12-29

A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

Noise isolation system for high-speed circuits

DOEpatents

McNeilly, David R.

1986-01-01

A noise isolation circuit is provided that consists of a dual function bypass which confines high-speed switching noise to the component or circuit which generates it and isolates the component or circuit from high-frequency noise transients which may be present on the ground and power supply busses. A local circuit ground is provided which is coupled to the system ground by sufficient impedance to force the dissipation of the noise signal in the local circuit or component generating the noise. The dual function bypass network couples high-frequency noise signals generated in the local component or circuit through a capacitor to the local ground while isolating the component or circuit from noise signals which may be present on the power supply busses or system ground. The network is an effective noise isolating system and is applicable to both high-speed analog and digital circuits.

Robustness to Faults Promotes Evolvability: Insights from Evolving Digital Circuits

PubMed Central

Nolfi, Stefano

2016-01-01

We demonstrate how the need to cope with operational faults enables evolving circuits to find more fit solutions. The analysis of the results obtained in different experimental conditions indicates that, in absence of faults, evolution tends to select circuits that are small and have low phenotypic variability and evolvability. The need to face operation faults, instead, drives evolution toward the selection of larger circuits that are truly robust with respect to genetic variations and that have a greater level of phenotypic variability and evolvability. Overall our results indicate that the need to cope with operation faults leads to the selection of circuits that have a greater probability to generate better circuits as a result of genetic variation with respect to a control condition in which circuits are not subjected to faults. PMID:27409589

Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

NASA Technical Reports Server (NTRS)

Jamot, Robert F.; Monroe, Ryan M.

2012-01-01

With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Signal processing: opportunities for superconductive circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ralston, R.W.

1985-03-01

Prime motivators in the evolution of increasingly sophisticated communication and detection systems are the needs for handling ever wider signal bandwidths and higher data-processing speeds. These same needs drive the development of electronic device technology. Until recently the superconductive community has been tightly focused on digital devices for high speed computers. The purpose of this paper is to describe opportunities and challenges which exist for both analog and digital devices in a less familiar area, that of wideband signal processing. The function and purpose of analog signal-processing components, including matched filters, correlators and Fourier transformers, will be described and examplesmore » of superconductive implementations given. A canonic signal-processing system is then configured using these components and digital output circuits to highlight the important issues of dynamic range, accuracy and equivalent computation rate. (Reprints)« less

OPTICAL correlation identification technology applied in underwater laser imaging target identification

NASA Astrophysics Data System (ADS)

Yao, Guang-tao; Zhang, Xiao-hui; Ge, Wei-long

2012-01-01

The underwater laser imaging detection is an effective method of detecting short distance target underwater as an important complement of sonar detection. With the development of underwater laser imaging technology and underwater vehicle technology, the underwater automatic target identification has gotten more and more attention, and is a research difficulty in the area of underwater optical imaging information processing. Today, underwater automatic target identification based on optical imaging is usually realized with the method of digital circuit software programming. The algorithm realization and control of this method is very flexible. However, the optical imaging information is 2D image even 3D image, the amount of imaging processing information is abundant, so the electronic hardware with pure digital algorithm will need long identification time and is hard to meet the demands of real-time identification. If adopt computer parallel processing, the identification speed can be improved, but it will increase complexity, size and power consumption. This paper attempts to apply optical correlation identification technology to realize underwater automatic target identification. The optics correlation identification technology utilizes the Fourier transform characteristic of Fourier lens which can accomplish Fourier transform of image information in the level of nanosecond, and optical space interconnection calculation has the features of parallel, high speed, large capacity and high resolution, combines the flexibility of calculation and control of digital circuit method to realize optoelectronic hybrid identification mode. We reduce theoretical formulation of correlation identification and analyze the principle of optical correlation identification, and write MATLAB simulation program. We adopt single frame image obtained in underwater range gating laser imaging to identify, and through identifying and locating the different positions of target, we can improve the speed and orientation efficiency of target identification effectively, and validate the feasibility of this method primarily.

A comparison of hardware description languages. [describing digital systems structure and behavior to a computer

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1978-01-01

Several high level languages which evolved over the past few years for describing and simulating the structure and behavior of digital systems, on digital computers are assessed. The characteristics of the four prominent languages (CDL, DDL, AHPL, ISP) are summarized. A criterion for selecting a suitable hardware description language for use in an automatic integrated circuit design environment is provided.

Northeast Artificial Intelligence Consortium (NAIC) Review of Technical Tasks. Volume 2, Part 1.

DTIC Science & Technology

1987-07-01

34- . 6.2 Transformation Invariant Attributes for S Digitized Object Outlines ................................. 469 6.3 Design of an Inference Engine for an...Attributes for Digital Object Outlines ...................................... 597 7 SPEECH UNDERSTANDING RESEARCH ( Rochester Institute of Technology...versatile maintenance expert system ES) for trouble-shooting--’ digital circuits. +" Some diagnosis systems, such as MYCLN [19] for medical diagnosis and CRIB

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

NASA Technical Reports Server (NTRS)

Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

2009-01-01

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

Direct Digital Boiler Control Systems for the Navy Small Boiler Equipment.

DTIC Science & Technology

1983-02-01

Hardware. Each full-size ACU a 6 caculation modules 30 arrme, modufes sation for dead time lag contains input/output circuit a 16 control mo uies a...along with lather modules of the DCS-1000 family. ’The complete instrument consists of plug-in circuit boards that allow easy Teplacement of a...Maintenance-Most systems indicate trouble areas with diagnostic routines or integral LED indicators so that circuit boards can be replaced to correct

Heterojunction bipolar transistor technology for data acquisition and communication

NASA Technical Reports Server (NTRS)

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Data acquisition channel apparatus

NASA Astrophysics Data System (ADS)

Higgins, C. H.; Skipper, J. D.

1985-10-01

Dicussed is a hybrid integrated circuit data acquisition channel apparatus employing an operational amplifier fed by a low current differential bipolar transistor preamplifier having separate feedback gain and signal gain determining elements and providing an amplified signal output to a sample and hold and analog-to-digital converter circuits. The disclosed apparatus operates with low energy and small space requirements and is capable of operations without the sample and hold circuit where the nature of the applied input signal permits.

A system for automatic analysis of blood pressure data for digital computer entry

NASA Technical Reports Server (NTRS)

Miller, R. L.

1972-01-01

Operation of automatic blood pressure data system is described. Analog blood pressure signal is analyzed by three separate circuits, systolic, diastolic, and cycle defect. Digital computer output is displayed on teletype paper tape punch and video screen. Illustration of system is included.

Digital design using selection operations

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor); Cameron, Eric G. (Inventor)

2004-01-01

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

On-chip enzymatic microbiofuel cell-powered integrated circuits.

PubMed

Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

2017-05-16

A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems.

PubMed

Sheng, Duo; Lai, Hsiu-Fan; Chan, Sheng-Min; Hong, Min-Rong

2015-02-13

An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascade-stage delay measurement circuit can enhance immunity to supply-voltage variations of the delay measurement resolution without extra self-biasing or calibration circuits. Simulation results show that the delay measurement resolution can be improved to 1.2 ps; the average delay resolution variation is 0.55% with supply-voltage variations of ±10%. Moreover, the proposed delay sensor can be implemented in an all-digital manner, making it very suitable for high-performance electronic system applications as well as system-level integration.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Controlling suspended samplers by programmable calculator and interface circuitry

Treesearch

Rand E. Eads; Mark R. Boolootian

1985-01-01

A programmable calculator connected to an interface circuit can control automatic samplers and record streamflow data. The circuit converts a voltage representing water stage to a digital signal. The sampling program logs streamflow data when there is a predefined deviation from a linear trend in the water elevation. The calculator estimates suspended sediment...

Controlling suspended sediment samplers by programmable calculator and interface circuitry

Treesearch

Rand E. Eads; Mark R. Boolootian

1985-01-01

A programmable calculator connected to an interface circuit can control automatic samplers and record streamflow data. The circuit converts a voltage representing water stage to a digital signal. The sampling program logs streamflow data when there is a predefined deviation from a linear trend in the water elevation. The calculator estimates suspended sediment...

Circuit For Current-vs.-Voltage Tests Of Semiconductors

NASA Technical Reports Server (NTRS)

Huston, Steven W.

1991-01-01

Circuit designed for measurement of dc current-versus-voltage characteristics of semiconductor devices. Operates in conjunction with x-y pen plotter or digital storage oscilloscope, which records data. Includes large feedback resistors to prevent high currents damaging device under test. Principal virtues: low cost, simplicity, and compactness. Also used to evaluate diodes and transistors.

Automatic sweep circuit

DOEpatents

Keefe, Donald J.

1980-01-01

An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

Easy-to-Implement Project Integrates Basic Electronics and Computer Programming

ERIC Educational Resources Information Center

Johnson, Richard; Shackelford, Ray

2008-01-01

The activities described in this article give students excellent experience with both computer programming and basic electronics. During the activities, students will work in small groups, using a BASIC Stamp development board to fabricate digital circuits and PBASIC to write program code that will control the circuits they have built. The…

A low-cost, scalable, current-sensing digital headstage for high channel count μECoG.

PubMed

Trumpis, Michael; Insanally, Michele; Zou, Jialin; Elsharif, Ashraf; Ghomashchi, Ali; Sertac Artan, N; Froemke, Robert C; Viventi, Jonathan

2017-04-01

High channel count electrode arrays allow for the monitoring of large-scale neural activity at high spatial resolution. Implantable arrays featuring many recording sites require compact, high bandwidth front-end electronics. In the present study, we investigated the use of a small, light weight, and low cost digital current-sensing integrated circuit for acquiring cortical surface signals from a 61-channel micro-electrocorticographic (μECoG) array. We recorded both acute and chronic μECoG signal from rat auditory cortex using our novel digital current-sensing headstage. For direct comparison, separate recordings were made in the same anesthetized preparations using an analog voltage headstage. A model of electrode impedance explained the transformation between current- and voltage-sensed signals, and was used to reconstruct cortical potential. We evaluated the digital headstage using several metrics of the baseline and response signals. The digital current headstage recorded neural signal with similar spatiotemporal statistics and auditory frequency tuning compared to the voltage signal. The signal-to-noise ratio of auditory evoked responses (AERs) was significantly stronger in the current signal. Stimulus decoding based on true and reconstructed voltage signals were not significantly different. Recordings from an implanted system showed AERs that were detectable and decodable for 52 d. The reconstruction filter mitigated the thermal current noise of the electrode impedance and enhanced overall SNR. We developed and validated a novel approach to headstage acquisition that used current-input circuits to independently digitize 61 channels of μECoG measurements of the cortical field. These low-cost circuits, intended to measure photo-currents in digital imaging, not only provided a signal representing the local cortical field with virtually the same sensitivity and specificity as a traditional voltage headstage but also resulted in a small, light headstage that can easily be scaled to record from hundreds of channels.

A low-cost, scalable, current-sensing digital headstage for high channel count μECoG

NASA Astrophysics Data System (ADS)

Trumpis, Michael; Insanally, Michele; Zou, Jialin; Elsharif, Ashraf; Ghomashchi, Ali; Sertac Artan, N.; Froemke, Robert C.; Viventi, Jonathan

2017-04-01

Objective. High channel count electrode arrays allow for the monitoring of large-scale neural activity at high spatial resolution. Implantable arrays featuring many recording sites require compact, high bandwidth front-end electronics. In the present study, we investigated the use of a small, light weight, and low cost digital current-sensing integrated circuit for acquiring cortical surface signals from a 61-channel micro-electrocorticographic (μECoG) array. Approach. We recorded both acute and chronic μECoG signal from rat auditory cortex using our novel digital current-sensing headstage. For direct comparison, separate recordings were made in the same anesthetized preparations using an analog voltage headstage. A model of electrode impedance explained the transformation between current- and voltage-sensed signals, and was used to reconstruct cortical potential. We evaluated the digital headstage using several metrics of the baseline and response signals. Main results. The digital current headstage recorded neural signal with similar spatiotemporal statistics and auditory frequency tuning compared to the voltage signal. The signal-to-noise ratio of auditory evoked responses (AERs) was significantly stronger in the current signal. Stimulus decoding based on true and reconstructed voltage signals were not significantly different. Recordings from an implanted system showed AERs that were detectable and decodable for 52 d. The reconstruction filter mitigated the thermal current noise of the electrode impedance and enhanced overall SNR. Significance. We developed and validated a novel approach to headstage acquisition that used current-input circuits to independently digitize 61 channels of μECoG measurements of the cortical field. These low-cost circuits, intended to measure photo-currents in digital imaging, not only provided a signal representing the local cortical field with virtually the same sensitivity and specificity as a traditional voltage headstage but also resulted in a small, light headstage that can easily be scaled to record from hundreds of channels.

A low-cost, scalable, current-sensing digital headstage for high channel count μECoG

PubMed Central

Trumpis, Michael; Insanally, Michele; Zou, Jialin; Elsharif, Ashraf; Ghomashchi, Ali; Artan, N. Sertac; Froemke, Robert C.; Viventi, Jonathan

2017-01-01

Objective High channel count electrode arrays allow for the monitoring of large-scale neural activity at high spatial resolution. Implantable arrays featuring many recording sites require compact, high bandwidth front-end electronics. In the present study, we investigated the use of a small, light weight, and low cost digital current-sensing integrated circuit for acquiring cortical surface signals from a 61-channel micro-electrocorticographic (μECoG) array. Approach We recorded both acute and chronic μECoG signal from rat auditory cortex using our novel digital current-sensing headstage. For direct comparison, separate recordings were made in the same anesthetized preparations using an analog voltage headstage. A model of electrode impedance explained the transformation between current- and voltage-sensed signals, and was used to reconstruct cortical potential. We evaluated the digital headstage using several metrics of the baseline and response signals. Main results The digital current headstage recorded neural signal with similar spatiotemporal statistics and auditory frequency tuning compared to the voltage signal. The signal-to-noise ratio of auditory evoked responses (AERs) was significantly stronger in the current signal. Stimulus decoding based on true and reconstructed voltage signals were not significantly different. Recordings from an implanted system showed AERs that were detectable and decodable for 52 days. The reconstruction filter mitigated the thermal current noise of the electrode impedance and enhanced overall SNR. Significance We developed and validated a novel approach to headstage acquisition that used current-input circuits to independently digitize 61 channels of μECoG measurements of the cortical field. These low-cost circuits, intended to measure photo-currents in digital imaging, not only provided a signal representing the local cortical field with virtually the same sensitivity and specificity as a traditional voltage headstage but also resulted in a small, light headstage that can easily be scaled to record from hundreds of channels. PMID:28102827

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

PubMed

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

The Mid-Infrared Instrument for the James Webb Space Telescope, VIII: The MIRI Focal Plane System

NASA Astrophysics Data System (ADS)

Ressler, M. E.; Sukhatme, K. G.; Franklin, B. R.; Mahoney, J. C.; Thelen, M. P.; Bouchet, P.; Colbert, J. W.; Cracraft, Misty; Dicken, D.; Gastaud, R.; Goodson, G. B.; Eccleston, Paul; Moreau, V.; Rieke, G. H.; Schneider, Analyn

2015-07-01

We describe the layout and unique features of the focal plane system for MIRI. We begin with the detector array and its readout integrated circuit (combining the amplifier unit cells and the multiplexer), the electronics, and the steps by which the data collection is controlled and the output signals are digitized and delivered to the JWST spacecraft electronics system. We then discuss the operation of this MIRI data system, including detector readout patterns, operation of subarrays, and data formats. Finally, we summarize the performance of the system, including remaining anomalies that need to be corrected in the data pipeline.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

The mini-O, a digital superhet, or a truly low-cost Omega navigation receiver

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1975-01-01

A quartz tuning fork filter circuit and some unique CMOS clock logic methods provide a very simple OMEGA-VLF receiver with true hyperbolic station pair phase difference outputs. An experimental system was implemented on a single battery-operated circuit board requiring only an external antenna preamplifier, and LOP output recorder. A bench evaluation and preliminary navigation tests indicate the technique is viable and can provide very low-cost OMEGA measurement systems. The method is promising for marine use with small boats in the present form, but might be implemented in conjunction with digital microprocessors for airborne navigation aids.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

PubMed

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Modeling and control parameters for GMAW, short-circuiting transfer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cook, G.E.; DeLapp, D.R.; Barnett, R.J.

1996-12-31

Digital signal processing was used to analyze the electrical arc signals of the gas metal arc welding process with short-circuiting transfer. Among the features extracted were arc voltage and current (both average and peak values), short-circuiting frequency, arc period, shorting period, and the ratio of the arcing to shorting period. Additionally , a Joule heating model was derived which accurately predicted the melt-back distance during each short. The short-circuiting frequency, the ratio of the arc period to short periods, and the melt-back distance were found to be good indicators for monitoring and control of stable arc conditions.

[Design of High Frequency Signal Detecting Circuit of Human Body Impedance Used for Ultrashort Wave Diathermy Apparatus].

PubMed

Fan, Xu; Wang, Yunguang; Cheng, Haiping; Chong, Xiaochen

2016-02-01

The present circuit was designed to apply to human tissue impedance tuning and matching device in ultra-short wave treatment equipment. In order to judge if the optimum status of circuit parameter between energy emitter circuit and accepter circuit is in well syntony, we designed a high frequency envelope detect circuit to coordinate with automatic adjust device of accepter circuit, which would achieve the function of human tissue impedance matching and tuning. Using the sampling coil to receive the signal of amplitude-modulated wave, we compared the voltage signal of envelope detect circuit with electric current of energy emitter circuit. The result of experimental study was that the signal, which was transformed by the envelope detect circuit, was stable and could be recognized by low speed Analog to Digital Converter (ADC) and was proportional to the electric current signal of energy emitter circuit. It could be concluded that the voltage, transformed by envelope detect circuit can mirror the real circuit state of syntony and realize the function of human tissue impedance collecting.

RADC SCAT automated sneak circuit analysis tool

NASA Astrophysics Data System (ADS)

Depalma, Edward L.

The sneak circuit analysis tool (SCAT) provides a PC-based system for real-time identification (during the design phase) of sneak paths and design concerns. The tool utilizes an expert system shell to assist the analyst so that prior experience with sneak analysis is not necessary for performance. Both sneak circuits and design concerns are targeted by this tool, with both digital and analog circuits being examined. SCAT focuses the analysis at the assembly level, rather than the entire system, so that most sneak problems can be identified and corrected by the responsible design engineer in a timely manner. The SCAT program identifies the sneak circuits to the designer, who then decides what course of action is necessary.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Chaos in a neural network circuit

NASA Astrophysics Data System (ADS)

Kepler, Thomas B.; Datt, Sumeet; Meyer, Robert B.; Abott, L. F.

1990-12-01

We have constructed a neural network circuit of four clipped, high-grain, integrating operational amplifiers coupled to each other through an array of digitally programmable resistor ladders (MDACs). In addition to fixed-point and cyclic behavior, the circuit exhibits chaotic behavior with complex strange attractors which are approached through period doubling, intermittent attractor expansion and/or quasiperiodic pathways. Couplings between the nonlinear circuit elements are controlled by a computer which can automatically search through the space of couplings for interesting phenomena. We report some initial statistical results relating the behavior of the network to properties of its coupling matrix. Through these results and further research the circuit should help resolve fundamental issues concerning chaos in neural networks.

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Make Your Own Digital Thermometer!

ERIC Educational Resources Information Center

Sorey, Timothy; Willard, Teri; Kim, Bom

2010-01-01

In the hands-on, guided-inquiry lesson presented in this article, high school students create, calibrate, and apply an affordable scientific-grade instrument (Lapp and Cyrus 2000). In just four class periods, they build a homemade integrated circuit (IC) digital thermometer, apply a math model to calibrate their instrument, and ask a researchable…

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

A digital indicator for maximum windspeeds.

Treesearch

William B. Fowler

1969-01-01

A simple device for indicating maximum windspeed during a time interval is described. Use of a unijunction transistor, for voltage sensing, results in a stable comparison circuit and also reduces overall component requirements. Measurement is presented digitally in 1-mile-per-hour increments over the range of 0-51 m.p.h.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

PubMed

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

A Basic Research for the Development and Evaluation of Novel MEMS Digital Accelerometers

DTIC Science & Technology

2013-02-01

that timing differences as measured by the circuit are linearly dependent on the measured capacitance changes. As such, the circuit’s readout is...error in the electronic measurement to refine the technique. An additional capability of the circuit is the ability to observe the impact of cold...low resistivity on (ɘ.01 Ω-cm) silicon on insulator wafers (SOI). The beams are fabricated in a 0.3 cm by 0.3 cm die which is then packaged and wire

High-frequency trigger generators for CuBr-laser high voltage pumping source

NASA Astrophysics Data System (ADS)

Torgaev, S.; Kozhemyak, O.; Yaroslavtsev, E.; Trigub, M.; Musorov, I.; Chertikhina, D.

2016-04-01

In this paper the circuits of high frequency trigger generators of pulses of the nanosecond duration are presented. A detailed study of a generator based on the avalanche transistor with the use of a coaxial cable instead of a capacitor is described. This circuit showed advanced characteristics of the output pulses. A circuit of a generator built on high-speed digital components is also considered. The basic advantages and disadvantages of both generators are presented in this paper.

Electrical Circuit Tester

DOEpatents

Love, Frank

2006-04-18

An electrical circuit testing device is provided, comprising a case, a digital voltage level testing circuit with a display means, a switch to initiate measurement using the device, a non-shorting switching means for selecting pre-determined electrical wiring configurations to be tested in an outlet, a terminal block, a five-pole electrical plug mounted on the case surface and a set of adapters that can be used for various multiple-pronged electrical outlet configurations for voltages from 100 600 VAC from 50 100 Hz.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Numerical Solution of Laminar and Turbulent Boundary Layer Equations Including Transition, and Experimenmtal Study of a Flat Plate with a Blunt Fin at Incidence.

DTIC Science & Technology

1986-03-01

93 3.6.5.4 Data Acquisition- Electrical Analog. . 95 3.6.6 Co-axial Thermocouple Gages ...... 97 3.6.6.1 Theory .................... 101 3.6.6.2...Preparation of Liquid Crystal Model . . . 233 Appendix G: Digital Image Processing . ........ 235 Appendix H: Electrical Analog Circuits ....... . 237...m. 232 H.la Thermal Circuit ..... ................. . 237 H.Ib Electrical Circuit ..... ............... 237 H.2 Electrical Analog Using Equal Sections

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

NASA Astrophysics Data System (ADS)

Chen, Keng; Zhang, Hong

2015-12-01

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm2 by using 180 nm CMOS technology.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Satellite networks in the ISDN era

NASA Astrophysics Data System (ADS)

Amadesi, P.; Haines, P.; Patacchini, A.

1986-12-01

The development of an integrated service digital network (ISDN) capable of supporting a wide range of services using a small set of standard multipurpose user-network interfaces is examined. The ISDN environment is expected to consist of functional elements such as, circuit switching, packet switching, and common channel signaling. The use of satellites or fiber optics in the ISDN is evaluated. The relation between satellites and the ISDN in the short-, medium-, and long-terms is analyzed. The recommendations of the consultative committee, CCIR, concerning the definition of the hypothetical reference digital path and the required quality and availability for ISDN applications, and the proposed plans of Eutelsat and Intelsat for satellite systems compatible with an ISDN are discussed. The application of business satellite networks and packet satellite networks to an ISDN is studied. The long-term objectives for an ISDN is a wideband system that accommodates digital transmission on circuit and packet switched bases.

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

NASA Astrophysics Data System (ADS)

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

2015-11-01

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

Subranging technique using superconducting technology

DOEpatents

Gupta, Deepnarayan

2003-01-01

Subranging techniques using "digital SQUIDs" are used to design systems with large dynamic range, high resolution and large bandwidth. Analog-to-digital converters (ADCs) embodying the invention include a first SQUID based "coarse" resolution circuit and a second SQUID based "fine" resolution circuit to convert an analog input signal into "coarse" and "fine" digital signals for subsequent processing. In one embodiment, an ADC includes circuitry for supplying an analog input signal to an input coil having at least a first inductive section and a second inductive section. A first superconducting quantum interference device (SQUID) is coupled to the first inductive section and a second SQUID is coupled to the second inductive section. The first SQUID is designed to produce "coarse" (large amplitude, low resolution) output signals and the second SQUID is designed to produce "fine" (low amplitude, high resolution) output signals in response to the analog input signals.

Open circuit potential monitored digital photocorrosion of GaAs/AlGaAs quantum well microstructures

NASA Astrophysics Data System (ADS)

Aithal, Srivatsa; Dubowski, Jan J.

2018-04-01

Nanostructuring of semiconductor wafers with an atomic level depth resolution is a challenging task, primarily due to the limited availability of instruments for in situ monitoring of such processes. Conventional digital etching relies on calibration procedures and cumbersome diagnostics applied between or at the end of etching cycles. We have developed a photoluminescence (PL) based process for monitoring in situ digital photocorrosion (DPC) of GaAs/AlGaAs microstructures at rates below 0.2 nm per cycle. In this communication, we demonstrate that DPC of GaAs/AlGaAs microstructures could be monitored with open circuit potential (OCP) measured between the photocorroding surface of a microstructure and an Ag/AgCl reference electrode installed in the sample chamber. The excellent correlation between the position of both PL and OCP maxima indicates that the DPC process could be monitored in situ for materials that do not necessarily exhibit measurable PL emission.

Laser Scanner Tests For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Kim, Quiesup; Soli, George A.; Schwartz, Harvey R.

1992-01-01

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

Circuit design for the retina-like image sensor based on space-variant lens array

NASA Astrophysics Data System (ADS)

Gao, Hongxun; Hao, Qun; Jin, Xuefeng; Cao, Jie; Liu, Yue; Song, Yong; Fan, Fan

2013-12-01

Retina-like image sensor is based on the non-uniformity of the human eyes and the log-polar coordinate theory. It has advantages of high-quality data compression and redundant information elimination. However, retina-like image sensors based on the CMOS craft have drawbacks such as high cost, low sensitivity and signal outputting efficiency and updating inconvenience. Therefore, this paper proposes a retina-like image sensor based on space-variant lens array, focusing on the circuit design to provide circuit support to the whole system. The circuit includes the following parts: (1) A photo-detector array with a lens array to convert optical signals to electrical signals; (2) a strobe circuit for time-gating of the pixels and parallel paths for high-speed transmission of the data; (3) a high-precision digital potentiometer for the I-V conversion, ratio normalization and sensitivity adjustment, a programmable gain amplifier for automatic generation control(AGC), and a A/D converter for the A/D conversion in every path; (4) the digital data is displayed on LCD and stored temporarily in DDR2 SDRAM; (5) a USB port to transfer the data to PC; (6) the whole system is controlled by FPGA. This circuit has advantages as lower cost, larger pixels, updating convenience and higher signal outputting efficiency. Experiments have proved that the grayscale output of every pixel basically matches the target and a non-uniform image of the target is ideally achieved in real time. The circuit can provide adequate technical support to retina-like image sensors based on space-variant lens array.

Conversion of cardiac performance data in analog form for digital computer entry

NASA Technical Reports Server (NTRS)

Miller, R. L.

1972-01-01

A system is presented which will reduce analog cardiac performance data and convert the results to digital form for direct entry into a commercial time-shared computer. Circuits are discussed which perform the measurement and digital conversion of instantaneous systolic and diastolic parameters from the analog blood pressure waveform. Digital averaging over a selected number of heart cycles is performed on these measurements, as well as those of flow and heart rate. The determination of average cardiac output and peripheral resistance, including trends, is the end result after processing by digital computer.

Four-to-one power combiner for 20 GHz phased array antenna using RADC MMIC phase shifters

NASA Technical Reports Server (NTRS)

1991-01-01

The design and microwave simulation of two-to-one microstrip power combiners is described. The power combiners were designed for use in a four element phase array receive antenna subarray at 20 GHz. Four test circuits are described which were designed to enable testing of the power combiner and the four element phased array antenna. Test Circuit 1 enables measurement of the two-to-one power combiner. Test Circuit 2 enables measurement of the four-to-one power combiner. Test Circuit 3 enables measurement of a four element antenna array without phase shifting MMIC's in order to characterize the power combiner with the antenna patch-to-microstrip coaxial feedthroughs. Test circuit 4 is the four element phased array antenna including the RADC MMIC phase shifters and appropriate interconnects to provide bias voltages and control phase bits.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Phase-locked loops. [in analog and digital circuits communication system

NASA Technical Reports Server (NTRS)

Gupta, S. C.

1975-01-01

An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

Representation and matching of knowledge to design digital systems

NASA Technical Reports Server (NTRS)

Jones, J. U.; Shiva, S. G.

1988-01-01

A knowledge-based expert system is described that provides an approach to solve a problem requiring an expert with considerable domain expertise and facts about available digital hardware building blocks. To design digital hardware systems from their high level VHDL (Very High Speed Integrated Circuit Hardware Description Language) representation to their finished form, a special data representation is required. This data representation as well as the functioning of the overall system is described.

Rounding Technique for High-Speed Digital Signal Processing

NASA Technical Reports Server (NTRS)

Wechsler, E. R.

1983-01-01

Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.

Christmas Light Display

NASA Astrophysics Data System (ADS)

Ross, Arthur; Renfro, Timothy

2012-03-01

The Digital Electronics class at McMurry University created a Christmas light display that toggles the power of different strands of lights, according to what frequencies are played in a song, as an example of an analog to digital circuit. This was accomplished using a BA3830S IC six-band audio filter and six solid-state relays.

76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-19

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-806] Certain Digital Televisions Containing... Investigation Pursuant to 19 U.S.C. 1337 AGENCY: U.S. International Trade Commission. ACTION: Notice. SUMMARY: Notice is hereby given that a complaint was filed with the U.S. International Trade Commission on August...

Time Domain Algorithms.

DTIC Science & Technology

1985-09-01

Conitr., vol. AC-2S, No. 1, pp. 07-99, Jan. 1083. [481 A. Fettweis, "Digital Circuits and Systems," ZEEE Trans. Circ. and Sys., vol. CAS-31, No. 1, pp...171 J. G. Proakis, Digital Communications, McGraw-Hill, New York, 1983. 1181 P. Monsen, "Adaptive Equalization of the Slow Fading Channel," ZEEE Tran

System and method for regulating resonant inverters

DOEpatents

Stevanovic, Ljubisa Dragoljub [Clifton Park, NY; Zane, Regan Andrew [Superior, CO

2007-08-28

A technique is provided for direct digital phase control of resonant inverters based on sensing of one or more parameters of the resonant inverter. The resonant inverter control system includes a switching circuit for applying power signals to the resonant inverter and a sensor for sensing one or more parameters of the resonant inverter. The one or more parameters are representative of a phase angle. The resonant inverter control system also includes a comparator for comparing the one or more parameters to a reference value and a digital controller for determining timing of the one or more parameters and for regulating operation of the switching circuit based upon the timing of the one or more parameters.

Multi-Modulator for Bandwidth-Efficient Communication

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Lay, Norman; Cheetham, Craig; Fong, Wai; Yeh, Pen-Shu; King, Robin; Ghuman, Parminder; Hoy, Scott; Fisher, Dave

2009-01-01

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

VLSI circuits implementing computational models of neocortical circuits.

PubMed

Wijekoon, Jayawan H B; Dudek, Piotr

2012-09-15

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

European roadmap on superconductive electronics - status and perspectives

NASA Astrophysics Data System (ADS)

Anders, S.; Blamire, M. G.; Buchholz, F.-Im.; Crété, D.-G.; Cristiano, R.; Febvre, P.; Fritzsch, L.; Herr, A.; Il'ichev, E.; Kohlmann, J.; Kunert, J.; Meyer, H.-G.; Niemeyer, J.; Ortlepp, T.; Rogalla, H.; Schurig, T.; Siegel, M.; Stolz, R.; Tarte, E.; ter Brake, H. J. M.; Toepfer, H.; Villegier, J.-C.; Zagoskin, A. M.; Zorin, A. B.

2010-12-01

Executive SummaryFor four decades semiconductor electronics has followed Moore’s law: with each generation of integration the circuit features became smaller, more complex and faster. This development is now reaching a wall so that smaller is no longer any faster. The clock rate has saturated at about 3-5 GHz and the parallel processor approach will soon reach its limit. The prime reason for the limitation the semiconductor electronics experiences is not the switching speed of the individual transistor, but its power dissipation and thus heat. Digital superconductive electronics is a circuit- and device-technology that is inherently faster at much less power dissipation than semiconductor electronics. It makes use of superconductors and Josephson junctions as circuit elements, which can provide extremely fast digital devices in a frequency range - dependent on the material - of hundreds of GHz: for example a flip-flop has been demonstrated that operated at 750 GHz. This digital technique is scalable and follows similar design rules as semiconductor devices. Its very low power dissipation of only 0.1 μW per gate at 100 GHz opens the possibility of three-dimensional integration. Circuits like microprocessors and analogue-to-digital converters for commercial and military applications have been demonstrated. In contrast to semiconductor circuits, the operation of superconducting circuits is based on naturally standardized digital pulses the area of which is exactly the flux quantum Φ0. The flux quantum is also the natural quantization unit for digital-to-analogue and analogue-to-digital converters. The latter application is so precise, that it is being used as voltage standard and that the physical unit ‘Volt’ is defined by means of this standard. Apart from its outstanding features for digital electronics, superconductive electronics provides also the most sensitive sensor for magnetic fields: the Superconducting Quantum Interference Device (SQUID). Amongst many other applications SQUIDs are used as sensors for magnetic heart and brain signals in medical applications, as sensor for geological surveying and food-processing and for non-destructive testing. As amplifiers of electrical signals, SQUIDs can nearly reach the theoretical limit given by Quantum Mechanics. A further important field of application is the detection of very weak signals by ‘transition-edge’ bolometers, superconducting nanowire single-photon detectors, and superconductive tunnel junctions. Their application as radiation detectors in a wide frequency range, from microwaves to X-rays is now standard. The very low losses of superconductors have led to commercial microwave filter designs that are now widely used in the USA in base stations for cellular phones and in military communication applications. The number of demonstrated applications is continuously increasing and there is no area in professional electronics, in which superconductive electronics cannot be applied and surpasses the performance of classical devices. Superconductive electronics has to be cooled to very low temperatures. Whereas this was a bottleneck in the past, cooling techniques have made a huge step forward in recent years: very compact systems with high reliability and a wide range of cooling power are available commercially, from microcoolers of match-box size with milli-Watt cooling power to high-reliability coolers of many Watts of cooling power for satellite applications. Superconductive electronics will not replace semiconductor electronics and similar room-temperature techniques in standard applications, but for those applications which require very high speed, low-power consumption, extreme sensitivity or extremely high precision, superconductive electronics is superior to all other available techniques. To strengthen the European competitiveness in superconductor electronics research projects have to be set-up in the following field: Ultra-sensitive sensing and imaging. Quantum measurement instrumentation. Advanced analogue-to-digital converters. Superconductive electronics technology.

High fidelity, radiation tolerant analog-to-digital converters

NASA Technical Reports Server (NTRS)

Wang, Charles Chang-I (Inventor); Linscott, Ivan Richard (Inventor); Inan, Umran S. (Inventor)

2012-01-01

Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming <60 milliWatts. Furthermore, even though it is manufactured in a commercial 0.25-.mu.m CMOS technology (1 .mu.m=12.sup.-6 meters), it maintains this performance in harsh radiation environments. Specifically, the stated performance is sustained through a highest tested 2 megarad(Si) total dose, and the ADC displays no latchup up to a highest tested linear energy transfer of 63 million electron Volts square centimeters per milligram at elevated temperature (131 degrees C.) and supply (2.7 Volts, versus 2.5 Volts nominal).

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

NASA Astrophysics Data System (ADS)

Bhasin, K. B.; Anzic, G.; Kunath, R. R.; Connolly, D. J.

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

Optical techniques to feed and control GaAs MMIC modules for phased array antenna applications

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Anzic, G.; Kunath, R. R.; Connolly, D. J.

1986-01-01

A complex signal distribution system is required to feed and control GaAs monolithic microwave integrated circuits (MMICs) for phased array antenna applications above 20 GHz. Each MMIC module will require one or more RF lines, one or more bias voltage lines, and digital lines to provide a minimum of 10 bits of combined phase and gain control information. In a closely spaced array, the routing of these multiple lines presents difficult topology problems as well as a high probability of signal interference. To overcome GaAs MMIC phased array signal distribution problems optical fibers interconnected to monolithically integrated optical components with GaAs MMIC array elements are proposed as a solution. System architecture considerations using optical fibers are described. The analog and digital optical links to respectively feed and control MMIC elements are analyzed. It is concluded that a fiber optic network will reduce weight and complexity, and increase reliability and performance, but higher power will be required.

One output function: a misconception of students studying digital systems - a case study

NASA Astrophysics Data System (ADS)

Trotskovsky, E.; Sabag, N.

2015-05-01

Background:Learning processes are usually characterized by students' misunderstandings and misconceptions. Engineering educators intend to help their students overcome their misconceptions and achieve correct understanding of the concept. This paper describes a misconception in digital systems held by many students who believe that combinational logic circuits should have only one output. Purpose:The current study aims to investigate the roots of the misconception about one-output function and the pedagogical methods that can help students overcome the misconception. Sample:Three hundred and eighty-one students in the Departments of Electrical and Electronics and Mechanical Engineering at an academic engineering college, who learned the same topics of a digital combinational system, participated in the research. Design and method:In the initial research stage, students were taught according to traditional method - first to design a one-output combinational logic system, and then to implement a system with a number of output functions. In the main stage, an experimental group was taught using a new method whereby they were shown how to implement a system with several output functions, prior to learning about one-output systems. A control group was taught using the traditional method. In the replication stage (the third stage), an experimental group was taught using the new method. A mixed research methodology was used to examine the results of the new learning method. Results:Quantitative research showed that the new teaching approach resulted in a statistically significant decrease in student errors, and qualitative research revealed students' erroneous thinking patterns. Conclusions:It can be assumed that the traditional teaching method generates an incorrect mental model of the one-output function among students. The new pedagogical approach prevented the creation of an erroneous mental model and helped students develop the correct conceptual understanding.

Digital Baseband Architecture For Transponder

NASA Technical Reports Server (NTRS)

Nguyen, Tien M.; Yeh, Hen-Geul

1995-01-01

Proposed advanced transponder for long-distance radio communication system with turnaround ranging contains carrier-signal-tracking loop including baseband digital "front end." For reduced cost, transponder includes analog intermediate-frequency (IF) section and analog automatic gain control (AGC) loop at first of two IF mixers. However, second IF mixer redesigned to ease digitization of baseband functions. To conserve power and provide for simpler and smaller transponder hardware, baseband digital signal-processing circuits designed to implement undersampling scheme. Furthermore, sampling scheme and sampling frequency chosen so redesign involves minimum modification of command-detector unit (CDU).

Development of a digital microfluidic platform for point of care testing

PubMed Central

Sista, Ramakrishna; Hua, Zhishan; Thwar, Prasanna; Sudarsan, Arjun; Srinivasan, Vijay; Eckhardt, Allen; Pollack, Michael; Pamula, Vamsee

2009-01-01

Point of care testing is playing an increasingly important role in improving the clinical outcome in health care management. The salient features of a point of care device are quick results, integrated sample preparation and processing, small sample volumes, portability, multifunctionality and low cost. In this paper, we demonstrate some of these salient features utilizing an electrowetting-based Digital Microfluidic platform. We demonstrate the performance of magnetic bead-based immunoassays (cardiac troponin I) on a digital microfluidic cartridge in less than 8 minutes using whole blood samples. Using the same microfluidic cartridge, a 40-cycle real-time polymerase chain reaction was performed within 12 minutes by shuttling a droplet between two thermal zones. We further demonstrate, on the same cartridge, the capability to perform sample preparation for bacterial and fungal infectious disease pathogens (methicillin-resistance Staphylococcus aureus and Candida albicans) and for human genomic DNA using magnetic beads. In addition to rapid results and integrated sample preparation, electrowetting-based digital microfluidic instruments are highly portable because fluid pumping is performed electronically. All the digital microfluidic chips presented here were fabricated on printed circuit boards utilizing mass production techniques that keep the cost of the chip low. Due to the modularity and scalability afforded by digital microfluidics, multifunctional testing capability, such as combinations within and between immunoassays, DNA amplification, and enzymatic assays, can be brought to the point of care at a relatively low cost because a single chip can be configured in software for different assays required along the path of care. PMID:19023472

Multi-level Simulation of a Real Time Vibration Monitoring System Component

NASA Technical Reports Server (NTRS)

Robertson, Bryan A.; Wilkerson, Delisa

2005-01-01

This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by Marshall Space Flight Center (MSFC) Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data fiom two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMC-IRA design has completed all engineering and deliverable unit testing. P

Multi-level Simulation of a Real Time Vibration Monitoring System Component

NASA Technical Reports Server (NTRS)

Roberston, Bryan; Wilkerson, DeLisa

2004-01-01

This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by MSFC Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data from two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMCIRA design has completed all engineering unit testing and the deliverable unit is currently under development.

Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

NASA Technical Reports Server (NTRS)

Slaughter, D. W.

1977-01-01

A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T.J.; Nowlen, S.P.; Anderson, D.J.

Smoke can adversely affect digital electronics; in the short term, it can lead to circuit bridging and in the long term to corrosion of metal parts. This report is a summary of the work to date and component-level tests by Sandia National Laboratories for the Nuclear Regulatory Commission to determine the impact of smoke on digital instrumentation and control equipment. The component tests focused on short-term effects such as circuit bridging in typical components and the factors that can influence how much the smoke will affect them. These factors include the component technology and packaging, physical board protection, and environmentalmore » conditions such as the amount of smoke, temperature of burn, and humidity level. The likelihood of circuit bridging was tested by measuring leakage currents and converting those currents to resistance in ohms. Hermetically sealed ceramic packages were more resistant to smoke than plastic packages. Coating the boards with an acrylic spray provided some protection against circuit bridging. The smoke generation factors that affect the resistance the most are humidity, fuel level, and burn temperature. The use of CO{sub 2} as a fire suppressant, the presence of galvanic metal, and the presence of PVC did not significantly affect the outcome of these results.« less

Synchronous radio-frequency FM signal generator using direct digital synthesizers

NASA Astrophysics Data System (ADS)

Arablu, Masoud; Kafashi, Sajad; Smith, Stuart T.

2018-04-01

A novel Radio-Frequency Frequency-Modulated (RF-FM) signal generation method is introduced and a prototype circuit developed to evaluate its functionality and performance. The RF-FM signal generator uses a modulated, voltage-controlled time delay to correspondingly modulate the phase of a 10 MHz sinusoidal reference signal. This modulated reference signal is, in turn, used to clock a Direct Digital Synthesizer (DDS) circuit resulting in an FM signal at its output. The modulating signal that is input to the voltage-controlled time delay circuit is generated by another DDS that is synchronously clocked by the same 10 MHz sine wave signal before modulation. As a consequence, all of the digital components are timed from a single sine wave oscillator that forms the basis of all timing. The resultant output signal comprises a center, or carrier, frequency plus a series of phase-synchronized sidebands having exact integer harmonic frequency separation. In this study, carrier frequencies ranging from 10 MHz to 70 MHz are generated with modulation frequencies ranging from 10 kHz to 300 kHz. The captured spectra show that the FM signal characteristics, amplitude and phase, of the sidebands and the modulation depth are consistent with the Jacobi-Anger expansion for modulated harmonic signals.

A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

NASA Astrophysics Data System (ADS)

Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan

2018-01-01

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V. He received 2016 International Low Power Design Contest Award from ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from Univ. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008, 2001, and 1999 Samsung Humantec Thesis Award and, 2005 ETRI Journal Paper of the Year Award. He is an author/co-author of +100 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed- mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an associate editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.

Binary to Octal and Octal to Binary Code Converter Using Mach-Zehnder Interferometer for High Speed Communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2017-05-01

Binary to octal and octal to binary code converter is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using external gates. In this paper, binary to octal and octal to binary code converter is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

Additively Manufactured IN718 Components with Wirelessly Powered and Interrogated Embedded Sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Attridge, Paul; Bajekal, Sanjay; Klecka, Michael

A methodology is described for embedding commercial-off-the-shelf sensors together with wireless communication and power circuit elements using direct laser metal sintered additively manufactured components. Physics based models of the additive manufacturing processes and sensor/wireless level performance models guided the design and embedment processes. A combination of cold spray deposition and laser engineered net shaping was used to fashion the transmitter/receiving elements and embed the sensors, thereby providing environmental protection and component robustness/survivability for harsh conditions. By design, this complement of analog and digital sensors were wirelessly powered and interrogated using a health and utilization monitoring system; enabling real-time, in situmore » prognostics and diagnostics.« less

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

Cryogenic applications of commercial electronic components

NASA Astrophysics Data System (ADS)

Buchanan, Ernest D.; Benford, Dominic J.; Forgione, Joshua B.; Harvey Moseley, S.; Wollack, Edward J.

2012-10-01

We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2 K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG [1] and in the GISMO [2] camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.

Implementation of olfactory bulb glomerular-layer computations in a digital neurosynaptic core.

PubMed

Imam, Nabil; Cleland, Thomas A; Manohar, Rajit; Merolla, Paul A; Arthur, John V; Akopyan, Filipp; Modha, Dharmendra S

2012-01-01

We present a biomimetic system that captures essential functional properties of the glomerular layer of the mammalian olfactory bulb, specifically including its capacity to decorrelate similar odor representations without foreknowledge of the statistical distributions of analyte features. Our system is based on a digital neuromorphic chip consisting of 256 leaky-integrate-and-fire neurons, 1024 × 256 crossbar synapses, and address-event representation communication circuits. The neural circuits configured in the chip reflect established connections among mitral cells, periglomerular cells, external tufted cells, and superficial short-axon cells within the olfactory bulb, and accept input from convergent sets of sensors configured as olfactory sensory neurons. This configuration generates functional transformations comparable to those observed in the glomerular layer of the mammalian olfactory bulb. Our circuits, consuming only 45 pJ of active power per spike with a power supply of 0.85 V, can be used as the first stage of processing in low-power artificial chemical sensing devices inspired by natural olfactory systems.

Cryogenic Applications of Commercial Electronic Components

NASA Technical Reports Server (NTRS)

Buchanan, Ernest D.; Benford, Dominic J.; Forgione, Joshua B.; Moseley, S. Harvey; Wollack, Edward J.

2012-01-01

We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG and in the GISMO camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.

AC resistance measuring instrument

DOEpatents

Hof, P.J.

1983-10-04

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument. 8 figs.

AC Resistance measuring instrument

DOEpatents

Hof, Peter J.

1983-01-01

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

A single chip 2 Gbit/s clock recovery subsystem for digital communications

NASA Astrophysics Data System (ADS)

Hickling, Ronald M.

A self-contained clock recovery/data resynchronizer phase locked loop (PLL) for use in microwave and fiber optic digital communications has been fabricated using GaAs integrated circuit technology. The IC contains the analog and digital components for the PLL: an edge-triggered phase detector based on a 1.2 GHz phase/frequency comparator, an op amp for creating the loop filter, and a VCO based on a differential source-coupled pair amplifier.

(M-CAT) Minor Caliber Weapons Trainer MK-19, 40mm Machine Gun

DTIC Science & Technology

1989-07-24

microprocessor chip with an Intel 387 math coprocessor. The Nova 620 is a digital time base corrector. It is used to time base correct the video data...the circuit. After filtering, the horizontal and vertical position signals are converted to digital values by the Data Translation (DTX-311) analog...from the computer. Each frame of the video disk is individually digitized as to target size, location, and range. The guns azimuth and elevation are

AN/TAC-1 demultiplexer circuit card assembly

NASA Astrophysics Data System (ADS)

Krueger, Paul J.

1989-01-01

This report describes the design, operation, and testing of the AN/TAC-1 demultiplexer subassembly. It demultiplexes the 6144 kb/s digital data stream received over fiber optic cable or tropo satellite support radio, and converts it into 2 digital groups and 16 digital channels. Timing recovery is accomplished by generating a 18432 kHz master clock synchronized to the incoming data. This master clock is divided modulo two to generate the proper group and loop timing.

Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications

NASA Astrophysics Data System (ADS)

Lin, Yu-Ta; Ker, Ming-Dou; Wang, Tzu-Ming

2011-03-01

A new on-panel readout circuit with threshold voltage compensation for capacitive sensor in low temperature polycrystalline silicon (poly-Si) thin-film transistor (LTPS-TFT) process has been proposed. In order to compensate the threshold voltage variation from LTPS process variation, the proposed readout circuit applies a novel compensation approach with switch capacitor technique. In addition, a 4-bit analog-to-digital converter (ADC) is added to identify different sensed capacitor values and further enhances the overall resolution of touch panel.

Minimal Power Latch for Single-Slope ADCs

NASA Technical Reports Server (NTRS)

Hancock, Bruce R. (Inventor)

2015-01-01

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Architecture for a 1-GHz Digital RADAR

NASA Technical Reports Server (NTRS)

Mallik, Udayan

2011-01-01

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

Functional High-Intensity Circuit Training Improves Body Composition, Peak Oxygen Uptake, Strength, and Alters Certain Dimensions of Quality of Life in Overweight Women.

PubMed

Sperlich, Billy; Wallmann-Sperlich, Birgit; Zinner, Christoph; Von Stauffenberg, Valerie; Losert, Helena; Holmberg, Hans-Christer

2017-01-01

The effects of circuit-like functional high-intensity training (Circuit HIIT ) alone or in combination with high-volume low-intensity exercise (Circuit combined ) on selected cardio-respiratory and metabolic parameters, body composition, functional strength and the quality of life of overweight women were compared. In this single-center, two-armed randomized, controlled study, overweight women performed 9-weeks (3 sessions·wk -1 ) of either Circuit HIIT ( n = 11), or Circuit combined ( n = 8). Peak oxygen uptake and perception of physical pain were increased to a greater extent ( p < 0.05) by Circuit HIIT , whereas Circuit combined improved perception of general health more ( p < 0.05). Both interventions lowered body mass, body-mass-index, waist-to-hip ratio, fat mass, and enhanced fat-free mass; decreased ratings of perceived exertion during submaximal treadmill running; improved the numbers of push-ups, burpees, one-legged squats, and 30-s skipping performed, as well as the height of counter-movement jumps; and improved physical and social functioning, role of physical limitations, vitality, role of emotional limitations, and mental health to a similar extent (all p < 0.05). Either forms of these multi-stimulating, circuit-like, multiple-joint training can be employed to improve body composition, selected variables of functional strength, and certain dimensions of quality of life in overweight women. However, Circuit HIIT improves peak oxygen uptake to a greater extent, but with more perception of pain, whereas Circuit combined results in better perception of general health.

Microcprocessing Computer Technician, Digital and Microprocessor Technician Program. Post-Graduate 5th Year.

ERIC Educational Resources Information Center

Carangelo, Pasquale R.; Janeczek, Anthony J.

Materials are provided for a two-semester digital and microprocessor technician postgraduate program. Prerequisites stated for the program include a background in DC and AC theory, solid state devices, basic circuit fundamentals, and basic math. A chronology of major topics and a listing of course objectives appear first. Theory outlines for each…

High-Speed Large-Alphabet Quantum Key Distribution Using Photonic Integrated Circuits

DTIC Science & Technology

2014-01-28

polarizing beam splitter, TDC: time-to-digital converter. Extra&loss& photon/bin frame size QSER secure bpp ECC secure&key&rate& none& 0.0031 64 14...to-digital converter. photon/frame frame size QSER secure bpp ECC secure&key& rate& 1.3 16 9.5 % 2.9 layered LDPC 7.3&Mbps& Figure 24: Operating

A Web-Based Visualization and Animation Platform for Digital Logic Design

ERIC Educational Resources Information Center

Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.

2015-01-01

This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

MANUFACTURING METHODS FOR PHASE SHIFTERS.

DTIC Science & Technology

MANUFACTURING), (*PHASE SHIFT CIRCUITS, FERRITES, GARNET , DIGITAL SYSTEMS, X BAND, C BAND, S BAND, RADAR EQUIPMENT, MAGNETIC MATERIALS, YTTRIUM COMPOUNDS, GADOLINIUM COMPOUNDS, ALUMINUM COMPOUNDS, IRON COMPOUNDS, OXIDES.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

The 4C/ID-Model in Physics Education: Instructional Design of a Digital Learning Environment to Teach Electrical Circuits

ERIC Educational Resources Information Center

Melo, Mário

2018-01-01

In this paper, readers are guided through the design and development of educational programs based on the 4C/ID model. This was illustrated via a practical example in Physics education, to teach the theme "Electrical circuits" to students of the 9th grade of compulsory education. In the article, the followed steps are described, from…

Topical Meeting of Broadband Analog and Digital Optoelectronics

DTIC Science & Technology

1992-01-01

effects [2]. Laser nonlinearitics can be minimised by careful design of the device to maximise the relaxation oscillation resonance frequency [2...feedback loop ultimately limits the stability of the circuit and determines the maximum frequency of operation. With hybrid circuit constructioi. this...range and number of accessible frequency channels), the tuning lever, and the filter selectivity (which determines the side-mode suppression ratio (SMSR

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Design of embedded endoscopic ultrasonic imaging system

NASA Astrophysics Data System (ADS)

Li, Ming; Zhou, Hao; Wen, Shijie; Chen, Xiodong; Yu, Daoyin

2008-12-01

Endoscopic ultrasonic imaging system is an important component in the endoscopic ultrasonography system (EUS). Through the ultrasonic probe, the characteristics of the fault histology features of digestive organs is detected by EUS, and then received by the reception circuit which making up of amplifying, gain compensation, filtering and A/D converter circuit, in the form of ultrasonic echo. Endoscopic ultrasonic imaging system is the back-end processing system of the EUS, with the function of receiving digital ultrasonic echo modulated by the digestive tract wall from the reception circuit, acquiring and showing the fault histology features in the form of image and characteristic data after digital signal processing, such as demodulation, etc. Traditional endoscopic ultrasonic imaging systems are mainly based on image acquisition and processing chips, which connecting to personal computer with USB2.0 circuit, with the faults of expensive, complicated structure, poor portability, and difficult to popularize. To against the shortcomings above, this paper presents the methods of digital signal acquisition and processing specially based on embedded technology with the core hardware structure of ARM and FPGA for substituting the traditional design with USB2.0 and personal computer. With built-in FIFO and dual-buffer, FPGA implement the ping-pong operation of data storage, simultaneously transferring the image data into ARM through the EBI bus by DMA function, which is controlled by ARM to carry out the purpose of high-speed transmission. The ARM system is being chosen to implement the responsibility of image display every time DMA transmission over and actualizing system control with the drivers and applications running on the embedded operating system Windows CE, which could provide a stable, safe and reliable running platform for the embedded device software. Profiting from the excellent graphical user interface (GUI) and good performance of Windows CE, we can not only clearly show 511×511 pixels ultrasonic echo images through application program, but also provide a simple and friendly operating interface with mouse and touch screen which is more convenient than the traditional endoscopic ultrasonic imaging system. Including core and peripheral circuits of FPGA and ARM, power network circuit and LCD display circuit, we designed the whole embedded system, achieving the desired purpose by implementing ultrasonic image display properly after the experimental verification, solving the problem of hugeness and complexity of the traditional endoscopic ultrasonic imaging system.