A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

A Fully Integrated Sensor SoC with Digital Calibration Hardware and Wireless Transceiver at 2.4 GHz

PubMed Central

Kim, Dong-Sun; Jang, Sung-Joon; Hwang, Tae-Ho

2013-01-01

A single-chip sensor system-on-a-chip (SoC) that implements radio for 2.4 GHz, complete digital baseband physical layer (PHY), 10-bit sigma-delta analog-to-digital converter and dedicated sensor calibration hardware for industrial sensing systems has been proposed and integrated in a 0.18-μm CMOS technology. The transceiver's building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indicator, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, the digital building block consists of offset quadrature phase-shift keying (OQPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, digital MAC function, sensor calibration hardware and embedded 8-bit microcontroller. The digital MAC function supports cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. The embedded sensor signal processing block consists of calibration coefficient calculator, sensing data calibration mapper and sigma-delta analog-to-digital converter with digital decimation filter. The sensitivity of the overall receiver and the error vector magnitude (EVM) of the overall transmitter are −99 dBm and 18.14%, respectively. The proposed calibration scheme has a reduction of errors by about 45.4% compared with the improved progressive polynomial calibration (PPC) method and the maximum current consumption of the SoC is 16 mA. PMID:23698271

Digital isothermal quantification of nucleic acids via simultaneous chemical initiation of recombinase polymerase amplification reactions on SlipChip.

PubMed

Shen, Feng; Davydova, Elena K; Du, Wenbin; Kreutz, Jason E; Piepenburg, Olaf; Ismagilov, Rustem F

2011-05-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However, it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipet loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false-positive results from preinitiation of the RPA amplification reaction before incubation were eliminated. End point fluorescence readout was used for "yes or no" digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37-42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications.

Digital Isothermal Quantification of Nucleic Acids via Simultaneous Chemical Initiation of Recombinase Polymerase Amplification Reactions on SlipChip

PubMed Central

Shen, Feng; Davydova, Elena K.; Du, Wenbin; Kreutz, Jason E.; Piepenburg, Olaf; Ismagilov, Rustem F.

2011-01-01

In this paper, digital quantitative detection of nucleic acids was achieved at the single-molecule level by chemical initiation of over one thousand sequence-specific, nanoliter, isothermal amplification reactions in parallel. Digital polymerase chain reaction (digital PCR), a method used for quantification of nucleic acids, counts the presence or absence of amplification of individual molecules. However it still requires temperature cycling, which is undesirable under resource-limited conditions. This makes isothermal methods for nucleic acid amplification, such as recombinase polymerase amplification (RPA), more attractive. A microfluidic digital RPA SlipChip is described here for simultaneous initiation of over one thousand nL-scale RPA reactions by adding a chemical initiator to each reaction compartment with a simple slipping step after instrument-free pipette loading. Two designs of the SlipChip, two-step slipping and one-step slipping, were validated using digital RPA. By using the digital RPA SlipChip, false positive results from pre-initiation of the RPA amplification reaction before incubation were eliminated. End-point fluorescence readout was used for “yes or no” digital quantification. The performance of digital RPA in a SlipChip was validated by amplifying and counting single molecules of the target nucleic acid, Methicillin-resistant Staphylococcus aureus (MRSA) genomic DNA. The digital RPA on SlipChip was also tolerant to fluctuations of the incubation temperature (37–42 °C), and its performance was comparable to digital PCR on the same SlipChip design. The digital RPA SlipChip provides a simple method to quantify nucleic acids without requiring thermal cycling or kinetic measurements, with potential applications in diagnostics and environmental monitoring under resource-limited settings. The ability to initiate thousands of chemical reactions in parallel on the nanoliter scale using solvent-resistant glass devices is likely to be useful for a broader range of applications. PMID:21476587

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Precision control of multiple quantum cascade lasers for calibration systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taubman, Matthew S., E-mail: Matthew.Taubman@pnnl.gov; Myers, Tanya L.; Pratt, Richard M.

We present a precision, 1-A, digitally interfaced current controller for quantum cascade lasers, with demonstrated temperature coefficients for continuous and 40-kHz full-depth square-wave modulated operation, of 1–2 ppm/ °C and 15 ppm/ °C, respectively. High precision digital to analog converters (DACs) together with an ultra-precision voltage reference produce highly stable, precision voltages, which are selected by a multiplexer (MUX) chip to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller, while ensuring protection of controller and all lasers during operation, standby,more » and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

Precision Control of Multiple Quantum Cascade Lasers for Calibration Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taubman, Matthew S.; Myers, Tanya L.; Pratt, Richard M.

We present a precision, digitally interfaced current controller for quantum cascade lasers, with demonstrated DC and modulated temperature coefficients of 1- 2 ppm/ºC and 15 ppm/ºC respectively. High linearity digital to analog converters (DACs) together with an ultra-precision voltage reference, produce highly stable, precision voltages. These are in turn selected by a low charge-injection multiplexer (MUX) chip, which are then used to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller while ensuring protection of controller and all lasersmore » during operation, standby and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

All-electronic droplet generation on-chip with real-time feedback control for EWOD digital microfluidics.

PubMed

Gong, Jian; Kim, Chang-Jin C J

2008-06-01

Electrowetting-on-dielectric (EWOD) actuation enables digital (or droplet) microfluidics where small packets of liquids are manipulated on a two-dimensional surface. Due to its mechanical simplicity and low energy consumption, EWOD holds particular promise for portable systems. To improve volume precision of the droplets, which is desired for quantitative applications such as biochemical assays, existing practices would require near-perfect device fabrication and operation conditions unless the droplets are generated under feedback control by an extra pump setup off of the chip. In this paper, we develop an all-electronic (i.e., no ancillary pumping) real-time feedback control of on-chip droplet generation. A fast voltage modulation, capacitance sensing, and discrete-time PID feedback controller are integrated on the operating electronic board. A significant improvement is obtained in the droplet volume uniformity, compared with an open loop control as well as the previous feedback control employing an external pump. Furthermore, this new capability empowers users to prescribe the droplet volume even below the previously considered minimum, allowing, for example, 1 : x (x < 1) mixing, in comparison to the previously considered n : m mixing (i.e., n and m unit droplets).

Micro flow-through PCR in a PMMA chip fabricated by KrF excimer laser.

PubMed

Yao, Liying; Liu, Baoan; Chen, Tao; Liu, Shibing; Zuo, Tiechuan

2005-09-01

As the third PCR technology, micro flow-through PCR chip can amplify DNA specifically in an exponential fashion in vitro. Nowadays many academies in the world have successfully amplified DNA using their own-made flow-through PCR chip. In this paper, the ablation principle of PMMA at 248 nm excimer laser was studied, then a PMMA based flow-through PCR chip with 20 cycles was fabricated by excimer laser at 19 kv and 18 mm/min. The chip was bonded together with another cover chip at 105( composite function)C, 160 N and 20 minutes. In the end, it was integrated with electrical thermal thin films and Pt 100 temperature sensors. The temperature controllers was built standard PID digital temperature controller, the temperature control precision was +/- 0.2( composite function)C. The temperature grads between the three temperature zones were 16.5 and 22.2( composite function)C respectively, the gaps between the temperature zones could realize heat insulation.

A 1-channel 3-band wide dynamic range compression chip for vibration transducer of implantable hearing aids.

PubMed

Kim, Dongwook; Seong, Kiwoong; Kim, Myoungnam; Cho, Jinho; Lee, Jyunghyun

2014-01-01

In this paper, a digital audio processing chip which uses a wide dynamic range compression (WDRC) algorithm is designed and implemented for implantable hearing aids system. The designed chip operates at a single voltage of 3.3V and drives a 16 bit parallel input and output at 32 kHz sample. The designed chip has 1-channel 3-band WDRC composed of a FIR filter bank, a level detector, and a compression part. To verify the performance of the designed chip, we measured the frequency separations of bands and compression gain control to reflect the hearing threshold level.

Digitally Controllable Current Amplifier and Current Conveyors in Practical Application of Controllable Frequency Filter

NASA Astrophysics Data System (ADS)

Polak, Josef; Jerabek, Jan; Langhammer, Lukas; Sotner, Roman; Dvorak, Jan; Panek, David

2016-07-01

This paper presents the simulations results in comparison with the measured results of the practical realization of the multifunctional second order frequency filter with a Digitally Adjustable Current Amplifier (DACA) and two Dual-Output Controllable Current Conveyors (CCCII +/-). This filter is designed for use in current mode. The filter was designed of the single input multiple outputs (SIMO) type, therefore it has only one input and three outputs with individual filtering functions. DACA element used in a newly proposed circuit is present in form of an integrated chip and the current conveyors are implemented using the Universal Current Conveyor (UCC) chip with designation UCC-N1B. Proposed frequency filter enables independent control of the pole frequency using parameters of two current conveyors and also independent control of the quality factor by change of a current gain of DACA.

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

NASA Technical Reports Server (NTRS)

Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.;

Time of flight system on a chip

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas P. (Inventor)

2006-01-01

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Self-powered integrated microfluidic point-of-care low-cost enabling (SIMPLE) chip

PubMed Central

Yeh, Erh-Chia; Fu, Chi-Cheng; Hu, Lucy; Thakur, Rohan; Feng, Jeffrey; Lee, Luke P.

2017-01-01

Portable, low-cost, and quantitative nucleic acid detection is desirable for point-of-care diagnostics; however, current polymerase chain reaction testing often requires time-consuming multiple steps and costly equipment. We report an integrated microfluidic diagnostic device capable of on-site quantitative nucleic acid detection directly from the blood without separate sample preparation steps. First, we prepatterned the amplification initiator [magnesium acetate (MgOAc)] on the chip to enable digital nucleic acid amplification. Second, a simplified sample preparation step is demonstrated, where the plasma is separated autonomously into 224 microwells (100 nl per well) without any hemolysis. Furthermore, self-powered microfluidic pumping without any external pumps, controllers, or power sources is accomplished by an integrated vacuum battery on the chip. This simple chip allows rapid quantitative digital nucleic acid detection directly from human blood samples (10 to 105 copies of methicillin-resistant Staphylococcus aureus DNA per microliter, ~30 min, via isothermal recombinase polymerase amplification). These autonomous, portable, lab-on-chip technologies provide promising foundations for future low-cost molecular diagnostic assays. PMID:28345028

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems.

PubMed

Wang, Cheng-Pin; Lee, Shuenn-Yuh; Lai, Wei-Chih

2013-01-01

This paper presents a low-power wireless ECG acquisition system-on-chip (SoC), including an RF front-end circuit, a power unit, an analog front-end circuit, and a digital circuitry. The proposed RF front-end circuit can provide the amplitude shift keying demodulation and distance to digital conversion to accurately receive the data from the reader. The received data will wake up the power unit to provide the required supply voltages of analog front-end (AFE) and digital circuitry. The AFE, including a pre-amplifier, an analog filter, a post-amplifier, and an analog-to-digital converter, is used for the ECG acquisition. Moreover, the EPC Class I Gen 2 UHF standard is employed in the digital circuitry for the handshaking of communication and the control of the system. The proposed SoC has been implemented in 0.18-µm standard CMOS process and the measured results reveal the communication is compatible to the RFID protocol. The average power consumption for the operating chip is 12 µW. Using a Sony PR44 battery to the supply power (605mAh@1.4V), the RFID tag SoC operates continuously for about 50,000 hours (>5 years), which is appropriate for wireless wearable ECG monitoring systems.

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Picoliter Well Array Chip-Based Digital Recombinase Polymerase Amplification for Absolute Quantification of Nucleic Acids.

PubMed

Li, Zhao; Liu, Yong; Wei, Qingquan; Liu, Yuanjie; Liu, Wenwen; Zhang, Xuelian; Yu, Yude

2016-01-01

Absolute, precise quantification methods expand the scope of nucleic acids research and have many practical applications. Digital polymerase chain reaction (dPCR) is a powerful method for nucleic acid detection and absolute quantification. However, it requires thermal cycling and accurate temperature control, which are difficult in resource-limited conditions. Accordingly, isothermal methods, such as recombinase polymerase amplification (RPA), are more attractive. We developed a picoliter well array (PWA) chip with 27,000 consistently sized picoliter reactions (314 pL) for isothermal DNA quantification using digital RPA (dRPA) at 39°C. Sample loading using a scraping liquid blade was simple, fast, and required small reagent volumes (i.e., <20 μL). Passivating the chip surface using a methoxy-PEG-silane agent effectively eliminated cross-contamination during dRPA. Our creative optical design enabled wide-field fluorescence imaging in situ and both end-point and real-time analyses of picoliter wells in a 6-cm(2) area. It was not necessary to use scan shooting and stitch serial small images together. Using this method, we quantified serial dilutions of a Listeria monocytogenes gDNA stock solution from 9 × 10(-1) to 4 × 10(-3) copies per well with an average error of less than 11% (N = 15). Overall dRPA-on-chip processing required less than 30 min, which was a 4-fold decrease compared to dPCR, requiring approximately 2 h. dRPA on the PWA chip provides a simple and highly sensitive method to quantify nucleic acids without thermal cycling or precise micropump/microvalve control. It has applications in fast field analysis and critical clinical diagnostics under resource-limited settings.

Picoliter Well Array Chip-Based Digital Recombinase Polymerase Amplification for Absolute Quantification of Nucleic Acids

PubMed Central

Li, Zhao; Liu, Yong; Wei, Qingquan; Liu, Yuanjie; Liu, Wenwen; Zhang, Xuelian; Yu, Yude

2016-01-01

Absolute, precise quantification methods expand the scope of nucleic acids research and have many practical applications. Digital polymerase chain reaction (dPCR) is a powerful method for nucleic acid detection and absolute quantification. However, it requires thermal cycling and accurate temperature control, which are difficult in resource-limited conditions. Accordingly, isothermal methods, such as recombinase polymerase amplification (RPA), are more attractive. We developed a picoliter well array (PWA) chip with 27,000 consistently sized picoliter reactions (314 pL) for isothermal DNA quantification using digital RPA (dRPA) at 39°C. Sample loading using a scraping liquid blade was simple, fast, and required small reagent volumes (i.e., <20 μL). Passivating the chip surface using a methoxy-PEG-silane agent effectively eliminated cross-contamination during dRPA. Our creative optical design enabled wide-field fluorescence imaging in situ and both end-point and real-time analyses of picoliter wells in a 6-cm2 area. It was not necessary to use scan shooting and stitch serial small images together. Using this method, we quantified serial dilutions of a Listeria monocytogenes gDNA stock solution from 9 × 10-1 to 4 × 10-3 copies per well with an average error of less than 11% (N = 15). Overall dRPA-on-chip processing required less than 30 min, which was a 4-fold decrease compared to dPCR, requiring approximately 2 h. dRPA on the PWA chip provides a simple and highly sensitive method to quantify nucleic acids without thermal cycling or precise micropump/microvalve control. It has applications in fast field analysis and critical clinical diagnostics under resource-limited settings. PMID:27074005

Packet Controller For Wireless Headset

NASA Technical Reports Server (NTRS)

Christensen, Kurt K.; Swanson, Richard J.

1993-01-01

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Single cell digital polymerase chain reaction on self-priming compartmentalization chip

PubMed Central

Zhu, Qiangyuan; Qiu, Lin; Xu, Yanan; Li, Guang; Mu, Ying

2017-01-01

Single cell analysis provides a new framework for understanding biology and disease, however, an absolute quantification of single cell gene expression still faces many challenges. Microfluidic digital polymerase chain reaction (PCR) provides a unique method to absolutely quantify the single cell gene expression, but only limited devices are developed to analyze a single cell with detection variation. This paper describes a self-priming compartmentalization (SPC) microfluidic digital polymerase chain reaction chip being capable of performing single molecule amplification from single cell. The chip can be used to detect four single cells simultaneously with 85% of sample digitization. With the optimized protocol for the SPC chip, we first tested the ability, precision, and sensitivity of our SPC digital PCR chip by assessing β-actin DNA gene expression in 1, 10, 100, and 1000 cells. And the reproducibility of the SPC chip is evaluated by testing 18S rRNA of single cells with 1.6%–4.6% of coefficient of variation. At last, by detecting the lung cancer related genes, PLAU gene expression of A549 cells at the single cell level, the single cell heterogeneity was demonstrated. So, with the power-free, valve-free SPC chip, the gene copy number of single cells can be quantified absolutely with higher sensitivity, reduced labor time, and reagent. We expect that this chip will enable new studies for biology and disease. PMID:28191267

Single cell digital polymerase chain reaction on self-priming compartmentalization chip.

PubMed

Zhu, Qiangyuan; Qiu, Lin; Xu, Yanan; Li, Guang; Mu, Ying

2017-01-01

Single cell analysis provides a new framework for understanding biology and disease, however, an absolute quantification of single cell gene expression still faces many challenges. Microfluidic digital polymerase chain reaction (PCR) provides a unique method to absolutely quantify the single cell gene expression, but only limited devices are developed to analyze a single cell with detection variation. This paper describes a self-priming compartmentalization (SPC) microfluidic digital polymerase chain reaction chip being capable of performing single molecule amplification from single cell. The chip can be used to detect four single cells simultaneously with 85% of sample digitization. With the optimized protocol for the SPC chip, we first tested the ability, precision, and sensitivity of our SPC digital PCR chip by assessing β-actin DNA gene expression in 1, 10, 100, and 1000 cells. And the reproducibility of the SPC chip is evaluated by testing 18S rRNA of single cells with 1.6%-4.6% of coefficient of variation. At last, by detecting the lung cancer related genes, PLAU gene expression of A549 cells at the single cell level, the single cell heterogeneity was demonstrated. So, with the power-free, valve-free SPC chip, the gene copy number of single cells can be quantified absolutely with higher sensitivity, reduced labor time, and reagent. We expect that this chip will enable new studies for biology and disease.

Digital characterization of a neuromorphic IRFPA

NASA Astrophysics Data System (ADS)

Caulfield, John T.; Fisher, John; Zadnik, Jerome A.; Mak, Ernest S.; Scribner, Dean A.

1995-05-01

This paper reports on the performance of the Neuromorphic IRFPA, the first IRFPA designed and fabricated to conduct temporal and spatial processing on the focal plane. The Neuromorphic IRFPA's unique on-chip processing capability can perform retina-like functions such as lateral inhibition and contrast enhancement, spatial and temporal filtering, image compression and edge enhancement, and logarithmic response. Previously, all evaluations of the Neuromorphic IRFPA camera have been performed on the analog video output. In the work leading up to this paper, the Neuromorphic was integrated to a digital recorder to collect quantitative laboratory and field data. This paper describes the operation and characterization of specific on-chip processes such as spatial and temporal kernel size control. The use of Neuromorphic on-chip processing in future IRFPAs is analyzed as applied to improving SNR via adaptive nonuniformity, charge handling, and dynamic range problems.

Research on control law accelerator of digital signal process chip TMS320F28035 for real-time data acquisition and processing

NASA Astrophysics Data System (ADS)

Zhao, Shuangle; Zhang, Xueyi; Sun, Shengli; Wang, Xudong

2017-08-01

TI C2000 series digital signal process (DSP) chip has been widely used in electrical engineering, measurement and control, communications and other professional fields, DSP TMS320F28035 is one of the most representative of a kind. When using the DSP program, need data acquisition and data processing, and if the use of common mode C or assembly language programming, the program sequence, analogue-to-digital (AD) converter cannot be real-time acquisition, often missing a lot of data. The control low accelerator (CLA) processor can run in parallel with the main central processing unit (CPU), and the frequency is consistent with the main CPU, and has the function of floating point operations. Therefore, the CLA coprocessor is used in the program, and the CLA kernel is responsible for data processing. The main CPU is responsible for the AD conversion. The advantage of this method is to reduce the time of data processing and realize the real-time performance of data acquisition.

Multi-beam and single-chip LIDAR with discrete beam steering by digital micromirror device

NASA Astrophysics Data System (ADS)

Rodriguez, Joshua; Smith, Braden; Hellman, Brandon; Gin, Adley; Espinoza, Alonzo; Takashima, Yuzuru

2018-02-01

A novel Digital Micromirror Device (DMD) based beam steering enables a single chip Light Detection and Ranging (LIDAR) system for discrete scanning points. We present increasing number of scanning point by using multiple laser diodes for Multi-beam and Single-chip DMD-based LIDAR.

Batteryless Electroencephalography (EEG): Subthreshold Voltage System-on-a-Chip (SoC) Design for Neurophysiological Measurement

DTIC Science & Technology

2015-03-01

example, be harvested via thermoelectric coupling requiring only a 1 °C temperature gradient (supplied by the human scalp at ambient room...controller. The amplifier chain will consist of a differential low-noise amplifier (LNA) with digitally modulated , voltage-offset control and a variable...result in decreased vertical resolution of the digitized signal, even in conjunction with the VOC/VGA modulation described above. Figure 4 shows

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Beigbeder, C.; Bernier, R.; Breton, D.; Bonneaud, G.; Caceres, T.; Chase, R.; Chauveau, J.; Del Buono, L.; Dohou, F.; Ducorps, A.; Gastaldi, F.; Genat, J. F.; Hrisoho, A.; Imbert, P.; Lebbolo, H.; Matricon, P.; Oxoby, G.; Renard, C.; Roos, L.; Sen, S.; Thiebaux, C.; Truong, K.; Tocut, V.; Vasileiadis, G.; Va'Vra, J.; Verderi, M.; Warner, D.; Wilson, R. J.; Wormser, G.; Zhang, B.; Zomer, F.

2000-12-01

Recent results from the Front-End electronics of the Detector of Internally Reflected Cerenkov light (DIRC) for the BaBar experiment at SLAC (Stanford, USA) are presented. It measures to better than 1 ns the arrival time of Cerenkov photoelectrons detected in a 11000 phototubes array and their amplitude spectra. It mainly comprises 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom digital time to digital chips (TDC) for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected front up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of the pre-production chips are presented, as well as system tests.

A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

PubMed Central

Huang, Che-Wei; Huang, Yu-Jie; Lu, Shey-Shi; Lin, Chih-Ting

2012-01-01

A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH) range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

Self-digitization microfluidic chip for absolute quantification of mRNA in single cells.

PubMed

Thompson, Alison M; Gansen, Alexander; Paguirigan, Amy L; Kreutz, Jason E; Radich, Jerald P; Chiu, Daniel T

2014-12-16

Quantification of mRNA in single cells provides direct insight into how intercellular heterogeneity plays a role in disease progression and outcomes. Quantitative polymerase chain reaction (qPCR), the current gold standard for evaluating gene expression, is insufficient for providing absolute measurement of single-cell mRNA transcript abundance. Challenges include difficulties in handling small sample volumes and the high variability in measurements. Microfluidic digital PCR provides far better sensitivity for minute quantities of genetic material, but the typical format of this assay does not allow for counting of the absolute number of mRNA transcripts samples taken from single cells. Furthermore, a large fraction of the sample is often lost during sample handling in microfluidic digital PCR. Here, we report the absolute quantification of single-cell mRNA transcripts by digital, one-step reverse transcription PCR in a simple microfluidic array device called the self-digitization (SD) chip. By performing the reverse transcription step in digitized volumes, we find that the assay exhibits a linear signal across a wide range of total RNA concentrations and agrees well with standard curve qPCR. The SD chip is found to digitize a high percentage (86.7%) of the sample for single-cell experiments. Moreover, quantification of transferrin receptor mRNA in single cells agrees well with single-molecule fluorescence in situ hybridization experiments. The SD platform for absolute quantification of single-cell mRNA can be optimized for other genes and may be useful as an independent control method for the validation of mRNA quantification techniques.

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

12-bit 32 channel 500 MS/s low-latency ADC for particle accelerators real-time control

NASA Astrophysics Data System (ADS)

Karnitski, Anton; Baranauskas, Dalius; Zelenin, Denis; Baranauskas, Gytis; Zhankevich, Alexander; Gill, Chris

2017-09-01

Particle beam control systems require real-time low latency digital feedback with high linearity and dynamic range. Densely packed electronic systems employ high performance multichannel digitizers causing excessive heat dissipation. Therefore, low power dissipation is another critical requirement for these digitizers. A described 12-bit 500 MS/s ADC employs a sub-ranging architecture based on a merged sample & hold circuit, a residue C-DAC and a shared 6-bit flash core ADC. The core ADC provides a sequential coarse and fine digitization featuring a latency of two clock cycles. The ADC is implemented in a 28 nm CMOS process and consumes 4 mW of power per channel from a 0.9 V supply (interfacing and peripheral circuits are excluded). Reduced power consumption and small on-chip area permits the implementation of 32 ADC channels on a 10.7 mm2 chip. The ADC includes a JESD204B standard compliant output data interface operated at the 7.5 Gbps/ch rate. To minimize the data interface related time latency, a special feature permitting to bypass the JESD204B interface is built in. DoE Phase I Award Number: DE-SC0017213.

Application of the ANNA neural network chip to high-speed character recognition.

PubMed

Sackinger, E; Boser, B E; Bromley, J; Lecun, Y; Jackel, L D

1992-01-01

A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision.

Versatile all-digital time interval measuring system

NASA Astrophysics Data System (ADS)

Vyhlidal, David; Cech, Miroslav

2011-06-01

This paper describes a design and performance of a versatile all-digital time interval measuring system. The measurement method is based on an interpolation principle. In this principle the time interval is first roughly digitized by a coarse counter driven by a high stability reference clock and the fractions between the clock periods are measured by two Time-to-Digital Converter chips TDC-GPX manufactured by Acam messelectronic. Control circuits allow programmable customization of the system to satisfy many applications such as laser range finding, event counting, or time-of-flight measurements in various physics experiments. The system has two reference clocks inputs and two independent channels for measuring start and stop events. Only one 40 MHz reference is required for the measurement. The second reference can be, for example, 1 PPS (Pulse per Second) signal from a GPS (Global Positioning System) to time tag events. Time intervals are measured using the highest resolution mode of the TDC-GPX chips. The resolution of each chip is software programmable and is PLL (Phase Locked Loop) stabilized against temperature and voltage variations. The system can achieve a timing resolution better than 15 ps rms with up to 90 kHz repetition rate. The time interval measurement range is from 0 ps up to 1 second. The power consumption of the whole system is 18 W including an embedded computer board and an LCD (Liquid Crystal Display) screen. The embedded computer controls the whole system, collects and evaluates measurement data and with the display provides a user interface. The system is implemented using commercially available components.

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim Farah, Fahim Farah; Deptuch, Grzegorz W.; Hoff, James R.

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array withoutmore » any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.« less

Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

NASA Astrophysics Data System (ADS)

Fahim, Farah; Deptuch, Grzegorz W.; Hoff, James R.; Mohseni, Hooman

2015-08-01

The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Picoradio: Communication/Computation Piconodes for Sensor Networks

DTIC Science & Technology

2003-01-02

diagram of PicoNode III, or Quark node. It is made from two custom chips, Strange RF and Charm digital processor , and is complemented by a set of...the chipset comprising of Strange (analog OOK transceiver) and Charm (digital processor ) chips. 44 Figure 33: System block diagram of the Quark node...19 2.B PICONODE II - TWO-CHIP PICONODE IMPLEMENTATION ......................................... 21 2.B.1 Baseband processor (BBP

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

Theoretical design and analysis of multivolume digital assays with wide dynamic range validated experimentally with microfluidic digital PCR.

PubMed

Kreutz, Jason E; Munson, Todd; Huynh, Toan; Shen, Feng; Du, Wenbin; Ismagilov, Rustem F

2011-11-01

This paper presents a protocol using theoretical methods and free software to design and analyze multivolume digital PCR (MV digital PCR) devices; the theory and software are also applicable to design and analysis of dilution series in digital PCR. MV digital PCR minimizes the total number of wells required for "digital" (single molecule) measurements while maintaining high dynamic range and high resolution. In some examples, multivolume designs with fewer than 200 total wells are predicted to provide dynamic range with 5-fold resolution similar to that of single-volume designs requiring 12,000 wells. Mathematical techniques were utilized and expanded to maximize the information obtained from each experiment and to quantify performance of devices and were experimentally validated using the SlipChip platform. MV digital PCR was demonstrated to perform reliably, and results from wells of different volumes agreed with one another. No artifacts due to different surface-to-volume ratios were observed, and single molecule amplification in volumes ranging from 1 to 125 nL was self-consistent. The device presented here was designed to meet the testing requirements for measuring clinically relevant levels of HIV viral load at the point-of-care (in plasma, <500 molecules/mL to >1,000,000 molecules/mL), and the predicted resolution and dynamic range was experimentally validated using a control sequence of DNA. This approach simplifies digital PCR experiments, saves space, and thus enables multiplexing using separate areas for each sample on one chip, and facilitates the development of new high-performance diagnostic tools for resource-limited applications. The theory and software presented here are general and are applicable to designing and analyzing other digital analytical platforms including digital immunoassays and digital bacterial analysis. It is not limited to SlipChip and could also be useful for the design of systems on platforms including valve-based and droplet-based platforms. In a separate publication by Shen et al. (J. Am. Chem. Soc., 2011, DOI: 10.1021/ja2060116), this approach is used to design and test digital RT-PCR devices for quantifying RNA.

Disposable world-to-chip interface for digital microfluidics

DOEpatents

Van Dam, R. Michael; Shah, Gaurav; Keng, Pei-Yuin

2017-05-16

The present disclosure sets forth incorporating microfluidic chips interfaces for use with digital microfluidic processes. Methods and devices according to the present disclosure utilize compact, integrated platforms that interface with a chip upstream and downstream of the reaction, as well as between intermediate reaction steps if needed. In some embodiments these interfaces are automated, including automation of a multiple reagent process. Various reagent delivery systems and methods are also disclosed.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

NASA Astrophysics Data System (ADS)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Manually Operatable On-Chip Bistable Pneumatic Microstructures for Microfluidic Manipulations

PubMed Central

Chen, A.; Pan, T.

2014-01-01

Bistable microvalves are of particular interest because of their distinct nature requiring energy consumption only during the transition between the open and closed states. This characteristic can be highly advantageous in reducing the number of external inputs and the complexity of control circuitries for microfluidic devices as contemporary lab-on-a-chip platforms are transferring from research settings to low-resource environments with high integratability and small form factor. In this paper, we first present manually operatable, on-chip bistable pneumatic microstructures (BPM) for microfluidic manipulation. The structural design and operation of the BPM devices can be readily integrated into any pneumatically powered microfluidic network consisting of pneumatic and fluidic channels. It is mainly comprised of a vacuum activation chamber (VAC) and a pressure release chamber (PRC), which users have direct control through finger pressing to switch between bistable vacuum state (VS) or atmospheric state (AS). We have integrated multiple BPM devices into a 4-to-1 microfluidic multiplexor to demonstrate on-chip digital flow switching from different sources. Furthermore, we have shown its clinical relevance in a point-of-care diagnostic chip that process blood samples to identify the distinct blood types (A/B/O) on chip. PMID:25007840

Manually operatable on-chip bistable pneumatic microstructures for microfluidic manipulations.

PubMed

Chen, Arnold; Pan, Tingrui

2014-09-07

Bistable microvalves are of particular interest because of their distinct nature of requiring energy consumption only during the transition between the open and closed states. This characteristic can be highly advantageous in reducing the number of external inputs and the complexity of control circuitries since microfluidic devices as contemporary lab-on-a-chip platforms are transferring from research settings to low-resource environments with high integrability and a small form factor. In this paper, we first present manually operatable, on-chip bistable pneumatic microstructures (BPMs) for microfluidic manipulation. The structural design and operation of the BPM devices can be readily integrated into any pneumatically powered microfluidic network consisting of pneumatic and fluidic channels. It is mainly composed of a vacuum activation chamber (VAC) and a pressure release chamber (PRC), of which users have direct control through finger pressing to switch either to the bistable vacuum state (VS) or the atmospheric state (AS). We have integrated multiple BPM devices into a 4-to-1 microfluidic multiplexor to demonstrate on-chip digital flow switching from different sources. Furthermore, we have shown its clinical relevance in a point-of-care diagnostic chip that processes blood samples to identify the distinct blood types (A/B/O) on-chip.

A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

PubMed

Chen, Jiann-Jong; Kung, Che-Min

2010-09-01

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

A scalable self-priming fractal branching microchannel net chip for digital PCR.

PubMed

Zhu, Qiangyuan; Xu, Yanan; Qiu, Lin; Ma, Congcong; Yu, Bingwen; Song, Qi; Jin, Wei; Jin, Qinhan; Liu, Jinyu; Mu, Ying

2017-05-02

As an absolute quantification method at the single-molecule level, digital PCR has been widely used in many bioresearch fields, such as next generation sequencing, single cell analysis, gene editing detection and so on. However, existing digital PCR methods still have some disadvantages, including high cost, sample loss, and complicated operation. In this work, we develop an exquisite scalable self-priming fractal branching microchannel net digital PCR chip. This chip with a special design inspired by natural fractal-tree systems has an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods. A special 10 nm nano-waterproof layer was created to prevent the solution from evaporating. A vacuum pre-packaging method called self-priming reagent introduction is used to passively drive the reagent flow into the microchannel nets, so that this chip can realize sequential reagent loading and isolation within a couple of minutes, which is very suitable for point-of-care detection. When the number of positive microwells stays in the range of 100 to 4000, the relative uncertainty is below 5%, which means that one panel can detect an average of 101 to 15 374 molecules by the Poisson distribution. This chip is proved to have an excellent ability for single molecule detection and quantification of low expression of hHF-MSC stem cell markers. Due to its potential for high throughput, high density, low cost, lack of sample and reagent loss, self-priming even compartmentalization and simple operation, we envision that this device will significantly expand and extend the application range of digital PCR involving rare samples, liquid biopsy detection and point-of-care detection with higher sensitivity and accuracy.

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Low-cost TDRSS communications for NASA's long duration balloon project

NASA Technical Reports Server (NTRS)

Israel, David J.

1993-01-01

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

A three-channel LED driver with single line transportation technique

NASA Astrophysics Data System (ADS)

Yu, Caideng; Du, Yiying; Jiang, Qiao; Zhou, Yun; Lv, Jian

2012-10-01

Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen' colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.

A silicon central pattern generator controls locomotion in vivo.

PubMed

Vogelstein, R J; Tenore, F; Guevremont, L; Etienne-Cummings, R; Mushahwar, V K

2008-09-01

We present a neuromorphic silicon chip that emulates the activity of the biological spinal central pattern generator (CPG) and creates locomotor patterns to support walking. The chip implements ten integrate-and-fire silicon neurons and 190 programmable digital-to-analog converters that act as synapses. This architecture allows for each neuron to make synaptic connections to any of the other neurons as well as to any of eight external input signals and one tonic bias input. The chip's functionality is confirmed by a series of experiments in which it controls the motor output of a paralyzed animal in real-time and enables it to walk along a three-meter platform. The walking is controlled under closed-loop conditions with the aide of sensory feedback that is recorded from the animal's legs and fed into the silicon CPG. Although we and others have previously described biomimetic silicon locomotor control systems for robots, this is the first demonstration of a neuromorphic device that can replace some functions of the central nervous system in vivo.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

A 32-channel fully implantable wireless neurosensor for simultaneous recording from two cortical regions.

PubMed

Aceros, Juan; Yin, Ming; Borton, David A; Patterson, William R; Nurmikko, Arto V

2011-01-01

We present a fully implantable, wireless, neurosensor for multiple-location neural interface applications. The device integrates two independent 16-channel intracortical microelectrode arrays and can simultaneously acquire 32 channels of broadband neural data from two separate cortical areas. The system-on-chip implantable sensor is built on a flexible Kapton polymer substrate and incorporates three very low power subunits: two cortical subunits connected to a common subcutaneous subunit. Each cortical subunit has an ultra-low power 16-channel preamplifier and multiplexer integrated onto a cortical microelectrode array. The subcutaneous epicranial unit has an inductively coupled power supply, two analog-to-digital converters, a low power digital controller chip, and microlaser-based infrared telemetry. The entire system is soft encapsulated with biocompatible flexible materials for in vivo applications. Broadband neural data is conditioned, amplified, and analog multiplexed by each of the cortical subunits and passed to the subcutaneous component, where it is digitized and combined with synchronization data and wirelessly transmitted transcutaneously using high speed infrared telemetry.

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

NASA Astrophysics Data System (ADS)

Park, Chester Sungchung; Park, Sungkyung

2018-07-01

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

Design and integration of an all-in-one biomicrofluidic chip

PubMed Central

Liu, Liyu; Cao, Wenbin; Wu, Jingbo; Wen, Weijia; Chang, Donald Choy; Sheng, Ping

2008-01-01

We demonstrate a highly integrated microfluidic chip with the function of DNA amplification. The integrated chip combines giant electrorheological-fluid actuated micromixer and micropump with a microheater array, all formed using soft lithography. Internal functional components are based on polydimethylsiloxane (PDMS) and silver∕carbon black-PDMS composites. The system has the advantages of small size with a high degree of integration, high polymerase chain reaction efficiency, digital control and simple fabrication at low cost. This integration approach shows promise for a broad range of applications in chemical synthesis and biological sensing∕analysis, as different components can be combined to target desired functionalities, with flexible designs of different microchips easily realizable through soft lithography. PMID:19693370

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

A droplet-to-digital (D2D) microfluidic device for single cell assays.

PubMed

Shih, Steve C C; Gach, Philip C; Sustarich, Jess; Simmons, Blake A; Adams, Paul D; Singh, Seema; Singh, Anup K

2015-01-07

We have developed a new hybrid droplet-to-digital microfluidic platform (D2D) that integrates droplet-in-channel microfluidics with digital microfluidics (DMF) for performing multi-step assays. This D2D platform combines the strengths of the two formats-droplets-in-channel for facile generation of droplets containing single cells, and DMF for on-demand manipulation of droplets including control of different droplet volumes (pL-μL), creation of a dilution series of ionic liquid (IL), and parallel single cell culturing and analysis for IL toxicity screening. This D2D device also allows for automated analysis that includes a feedback-controlled system for merging and splitting of droplets to add reagents, an integrated Peltier element for parallel cell culture at optimum temperature, and an impedance sensing mechanism to control the flow rate for droplet generation and preventing droplet evaporation. Droplet-in-channel is well-suited for encapsulation of single cells as it allows the careful manipulation of flow rates of aqueous phase containing cells and oil to optimize encapsulation. Once single cell containing droplets are generated, they are transferred to a DMF chip via a capillary where they are merged with droplets containing IL and cultured at 30 °C. The DMF chip, in addition to permitting cell culture and reagent (ionic liquid/salt) addition, also allows recovery of individual droplets for off-chip analysis such as further culturing and measurement of ethanol production. The D2D chip was used to evaluate the effect of IL/salt type (four types: NaOAc, NaCl, [C2mim] [OAc], [C2mim] [Cl]) and concentration (four concentrations: 0, 37.5, 75, 150 mM) on the growth kinetics and ethanol production of yeast and as expected, increasing IL concentration led to lower biomass and ethanol production. Specifically, [C2mim] [OAc] had inhibitory effects on yeast growth at concentrations 75 and 150 mM and significantly reduced their ethanol production compared to cells grown in other ILs/salts. The growth curve trends obtained by D2D matched conventional yeast culturing in microtiter wells, validating the D2D platform. We believe that our approach represents a generic platform for multi-step biochemical assays such as drug screening, digital PCR, enzyme assays, immunoassays and cell-based assays.

A finite state machine read-out chip for integrated surface acoustic wave sensors

NASA Astrophysics Data System (ADS)

Rakshit, Sambarta; Iliadis, Agis A.

2015-01-01

A finite state machine based integrated sensor circuit suitable for the read-out module of a monolithically integrated SAW sensor on Si is reported. The primary sensor closed loop consists of a voltage controlled oscillator (VCO), a peak detecting comparator, a finite state machine (FSM), and a monolithically integrated SAW sensor device. The output of the system oscillates within a narrow voltage range that correlates with the SAW pass-band response. The period of oscillation is of the order of the SAW phase delay. We use timing information from the FSM to convert SAW phase delay to an on-chip 10 bit digital output operating on the principle of time to digital conversion (TDC). The control inputs of this digital conversion block are generated by a second finite state machine operating under a divided system clock. The average output varies with changes in SAW center frequency, thus tracking mass sensing events in real time. Based on measured VCO gain of 16 MHz/V our system will convert a 10 kHz SAW frequency shift to a corresponding mean voltage shift of 0.7 mV. A corresponding shift in phase delay is converted to a one or two bit shift in the TDC output code. The system can handle alternate SAW center frequencies and group delays simply by adjusting the VCO control and TDC delay control inputs. Because of frequency to voltage and phase to digital conversion, this topology does not require external frequency counter setups and is uniquely suitable for full monolithic integration of autonomous sensor systems and tags.

Multiplexed quantification of nucleic acids with large dynamic range using multivolume digital RT-PCR on a rotational SlipChip tested with HIV and hepatitis C viral load.

PubMed

Shen, Feng; Sun, Bing; Kreutz, Jason E; Davydova, Elena K; Du, Wenbin; Reddy, Poluru L; Joseph, Loren J; Ismagilov, Rustem F

2011-11-09

In this paper, we are working toward a problem of great importance to global health: determination of viral HIV and hepatitis C (HCV) loads under point-of-care and resource limited settings. While antiretroviral treatments are becoming widely available, viral load must be evaluated at regular intervals to prevent the spread of drug resistance and requires a quantitative measurement of RNA concentration over a wide dynamic range (from 50 up to 10(6) molecules/mL for HIV and up to 10(8) molecules/mL for HCV). "Digital" single molecule measurements are attractive for quantification, but the dynamic range of such systems is typically limited or requires excessive numbers of compartments. Here we designed and tested two microfluidic rotational SlipChips to perform multivolume digital RT-PCR (MV digital RT-PCR) experiments with large and tunable dynamic range. These designs were characterized using synthetic control RNA and validated with HIV viral RNA and HCV control viral RNA. The first design contained 160 wells of each of four volumes (125 nL, 25 nL, 5 nL, and 1 nL) to achieve a dynamic range of 5.2 × 10(2) to 4.0 × 10(6) molecules/mL at 3-fold resolution. The second design tested the flexibility of this approach, and further expanded it to allow for multiplexing while maintaining a large dynamic range by adding additional wells with volumes of 0.2 nL and 625 nL and dividing the SlipChip into five regions to analyze five samples each at a dynamic range of 1.8 × 10(3) to 1.2 × 10(7) molecules/mL at 3-fold resolution. No evidence of cross-contamination was observed. The multiplexed SlipChip can be used to analyze a single sample at a dynamic range of 1.7 × 10(2) to 2.0 × 10(7) molecules/mL at 3-fold resolution with limit of detection of 40 molecules/mL. HIV viral RNA purified from clinical samples were tested on the SlipChip, and viral load results were self-consistent and in good agreement with results determined using the Roche COBAS AmpliPrep/COBAS TaqMan HIV-1 Test. With further validation, this SlipChip should become useful to precisely quantify viral HIV and HCV RNA for high-performance diagnostics in resource-limited settings. These microfluidic designs should also be valuable for other diagnostic and research applications, including detecting rare cells and rare mutations, prenatal diagnostics, monitoring residual disease, and quantifying copy number variation and gene expression patterns. The theory for the design and analysis of multivolume digital PCR experiments is presented in other work by Kreutz et al.

An Implantable RFID Sensor Tag toward Continuous Glucose Monitoring.

PubMed

Xiao, Zhibin; Tan, Xi; Chen, Xianliang; Chen, Sizheng; Zhang, Zijian; Zhang, Hualei; Wang, Junyu; Huang, Yue; Zhang, Peng; Zheng, Lirong; Min, Hao

2015-05-01

This paper presents a wirelessly powered implantable electrochemical sensor tag for continuous blood glucose monitoring. The system is remotely powered by a 13.56-MHz inductive link and utilizes an ISO 15693 radio frequency identification (RFID) standard for communication. This paper provides reliable and accurate measurement for changing glucose level. The sensor tag employs a long-term glucose sensor, a winding ferrite antenna, an RFID front-end, a potentiostat, a 10-bit sigma-delta analog to digital converter, an on-chip temperature sensor, and a digital baseband for protocol processing and control. A high-frequency external reader is used to power, command, and configure the sensor tag. The only off-chip support circuitry required is a tuned antenna and a glucose microsensor. The integrated chip fabricated in SMIC 0.13-μm CMOS process occupies an area of 1.2 mm ×2 mm and consumes 50 μW. The power sensitivity of the whole system is -4 dBm. The sensor tag achieves a measured glucose range of 0-30 mM with a sensitivity of 0.75 nA/mM.

Design of integrated eye tracker-display device for head mounted systems

NASA Astrophysics Data System (ADS)

David, Y.; Apter, B.; Thirer, N.; Baal-Zedaka, I.; Efron, U.

2009-08-01

We propose an Eye Tracker/Display system, based on a novel, dual function device termed ETD, which allows sharing the optical paths of the Eye tracker and the display and on-chip processing. The proposed ETD design is based on a CMOS chip combining a Liquid-Crystal-on-Silicon (LCoS) micro-display technology with near infrared (NIR) Active Pixel Sensor imager. The ET operation allows capturing the Near IR (NIR) light, back-reflected from the eye's retina. The retinal image is then used for the detection of the current direction of eye's gaze. The design of the eye tracking imager is based on the "deep p-well" pixel technology, providing low crosstalk while shielding the active pixel circuitry, which serves the imaging and the display drivers, from the photo charges generated in the substrate. The use of the ETD in the HMD Design enables a very compact design suitable for Smart Goggle applications. A preliminary optical, electronic and digital design of the goggle and its associated ETD chip and digital control, are presented.

Design and Implement of Low Ripple and Quasi-digital Power Supply

NASA Astrophysics Data System (ADS)

Xiangli, Li; Yanjun, Wei; Hanhong, Qi; Yan, Ma

A switch linearity hybrid power supply based on single chip microcomputer is designed which merged the merits of the switching and linear power supply. Main circuit includes pre-regulator which works in switching mode and series regulator which works in linear mode. Two-stage regulation mode was adopted in the main circuit of the power. A single chip computer (SCM) and high resolution of series D/A and A/D converters are applied to control and measurement which achieved continuous adjustable and low ripple constant current or voltage power supply

Stochastic architecture for Hopfield neural nets

NASA Technical Reports Server (NTRS)

Pavel, Sandy

1992-01-01

An expandable stochastic digital architecture for recurrent (Hopfield like) neural networks is proposed. The main features and basic principles of stochastic processing are presented. The stochastic digital architecture is based on a chip with n full interconnected neurons with a pipeline, bit processing structure. For large applications, a flexible way to interconnect many such chips is provided.

1-Million droplet array with wide-field fluorescence imaging for digital PCR.

PubMed

Hatch, Andrew C; Fisher, Jeffrey S; Tovar, Armando R; Hsieh, Albert T; Lin, Robert; Pentoney, Stephen L; Yang, David L; Lee, Abraham P

2011-11-21

Digital droplet reactors are useful as chemical and biological containers to discretize reagents into picolitre or nanolitre volumes for analysis of single cells, organisms, or molecules. However, most DNA based assays require processing of samples on the order of tens of microlitres and contain as few as one to as many as millions of fragments to be detected. Presented in this work is a droplet microfluidic platform and fluorescence imaging setup designed to better meet the needs of the high-throughput and high-dynamic-range by integrating multiple high-throughput droplet processing schemes on the chip. The design is capable of generating over 1-million, monodisperse, 50 picolitre droplets in 2-7 minutes that then self-assemble into high density 3-dimensional sphere packing configurations in a large viewing chamber for visualization and analysis. This device then undergoes on-chip polymerase chain reaction (PCR) amplification and fluorescence detection to digitally quantify the sample's nucleic acid contents. Wide-field fluorescence images are captured using a low cost 21-megapixel digital camera and macro-lens with an 8-12 cm(2) field-of-view at 1× to 0.85× magnification, respectively. We demonstrate both end-point and real-time imaging ability to perform on-chip quantitative digital PCR analysis of the entire droplet array. Compared to previous work, this highly integrated design yields a 100-fold increase in the number of on-chip digitized reactors with simultaneous fluorescence imaging for digital PCR based assays.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Digital PCR on a SlipChip.

PubMed

Shen, Feng; Du, Wenbin; Kreutz, Jason E; Fok, Alice; Ismagilov, Rustem F

2010-10-21

This paper describes a SlipChip to perform digital PCR in a very simple and inexpensive format. The fluidic path for introducing the sample combined with the PCR mixture was formed using elongated wells in the two plates of the SlipChip designed to overlap during sample loading. This fluidic path was broken up by simple slipping of the two plates that removed the overlap among wells and brought each well in contact with a reservoir preloaded with oil to generate 1280 reaction compartments (2.6 nL each) simultaneously. After thermal cycling, end-point fluorescence intensity was used to detect the presence of nucleic acid. Digital PCR on the SlipChip was tested quantitatively by using Staphylococcus aureus genomic DNA. As the concentration of the template DNA in the reaction mixture was diluted, the fraction of positive wells decreased as expected from the statistical analysis. No cross-contamination was observed during the experiments. At the extremes of the dynamic range of digital PCR the standard confidence interval determined using a normal approximation of the binomial distribution is not satisfactory. Therefore, statistical analysis based on the score method was used to establish these confidence intervals. The SlipChip provides a simple strategy to count nucleic acids by using PCR. It may find applications in research applications such as single cell analysis, prenatal diagnostics, and point-of-care diagnostics. SlipChip would become valuable for diagnostics, including applications in resource-limited areas after integration with isothermal nucleic acid amplification technologies and visual readout.

Digital Microfluidics Sample Analyzer

NASA Technical Reports Server (NTRS)

Pollack, Michael G.; Srinivasan, Vijay; Eckhardt, Allen; Paik, Philip Y.; Sudarsan, Arjun; Shenderov, Alex; Hua, Zhishan; Pamula, Vamsee K.

2010-01-01

Three innovations address the needs of the medical world with regard to microfluidic manipulation and testing of physiological samples in ways that can benefit point-of-care needs for patients such as premature infants, for which drawing of blood for continuous tests can be life-threatening in their own right, and for expedited results. A chip with sample injection elements, reservoirs (and waste), droplet formation structures, fluidic pathways, mixing areas, and optical detection sites, was fabricated to test the various components of the microfluidic platform, both individually and in integrated fashion. The droplet control system permits a user to control droplet microactuator system functions, such as droplet operations and detector operations. Also, the programming system allows a user to develop software routines for controlling droplet microactuator system functions, such as droplet operations and detector operations. A chip is incorporated into the system with a controller, a detector, input and output devices, and software. A novel filler fluid formulation is used for the transport of droplets with high protein concentrations. Novel assemblies for detection of photons from an on-chip droplet are present, as well as novel systems for conducting various assays, such as immunoassays and PCR (polymerase chain reaction). The lab-on-a-chip (a.k.a., lab-on-a-printed-circuit board) processes physiological samples and comprises a system for automated, multi-analyte measurements using sub-microliter samples of human serum. The invention also relates to a diagnostic chip and system including the chip that performs many of the routine operations of a central labbased chemistry analyzer, integrating, for example, colorimetric assays (e.g., for proteins), chemiluminescence/fluorescence assays (e.g., for enzymes, electrolytes, and gases), and/or conductometric assays (e.g., for hematocrit on plasma and whole blood) on a single chip platform.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Machine vision for digital microfluidics

NASA Astrophysics Data System (ADS)

Shin, Yong-Jun; Lee, Jeong-Bong

2010-01-01

Machine vision is widely used in an industrial environment today. It can perform various tasks, such as inspecting and controlling production processes, that may require humanlike intelligence. The importance of imaging technology for biological research or medical diagnosis is greater than ever. For example, fluorescent reporter imaging enables scientists to study the dynamics of gene networks with high spatial and temporal resolution. Such high-throughput imaging is increasingly demanding the use of machine vision for real-time analysis and control. Digital microfluidics is a relatively new technology with expectations of becoming a true lab-on-a-chip platform. Utilizing digital microfluidics, only small amounts of biological samples are required and the experimental procedures can be automatically controlled. There is a strong need for the development of a digital microfluidics system integrated with machine vision for innovative biological research today. In this paper, we show how machine vision can be applied to digital microfluidics by demonstrating two applications: machine vision-based measurement of the kinetics of biomolecular interactions and machine vision-based droplet motion control. It is expected that digital microfluidics-based machine vision system will add intelligence and automation to high-throughput biological imaging in the future.

275 C Downhole Microcomputer System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chris Hutchens; Hooi Miin Soo

2008-08-31

An HC11 controller IC and along with serial SRAM and ROM support ICs chip set were developed to support a data acquisition and control for extreme temperature/harsh environment conditions greater than 275 C. The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications and was the logical choice for a downhole controller. This extreme temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs, The microcomputer chip consists of the microprocessormore » ALU, a small boot ROM, 4 kbyte data RAM, counter/timer unit, serial peripheral interface (SPI), asynchronous serial interface (SCI), and the A, B, C, and D parallel ports. The chip is code compatible with the single chip mode commercial 68HC11 except for the absence of the analog to digital converter system. To avoid mask programmed internal ROM, a boot program is used to load the microcomputer program from an external mask SPI ROM. A SPI RAM IC completes the chip set and allows data RAM to be added in 4 kbyte increments. The HC11 controller IC chip set is implemented in the Peregrine Semiconductor 0.5 micron Silicon-on-Sapphire (SOS) process using a custom high temperature cell library developed at Oklahoma State University. Yield data is presented for all, the HC11, SPI-RAM and ROM. The lessons learned in this project were extended to the successful development of two high temperature versions of the LEON3 and a companion 8 Kbyte SRAM, a 200 C version for the Navy and a 275 C version for the gas industry.« less

Direct-referencing Two-dimensional-array Digital Microfluidics Using Multi-layer Printed Circuit Board

PubMed Central

Gong, Jian; Kim, Chang-Jin “CJ”

2008-01-01

Digital (i.e. droplet-based) microfluidics, by the electrowetting-on-dielectric (EWOD) mechanism, has shown great potential for a wide range of applications, such as lab-on-a-chip. While most reported EWOD chips use a series of electrode pads essentially in one-dimensional line pattern designed for specific tasks, the desired universal chips allowing user-reconfigurable paths would require the electrode pads in two-dimensional pattern. However, to electrically access the electrode pads independently, conductive lines need to be fabricated underneath the pads in multiple layers, raising a cost issue especially for disposable chip applications. In this article, we report the building of digital microfluidic plates based on a printed-circuit-board (PCB), in which multilayer electrical access lines were created inexpensively using mature PCB technology. However, due to its surface topography and roughness and resulting high resistance against droplet movement, as-fabricated PCB surfaces require unacceptably high (~500 V) voltages unless coated with or immersed in oil. Our goal is EWOD operations of aqueous droplets not only on oil-covered but also on dry surfaces. To meet varying levels of performances, three types of gradually complex post-PCB microfabrication processes are developed and evaluated. By introducing land-grid-array (LGA) sockets in the packaging, a scalable digital microfluidics system with reconfigurable and low-cost chip is also demonstrated. PMID:19234613

ALL-ELECTRONIC DROPLET GENERATION ON-CHIP WITH REAL-TIME FEEDBACK CONTROL FOR EWOD DIGITIAL MICROFLUIDICS

PubMed Central

Gong, Jian; Kim, Chang-Jin “CJ”

2009-01-01

Electrowetting-on-dielectric (EWOD) actuation enables digital (or droplet) microfluidics where small packets of liquids are manipulated on a two-dimensional surface. Due to its mechanical simplicity and low energy consumption, EWOD holds particular promise for portable systems. To improve volume precision of the droplets, which is desired for quantitative applications such as biochemical assays, existing practices would require near-perfect device fabricaion and operation conditions unless the droplets are generated under feedback control by an extra pump setup off of the chip. In this paper, we develop an all-electronic (i.e., no ancillary pumping) real-time feedback control of on-chip droplet generation. A fast voltage modulation, capacitance sensing, and discrete-time PID feedback controller are integrated on the operating electronic board. A significant improvement is obtained in the droplet volume uniformity, compared with an open loop control as well as the previous feedback control employing an external pump. Furthermore, this new capability empowers users to prescribe the droplet volume even below the previously considered minimum, allowing, for example, 1:x (x < 1) mixing, in comparison to the previously considered n:m mixing (i.e., n and m unit droplets). PMID:18497909

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

NASA Astrophysics Data System (ADS)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Absolute quantification of DNA methylation using microfluidic chip-based digital PCR.

PubMed

Wu, Zhenhua; Bai, Yanan; Cheng, Zule; Liu, Fangming; Wang, Ping; Yang, Dawei; Li, Gang; Jin, Qinghui; Mao, Hongju; Zhao, Jianlong

2017-10-15

Hypermethylation of CpG islands in the promoter region of many tumor suppressor genes downregulates their expression and in a result promotes tumorigenesis. Therefore, detection of DNA methylation status is a convenient diagnostic tool for cancer detection. Here, we reported a novel method for the integrative detection of methylation by the microfluidic chip-based digital PCR. This method relies on methylation-sensitive restriction enzyme HpaII, which cleaves the unmethylated DNA strands while keeping the methylated ones intact. After HpaII treatment, the DNA methylation level is determined quantitatively by the microfluidic chip-based digital PCR with the lower limit of detection equal to 0.52%. To validate the applicability of this method, promoter methylation of two tumor suppressor genes (PCDHGB6 and HOXA9) was tested in 10 samples of early stage lung adenocarcinoma and their adjacent non-tumorous tissues. The consistency was observed in the analysis of these samples using our method and a conventional bisulfite pyrosequencing. Combining high sensitivity and low cost, the microfluidic chip-based digital PCR method might provide a promising alternative for the detection of DNA methylation and early diagnosis of epigenetics-related diseases. Copyright © 2017 Elsevier B.V. All rights reserved.

Effect of bone chip orientation on quantitative estimates of changes in bone mass using digital subtraction radiography.

PubMed

Mol, André; Dunn, Stanley M

2003-06-01

To assess the effect of the orientation of arbitrarily shaped bone chips on the correlation between radiographic estimates of bone loss and true mineral loss using digital subtraction radiography. Twenty arbitrarily shaped bone chips (dry weight 1-10 mg) were placed individually on the superior lingual aspect of the interdental alveolar bone of a dry dentate hemi-mandible. After acquiring the first baseline image, each chip was rotated 90 degrees and a second radiograph was captured. Follow-up images were created without the bone chips and after rotating the mandible 0, 1, 2, 4, and 6 degrees around a vertical axis. Aluminum step tablet intensities were used to normalize image intensities for each image pair. Follow-up images were registered and geometrically standardized using projective standardization. Bone chips were dry ashed and analyzed for calcium content using atomic absorption. No significant difference was found between the radiographic estimates of bone loss from the different bone chip orientations (Wilcoxon: P > 0.05). The correlation between the two series of estimates for all rotations was 0.93 (Spearman: P < 0.05). Linear regression analysis indicated that both correlates did not differ appreciably ( and ). It is concluded that the spatial orientation of arbitrarily shaped bone chips does not have a significant impact on quantitative estimates of changes in bone mass in digital subtraction radiography. These results were obtained in the presence of irreversible projection errors of up to six degrees and after application of projective standardization for image reconstruction and image registration.

Real-time, multiplexed electrochemical DNA detection using an active complementary metal-oxide-semiconductor biosensor array with integrated sensor electronics.

PubMed

Levine, Peter M; Gong, Ping; Levicky, Rastislav; Shepard, Kenneth L

2009-03-15

Optical biosensing based on fluorescence detection has arguably become the standard technique for quantifying extents of hybridization between surface-immobilized probes and fluorophore-labeled analyte targets in DNA microarrays. However, electrochemical detection techniques are emerging which could eliminate the need for physically bulky optical instrumentation, enabling the design of portable devices for point-of-care applications. Unlike fluorescence detection, which can function well using a passive substrate (one without integrated electronics), multiplexed electrochemical detection requires an electronically active substrate to analyze each array site and benefits from the addition of integrated electronic instrumentation to further reduce platform size and eliminate the electromagnetic interference that can result from bringing non-amplified signals off chip. We report on an active electrochemical biosensor array, constructed with a standard complementary metal-oxide-semiconductor (CMOS) technology, to perform quantitative DNA hybridization detection on chip using targets conjugated with ferrocene redox labels. A 4 x 4 array of gold working electrodes and integrated potentiostat electronics, consisting of control amplifiers and current-input analog-to-digital converters, on a custom-designed 5 mm x 3 mm CMOS chip drive redox reactions using cyclic voltammetry, sense DNA binding, and transmit digital data off chip for analysis. We demonstrate multiplexed and specific detection of DNA targets as well as real-time monitoring of hybridization, a task that is difficult, if not impossible, with traditional fluorescence-based microarrays.

On-chip temperature-based digital signal processing for customized wireless microcontroller

NASA Astrophysics Data System (ADS)

Farhah Razanah Faezal, Siti; Isa, Mohd Nazrin Md; Harun, Azizi; Nizam Mohyar, Shaiful; Bahari Jambek, Asral

2017-11-01

Increases in die size and power density inside system-on-chip (SoC) design have brought thermal issue inside the system. Uneven heat-up and increasing in temperature offset on-chip has become a major factor that can limits the system performance. This paper presents the design and simulation of a temperature-based digital signal processing for modern system-on-chip design using the Verilog HDL. This design yields continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Altera Quartus Software v. 14. With system above, microcontroller can achieve nominal power dissipation and operation is within the temperature range due to the incorporate of an interrupt-based system.

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Chauveau, J.; Del Buono, L.; Genat, J. F.; Lebbolo, H.; Roos, L.; Zhang, B.; Beigbeder, C.; Bernier, R.; Breton, D.; Caceres, T.; Chase, R.; Ducorps, A.; Hrisoho, A.; Imbert, P.; Sen, S.; Tocut, V.; Truong, K.; Wormser, G.; Zomer, F.; Bonneaud, G.; Dohou, F.; Gastaldi, F.; Matricon, P.; Renard, C.; Thiebaux, C.; Vasileiadis, G.; Verderi, M.; Oxoby, G.; Va'Vra, J.; Warner, D.; Wilson, R. J.

1999-08-01

The detector of Internally Reflected Cherenkov light (DIRC) of the BaBar detector (SLAC Stanford, USA) measures better than 1 ns the arrival time of Cherenkov photoelectrons, detected in a 11 000 phototubes array and their amplitude spectra. It mainly comprises of 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom Analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom Digital TDC chips for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test of the pre-production chips have been performed as well as system tests.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

3D nanofabrication inside rapid prototyped microfluidic channels showcased by wet-spinning of single micrometre fibres.

PubMed

Lölsberg, Jonas; Linkhorst, John; Cinar, Arne; Jans, Alexander; Kuehne, Alexander J C; Wessling, Matthias

2018-05-01

Microfluidics is an established multidisciplinary research domain with widespread applications in the fields of medicine, biotechnology and engineering. Conventional production methods of microfluidic chips have been limited to planar structures, preventing the exploitation of truly three-dimensional architectures for applications such as multi-phase droplet preparation or wet-phase fibre spinning. Here the challenge of nanofabrication inside a microfluidic chip is tackled for the showcase of a spider-inspired spinneret. Multiphoton lithography, an additive manufacturing method, was used to produce free-form microfluidic masters, subsequently replicated by soft lithography. Into the resulting microfluidic device, a three-dimensional spider-inspired spinneret was directly fabricated in-chip via multiphoton lithography. Applying this unprecedented fabrication strategy, the to date smallest printed spinneret nozzle is produced. This spinneret resides tightly sealed, connecting it to the macroscopic world. Its functionality is demonstrated by wet-spinning of single-digit micron fibres through a polyacrylonitrile coagulation process induced by a water sheath layer. The methodology developed here demonstrates fabrication strategies to interface complex architectures into classical microfluidic platforms. Using multiphoton lithography for in-chip fabrication adopts a high spatial resolution technology for improving geometry and thus flow control inside microfluidic chips. The showcased fabrication methodology is generic and will be applicable to multiple challenges in fluid control and beyond.

Results and Insights on the Impact of Smoke on Digital Instrumentation and Control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T. J.; Nowlen, S. P.

2001-01-31

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The major effect of smoke has been to increase leakage currents (through circuit bridging across contacts and leads) and tomore » cause momentary upsets and failures in digital systems. This report summarizes two previous reports and presents new results from conformal coating, memory chip, and hard drive tests. The report describes practices for mitigation of smoke damage through digital system design, fire barriers, ventilation, fire suppressants, and post fire procedures.« less

A design of LED adaptive dimming lighting system based on incremental PID controller

NASA Astrophysics Data System (ADS)

He, Xiangyan; Xiao, Zexin; He, Shaojia

2010-11-01

As a new generation energy-saving lighting source, LED is applied widely in various technology and industry fields. The requirement of its adaptive lighting technology is more and more rigorous, especially in the automatic on-line detecting system. In this paper, a closed loop feedback LED adaptive dimming lighting system based on incremental PID controller is designed, which consists of MEGA16 chip as a Micro-controller Unit (MCU), the ambient light sensor BH1750 chip with Inter-Integrated Circuit (I2C), and constant-current driving circuit. A given value of light intensity required for the on-line detecting environment need to be saved to the register of MCU. The optical intensity, detected by BH1750 chip in real time, is converted to digital signal by AD converter of the BH1750 chip, and then transmitted to MEGA16 chip through I2C serial bus. Since the variation law of light intensity in the on-line detecting environment is usually not easy to be established, incremental Proportional-Integral-Differential (PID) algorithm is applied in this system. Control variable obtained by the incremental PID determines duty cycle of Pulse-Width Modulation (PWM). Consequently, LED's forward current is adjusted by PWM, and the luminous intensity of the detection environment is stabilized by self-adaptation. The coefficients of incremental PID are obtained respectively after experiments. Compared with the traditional LED dimming system, it has advantages of anti-interference, simple construction, fast response, and high stability by the use of incremental PID algorithm and BH1750 chip with I2C serial bus. Therefore, it is suitable for the adaptive on-line detecting applications.

Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Rolando, Sébastien; Corbière, Franck; Rizzolo, Serena; Chabane, Aziouz; Girard, Sylvain; Baer, Jérémy; Estribeau, Magali; Magnan, Pierre; Paillet, Philippe; Van Uffelen, Marco; Mont Casellas, Laura; Scott, Robin; Gaillardin, Marc; Marcandella, Claude; Marcelot, Olivier; Allanche, Timothé

2017-01-01

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed.

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

NASA Technical Reports Server (NTRS)

Petersen, W. C.; Siu, D. P.; Cook, H. F.

1991-01-01

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

Integration of image capture and processing: beyond single-chip digital camera

NASA Astrophysics Data System (ADS)

Lim, SukHwan; El Gamal, Abbas

2001-05-01

An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image senor to enable new applications such as multiple capture for enhancing dynamic range and to improve the performance of existing applications such as optical flow estimation. Conventional digital cameras operate at low frame rates and it would be too costly, if not infeasible, to operate their chips at high frame rates. Integration solves this problem. The idea is to capture images at much higher frame rates than he standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. This idea is applied to optical flow estimation, where significant performance improvements are demonstrate over methods using standard frame rate sequences. We then investigate the constraints on memory size and processing power that can be integrated with a CMOS image sensor in a 0.18 micrometers process and below. We show that enough memory and processing power can be integrated to be able to not only perform the functions of a conventional camera system but also to perform applications such as real time optical flow estimation.

A novel miniaturized PCR multi-reactor array fabricated using flip-chip bonding techniques

NASA Astrophysics Data System (ADS)

Zou, Zhi-Qing; Chen, Xiang; Jin, Qing-Hui; Yang, Meng-Su; Zhao, Jian-Long

2005-08-01

This paper describes a novel miniaturized multi-chamber array capable of high throughput polymerase chain reaction (PCR). The structure of the proposed device is verified by using finite element analysis (FEA) to optimize the thermal performance, and then implemented on a glass-silicon substrate using a standard MEMS process and post-processing. Thermal analysis simulation and verification of each reactor cell is equipped with integrated Pt temperature sensors and heaters at the bottom of the reaction chamber for real-time accurate temperature sensing and control. The micro-chambers are thermally separated from each other, and can be controlled independently. The multi-chip array was packaged on a printed circuit board (PCB) substrate using a conductive polymer flip-chip bonding technique, which enables effective heat dissipation and suppresses thermal crosstalk between the chambers. The designed system has successfully demonstrated a temperature fluctuation of ±0.5 °C during thermal multiplexing of up to 2 × 2 chambers, a full speed of 30 min for 30 cycle PCR, as well as the capability of controlling each chamber digitally and independently.

CHIP Demonstrator: Semantics-Driven Recommendations and Museum Tour Generation

NASA Astrophysics Data System (ADS)

Aroyo, Lora; Stash, Natalia; Wang, Yiwen; Gorgels, Peter; Rutledge, Lloyd

The main objective of the CHIP project is to demonstrate how Semantic Web technologies can be deployed to provide personalized access to digital museum collections. We illustrate our approach with the digital database ARIA of the Rijksmuseum Amsterdam. For the semantic enrichment of the Rijksmuseum ARIA database we collaborated with the CATCH STITCH project to produce mappings to Iconclass, and with the MultimediaN E-culture project to produce the RDF/OWL of the ARIA and Adlib databases. The main focus of CHIP is on exploring the potential of applying adaptation techniques to provide personalized experience for the museum visitors both on the Web site and in the museum.

Digital quantification of DNA via isothermal amplification on a self-driven microfluidic chip featuring hydrophilic film-coated polydimethylsiloxane.

PubMed

Ma, Yu-Dong; Chang, Wen-Hsin; Luo, Kang; Wang, Chih-Hung; Liu, Shih-Yuan; Yen, Wen-Hsiang; Lee, Gwo-Bin

2018-01-15

Loop-mediated isothermal amplification (LAMP) is a DNA amplification approach characterized by high sensitivity and specificity. In "digital LAMP", small quantities of both template DNA and reagents are encapsulated within a droplet or microwell, allowing for analysis of precious nucleic acid samples in shorter amounts of time relative to traditional DNA amplification protocols (e.g., PCR) with an improved limit of detection. In this study, an integrated, self-driven microfluidic chip was designed to carry out digital LAMP. The entire quantification process could be automatically performed on this chip via capillary forces enabled through microwells comprised of polydimethylsiloxane (PDMS) surfaces coated with a hydrophilic film; no external pumps were required. Moreover, digitized droplets could be separated from each other by normally-closed microvalves. The contact angle of the hydrophilic film-coated PDMS surface was only 14.3°. This is the first time that a rapid (30min) and simple method has been used to create hydrophilic PDMS surfaces that allow for digital LAMP to be performed in a self-driven microfluidic device. As a proof of concept, amplification of a gene specific to a vancomycin-resistant Enterococcus strain was performed on the developed microfluidic chip within 30min, and the limit of detection was only 11 copies with a volume of 30μL. This device may therefore become a promising tool for clinical diagnosis and point-of-care applications. Copyright © 2017 Elsevier B.V. All rights reserved.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Orientation-selective aVLSI spiking neurons.

PubMed

Liu, S C; Kramer, J; Indiveri, G; Delbrück, T; Burg, T; Douglas, R

2001-01-01

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

The role of EEPROM devices in upcoming ISDN applications

NASA Astrophysics Data System (ADS)

Nette, Herbert L.

1991-02-01

Integrated Services Digital Network (ISDN) equipments are rapidly becoming a major market for semiconductor chips. Although at first glance this growing market appears to be geared at logic chips, nonvolatile memories represent important support chips and will become a significant segment of this market. Challenges in these applications consist in operating EEPROMs at lower voltages and lower power and embedding them on ever more complex communications processor chips.

OSCAR: A Compact, Powerful and Versatile On Board Computer Based on LEON3 Core

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Lefevre, Aurelien; Koebel, Franck

2011-08-01

Satellites are controlled via a platform On Board Computer (OBC) that manages different parameters (attitude, orbit, modes, temperatures ...) with respect to its payload mission (telecommunication, earth observation, scientific mission). The platform OBC is connected to the satellite and the ground control via digital links, and executes on board software.The main functions of a platform OBC are to provide the satellite flight segment with the following features: o Processing resources for the flight mission software o TM/TC services and interfaces with the RF communication chaino General communication services with the Avionicsand payload equipments through an on-board communication bus based on the MIL-1553B standard or CANo Time synchronization and distributiono Failure tolerant architecture based on the use of redounded reconfiguration units and redundancyimplementationFrom a hardware point of view, it groups a lot of digital functions usually dispatched on numerous chips (processor, co-processor, digital links IP ...) together. In order to reach an ultimate level of integration, Astrium has designed an ASIC gathering on a single chip all the required digital functions: the SCOC3 ASIC.Astrium has developed an OBC based on this SCOC3 ASIC: the OSCAR (Optimized Spacecraft Computer Architecture with Reconfiguration). It is now available off-the-shelf as the new OBC product family of Astrium.This paper presents the major innovations introduced by Astrium for SCOC3 and OSCAR with the objective to save cost and mass through a solution compatible with any class quality project, using a unique software development environment for user.

A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

NASA Astrophysics Data System (ADS)

Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, T.J.; Antonescu, C.

A program to assess the impact of smoke on digital instrumentation and control (I and C) safety systems began in 1994, funded by the US Nuclear Regulatory Commission Office of Research. Digital I and C safety systems are likely replacements for today`s analog systems. The nuclear industry has little experience in qualifying digital electronics for critical systems, part of which is understanding system performance during plant fires. The results of tests evaluating the performance of digital circuits and chip technologies exposed to the various smoke and humidity conditions representative of cable fires are discussed. Tests results show that low tomore » moderate smoke densities can cause intermittent failures of digital systems. Smoke increases leakage currents between biased contacts, leading to shorts. Chips with faster switching times, and thus higher output drive currents, are less sensitive to leakage currents and thus to smoke. Contact corrosion from acidic gases in smoke and inductance of stray capacitance are less important contributors to system upset. Transmission line coupling was increased because the smoke acted as a conductive layer between the lines. Permanent circuit damage was not obvious in the 24 hr of circuit monitoring. Test results also show that polyurethane, parylene, and acrylic conformal coatings are more effective in protecting against smoke than epoxy or silicone. Common-sense mitigation measures are discussed. Unfortunately the authors are a long way from standard tests for smoke exposure that capture the variations in smoke exposure possible in an actual fire.« less

640 X 480 MOS PtSi IR sensor

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1991-12-01

The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

Research on numerical control system based on S3C2410 and MCX314AL

NASA Astrophysics Data System (ADS)

Ren, Qiang; Jiang, Tingbiao

2008-10-01

With the rapid development of micro-computer technology, embedded system, CNC technology and integrated circuits, numerical control system with powerful functions can be realized by several high-speed CPU chips and RISC (Reduced Instruction Set Computing) chips which have small size and strong stability. In addition, the real-time operating system also makes the attainment of embedded system possible. Developing the NC system based on embedded technology can overcome some shortcomings of common PC-based CNC system, such as the waste of resources, low control precision, low frequency and low integration. This paper discusses a hardware platform of ENC (Embedded Numerical Control) system based on embedded processor chip ARM (Advanced RISC Machines)-S3C2410 and DSP (Digital Signal Processor)-MCX314AL and introduces the process of developing ENC system software. Finally write the MCX314AL's driver under the embedded Linux operating system. The embedded Linux operating system can deal with multitask well moreover satisfy the real-time and reliability of movement control. NC system has the advantages of best using resources and compact system with embedded technology. It provides a wealth of functions and superior performance with a lower cost. It can be sure that ENC is the direction of the future development.

Digital Waveguide Architectures for Virtual Musical Instruments

NASA Astrophysics Data System (ADS)

Smith, Julius O.

Digital sound synthesis has become a standard staple of modern music studios, videogames, personal computers, and hand-held devices. As processing power has increased over the years, sound synthesis implementations have evolved from dedicated chip sets, to single-chip solutions, and ultimately to software implementations within processors used primarily for other tasks (such as for graphics or general purpose computing). With the cost of implementation dropping closer and closer to zero, there is increasing room for higher quality algorithms.

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

Smart single-chip gas sensor microsystem

NASA Astrophysics Data System (ADS)

Hagleitner, C.; Hierlemann, A.; Lange, D.; Kummer, A.; Kerness, N.; Brand, O.; Baltes, H.

2001-11-01

Research activity in chemical gas sensing is currently directed towards the search for highly selective (bio)chemical layer materials, and to the design of arrays consisting of different partially selective sensors that permit subsequent pattern recognition and multi-component analysis. Simultaneous use of various transduction platforms has been demonstrated, and the rapid development of integrated-circuit technology has facilitated the fabrication of planar chemical sensors and sensors based on three-dimensional microelectromechanical systems. Complementary metal-oxide silicon processes have previously been used to develop gas sensors based on metal oxides and acoustic-wave-based sensor devices. Here we combine several of these developments to fabricate a smart single-chip chemical microsensor system that incorporates three different transducers (mass-sensitive, capacitive and calorimetric), all of which rely on sensitive polymeric layers to detect airborne volatile organic compounds. Full integration of the microelectronic and micromechanical components on one chip permits control and monitoring of the sensor functions, and enables on-chip signal amplification and conditioning that notably improves the overall sensor performance. The circuitry also includes analog-to-digital converters, and an on-chip interface to transmit the data to off-chip recording units. We expect that our approach will provide a basis for the further development and optimization of gas microsystems.

Active Microelectronic Neurosensor Arrays for Implantable Brain Communication Interfaces

PubMed Central

Song, Y.-K.; Borton, D. A.; Park, S.; Patterson, W. R.; Bull, C. W.; Laiwalla, F.; Mislow, J.; Simeral, J. D.; Donoghue, J. P.; Nurmikko, A. V.

2010-01-01

We have built a wireless implantable microelectronic device for transmitting cortical signals transcutaneously. The device is aimed at interfacing a microelectrode array cortical to an external computer for neural control applications. Our implantable microsystem enables presently 16-channel broadband neural recording in a non-human primate brain by converting these signals to a digital stream of infrared light pulses for transmission through the skin. The implantable unit employs a flexible polymer substrate onto which we have integrated ultra-low power amplification with analog multiplexing, an analog-to-digital converter, a low power digital controller chip, and infrared telemetry. The scalable 16-channel microsystem can employ any of several modalities of power supply, including via radio frequency by induction, or infrared light via a photovoltaic converter. As of today, the implant has been tested as a sub-chronic unit in non-human primates (~ 1 month), yielding robust spike and broadband neural data on all available channels. PMID:19502132

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

NASA Astrophysics Data System (ADS)

Li, Hangbiao; Zhang, Bo; Luo, Ping; Zhen, Shaowei; Liao, Pengfei; He, Yajuan; Li, Zhaoji

2015-09-01

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.

On-chip dynamic stress control for cancer cell evolution study

NASA Astrophysics Data System (ADS)

Liu, Liyu; Austin, Robert

2010-03-01

The growth and spreading of cancer in host organisms is an evolutionary process. Cells accumulate mutations that help them adapt to changing environments and to obtain survival fitness. However, all cancer--promoting mutations do not occur at once. Cancer cells face selective environmental pressures that drive their evolution in stages. In traditional cancer studies, environmental stress is usually homogenous in space and difficult to change in time. Here, we propose a microfluidic chip employing embedded dynamic traps to generate dynamic heterogeneous microenvironments for cancer cells in evolution studies. Based on polydimethylsiloxane (PDMS) flexible diaphragms, these traps are able to enclose and shield cancer cells or expose them to external environmental stress. Digital controls for each trap determine the nutrition, antibiotics, CO2/O2 conditions, and temperatures to which trapped cells are subjected. Thus, the stress applied to cells can be varied in intensity and duration in each trap independently. The chip can also output cells from specific traps for sequencing and other biological analysis. Hence our design simultaneously monitors and analyzes cell evolution behaviors under dynamic stresses.

Impact of Smoke Exposure on Digital Instrumentation and Control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tanaka, Tina J.; Nowlen, Steven P.; Korsah, Kofi

2003-08-15

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke hasmore » been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers' IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.« less

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

Two CMOS gate arrays for the EPACT experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winkert, G.

1992-08-01

Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows formore » commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.« less

About machine-readable travel documents

NASA Astrophysics Data System (ADS)

Vaudenay, S.; Vuagnoux, M.

2007-07-01

Passports are documents that help immigration officers to identify people. In order to strongly authenticate their data and to automatically identify people, they are now equipped with RFID chips. These contain private information, biometrics, and a digital signature by issuing authorities. Although they substantially increase security at the border controls, they also come with new security and privacy issues. In this paper, we survey existing protocols and their weaknesses.

First results of the front-end ASIC for the strip detector of the PANDA MVD

NASA Astrophysics Data System (ADS)

Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

2017-03-01

PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

Reconfigurable virtual electrowetting channels.

PubMed

Banerjee, Ananda; Kreit, Eric; Liu, Yuguang; Heikenfeld, Jason; Papautsky, Ian

2012-02-21

Lab-on-a-chip systems rely on several microfluidic paradigms. The first uses a fixed layout of continuous microfluidic channels. Such lab-on-a-chip systems are almost always application specific and far from a true "laboratory." The second involves electrowetting droplet movement (digital microfluidics), and allows two-dimensional computer control of fluidic transport and mixing. The merging of the two paradigms in the form of programmable electrowetting channels takes advantage of both the "continuous" functionality of rigid channels based on which a large number of applications have been developed to date and the "programmable" functionality of digital microfluidics that permits electrical control of on-chip functions. In this work, we demonstrate for the first time programmable formation of virtual microfluidic channels and their continuous operation with pressure driven flows using an electrowetting platform. Experimental, theoretical, and numerical analyses of virtual channel formation with biologically relevant electrolyte solutions and electrically-programmable reconfiguration are presented. We demonstrate that the "wall-less" virtual channels can be formed reliably and rapidly, with propagation rates of 3.5-3.8 mm s(-1). Pressure driven transport in these virtual channels at flow rates up to 100 μL min(-1) is achievable without distortion of the channel shape. We further demonstrate that these virtual channels can be switched on-demand between multiple inputs and outputs. Ultimately, we envision a platform that would provide rapid prototyping of microfluidic concepts and would be capable of a vast library of functions and benefitting applications from clinical diagnostics in resource-limited environments to rapid system prototyping to high throughput pharmaceutical applications.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Digital Ratiometer

NASA Technical Reports Server (NTRS)

Beer, R.

1985-01-01

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

Modeling and Simulation of Lab-on-a-Chip Systems

DTIC Science & Technology

2005-08-12

complex chip geometries (including multiple turns). Variations of sample concentration profiles in laminar diffusion-based micromixers are also derived...CHAPTER 6 MODELING OF LAMINAR DIFFUSION-BASED COMPLEX ELECTROKINETIC PASSIVE MICROMIXERS ...140 6.4.4 Multi-Stream (Inter-Digital) Micromixers

Bio-inspired multi-mode optic flow sensors for micro air vehicles

NASA Astrophysics Data System (ADS)

Park, Seokjun; Choi, Jaehyuk; Cho, Jihyun; Yoon, Euisik

2013-06-01

Monitoring wide-field surrounding information is essential for vision-based autonomous navigation in micro-air-vehicles (MAV). Our image-cube (iCube) module, which consists of multiple sensors that are facing different angles in 3-D space, can be applied to the wide-field of view optic flows estimation (μ-Compound eyes) and to attitude control (μ- Ocelli) in the Micro Autonomous Systems and Technology (MAST) platforms. In this paper, we report an analog/digital (A/D) mixed-mode optic-flow sensor, which generates both optic flows and normal images in different modes for μ- Compound eyes and μ-Ocelli applications. The sensor employs a time-stamp based optic flow algorithm which is modified from the conventional EMD (Elementary Motion Detector) algorithm to give an optimum partitioning of hardware blocks in analog and digital domains as well as adequate allocation of pixel-level, column-parallel, and chip-level signal processing. Temporal filtering, which may require huge hardware resources if implemented in digital domain, is remained in a pixel-level analog processing unit. The rest of the blocks, including feature detection and timestamp latching, are implemented using digital circuits in a column-parallel processing unit. Finally, time-stamp information is decoded into velocity from look-up tables, multiplications, and simple subtraction circuits in a chip-level processing unit, thus significantly reducing core digital processing power consumption. In the normal image mode, the sensor generates 8-b digital images using single slope ADCs in the column unit. In the optic flow mode, the sensor estimates 8-b 1-D optic flows from the integrated mixed-mode algorithm core and 2-D optic flows with an external timestamp processing, respectively.

Quantifying the benefits of improved rolling of chip seals : final report, June 2008.

DOT National Transportation Integrated Search

2008-06-01

This report presents an improvement in the rolling protocol for chip seals based on an evaluation of aggregate : retention performance and aggregate embedment depth. The flip-over test (FOT), Vialit test, modified sand circle : test, digital image pr...

Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Gurbuz, Yasar

2013-06-01

Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.

Demosaiced pixel super-resolution in digital holography for multiplexed computational color imaging on-a-chip (Conference Presentation)

NASA Astrophysics Data System (ADS)

Wu, Yichen; Zhang, Yibo; Luo, Wei; Ozcan, Aydogan

2017-03-01

Digital holographic on-chip microscopy achieves large space-bandwidth-products (e.g., >1 billion) by making use of pixel super-resolution techniques. To synthesize a digital holographic color image, one can take three sets of holograms representing the red (R), green (G) and blue (B) parts of the spectrum and digitally combine them to synthesize a color image. The data acquisition efficiency of this sequential illumination process can be improved by 3-fold using wavelength-multiplexed R, G and B illumination that simultaneously illuminates the sample, and using a Bayer color image sensor with known or calibrated transmission spectra to digitally demultiplex these three wavelength channels. This demultiplexing step is conventionally used with interpolation-based Bayer demosaicing methods. However, because the pixels of different color channels on a Bayer image sensor chip are not at the same physical location, conventional interpolation-based demosaicing process generates strong color artifacts, especially at rapidly oscillating hologram fringes, which become even more pronounced through digital wave propagation and phase retrieval processes. Here, we demonstrate that by merging the pixel super-resolution framework into the demultiplexing process, such color artifacts can be greatly suppressed. This novel technique, termed demosaiced pixel super-resolution (D-PSR) for digital holographic imaging, achieves very similar color imaging performance compared to conventional sequential R,G,B illumination, with 3-fold improvement in image acquisition time and data-efficiency. We successfully demonstrated the color imaging performance of this approach by imaging stained Pap smears. The D-PSR technique is broadly applicable to high-throughput, high-resolution digital holographic color microscopy techniques that can be used in resource-limited-settings and point-of-care offices.

640 X 480 PtSi MOS infrared imager

NASA Astrophysics Data System (ADS)

Sauer, Donald J.; Shallcross, Frank V.; Hseuh, Fu-Lung; Meray, Grazyna M.; Levine, Peter A.; Gilmartin, Harvey R.; Villani, Thomas S.; Esposito, Benjamin J.; Tower, John R.

1992-09-01

The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 10(superscript 6) electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

Field-portable lensfree tomographic microscope†

PubMed Central

Isikman, Serhan O.; Bishara, Waheb; Sikora, Uzair; Yaglidere, Oguzhan; Yeah, John; Ozcan, Aydogan

2011-01-01

We present a field-portable lensfree tomographic microscope, which can achieve sectional imaging of a large volume (~20 mm3) on a chip with an axial resolution of <7 μm. In this compact tomographic imaging platform (weighing only ~110 grams), 24 light-emitting diodes (LEDs) that are each butt-coupled to a fibre-optic waveguide are controlled through a cost-effective micro-processor to sequentially illuminate the sample from different angles to record lensfree holograms of the sample that is placed on the top of a digital sensor array. In order to generate pixel super-resolved (SR) lensfree holograms and hence digitally improve the achievable lateral resolution, multiple sub-pixel shifted holograms are recorded at each illumination angle by electromagnetically actuating the fibre-optic waveguides using compact coils and magnets. These SR projection holograms obtained over an angular range of ~50° are rapidly reconstructed to yield projection images of the sample, which can then be back-projected to compute tomograms of the objects on the sensor-chip. The performance of this compact and light-weight lensfree tomographic microscope is validated by imaging micro-beads of different dimensions as well as a Hymenolepis nana egg, which is an infectious parasitic flatworm. Achieving a decent three-dimensional spatial resolution, this field-portable on-chip optical tomographic microscope might provide a useful toolset for telemedicine and high-throughput imaging applications in resource-poor settings. PMID:21573311

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

A digitalized silicon microgyroscope based on embedded FPGA.

PubMed

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-09-27

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

PubMed Central

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-01-01

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

Self-digitization chip for single-cell genotyping of cancer-related mutations

PubMed Central

Monroe, Luke D.; Kreutz, Jason E.; Schneider, Thomas; Fujimoto, Bryant S.; Chiu, Daniel T.; Radich, Jerald P.; Paguirigan, Amy L.

2018-01-01

Cancer is a heterogeneous disease, and patient-level genetic assessments can guide therapy choice and impact prognosis. However, little is known about the impact of genetic variability within a tumor, intratumoral heterogeneity (ITH), on disease progression or outcome. Current approaches using bulk tumor specimens can suggest the presence of ITH, but only single-cell genetic methods have the resolution to describe the underlying clonal structures themselves. Current techniques tend to be labor and resource intensive and challenging to characterize with respect to sources of biological and technical variability. We have developed a platform using a microfluidic self-digitization chip to partition cells in stationary volumes for cell imaging and allele-specific PCR. Genotyping data from only confirmed single-cell volumes is obtained and subject to a variety of relevant quality control assessments such as allele dropout, false positive, and false negative rates. We demonstrate single-cell genotyping of the NPM1 type A mutation, an important prognostic indicator in acute myeloid leukemia, on single cells of the cell line OCI-AML3, describing a more complex zygosity distribution than would be predicted via bulk analysis. PMID:29718986

Self-digitization chip for single-cell genotyping of cancer-related mutations.

PubMed

Thompson, Alison M; Smith, Jordan L; Monroe, Luke D; Kreutz, Jason E; Schneider, Thomas; Fujimoto, Bryant S; Chiu, Daniel T; Radich, Jerald P; Paguirigan, Amy L

2018-01-01

Cancer is a heterogeneous disease, and patient-level genetic assessments can guide therapy choice and impact prognosis. However, little is known about the impact of genetic variability within a tumor, intratumoral heterogeneity (ITH), on disease progression or outcome. Current approaches using bulk tumor specimens can suggest the presence of ITH, but only single-cell genetic methods have the resolution to describe the underlying clonal structures themselves. Current techniques tend to be labor and resource intensive and challenging to characterize with respect to sources of biological and technical variability. We have developed a platform using a microfluidic self-digitization chip to partition cells in stationary volumes for cell imaging and allele-specific PCR. Genotyping data from only confirmed single-cell volumes is obtained and subject to a variety of relevant quality control assessments such as allele dropout, false positive, and false negative rates. We demonstrate single-cell genotyping of the NPM1 type A mutation, an important prognostic indicator in acute myeloid leukemia, on single cells of the cell line OCI-AML3, describing a more complex zygosity distribution than would be predicted via bulk analysis.

A new electrowetting lab-on-a-chip platform based on programmable and virtual wall-less channels

NASA Astrophysics Data System (ADS)

Banerjee, Ananda; Kreit, Eric; Dhindsa, Manjeet; Heikenfeld, Jason; Papautsky, Ian

2011-02-01

Microscale liquid handling based on electrowetting has been previously demonstrated by several groups. Such liquid manipulation however is limited to control of individual droplets, aptly termed digital microfluidics. The inability to form continuous channels thus prevents conventional microfluidic sample manipulation and analysis approaches, such as electroosmosis and electrophoresis. In this paper, we discuss our recent progress on the development of electrowettingbased virtual channels. These channels can be created and reconfigured on-demand and preserve their shape without external stimulus. We also discuss recent progress towards demonstrating electroosmotic flows in such microchannels for fluid transport. This would permit a variety of basic functionalities in this new platform including sample transport and mixing between various functional areas of the chip.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Digital Microfluidics Assisted Sealing of Individual Magnetic Particles in Femtoliter-Sized Reaction Wells for Single-Molecule Detection.

PubMed

Decrop, Deborah; Ruiz, Elena Pérez; Kumar, Phalguni Tewari; Tripodi, Lisa; Kokalj, Tadej; Lammertyn, Jeroen

2017-01-01

Digital microfluidics has emerged in the last years as a promising liquid handling technology for a variety of applications. Here, we describe in detail how to build up an electrowetting-on-dielectric-based digital microfluidic chip with unique advantages for performing single-molecule detection. We illustrate how superparamagnetic particles can be printed with very high loading efficiency (over 98 %) and single-particle resolution in the microwell array patterned in the Teflon-AF ® surface of the grounding plate of the chip. Finally, the potential of the device for its application to single-molecule detection is demonstrated by the ultrasensitive detection of the biotinylated enzyme β-Galactosidase captured on streptavidin-coated particles in the described platform.

System-on-Chip Design and Implementation

ERIC Educational Resources Information Center

Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.

2010-01-01

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant…

MEDIPIX: a VLSI chip for a GaAs pixel detector for digital radiology

NASA Astrophysics Data System (ADS)

Amendolia, S. R.; Bertolucci, E.; Bisogni, M. G.; Bottigli, U.; Ceccopieri, A.; Ciocci, M. A.; Conti, M.; Delogu, P.; Fantacci, M. E.; Maestro, P.; Marzulli, V.; Pernigotti, E.; Romeo, N.; Rosso, V.; Rosso, P.; Stefanini, A.; Stumbo, S.

1999-02-01

A GaAs pixel detector designed for digital mammography, equipped with a 36-channel single photon counting discrete read-out electronics, was tested using a test object developed for quality control purposes in mammography. Each pixel was 200×200 μm 2 large, and 200 μm deep. The choice of GaAs with respect to silicon (largely used in other applications and with a more established technique) has been made because of the much better detection efficiency at mammographic energies, combined with a very good charge collection efficiency achieved thanks to new ohmic contacts. This GaAs detector is able to perform a measurement of low-contrast details, with minimum contrast lower (nearly a factor two) than that typically achievable with standard mammographic film+screen systems in the same conditions of clinical routine. This should allow for an earlier diagnosis of breast tumour masses. Due to these encouraging results, the next step in the evolution of our imaging system based on GaAs detectors has been the development of a VLSI front-end prototype chip (MEDIPIX ) in order to cover a much larger diagnostic area. The chip reads 64×64 channels in single photon counting mode, each one 170 μm wide. Each channel contains also a test input where a signal can be simulated, injecting a known charge through a 16 f F capacitor. Fake signals have been injected via the test input measuring and equalizing minimum thresholds for all the channels. On an average, in most of the performing chips available up to now, we have found that it is possible to set a threshold as low as 1800 electrons with an RMS of 150 electrons (10 standard deviations lower than the 20 keV photon signal roughly equivalent to 4500 electrons). The detector, bump-bonded to the chip, will be tested and a ladder of detectors will be prepared to be able to scan large surface objects.

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

NASA Astrophysics Data System (ADS)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

Size, shape and flow characterization of ground wood chip and ground wood pellet particles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rezaei, Hamid; Lim, C. Jim; Lau, Anthony

Size, shape and density of biomass particles influence their transportation, fluidization, rates of drying and thermal decomposition. Pelleting wood particles increases the particle density and reduces the variability of physical properties among biomass particles. In this study, pine chips prepared for pulping and commercially produced pine pellets were ground in a hammer mill using grinder screens of 3.2, 6.3, 12.7 and 25.4mmperforations. Pellets consumed about 7 times lower specific grinding energy than chips to produce the same size of particles. Grinding pellets produced the smaller particles with narrower size distribution than grinding chips. Derived shape factors in digital image analysismore » showed that chip particles were rectangular and had the aspect ratios about one third of pellet particles. Pellet particles were more circular shape. The mechanical sieving underestimated the actual particle size and did not represent the size of particles correctly. Instead, digital imaging is preferred. Angle of repose and compressibility tests represented the flow properties of ground particles. Pellet particles made a less compacted bulk, had lower cohesion and did flow easier in a pile of particles. In conclusion, particle shape affected the flow properties more than particle size« less

Size, shape and flow characterization of ground wood chip and ground wood pellet particles

DOE PAGES

Rezaei, Hamid; Lim, C. Jim; Lau, Anthony; ...

2016-07-11

Size, shape and density of biomass particles influence their transportation, fluidization, rates of drying and thermal decomposition. Pelleting wood particles increases the particle density and reduces the variability of physical properties among biomass particles. In this study, pine chips prepared for pulping and commercially produced pine pellets were ground in a hammer mill using grinder screens of 3.2, 6.3, 12.7 and 25.4mmperforations. Pellets consumed about 7 times lower specific grinding energy than chips to produce the same size of particles. Grinding pellets produced the smaller particles with narrower size distribution than grinding chips. Derived shape factors in digital image analysismore » showed that chip particles were rectangular and had the aspect ratios about one third of pellet particles. Pellet particles were more circular shape. The mechanical sieving underestimated the actual particle size and did not represent the size of particles correctly. Instead, digital imaging is preferred. Angle of repose and compressibility tests represented the flow properties of ground particles. Pellet particles made a less compacted bulk, had lower cohesion and did flow easier in a pile of particles. In conclusion, particle shape affected the flow properties more than particle size« less

Computation of dark frames in digital imagers

NASA Astrophysics Data System (ADS)

Widenhorn, Ralf; Rest, Armin; Blouke, Morley M.; Berry, Richard L.; Bodegom, Erik

2007-02-01

Dark current is caused by electrons that are thermally exited into the conduction band. These electrons are collected by the well of the CCD and add a false signal to the chip. We will present an algorithm that automatically corrects for dark current. It uses a calibration protocol to characterize the image sensor for different temperatures. For a given exposure time, the dark current of every pixel is characteristic of a specific temperature. The dark current of every pixel can therefore be used as an indicator of the temperature. Hot pixels have the highest signal-to-noise ratio and are the best temperature sensors. We use the dark current of a several hundred hot pixels to sense the chip temperature and predict the dark current of all pixels on the chip. Dark current computation is not a new concept, but our approach is unique. Some advantages of our method include applicability for poorly temperature-controlled camera systems and the possibility of ex post facto dark current correction.

Design of video interface conversion system based on FPGA

NASA Astrophysics Data System (ADS)

Zhao, Heng; Wang, Xiang-jun

2014-11-01

This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

Research on phase locked loop in optical memory servo system

NASA Astrophysics Data System (ADS)

Qin, Liqin; Ma, Jianshe; Zhang, Jianyong; Pan, Longfa; Deng, Ming

2005-09-01

Phase locked loop (PLL) is a closed loop automatic control system, which can track the phase of input signal. It widely applies in each area of electronic technology. This paper research the phase locked loop in optical memory servo area. This paper introduces the configuration of digital phase locked loop (PLL) and phase locked servo system, the control theory, and analyses system's stability. It constructs the phase locked loop experiment system of optical disk spindle servo, which based on special chip. DC motor is main object, this system adopted phase locked servo technique and digital signal processor (DSP) to achieve constant linear velocity (CLV) in controlling optical spindle motor. This paper analyses the factors that affect the stability of phase locked loop in spindle servo system, and discusses the affection to the optical disk readout signal and jitter due to the stability of phase locked loop.

High-definition video display based on the FPGA and THS8200

NASA Astrophysics Data System (ADS)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

NASA Technical Reports Server (NTRS)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Novel method to detect microRNAs using chip-based QuantStudio 3D digital PCR.

PubMed

Conte, Davide; Verri, Carla; Borzi, Cristina; Suatoni, Paola; Pastorino, Ugo; Sozzi, Gabriella; Fortunato, Orazio

2015-10-23

Research efforts for the management of cancer, in particular for lung cancer, are directed to identify new strategies for its early detection. MicroRNAs (miRNAs) are a new promising class of circulating biomarkers for cancer detection, but lack of consensus on data normalization methods has affected the diagnostic potential of circulating miRNAs. There is a growing interest in techniques that allow an absolute quantification of miRNAs which could be useful for early diagnosis. Recently, digital PCR, mainly based on droplets generation, emerged as an affordable technology for precise and absolute quantification of nucleic acids. In this work, we described a new interesting approach for profiling circulating miRNAs in plasma samples using a chip-based platform, the QuantStudio 3D digital PCR. The proposed method was validated using synthethic oligonucleotide at serial dilutions in plasma samples of lung cancer patients and in lung tissues and cell lines. Given its reproducibility and reliability, our approach could be potentially applied for the identification and quantification of miRNAs in other biological samples such as circulating exosomes or protein complexes. As chip-digital PCR becomes more established, it would be a robust tool for quantitative assessment of miRNA copy number for diagnosis of lung cancer and other diseases.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Development of a digital microfluidic platform for point of care testing

PubMed Central

Sista, Ramakrishna; Hua, Zhishan; Thwar, Prasanna; Sudarsan, Arjun; Srinivasan, Vijay; Eckhardt, Allen; Pollack, Michael; Pamula, Vamsee

2009-01-01

Point of care testing is playing an increasingly important role in improving the clinical outcome in health care management. The salient features of a point of care device are quick results, integrated sample preparation and processing, small sample volumes, portability, multifunctionality and low cost. In this paper, we demonstrate some of these salient features utilizing an electrowetting-based Digital Microfluidic platform. We demonstrate the performance of magnetic bead-based immunoassays (cardiac troponin I) on a digital microfluidic cartridge in less than 8 minutes using whole blood samples. Using the same microfluidic cartridge, a 40-cycle real-time polymerase chain reaction was performed within 12 minutes by shuttling a droplet between two thermal zones. We further demonstrate, on the same cartridge, the capability to perform sample preparation for bacterial and fungal infectious disease pathogens (methicillin-resistance Staphylococcus aureus and Candida albicans) and for human genomic DNA using magnetic beads. In addition to rapid results and integrated sample preparation, electrowetting-based digital microfluidic instruments are highly portable because fluid pumping is performed electronically. All the digital microfluidic chips presented here were fabricated on printed circuit boards utilizing mass production techniques that keep the cost of the chip low. Due to the modularity and scalability afforded by digital microfluidics, multifunctional testing capability, such as combinations within and between immunoassays, DNA amplification, and enzymatic assays, can be brought to the point of care at a relatively low cost because a single chip can be configured in software for different assays required along the path of care. PMID:19023472

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krzyżanowska, A.; Deptuch, G. W.; Maj, P.

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operationmore » of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.« less

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

NASA Astrophysics Data System (ADS)

Marconi, S.; Conti, E.; Christiansen, J.; Placidi, P.

2018-05-01

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted.

SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

NASA Astrophysics Data System (ADS)

Adolfsson, J.; Ayala Pabon, A.; Bregant, M.; Britton, C.; Brulin, G.; Carvalho, D.; Chambert, V.; Chinellato, D.; Espagnon, B.; Hernandez Herrera, H. D.; Ljubicic, T.; Mahmood, S. M.; Mjörnmark, U.; Moraes, D.; Munhoz, M. G.; Noël, G.; Oskarsson, A.; Osterman, L.; Pilyar, A.; Read, K.; Ruette, A.; Russo, P.; Sanches, B. C. S.; Severo, L.; Silvermyr, D.; Suire, C.; Tambave, G. J.; Tun-Lanoë, K. M. M.; van Noije, W.; Velure, A.; Vereschagin, S.; Wanlin, E.; Weber, T. O.; Zaporozhets, S.

2017-04-01

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Actuation of digital micro drops by electrowetting on open microfluidic chips fabricated in photolithography.

PubMed

Ko, Hyojin; Lee, Jeong Soo; Jung, Chan-Hee; Choi, Jae-Hak; Kwon, Oh-Sun; Shin, Kwanwoo

2014-08-01

Basic manipulations of discrete liquid drops on opened microfluidic chips based on electrowetting on dielectrics were described. While most developed microfluidic chips are closed systems equipped with a top plate to cover mechanically and to contact electrically to drop samples, our chips are opened systems with a single plate without any electric contact to drops directly. The chips consist of a linear array of patterned electrodes at 1.8 mm pitch was fabricated on a glass plate coated with thin hydrophobic and dielectric layers by using various methods including photolithography, spin coating and ion sputtering. Several actuations such as lateral oscillation, colliding mergence and translational motion for 3-10 μL water drops have been demonstrated satisfactory. All these kinetic performances of opened chips were similar to those of closed chip systems, indicating superiority of a none-contact method for the transport of drops on opened microfluidic chips actuated by using electrowetting technique.

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

NASA Astrophysics Data System (ADS)

Dickerson, Samuel J.; Noyola, Arnaldo J.; Levitan, Steven P.; Chiarulli, Donald M.

2007-01-01

In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer, which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology, we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack. We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with macro-scale optical techniques.

Alpha Control - A new Concept in SPM Control

NASA Astrophysics Data System (ADS)

Spizig, P.; Sanchen, D.; Volswinkler, G.; Ibach, W.; Koenen, J.

2006-03-01

Controlling modern Scanning Probe Microscopes demands highly sophisticated electronics. While flexibility and powerful computing power is of great importance in facilitating the variety of measurement modes, extremely low noise is also a necessity. Accordingly, modern SPM Controller designs are based on digital electronics to overcome the drawbacks of analog designs. While todays SPM controllers are based on DSPs or Microprocessors and often still incorporate analog parts, we are now introducing a completely new approach: Using a Field Programmable Gate Array (FPGA) to implement the digital control tasks allows unrivalled data processing speed by computing all tasks in parallel within a single chip. Time consuming task switching between data acquisition, digital filtering, scanning and the computing of feedback signals can be completely avoided. Together with a star topology to avoid any bus limitations in accessing the variety of ADCs and DACs, this design guarantees for the first time an entirely deterministic timing capability in the nanosecond regime for all tasks. This becomes especially useful for any external experiments which must be synchronized with the scan or for high speed scans that require not only closed loop control of the scanner, but also dynamic correction of the scan movement. Delicate samples additionally benefit from extremely high sample rates, allowing highly resolved signals and low noise levels.

Multi-angle lensless digital holography for depth resolved imaging on a chip.

PubMed

Su, Ting-Wei; Isikman, Serhan O; Bishara, Waheb; Tseng, Derek; Erlinger, Anthony; Ozcan, Aydogan

2010-04-26

A multi-angle lensfree holographic imaging platform that can accurately characterize both the axial and lateral positions of cells located within multi-layered micro-channels is introduced. In this platform, lensfree digital holograms of the micro-objects on the chip are recorded at different illumination angles using partially coherent illumination. These digital holograms start to shift laterally on the sensor plane as the illumination angle of the source is tilted. Since the exact amount of this lateral shift of each object hologram can be calculated with an accuracy that beats the diffraction limit of light, the height of each cell from the substrate can be determined over a large field of view without the use of any lenses. We demonstrate the proof of concept of this multi-angle lensless imaging platform by using light emitting diodes to characterize various sized microparticles located on a chip with sub-micron axial and lateral localization over approximately 60 mm(2) field of view. Furthermore, we successfully apply this lensless imaging approach to simultaneously characterize blood samples located at multi-layered micro-channels in terms of the counts, individual thicknesses and the volumes of the cells at each layer. Because this platform does not require any lenses, lasers or other bulky optical/mechanical components, it provides a compact and high-throughput alternative to conventional approaches for cytometry and diagnostics applications involving lab on a chip systems.

Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip"

NASA Astrophysics Data System (ADS)

Sokolovskiy, A. V.; Dmitriev, D. D.; Veisov, E. A.; Gladyshev, A. B.

2018-05-01

The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.

System on a Chip (SoC) Overview

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

PubMed

Nose, Atsushi; Yamazaki, Tomohiro; Katayama, Hironobu; Uehara, Shuji; Kobayashi, Masatsugu; Shida, Sayaka; Odahara, Masaki; Takamiya, Kenichi; Matsumoto, Shizunori; Miyashita, Leo; Watanabe, Yoshihiro; Izawa, Takashi; Muramatsu, Yoshinori; Nitta, Yoshikazu; Ishikawa, Masatoshi

2018-04-24

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

Traffic Monitor

NASA Technical Reports Server (NTRS)

1995-01-01

Intelligent Vision Systems, Inc. (InVision) needed image acquisition technology that was reliable in bad weather for its TDS-200 Traffic Detection System. InVision researchers used information from NASA Tech Briefs and assistance from Johnson Space Center to finish the system. The NASA technology used was developed for Earth-observing imaging satellites: charge coupled devices, in which silicon chips convert light directly into electronic or digital images. The TDS-200 consists of sensors mounted above traffic on poles or span wires, enabling two sensors to view an intersection; a "swing and sway" feature to compensate for movement of the sensors; a combination of electronic shutter and gain control; and sensor output to an image digital signal processor, still frame video and optionally live video.

The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

NASA Astrophysics Data System (ADS)

Fu, Y.; Brezina, C.; Desch, K.; Poikela, T.; Llopart, X.; Campbell, M.; Massimiliano, D.; Gromov, V.; Kluit, R.; van Beauzekom, M.; Zappon, F.; Zivkovic, V.

2014-01-01

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

NASA Technical Reports Server (NTRS)

Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan;

Field-portable lensfree tomographic microscope.

PubMed

Isikman, Serhan O; Bishara, Waheb; Sikora, Uzair; Yaglidere, Oguzhan; Yeah, John; Ozcan, Aydogan

2011-07-07

We present a field-portable lensfree tomographic microscope, which can achieve sectional imaging of a large volume (∼20 mm(3)) on a chip with an axial resolution of <7 μm. In this compact tomographic imaging platform (weighing only ∼110 grams), 24 light-emitting diodes (LEDs) that are each butt-coupled to a fibre-optic waveguide are controlled through a cost-effective micro-processor to sequentially illuminate the sample from different angles to record lensfree holograms of the sample that is placed on the top of a digital sensor array. In order to generate pixel super-resolved (SR) lensfree holograms and hence digitally improve the achievable lateral resolution, multiple sub-pixel shifted holograms are recorded at each illumination angle by electromagnetically actuating the fibre-optic waveguides using compact coils and magnets. These SR projection holograms obtained over an angular range of ±50° are rapidly reconstructed to yield projection images of the sample, which can then be back-projected to compute tomograms of the objects on the sensor-chip. The performance of this compact and light-weight lensfree tomographic microscope is validated by imaging micro-beads of different dimensions as well as a Hymenolepis nana egg, which is an infectious parasitic flatworm. Achieving a decent three-dimensional spatial resolution, this field-portable on-chip optical tomographic microscope might provide a useful toolset for telemedicine and high-throughput imaging applications in resource-poor settings. This journal is © The Royal Society of Chemistry 2011

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Vertical Integration of System-on-Chip Concepts in the Digital Design Curriculum

ERIC Educational Resources Information Center

Tang, Ying; Head, L. M.; Ramachandran, R. P.; Chatman, L. M.

2011-01-01

The rapid evolution of System-on-Chip (SoC) challenges academic curricula to keep pace with multidisciplinary/interdisciplinary system thinking. This paper presents a curricular prototype that cuts across artificial course boundaries and provides a meaningful exploration of diverse facets of SoC design. Specifically, experimental contents of a…

Increasing Electrochemiluminescence Intensity of a Wireless Electrode Array Chip by Thousands of Times Using a Diode for Sensitive Visual Detection by a Digital Camera.

PubMed

Qi, Liming; Xia, Yong; Qi, Wenjing; Gao, Wenyue; Wu, Fengxia; Xu, Guobao

2016-01-19

Both a wireless electrochemiluminescence (ECL) electrode microarray chip and the dramatic increase in ECL by embedding a diode in an electromagnetic receiver coil have been first reported. The newly designed device consists of a chip and a transmitter. The chip has an electromagnetic receiver coil, a mini-diode, and a gold electrode array. The mini-diode can rectify alternating current into direct current and thus enhance ECL intensities by 18 thousand times, enabling a sensitive visual detection using common cameras or smart phones as low cost detectors. The detection limit of hydrogen peroxide using a digital camera is comparable to that using photomultiplier tube (PMT)-based detectors. Coupled with a PMT-based detector, the device can detect luminol with higher sensitivity with linear ranges from 10 nM to 1 mM. Because of the advantages including high sensitivity, high throughput, low cost, high portability, and simplicity, it is promising in point of care testing, drug screening, and high throughput analysis.

A Digitally Programmable Cytomorphic Chip for Simulation of Arbitrary Biochemical Reaction Networks.

PubMed

Woo, Sung Sik; Kim, Jaewook; Sarpeshkar, Rahul

2018-04-01

Prior work has shown that compact analog circuits can faithfully represent and model fundamental biomolecular circuits via efficient log-domain cytomorphic transistor equivalents. Such circuits have emphasized basis functions that are dominant in genetic transcription and translation networks and deoxyribonucleic acid (DNA)-protein binding. Here, we report a system featuring digitally programmable 0.35 μm BiCMOS analog cytomorphic chips that enable arbitrary biochemical reaction networks to be exactly represented thus enabling compact and easy composition of protein networks as well. Since all biomolecular networks can be represented as chemical reaction networks, our protein networks also include the former genetic network circuits as a special case. The cytomorphic analog protein circuits use one fundamental association-dissociation-degradation building-block circuit that can be configured digitally to exactly represent any zeroth-, first-, and second-order reaction including loading, dynamics, nonlinearity, and interactions with other building-block circuits. To address a divergence issue caused by random variations in chip fabrication processes, we propose a unique way of performing computation based on total variables and conservation laws, which we instantiate at both the circuit and network levels. Thus, scalable systems that operate with finite error over infinite time can be built. We show how the building-block circuits can be composed to form various network topologies, such as cascade, fan-out, fan-in, loop, dimerization, or arbitrary networks using total variables. We demonstrate results from a system that combines interacting cytomorphic chips to simulate a cancer pathway and a glycolysis pathway. Both simulations are consistent with conventional software simulations. Our highly parallel digitally programmable analog cytomorphic systems can lead to a useful design, analysis, and simulation tool for studying arbitrary large-scale biological networks in systems and synthetic biology.

Integrated chemical/biochemical sample collection, pre-concentration, and analysis on a digital microfluidic lab-on-a-chip platform

NASA Astrophysics Data System (ADS)

Fair, Richard B.; Khlystov, A.; Srinivasan, Vijay; Pamula, Vamsee K.; Weaver, Kathryn N.

2004-12-01

An ideal on-site chemical/biochemical analysis system must be inexpensive, sensitive, fully automated and integrated, reliable, and compatible with a broad range of samples. The advent of digital microfluidic lab-on-a-chip (LoC) technology offers such a detection system due to the advantages in portability, reduction of the volumes of the sample and reagents, faster analysis times, increased automation, low power consumption, compatibility with mass manufacturing, and high throughput. We describe progress towards integrating sample collection onto a digital microfluidic LoC that is a component of a cascade impactor device. The sample collection is performed by impacting airborne particles directly onto the surface of the chip. After the collection phase, the surface of the chip is washed with a micro-droplet of solvent. The droplet will be digitally directed across the impaction surface, dissolving sample constituents. Because of the very small droplet volume used for extraction of the sample from a wide colection area, the resulting solution is realatively concentrated and the analytes can be detected after a very short sampling time (1 min) due to such pre-concentration. After the washing phase, the droplet is mixed with specific reagents that produce colored reaction products. The concentration of the analyte is quantitatively determined by measuring absorption at target wavelengths using a simple light emitting diode and photodiode setup. Specific applications include automatic measurements of major inorganic ions in aerosols, such as sulfate, nitrate and ammonium, with a time resolution of 1 min and a detection limit of 30 nm/m3. We have already demonstrated the detection and quantification of nitroaromatic explosives without integrating the sample collection. Other applications being developed include airborne bioagent detection.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

MuTRiG: a mixed signal Silicon Photomultiplier readout ASIC with high timing resolution and gigabit data link

NASA Astrophysics Data System (ADS)

Chen, H.; Briggl, K.; Eckert, P.; Harion, T.; Munwes, Y.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

2017-01-01

MuTRiG is a mixed signal Silicon Photomultiplier readout ASIC designed in UMC 180 nm CMOS technology for precise timing and high event rate applications in high energy physics experiments and medical imaging. It is dedicated to the readout of the scintillating fiber detector and the scintillating tile detector of the Mu3e experiment. The MuTRiG chip extends the excellent timing performance of the STiCv3 chip with a fast digital readout for high rate applications. The high timing performance of the fully differential SiPM readout channels and 50 ps time binning TDCs are complemented by an upgraded digital readout logic and a 1.28 Gbps LVDS serial data link. The design of the chip and the characterization results of the analog front-end, TDC and the LVDS data link are presented.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Image Understanding. Proceedings of a Workshop Held in Pittsburgh, Pennsylvania on 11-13 September, 1990

DTIC Science & Technology

1990-09-01

performed some preliminary longest piers are about three times the length of a de- experiments to detect the ships in the high resolution stroyer...statistics, and these are coordinates then shipped via a high - speed interface to a host where the stereo triangulation and kinematic control algorithms Grasp...Design: Perception research includes the design of new sensor technologies, such as this hybrid analog/digital chip for a high - speed light-stripe

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

Integration of reconfigurable potentiometric electrochemical sensors into a digital microfluidic platform.

PubMed

Farzbod, Ali; Moon, Hyejin

2018-05-30

This paper presents the demonstration of on-chip fabrication of a potassium-selective sensor array enabled by electrowetting on dielectric digital microfluidics for the first time. This demonstration proves the concept that electrochemical sensors can be seamlessly integrated with sample preparation units in a digital microfluidic platform. More significantly, the successful on-chip fabrication of a sensor array indicates that sensors become reconfigurable and have longer lifetime in a digital microfluidic platform. The on-chip fabrication of ion-selective electrodes includes electroplating Ag followed by forming AgCl layer by chemical oxidation and depositing a thin layer of desired polymer-based ion selective membrane on one of the sensor electrodes. In this study, potassium ionophores work as potassium ion channels and make the membrane selective to potassium ions. This selectiveness results in the voltage difference across the membrane layer, which is correlated with potassium ion concentration. The calibration curve of the fabricated potassium-selective electrode demonstrates the slope of 58 mV/dec for potassium concentration in KCl sample solutions and shows good agreement with the ideal Nernstian response. The proposed sensor platform is an outstanding candidate for a portable home-use for continuous monitoring of ions thanks to its advantages such as easy automation of sample preparation and detection processes, elongated sensor lifetime, minimal membrane and sample consumption, and user-definable/reconfigurable sensor array. Copyright © 2018 Elsevier B.V. All rights reserved.

Next-generation digital camera integration and software development issues

NASA Astrophysics Data System (ADS)

Venkataraman, Shyam; Peters, Ken; Hecht, Richard

1998-04-01

This paper investigates the complexities associated with the development of next generation digital cameras due to requirements in connectivity and interoperability. Each successive generation of digital camera improves drastically in cost, performance, resolution, image quality and interoperability features. This is being accomplished by advancements in a number of areas: research, silicon, standards, etc. As the capabilities of these cameras increase, so do the requirements for both hardware and software. Today, there are two single chip camera solutions in the market including the Motorola MPC 823 and LSI DCAM- 101. Real time constraints for a digital camera may be defined by the maximum time allowable between capture of images. Constraints in the design of an embedded digital camera include processor architecture, memory, processing speed and the real-time operating systems. This paper will present the LSI DCAM-101, a single-chip digital camera solution. It will present an overview of the architecture and the challenges in hardware and software for supporting streaming video in such a complex device. Issues presented include the development of the data flow software architecture, testing and integration on this complex silicon device. The strategy for optimizing performance on the architecture will also be presented.

Hierarchical CAD Tools for Radiation Hardened Mixed Signal Electronic Circuits

DTIC Science & Technology

2005-01-28

11 Figure 3: Schematic of Analog and Digital Components 12 Figure 4: Dose Rate Syntax 14 Figure 5: Single Event Effects (SEE) Syntax 15 Figure 6...Harmony-AMS simulation of a Digital Phase Locked Loop 19 Figure 10: SEE results from DPLL Simulation 20 Figure 11: Published results used for validation...analog and digital circuitry. Combining the analog and digital elements onto a single chip has several advantages, but also creates unique challenges

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Photoelectric radar servo control system based on ARM+FPGA

NASA Astrophysics Data System (ADS)

Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

2016-01-01

In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a large number of experiments verify the reliability of embedded servo control system's functions, the stability of the program and the stability of the hardware circuit. Meanwhile, the system can also achieve the satisfactory of user experience, to achieve a multi-mode motion, real-time motion status monitoring, online system parameter changes and other convenient features.

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Digital telephony analysis model and issues

NASA Astrophysics Data System (ADS)

Keuthan, Lynn M.

1995-09-01

Experts in the fields of digital telephony and communications security have stated the need for an analytical tool for evaluating complex issues. Some important policy issues discussed by experts recently include implementing digital wire-taps, implementation of the 'Clipper Chip', required registration of encryption/decryption keys, and export control of cryptographic equipment. Associated with the implementation of these policies are direct costs resulting from implementation, indirect cost benefits from implementation, and indirect costs resulting from the risks of implementation or factors reducing cost benefits. Presented herein is a model for analyzing digital telephony policies and systems and their associated direct costs and indirect benefit and risk factors. In order to present the structure of the model, issues of national importance and business-related issues are discussed. The various factors impacting the implementation of the associated communications systems and communications security are summarized, and various implementation tradeoffs are compared based on economic benefits/impact. The importance of the issues addressed herein, as well as other digital telephony issues, has greatly increased with the enormous increases in communication system connectivity due to the advance of the National Information Infrastructure.

ChIP-seq.

PubMed

Kim, Tae Hoon; Dekker, Job

2018-05-01

Owing to its digital nature, ChIP-seq has become the standard method for genome-wide ChIP analysis. Using next-generation sequencing platforms (notably the Illumina Genome Analyzer), millions of short sequence reads can be obtained. The densities of recovered ChIP sequence reads along the genome are used to determine the binding sites of the protein. Although a relatively small amount of ChIP DNA is required for ChIP-seq, the current sequencing platforms still require amplification of the ChIP DNA by ligation-mediated PCR (LM-PCR). This protocol, which involves linker ligation followed by size selection, is the standard ChIP-seq protocol using an Illumina Genome Analyzer. The size-selected ChIP DNA is amplified by LM-PCR and size-selected for the second time. The purified ChIP DNA is then loaded into the Genome Analyzer. The ChIP DNA can also be processed in parallel for ChIP-chip results. © 2018 Cold Spring Harbor Laboratory Press.

Spectral Demultiplexing in Holographic and Fluorescent On-chip Microscopy

NASA Astrophysics Data System (ADS)

Sencan, Ikbal; Coskun, Ahmet F.; Sikora, Uzair; Ozcan, Aydogan

2014-01-01

Lensfree on-chip imaging and sensing platforms provide compact and cost-effective designs for various telemedicine and lab-on-a-chip applications. In this work, we demonstrate computational solutions for some of the challenges associated with (i) the use of broadband, partially-coherent illumination sources for on-chip holographic imaging, and (ii) multicolor detection for lensfree fluorescent on-chip microscopy. Specifically, we introduce spectral demultiplexing approaches that aim to digitally narrow the spectral content of broadband illumination sources (such as wide-band light emitting diodes or even sunlight) to improve spatial resolution in holographic on-chip microscopy. We also demonstrate the application of such spectral demultiplexing approaches for wide-field imaging of multicolor fluorescent objects on a chip. These computational approaches can be used to replace e.g., thin-film interference filters, gratings or other optical components used for spectral multiplexing/demultiplexing, which can form a desirable solution for cost-effective and compact wide-field microscopy and sensing needs on a chip.

A single-chip event sequencer and related microcontroller instrumentation for atomic physics research.

PubMed

Eyler, E E

2011-01-01

A 16-bit digital event sequencer with 50 ns resolution and 50 ns trigger jitter is implemented by using an internal 32-bit timer on a dsPIC30F4013 microcontroller, controlled by an easily modified program written in standard C. It can accommodate hundreds of output events, and adjacent events can be spaced as closely as 1.5 μs. The microcontroller has robust 5 V inputs and outputs, allowing a direct interface to common laboratory equipment and other electronics. A USB computer interface and a pair of analog ramp outputs can be added with just two additional chips. An optional display/keypad unit allows direct interaction with the sequencer without requiring an external computer. Minor additions also allow simple realizations of other complex instruments, including a precision high-voltage ramp generator for driving spectrum analyzers or piezoelectric positioners, and a low-cost proportional integral differential controller and lock-in amplifier for laser frequency stabilization with about 100 kHz bandwidth.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

The use of low resistivity substrates for optimal noise reduction, ground referencing, and current conduction in mixed signal ASICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zimmerman, T.

1997-12-01

This paper is distilled from a talk given at the 3rd International Meeting on Front End Electronics in Taos, N.M. on Nov. 7,1997. It is based on experience gained by designing and testing the SVX3 128 channel silicon strip detector readout chip. The SVX3 chip organization is shown in Fig. 1. The Front End section consists of an integrator and analog pipeline designed at Fermilab, and the Back End section is an ADC plus sparsification and readout logic designed at LBL. SVX3 is a deadtimeless readout chip, which means that the front end is acquiring low level analog signals whilemore » the back end is digitizing and reading out digital signals. It is thus a true mixed signal chip, and demands close attention to avoid disastrous coupling from the digital to the analog sections. SVX3 is designed in a bulk CMOS process (i.e., the circuits sit in a silicon substrate). In such a process, the substrate becomes a potential coupling path. This paper discusses the effect of the substrate resistivity on coupling, and also goes into a more general discussion of grounding and referencing in mixed signal designs and how low resistivity substrates can be used to advantage. Finally, an alternative power supply current conduction method for ASICs is presented as an additional advantage which can be obtained with low resistivity substrates. 1 ref., 13 figs., 1 tab.« less

Superconducting Qubit with Integrated Single Flux Quantum Controller Part I: Theory and Fabrication

NASA Astrophysics Data System (ADS)

Beck, Matthew; Leonard, Edward, Jr.; Thorbeck, Ted; Zhu, Shaojiang; Howington, Caleb; Nelson, Jj; Plourde, Britton; McDermott, Robert

As the size of quantum processors grow, so do the classical control requirements. The single flux quantum (SFQ) Josephson digital logic family offers an attractive route to proximal classical control of multi-qubit processors. Here we describe coherent control of qubits via trains of SFQ pulses. We discuss the fabrication of an SFQ-based pulse generator and a superconducting transmon qubit on a single chip. Sources of excess microwave loss stemming from the complex multilayer fabrication of the SFQ circuit are discussed. We show how to mitigate this loss through judicious choice of process workflow and appropriate use of sacrificial protection layers. Present address: IBM T.J. Watson Research Center.

Digital design using selection operations

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor); Cameron, Eric G. (Inventor)

2004-01-01

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Digital microfluidics – a new paradigm for radiochemistry

PubMed Central

Keng, Pei Yuin; van Dam, R. Michael

2016-01-01

The emerging technology of digital microfluidics is opening up the possibility to perform radiochemistry at the microliter scale to produce tracers for positron emission tomography (PET) labeled with fluorine-18 or other isotopes. Working at this volume scale not only reduces reagent costs, but also improves specific activity (SA) by reduction of contamination by the stable isotope. This technology could provide a practical means to routinely prepare high SA tracers for applications such as neuroimaging, and could make it possible to routinely achieve high SA using synthesis strategies such as isotopic exchange. Reagent droplets are controlled electronically, providing high reliability, a compact control system, and flexibility for diverse syntheses with a single chip design. The compact size may enable the development of a self-shielded synthesizer that does not require a hot cell. This article reviews the progress of this technology and its application to the synthesis of PET tracers. PMID:26650206

Low-complexity camera digital signal imaging for video document projection system

NASA Astrophysics Data System (ADS)

Hsia, Shih-Chang; Tsai, Po-Shien

2011-04-01

We present high-performance and low-complexity algorithms for real-time camera imaging applications. The main functions of the proposed camera digital signal processing (DSP) involve color interpolation, white balance, adaptive binary processing, auto gain control, and edge and color enhancement for video projection systems. A series of simulations demonstrate that the proposed method can achieve good image quality while keeping computation cost and memory requirements low. On the basis of the proposed algorithms, the cost-effective hardware core is developed using Verilog HDL. The prototype chip has been verified with one low-cost programmable device. The real-time camera system can achieve 1270 × 792 resolution with the combination of extra components and can demonstrate each DSP function.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

Optimized linear motor and digital PID controller setup used in Mössbauer spectrometer

NASA Astrophysics Data System (ADS)

Kohout, Pavel; Kouřil, Lukáš; Navařík, Jakub; Novák, Petr; Pechoušek, Jiří

2014-10-01

Optimization of a linear motor and digital PID controller setup used in a Mössbauer spectrometer is presented. Velocity driving system with a digital PID feedback subsystem was developed in the LabVIEW graphical environment and deployed on the sbRIO real-time hardware device (National Instruments). The most important data acquisition processes are performed as real-time deterministic tasks on an FPGA chip. Velocity transducer of a double loudspeaker type with a power amplifier circuit is driven by the system. Series of calibration measurements were proceeded to find the optimal setup of the P, I, D parameters together with velocity error signal analysis. The shape and given signal characteristics of the velocity error signal are analyzed in details. Remote applications for controlling and monitoring the PID system from computer or smart phone, respectively, were also developed. The best setup and P, I, D parameters were set and calibration spectrum of α-Fe sample with an average nonlinearity of the velocity scale below 0.08% was collected. Furthermore, the width of the spectral line below 0.30 mm/s was observed. Powerful and complex velocity driving system was designed.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Electrostatically focused addressable field emission array chips (AFEA's) for high-speed massively parallel maskless digital E-beam direct write lithography and scanning electron microscopy

DOEpatents

Thomas, Clarence E.; Baylor, Larry R.; Voelkl, Edgar; Simpson, Michael L.; Paulus, Michael J.; Lowndes, Douglas H.; Whealton, John H.; Whitson, John C.; Wilgen, John B.

2002-12-24

Systems and methods are described for addressable field emission array (AFEA) chips. A method of operating an addressable field-emission array, includes: generating a plurality of electron beams from a pluralitly of emitters that compose the addressable field-emission array; and focusing at least one of the plurality of electron beams with an on-chip electrostatic focusing stack. The systems and methods provide advantages including the avoidance of space-charge blow-up.

A review of digital microfluidics as portable platforms for lab-on a-chip applications.

PubMed

Samiei, Ehsan; Tabrizian, Maryam; Hoorfar, Mina

2016-07-07

Following the development of microfluidic systems, there has been a high tendency towards developing lab-on-a-chip devices for biochemical applications. A great deal of effort has been devoted to improve and advance these devices with the goal of performing complete sets of biochemical assays on the device and possibly developing portable platforms for point of care applications. Among the different microfluidic systems used for such a purpose, digital microfluidics (DMF) shows high flexibility and capability of performing multiplex and parallel biochemical operations, and hence, has been considered as a suitable candidate for lab-on-a-chip applications. In this review, we discuss the most recent advances in the DMF platforms, and evaluate the feasibility of developing multifunctional packages for performing complete sets of processes of biochemical assays, particularly for point-of-care applications. The progress in the development of DMF systems is reviewed from eight different aspects, including device fabrication, basic fluidic operations, automation, manipulation of biological samples, advanced operations, detection, biological applications, and finally, packaging and portability of the DMF devices. Success in developing the lab-on-a-chip DMF devices will be concluded based on the advances achieved in each of these aspects.

Scalable Device for Automated Microbial Electroporation in a Digital Microfluidic Platform.

PubMed

Madison, Andrew C; Royal, Matthew W; Vigneault, Frederic; Chen, Liji; Griffin, Peter B; Horowitz, Mark; Church, George M; Fair, Richard B

2017-09-15

Electrowetting-on-dielectric (EWD) digital microfluidic laboratory-on-a-chip platforms demonstrate excellent performance in automating labor-intensive protocols. When coupled with an on-chip electroporation capability, these systems hold promise for streamlining cumbersome processes such as multiplex automated genome engineering (MAGE). We integrated a single Ti:Au electroporation electrode into an otherwise standard parallel-plate EWD geometry to enable high-efficiency transformation of Escherichia coli with reporter plasmid DNA in a 200 nL droplet. Test devices exhibited robust operation with more than 10 transformation experiments performed per device without cross-contamination or failure. Despite intrinsic electric-field nonuniformity present in the EP/EWD device, the peak on-chip transformation efficiency was measured to be 8.6 ± 1.0 × 10 8 cfu·μg -1 for an average applied electric field strength of 2.25 ± 0.50 kV·mm -1 . Cell survival and transformation fractions at this electroporation pulse strength were found to be 1.5 ± 0.3 and 2.3 ± 0.1%, respectively. Our work expands the EWD toolkit to include on-chip microbial electroporation and opens the possibility of scaling advanced genome engineering methods, like MAGE, into the submicroliter regime.

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging.

PubMed

Attarzadeh, Hourieh; Xu, Ye; Ytterdal, Trond

2017-10-01

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

Three levels of neuroelectronic interfacing: silicon chips with ion channels, nerve cells, and brain tissue.

PubMed

Fromherz, Peter

2006-12-01

We consider the direct electrical interfacing of semiconductor chips with individual nerve cells and brain tissue. At first, the structure of the cell-chip contact is studied. Then we characterize the electrical coupling of ion channels--the electrical elements of nerve cells--with transistors and capacitors in silicon chips. On that basis it is possible to implement signal transmission between microelectronics and the microionics of nerve cells in both directions. Simple hybrid neuroelectronic systems are assembled with neuron pairs and with small neuronal networks. Finally, the interfacing with capacitors and transistors is extended to brain tissue cultured on silicon chips. The application of highly integrated silicon chips allows an imaging of neuronal activity with high spatiotemporal resolution. The goal of the work is an integration of neuronal network dynamics with digital electronics on a microscopic level with respect to experiments in brain research, medical prosthetics, and information technology.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

NASA Astrophysics Data System (ADS)

Marconi, S.; Orfanelli, S.; Karagounis, M.; Hemperek, T.; Christiansen, J.; Placidi, P.

2017-02-01

A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level.

Study of optical techniques for the Ames unitary wind tunnel: Digital image processing, part 6

NASA Technical Reports Server (NTRS)

Lee, George

1993-01-01

A survey of digital image processing techniques and processing systems for aerodynamic images has been conducted. These images covered many types of flows and were generated by many types of flow diagnostics. These include laser vapor screens, infrared cameras, laser holographic interferometry, Schlieren, and luminescent paints. Some general digital image processing systems, imaging networks, optical sensors, and image computing chips were briefly reviewed. Possible digital imaging network systems for the Ames Unitary Wind Tunnel were explored.

Blinded evaluation of the effects of high definition and magnification on perceived image quality in laryngeal imaging.

PubMed

Otto, Kristen J; Hapner, Edie R; Baker, Michael; Johns, Michael M

2006-02-01

Advances in commercial video technology have improved office-based laryngeal imaging. This study investigates the perceived image quality of a true high-definition (HD) video camera and the effect of magnification on laryngeal videostroboscopy. We performed a prospective, dual-armed, single-blinded analysis of a standard laryngeal videostroboscopic examination comparing 3 separate add-on camera systems: a 1-chip charge-coupled device (CCD) camera, a 3-chip CCD camera, and a true 720p (progressive scan) HD camera. Displayed images were controlled for magnification and image size (20-inch [50-cm] display, red-green-blue, and S-video cable for 1-chip and 3-chip cameras; digital visual interface cable and HD monitor for HD camera). Ten blinded observers were then asked to rate the following 5 items on a 0-to-100 visual analog scale: resolution, color, ability to see vocal fold vibration, sense of depth perception, and clarity of blood vessels. Eight unblinded observers were then asked to rate the difference in perceived resolution and clarity of laryngeal examination images when displayed on a 10-inch (25-cm) monitor versus a 42-inch (105-cm) monitor. A visual analog scale was used. These monitors were controlled for actual resolution capacity. For each item evaluated, randomized block design analysis demonstrated that the 3-chip camera scored significantly better than the 1-chip camera (p < .05). For the categories of color and blood vessel discrimination, the 3-chip camera scored significantly better than the HD camera (p < .05). For magnification alone, observers rated the 42-inch monitor statistically better than the 10-inch monitor. The expense of new medical technology must be judged against its added value. This study suggests that HD laryngeal imaging may not add significant value over currently available video systems, in perceived image quality, when a small monitor is used. Although differences in clarity between standard and HD cameras may not be readily apparent on small displays, a large display size coupled with HD technology may impart improved diagnosis of subtle vocal fold lesions and vibratory anomalies.

A novel digital image sensor with row wise gain compensation for Hyper Spectral Imager (HySI) application

NASA Astrophysics Data System (ADS)

Lin, Shengmin; Lin, Chi-Pin; Wang, Weng-Lyang; Hsiao, Feng-Ke; Sikora, Robert

2009-08-01

A 256x512 element digital image sensor has been developed which has a large pixel size, slow scan and low power consumption for Hyper Spectral Imager (HySI) applications. The device is a mixed mode, silicon on chip (SOC) IC. It combines analog circuitry, digital circuitry and optical sensor circuitry into a single chip. This chip integrates a 256x512 active pixel sensor array, a programming gain amplifier (PGA) for row wise gain setting, I2C interface, SRAM, 12 bit analog to digital convertor (ADC), voltage regulator, low voltage differential signal (LVDS) and timing generator. The device can be used for 256 pixels of spatial resolution and 512 bands of spectral resolution ranged from 400 nm to 950 nm in wavelength. In row wise gain readout mode, one can set a different gain on each row of the photo detector by storing the gain setting data on the SRAM thru the I2C interface. This unique row wise gain setting can be used to compensate the silicon spectral response non-uniformity problem. Due to this unique function, the device is suitable for hyper-spectral imager applications. The HySI camera located on-board the Chandrayaan-1 satellite, was successfully launched to the moon on Oct. 22, 2008. The device is currently mapping the moon and sending back excellent images of the moon surface. The device design and the moon image data will be presented in the paper.

A 256×256 low-light-level CMOS imaging sensor with digital CDS

NASA Astrophysics Data System (ADS)

Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

2016-10-01

In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

Monte Carlo Modeling-Based Digital Loop-Mediated Isothermal Amplification on a Spiral Chip for Absolute Quantification of Nucleic Acids.

PubMed

Xia, Yun; Yan, Shuangqian; Zhang, Xian; Ma, Peng; Du, Wei; Feng, Xiaojun; Liu, Bi-Feng

2017-03-21

Digital loop-mediated isothermal amplification (dLAMP) is an attractive approach for absolute quantification of nucleic acids with high sensitivity and selectivity. Theoretical and numerical analysis of dLAMP provides necessary guidance for the design and analysis of dLAMP devices. In this work, a mathematical model was proposed on the basis of the Monte Carlo method and the theories of Poisson statistics and chemometrics. To examine the established model, we fabricated a spiral chip with 1200 uniform and discrete reaction chambers (9.6 nL) for absolute quantification of pathogenic DNA samples by dLAMP. Under the optimized conditions, dLAMP analysis on the spiral chip realized quantification of nucleic acids spanning over 4 orders of magnitude in concentration with sensitivity as low as 8.7 × 10 -2 copies/μL in 40 min. The experimental results were consistent with the proposed mathematical model, which could provide useful guideline for future development of dLAMP devices.

Wide-field computational imaging of pathology slides using lens-free on-chip microscopy.

PubMed

Greenbaum, Alon; Zhang, Yibo; Feizi, Alborz; Chung, Ping-Luen; Luo, Wei; Kandukuri, Shivani R; Ozcan, Aydogan

2014-12-17

Optical examination of microscale features in pathology slides is one of the gold standards to diagnose disease. However, the use of conventional light microscopes is partially limited owing to their relatively high cost, bulkiness of lens-based optics, small field of view (FOV), and requirements for lateral scanning and three-dimensional (3D) focus adjustment. We illustrate the performance of a computational lens-free, holographic on-chip microscope that uses the transport-of-intensity equation, multi-height iterative phase retrieval, and rotational field transformations to perform wide-FOV imaging of pathology samples with comparable image quality to a traditional transmission lens-based microscope. The holographically reconstructed image can be digitally focused at any depth within the object FOV (after image capture) without the need for mechanical focus adjustment and is also digitally corrected for artifacts arising from uncontrolled tilting and height variations between the sample and sensor planes. Using this lens-free on-chip microscope, we successfully imaged invasive carcinoma cells within human breast sections, Papanicolaou smears revealing a high-grade squamous intraepithelial lesion, and sickle cell anemia blood smears over a FOV of 20.5 mm(2). The resulting wide-field lens-free images had sufficient image resolution and contrast for clinical evaluation, as demonstrated by a pathologist's blinded diagnosis of breast cancer tissue samples, achieving an overall accuracy of ~99%. By providing high-resolution images of large-area pathology samples with 3D digital focus adjustment, lens-free on-chip microscopy can be useful in resource-limited and point-of-care settings. Copyright © 2014, American Association for the Advancement of Science.

A poly(dimethylsiloxane) microfluidic sheet reversibly adhered on a glass plate for creation of emulsion droplets for droplet digital PCR.

PubMed

Nakashoji, Yuta; Tanaka, Hironari; Tsukagoshi, Kazuhiko; Hashimoto, Masahiko

2017-01-01

A PDMS microfluidic chip with T-junction channel geometry, two inlet reservoirs, and one outlet reservoir was reversibly adhered on a glass plate through the viscoelastic properties of PDMS. This formed a detachable microfluidic device for creation of water-in-oil emulsion droplets that were used as discrete reaction compartments for the droplet digital PCR. The PDMS/glass device could continuously produce monodisperse droplets without leakage of fluids using a vacuum-driven autonomous micropumping method. This droplet preparation technique only required evacuation of air dissolved in the PDMS before loading of oil and aqueous phases into separate inlet reservoirs. Degassing of the PDMS chip at approximately 300 Pa for 1.5 h in a vacuum desiccator gave 40 000 droplets in 80 min, which corresponded to a generation frequency of up to nine droplets per second. Over multiple runs the droplet creation was very reproducible, and the size reproducibility of generated droplets (polydispersity of up to 4.1%) was comparable to that acquired using other microfluidic droplet preparation techniques. Because the PDMS chip can be peeled off the glass plate, blocked channels can easily be fixed when they arise, and this extends the lifetime of the chip. Single DNA molecules partitioned into the droplets were successfully amplified by PCR. In addition, the droplet digital PCR platform allowed absolute quantification of low copy numbers of target DNA, and was robust against instrumental variance. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Microfluidic valve array control system integrating a fluid demultiplexer circuit

NASA Astrophysics Data System (ADS)

Kawai, Kentaro; Arima, Kenta; Morita, Mizuho; Shoji, Shuichi

2015-06-01

This paper proposes an efficient control method for the large-scale integration of microvalves in microfluidic systems. The proposed method can control 2n individual microvalves with 2n + 2 control lines (where n is an integer). The on-chip valves are closed by applying pressure to a control line, similar to conventional pneumatic microvalves. Another control line closes gate valves between the control line to the on-chip valves and the on-chip valves themselves, to preserve the state of the on-chip valves. The remaining control lines select an activated gate valve. While the addressed gate valve is selected by the other control lines, the corresponding on-chip valve is actuated by applying input pressure to the control line to the on-chip valves. Using this method would substantially reduce the number of world-to-chip connectors and off-chip valve controllers. Experiments conducted using a fabricated 28 microvalve array device, comprising 256 individual on-chip valves controlled with 18 (2   ×   8 + 2) control lines, yielded switching speeds for the selected on-chip valve under 90 ms.

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid-wave IR (MWIR) and long-wave IR (LWIR) spectral bands.

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Advances in Testing Techniques for Digital Microfluidic Biochips

PubMed Central

Shukla, Vineeta; Hussin, Fawnizu Azmadi; Hamid, Nor Hisham; Zain Ali, Noohul Basheer

2017-01-01

With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips. PMID:28749411

Advances in Testing Techniques for Digital Microfluidic Biochips.

PubMed

Shukla, Vineeta; Hussin, Fawnizu Azmadi; Hamid, Nor Hisham; Zain Ali, Noohul Basheer

2017-07-27

With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips.

A high sensitive 66 dB linear dynamic range receiver for 3-D laser radar

NASA Astrophysics Data System (ADS)

Ma, Rui; Zheng, Hao; Zhu, Zhangming

2017-08-01

This study presents a CMOS receiver chip realized in 0.18 μm standard CMOS technology and intended for high precision 3-D laser radar. The chip includes an adjustable gain transimpedance pre-amplifier, a post-amplifier and two timing comparators. An additional feedback is employed in the regulated cascode transimpedance amplifier to decrease the input impedance, and a variable gain transimpedance amplifier controlled by digital switches and analog multiplexer is utilized to realize four gain modes, extending the input dynamic range. The measurement shows that the highest transimpedance of the channel is 50 k {{Ω }}, the uncompensated walk error is 1.44 ns in a wide linear dynamic range of 66 dB (1:2000), and the input referred noise current is 2.3 pA/\\sqrt{{Hz}} (rms), resulting in a very low detectable input current of 1 μA with SNR = 5.

DFB laser array driver circuit controlled by adjustable signal

NASA Astrophysics Data System (ADS)

Du, Weikang; Du, Yinchao; Guo, Yu; Li, Wei; Wang, Hao

2018-01-01

In order to achieve the intelligent controlling of DFB laser array, this paper presents the design of an intelligence and high precision numerical controlling electric circuit. The system takes MCU and FPGA as the main control chip, with compact, high-efficiency, no impact, switching protection characteristics. The output of the DFB laser array can be determined by an external adjustable signal. The system transforms the analog control model into a digital control model, which improves the performance of the driver. The system can monitor the temperature and current of DFB laser array in real time. The output precision of the current can reach ± 0.1mA, which ensures the stable and reliable operation of the DFB laser array. Such a driver can benefit the flexible usage of the DFB laser array.

High flux heat exchanger

NASA Astrophysics Data System (ADS)

Flynn, Edward M.; Mackowski, Michael J.

1993-01-01

This interim report documents the results of the first two phases of a four-phase program to develop a high flux heat exchanger for cooling future high performance aircraft electronics. Phase 1 defines future needs for high flux heat removal in advanced military electronics systems. The results are sorted by broad application categories: (1) commercial digital systems, (2) military data processors, (3) power processors, and (4) radar and optical systems. For applications expected to be fielded in five to ten years, the outlook is for steady state flux levels of 30-50 W/sq cm for digital processors and several hundred W/sq cm for power control applications. In Phase 1, a trade study was conducted on emerging cooling technologies which could remove a steady state chip heat flux of 100 W/sq cm while holding chip junction temperature to 90 C. Constraints imposed on heat exchanger design, in order to reflect operation in a fighter aircraft environment, included a practical lower limit on coolant supply temperature, the preference for a nontoxic, nonflammable, and nonfreezing coolant, the need to minimize weight and volume, and operation in an accelerating environment. The trade study recommended the Compact High Intensity Cooler (CHIC) for design, fabrication, and test in the final two phases of this program.

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

NASA Astrophysics Data System (ADS)

Manghisoni, M.; Fabris, L.; Re, V.; Traversi, G.; Ratti, L.; Grassi, M.; Lodola, L.; Malcovati, P.; Vacchi, C.; Pancheri, L.; Benkechcache, M. E. A.; Dalla Betta, G.-F.; Xu, H.; Verzellesi, G.; Ronchin, S.; Boscardin, M.; Batignani, G.; Bettarini, S.; Casarosa, G.; Forti, F.; Giorgi, M.; Paladino, A.; Paoloni, E.; Rizzo, G.; Morsani, F.

2016-11-01

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Camera-on-a-Chip

NASA Technical Reports Server (NTRS)

1999-01-01

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Insertion of GaAs MMICs into EW systems

NASA Astrophysics Data System (ADS)

Schineller, E. R.; Pospishil, A.; Grzyb, J.

1989-09-01

Development activities on a microwave/mm-wave monolithic IC (MIMIC) program are described, as well as the methodology for inserting these GaAs IC chips into several EW systems. The generic EW chip set developed on the MIMIC program consists of 23 broadband chip types, including amplifiers, oscillators, mixers, switches, variable attenuators, power dividers, and power combiners. These chips are being designed for fabrication using the multifunction self-aligned gate process. The benefits from GaAs IC insertion are quantified by a comparison of hardware units fabricated with existing MIC and digital ECL technology and the same units manufactured with monolithic technology. It is found that major improvements in cost, reliability, size, weight, and performance can be realized. Examples illustrating the methodology for technology insertion are presented.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

Active-Pixel Image Sensor With Analog-To-Digital Converters

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

1995-01-01

Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

Single chip lidar with discrete beam steering by digital micromirror device.

PubMed

Smith, Braden; Hellman, Brandon; Gin, Adley; Espinoza, Alonzo; Takashima, Yuzuru

2017-06-26

A novel method of beam steering enables a large field of view and reliable single chip light detection and ranging (lidar) by utilizing a mass-produced digital micromirror device (DMD). Using a short pulsed laser, the micromirrors' rotation is frozen in mid-transition, which forms a programmable blazed grating. The blazed grating efficiently redistributes the light to a single diffraction order, among several. We demonstrated time of flight measurements for five discrete angles using this beam steering method with a nano second 905nm laser and Si avalanche diode. A distance accuracy of < 1 cm over a 1 m distance range, a 48° full field of view, and a measurement rate of 3.34k points/s is demonstrated.

Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

PubMed

He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

2013-09-18

The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

NASA Astrophysics Data System (ADS)

Takashima, Ichiro; Kajiwara, Riichi; Murano, Kiyo; Iijima, Toshio; Morinaka, Yasuhiro; Komobuchi, Hiroyoshi

2001-04-01

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Electronic readout system for the Belle II imaging Time-Of-Propagation detector

NASA Astrophysics Data System (ADS)

Kotchetkov, Dmitri

2017-07-01

The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

Temperature Tolerant Evolvable Systems Utilizing FPGA Boards and Bias-Controlled Amplifiers

NASA Technical Reports Server (NTRS)

Kumar, Nikhil R.

2005-01-01

Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond Earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfigurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfigure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-l990s, but one problem remains-the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180 to 120 C) has been done on devices found on FPGA boards (taking the role of the EP), such as the Analog to Digital and the Digital to Analog Converter. The EP is used in conjunction with a bias-controlled amplifier and a new prototype relay board, which is interconnected with 6 G4-FETs, a tri-input transistor-like element developed at JPL. The greatest improvements to be made lie in the reconfigurable device, so future design and testing of the G4-FET chip is required.

A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

NASA Astrophysics Data System (ADS)

Nasir, Z.; Ruslan, S. H.

2017-08-01

A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

Research and development of biochip technologies in Taiwan

NASA Astrophysics Data System (ADS)

Ting, Solomon J.; Chiou, Arthur E. T.

2000-07-01

Recent advancements in several genome-sequencing projects have stimulated an enormous interest in microarray DNA chip technology, especially in the biomedical sciences and pharmaceutical industries. The DNA chips facilitated the miniaturization of conventional nucleic acid hybridizations, by either robotically spotting thousands of library cDNAs or in situ synthesis of high-density oligonucleotides onto solid supports. These innovations have found a wide range of applications in molecular biology, especially in studying gene expression and discovering new genes from the global view of genomic analysis. The research and development of this powerful tool has also received great attentions in Taiwan. In this paper, we report the current progresses of our DNA chip project, along with the current status of other biochip projects in Taiwan, such as protein chip, PCR chip, electrophoresis chip, olfactory chip, etc. The new development of biochip technologies integrates the biotechnology with the semiconductor processing, the micro- electro-mechanical, optoelectronic, and digital signal processing technologies. Most of these biochip technologies utilitze optical detection methods for data acquisition and analysis. The strengths and advantages of different approaches are compared and discussed in this report.

A single chip 2 Gbit/s clock recovery subsystem for digital communications

NASA Astrophysics Data System (ADS)

Hickling, Ronald M.

A self-contained clock recovery/data resynchronizer phase locked loop (PLL) for use in microwave and fiber optic digital communications has been fabricated using GaAs integrated circuit technology. The IC contains the analog and digital components for the PLL: an edge-triggered phase detector based on a 1.2 GHz phase/frequency comparator, an op amp for creating the loop filter, and a VCO based on a differential source-coupled pair amplifier.

(M-CAT) Minor Caliber Weapons Trainer MK-19, 40mm Machine Gun

DTIC Science & Technology

1989-07-24

microprocessor chip with an Intel 387 math coprocessor. The Nova 620 is a digital time base corrector. It is used to time base correct the video data...the circuit. After filtering, the horizontal and vertical position signals are converted to digital values by the Data Translation (DTX-311) analog...from the computer. Each frame of the video disk is individually digitized as to target size, location, and range. The guns azimuth and elevation are

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

NASA Astrophysics Data System (ADS)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

MICROROC: MICRO-mesh gaseous structure Read-Out Chip

NASA Astrophysics Data System (ADS)

Adloff, C.; Blaha, J.; Chefdeville, M.; Dalmaz, A.; Drancourt, C.; Dulucq, F.; Espargilière, A.; Gaglione, R.; Geffroy, N.; Jacquemier, J.; Karyotakis, Y.; Martin-Chassard, G.; Prast, J.; Seguin-Moreau, N.; de La Taille, Ch; Vouters, G.

2012-01-01

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active medium of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at a future linear collider (ILC/CLIC). Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital readout calorimeter). To validate the concept of digital hadronic calorimetry with such small cell size, the construction and test of a cubic meter technological prototype, made of 40 planes of one square meter each, is necessary. This technological prototype would contain about 400 000 electronic channels, thus requiring the development of front-end ASIC. Based on the experience gained with previous ASIC that were mounted on detectors and tested in particle beams, a new ASIC called MICROROC has been developped. This paper summarizes the caracterisation campaign that was conducted on this new chip as well as its integration into a large area Micromegas chamber of one square meter.

MEDUSA-32: A low noise, low power silicon strip detector front-end electronics, for space applications

NASA Astrophysics Data System (ADS)

Cicuttin, Andres; Colavita, Alberto; Cerdeira, Alberto; Fratnik, Fabio; Vacchi, Andrea

1997-02-01

In this report we describe a mixed analog-digital integrated circuit (IC) designed as the front-end electronics for silicon strip-detectors for space applications. In space power consumption, compactness and robustness become critical constraints for a pre-amplifier design. The IC is a prototype with 32 complete channels, and it is intended for a large area particle tracker of a new generation of gamma ray telescopes. Each channel contains a charge sensitive amplifier, a pulse shaper, a discriminator and two digital buffers. The reference trip point of the discriminator is adjustable. This chip also has a custom PMOSFET transistor per channel, included in order to provide the high dynamic resistance needed to reverse-bias the strip diode. The digital part of the chip is used to store and serially shift out the state of the channels. There is also a storage buffer that allows the disabling of non-functioning channels if it is required by the data acquisition system. An input capacitance of 30 pF introduced at the input of the front-end produces less than 1000 electrons of RMS equivalent noise charge (ENC), for a total power dissipation of only 60 μW per channel. The chip was made using Orbit's 1.2 μm double poly, double metal n-well low noise CMOS process. The dimensions of the IC are 2400 μm × 8840 μm.

Design and construction of a prototype ACTS propagation terminal

NASA Technical Reports Server (NTRS)

Stutzman, Warren; Pratt, Tim; Nunnally, Charles; Nealy, Randall; Remaklus, Will; Sylvester, Bill; Predoehl, Andrew; Gaff, Doug

1993-01-01

The launch schedule for the Advanced Communication Technology Satellite (ACTS) spacecraft did not leave sufficient time for completion of the prototype ACTS Propagation Terminals (APT) prior to initiation of the APT production phase. In fact, the approach used was to construct and test all subassemblies of the terminal with special emphasis on the technically challenging portions. These include the RF front end that uses a state-of-the-art down converter which integrates a low noise amplifier, mixer, post amplifier, filter, and local oscillator port frequency doubler into a single small package. In addition, a new digital receiver that uses the latest DSP technology was developed. Both of these subassemblies were thoroughly tested. The highest risk technology in the APT program was the digital receiver. Several candidate algorithms and DSP chips were investigated early on, primarily under JPL sponsorship. A receiver was constructed based on Texas Instruments chip. The final prototype digital receiver was one based on an Analog Devices chip. The design and test results are documented in a report prepared for this grant. A Primary Design Review (PDR) was conducted 30 May 1991, and a Critical Design Review was held 7 Jul. 1992. Final complete documentation of the APT's will appear in the form of three reports: a hardware description report, a report on the data collection code (ACTS VIEW), and a report on the preprocessing code.

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

NASA Technical Reports Server (NTRS)

Schuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li; Madala, Shridhar

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Easy detection of multiple Alexandrium species using DNA chromatography chip.

PubMed

Nagai, Satoshi; Miyamoto, Shigehiko; Ino, Keita; Tajimi, Seisuke; Nishi, Hiromi; Tomono, Jun

2016-01-01

In this study, the Kaneka DNA chromatography chip (KDCC) for the Alexandrium species was successfully developed for simultaneous detection of five Alexandrium species. This method utilizes a DNA-DNA hybridization technology. In the PCR process, specifically designed tagged-primers are used, i.e. a forward primer consisting of a tag domain, which can conjugate with gold nanocolloids on the chip, and a primer domain, which can anneal/amplify the target sequence. However, the reverse primer consists of a tag domain, which can hybridize to the solid-phased capture probe on the chip, and a primer domain, which can anneal/amplify the target sequence. As a result, a red line that originates from gold nanocolloids appears as a positive signal on the chip, and the amplicon is detected visually by the naked eye. This technique is simple, because it is possible to visually detect the target species soon after (<5min) the application of 2μL of PCR amplicon and 65μL of development buffer to the sample pad of the chip. Further, this technique is relatively inexpensive and does not require expensive laboratory equipment, such as real-time Q-PCR machines or DNA microarray detectors, but a thermal cycler. Regarding the detection limit of KDCC for the five Alexandrium species, it varied among species and it was <0.1-10pg and equivalent to 5-500 copies of rRNA genes, indicating that the technique is sensitive enough for practical use to detect several cells of the target species from 1L of seawater. The detection sensitivity of KDCC was also evaluated with two different techniques, i.e. a multiplex-PCR and a digital DNA hybridization by digital DNA chip analyzer (DDCA), using natural plankton assemblages. There was no significant difference in the detection sensitivity among the three techniques, suggesting KDCC can be readily used to monitor the HAB species. Copyright © 2015 Elsevier B.V. All rights reserved.

Wireless neural recording with single low-power integrated circuit.

PubMed

Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

2009-08-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

Microcircuit Device Reliability Digital Detailed Data

DTIC Science & Technology

1976-01-01

TYPE s No. FUNCTION A LASS PINS TEMP. TYPE CLASS LEVEL I eFAILED 8 NO. CHIP TEST APPL. TEST PAR1 t T AGATES PROTECT. DATE E:V. D TYPE HOURST :708 FLIP...LEVEL # EFAILED s a NO. t CHIP i TEST 3 APPL. a TEST I PAR! 3 a GATES s PROTECT. a DATE 3 ENV. t TYPE I 3 -OUHb s 354H0( 3 GATE C-I CDIP 14 150C :11.A

EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

NASA Astrophysics Data System (ADS)

Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

2003-10-01

We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Clock jitter generator with picoseconds resolution

NASA Astrophysics Data System (ADS)

Jovanović, Goran; Stojčev, Mile; Nikolić, Tatjana

2013-06-01

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

Implementation and Performance of GaAs Digital Signal Processing ASICs

NASA Technical Reports Server (NTRS)

Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

1993-01-01

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

NASA Astrophysics Data System (ADS)

Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

2015-10-01

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

Product assurance technology for custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

The digital compensation technology system for automotive pressure sensor

NASA Astrophysics Data System (ADS)

Guo, Bin; Li, Quanling; Lu, Yi; Luo, Zai

2011-05-01

Piezoresistive pressure sensor be made of semiconductor silicon based on Piezoresistive phenomenon, has many characteristics. But since the temperature effect of semiconductor, the performance of silicon sensor is also changed by temperature, and the pressure sensor without temperature drift can not be produced at present. This paper briefly describe the principles of sensors, the function of pressure sensor and the various types of compensation method, design the detailed digital compensation program for automotive pressure sensor. Simulation-Digital mixed signal conditioning is used in this dissertation, adopt signal conditioning chip MAX1452. AVR singlechip ATMEGA128 and other apparatus; fulfill the design of digital pressure sensor hardware circuit and singlechip hardware circuit; simultaneously design the singlechip software; Digital pressure sensor hardware circuit is used to implementing the correction and compensation of sensor; singlechip hardware circuit is used to implementing to controll the correction and compensation of pressure sensor; singlechip software is used to implementing to fulfill compensation arithmetic. In the end, it implement to measure the output of sensor, and contrast to the data of non-compensation, the outcome indicates that the compensation precision of compensated sensor output is obviously better than non-compensation sensor, not only improving the compensation precision but also increasing the stabilization of pressure sensor.

Silicon photonics devices for metro applications

NASA Astrophysics Data System (ADS)

Fukuda, H.; Kikuchi, K.; Jizodo, M.; Kawamura, Y.; Takeda, K.; Honda, K.

2017-01-01

Digital coherent technology is considered an attractive way of realizing both high-speed metro links and long distance transmissions. In metro areas, there is a strong demand for a smaller, faster transceiver module. This demand is mainly driven by the rapidly increasing data center interconnection traffic, where transmission capacity per faceplane is a key feature. Therefore, optical integration technology is desired. Since compensation in digital coherent technology is performed in the electrical or digital domain, users can deal with those optics performances that are not compensated for digitally. This means using a new material that cannot provide perfect characteristics but that is suitable for miniaturization and integration is possible. Silicon photonics (SiPh) is considered an attractive technology that would enable the significant miniaturization of optical circuits and be capable of optical integration with high manufacturability. While SiPh-based devices have begun to be deployed for very short or short reach links on the basis of direct detection technology, their digital coherent applications have recently been investigated in view of their integration capability. This paper describes recent progress on SiPh-based integrated optical devices for high-speed digital coherent transceivers targeting metro links. An optical modulator and receiver with related circuits have been integrated into a single SiPh chip. TEC-free operation under non-hermetic conditions and the direct attachment of optical fibers have both been realized. Very thin and small packaging with sufficient performance has been demonstrated by using the SiPh chip co-packaged with high-speed ICs.

Wireless Neural Recording With Single Low-Power Integrated Circuit

PubMed Central

Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

2010-01-01

We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

Computation and brain processes, with special reference to neuroendocrine systems.

PubMed

Toni, Roberto; Spaletta, Giulia; Casa, Claudia Della; Ravera, Simone; Sandri, Giorgio

2007-01-01

The development of neural networks and brain automata has made neuroscientists aware that the performance limits of these brain-like devices lies, at least in part, in their computational power. The computational basis of a. standard cybernetic design, in fact, refers to that of a discrete and finite state machine or Turing Machine (TM). In contrast, it has been suggested that a number of human cerebral activites, from feedback controls up to mental processes, rely on a mixing of both finitary, digital-like and infinitary, continuous-like procedures. Therefore, the central nervous system (CNS) of man would exploit a form of computation going beyond that of a TM. This "non conventional" computation has been called hybrid computation. Some basic structures for hybrid brain computation are believed to be the brain computational maps, in which both Turing-like (digital) computation and continuous (analog) forms of calculus might occur. The cerebral cortex and brain stem appears primary candidate for this processing. However, also neuroendocrine structures like the hypothalamus are believed to exhibit hybrid computional processes, and might give rise to computational maps. Current theories on neural activity, including wiring and volume transmission, neuronal group selection and dynamic evolving models of brain automata, bring fuel to the existence of natural hybrid computation, stressing a cooperation between discrete and continuous forms of communication in the CNS. In addition, the recent advent of neuromorphic chips, like those to restore activity in damaged retina and visual cortex, suggests that assumption of a discrete-continuum polarity in designing biocompatible neural circuitries is crucial for their ensuing performance. In these bionic structures, in fact, a correspondence exists between the original anatomical architecture and synthetic wiring of the chip, resulting in a correspondence between natural and cybernetic neural activity. Thus, chip "form" provides a continuum essential to chip "function". We conclude that it is reasonable to predict the existence of hybrid computational processes in the course of many human, brain integrating activities, urging development of cybernetic approaches based on this modelling for adequate reproduction of a variety of cerebral performances.

Applied digital signal processing systems for vortex flowmeter with digital signal processing.

PubMed

Xu, Ke-Jun; Zhu, Zhi-Hai; Zhou, Yang; Wang, Xiao-Fen; Liu, San-Shan; Huang, Yun-Zhi; Chen, Zhi-Yuan

2009-02-01

The spectral analysis is combined with digital filter to process the vortex sensor signal for reducing the effect of disturbance at low frequency from pipe vibrations and increasing the turndown ratio. Using digital signal processing chip, two kinds of digital signal processing systems are developed to implement these algorithms. One is an integrative system, and the other is a separated system. A limiting amplifier is designed in the input analog condition circuit to adapt large amplitude variation of sensor signal. Some technique measures are taken to improve the accuracy of the output pulse, speed up the response time of the meter, and reduce the fluctuation of the output signal. The experimental results demonstrate the validity of the digital signal processing systems.

VASP-4096: a very high performance programmable device for digital media processing applications

NASA Astrophysics Data System (ADS)

Krikelis, Argy

2001-03-01

Over the past few years, technology drivers for microprocessors have changed significantly. Media data delivery and processing--such as telecommunications, networking, video processing, speech recognition and 3D graphics--is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper presents the architecture of the VASP-4096 processor. VASP-4096 provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the VASP-4096 is the integration of thousands of processing units in a single chip that are capable of support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, VASP-4096 integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 Kbytes of Data Memory, and I/O interfaces. The SIMD processing in VASP-4096 implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate), and a 64- bit 66 MHz PCI interface. VASP-4096, compared with other processors architectures that support media processing, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re- used in future chip generations.

FPGA-based digital signal processing for the next generation radio astronomy instruments: ultra-pure sideband separation and polarization detection

NASA Astrophysics Data System (ADS)

Alvear, Andrés.; Finger, Ricardo; Fuentes, Roberto; Sapunar, Raúl; Geelen, Tom; Curotto, Franco; Rodríguez, Rafael; Monasterio, David; Reyes, Nicolás.; Mena, Patricio; Bronfman, Leonardo

2016-07-01

Field Programmable Gate Arrays (FPGAs) capacity and Analog to Digital Converters (ADCs) speed have largely increased in the last decade. Nowadays we can find one million or more logic blocks (slices) as well as several thousand arithmetic units (ALUs/DSP) available on a single FPGA chip. We can also commercially procure ADC chips reaching 10 GSPS, with 8 bits resolution or more. This unprecedented power of computing hardware has allowed the digitalization of signal processes traditionally performed by analog components. In radio astronomy, the clearest example has been the development of digital sideband separating receivers which, by replacing the IF hybrid and calibrating the system imbalances, have exhibited a sideband rejection above 40dB; this is 20 to 30dB higher than traditional analog sideband separating (2SB) receivers. In Rodriguez et al.,1 and Finger et al.,2 we have demonstrated very high digital sideband separation at 3mm and 1mm wavelengths, using laboratory setups. We here show the first implementation of such technique with a 3mm receiver integrated into a telescope, where the calibration was performed by quasi-optical injection of the test tone in front of the Cassegrain antenna. We also reported progress in digital polarization synthesis, particularly in the implementation of a calibrated Digital Ortho-Mode Transducer (DOMT) based on the Morgan et al. proof of concept.3 They showed off- line synthesis of polarization with isolation higher than 40dB. We plan to implement a digital polarimeter in a real-time FPGA-based (ROACH-2) platform, to show ultra-pure polarization isolation in a non-stop integrating spectrometer.

A microprocessor based anti-aliasing filter for a PCM system

NASA Technical Reports Server (NTRS)

Morrow, D. C.; Sandlin, D. R.

1984-01-01

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

GridPix detectors: Production and beam test results

NASA Astrophysics Data System (ADS)

Koppert, W. J. C.; van Bakel, N.; Bilevych, Y.; Colas, P.; Desch, K.; Fransen, M.; van der Graaf, H.; Hartjes, F.; Hessey, N. P.; Kaminski, J.; Schmitz, J.; Schön, R.; Zappon, F.

2013-12-01

The innovative GridPix detector is a Time Projection Chamber (TPC) that is read out with a Timepix-1 pixel chip. By using wafer post-processing techniques an aluminium grid is placed on top of the chip. When operated, the electric field between the grid and the chip is sufficient to create electron induced avalanches which are detected by the pixels. The time-to-digital converter (TDC) records the drift time enabling the reconstruction of high precision 3D track segments. Recently GridPixes were produced on full wafer scale, to meet the demand for more reliable and cheaper devices in large quantities. In a recent beam test the contribution of both diffusion and time walk to the spatial and angular resolutions of a GridPix detector with a 1.2 mm drift gap are studied in detail. In addition long term tests show that in a significant fraction of the chips the protection layer successfully quenches discharges, preventing harm to the chip.

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Performance of generation III 640 X 480 PtSi MOS array

NASA Astrophysics Data System (ADS)

Villani, Thomas S.; Esposito, Benjamin J.; Pletcher, T. J.; Sauer, Donald J.; Levine, Peter A.; Shallcross, Frank V.; Meray, Grazyna M.; Tower, John R.

1994-07-01

The design and performance of a third generation 640(H) X 480(V) PtSi focal plane array is presented. The 3 to 5 micron MWIR focal plane array supports interlaced, progressive scan, and subframe readout under control of on-chip digital decoders. The new design utilizes 1.25 micrometers design rules to achieve a 50% fill-factor, a noise equivalent delta temperature of <0.07 C (f/1.5, 30 Hz, 300 K), and a saturation level >1.5 X 10(superscript 6)e. The power dissipation is less than 110 mW.

Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

NASA Technical Reports Server (NTRS)

Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Staller, C.; Zhou, Z;

A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response

NASA Technical Reports Server (NTRS)

Ferguson, Michael I.; MacDonald, Eric; Foor, David

2005-01-01

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

NASA Technical Reports Server (NTRS)

Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

1993-01-01

The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

Effects of channel tap spacing on delay-lock tracking

NASA Astrophysics Data System (ADS)

Dana, Roger A.; Milner, Brian R.; Bogusch, Robert L.

1995-12-01

High fidelity simulations of communication links operating through frequency selective fading channels require both accurate channel models and faithful reproduction of the received signal. In modern radio receivers, processing beyond the analog-to-digital converter (A/D) is done digitally, so a high fidelity simulation is actually an emulation of this digital signal processing. The 'simulation' occurs in constructing the output of the A/D. One approach to constructing the A/D output is to convolve the channel impulse response function with the combined impulse response of the transmitted modulation and the A/D. For both link simulations and hardware channel simulators, the channel impulse response function is then generated with a finite number of samples per chip, and the convolution is implemented in a tapped delay line. In this paper we discuss the effects of the channel model tap spacing on the performance of delay locked loops (DLLs) in both direct sequence and frequency hopped spread spectrum systems. A frequency selective fading channel is considered, and the channel impulse response function is constructed with an integer number of taps per modulation symbol or chip. The tracking loop time delay is computed theoretically for this tapped delay line channel model and is compared to the results of high fidelity simulations of actual DLLs. A surprising result is obtained. The performance of the DLL depends strongly on the number of taps per chip. As this number increases the DLL delay approaches the theoretical limit.

IF digitization receiver of wideband digital array radar test-bed

NASA Astrophysics Data System (ADS)

Li, Weixing; Zhang, Yue; Lin, Jianzhi; Chen, Zengping

2014-10-01

In this paper, an X-band, 8-element wideband digital array radar (DAR) test-bed is presented, which makes use of a novel digital backend coupled with highly-integrated, multi-channel intermediate frequency (IF) digital receiver. Radar returns are received by the broadband antenna and then down-converted to the IF of 0.6GHz-3.0GHz. Four band-pass filters are applied in the front-end to divide the IF returns into four frequency bands with the instantaneous bandwidth of 500MHz. Every four array elements utilize a digital receiver, which is focused in this paper. The digital receivers are designed in a compact and flexible manner to meet the demands of DAR system. Each receiver consists of a fourchannel ADC, a high-performance FPGA, four DDR3 chips and two optical transceivers. With the sampling rate of up to 1.2GHz each channel, the ADC is capable of directly sampling the IF returns of four array elements at 10bits. In addition to serving as FIFO and controller, the onboard FPGA is also utilized for the implementation of various real-time algorithms such as DDC and channel calibration. Data is converted to bit stream and transferred through two low overhead, high data rate and multi-channel optical transceivers. Key technologies such as channel calibration and wideband DOA are studied with the measured data which is obtained in the experiments to illustrate the functionality of the system.

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P. K. A.

2014-01-01

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W−1/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems. PMID:25417847

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide.

PubMed

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P K A

2014-11-24

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W(-1)/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

Demonstration of multi-wavelength tunable fiber lasers based on a digital micromirror device processor.

PubMed

Ai, Qi; Chen, Xiao; Tian, Miao; Yan, Bin-bin; Zhang, Ying; Song, Fei-jun; Chen, Gen-xiang; Sang, Xin-zhu; Wang, Yi-quan; Xiao, Feng; Alameh, Kamal

2015-02-01

Based on a digital micromirror device (DMD) processor as the multi-wavelength narrow-band tunable filter, we demonstrate a multi-port tunable fiber laser through experiments. The key property of this laser is that any lasing wavelength channel from any arbitrary output port can be switched independently over the whole C-band, which is only driven by single DMD chip flexibly. All outputs display an excellent tuning capacity and high consistency in the whole C-band with a 0.02 nm linewidth, 0.055 nm wavelength tuning step, and side-mode suppression ratio greater than 60 dB. Due to the automatic power control and polarization design, the power uniformity of output lasers is less than 0.008 dB and the wavelength fluctuation is below 0.02 nm within 2 h at room temperature.

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Song, Z.; Wang, Y.; Kuang, J.

2018-05-01

Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0–10 ns), and their measurement throughput reaches 277 M measures per second.

Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

PubMed Central

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

2014-01-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

PubMed

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

New technologies for radiation-hardening analog to digital converters

NASA Technical Reports Server (NTRS)

Gauthier, M. K.

1982-01-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

Compact wavelength-selective optical switch based on digital optical phase conjugation.

PubMed

Li, Zhiyang; Claver, Havyarimana

2013-11-15

In this Letter, we show that digital optical phase conjugation might be utilized to construct a new kind of wavelength-selective switches. When incorporated with a multimode interferometer, these switches have wide bandwidth, high tolerance for fabrication error, and low polarization dependency. They might help to build large-scale multiwavelength nonblocking switching systems, or even to fabricate an optical cross-connecting or routing system on a chip.

Low-power wireless ECG acquisition and classification system for body sensor networks.

PubMed

Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

2015-01-01

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder.

PubMed

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder

PubMed Central

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive. PMID:28018162

Photo-actuation of liquids for light-driven microfluidics: state of the art and perspectives.

PubMed

Baigl, Damien

2012-10-07

Using light to control liquid motion is a new paradigm for the actuation of microfluidic systems. We review here the different principles and strategies to induce or control liquid motion using light, which includes the use of radiation pressure, optical tweezers, light-induced wettability gradients, the thermocapillary effect, photosensitive surfactants, the chromocapillary effect, optoelectrowetting, photocontrolled electroosmotic flows and optical dielectrophoresis. We analyze the performance of these approaches to control using light many kinds of microfluidic operations involving discrete pL- to μL-sized droplets (generation, driving, mixing, reaction, sorting) or fluid flows in microchannels (valve operation, injection, pumping, flow rate control). We show that a complete toolbox is now available to control microfluidic systems by light. We finally discuss the perspectives of digital optofluidics as well as microfluidics based on all optical fluidic chips and optically reconfigurable devices.

SCOC3: A Brand New Heart for Space Mission

NASA Astrophysics Data System (ADS)

Poupat, Jean-Luc; Lefevre, Aurelien

2012-08-01

Satellites are controlled via a platform On Board Computer (OBC) that manages different parameters (attitude, orbit, modes, temperatures ...) with respect to its payload mission (telecommunication, earth observation, scientific mission). The platform OBC is connected to the satellite and the ground control via digital links, and executes on board software.The main functions of a platform OBC are to provide the satellite flight segment with the following features: o Processing resources for the flight mission softwareo TM/TC services and interfaces with the RF communication chaino General communication services with the Avionics and payload equipments through on- board communication buso Time synchronization and distributiono Failure tolerant architecture based on the use of redounded reconfiguration units and redundancy implementationIn order to reach an ultimate level of integration, Astrium has designed an ASIC gathering on a single chip all these required digital functions: the SCOC3 ASIC.This paper presents in a first part the major innovations introduced by Astrium for SCOC3, in a second part the development tools associated to SCOC3, and in a third part the status concerning its commercialization.

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

Burst Mode ASIC-Based Modem

NASA Technical Reports Server (NTRS)

1997-01-01

The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

CMOS serial link for fully duplexed data communication

NASA Astrophysics Data System (ADS)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems.

PubMed

Sheng, Duo; Lai, Hsiu-Fan; Chan, Sheng-Min; Hong, Min-Rong

2015-02-13

An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascade-stage delay measurement circuit can enhance immunity to supply-voltage variations of the delay measurement resolution without extra self-biasing or calibration circuits. Simulation results show that the delay measurement resolution can be improved to 1.2 ps; the average delay resolution variation is 0.55% with supply-voltage variations of ±10%. Moreover, the proposed delay sensor can be implemented in an all-digital manner, making it very suitable for high-performance electronic system applications as well as system-level integration.

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

NASA Astrophysics Data System (ADS)

Si, Chen; Zengwang, Yang; Mingliang, Gu

2011-04-01

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

Controlling the type and the form of chip when machining steel

NASA Astrophysics Data System (ADS)

Gruby, S. V.; Lasukov, A. A.; Nekrasov, R. Yu; Politsinsky, E. V.; Arkhipova, D. A.

2016-08-01

The type of the chip produced in the process of machining influences many factors of production process. Controlling the type of chip when cutting metals is important for producing swarf chips and for easing its utilization as well as for protecting the machined surface, cutting tool and the worker. In the given work we provide the experimental data on machining structural steel with implanted tool. The authors show that it is possible to control the chip formation process to produce the required type of chip by selecting the material for machining the tool surface.

Optimal Data Transmission on MIMO OFDM Channels

DTIC Science & Technology

2008-12-01

Channel State Information dB decibel DFT Discrete Fourier Transform DWTS Digital Wideband Transmission System ETSI European Telecommunications...me facultaram durante a minha infância e juventude , que em conjunto com seu permanente apoio e amor me permitiram sonhar e voar tão alto. Agradeço...transmitter, it is far simpler to build such a system using an IDFT chip, generate the overall OFDM signal in baseband and digital format, and finally

Teaching Quality Control with Chocolate Chip Cookies

ERIC Educational Resources Information Center

Baker, Ardith

2014-01-01

Chocolate chip cookies are used to illustrate the importance and effectiveness of control charts in Statistical Process Control. By counting the number of chocolate chips, creating the spreadsheet, calculating the control limits and graphing the control charts, the student becomes actively engaged in the learning process. In addition, examining…

Backside illuminated CMOS-TDI line scan sensor for space applications

NASA Astrophysics Data System (ADS)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Programmable bio-nano-chip system: a flexible point-of-care platform for bioscience and clinical measurements

PubMed Central

McRae, Michael. P.; Simmons, Glennon. W.; Wong, Jorge; Shadfan, Basil; Gopalkrishnan, Sanjiv; Christodoulides, Nicolaos

2015-01-01

The development of integrated instrumentation for universal bioassay systems serves as a key goal for the lab-on-a-chip community. The programmable bio-nano-chip (p-BNC) system is a versatile multiplexed and multiclass chemical- and bio-sensing system for bioscience and clinical measurements. The system is comprised of two main components, a disposable cartridge and a portable analyzer. The customizable single-use plastic cartridges, which now can be manufactured in high volumes using injection molding, are designed for analytical performance, ease of use, reproducibility, and low cost. These labcard devices implement high surface area nano-structured biomarker capture elements that enable high performance signaling and are index matched to real-world biological specimens. This detection modality, along with the convenience of on-chip fluid storage in blisters and self-contained waste, represents a standard process to digitize biological signatures at the point-of-care. A companion portable analyzer prototype has been developed to integrate fluid motivation, optical detection, and automated data analysis, and it serves as the human interface for complete assay automation. In this report, we provide a systems-level perspective of the p-BNC universal biosensing platform with an emphasis on flow control, device integration, and automation. To demonstrate the flexibility of the p-BNC, we distinguish diseased and non-case patients across three significant disease applications: prostate cancer, ovarian cancer, and acute myocardial infarction. Progress towards developing a rapid 7 minute myoglobin assay is presented using the fully automated p-BNC system. PMID:26308851

Microfluidic Devices for Forensic DNA Analysis: A Review.

PubMed

Bruijns, Brigitte; van Asten, Arian; Tiggelaar, Roald; Gardeniers, Han

2016-08-05

Microfluidic devices may offer various advantages for forensic DNA analysis, such as reduced risk of contamination, shorter analysis time and direct application at the crime scene. Microfluidic chip technology has already proven to be functional and effective within medical applications, such as for point-of-care use. In the forensic field, one may expect microfluidic technology to become particularly relevant for the analysis of biological traces containing human DNA. This would require a number of consecutive steps, including sample work up, DNA amplification and detection, as well as secure storage of the sample. This article provides an extensive overview of microfluidic devices for cell lysis, DNA extraction and purification, DNA amplification and detection and analysis techniques for DNA. Topics to be discussed are polymerase chain reaction (PCR) on-chip, digital PCR (dPCR), isothermal amplification on-chip, chip materials, integrated devices and commercially available techniques. A critical overview of the opportunities and challenges of the use of chips is discussed, and developments made in forensic DNA analysis over the past 10-20 years with microfluidic systems are described. Areas in which further research is needed are indicated in a future outlook.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

Digital Filter ASIC for NASA Deep Space Radio Science

NASA Technical Reports Server (NTRS)

Kowalski, James E.

1995-01-01

This paper is about the implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB. The chip uses two decimation by five units and six decimations by two executed by a single decimation by two units. The six decimations by two consist of six halfband filters, five having 30-taps and one having 51-taps. Use of a 16x16 register file for the digital delay lines enables implementation in the Vitesse 350K gate array.

High-Speed Binary-Output Image Sensor

NASA Technical Reports Server (NTRS)

Fossum, Eric; Panicacci, Roger A.; Kemeny, Sabrina E.; Jones, Peter D.

1996-01-01

Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.

F-16XL ship #1 (#849) during first flight of the Digital Flight Control System (DFCS)

NASA Technical Reports Server (NTRS)

1997-01-01

After completing its first flight with the Digital Flight Control System on December 16, 1997, the F-16XL #1 aircraft began a series of envelope expansion flights. On January 27 and 29, 1998, it successfully completed structural clearance tests, as well as most of the load testing Only flights at Mach 1.05 at 10,000 feet, Mach 1.1 at 15,000 feet, and Mach 1.2 at 20,000 feet remained. During the next flight, on February 4, an instrumentation problem cut short the planned envelope expansion tests. After the problem was corrected, the F-16XL returned to flight status, and on February 18 and 20, flight control and evaluation flights were made. Two more research flights were planned for the following week, but another problem appeared. During the ground start up, project personnel noticed that the leading edge flap moved without being commanded. The Digital Flight Control Computer was sent to the Lockheed-Martin facility at Fort Worth, where the problem was traced to a defective chip in the computer. After it was replaced, the F-16XL #1 flew a highly successful flight controls and handling qualities evaluation flight on March 26, clearing the way for the final tests. The final limited loads expansion flight occurred on March 31, and was fully successful. As a result, the on-site Lockheed-Martin loads engineer cleared the aircraft to Mach 1.8. The remaining two handling qualities and flight control evaluation flights were both made on April 3, 1998. These three flights concluded the flight test portion of the DFCS upgrade.

Rapid determination of cell mass and density using digitally controlled electric field in a microfluidic chip.

PubMed

Zhao, Yuliang; Lai, Hok Sum Sam; Zhang, Guanglie; Lee, Gwo-Bin; Li, Wen Jung

2014-11-21

The density of a single cell is a fundamental property of cells. Cells in the same cycle phase have similar volume, but the differences in their mass and density could elucidate each cell's physiological state. Here we report a novel technique to rapidly measure the density and mass of a single cell using an optically induced electrokinetics (OEK) microfluidic platform. Presently, single cellular mass and density measurement devices require a complicated fabrication process and their output is not scalable, i.e., it is extremely difficult to measure the mass and density of a large quantity of cells rapidly. The technique reported here operates on a principle combining sedimentation theory, computer vision, and microparticle manipulation techniques in an OEK microfluidic platform. We will show in this paper that this technique enables the measurement of single-cell volume, density, and mass rapidly and accurately in a repeatable manner. The technique is also scalable - it allows simultaneous measurement of volume, density, and mass of multiple cells. Essentially, a simple time-controlled projected light pattern is used to illuminate the selected area on the OEK microfluidic chip that contains cells to lift the cells to a particular height above the chip's surface. Then, the cells are allowed to "free fall" to the chip's surface, with competing buoyancy, gravitational, and fluidic drag forces acting on the cells. By using a computer vision algorithm to accurately track the motion of the cells and then relate the cells' motion trajectory to sedimentation theory, the volume, mass, and density of each cell can be rapidly determined. A theoretical model of micro-sized spheres settling towards an infinite plane in a microfluidic environment is first derived and validated experimentally using standard micropolystyrene beads to demonstrate the viability and accuracy of this new technique. Next, we show that the yeast cell volume, mass, and density could be rapidly determined using this technology, with results comparable to those using the existing method suspended microchannel resonator.

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

Optimization of the polyplanar optical display electronics for a monochrome B-52 display

NASA Astrophysics Data System (ADS)

DeSanto, Leonard

1998-09-01

The Polyplanar Optical Display (POD) is a unique display screen which can be used with any projection source. The prototype ten-inch display is two inches thick and has a matte black face which allows for high contrast images. The prototype being developed is a form, fit and functional replacement display for the B-52 aircraft which uses a monochrome ten-inch display. In order to achieve a long lifetime, the new display uses a new 200 mW green solid-state laser (10,000 hr. life) at 532 nm as its light source. To produce real-time video, the laser light is being modulated by a Digital Light Processing (DLPTM) chip manufactured by Texas Instruments (TI). In order to use the solid-state laser as the light source and also fit within the constraints of the B-52 display, the Digital Micromirror Device (DMDTM) chip is operated remotely from the Texas Instruments circuit board. In order to achieve increased brightness a monochrome digitizing interface was investigated. The operation of the DMDTM divorced from the light engine and the interfacing of the DMDTM board with the RS-170 video format specific to the B-52 aircraft will be discussed, including the increased brightness of the monochrome digitizing interface. A brief description of the electronics required to drive the new 200 mW laser is also presented.

The next generation of neural network chips

DOE Office of Scientific and Technical Information (OSTI.GOV)

Beiu, V.

There have been many national and international neural networks research initiatives: USA (DARPA, NIBS), Canada (IRIS), Japan (HFSP) and Europe (BRAIN, GALA TEA, NERVES, ELENE NERVES 2) -- just to mention a few. Recent developments in the field of neural networks, cognitive science, bioengineering and electrical engineering have made it possible to understand more about the functioning of large ensembles of identical processing elements. There are more research papers than ever proposing solutions and hardware implementations are by no means an exception. Two fields (computing and neuroscience) are interacting in ways nobody could imagine just several years ago, and --more » with the advent of new technologies -- researchers are focusing on trying to copy the Brain. Such an exciting confluence may quite shortly lead to revolutionary new computers and it is the aim of this invited session to bring to light some of the challenging research aspects dealing with the hardware realizability of future intelligent chips. Present-day (conventional) technology is (still) mostly digital and, thus, occupies wider areas and consumes much more power than the solutions envisaged. The innovative algorithmic and architectural ideals should represent important breakthroughs, paving the way towards making neural network chips available to the industry at competitive prices, in relatively small packages and consuming a fraction of the power required by equivalent digital solutions.« less

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

NASA Technical Reports Server (NTRS)

Kaplan, Steven B.; Pylov, Sergey V.; Pambianchi, Michael

2003-01-01

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

An optimized resistor pattern for temperature gradient control in microfluidics

NASA Astrophysics Data System (ADS)

Selva, Bertrand; Marchalot, Julien; Jullien, Marie-Caroline

2009-06-01

In this paper, we demonstrate the possibility of generating high-temperature gradients with a linear temperature profile when heating is provided in situ. Thanks to improved optimization algorithms, the shape of resistors, which constitute the heating source, is optimized by applying the genetic algorithm NSGA-II (acronym for the non-dominated sorting genetic algorithm) (Deb et al 2002 IEEE Trans. Evol. Comput. 6 2). Experimental validation of the linear temperature profile within the cavity is carried out using a thermally sensitive fluorophore, called Rhodamine B (Ross et al 2001 Anal. Chem. 73 4117-23, Erickson et al 2003 Lab Chip 3 141-9). The high level of agreement obtained between experimental and numerical results serves to validate the accuracy of this method for generating highly controlled temperature profiles. In the field of actuation, such a device is of potential interest since it allows for controlling bubbles or droplets moving by means of thermocapillary effects (Baroud et al 2007 Phys. Rev. E 75 046302). Digital microfluidics is a critical area in the field of microfluidics (Dreyfus et al 2003 Phys. Rev. Lett. 90 14) as well as in the so-called lab-on-a-chip technology. Through an example, the large application potential of such a technique is demonstrated, which entails handling a single bubble driven along a cavity using simple and tunable embedded resistors.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

Design of an anti-Rician-fading modem for mobile satellite communication systems

NASA Technical Reports Server (NTRS)

Kojima, Toshiharu; Ishizu, Fumio; Miyake, Makoto; Murakami, Keishi; Fujino, Tadashi

1995-01-01

To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.

A CMOS Imager with Focal Plane Compression using Predictive Coding

NASA Technical Reports Server (NTRS)

Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

2007-01-01

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Lensfree on-chip microscopy over a wide field-of-view using pixel super-resolution

PubMed Central

Bishara, Waheb; Su, Ting-Wei; Coskun, Ahmet F.; Ozcan, Aydogan

2010-01-01

We demonstrate lensfree holographic microscopy on a chip to achieve ~0.6 µm spatial resolution corresponding to a numerical aperture of ~0.5 over a large field-of-view of ~24 mm2. By using partially coherent illumination from a large aperture (~50 µm), we acquire lower resolution lensfree in-line holograms of the objects with unit fringe magnification. For each lensfree hologram, the pixel size at the sensor chip limits the spatial resolution of the reconstructed image. To circumvent this limitation, we implement a sub-pixel shifting based super-resolution algorithm to effectively recover much higher resolution digital holograms of the objects, permitting sub-micron spatial resolution to be achieved across the entire sensor chip active area, which is also equivalent to the imaging field-of-view (24 mm2) due to unit magnification. We demonstrate the success of this pixel super-resolution approach by imaging patterned transparent substrates, blood smear samples, as well as Caenoharbditis Elegans. PMID:20588977

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Advanced system on a chip microelectronics for spacecraft and science instruments

NASA Astrophysics Data System (ADS)

Paschalidis, Nikolaos P.

2003-01-01

The explosive growth of the modern microelectronics field opens new horizons for the development of new lightweight, low power, and smart spacecraft and science instrumentation systems in the new millennium explorations. Although this growth is mostly driven by the commercial need for low power, portable and computationally intensive products, the applicability is obvious in the space sector. The additional difficulties needed to be overcome for applicability in space include radiation hardness for total ionizing dose and single event effects (SEE), and reliability. Additionally, this new capability introduces a whole new philosophy of design and R&D, with strong implications in organizational and inter-agency program management. One key component specifically developed towards low power, small size, highly autonomous spacecraft systems, is the smart sensor remote input/output (TRIO) chip. TRIO can interface to 32 transducers with current sources/sinks and voltage sensing. It includes front-end analog signal processing, a 10-bit ADC, memory, and standard serial and parallel I/Os. These functions are very useful for spacecraft and subsystems health and status monitoring, and control actions. The key contributions of the TRIO are feasibility of modular architectures, elimination of several miles of wire harnessing, and power savings by orders of magnitude. TRIO freely operates from a single power supply 2.5- 5.5 V with power dissipation <10 mW. This system on a chip device rapidly becomes a NASA and Commercial Space standard as it is already selected by thousands in several new millennium missions, including Europa Orbiter, Mars Surveyor Program, Solar Probe, Pluto Express, Stereo, Contour, Messenger, etc. In the Science Instrumentation field common instruments that can greatly take advantage of the new technologies are: energetic-particle/plasma and wave instruments, imagers, mass spectrometers, X-ray and UV spectrographs, magnetometers, laser rangefinding instruments, etc. Common measurements that apply to many of these instruments are precise time interval measurement and high resolution read-out of solid state detectors. A precise time interval measurement chip was specially developed that achieves ˜100 ps (×10 improvement) time resolution at a power dissipation ˜20 mW (×50 improvement), dead time ˜1.5 μs (×20 improvement), and chip die size 5 mm×5 mm versus two 20 cm×20 cm doubled sided boards. This device is selected as a key enabling technology for several NASA particle, delay line imaging, and laser range finding instruments onboard (NASA Image, Messenger, etc. missions). Another device with universal application is radiation energy read-out from solid state detectors. Multi-channel low-power and end-to-end sensor input—digital output is key for the new generation instruments. The readout channel comprises of a Charge Sensitive Preamplifier with a target sensitivity of ˜1 KeV FWHM at 20 pf detector capacitance, a Shaper Amplifier with programmable time constant/gain, and an ADC. The read-out chip together with the precise time interval chip comprises the essential elements of a common particle spectroscopy instrument. To mention some more applications fast-signal acquisition—and digitization is a very useful function for a category of instrument such as mass spectroscopy and profile laser rangefinding. The single chip approach includes a high bandwidth preamplifier, fast sampling ˜5 ns, analog memory ˜10K locations, 12-bit ADC and serial/parallel I/Os. The wealth of the applications proves the advanced microelectronics field as a key enabling technology for the new millennium space exploration.

An Embedded Sensor Node Microcontroller with Crypto-Processors.

PubMed

Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

2016-04-27

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed.

Impact of device level faults in a digital avionic processor

NASA Technical Reports Server (NTRS)

Suk, Ho Kim

1989-01-01

This study describes an experimental analysis of the impact of gate and device-level faults in the processor of a Bendix BDX-930 flight control system. Via mixed mode simulation, faults were injected at the gate (stuck-at) and at the transistor levels and, their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model, as far as error activity or detection within a functional unit is concerned. In so far as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other. The stuck-at model, however, overestimates, by over 100 percent, the probability of fault propagation to the output pins. An evaluation of the Mean Error Durations and the Mean Time Between Errors at the output pins shows that the stuck-at model significantly underestimates (by 62 percent) the impact of an internal chip fault on the output pins. Finally, the study also quantifies the impact of device fault by location, both internally and at the output pins.

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

NASA Astrophysics Data System (ADS)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

An Embedded Sensor Node Microcontroller with Crypto-Processors

PubMed Central

Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

2016-01-01

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed. PMID:27128925

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

Flight Qualified Micro Sun Sensor

NASA Technical Reports Server (NTRS)

Liebe, Carl Christian; Mobasser, Sohrab; Wrigley, Chris; Schroeder, Jeffrey; Bae, Youngsam; Naegle, James; Katanyoutanant, Sunant; Jerebets, Sergei; Schatzel, Donald; Lee, Choonsup

2007-01-01

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Batch manufacturing: Six strategic needs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ash, R.H.; Chappell, D.A.

1995-08-01

Since the advent of industrial digital control systems in the mid-1970s, industry has had the promise of integrated, configurable digital batch control systems to replace the morass of electromechanical devices like relays and stepping switches, recorders, and indicators which comprised the components of previous generations of batch control systems - the {open_quotes}monolithic monsters{close_quotes} of the 1960s and earlier. To help fulfill that promise, there have been many wide-ranging proprietary automation solutions for batch control since 1975, many of them technically excellent. However, even the best examples suffered from the lack of a common language and unifying concept permitting separate systemsmore » to be interconnected and work together. Today, some 20 years after the digital revolution began, industry has microprocessors, memory chips, data highways, and other marvelous technology to help automate the control of discontinuous processes. They also are on the way to having an accepted standard for batch automation, ISA S88. Batching systems are at once conceptually simple but executionally complex. The notion of adding ingredients one at a time to a vat, mixing, and then processing into final form is as old as the stone age. Every homemaker on earth, male or female, is familiar with how to follow a recipe to create some sumptuous item of culinary delight. Food recipes, so familiar and ubiquitous, are really just microcosms of the S88 recipe standard. They contain the same components: (1) Header (name and description of item being prepared, sometimes serving size); (2) Formula (list and amount of ingredients); (3) Equipment requirements (pans, mixing and cooking equipment); (4) Procedure (description of order of ingredient addition, mixing and other processing steps, baking/cooling time, and other processing steps); and (5) Other information (safety, cautions, and other miscellaneous instructions).« less

Implementation of the Domino Sampling Waveform digitizer in the PIBETA experiment

NASA Astrophysics Data System (ADS)

Wang, Ying

The Domino Sampling Chip(DSC)-Waveform digitization system is a significant addition to electronics arsenal of PIBETA experiment. It is used to digitize waveforms from every photo tube in the detector. Through carefully programmed offline analysis of its raw data collected during regular runtime, better timing and energy resolution are achieved compared with feast's results. And more importantly, the geometric character of the digitized waveform which contains information of energy deposition of particle decays can be utilized for particle identification, a great advantage that regular unit could not possess. In addition to fastbus, incorporate DSC data through its offline analysis including timing and energy offset, scale calibration will contribute a final more precise result of PIBETA experiment.

Compact, Low-Overhead, MIL-STD-1553B Controller

NASA Technical Reports Server (NTRS)

Katz, Richard; Barto, Rod

2009-01-01

A compact and flexible controller has been developed to provide MIL-STD- 1553B Remote Terminal (RT) communications and supporting and related functions with minimal demand on the resources of the system in which the controller is to be installed. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD-1553B is commonly used in defense and space applications.) Many other MIL-STD-1553B RT controllers are complicated, and to enable them to function, it is necessary to provide software and to use such ancillary separate hardware devices as microprocessors and dual-port memories. The present controller functions without need for software and any ancillary hardware. In addition, it contains a flexible system interface and extensive support hardware while including on-chip error-checking and diagnostic support circuitry. This controller is implemented within part of a modern field-programmable gate array.

Single-Chip Microcomputer Control Of The PWM Inverter

NASA Astrophysics Data System (ADS)

Morimoto, Masayuki; Sato, Shinji; Sumito, Kiyotaka; Oshitani, Katsumi

1987-10-01

A single-chip microcomputer-based con-troller for a pulsewidth modulated 1.7 KVA inverter of an airconditioner is presented. The PWM pattern generation and the system control of the airconditioner are achieved by software of the 8-bit single-chip micro-computer. The single-chip microcomputer has the disadvantages of low processing speed and small memory capacity which can be overcome by the magnetic flux control method. The PWM pattern is generated every 90 psec. The memory capacity of the PWM look-up table is less than 2 kbytes. The simple and reliable control is realized by the software-based implementation.

Anti-Hassle Chip

NASA Technical Reports Server (NTRS)

1998-01-01

With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

First Results of Digital Topography Applied to Macromolecular Crystals

NASA Technical Reports Server (NTRS)

Lovelace, J.; Soares, A. S.; Bellamy, H.; Sweet, R. M.; Snell, E. H.; Borgstahl, G.

2004-01-01

An inexpensive digital CCD camera was used to record X-ray topographs directly from large imperfect crystals of cubic insulin. The topographs recorded were not as detailed as those which can be measured with film or emulsion plates but do show great promise. Six reflections were recorded using a set of finely spaced stills encompassing the rocking curve of each reflection. A complete topographic reflection profile could be digitally imaged in minutes. Interesting and complex internal structure was observed by this technique.The CCD chip used in the camera has anti-blooming circuitry and produced good data quality even when pixels became overloaded.

Learning in Stochastic Bit Stream Neural Networks.

PubMed

van Daalen, Max; Shawe-Taylor, John; Zhao, Jieyu

1996-08-01

This paper presents learning techniques for a novel feedforward stochastic neural network. The model uses stochastic weights and the "bit stream" data representation. It has a clean analysable functionality and is very attractive with its great potential to be implemented in hardware using standard digital VLSI technology. The design allows simulation at three different levels and learning techniques are described for each level. The lowest level corresponds to on-chip learning. Simulation results on three benchmark MONK's problems and handwritten digit recognition with a clean set of 500 16 x 16 pixel digits demonstrate that the new model is powerful enough for the real world applications. Copyright 1996 Elsevier Science Ltd

75 FR 16507 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-01

... Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same... synchronous dynamic random access memory controllers and products containing same by reason of infringement of... semiconductor chips having synchronous dynamic random access memory controllers and products containing same...

A micro surface tension pump (MISPU) in a glass microchip.

PubMed

Peng, Xing Yue Larry

2011-01-07

A non-membrane micro surface tension pump (MISPU) was fabricated on a glass microchip by one-step glass etching. It needs no material other than glass and is driven by digital gas pressure. The MISPU can be seen working like a piston pump inside the glass microchip under a microscope. The design of the valves (MISVA) and pistons (MISTON) was based on the surface tension theory of the micro surface tension alveolus (MISTA). The digital gas pressure controls the moving gas-liquid interface to open or close the input and output MISVAs to refill or drive the MISTON for pumping a liquid. Without any moving parts, a MISPU is a kind of long-lasting micro pump for micro chips that does not lose its water pumping efficiency over a 20-day period. The volumetric pump output varied from 0 to 10 nl s(-1) when the pump cycle time decreased from 5 min to 15 s. The pump head pressure was 1 kPa.

Continuous Digital Light Processing (cDLP): Highly Accurate Additive Manufacturing of Tissue Engineered Bone Scaffolds.

PubMed

Dean, David; Jonathan, Wallace; Siblani, Ali; Wang, Martha O; Kim, Kyobum; Mikos, Antonios G; Fisher, John P

2012-03-01

Highly accurate rendering of the external and internal geometry of bone tissue engineering scaffolds effects fit at the defect site, loading of internal pore spaces with cells, bioreactor-delivered nutrient and growth factor circulation, and scaffold resorption. It may be necessary to render resorbable polymer scaffolds with 50 μm or less accuracy to achieve these goals. This level of accuracy is available using Continuous Digital Light processing (cDLP) which utilizes a DLP(®) (Texas Instruments, Dallas, TX) chip. One such additive manufacturing device is the envisionTEC (Ferndale, MI) Perfactory(®). To use cDLP we integrate a photo-crosslinkable polymer, a photo-initiator, and a biocompatible dye. The dye attenuates light, thereby limiting the depth of polymerization. In this study we fabricated scaffolds using the well-studied resorbable polymer, poly(propylene fumarate) (PPF), titanium dioxide (TiO(2)) as a dye, Irgacure(®) 819 (BASF [Ciba], Florham Park, NJ) as an initiator, and diethyl fumarate as a solvent to control viscosity.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Integrated optical transceiver with electronically controlled optical beamsteering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Davids, Paul; DeRose, Christopher; Tauke-Pedretti, Anna

A beam-steering optical transceiver is provided. The transceiver includes one or more modules, each comprising an antenna chip and a control chip bonded to the antenna chip. Each antenna chip has a feeder waveguide, a plurality of row waveguides that tap off from the feeder waveguide, and a plurality of metallic nanoantenna elements arranged in a two-dimensional array of rows and columns such that each row overlies one of the row waveguides. Each antenna chip also includes a plurality of independently addressable thermo-optical phase shifters, each configured to produce a thermo-optical phase shift in a respective row. Each antenna chipmore » also has, for each row, a row-wise heating circuit configured to produce a respective thermo-optic phase shift at each nanoantenna element along its row. The control chip includes controllable current sources for the independently addressable thermo-optical phase shifters and the row-wise heating circuits.« less

Microfluidic Devices for Forensic DNA Analysis: A Review

PubMed Central

Bruijns, Brigitte; van Asten, Arian; Tiggelaar, Roald; Gardeniers, Han

2016-01-01

Microfluidic devices may offer various advantages for forensic DNA analysis, such as reduced risk of contamination, shorter analysis time and direct application at the crime scene. Microfluidic chip technology has already proven to be functional and effective within medical applications, such as for point-of-care use. In the forensic field, one may expect microfluidic technology to become particularly relevant for the analysis of biological traces containing human DNA. This would require a number of consecutive steps, including sample work up, DNA amplification and detection, as well as secure storage of the sample. This article provides an extensive overview of microfluidic devices for cell lysis, DNA extraction and purification, DNA amplification and detection and analysis techniques for DNA. Topics to be discussed are polymerase chain reaction (PCR) on-chip, digital PCR (dPCR), isothermal amplification on-chip, chip materials, integrated devices and commercially available techniques. A critical overview of the opportunities and challenges of the use of chips is discussed, and developments made in forensic DNA analysis over the past 10–20 years with microfluidic systems are described. Areas in which further research is needed are indicated in a future outlook. PMID:27527231

Compact and light-weight automated semen analysis platform using lensfree on-chip microscopy.

PubMed

Su, Ting-Wei; Erlinger, Anthony; Tseng, Derek; Ozcan, Aydogan

2010-10-01

We demonstrate a compact and lightweight platform to conduct automated semen analysis using a lensfree on-chip microscope. This holographic on-chip imaging platform weighs ∼46 g, measures ∼4.2 × 4.2 × 5.8 cm, and does not require any lenses, lasers or other bulky optical components to achieve phase and amplitude imaging of sperms over ∼24 mm(2) field-of-view with an effective numerical aperture of ∼0.2. Using this wide-field lensfree on-chip microscope, semen samples are imaged for ∼10 s, capturing a total of ∼20 holographic frames. Digital subtraction of these consecutive lensfree frames, followed by appropriate processing of the reconstructed images, enables automated quantification of the count, the speed and the dynamic trajectories of motile sperms, while summation of the same frames permits counting of immotile sperms. Such a compact and lightweight automated semen analysis platform running on a wide-field lensfree on-chip microscope could be especially important for fertility clinics, personal male fertility tests, as well as for field use in veterinary medicine such as in stud farming and animal breeding applications.

On-chip microsystems in silicon: opportunities and limitations

NASA Astrophysics Data System (ADS)

Wolffenbuttel, R. F.

1996-03-01

Integrated on-chip micro-instrumentation systems in silicon are complete data acquisition systems on a single chip. This concept has appeared to be the ultimate solution in many applications, as it enables in principle the metamorphosis of a basic sensing element, affected with many shortcomings, into an on-chip data acquisition unit that provides an output digital data stream in a standard format not corrupted by sensor non-idealities. Market acceptance would be maximum, as no special knowledge about the internal operation is required, self-test and self-calibration can be included and the dimensions are not different from those of the integrated circuit. The various aspects that are relevant in estimating the constraints for successful implementation of the integrated silicon smart sensor will be outlined in comparison with the properties of more conventional sensor fabrication technologies. It will be shown that the acceptance of on-chip functional integration in an application depends primarily on the added value in terms of improved specification or functionality that the resulting device provides in that application. The economic viability is therefore decisive rather than the technological constraints. This is in contrast to the traditional technology push prevailing in sensor research over market pull mechanisms.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Resolution power in digital in-line holography

NASA Astrophysics Data System (ADS)

Garcia-Sucerquia, J.; Xu, W.; Jericho, S. K.; Jericho, M. H.; Klages, P.; Kreuzer, H. J.

2006-01-01

Digital in-line holographic microscopy (DIHM) can achieve wavelength resolution both laterally and in depth with the simple optical setup consisting of a laser illuminating a wavelength-sized pinhole and a CCD camera for recording the hologram. The reconstruction is done numerically on the basis of the Kirchhoff-Helmholtz transform which yields a three-dimensional image of the objects throughout the sample volume. Resolution in DIHM depends on several controllable factors or parameters: (1) pinhole size controlling spatial coherence, (2) numerical aperture given by the size and positioning of the recording CCD chip, (3) pixel density and dynamic range controlling fringe resolution and noise level in the hologram and (4) wavelength. We present a detailed study of the individual and combined effects of these factors by doing an analytical analysis coupled with numerical simulations of holograms and their reconstruction. The result of this analysis is a set of criteria, also in the form of graphs, which can be used for the optimum design of the DIHM setup. We will also present a series of experimental results that test and confirm our theoretical analysis. The ultimate resolution to date is the imaging of the motion of submicron spheres and bacteria, a few microns apart, with speeds of hundreds of microns per second.

Manufacturing Methods and Technology for Digital Fault Isolation for Printed Circuit Boards.

DTIC Science & Technology

1979-08-25

microprocessors and support chips, ROMs, RAMs, UARTs , etc. They also include rules for busses and memory testing. The special rules for test points emphasize...I 8). UART .. ...................................................... I 9). SAT...0.0 I ( 8). UART ...................................................... 0.0O S 9). SAT

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rey, D.; Ryan, W.; Ross, M.

A method for more efficiently utilizing the frequency bandwidth allocated for data transmission is presented. Current space and range communication systems use modulation and coding schemes that transmit 0.5 to 1.0 bits per second per Hertz of radio frequency bandwidth. The goal in this LDRD project is to increase the bandwidth utilization by employing advanced digital communications techniques. This is done with little or no increase in the transmit power which is usually very limited on airborne systems. Teaming with New Mexico State University, an implementation of trellis coded modulation (TCM), a coding and modulation scheme pioneered by Ungerboeck, wasmore » developed for this application and simulated on a computer. TCM provides a means for reliably transmitting data while simultaneously increasing bandwidth efficiency. The penalty is increased receiver complexity. In particular, the trellis decoder requires high-speed, application-specific digital signal processing (DSP) chips. A system solution based on the QualComm Viterbi decoder and the Graychip DSP receiver chips is presented.« less

Analog pixel array detectors.

PubMed

Ercan, A; Tate, M W; Gruner, S M

2006-03-01

X-ray pixel array detectors (PADs) are generally thought of as either digital photon counters (DPADs) or X-ray analog-integrating pixel array detectors (APADs). Experiences with APADs, which are especially well suited for X-ray imaging experiments where transient or high instantaneous flux events must be recorded, are reported. The design, characterization and experimental applications of several APAD designs developed at Cornell University are discussed. The simplest design is a ;flash' architecture, wherein successive integrated X-ray images, as short as several hundred nanoseconds in duration, are stored in the detector chips for later off-chip digitization. Radiography experiments using a prototype flash APAD are summarized. Another design has been implemented that combines flash capability with the ability to continuously stream X-ray images at slower (e.g. milliseconds) rates. Progress is described towards radiation-hardened APADs that can be tiled to cover a large area. A mixed-mode PAD, design by combining many of the attractive features of both APADs and DPADs, is also described.

Implementation of olfactory bulb glomerular-layer computations in a digital neurosynaptic core.

PubMed

Imam, Nabil; Cleland, Thomas A; Manohar, Rajit; Merolla, Paul A; Arthur, John V; Akopyan, Filipp; Modha, Dharmendra S

2012-01-01

We present a biomimetic system that captures essential functional properties of the glomerular layer of the mammalian olfactory bulb, specifically including its capacity to decorrelate similar odor representations without foreknowledge of the statistical distributions of analyte features. Our system is based on a digital neuromorphic chip consisting of 256 leaky-integrate-and-fire neurons, 1024 × 256 crossbar synapses, and address-event representation communication circuits. The neural circuits configured in the chip reflect established connections among mitral cells, periglomerular cells, external tufted cells, and superficial short-axon cells within the olfactory bulb, and accept input from convergent sets of sensors configured as olfactory sensory neurons. This configuration generates functional transformations comparable to those observed in the glomerular layer of the mammalian olfactory bulb. Our circuits, consuming only 45 pJ of active power per spike with a power supply of 0.85 V, can be used as the first stage of processing in low-power artificial chemical sensing devices inspired by natural olfactory systems.

3D digital image correlation using single color camera pseudo-stereo system

NASA Astrophysics Data System (ADS)

Li, Junrui; Dan, Xizuo; Xu, Wan; Wang, Yonghong; Yang, Guobiao; Yang, Lianxiang

2017-10-01

Three dimensional digital image correlation (3D-DIC) has been widely used by industry to measure the 3D contour and whole-field displacement/strain. In this paper, a novel single color camera 3D-DIC setup, using a reflection-based pseudo-stereo system, is proposed. Compared to the conventional single camera pseudo-stereo system, which splits the CCD sensor into two halves to capture the stereo views, the proposed system achieves both views using the whole CCD chip and without reducing the spatial resolution. In addition, similarly to the conventional 3D-DIC system, the center of the two views stands in the center of the CCD chip, which minimizes the image distortion relative to the conventional pseudo-stereo system. The two overlapped views in the CCD are separated by the color domain, and the standard 3D-DIC algorithm can be utilized directly to perform the evaluation. The system's principle and experimental setup are described in detail, and multiple tests are performed to validate the system.

SAW correlator spread spectrum receiver

DOEpatents

Brocato, Robert W

2014-04-01

A surface acoustic wave (SAW) correlator spread-spectrum (SS) receiver is disclosed which utilizes a first demodulation stage with a chip length n and a second demodulation stage with a chip length m to decode a transmitted SS signal having a code length l=n.times.m which can be very long (e.g. up to 2000 chips or more). The first demodulation stage utilizes a pair of SAW correlators which demodulate the SS signal to generate an appropriate code sequence at an intermediate frequency which can then be fed into the second demodulation stage which can be formed from another SAW correlator, or by a digital correlator. A compound SAW correlator comprising two input transducers and a single output transducer is also disclosed which can be used to form the SAW correlator SS receiver, or for use in processing long code length signals.

Microcomputer-based Peltier thermostat for precision optical radiation measurements

NASA Astrophysics Data System (ADS)

Zhu, Xiaosong; Krochmann, Eike; Chen, Jiashu

1992-03-01

We have developed a microcomputer-based thermostat for a light measuring head in precision optical radiation measurements. This thermostat consists of a single-chip microcomputer, a digital-to-analog converter, a liquid crystal display, a power operational amplifier, and a Peltier element (thermoelectric cooler). The Peltier element keeps the temperature of the photometer head at 20±0.1 °C in the ambient temperature range from -20 to 60 °C. A control algorithm which combines the ``Bang-Bang'' mode and proportional-plus-integral-plus-derivative mode is used to achieve fast and smooth thermostatic performance. This thermostat is effective, inexpensive, and easy to adjust. Several applications of the Peltier thermostat are mentioned.

SYRMEP front-end and read-out electronics

NASA Astrophysics Data System (ADS)

Arfelli, F.; Bonvicini, V.; Bravin, A.; Cantatore, G.; Castelli, E.; Cristaudo, P.; Di Michiel, M.; Longo, R.; Olivo, A.; Pani, S.; Pontoni, D.; Poropat, P.; Prest, M.; Rashevsky, A.; Tomasini, F.; Tromba, G.; Vacchi, A.; Vallazza, E.

1998-02-01

The SYRMEP approach to digital mammography implies the use of a monochromatic X-ray beam from a synchrotron source and a slot of superimposed silicon microstrip detectors as a scanning image receptor. The microstrips are read by 32-channel chips mounted on 7-layer hybrid circuits which receive control signals and operating voltages from a MASTER-SLAVE configuration of cards. The MASTER card is driven by the CIRM, a dedicated CAMAC module whose timing function can be easily excluded to obtain data-storage-only units connected to different MASTERs: this second-level modular expansion capability fully achieves the tasks of an electronics system able to follow the SYRMEP detector growth till the final size of seven thousands of channels.

Digital photography for the light microscope: results with a gated, video-rate CCD camera and NIH-image software.

PubMed

Shaw, S L; Salmon, E D; Quatrano, R S

1995-12-01

In this report, we describe a relatively inexpensive method for acquiring, storing and processing light microscope images that combines the advantages of video technology with the powerful medium now termed digital photography. Digital photography refers to the recording of images as digital files that are stored, manipulated and displayed using a computer. This report details the use of a gated video-rate charge-coupled device (CCD) camera and a frame grabber board for capturing 256 gray-level digital images from the light microscope. This camera gives high-resolution bright-field, phase contrast and differential interference contrast (DIC) images but, also, with gated on-chip integration, has the capability to record low-light level fluorescent images. The basic components of the digital photography system are described, and examples are presented of fluorescence and bright-field micrographs. Digital processing of images to remove noise, to enhance contrast and to prepare figures for printing is discussed.

Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect.

PubMed

Liao, Chen; Hu, Shiyan

2014-03-01

Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique.

Digital detection of multiple minority mutants and expression levels of multiple colorectal cancer-related genes using digital-PCR coupled with bead-array.

PubMed

Huang, Huan; Li, Shuo; Sun, Lizhou; Zhou, Guohua

2015-01-01

To simultaneously analyze mutations and expression levels of multiple genes on one detection platform, we proposed a method termed "multiplex ligation-dependent probe amplification-digital amplification coupled with hydrogel bead-array" (MLPA-DABA) and applied it to diagnose colorectal cancer (CRC). CRC cells and tissues were sampled to extract nucleic acid, perform MLPA with sequence-tagged probes, perform digital emulsion polymerase chain reaction (PCR), and produce a hydrogel bead-array to immobilize beads and form a single bead layer on the array. After hybridization with fluorescent probes, the number of colored beads, which reflects the abundance of expressed genes and the mutation rate, was counted for diagnosis. Only red or green beads occurred on the chips in the mixed samples, indicating the success of single-molecule PCR. When a one-source sample was analyzed using mixed MLPA probes, beads of only one color occurred, suggesting the high specificity of the method in analyzing CRC mutation and gene expression. In gene expression analysis of a CRC tissue from one CRC patient, the mutant percentage was 3.1%, and the expression levels of CRC-related genes were much higher than those of normal tissue. The highly sensitive MLPA-DABA succeeds in the relative quantification of mutations and gene expressions of exfoliated cells in stool samples of CRC patients on the same chip platform. MLPA-DABA coupled with hydrogel bead-array is a promising method in the non-invasive diagnosis of CRC.

Optimization of the polyplanar optical display electronics for a monochrome B-52 display

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeSanto, L.

The Polyplanar Optical Display (POD) is a unique display screen which can be used with any projection source. The prototype ten-inch display is two inches thick and has a matte black face which allows for high contrast images. The prototype being developed is a form, fit and functional replacement display for the B-52 aircraft which uses a monochrome ten-inch display. In order to achieve a long lifetime, the new display uses a new 200 mW green solid-state laser (10,000 hr. life) at 532 nm as its light source. To produce real-time video, the laser light is being modulated by amore » Digital Light Processing (DLP{trademark}) chip manufactured by Texas Instruments (TI). In order to use the solid-state laser as the light source and also fit within the constraints of the B-52 display, the Digital Micromirror Device (DMD{trademark}) chip is operated remotely from the Texas Instruments circuit board. In order to achieve increased brightness a monochrome digitizing interface was investigated. The operation of the DMD{trademark} divorced from the light engine and the interfacing of the DMD{trademark} board with the RS-170 video format specific to the B-52 aircraft will be discussed, including the increased brightness of the monochrome digitizing interface. A brief description of the electronics required to drive the new 200 mW laser is also presented.« less

Tinker's Toys: Lessons from Bank Street: Hardware.

ERIC Educational Resources Information Center

Tinker, Robert

1985-01-01

Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

NASA Astrophysics Data System (ADS)

Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

2017-10-01

In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

Performance analysis of an all-digital BPSK direct sequence spread-spectrum IF receiver architecture

NASA Astrophysics Data System (ADS)

Chung, Bong-Young; Chien, Charles; Samueli, Henry; Jain, Rajeev

1993-09-01

A VLSI architecture for an all-digital binary phase shift keyed (BPSK) direct-sequence (DS) spread spectrum (SS) IF receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costar loop for carrier recovery and a delay-locked loop for clock recovery. For the PN acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/ second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel. The probability of PN acquisition within 5 ms is approximately 56% at -17 dB IF input SNR and 82% at -11 dB IF input SNR.

Identification of a novel large deletion in a patient with severe factor V deficiency using an in-house F5 MLPA assay.

PubMed

Nuzzo, F; Paraboschi, E M; Straniero, L; Pavlova, A; Duga, S; Castoldi, E

2015-01-01

Factor V (FV) deficiency is a rare autosomal recessive bleeding disorder caused by mutations in the F5 gene. FV-deficient patients in whom no mutation or only one mutation is found may harbour large gene rearrangements, which are not detected by conventional mutation screening strategies. The aim of this study was to develop and validate a multiplex ligation-dependent probe amplification (MLPA) assay for the detection of large deletions and duplications in the F5 gene. Twenty-two MLPA probes targeting 19 of the 25 exons and the upstream and downstream regions of the F5 gene were designed and tested in 10 normal controls, a patient with a known heterozygous deletion of F5 exons 1-7 (positive control) and 14 genetically unexplained FV-deficient patients. MLPA results were confirmed by digital PCR on a QuantStudio(™) 3D Digital PCR System. The F5-specific probes yielded a reproducible peak profile in normal controls, correctly detected the known deletion in the positive control and suggested the presence of a novel deletion of exons 9-10 in a patient with undetectable FV levels and only one identified mutation. Follow-up by chip-based digital PCR, long-range PCR and direct sequencing confirmed that this patient carried a heterozygous F5 deletion of 1823 bp extending from intron 8 to intron 10. Bioinformatics sequence analysis pinpointed repetitive elements that might have originated the deletion. In conclusion, we have developed and validated an MLPA assay for the detection of gross F5 gene rearrangements. This assay may represent a valuable tool for the molecular diagnosis of FV deficiency. © 2014 John Wiley & Sons Ltd.

Digital Microfluidic Dynamic Culture of Mammalian Embryos on an Electrowetting on Dielectric (EWOD) Chip

PubMed Central

Huang, Hong-Yuan; Shen, Hsien-Hua; Tien, Chang-Hung; Li, Chin-Jung; Fan, Shih-Kang; Liu, Cheng-Hsien; Hsu, Wen-Syang; Yao, Da-Jeng

2015-01-01

Current human fertilization in vitro (IVF) bypasses the female oviduct and manually inseminates, fertilizes and cultivates embryos in a static microdrop containing appropriate chemical compounds. A microfluidic microchannel system for IVF is considered to provide an improved in-vivo-mimicking environment to enhance the development in a culture system for an embryo before implantation. We demonstrate a novel digitalized microfluidic device powered with electrowetting on a dielectric (EWOD) to culture an embryo in vitro in a single droplet in a microfluidic environment to mimic the environment in vivo for development of the embryo and to culture the embryos with good development and live births. Our results show that the dynamic culture powered with EWOD can manipulate a single droplet containing one mouse embryo and culture to the blastocyst stage. The rate of embryo cleavage to a hatching blastocyst with a dynamic culture is significantly greater than that with a traditional static culture (p<0.05). The EWOD chip enhances the culture of mouse embryos in a dynamic environment. To test the reproductive outcome of the embryos collected from an EWOD chip as a culture system, we transferred embryos to pseudo-pregnant female mice and produced live births. These results demonstrate that an EWOD-based microfluidic device is capable of culturing mammalian embryos in a microfluidic biological manner, presaging future clinical application. PMID:25933003

Digital Microfluidic Dynamic Culture of Mammalian Embryos on an Electrowetting on Dielectric (EWOD) Chip.

PubMed

Huang, Hong-Yuan; Shen, Hsien-Hua; Tien, Chang-Hung; Li, Chin-Jung; Fan, Shih-Kang; Liu, Cheng-Hsien; Hsu, Wen-Syang; Yao, Da-Jeng

2015-01-01

Current human fertilization in vitro (IVF) bypasses the female oviduct and manually inseminates, fertilizes and cultivates embryos in a static microdrop containing appropriate chemical compounds. A microfluidic microchannel system for IVF is considered to provide an improved in-vivo-mimicking environment to enhance the development in a culture system for an embryo before implantation. We demonstrate a novel digitalized microfluidic device powered with electrowetting on a dielectric (EWOD) to culture an embryo in vitro in a single droplet in a microfluidic environment to mimic the environment in vivo for development of the embryo and to culture the embryos with good development and live births. Our results show that the dynamic culture powered with EWOD can manipulate a single droplet containing one mouse embryo and culture to the blastocyst stage. The rate of embryo cleavage to a hatching blastocyst with a dynamic culture is significantly greater than that with a traditional static culture (p<0.05). The EWOD chip enhances the culture of mouse embryos in a dynamic environment. To test the reproductive outcome of the embryos collected from an EWOD chip as a culture system, we transferred embryos to pseudo-pregnant female mice and produced live births. These results demonstrate that an EWOD-based microfluidic device is capable of culturing mammalian embryos in a microfluidic biological manner, presaging future clinical application.

Technology for On-Chip Qubit Control with Microfabricated Surface Ion Traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Highstrete, Clark; Scott, Sean Michael; Nordquist, Christopher D.

2013-11-01

Trapped atomic ions are a leading physical system for quantum information processing. However, scalability and operational fidelity remain limiting technical issues often associated with optical qubit control. One promising approach is to develop on-chip microwave electronic control of ion qubits based on the atomic hyperfine interaction. This project developed expertise and capabilities at Sandia toward on-chip electronic qubit control in a scalable architecture. The project developed a foundation of laboratory capabilities, including trapping the 171Yb + hyperfine ion qubit and developing an experimental microwave coherent control capability. Additionally, the project investigated the integration of microwave device elements with surface ionmore » traps utilizing Sandia’s state-of-the-art MEMS microfabrication processing. This effort culminated in a device design for a multi-purpose ion trap experimental platform for investigating on-chip microwave qubit control, laying the groundwork for further funded R&D to develop on-chip microwave qubit control in an architecture that is suitable to engineering development.« less

Satellite analog FDMA/FM to digital TDMA conversion

NASA Technical Reports Server (NTRS)

Driggers, T.; Nguyen, T.; Kolavennu, V.

1987-01-01

The results of a study which investigated design issues regarding the use of analog to digital (A/D) conversion on board a satellite are presented. The need for A/D, and of course D/A as well, conversion arose from a satellite design which required analog FDMA/FM up and down links to/from a digitally modulated intersatellite link. There are also some advantages when one must interconnect a large number of various spot beams which are using analog, and therefore cannot take advantage of SS/TDMA switching among the beams, thus resulting in low fill factors. Various tradeoffs were performed regarding the implementation of on-board A/D processing, including mass, power, and costs. The various technologies which were considered included flash ADCs, surface acoustic wave (SAW) devices, and digital signal processing (DSP) chips. Impact analyses were also performed to determine the effect on ground stations to convert to digital if the A/D approach were not implemented.

A 1024×768-12μm Digital ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim

2017-02-01

This paper reports the development of a new digital microbolometer Readout Integrated Circuit (D-ROIC), called MT10212BD. It has a format of 1024 × 768 (XGA) and a pixel pitch of 12μm. MT10212BD is Mikro Tasarim's second 12μm pitch microbolometer ROIC, which is developed specifically for surface micro machined microbolometer detector arrays with small pixel pitch using high-TCR pixel materials, such as VOx and a Si. MT10212BD has an alldigital system on-chip architecture, which generates programmable timing and biasing, and performs 14-bit analog to digital conversion (ADC). The signal processing chain in the ROIC is composed of pixel bias circuitry, integrator based programmable gain amplifier followed by column parallel ADC circuitry. MT10212BD has a serial programming interface that can be used to configure the programmable ROIC features and to load the Non-Uniformity-Correction (NUC) date to the ROIC. MT10212BD has a total of 8 high-speed serial digital video outputs, which can be programmed to operate in the 2, 4, and 8-output modes and can support frames rates above 60 fps. The high-speed serial digital outputs supports data rates as high as 400 Mega-bits/s, when operated at 50 MHz system clock frequency. There is an on-chip phase-locked-loop (PLL) based timing circuitry to generate the high speed clocks used in the ROIC. The ROIC is designed to support pixel resistance values ranging from 30KΩ to 90kΩ, with a nominal value of 60KΩ. The ROIC has a globally programmable gain in the column readout, which can be adjusted based on the detector resistance value.

The Future of Hearing Aid Technology

PubMed Central

Edwards, Brent

2007-01-01

Hearing aids have advanced significantly over the past decade, primarily due to the maturing of digital technology. The next decade should see an even greater number of innovations to hearing aid technology, and this article attempts to predict in which areas the new developments will occur. Both incremental and radical innovations in digital hearing aids will be driven by research advances in the following fields: (1) wireless technology, (2) digital chip technology, (3) hearing science, and (4) cognitive science. The opportunities and limitations for each of these areas will be discussed. Additionally, emerging trends such as connectivity and individualization will also drive new technology, and these are discussed within the context of the areas given here. PMID:17301336

Integrated imaging sensor systems with CMOS active pixel sensor technology

NASA Technical Reports Server (NTRS)

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Narrowband Interference Suppression in Spread Spectrum Communication Systems

DTIC Science & Technology

1995-12-01

receiver input. As stated earlier, these waveforms must be sampled to obtain the discrete time sequences. The sampling theorem states: A bandlimited...From the FFT chips, the data is passed to a Plessey PDSP16330 Pythagoras Processor. The 16330 is a high-speed digital CMOS IC that converts real and

Testing interconnected VLSI circuits in the Big Viterbi Decoder

NASA Technical Reports Server (NTRS)

Onyszchuk, I. M.

1991-01-01

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Additive manufacturing of microfluidic glass chips

NASA Astrophysics Data System (ADS)

Kotz, F.; Helmer, D.; Rapp, B. E.

2018-02-01

Additive manufacturing has gained great interest in the microfluidic community due to the numerous channel designs which can be tested in the early phases of a lab-on-a-chip device development. High resolution additive manufacturing like microstereolithography is largely associated with polymers. Polymers are at a disadvantage compared to other materials due to their softness and low chemical resistance. Whenever high chemical and thermal resistance combined with high optical transparency is needed, glasses become the material of choice. However, glasses are difficult to structure at the microscale requiring hazardous chemicals for etching processes. In this work we present additive manufacturing and high resolution patterning of microfluidic chips in transparent fused silica glass using stereolithography and microlithography. We print an amorphous silica nanocomposite at room temperature using benchtop stereolithography printers and a custom built microlithography system based on a digital mirror device. Using microlithography we printed structures with tens of micron resolution. The printed part is then converted to a transparent fused silica glass using thermal debinding and sintering. Printing of a microfluidic chip can be done within 30 minutes. The heat treatment can be done within two days.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

Wood chips for dust control on surface-mine haul roads

Treesearch

George P., Jr. Williams

1979-01-01

On a coal haul spur road where water sprinkling was the primary method of dust control, the duration of control was increased tenfold by covering the road surface with a layer of wood chips. The chip blanket prevented existing dust-size particles from being kicked up and swept into plumes by passing traffic, insulated the road surface against evaporation and protected...

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Droplet-based Biosensing for Lab-on-a-Chip, Open Microfluidics Platforms

PubMed Central

Dak, Piyush; Ebrahimi, Aida; Swaminathan, Vikhram; Duarte-Guevara, Carlos; Bashir, Rashid; Alam, Muhammad A.

2016-01-01

Low cost, portable sensors can transform health care by bringing easily available diagnostic devices to low and middle income population, particularly in developing countries. Sample preparation, analyte handling and labeling are primary cost concerns for traditional lab-based diagnostic systems. Lab-on-a-chip (LoC) platforms based on droplet-based microfluidics promise to integrate and automate these complex and expensive laboratory procedures onto a single chip; the cost will be further reduced if label-free biosensors could be integrated onto the LoC platforms. Here, we review some recent developments of label-free, droplet-based biosensors, compatible with “open” digital microfluidic systems. These low-cost droplet-based biosensors overcome some of the fundamental limitations of the classical sensors, enabling timely diagnosis. We identify the key challenges that must be addressed to make these sensors commercially viable and summarize a number of promising research directions. PMID:27089377

64 x 64 thresholding photodetector array for optical pattern recognition

NASA Astrophysics Data System (ADS)

Langenbacher, Harry; Chao, Tien-Hsin; Shaw, Timothy; Yu, Jeffrey W.

1993-10-01

A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Learning and optimization with cascaded VLSI neural network building-block chips

NASA Technical Reports Server (NTRS)

Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

1992-01-01

To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

Fault Tolerant Characteristics of Artificial Neural Network Electronic Hardware

NASA Technical Reports Server (NTRS)

Zee, Frank

1995-01-01

The fault tolerant characteristics of analog-VLSI artificial neural network (with 32 neurons and 532 synapses) chips are studied by exposing them to high energy electrons, high energy protons, and gamma ionizing radiations under biased and unbiased conditions. The biased chips became nonfunctional after receiving a cumulative dose of less than 20 krads, while the unbiased chips only started to show degradation with a cumulative dose of over 100 krads. As the total radiation dose increased, all the components demonstrated graceful degradation. The analog sigmoidal function of the neuron became steeper (increase in gain), current leakage from the synapses progressively shifted the sigmoidal curve, and the digital memory of the synapses and the memory addressing circuits began to gradually fail. From these radiation experiments, we can learn how to modify certain designs of the neural network electronic hardware without using radiation-hardening techniques to increase its reliability and fault tolerance.

Droplet-based Biosensing for Lab-on-a-Chip, Open Microfluidics Platforms.

PubMed

Dak, Piyush; Ebrahimi, Aida; Swaminathan, Vikhram; Duarte-Guevara, Carlos; Bashir, Rashid; Alam, Muhammad A

2016-04-14

Low cost, portable sensors can transform health care by bringing easily available diagnostic devices to low and middle income population, particularly in developing countries. Sample preparation, analyte handling and labeling are primary cost concerns for traditional lab-based diagnostic systems. Lab-on-a-chip (LoC) platforms based on droplet-based microfluidics promise to integrate and automate these complex and expensive laboratory procedures onto a single chip; the cost will be further reduced if label-free biosensors could be integrated onto the LoC platforms. Here, we review some recent developments of label-free, droplet-based biosensors, compatible with "open" digital microfluidic systems. These low-cost droplet-based biosensors overcome some of the fundamental limitations of the classical sensors, enabling timely diagnosis. We identify the key challenges that must be addressed to make these sensors commercially viable and summarize a number of promising research directions.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.

Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

NASA Astrophysics Data System (ADS)

Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

2008-10-01

This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

A switchable digital microfluidic droplet dye-laser.

PubMed

Kuehne, Alexander J C; Gather, Malte C; Eydelnant, Irwin A; Yun, Seok-Hyun; Weitz, David A; Wheeler, Aaron R

2011-11-07

Digital microfluidic devices allow the manipulation of droplets between two parallel electrodes. These electrodes can act as mirrors generating a micro-cavity, which can be exploited for a droplet dye-laser. Three representative laser-dyes with emission wavelengths spanning the whole visible spectrum are chosen to show the applicability of this concept. Sub-microlitre droplets of laser-dye solution are moved in and out of a lasing site on-chip to down-convert the UV-excitation light into blue, green and red laser-pulses. This journal is © The Royal Society of Chemistry 2011

MiniDSS: a low-power and high-precision miniaturized digital sun sensor

NASA Astrophysics Data System (ADS)

de Boer, B. M.; Durkut, M.; Laan, E.; Hakkesteegt, H.; Theuwissen, A.; Xie, N.; Leijtens, J. L.; Urquijo, E.; Bruins, P.

2017-11-01

A high-precision and low-power miniaturized digital sun sensor has been developed at TNO. The single-chip sun sensor comprises an application specific integrated circuit (ASIC) on which an active pixel sensor (APS), read-out and processing circuitry as well as communication circuitry are combined. The design was optimized for low recurrent cost. The sensor is albedo insensitive and the prototype combines an accuracy in the order of 0.03° with a mass of just 72 g and a power consumption of only 65 mW.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

Multichannel Baseband Processor for Wideband CDMA

NASA Astrophysics Data System (ADS)

Jalloul, Louay M. A.; Lin, Jim

2005-12-01

The system architecture of the cellular base station modem engine (CBME) is described. The CBME is a single-chip multichannel transceiver capable of processing and demodulating signals from multiple users simultaneously. It is optimized to process different classes of code-division multiple-access (CDMA) signals. The paper will show that through key functional system partitioning, tightly coupled small digital signal processing cores, and time-sliced reuse architecture, CBME is able to achieve a high degree of algorithmic flexibility while maintaining efficiency. The paper will also highlight the implementation and verification aspects of the CBME chip design. In this paper, wideband CDMA is used as an example to demonstrate the architecture concept.

Unraveling the CHIP:Hsp70 complex as an information processor for protein quality control.

PubMed

VanPelt, Jamie; Page, Richard C

2017-02-01

The CHIP:Hsp70 complex stands at the crossroads of the cellular protein quality control system. Hsp70 facilitates active refolding of misfolded client proteins, while CHIP directs ubiquitination of misfolded client proteins bound to Hsp70. The direct competition between CHIP and Hsp70 for the fate of misfolded proteins leads to the question: how does the CHIP:Hsp70 complex execute triage decisions that direct misfolded proteins for either refolding or degradation? The current body of literature points toward action of the CHIP:Hsp70 complex as an information processor that takes inputs in the form of client folding state, dynamics, and posttranslational modifications, then outputs either refolded or ubiquitinated client proteins. Herein we examine the CHIP:Hsp70 complex beginning with the structure and function of CHIP and Hsp70, followed by an examination of recent studies of the interactions and dynamics of the CHIP:Hsp70 complex. Copyright © 2016 Elsevier B.V. All rights reserved.

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring

PubMed Central

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-01-01

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO2 detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO2 sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO2/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations. PMID:28353680

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring.

PubMed

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-03-29

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO₂ detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO₂ sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO₂/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations.

Fabrication of polydimethylsiloxane (PDMS) nanofluidic chips with controllable channel size and spacing.

PubMed

Peng, Ran; Li, Dongqing

2016-10-07

The ability to create reproducible and inexpensive nanofluidic chips is essential to the fundamental research and applications of nanofluidics. This paper presents a novel and cost-effective method for fabricating a single nanochannel or multiple nanochannels in PDMS chips with controllable channel size and spacing. Single nanocracks or nanocrack arrays, positioned by artificial defects, are first generated on a polystyrene surface with controllable size and spacing by a solvent-induced method. Two sets of optimal working parameters are developed to replicate the nanocracks onto the polymer layers to form the nanochannel molds. The nanochannel molds are used to make the bi-layer PDMS microchannel-nanochannel chips by simple soft lithography. An alignment system is developed for bonding the nanofluidic chips under an optical microscope. Using this method, high quality PDMS nanofluidic chips with a single nanochannel or multiple nanochannels of sub-100 nm width and height and centimeter length can be obtained with high repeatability.

The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

NASA Astrophysics Data System (ADS)

Qixing, Chen; Qiyu, Luo

2013-03-01

At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n-1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current Icha; it is only 1/2n-1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is: n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized: (1) the total current is less than 200 μA (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.

Fabrication and characterization of SPR chips with the modified bovine serum albumin

NASA Astrophysics Data System (ADS)

Chen, Xing; Zhang, Lu-lu; Cui, Da-fu

2016-03-01

A facile surface plasmon resonance (SPR) chip is developed for small molecule determination and analysis. The SPR chip was prepared based on a self assembling principle, in which the modified bovine serum albumin (BSA) was directly self-assembled onto the bare gold surface. The surface morphology of the chip with the modified BSA was investigated by atomic force microscopy (AFM) and its optical properties were characterized. The surface binding capacity of the bare facile SPR chip with a uniform morphology is 8 times of that of the bare control SPR chip. Based on the experiments of immune reaction between cortisol antibody and cortisol derivative, the sensitivity of the facile SPR chip with the modified BSA is much higher than that of the control SPR chip with the un-modified BSA. The facile SPR chip has been successfully used to detect small molecules. The lowest detection limit is 5 ng/mL with a linear range of 5—100 ng/mL for cortisol analysis. The novel facile SPR chip can also be applied to detect other small molecules.

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

NASA Technical Reports Server (NTRS)

Bolcar, Matthew R.; Leisawitz, David; Maher, Steve; Rinehart, Stephen

2012-01-01

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Microvalve controlled multi-functional microfluidic chip for divisional cell co-culture.

PubMed

Li, Rui; Zhang, Xingjian; Lv, Xuefei; Geng, Lina; Li, Yongrui; Qin, Kuiwei; Deng, Yulin

2017-12-15

Pneumatic micro-valve controlled microfluidic chip provides precise fluidic control for cell manipulation. In this paper, a multi-functional microfluidic chip was designed for three separate experiments: 1. Different cell lines were dispensed and cultured; 2. Three transfected SH-SY5Y cells were introduced and treated with methyl-phenyl-pyridinium (MPP + ) as drug delivery mode; 3. Specific protection and interaction were observed among cell co-culture after nerve damage. The outcomes revealed the potential and practicability of our entire multi-functional pneumatic chip system on different cell biology applications. Copyright © 2017. Published by Elsevier Inc.

CALORIC: A readout chip for high granularity calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Royer, L.; Bonnard, J.; Manen, S.

2011-07-01

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10 pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gainmore » shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1 pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35 {mu}m CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 {mu}W thanks to the power pulsing. The total area of the channel is 1.2 mm{sup 2} with an analog memory depth of 16. (authors)« less

Digital interface of electronic transformers based on embedded system

NASA Astrophysics Data System (ADS)

Shang, Qiufeng; Qi, Yincheng

2008-10-01

Benefited from digital interface of electronic transformers, information sharing and system integration in substation can be realized. An embedded system-based digital output scheme of electronic transformers is proposed. The digital interface is designed with S3C44B0X 32bit RISC microprocessor as the hardware platform. The μCLinux operation system (OS) is transplanted on ARM7 (S3C44B0X). Applying Ethernet technology as the communication mode in the substation automation system is a new trend. The network interface chip RTL8019AS is adopted. Data transmission is realized through the in-line TCP/IP protocol of uClinux embedded OS. The application result and character analysis show that the design can meet the real-time and reliability requirements of IEC60044-7/8 electronic voltage/current instrument transformer standards.

An ultra-low-power pulse oximeter implemented with an energy-efficient transimpedance amplifier.

PubMed

Tavakoli, M; Turicchia, L; Sarpeshkar, R

2010-02-01

Pulse oximeters are ubiquitous in modern medicine to noninvasively measure the percentage of oxygenated hemoglobin in a patient's blood by comparing the transmission characteristics of red and infrared light-emitting diode light through the patient's finger with a photoreceptor. We present an analog single-chip pulse oximeter with 4.8-mW total power dissipation, which is an order of magnitude below our measurements on commercial implementations. The majority of this power reduction is due to the use of a novel logarithmic transimpedance amplifier with inherent contrast sensitivity, distributed amplification, unilateralization, and automatic loop gain control. The transimpedance amplifier, together with a photodiode current source, form a high-performance photoreceptor with characteristics similar to those found in nature, which allows LED power to be reduced. Therefore, our oximeter is well suited for portable medical applications, such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing. Furthermore, our design obviates the need for an A-to-D and digital signal processor and leads to a small single-chip solution. We outline how extensions of our work could lead to submilliwatt oximeters.

Low Power Near Field Communication Methods for RFID Applications of SIM Cards.

PubMed

Chen, Yicheng; Zheng, Zhaoxia; Gong, Mingyang; Yu, Fengqi

2017-04-14

Power consumption and communication distance have become crucial challenges for SIM card RFID (radio frequency identification) applications. The combination of long distance 2.45 GHz radio frequency (RF) technology and low power 2 kHz near distance communication is a workable scheme. In this paper, an ultra-low frequency 2 kHz near field communication (NFC) method suitable for SIM cards is proposed and verified in silicon. The low frequency transmission model based on electromagnetic induction is discussed. Different transmission modes are introduced and compared, which show that the baseband transmit mode has a better performance. The low-pass filter circuit and programmable gain amplifiers are applied for noise reduction and signal amplitude amplification. Digital-to-analog converters and comparators are used to judge the card approach and departure. A novel differential Manchester decoder is proposed to deal with the internal clock drift in range-controlled communication applications. The chip has been fully implemented in 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, with a 330 µA work current and a 45 µA idle current. The low frequency chip can be integrated into a radio frequency SIM card for near field RFID applications.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

Optimal scan strategy for mega-pixel and kilo-gray-level OLED-on-silicon microdisplay.

PubMed

Ji, Yuan; Ran, Feng; Ji, Weigui; Xu, Meihua; Chen, Zhangjing; Jiang, Yuxi; Shen, Weixin

2012-06-10

The digital pixel driving scheme makes the organic light-emitting diode (OLED) microdisplays more immune to the pixel luminance variations and simplifies the circuit architecture and design flow compared to the analog pixel driving scheme. Additionally, it is easily applied in full digital systems. However, the data bottleneck becomes a notable problem as the number of pixels and gray levels grow dramatically. This paper will discuss the digital driving ability to achieve kilogray-levels for megapixel displays. The optimal scan strategy is proposed for creating ultra high gray levels and increasing light efficiency and contrast ratio. Two correction schemes are discussed to improve the gray level linearity. A 1280×1024×3 OLED-on-silicon microdisplay, with 4096 gray levels, is designed based on the optimal scan strategy. The circuit driver is integrated in the silicon backplane chip in the 0.35 μm 3.3 V-6 V dual voltage one polysilicon layer, four metal layers (1P4M) complementary metal-oxide semiconductor (CMOS) process with custom top metal. The design aspects of the optimal scan controller are also discussed. The test results show the gray level linearity of the correction schemes for the optimal scan strategy is acceptable by the human eye.

Controlled droplet microfluidic systems for multistep chemical and biological assays.

PubMed

Kaminski, T S; Garstecki, P

2017-10-16

Droplet microfluidics is a relatively new and rapidly evolving field of science focused on studying the hydrodynamics and properties of biphasic flows at the microscale, and on the development of systems for practical applications in chemistry, biology and materials science. Microdroplets present several unique characteristics of interest to a broader research community. The main distinguishing features include (i) large numbers of isolated compartments of tiny volumes that are ideal for single cell or single molecule assays, (ii) rapid mixing and negligible thermal inertia that all provide excellent control over reaction conditions, and (iii) the presence of two immiscible liquids and the interface between them that enables new or exotic processes (the synthesis of new functional materials and structures that are otherwise difficult to obtain, studies of the functions and properties of lipid and polymer membranes and execution of reactions at liquid-liquid interfaces). The most frequent application of droplet microfluidics relies on the generation of large numbers of compartments either for ultrahigh throughput screens or for the synthesis of functional materials composed of millions of droplets or particles. Droplet microfluidics has already evolved into a complex field. In this review we focus on 'controlled droplet microfluidics' - a portfolio of techniques that provide convenient platforms for multistep complex reaction protocols and that take advantage of automated and passive methods of fluid handling on a chip. 'Controlled droplet microfluidics' can be regarded as a group of methods capable of addressing and manipulating droplets in series. The functionality and complexity of controlled droplet microfluidic systems can be positioned between digital microfluidics (DMF) addressing each droplet individually using 2D arrays of electrodes and ultrahigh throughput droplet microfluidics focused on the generation of hundreds of thousands or even millions of picoliter droplets that cannot be individually addressed by their location on a chip.

Microfluidic "Pouch" Chips for Immunoassays and Nucleic Acid Amplification Tests.

PubMed

Mauk, Michael G; Liu, Changchun; Qiu, Xianbo; Chen, Dafeng; Song, Jinzhao; Bau, Haim H

2017-01-01

Microfluidic cassettes ("chips") for processing and analysis of clinical specimens and other sample types facilitate point-of-care (POC) immunoassays and nucleic acid based amplification tests. These single-use test chips can be self-contained and made amenable to autonomous operation-reducing or eliminating supporting instrumentation-by incorporating laminated, pliable "pouch" and membrane structures for fluid storage, pumping, mixing, and flow control. Materials and methods for integrating flexible pouch compartments and diaphragm valves into hard plastic (e.g., acrylic and polycarbonate) microfluidic "chips" for reagent storage, fluid actuation, and flow control are described. We review several versions of these pouch chips for immunoassay and nucleic acid amplification tests, and describe related fabrication techniques. These protocols thus offer a "toolbox" of methods for storage, pumping, and flow control functions in microfluidic devices.

Speech coding at 4800 bps for mobile satellite communications

NASA Technical Reports Server (NTRS)

Gersho, Allen; Chan, Wai-Yip; Davidson, Grant; Chen, Juin-Hwey; Yong, Mei

1988-01-01

A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Hardware platforms for MEMS gyroscope tuning based on evolutionary computation using open-loop and closed -loop frequency response

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Ferguson, Michael I.; Fink, Wolfgang; Oks, Boris; Peay, Chris; Terrile, Richard; Cheng, Yen; Kim, Dennis; MacDonald, Eric; Foor, David

2005-01-01

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development of a hardware platform for integrated tuning and closed loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Scalable hybrid computation with spikes.

PubMed

Sarpeshkar, Rahul; O'Halloran, Micah

2002-09-01

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.

Digital Detection of Multiple Minority Mutants and Expression Levels of Multiple Colorectal Cancer-Related Genes Using Digital-PCR Coupled with Bead-Array

PubMed Central

Huang, Huan; Li, Shuo; Sun, Lizhou; Zhou, Guohua

2015-01-01

To simultaneously analyze mutations and expression levels of multiple genes on one detection platform, we proposed a method termed “multiplex ligation-dependent probe amplification–digital amplification coupled with hydrogel bead-array” (MLPA–DABA) and applied it to diagnose colorectal cancer (CRC). CRC cells and tissues were sampled to extract nucleic acid, perform MLPA with sequence-tagged probes, perform digital emulsion polymerase chain reaction (PCR), and produce a hydrogel bead-array to immobilize beads and form a single bead layer on the array. After hybridization with fluorescent probes, the number of colored beads, which reflects the abundance of expressed genes and the mutation rate, was counted for diagnosis. Only red or green beads occurred on the chips in the mixed samples, indicating the success of single-molecule PCR. When a one-source sample was analyzed using mixed MLPA probes, beads of only one color occurred, suggesting the high specificity of the method in analyzing CRC mutation and gene expression. In gene expression analysis of a CRC tissue from one CRC patient, the mutant percentage was 3.1%, and the expression levels of CRC-related genes were much higher than those of normal tissue. The highly sensitive MLPA–DABA succeeds in the relative quantification of mutations and gene expressions of exfoliated cells in stool samples of CRC patients on the same chip platform. MLPA–DABA coupled with hydrogel bead-array is a promising method in the non-invasive diagnosis of CRC. PMID:25880764

Advanced Microcomputer Service Technician. Teacher Edition.

ERIC Educational Resources Information Center

Brown, A. O., III; Fulkerson, Dan, Ed.

This manual is the second of a three-text microcomputer service and repair series. This text addresses the training needs of "chip level" technicians who work with digital troubleshooting instruments to solve the complex microcomputer problems that are sent to them from computer stores that do not have full-service facilities. The manual contains…

22 CFR 51.1 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-04-01

... photograph, a unique chip number, and a digital signature to protect the integrity of the stored information... territories and possessions. (k) U.S. citizen means a person who acquired U.S. citizenship at birth or upon naturalization as provided by law and who has not subsequently lost such citizenship. (l) U.S. national means a U...

76 FR 46313 - Notice of Issuance of Final Determination Concerning Iridium Satellite Telephones

Federal Register 2010, 2011, 2012, 2013, 2014

2011-08-02

... modulates them into radio streams that communicate with the Iridium gateway network infrastructure using a... (DSP) cores, made in China, and two radio frequency (RF) backend chips, made in Taiwan. The bill of... marking of a cellular phone. CBP found that a digital mobile telephone was substantially transformed in...

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

Standard Transistor Array (STAR). Volume 1: Placement technique

NASA Technical Reports Server (NTRS)

Cox, G. W.; Caroll, B. D.

1979-01-01

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.

Attractive design: an elution solvent optimization platform for magnetic-bead-based fractionation using digital microfluidics and design of experiments.

PubMed

Lafrenière, Nelson M; Mudrik, Jared M; Ng, Alphonsus H C; Seale, Brendon; Spooner, Neil; Wheeler, Aaron R

2015-04-07

There is great interest in the development of integrated tools allowing for miniaturized sample processing, including solid phase extraction (SPE). We introduce a new format for microfluidic SPE relying on C18-functionalized magnetic beads that can be manipulated in droplets in a digital microfluidic platform. This format provides the opportunity to tune the amount (and potentially the type) of stationary phase on-the-fly, and allows the removal of beads after the extraction (to enable other operations in same device-space), maintaining device reconfigurability. Using the new method, we employed a design of experiments (DOE) operation to enable automated on-chip optimization of elution solvent composition for reversed phase SPE of a model system. Further, conditions were selected to enable on-chip fractionation of multiple analytes. Finally, the method was demonstrated to be useful for online cleanup of extracts from dried blood spot (DBS) samples. We anticipate this combination of features will prove useful for separating a wide range of analytes, from small molecules to peptides, from complex matrices.

Toward CMOS image sensor based glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

RASDR: Benchtop Demonstration of SDR for Radio Astronomy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, Bogdan; Oxley, Paul; Fields, David

The Society of Amateur Radio Astronomers (SARA) members present the benchtop version of RASDR, a Software Defined Radio (SDR) that is optimized for Radio Astronomy. RASDR has the potential to be a common digital receiver interface useful to many SARA members. This document describes the RASDR 0.0 , which provides digitized radio data to a backend computer through a USB 2.0 interface. A primary component of RASDR is the Lime Microsystems Femtocell chip which tunes from a 0.4-4 GHz center frequency with several selectable bandwidths from 0.75 MHz to 14 MHz. A second component is a board with a Complexmore » Programmable Logic Device (CPLD) chip that connects to the Femtocell and provides two USB connections to the backend computer. A third component is an analog balanced mixer up conversion section. Together these three components enable RASDR to tune from 0.015 MHz thru 3.8GHz of the radio frequency (RF) spectrum. We will demonstrate and discuss capabilities of the breadboard system and SARA members will be able to operate the unit hands-on throughout the workshop.« less

High-Rate Digital Receiver Board

NASA Technical Reports Server (NTRS)

Ghuman, Parminder; Bialas, Thomas; Brambora, Clifford; Fisher, David

2004-01-01

A high-rate digital receiver (HRDR) implemented as a peripheral component interface (PCI) board has been developed as a prototype of compact, general-purpose, inexpensive, potentially mass-producible data-acquisition interfaces between telemetry systems and personal computers. The installation of this board in a personal computer together with an analog preprocessor enables the computer to function as a versatile, highrate telemetry-data-acquisition and demodulator system. The prototype HRDR PCI board can handle data at rates as high as 600 megabits per second, in a variety of telemetry formats, transmitted by diverse phase-modulation schemes that include binary phase-shift keying and various forms of quadrature phaseshift keying. Costing less than $25,000 (as of year 2003), the prototype HRDR PCI board supplants multiple racks of older equipment that, when new, cost over $500,000. Just as the development of standard network-interface chips has contributed to the proliferation of networked computers, it is anticipated that the development of standard chips based on the HRDR could contribute to reductions in size and cost and increases in performance of telemetry systems.

A research of a high precision multichannel data acquisition system

NASA Astrophysics Data System (ADS)

Zhong, Ling-na; Tang, Xiao-ping; Yan, Wei

2013-08-01

The output signals of the focusing system in lithography are analog. To convert the analog signals into digital ones which are more flexible and stable to process, a desirable data acquisition system is required. The resolution of data acquisition, to some extent, affects the accuracy of focusing. In this article, we first compared performance between the various kinds of analog-to-digital converters (ADC) available on the market at the moment. Combined with the specific requirements (sampling frequency, converting accuracy, numbers of channels etc) and the characteristics (polarization, amplitude range etc) of the analog signals, the model of the ADC to be used as the core chip in our hardware design was determined. On this basis, we chose other chips needed in the hardware circuit that would well match with ADC, then the overall hardware design was obtained. Validation of our data acquisition system was verified through experiments and it can be demonstrated that the system can effectively realize the high resolution conversion of the multi-channel analog signals and give the accurate focusing information in lithography.

A lab-on-chip for biothreat detection using single-molecule DNA mapping.

PubMed

Meltzer, Robert H; Krogmeier, Jeffrey R; Kwok, Lisa W; Allen, Richard; Crane, Bryan; Griffis, Joshua W; Knaian, Linda; Kojanian, Nanor; Malkin, Gene; Nahas, Michelle K; Papkov, Vyacheslav; Shaikh, Saad; Vyavahare, Kedar; Zhong, Qun; Zhou, Yi; Larson, Jonathan W; Gilmanshin, Rudolf

2011-03-07

Rapid, specific, and sensitive detection of airborne bacteria, viruses, and toxins is critical for biodefense, yet the diverse nature of the threats poses a challenge for integrated surveillance, as each class of pathogens typically requires different detection strategies. Here, we present a laboratory-on-a-chip microfluidic device (LOC-DLA) that integrates two unique assays for the detection of airborne pathogens: direct linear analysis (DLA) with unsurpassed specificity for bacterial threats and Digital DNA for toxins and viruses. The LOC-DLA device also prepares samples for analysis, incorporating upstream functions for concentrating and fractionating DNA. Both DLA and Digital DNA assays are single molecule detection technologies, therefore the assay sensitivities depend on the throughput of individual molecules. The microfluidic device and its accompanying operation protocols have been heavily optimized to maximize throughput and minimize the loss of analyzable DNA. We present here the design and operation of the LOC-DLA device, demonstrate multiplex detection of rare bacterial targets in the presence of 100-fold excess complex bacterial mixture, and demonstrate detection of picogram quantities of botulinum toxoid.

Adjunctive Effects of A Piscean Collagen-Based Controlled-Release Chlorhexidine Chip in the Treatment of Chronic Periodontitis: A Clinical and Microbiological Study

PubMed Central

John, Priya; Lazarus, Flemingson; Selvam, Arul; Prabhuji, Munivenkatappa Lakshmaiah Venkatesh

2015-01-01

Introduction PerioChip a bovine origin gelatine based CHX chip has shown beneficial effects in the management of Chronic Periodontitis. A new fish collagen based CHX chip similar to PerioChip is currently available; however this product has not been thoroughly researched. Aim The aim of the present study was to evaluate the effectiveness of a new Piscean collagen-based controlled-release chlorhexidine chip (CHX chip) as an adjunctive therapy to scaling and root planing (SRP). Settings and Design The study was conducted as a randomised, split-mouth, controlled clinical trial at Krishnadevaraya College of Dental Sciences, Bangalore, India. Materials and Methods In a split–mouth study involving 20 sites in 10 patients with chronic periodontitis, control sites received scaling and root planing and test sites received scaling and root planing (SRP) and the intrapocket CHX chip placement as an adjunct. Subgingival plaque samples were collected from both control and test sites at baseline, 11 days and 11 weeks and the anaerobic colony count were assessed. Clinical parameters that were recorded at baseline and 11 weeks were gingival index, Plaque index, Probing pocket depth (PPD), and Clinical attachment level (CAL). Plaque index was recorded additionally at 11 days. Results In the test group there was a statistically significant reduction in the total anaerobic colony count, gingival index and plaque scores from baseline as compared to control sites at all time intervals. An additional 0.8mm reduction in mean probing pocket depth was noted in the test group. Gain in Clinical attachment level was comparable in both groups. Conclusion The adjunctive use of the new collagen-based CHX chip yielded significant antimicrobial benefit accompanied by a reduction in probing depth and a clinical attachment level gain as compared to SRP alone. This suggests that it may be a useful treatment option of nonsurgical periodontal treatment of chronic periodontitis. PMID:26155567

Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

PubMed

Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

2015-05-18

This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C.

Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips

PubMed Central

Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

2015-01-01

This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of −0.7/0.6 °C from −30 °C to 70 °C after 1-point calibration at 30 °C. PMID:25993518

Controlled and tunable polymer particles' production using a single microfluidic device

NASA Astrophysics Data System (ADS)

Amoyav, Benzion; Benny, Ofra

2018-04-01

Microfluidics technology offers a new platform to control liquids under flow in small volumes. The advantage of using small-scale reactions for droplet generation along with the capacity to control the preparation parameters, making microfluidic chips an attractive technology for optimizing encapsulation formulations. However, one of the drawback in this methodology is the ability to obtain a wide range of droplet sizes, from sub-micron to microns using a single chip design. In fact, typically, droplet chips are used for micron-dimension particles, while nanoparticles' synthesis requires complex chips design (i.e., microreactors and staggered herringbone micromixer). Here, we introduce the development of a highly tunable and controlled encapsulation technique, using two polymer compositions, for generating particles ranging from microns to nano-size using the same simple single microfluidic chip design. Poly(lactic-co-glycolic acid) (PLGA 50:50) or PLGA/polyethylene glycol polymeric particles were prepared with focused-flow chip, yielding monodisperse particle batches. We show that by varying flow rate, solvent, surfactant and polymer composition, we were able to optimize particles' size and decrease polydispersity index, using simple chip designs with no further related adjustments or costs. Utilizing this platform, which offers tight tuning of particle properties, could offer an important tool for formulation development and can potentially pave the way towards a better precision nanomedicine.

A Wireless Magnetoresistive Sensing System for an Intraoral Tongue-Computer Interface

PubMed Central

Park, Hangue; Kiani, Mehdi; Lee, Hyung-Min; Kim, Jeonghee; Block, Jacob; Gosselin, Benoit; Ghovanloo, Maysam

2015-01-01

Tongue drive system (TDS) is a tongue-operated, minimally invasive, unobtrusive, and wireless assistive technology (AT) that infers users’ intentions by detecting their voluntary tongue motion and translating them into user-defined commands. Here we present the new intraoral version of the TDS (iTDS), which has been implemented in the form of a dental retainer. The iTDS system-on-a-chip (SoC) features a configurable analog front-end (AFE) that reads the magnetic field variations inside the mouth from four 3-axial magnetoresistive sensors located at four corners of the iTDS printed circuit board (PCB). A dual-band transmitter (Tx) on the same chip operates at 27 and 432 MHz in the Industrial/Scientific/Medical (ISM) band to allow users to switch in the presence of external interference. The Tx streams the digitized samples to a custom-designed TDS universal interface, built from commercial off-the-shelf (COTS) components, which delivers the iTDS data to other devices such as smartphones, personal computers (PC), and powered wheelchairs (PWC). Another key block on the iTDS SoC is the power management integrated circuit (PMIC), which provides individually regulated and duty-cycled 1.8 V supplies for sensors, AFE, Tx, and digital control blocks. The PMIC also charges a 50 mAh Li-ion battery with constant current up to 4.2 V, and recovers data and clock to update its configuration register through a 13.56 MHz inductive link. The iTDS SoC has been implemented in a 0.5-μm standard CMOS process and consumes 3.7 mW on average. PMID:23853258

An automatic analyzer of solid state nuclear track detectors using an optic RAM as image sensor

NASA Astrophysics Data System (ADS)

Staderini, Enrico Maria; Castellano, Alfredo

1986-02-01

An optic RAM is a conventional digital random access read/write dynamic memory device featuring a quartz windowed package and memory cells regularly ordered on the chip. Such a device is used as an image sensor because each cell retains data stored in it for a time depending on the intensity of the light incident on the cell itself. The authors have developed a system which uses an optic RAM to acquire and digitize images from electrochemically etched CR39 solid state nuclear track detectors (SSNTD) in the track count rate up to 5000 cm -2. On the digital image so obtained, a microprocessor, with appropriate software, performs image analysis, filtering, tracks counting and evaluation.

Digital logic optimization using selection operators

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Highly sensitive detection and mutational analysis of lung cancer circulating tumor cells using integrated combined immunomagnetic beads with a droplet digital PCR chip.

PubMed

Gao, Wanlei; Huang, Ting; Yuan, Haojun; Yang, Jun; Jin, Qinghui; Jia, Chunping; Mao, Guoxin; Zhao, Jianlong

2018-08-01

Circulating tumor cells (CTCs) have become an important biomarker for liquid biopsy to monitor tumor progression and indicate response to therapies. Many epithelial cellular adhesion molecule (EpCAM) dependent CTC isolation methods have been developed, which have a limitation for low EpCAM expressed tumor cells. In an effort to overcome these drawbacks, we developed combined immunomagnetic beads (EpCAM, Mucin1 and epidermal growth factor receptor) to sensitively isolate CTCs for immunofluorescence analysis and genetic characterization. With this combined immunomagnetic beads, 93.35% H446 cells from spiked blood sample can be recovered. We were able to detect CTCs in 127 among 143 patients included in the study (88.8%). Some CTC clusters were captured with the combined magnetic beads system. In 17 of them, CTCs after chemotherapy significantly decreased compared to that before chemotherapy (4.42 (± 3.94) vs. 12 (± 7)/mL, P = 0.002). For subsequent genetic characterization of CTCs, 2 of 6 samples, using a droplet digital PCR (ddPCR) chip, have detectable EGFR L858R mutation in the cells enriched with the combined immunomagnetic beads. In conclusion, this method integrating the combined immunomagnetic beads and the ddPCR chip for CTCs detection can be of potential application in terms of diagnosis, therapeutic evaluation and personalized medicine in lung cancer. Copyright © 2018 Elsevier B.V. All rights reserved.

A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications †

PubMed Central

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Muroyama, Masanori

2017-01-01

Robot tactile sensation can enhance human–robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as “sensor platform LSI”) as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated. PMID:29061954

A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications.

PubMed

Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Nonomura, Yutaka; Muroyama, Masanori

2017-08-28

Robot tactile sensation can enhance human-robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as "sensor platform LSI") as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated.

SiC Integrated Circuits for Power Device Drivers Able to Operate in Harsh Environments

NASA Astrophysics Data System (ADS)

Godignon, P.; Alexandru, M.; Banu, V.; Montserrat, J.; Jorda, X.; Vellvehi, M.; Schmidt, B.; Michel, P.; Millan, J.

2014-08-01

The currently developed SiC electronic devices are more robust to high temperature operation and radiation exposure damage than correspondingly rated Si ones. In order to integrate the existent SiC high power and high temperature electronics into more complex systems, a SiC integrated circuit (IC) technology capable of operation at temperatures substantially above the conventional ones is required. Therefore, this paper is a step towards the development of ICs-control electronics that have to attend the harsh environment power applications. Concretely, we present the development of SiC MESFET-based digital circuitry, able to integrate gate driver for SiC power devices. Furthermore, a planar lateral power MESFET is developed with the aim of its co-integration on the same chip with the previously mentioned SiC digital ICs technology. And finally, experimental results on SiC Schottky-gated devices irradiated with protons and electrons are presented. This development is based on the Tungsten-Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine.

PubMed

Hu, Miao; Graves, Catherine E; Li, Can; Li, Yunning; Ge, Ning; Montgomery, Eric; Davila, Noraica; Jiang, Hao; Williams, R Stanley; Yang, J Joshua; Xia, Qiangfei; Strachan, John Paul

2018-03-01

Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small-scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High-precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single-layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

The origins of informatics.

PubMed Central

Collen, M F

1994-01-01

This article summarizes the origins of informatics, which is based on the science, engineering, and technology of computer hardware, software, and communications. In just four decades, from the 1950s to the 1990s, computer technology has progressed from slow, first-generation vacuum tubes, through the invention of the transistor and its incorporation into microprocessor chips, and ultimately, to fast, fourth-generation very-large-scale-integrated silicon chips. Programming has undergone a parallel transformation, from cumbersome, first-generation, machine languages to efficient, fourth-generation application-oriented languages. Communication has evolved from simple copper wires to complex fiberoptic cables in computer-linked networks. The digital computer has profound implications for the development and practice of clinical medicine. PMID:7719803

Portable and cost-effective pixel super-resolution on-chip microscope for telemedicine applications.

PubMed

Bishara, Waheb; Sikora, Uzair; Mudanyali, Onur; Su, Ting-Wei; Yaglidere, Oguzhan; Luckhart, Shirley; Ozcan, Aydogan

2011-01-01

We report a field-portable lensless on-chip microscope with a lateral resolution of <1 μm and a large field-of-view of ~24 mm(2). This microscope is based on digital in-line holography and a pixel super-resolution algorithm to process multiple lensfree holograms and obtain a single high-resolution hologram. In its compact and cost-effective design, we utilize 23 light emitting diodes butt-coupled to 23 multi-mode optical fibers, and a simple optical filter, with no moving parts. Weighing only ~95 grams, we demonstrate the performance of this field-portable microscope by imaging various objects including human malaria parasites in thin blood smears.

An embedded vision system for an unmanned four-rotor helicopter

NASA Astrophysics Data System (ADS)

Lillywhite, Kirt; Lee, Dah-Jye; Tippetts, Beau; Fowers, Spencer; Dennis, Aaron; Nelson, Brent; Archibald, James

2006-10-01

In this paper an embedded vision system and control module is introduced that is capable of controlling an unmanned four-rotor helicopter and processing live video for various law enforcement, security, military, and civilian applications. The vision system is implemented on a newly designed compact FPGA board (Helios). The Helios board contains a Xilinx Virtex-4 FPGA chip and memory making it capable of implementing real time vision algorithms. A Smooth Automated Intelligent Leveling daughter board (SAIL), attached to the Helios board, collects attitude and heading information to be processed in order to control the unmanned helicopter. The SAIL board uses an electrolytic tilt sensor, compass, voltage level converters, and analog to digital converters to perform its operations. While level flight can be maintained, problems stemming from the characteristics of the tilt sensor limits maneuverability of the helicopter. The embedded vision system has proven to give very good results in its performance of a number of real-time robotic vision algorithms.

Enhancements to a Superconducting Quantum Interference Device (SQUID) Multiplexer Readout and Control System

NASA Technical Reports Server (NTRS)

Forgione, J.; Benford, D. J.; Buchanan, E. D.; Moseley, S. H.; Rebar, J.; Shafer, R. A.

2004-01-01

Far-infrared detector arrays such as the 16x32 superconducting bolometer array for the SAFIRE instrument (flying on the SOFIA airborne observatory) require systems of readout and control electronics to provide translation between a user-driven, digital PC and the cold, analog world of the cryogenic detector. In 2001, the National Institute of Standards and Technology (NIST) developed their Mark III electronics for purposes of control and readout of their 1x32 SQUID Multiplexer chips. We at NASA s Goddard Space Flight Center acquired a Mark 111 system and subsequently designed upgrades to suit our and our collaborators purposes. We developed an arbitrary, programmable multiplexing system that allows the user to cycle through rows in a SQUID array in an infinite number of combinations. We provided hooks in the Mark III system to allow readout of signals from outside the Mark 111 system, such as telescope status information. Finally, we augmented the heart of the system with a new feedback algorithm implementation, flexible diagnostic tools, and informative telemetry.

Enhancements to a superconducting quantum interference device (SQUID) multiplexer readout and control system

NASA Astrophysics Data System (ADS)

Forgione, Joshua B.; Benford, Dominic J.; Buchanan, Ernest D.; Moseley, S. H., Jr.; Rebar, Joyce; Shafer, Richard A.

2004-10-01

Far-infrared detector arrays such as the 16x32 superconducting bolometer array for the SAFIRE instrument (flying on the SOFIA airborne observatory) require systems of readout and control electronics to provide translation between a user-driven, digital PC and the cold, analog world of the cryogenic detector. In 2001, the National Institute of Standards and Technology (NIST) developed their Mark III electronics for purposes of control and readout of their 1x32 SQUID Multiplexer chips. We at NASA's Goddard Space Flight Center acquired a Mark III system and subsequently designed upgrades to suit our and our collaborators' purposes. We developed an arbitrary, programmable multiplexing system that allows the user to cycle through rows in a SQUID array in an infinite number of combinations. We provided 'hooks' in the Mark III system to allow readout of signals from outside the Mark III system, such as telescope status information. Finally, we augmented the heart of the system with a new feedback algorithm implementation, flexible diagnostic tools, and informative telemetry.

The Ubiquitin Ligase CHIP Prevents SirT6 Degradation through Noncanonical Ubiquitination

PubMed Central

Ronnebaum, Sarah M.; Wu, Yaxu; McDonough, Holly

2013-01-01

The ubiquitin ligase CHIP (carboxyl terminus of Hsp70-interacting protein) regulates protein quality control, and CHIP deletion accelerates aging and reduces the life span in mice. Here, we reveal a mechanism for CHIP's influence on longevity by demonstrating that CHIP stabilizes the sirtuin family member SirT6, a lysine deacetylase/ADP ribosylase involved in DNA repair, metabolism, and longevity. In CHIP-deficient cells, SirT6 protein half-life is substantially reduced due to increased proteasome-mediated degradation, but CHIP overexpression in these cells increases SirT6 protein expression without affecting SirT6 transcription. CHIP noncanonically ubiquitinates SirT6 at K170, which stabilizes SirT6 and prevents SirT6 canonical ubiquitination by other ubiquitin ligases. In CHIP-depleted cells, SirT6 K170 mutation increases SirT6 half-life and prevents proteasome-mediated degradation. The global decrease in SirT6 expression in the absence of CHIP is associated with decreased SirT6 promoter occupancy, which increases histone acetylation and promotes downstream gene transcription in CHIP-depleted cells. Cells lacking CHIP are hypersensitive to DNA-damaging agents, but DNA repair and cell viability are rescued by enforced expression of SirT6. The discovery of this CHIP-SirT6 interaction represents a novel protein-stabilizing mechanism and defines an intersection between protein quality control and epigenetic regulation to influence pathways that regulate the biology of aging. PMID:24043303

Clonal haemopoiesis and therapy-related myeloid malignancies in elderly patients: a proof-of-concept, case-control study.

PubMed

Gillis, Nancy K; Ball, Markus; Zhang, Qing; Ma, Zhenjun; Zhao, YuLong; Yoder, Sean J; Balasis, Maria E; Mesa, Tania E; Sallman, David A; Lancet, Jeffrey E; Komrokji, Rami S; List, Alan F; McLeod, Howard L; Alsina, Melissa; Baz, Rachid; Shain, Kenneth H; Rollison, Dana E; Padron, Eric

2017-01-01

Clonal haemopoiesis of indeterminate potential (CHIP) is an age-associated genetic event linked to increased risk of primary haematological malignancies and increased all-cause mortality, but the prevalence of CHIP in patients who develop therapy-related myeloid neoplasms is unknown. We did this study to investigate whether chemotherapy-treated patients with cancer who have CHIP are at increased risk of developing therapy-related myeloid neoplasms. We did a nested, case-control, proof-of-concept study to compare the prevalence of CHIP between patients with cancer who later developed therapy-related myeloid neoplasms (cases) and patients who did not develop these neoplasms (controls). We identified cases from our internal biorepository of 123 357 patients who consented to participate in the Total Cancer Care biobanking protocol at Moffitt Cancer Center (Tampa, FL, USA) between Jan 1, 2006, and June 1, 2016. We included all individuals who were diagnosed with a primary malignancy, were treated with chemotherapy, subsequently developed a therapy-related myeloid neoplasm, and were 70 years or older at either diagnosis. For inclusion in this study, individuals must have had a peripheral blood or mononuclear cell sample collected before the diagnosis of therapy-related myeloid neoplasm. Controls were individuals who were diagnosed with a primary malignancy at age 70 years or older and were treated with chemotherapy but did not develop therapy-related myeloid neoplasms. Controls were matched to cases in at least a 4:1 ratio on the basis of sex, primary tumour type, age at diagnosis, smoking status, chemotherapy drug class, and duration of follow-up. We used sequential targeted and whole-exome sequencing and described clonal evolution in cases for whom paired CHIP and therapy-related myeloid neoplasm samples were available. The primary endpoint of this study was the development of therapy-related myeloid neoplasm and the primary exposure was CHIP. We identified 13 cases and 56 case-matched controls. The prevalence of CHIP in all patients (23 [33%] of 69 patients) was higher than has previously been reported in elderly individuals without cancer (about 10%). Cases had a significantly higher prevalence of CHIP than did matched controls (eight [62%] of 13 cases vs 15 [27%] of 56 controls, p=0·024; odds ratio 5·75, 95% CI 1·52-25·09, p=0·013). The most commonly mutated genes in cases with CHIP were TET2 (three [38%] of eight patients) and TP53(three [38%] of eight patients), whereas controls most often had TET2 mutations (six [40%] of 15 patients). In most (four [67%] of six patients) cases for whom paired CHIP and therapy-related myeloid neoplasm samples were available, the mean allele frequency of CHIP mutations had expanded by the time of the therapy-related myeloid neoplasm diagnosis. However, a subset of paired samples (two [33%] of six patients) had CHIP mutations that decreased in allele frequency, giving way to expansion of a distinct mutant clone. Patients with cancer who have CHIP are at increased risk of developing therapy-related myeloid neoplasms. The distribution of CHIP-related gene mutations differs between individuals with therapy-related myeloid neoplasm and those without, suggesting that mutation-specific differences might exist in therapy-related myeloid neoplasm risk. Moffitt Cancer Center. Copyright © 2017 Elsevier Ltd. All rights reserved.

Massively parallel information processing systems for space applications

NASA Technical Reports Server (NTRS)

Schaefer, D. H.

1979-01-01

NASA is developing massively parallel systems for ultra high speed processing of digital image data collected by satellite borne instrumentation. Such systems contain thousands of processing elements. Work is underway on the design and fabrication of the 'Massively Parallel Processor', a ground computer containing 16,384 processing elements arranged in a 128 x 128 array. This computer uses existing technology. Advanced work includes the development of semiconductor chips containing thousands of feedthrough paths. Massively parallel image analog to digital conversion technology is also being developed. The goal is to provide compact computers suitable for real-time onboard processing of images.

Microcontroller interface for diode array spectrometry

NASA Astrophysics Data System (ADS)

Aguo, L.; Williams, R. R.

An alternative to bus-based computer interfacing is presented using diode array spectrometry as a typical application. The new interface consists of an embedded single-chip microcomputer, known as a microcontroller, which provides all necessary digital I/O and analog-to-digital conversion (ADC) along with an unprecedented amount of intelligence. Communication with a host computer system is accomplished by a standard serial interface so this type of interfacing is applicable to a wide range of personal and minicomputers and can be easily networked. Data are acquired asynchronousty and sent to the host on command. New operating modes which have no traditional counterparts are presented.

Waveform digitization for high resolution timing detectors with silicon photomultipliers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ronzhin, A.; Albrow, M. G.; Los, S.

2012-03-01

The results of time resolution studies with silicon photomultipliers (SiPMs) read out with high bandwidth constant fraction discrimination electronics were presented earlier [1-3]. Here we describe the application of fast waveform digitization readout based on the DRS4 chip [4], a switched capacitor array (SCA) produced by the Paul Scherrer Institute, to further our goal of developing high time resolution detectors based on SiPMs. The influence of the SiPM signal shape on the time resolution was investigated. Different algorithms to obtain the best time resolution are described, and test beam results are presented.

Analytical study of a microfludic DNA amplification chip using water cooling effect.

PubMed

Chen, Jyh Jian; Shen, Chia Ming; Ko, Yu Wei

2013-04-01

A novel continuous-flow polymerase chain reaction (PCR) chip has been analyzed in our work. Two temperature zones are controlled by two external controllers and the other temperature zone at the chip center is controlled by the flow rate of the fluid inside a channel under the glass chip. By employing a water cooling channel at the chip center, the sequence of denaturation, annealing, and extension can be created due to the forced convection effect. The required annealing temperature of PCR less than 313 K can also be demonstrated in this chip. The Poly(methyl methacrylate) (PMMA) cooling channel with the thin aluminum cover is utilized to enhance the temperature uniformity. The size of this chip is 76 mm × 26 mm × 3 mm. This device represents the first demonstration of water cooling thermocycling within continuous-flow PCR microfluidics. The commercial software CFD-ACE+(TM) is utilized to determine the distances between the heating assemblies within the chip. We investigate the influences of various chip materials, operational parameters of the cooling channel and geometric parameters of the chip on the temperature uniformity on the chip surface. Concerning the temperature uniformity of the working zones and the lowest temperature at the annealing zone, the air gap spacing of 1 mm and the cooling channel thicknesses of 1 mm of the PMMA channel with an aluminum cover are recommended in our design. The hydrophobic surface of the PDMS channel was modified by filling it with 20 % Tween 20 solution and then adding bovine serum albumin (BSA) solution to the PCR mixture. DNA fragments with different lengths (372 bp and 478 bp) are successfully amplified with the device.

Microfluidic proportional flow controller

PubMed Central

Prentice-Mott, Harrison; Toner, Mehmet; Irimia, Daniel

2011-01-01

Precise flow control in microfluidic chips is important for many biochemical assays and experiments at microscale. While several technologies for controlling fluid flow have been implemented either on- or off-chip, these can provide either high-speed or high-precision control, but seldom could accomplish both at the same time. Here we describe a new on-chip, pneumatically activated flow controller that allows for fast and precise control of the flow rate through a microfluidic channel. Experimental results show that the new proportional flow controllers exhibited a response time of approximately 250 ms, while our numerical simulations suggest that faster actuation down to approximately 50 ms could be achieved with alternative actuation schemes. PMID:21874096

Three-color crystal digital PCR.

PubMed

Madic, J; Zocevic, A; Senlis, V; Fradet, E; Andre, B; Muller, S; Dangla, R; Droniou, M E

2016-12-01

Digital PCR is an exciting new field for molecular analysis, allowing unprecedented precision in the quantification of nucleic acids, as well as the fine discrimination of rare molecular events in complex samples. We here present a novel technology for digital PCR, Crystal Digital PCR™, which relies on the use of a single chip to partition samples into 2D droplet arrays, which are then subjected to thermal cycling and finally read using a three-color fluorescence scanning device. This novel technology thus allows three-color multiplexing, which entails a different approach to data analysis. In the present publication, we present this innovative workflow, which is both fast and user-friendly, and discuss associated data analysis issue, such as fluorescence spillover compensation and data representation. Lastly, we also present proof-of-concept of this three-color detection system, using a quadriplex assay for the detection of EGFR mutations L858R, L861Q and T790M.

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

NASA Technical Reports Server (NTRS)

Ruiz, B. Ian; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

Signal-chip microcomputer control system for a diffraction grating ruling engine

NASA Astrophysics Data System (ADS)

Wang, Xiaolin; Zhang, Yuhua; Yang, Houmin; Guo, Du

1998-08-01

A control system with a chip of 8031 single-chip microcomputer as its nucleus for a diffraction grating ruling engine has been developed, its hardware and software are presented in this paper. A series of techniques such as program-controlled amplifier and interference fringes subdivision as well as motor velocity step governing are adopted to improve the control accuracy. With this control system, 8 kinds of gratings of different spacings can be ruled, the positioning precision of the diffraction grating ruling engine (sigma) equals 3.6 nm, and the maximum positioning error is less than 14.6 nm.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

NASA Astrophysics Data System (ADS)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Next Generation Instrumentation Bus Test Plan for Fibre Channel

DTIC Science & Technology

1999-09-30

sample for port testing. The heart of the Fibre Xpress network cards is the tachyon chip from Hewlett Packard. The tachyon chip is basically a single...be to test the protocols. 1.5.1.1 Tachyon chip The user’s manual for the Tachyon controller chip identifies the following FC-AL specification

An 11-bit and 39 ps resolution time-to-digital converter for ADPLL in digital television

NASA Astrophysics Data System (ADS)

Liu, Wei; (Ruth) Li, Wei; Ren, P.; Lin, C. L.; Zhang, Shengdong; Wang, Yangyuan

2010-04-01

We propose and demonstrate an 11-bit time-to-digital converter (TDC) for all-digital phase-locked loops (ADPLLs) in digital television. The proposed TDC converts the width of the input pulse into digital output with the tap space of the outputs of a free-running ring oscillator (FRO) being the conversion resolution. The FRO is in a structure of coiled cell array and the TDC core is symmetrical in the input structure. This leads to equally spaced taps in the reference clocks and thereby a high TDC conversion linearity. The TDC is fabricated in 0.13 μm CMOS process and the chip area is 0.025 mm2. The measurement results show that the TDC has a conversion resolution of 39 ps at 1.2 V power supply and a 4.5 ns dead time in the 11-bits output case. Both the differential non-linearity (DNL) and integral non-linearity (INL) are below 0.5 LSB. The power consumption of the whole circuit is 4.2 mW.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fahim, Farah; Deptuch, Grzegorz; Shenai, Alpana

The Vertically Integrated Photon Imaging Chip - Large, (VIPIC-L), is a large area, small pixel (65μm), 3D integrated, photon counting ASIC with zero-suppressed or full frame dead-time-less data readout. It features data throughput of 14.4 Gbps per chip with a full frame readout speed of 56kframes/s in the imaging mode. VIPIC-L contain 192 x 192 pixel array and the total size of the chip is 1.248cm x 1.248cm with only a 5μm periphery. It contains about 120M transistors. A 1.3M pixel camera module will be developed by arranging a 6 x 6 array of 3D VIPIC-L’s bonded to a largemore » area silicon sensor on the analog side and to a readout board on the digital side. The readout board hosts a bank of FPGA’s, one per VIPIC-L to allow processing of up to 0.7 Tbps of raw data produced by the camera.« less

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

NASA Astrophysics Data System (ADS)

Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

2017-03-01

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

A UHF RFID system with on-chip-antenna tag for short range communication

NASA Astrophysics Data System (ADS)

Qi, Peng; Chun, Zhang; Xijin, Zhao; Zhihua, Wang

2015-05-01

A UHF RF identification system based on the 0.18 μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole tag chip with the antenna takes up an area of 0.36 mm2, which is smaller than other reported tags with an on-chip antenna (OCA) using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption, and minimize the size of the tag. The specialized SOC reader system consists of the RF transceiver, digital baseband, MCU and host interface. Its power consumption is about 500 mW. Measurement results show that the system's reading range is 2 mm with 20 dBm reader output power. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters, depending on the shape and size of the inductive antenna.

Micromagnetic Architectures for On-chip Microparticle Transport

NASA Astrophysics Data System (ADS)

Ouk, Minae; Beach, Geoffrey S. D.

2015-03-01

Superparamagnetic microbeads (SBs) are widely used to capture and manipulate biological entities in a fluid environment. Chip-based magnetic actuation provides a means to transport SBs in lab-on-a-chip devices. This is usually accomplished using the stray field from patterned magnetic microstructures, or domain walls in magnetic nanowires. Magnetic anti-dot arrays are particularly attractive due to the high-gradient stray fields from their partial domain wall structures. Here we use a self-assembly method to create magnetic anti-dot arrays in Co films, and describe the motion of SBs across the surface by a rotating field. We find a critical field-rotation frequency beyond which bead motion ceases and a critical threshold for both the in-plane and out-of-plane field components that must be exceeded for bead motion to occur. We show that these field thresholds are bead size dependent, and can thus be used to digitally separate magnetic beads in multi-bead populations. Hence these large-area structures can be used to combine long distance transport with novel functionalities.

Control and measurement of the phase behavior of aqueous solutions using microfluidics

PubMed Central

Shim, Jung-uk; Cristobal, Galder; Link, Darren R.; Thorsen, Todd; Jia, Yanwei; Piattelli, Katie; Fraden, Seth

2008-01-01

A microfluidic device denoted the Phase Chip has been designed to measure and manipulate the phase diagram of multi-component fluid mixtures. The Phase Chip exploits the permeation of water through poly(dimethylsiloxane) (PDMS) in order to controllably vary the concentration of solutes in aqueous nanoliter volume microdrops stored in wells. The permeation of water in the Phase Chip is modeled using the diffusion equation and good agreement between experiment and theory is obtained. The Phase Chip operates by first creating drops of the water/solute mixture whose composition varies sequentially. Next, drops are transported down channels and guided into storage wells using surface tension forces. Finally, the solute concentration of each stored drop is simultaneously varied and measured. Two applications of the Phase Chip are presented. First, the phase diagram of a polymer/salt mixture is measured on-chip and validated off-chip and second, protein crystallization rates are enhanced through the manipulation of the kinetics of nucleation and growth. PMID:17580868

Ube2w and ataxin-3 coordinately regulate the ubiquitin ligase CHIP

PubMed Central

Scaglione, K. Matthew; Zavodszky, Eszter; Todi, Sokol V.; Patury, Srikanth; Xu, Ping; Rodríguez-Lebrón, Edgardo; Fischer, Svetlana; Konen, John; Djarmati, Ana; Peng, Junmin; Gestwicki, Jason E.; Paulson, Henry L.

2011-01-01

Summary The mechanisms by which ubiquitin ligases are regulated remain poorly understood. Here we describe a series of molecular events that coordinately regulate CHIP, a neuroprotective E3 implicated in protein quality control. Through their opposing activities, the initiator E2, Ube2w, and the specialized deubiquitinating enzyme (DUB), ataxin-3, participate in initiating, regulating and terminating the CHIP ubiquitination cycle. Monoubiquitination of CHIP by Ube2w stabilizes the interaction between CHIP and ataxin-3, which through its DUB activity limits the length of chains attached to CHIP substrates. Upon completion of substrate ubiquitination ataxin-3 deubiquitinates CHIP, effectively terminating the reaction. Our results suggest that functional pairing of E3s with ataxin-3 or similar DUBs represents an important point of regulation in ubiquitin-dependent protein quality control. In addition, the results shed light on disease pathogenesis in SCA3, a neurodegenerative disorder caused by polyglutamine expansion in ataxin-3. PMID:21855799

Breast Biopsy System

NASA Technical Reports Server (NTRS)

1994-01-01

Charge Coupled Devices (CCDs) are high technology silicon chips that connect light directly into electronic or digital images, which can be manipulated or enhanced by computers. When Goddard Space Flight Center (GSFC) scientists realized that existing CCD technology could not meet scientific requirements for the Hubble Space Telescope Imagining Spectrograph, GSFC contracted with Scientific Imaging Technologies, Inc. (SITe) to develop an advanced CCD. SITe then applied many of the NASA-driven enhancements to the manufacture of CCDs for digital mammography. The resulting device images breast tissue more clearly and efficiently. The LORAD Stereo Guide Breast Biopsy system incorporates SITe's CCD as part of a digital camera system that is replacing surgical biopsy in many cases. Known as stereotactic needle biopsy, it is performed under local anesthesia with a needle and saves women time, pain, scarring, radiation exposure and money.

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

NASA Astrophysics Data System (ADS)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

High-speed photonically assisted analog-to-digital conversion using a continuous wave multiwavelength source and phase modulation.

PubMed

Bortnik, Bartosz J; Fetterman, Harold R

2008-10-01

A more simple photonically assisted analog-to-digital conversion system utilizing a cw multiwavelength source and phase modulation instead of a mode-locked laser is presented. The output of the cw multiwavelength source is launched into a dispersive device (such as a single-mode fiber). This fiber creates a pulse train, where the central wavelength of each pulse corresponds to a spectral line of the optical source. The pulses can then be either dispersed again to perform discrete wavelength time stretching or demultiplexed for continuous time analog-to-digital conversion. We experimentally demonstrate the operation of both time stretched and interleaved systems at 38 GHz. The potential of integrating this type of system on a monolithic chip is discussed.

Reading Out Single-Molecule Digital RNA and DNA Isothermal Amplification in Nanoliter Volumes with Unmodified Camera Phones

PubMed Central

2016-01-01

Digital single-molecule technologies are expanding diagnostic capabilities, enabling the ultrasensitive quantification of targets, such as viral load in HIV and hepatitis C infections, by directly counting single molecules. Replacing fluorescent readout with a robust visual readout that can be captured by any unmodified cell phone camera will facilitate the global distribution of diagnostic tests, including in limited-resource settings where the need is greatest. This paper describes a methodology for developing a visual readout system for digital single-molecule amplification of RNA and DNA by (i) selecting colorimetric amplification-indicator dyes that are compatible with the spectral sensitivity of standard mobile phones, and (ii) identifying an optimal ratiometric image-process for a selected dye to achieve a readout that is robust to lighting conditions and camera hardware and provides unambiguous quantitative results, even for colorblind users. We also include an analysis of the limitations of this methodology, and provide a microfluidic approach that can be applied to expand dynamic range and improve reaction performance, allowing ultrasensitive, quantitative measurements at volumes as low as 5 nL. We validate this methodology using SlipChip-based digital single-molecule isothermal amplification with λDNA as a model and hepatitis C viral RNA as a clinically relevant target. The innovative combination of isothermal amplification chemistry in the presence of a judiciously chosen indicator dye and ratiometric image processing with SlipChip technology allowed the sequence-specific visual readout of single nucleic acid molecules in nanoliter volumes with an unmodified cell phone camera. When paired with devices that integrate sample preparation and nucleic acid amplification, this hardware-agnostic approach will increase the affordability and the distribution of quantitative diagnostic and environmental tests. PMID:26900709

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

PubMed

Um, Ji-Yong; Kim, Yoon-Jee; Cho, Seong-Eun; Chae, Min-Kyun; Kim, Byungsub; Sim, Jae-Yoon; Park, Hong-June

2015-02-01

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

Analog and digital transport of RF channels over converged 5G wireless-optical networks

NASA Astrophysics Data System (ADS)

Binh, Le Nguyen

2016-02-01

Under the exponential increase demand by the emerging 5G wireless access networking and thus data-center based Internet, novel and economical transport of RF channels to and from wireless access systems. This paper presents the transport technologies of RF channels over the analog and digital domain so as to meet the demands of the transport capacity reaching multi-Tbps, in the followings: (i) The convergence of 5G broadband wireless and optical networks and its demands on capacity delivery and network structures; (ii) Analog optical technologies for delivery of both the information and RF carriers to and from multiple-input multiple-output (MIMO) antenna sites so as to control the beam steering of MIMO antenna in the mmW at either 28.6 GHz and 56.8 GHz RF carrier and delivery of channels of aggregate capacity reaching several Tbps; (ii) Transceiver employing advanced digital modulation formats and digital signal processing (DSP) so as to provide 100G and beyond transmission rate to meet the ultra-high capacity demands with flexible spectral grids, hence pay-on-demand services. The interplay between DSP-based and analog transport techniques is examined; (iii) Transport technologies for 5G cloud access networks and associate modulation and digital processing techniques for capacity efficiency; and (iv) Finally the integrated optic technologies with novel lasers, comb generators and simultaneous dual function photonic devices for both demultiplexing/multiplexing and modulation are proposed, hence a system on chip structure can be structured. Quantum dot lasers and matrixes of micro ring resonators are integrated on the same Si-on-Silica substrate are proposed and described.

A versatile electrowetting-based digital microfluidic platform for quantitative homogeneous and heterogeneous bio-assays

NASA Astrophysics Data System (ADS)

Vergauwe, Nicolas; Witters, Daan; Ceyssens, Frederik; Vermeir, Steven; Verbruggen, Bert; Puers, Robert; Lammertyn, Jeroen

2011-05-01

Electrowetting-on-dielectric (EWOD) lab-on-a-chip systems have already proven their potential within a broad range of bio-assays. Nevertheless, research on the analytical performance of those systems is limited, yet crucial for a further breakthrough in the diagnostic field. Therefore, this paper presents the intrinsic possibilities of an EWOD lab-on-a-chip as a versatile platform for homogeneous and heterogeneous bio-assays with high analytical performance. Both droplet dispensing and splitting cause variations in droplet size, thereby directly influencing the assay's performance. The extent to which they influence the performance is assessed by a theoretical sensitivity analysis, which allows the definition of a basic framework for the reduction of droplet size variability. Taking advantage of the optimized droplet manipulations, both homogeneous and heterogeneous bio-assays are implemented in the EWOD lab-on-a-chip to demonstrate the analytical capabilities and versatility of the device. A fully on-chip enzymatic assay is realized with high analytical performance. It demonstrates the promising capabilities of an EWOD lab-on-a-chip in food-related and medical applications, such as nutritional and blood analyses. Further, a magnetic bio-assay for IgE detection using superparamagnetic nanoparticles is presented whereby the nanoparticles are used as solid carriers during the bio-assay. Crucial elements are the precise manipulation of the superparamagnetic nanoparticles with respect to dispensing and separation. Although the principle of using nano-carriers is demonstrated for protein detection, it can be easily extended to a broader range of bio-related applications like DNA sensing. In heterogeneous bio-assays the chip surface is actively involved during the execution of the bio-assay. Through immobilization of specific biological compounds like DNA, proteins and cells a reactive chip surface is realized, which enhances the bio-assay performance. To demonstrate this potential, on-chip adhesion islands are fabricated to immobilize MCF-7 human breast cancer cells. Viability studies are performed to assess the functionalization efficiency.

Memcapacitor model and its application in chaotic oscillator with memristor.

PubMed

Wang, Guangyi; Zang, Shouchi; Wang, Xiaoyuan; Yuan, Fang; Iu, Herbert Ho-Ching

2017-01-01

Memristors and memcapacitors are two new nonlinear elements with memory. In this paper, we present a Hewlett-Packard memristor model and a charge-controlled memcapacitor model and design a new chaotic oscillator based on the two models for exploring the characteristics of memristors and memcapacitors in nonlinear circuits. Furthermore, many basic dynamical behaviors of the oscillator, including equilibrium sets, Lyapunov exponent spectrums, and bifurcations with various circuit parameters, are investigated theoretically and numerically. Our analysis results show that the proposed oscillator possesses complex dynamics such as an infinite number of equilibria, coexistence oscillation, and multi-stability. Finally, a discrete model of the chaotic oscillator is given and the main statistical properties of this oscillator are verified via Digital Signal Processing chip experiments and National Institute of Standards and Technology tests.

A Report of Bethune-Cookman College NASA JOVE Projects

NASA Technical Reports Server (NTRS)

Agba, Lawrence C.; David, Sunil K.; Rao, Narsing G.; Rahmani, Munir A.

1997-01-01

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

NASA Technical Reports Server (NTRS)

Monaco, Lisa

2003-01-01

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Towards a Generic and Adaptive System-On-Chip Controller for Space Exploration Instrumentation

NASA Technical Reports Server (NTRS)

Iturbe, Xabier; Keymeulen, Didier; Yiu, Patrick; Berisford, Dan; Hand, Kevin; Carlson, Robert; Ozer, Emre

2015-01-01

This paper introduces one of the first efforts conducted at NASA’s Jet Propulsion Laboratory (JPL) to develop a generic System-on-Chip (SoC) platform to control science instruments that are proposed for future NASA missions. The SoC platform is named APEX-SoC, where APEX stands for Advanced Processor for space Exploration, and is based on a hybrid Xilinx Zynq that combines an FPGA and an ARM Cortex-A9 dual-core processor on a single chip. The Zynq implements a generic and customizable on-chip infrastructure that can be reused with a variety of instruments, and it has been coupled with a set of off-chip components that are necessary to deal with the different instruments. We have taken JPL’s Compositional InfraRed Imaging Spectrometer (CIRIS), which is proposed for NASA icy moons missions, as a use-case scenario to demonstrate that the entire data processing, control and interface of an instrument can be implemented on a single device using the on-chip infrastructure described in this paper. We show that the performance results achieved in this preliminary version of the instrumentation controller are sufficient to fulfill the science requirements demanded to the CIRIS instrument in future NASA missions, such as Europa.

Well Monitoring System For EGS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Normann, Randy; Glowka, Dave; Normann, Charles

This grant is a collection of projects designed to move aircraft high temperature electronics technology into the geothermal industry. Randy Normann is the lead. He licensed the HT83SNL00 chip from Sandia National Labs. This chip enables aircraft developed electronics for work within a geothermal well logging tool. However, additional elements are needed to achieve commercially successful logging tools. These elements are offered by a strong list of industrial partners on this grant as: Electrochemical Systems Inc. for HT Rechargeable Batteries, Frequency Management Systems for 300C digital clock, Sandia National Labs for experts in high temperature solder, Honeywell Solid-State Electronics Centermore » for reprogrammable high temperature memory. During the course of this project MagiQ Technologies for high temperature fiber optics.« less

Advanced Exploration Technologies: Micro and Nano Technologies Enabling Space Missions in the 21st Century

NASA Technical Reports Server (NTRS)

Krabach, Timothy

1998-01-01

Some of the many new and advanced exploration technologies which will enable space missions in the 21st century and specifically the Manned Mars Mission are explored in this presentation. Some of these are the system on a chip, the Computed-Tomography imaging Spectrometer, the digital camera on a chip, and other Micro Electro Mechanical Systems (MEMS) technology for space. Some of these MEMS are the silicon micromachined microgyroscope, a subliming solid micro-thruster, a micro-ion thruster, a silicon seismometer, a dewpoint microhygrometer, a micro laser doppler anemometer, and tunable diode laser (TDL) sensors. The advanced technology insertion is critical for NASA to decrease mass, volume, power and mission costs, and increase functionality, science potential and robustness.

An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

NASA Technical Reports Server (NTRS)

Deutsch, L. J.

1985-01-01

A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

Increasing security in inter-chip communication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Edwards, Nathan J.; Hamlet, Jason; Bauer, Todd

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Increasing security in inter-chip communication

DOEpatents

Edwards, Nathan J; Hamlet, Jason; Bauer, Todd; Helinski, Ryan

2014-10-28

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Multi-channel imaging cytometry with a single detector

NASA Astrophysics Data System (ADS)

Locknar, Sarah; Barton, John; Entwistle, Mark; Carver, Gary; Johnson, Robert

2018-02-01

Multi-channel microscopy and multi-channel flow cytometry generate high bit data streams. Multiple channels (both spectral and spatial) are important in diagnosing diseased tissue and identifying individual cells. Omega Optical has developed techniques for mapping multiple channels into the time domain for detection by a single high gain, high bandwidth detector. This approach is based on pulsed laser excitation and a serial array of optical fibers coated with spectral reflectors such that up to 15 wavelength bins are sequentially detected by a single-element detector within 2.5 μs. Our multichannel microscopy system uses firmware running on dedicated DSP and FPGA chips to synchronize the laser, scanning mirrors, and sampling clock. The signals are digitized by an NI board into 14 bits at 60MHz - allowing for 232 by 174 pixel fields in up to 15 channels with 10x over sampling. Our multi-channel imaging cytometry design adds channels for forward scattering and back scattering to the fluorescence spectral channels. All channels are detected within the 2.5 μs - which is compatible with fast cytometry. Going forward, we plan to digitize at 16 bits with an A-toD chip attached to a custom board. Processing these digital signals in custom firmware would allow an on-board graphics processing unit to display imaging flow cytometry data over configurable scanning line lengths. The scatter channels can be used to trigger data buffering when a cell is present in the beam. This approach enables a low cost mechanically robust imaging cytometer.

Systolic VLSI Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

1986-01-01

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.