KSC-2014-4602

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Jim Grossman

KSC-2014-4588

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Cory Huston

KSC-2014-4591

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Cory Huston

KSC-2014-4593

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Ben Smegelsky

KSC-2014-4590

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Cory Huston

KSC-2014-4601

NASA Image and Video Library

2014-11-26

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, work continues to install 24 light emitting diode LED panels in the new countdown clock at the spaceport's Press Site. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Jim Grossman

91. VIEW OF OBSOLETE AIRCONDITIONING DUCTS LOCATED IN NORTHWEST CORNER ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

91. VIEW OF OBSOLETE AIR-CONDITIONING DUCTS LOCATED IN NORTHWEST CORNER OF ROOM, ABOVE SLC-3E AUTOPILOT EQUIPMENT. DIGITAL COUNTDOWN AND HOLD CLOCKS ON WALL LEFT OF DUCTS - Vandenberg Air Force Base, Space Launch Complex 3, Launch Operations Building, Napa & Alden Roads, Lompoc, Santa Barbara County, CA

KSC-2014-4585

NASA Image and Video Library

2014-11-25

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, the first of 24 light emitting diode LED panels have arrived for installation in the new countdown clock at the spaceport's Press Site. A new modern, multimedia display soon will be installed, similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Jim Grossmann

KSC-2014-4586

NASA Image and Video Library

2014-11-25

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, assembly has begun on the first of 24 light emitting diode LED panels for installation in the new countdown clock at the spaceport's Press Site. The new modern, multimedia display will be similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Jim Grossmann

KSC-2014-4587

NASA Image and Video Library

2014-11-25

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, assembly has begun on the first of 24 light emitting diode LED panels for installation in the new countdown clock at the spaceport's Press Site. The new modern, multimedia display will be similar to the screens seen at sporting venues. The new screen will be nearly 26 feet wide by 7 feet high, a foot taller than the original clock. The historic countdown clock was designed by Kennedy engineers and built by space center technicians before Apollo 12 in 1969. NASA has requested to acquire the countdown clock from the agency’s Artifact Working Group at the agency's Headquarters for likely display at the Kennedy Space Center Visitor Complex. For more information on the countdown clock, go to http://go.nasa.gov/10Zku10. Photo credit: NASA/Jim Grossmann

Countdown Clock Ribbon Cutting

NASA Image and Video Library

2016-03-01

Kennedy Space Center Director Bob Cabana speaks at the dedication of the newest display at the entrance to the center's visitor complex. The historic countdown clock was originally set up at the space center's Press Site and was used from the launch of Apollo 12 on Nov. 14, 1969 to the final space shuttle mission, STS-135, launched on July 8, 2011. The old countdown clock was replaced in 2014 with a modern light emitting diode, or LED, display.

80. FOUR VIDEO MONITORS LOCATED ALONG THE SOUTH WALL OF ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

80. FOUR VIDEO MONITORS LOCATED ALONG THE SOUTH WALL OF SLC-3E CONTROL ROOM. (TWO VIDEOTEK MONITORS ON LEFT (EAST) ARE COLOR; OTHERS ARE BLACK AND WHITE.) DIGITAL COUNTDOWN, HOLD, AND GREENWHICH MEAN TIME CLOCKS LOCATED ABOVE MONITORS 4 AND 5. - Vandenberg Air Force Base, Space Launch Complex 3, Launch Operations Building, Napa & Alden Roads, Lompoc, Santa Barbara County, CA

73. VIEW OF LAUNCH OPERATOR AND LAUNCH ANAYLST PANELS LOCATED ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

73. VIEW OF LAUNCH OPERATOR AND LAUNCH ANAYLST PANELS LOCATED NEAR CENTER OF SOUTH WALL OF SLC-3E CONTROL ROOM. FROM LEFT TO RIGHT ON WALL IN BACKGROUND: COMMUNICATIONS HEADSET AND FOOT PEDAL IN FORGROUND. ACCIDENT REPORTING EMERGENCY NOTIFICATION SYSTEM TELEPHONE, ATLAS H FUEL COUNTER, AND DIGITAL COUNTDOWN CLOCK. - Vandenberg Air Force Base, Space Launch Complex 3, Launch Operations Building, Napa & Alden Roads, Lompoc, Santa Barbara County, CA

81. THREE ADDITIONAL BLACK AND WHITE VIDEO MONITORS LOCATED IMMEDIATELY ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

81. THREE ADDITIONAL BLACK AND WHITE VIDEO MONITORS LOCATED IMMEDIATELY WEST OF THOSE IN CA-133-1-A-80. COMPLEX SAFETY WARNING LIGHTS FOR SLC-3E (PAD 2) AND BLDG. 763 (LOB) LOCATED ABOVE MONITOR 3; GREEN LIGHTS ON BOTTOM OF EACH STACK ILLUMINATED. LEFT TO RIGHT BELOW MONITORS: ACCIDENT REPORTING EMERGENCY NOTIFICATION SYSTEM TELEPHONE, ATLAS H FUEL COUNTER, AND DIGITAL COUNTDOWN CLOCK. - Vandenberg Air Force Base, Space Launch Complex 3, Launch Operations Building, Napa & Alden Roads, Lompoc, Santa Barbara County, CA

Launch Support Video Site

NASA Technical Reports Server (NTRS)

OFarrell, Zachary L.

2013-01-01

The goal of this project is to create a website that displays video, countdown clock, and event times to customers during launches, without needing to be connected to the internal operations network. The requirements of this project are to also minimize the delay in the clock and events to be less than two seconds. The two parts of this are the webpage, which will display the data and videos to the user, and a server to send clock and event data to the webpage. The webpage is written in HTML with CSS and JavaScript. The JavaScript is responsible for connecting to the server, receiving new clock data, and updating the webpage. JavaScript is used for this because it can send custom HTTP requests from the webpage, and provides the ability to update parts of the webpage without having to refresh the entire page. The server application will act as a relay between the operations network, and the open internet. On the operations network side, the application receives multicast packets that contain countdown clock and events data. It will then parse the data into current countdown times and events, and create a packet with that information that can be sent to webpages. The other part will accept HTTP requests from the webpage, and respond to them with current data. The server is written in C# with some C++ files used to define the structure of data packets. The videos for the webpage will be shown in an embedded player from UStream.

LED instrument approach instruction display

NASA Technical Reports Server (NTRS)

Meredith, B. D.; Kelly, W. L., IV; Crouch, R. K.

1979-01-01

A display employing light emitting diodes (LED's) was developed to demonstrate the feasibility of such displays for presenting landing and navigation information to reduce the workload of general aviation pilots during IFR flight. The display consists of a paper tape reader, digital memory, control electronics, digital latches, and LED alphanumeric displays. A presentable digital countdown clock-timer is included as part of the system to provide a convenient means of monitoring time intervals for precise flight navigation. The system is a limited capability prototype assembled to test pilot reaction to such a device under simulated IFR operation. Pilot opinion indicates that the display is helpful in reducing the IFR pilots workload when used with a runway approach plate. However, the development of a compact, low power second generation display was recommended which could present several instructions simultaneously and provide information update capability. A microprocessor-based display could fulfill these requirements.

Media at the Press Site for the Orion Launch

NASA Image and Video Library

2014-12-04

At NASA's Kennedy Space Center in Florida, the new countdown clock at the spaceport's Press Site is used for the first time as preparations were underway for the Orion Flight Test. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen is nearly 26 feet wide by 7 feet high, a foot taller than the original clock.

KSC-2014-4688

NASA Image and Video Library

2014-12-04

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, the new countdown clock at the spaceport's Press Site is used for the first time as preparations were underway for the Orion Flight Test. The modern, multimedia display is similar to the screens seen at sporting venues. The new screen is nearly 26 feet wide by 7 feet high, a foot taller than the original clock. For more information, visit www.nasa.gov/orion Photo credit: NASA/Frankie Martin

KSC-92PC-578

NASA Image and Video Library

1992-03-20

STS-45 Mission Commander Charlie Bolden, Jr., is glad to be back in Florida and ready for the launch of the 46th Shuttle Mission. Bolden and six fellow crew members arrived at KSC's landing strip after the Countdown Clock had already stated ticking toward liftoff of the Space Shuttle Atlantis from Pad 39-A.

KSC-97PC1539

NASA Image and Video Library

1997-10-12

At Launch Complex 40 on Cape Canaveral Air Station, the Mobile Service Tower is rolled away from the Titan IVB/Centaur carrying the Cassini spacecraft, marking a major milestone in the launch countdown sequence. Retraction of the structure began about an hour later than scheduled due to minor problems with ground support equipment. The countdown clock for the Cassini mission began ticking earlier today at the T-26-hour mark. Other upcoming prelaunch milestones include activation of the final launch sequence for the Cassini spacecraft at the T-180-minute mark in the countdown, to be followed about an hour later by initiation of loading of the Titan IVB's Centaur stage with its complement of liquid hydrogen and liquid oxygen. Liftoff of Cassini on the journey to Saturn and its moon Titan is slated to occur during a window opening at 4:55 a.m. EDT, Oct. 13, and extending through 7:15 a.m

Titan 4B/Centaur/Cassini Service Tower Rollaway

NASA Technical Reports Server (NTRS)

1997-01-01

KENNEDY SPACE CENTER, FLA. -- At Launch Complex 40 on Cape Canaveral Air Station, the Mobile Service Tower is rolled away from the Titan IVB/Centaur carrying the Cassini spacecraft, marking a major milestone in the launch countdown sequence. Retraction of the structure began about an hour later than scheduled due to minor problems with ground support equipment. The countdown clock for the Cassini mission began ticking earlier today at the T-26-hour mark. Other upcoming prelaunch milestones include activation of the final launch sequence for the Cassini spacecraft at the T-180-minute mark in the countdown, to be followed about an hour later by initiation of loading of the Titan IVB's Centaur stage with its complement of liquid hydrogen and liquid oxygen. Liftoff of Cassini on the journey to Saturn and its moon Titan is slated to occur during a window opening at 4:55 a.m. EDT, Oct. 13, and extending through 7:15 a.m.

T-38 AT SLF DURING STS-80 CREW ARRIVAL

NASA Technical Reports Server (NTRS)

1996-01-01

A T-38 parked at KSC's Shuttle Landing Facility is profiled against the brilliant twilight sky. The five astronauts assigned to Space Shuttle Mission STS-80 arrived from Houston at around 6:30 p.m.: Mission Commander Kenneth D. Cockrell; Pilot Kent V. Rominger; and Mission Specialists Tamara E. Jernigan, Thomas D. Jones and Story Musgrave headed for the crew quarters in the Operations and Checkout Building. Tomorrow, Nov. 12, the launch countdown will begin at 1 p.m. with the countdown clock set at T- 43 hours. The Space Shuttle Columbia is scheduled for liftoff from Launch Pad 39B at 2:50 p.m. EST, Nov. 15.

Media at the Press Site for the Orion Launch

NASA Image and Video Library

2014-12-04

At NASA's Kennedy Space Center in Florida, the new countdown clock at the spaceport's Press Site is used for the first time as preparations were underway for the Orion Flight Test. News media representatives gather in anticipation of the launch of NASA's Orion spacecraft atop a United Launch Alliance Delta IV Heavy rocket.

KSC-03pd0117

NASA Image and Video Library

2003-01-16

KENNEDY SPACE CENTER, FLA. - A crowd by the countdown clock watches as Space Shuttle Columbia roars toward space on mission STS-107. Following a flawless and uneventful countdown, liftoff occurred on-time at 10:39 a.m. EST. The 16-day research mission will include FREESTAR (Fast Reaction Experiments Enabling Science, Technology, Applications and Research) and the SHI Research Double Module (SHI/RDM), known as SPACEHAB. Experiments on the module range from material sciences to life sciences. Landing is scheduled at about 8:53 a.m. EST on Saturday, Feb. 1. This mission is the first Shuttle mission of 2003. Mission STS-107 is the 28th flight of the orbiter Columbia and the 113th flight overall in NASA's Space Shuttle program.

A Clockwork War: Rhetorics of Time in a Time of Terror

ERIC Educational Resources Information Center

Stahl, Roger

2008-01-01

Expressions of time have increasingly infused the rhetorical experience of post-industrial war, especially since 9/11. This essay demonstrates how these "signs of time" operate as one of three tropes: deadline/countdown, infinite/infinitesimal war, and the ticking clock. The persistence of such signs of time in public discourse can be seen as an…

Effects of digital countdown timer on intersection safety and efficiency: A systematic review.

PubMed

Fu, Chuanyun; Zhang, Yaping; Qi, Weiwei; Cheng, Shaowu

2016-01-01

To investigate the available evidence referring to the effectiveness of digital countdown timers (DCTs) in improving the safety and operational efficiency of signalized intersection. A systematic review was performed according to the Preferred Reporting Items for Systematic Reviews and Meta-Analysis (PRISMA) statement guidelines. Relevant literature was searched from electronic databases using key terms. Based on study selection and methodological quality assessment, 14 studies were included in the review. Findings of the studies were synthesized in a narrative analysis. Three types of DCT had different effects on intersection safety and operational efficiency. Green signal countdown timers (GSCTs) reduced red light violations, type I dilemma zone distributions, and rear-end collision likelihood but increased crossing after yellow onset and had mixed impacts on type II dilemma zone distributions and intersection capacity. In contrast, red signal countdown timers (RSCTs) increased intersection capacity, although their effectiveness in reducing red light violations dissipated over time. Likewise, continuous countdown timers (CCTs) significantly enhanced intersection capacity but had mixed influences on red light violations and crossing after yellow onset. Due to the limited and inconsistent evidence regarding DCTs' effects on intersection safety and efficiency, it is not sufficient to recommend any type of DCT to be installed at signalized intersections to improve safety and operational efficiency. Nevertheless, it is apparent that both RSCTs and CCTs enhance intersection capacity, though their impacts on intersection safety are unclear. Future studies need to further verify those anticipated safe and operational benefits of DCTs with enriched field observation data.

High speed imager test station

DOEpatents

Yates, George J.; Albright, Kevin L.; Turko, Bojan T.

1995-01-01

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.

High speed imager test station

DOEpatents

Yates, G.J.; Albright, K.L.; Turko, B.T.

1995-11-14

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment. 12 figs.

A clocking discipline for two-phase digital integrated circuits

NASA Astrophysics Data System (ADS)

Noice, D. C.

1983-09-01

Sooner or later a designer of digital circuits must face the problem of timing verification so he can avoid errors caused by clock skew, critical races, and hazards. Unlike previous verification methods, such as timing simulation and timing analysis, the approach presented here guarantees correct operation despite uncertainty about delays in the circuit. The result is a clocking discipline that deals with timing abstractions only. It is not based on delay calculations; it is only concerned with the correct, synchronous operation at some clock rate. Accordingly, it may be used earlier in the design cycle, which is particularly important to integrated circuit designs. The clocking discipline consists of a notation of clocking types, and composition rules for using the types. Together, the notation and rules define a formal theory of two phase clocking. The notation defines the names and exact characteristics for different signals that are used in a two phase digital system. The notation makes it possible to develop rules for propagating the clocking types through particular circuits.

Time management displays for shuttle countdown

NASA Technical Reports Server (NTRS)

Beller, Arthur E.; Hadaller, H. Greg; Ricci, Mark J.

1992-01-01

The Intelligent Launch Decision Support System project is developing a Time Management System (TMS) for the NASA Test Director (NTD) to use for time management during Shuttle terminal countdown. TMS is being developed in three phases: an information phase; a tool phase; and an advisor phase. The information phase is an integrated display (TMID) of firing room clocks, of graphic timelines with Ground Launch Sequencer events, and of constraints. The tool phase is a what-if spreadsheet (TMWI) for devising plans for resuming from unplanned hold situations. It is tied to information in TMID, propagates constraints forward and backward to complete unspecified values, and checks the plan against constraints. The advisor phase is a situation advisor (TMSA), which proactively suggests tactics. A concept prototype for TMSA is under development. The TMID is currently undergoing field testing. Displays for TMID and TMWI are described. Descriptions include organization, rationale for organization, implementation choices and constraints, and use by NTD.

Variable frequency microprocessor clock generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Branson, C.N.

A microprocessor-based system is described comprising: a digital central microprocessor provided with a clock input and having a rate of operation determined by the frequency of a clock signal input thereto; memory means operably coupled to the central microprocessor for storing programs respectively including a plurality of instructions and addressable by the central microprocessor; peripheral device operably connected to the central microprocessor, the first peripheral device being addressable by the central microprocessor for control thereby; a system clock generator for generating a digital reference clock signal having a reference frequency rate; and frequency rate reduction circuit means connected between themore » clock generator and the clock input of the central microprocessor for selectively dividing the reference clock signal to generate a microprocessor clock signal as an input to the central microprocessor for clocking the central microprocessor.« less

Processing of visually presented clock times.

PubMed

Goolkasian, P; Park, D C

1980-11-01

The encoding and representation of visually presented clock times was investigated in three experiments utilizing a comparative judgment task. Experiment 1 explored the effects of comparing times presented in different formats (clock face, digit, or word), and Experiment 2 examined angular distance effects created by varying positions of the hands on clock faces. In Experiment 3, encoding and processing differences between clock faces and digitally presented times were directly measured. Same/different reactions to digitally presented times were faster than to times presented on a clock face, and this format effect was found to be a result of differences in processing that occurred after encoding. Angular separation also had a limited effect on processing. The findings are interpreted within the framework of theories that refer to the importance of representational codes. The applicability to the data of Bank's semantic-coding theory, Paivio's dual-coding theory, and the levels-of-processing view of memory are discussed.

STS-71 crew addresses news media

NASA Technical Reports Server (NTRS)

1995-01-01

Following their arrival at KSC's Shuttle Landing Facility, the STS-71 flight crew takes a moment to address news media gathered to greet them. The journey from Johnson Space Center in Houston brings the flight crew one step closer to an historic spaceflight, the first docking of the U.S. Space Shuttle with the Russian Space Station Mir. The countdown clock already has begun ticking toward liftoff of the Shuttle Atlantis on that flight, currently scheduled for June 23 at 5:08 p.m. EDT.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

KSC-2015-1332

NASA Image and Video Library

2015-02-11

The SpaceX Falcon 9 rocket carrying NOAA’s Deep Space Climate Observatory spacecraft, or DSCOVR, rises in the background as the countdown clock at NASA’s Kennedy Space Center in Florida reads 44 seconds into flight. The Falcon 9 launched from Space Launch Complex 40 at Cape Canaveral Air Force Station at 6:03 p.m. EST. DSCOVR is a partnership between NOAA, NASA and the U.S. Air Force, and will maintain the nation's real-time solar wind monitoring capabilities. To learn more about DSCOVR, visit http://www.nesdis.noaa.gov/DSCOVR. Photo credit: NASA/Frankie Martin

KSC-2015-1329

NASA Image and Video Library

2015-02-11

Liftoff of the SpaceX Falcon 9 rocket carrying NOAA’s Deep Space Climate Observatory spacecraft, or DSCOVR, is visible in the realtime camera view on the countdown clock at NASA’s Kennedy Space Center in Florida. The Falcon 9 launched from Space Launch Complex 40 at Cape Canaveral Air Force Station at 6:03 p.m. EST. DSCOVR is a partnership between NOAA, NASA and the U.S. Air Force, and will maintain the nation's real-time solar wind monitoring capabilities. To learn more about DSCOVR, visit http://www.nesdis.noaa.gov/DSCOVR. Photo credit: NASA/Frankie Martin

KSC-2015-1331

NASA Image and Video Library

2015-02-11

The countdown clock at NASA’s Kennedy Space Center in Florida reads 30 seconds into flight of the SpaceX Falcon 9 rocket carrying NOAA’s Deep Space Climate Observatory spacecraft, or DSCOVR, seen rising in the background. The Falcon 9 launched from Space Launch Complex 40 at Cape Canaveral Air Force Station at 6:03 p.m. EST. DSCOVR is a partnership between NOAA, NASA and the U.S. Air Force, and will maintain the nation's real-time solar wind monitoring capabilities. To learn more about DSCOVR, visit http://www.nesdis.noaa.gov/DSCOVR. Photo credit: NASA/Frankie Martin

Digital-data receiver synchronization

DOEpatents

Smith, Stephen F.; Turner, Gary W.

2005-08-02

Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.

Digital-data receiver synchronization method and apparatus

DOEpatents

Smith, Stephen F.; Turner, Gary W.

2005-12-06

Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock may be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.

Digital-data receiver synchronization method and apparatus

DOEpatents

Smith, Stephen F [Loudon, TN; Turner, Gary W [Clinton, TN

2009-09-08

Digital data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.

1992-01-01

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Architectural design proposal for real time clock for wireless microcontroller unit

NASA Astrophysics Data System (ADS)

Alias, Muhammad Nor Azwan Mohd; Nizam Mohyar, Shaiful

2017-11-01

In this project, we are developing an Intellectual properties (IP) which is a dedicated real-time clock (RTC) system for a wireless microcontroller. This IP is developed using Verilog Hardware Description Language (Verilog HDL) and being simulated using Quartus II and Synopsys software. This RTC will be used in microcontroller system to provide precise time and date which can be used for various applications. It plays a very important role in the real-time systems like digital clock, attendance system, digital camera and more.

Strategies for synchronisation in an evolving telecommunications network

NASA Astrophysics Data System (ADS)

Avery, Rob

1992-06-01

The achievement of precise synchronization in the telecommunications environment is addressed. Transmitting the timing from node to node has been the inherent problem for all digital networks. Traditional network equipment used to transfer synchronization, such as digital switching ststems, adds impairments to the once traceable signal. As the synchronization signals are passed from node to node, they lose stability by passing through intervening clocks. Timing would be an integrated part of all new network and service deployments. New transmission methods, such as the Synchronous Digital Hierarchy (SDH), survivable network topologies and the issues that arise from them, necessitate a review of current network synchronization strategies. Challenges that face the network are itemized. A demonstration of why localized Primary Reference Clocks (PRC) in key nodes and the Synchronization Supply Unit (SSU) clock architecture of transit and local node clocks is a technically and economically viable solution to the issues facing network planners today is given.

Clock distribution for BaF2 readout electronics at CSNS-WNS

NASA Astrophysics Data System (ADS)

He, Bing; Cao, Ping; Zhang, De-Liang; Wang, Qi; Zhang, Ya-Xi; Qi, Xin-Cheng; An, Qi

2017-01-01

A BaF2 (Barium Fluoride) detector array is designed to precisely measure the (n, γ) cross section at the CSNS-WNS (white neutron source at China Spallation Neutron Source). It is a 4π solid angle-shaped detector array consisting of 92 BaF2 crystal elements. To discriminate signals from the BaF2 detector, a pulse shape discrimination method is used, supported by a waveform digitization technique. There are 92 channels for digitizing. The precision and synchronization of clock distribution restricts the performance of waveform digitizing. In this paper, a clock prototype for the BaF2 readout electronics at CSNS-WNS is introduced. It is based on the PXIe platform and has a twin-stage tree topology. In the first stage, clock is synchronously distributed from the tree root to each PXIe crate through a coaxial cable over a long distance, while in the second stage, the clock is further distributed to each electronic module through a PXIe dedicated differential star bus. With the help of this topology, each tree node can fan out up to 20 clocks with 3U size. Test results show the clock jitter is less than 20 ps, which meets the requirements of the BaF2 readout electronics. Besides, this clock system has the advantages of high density, simplicity, scalability and cost saving, so it can be useful for other clock distribution applications. Supported by National Research and Development plan (2016 YFA0401602) NSAF (U1530111) and National Natural Science Foundation of China (11005107)

KSC-2015-1330

NASA Image and Video Library

2015-02-11

The SpaceX Falcon 9 rocket carrying NOAA’s Deep Space Climate Observatory spacecraft, or DSCOVR, rises above the treeline as a realtime camera view of the launch is visible on the countdown clock at NASA’s Kennedy Space Center in Florida. The Falcon 9 launched from Space Launch Complex 40 at Cape Canaveral Air Force Station at 6:03 p.m. EST. DSCOVR is a partnership between NOAA, NASA and the U.S. Air Force, and will maintain the nation's real-time solar wind monitoring capabilities. To learn more about DSCOVR, visit http://www.nesdis.noaa.gov/DSCOVR. Photo credit: NASA/Frankie Martin

STS-73 Cmdr Kenneth D. Bowersox arrives at SLF

NASA Technical Reports Server (NTRS)

1995-01-01

STS-73 Mission Commander Kenneth D. Bowersox arrives at KSC's Shuttle Landing Facility (SLF), ready to fly one spaceship into orbit as another vehicle is prepared for a different destination behind him. Bowersox and his six-member crew flew into KSC just hours after the countdown clock began ticking toward a scheduled liftoff of the Space Shuttle Columbia from Pad 39B at 9:35 a.m EDT, Sept. 28. The orbiter Discovery was towed to the SLF for a cross-country trip to the West Coast and a regularly scheduled refurbishment and checkout period.

STS-78 Payload Specialist Thirsk and Favier at SLF

NASA Technical Reports Server (NTRS)

1996-01-01

KENNEDY SPACE CENTER, FLA. -- STS-78 Payload Specialists Robert Brenton Thirsk (Canadian Space Agency) (left) and Jean-Jacques Favier (French Space Agency) are holding an Olympic torch presented to the crew after they arrived at KSC's Shuttle Landing Facility. The crew will take the torch with them on their upcoming spaceflight and then present it upon their return to a representative of the Atlanta Committee for the Olympic games (ACOG). The countdown clock began ticking earlier today toward the June 20 launch of the Space Shuttle Columbia on Mission STS- 78, the fifth Shuttle flight of 1996.

Curriculum Sequencing and the Acquisition of Clock-Reading Skills among Chinese and Flemish Children

ERIC Educational Resources Information Center

Burny, Elise; Valcke, Martin; Desoete, Annemie; Van Luit, Johannes E. Hans

2013-01-01

The present study addresses the impact of the curriculum on primary school children's acquisition of clock-reading knowledge from analog and digital clocks. Focusing on Chinese and Flemish children's clock-reading knowledge, the study is about whether the differences in sequencing of learning and instruction opportunities--as defined by the…

Clock jitter generator with picoseconds resolution

NASA Astrophysics Data System (ADS)

Jovanović, Goran; Stojčev, Mile; Nikolić, Tatjana

2013-06-01

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

A single chip 2 Gbit/s clock recovery subsystem for digital communications

NASA Astrophysics Data System (ADS)

Hickling, Ronald M.

A self-contained clock recovery/data resynchronizer phase locked loop (PLL) for use in microwave and fiber optic digital communications has been fabricated using GaAs integrated circuit technology. The IC contains the analog and digital components for the PLL: an edge-triggered phase detector based on a 1.2 GHz phase/frequency comparator, an op amp for creating the loop filter, and a VCO based on a differential source-coupled pair amplifier.

AN/TAC-1 demultiplexer circuit card assembly

NASA Astrophysics Data System (ADS)

Krueger, Paul J.

1989-01-01

This report describes the design, operation, and testing of the AN/TAC-1 demultiplexer subassembly. It demultiplexes the 6144 kb/s digital data stream received over fiber optic cable or tropo satellite support radio, and converts it into 2 digital groups and 16 digital channels. Timing recovery is accomplished by generating a 18432 kHz master clock synchronized to the incoming data. This master clock is divided modulo two to generate the proper group and loop timing.

When will we reach 1.5 of global warming?

NASA Astrophysics Data System (ADS)

Matthews, D.

2017-12-01

Recent global temperature trends indicate that we may be rapidly approaching 1.5 degrees of global warming. However, rigorous estimates of when this target will be breached are rare, and are highly sensitive to small errors in observed and model-simulated historical warming, as well as widely-varying estimates of the allowable emissions for 1.5°C. Here, I present a proposed method to estimate the time remaining to 1.5°C using a new estimate of human-attributable warming, updated CO2 emissions trends, and the latest estimates of the 1.5°C carbon budget. The resulting calculation suggests that a continuation of recent CO2 emission trends would take us past 1.5°C in 2033, a little less than 16 years from now. Uncertainties in this calculation remain large, reflecting both fundamental scientific uncertainties associated with the climate response to emissions, as well as uncertainties associated with human mitigation decisions and their effect on future CO2 and non-CO2 greenhouse gas emissions. However, it is nevertheless important to provide a robust and widely-accepted best estimate of the time remaining before we breach the climate targets that have been adopted in the Paris climate agreement, so as to clearly communicate our scientific understanding to policy makers and the general public. To this end, in an effort to visualize and track our progress towards these target, we have develop an online and projectable climate clock, which shows a real-time countdown of the time remaining to 1.5 and 2°C of global warming (see www.climateclock.net). This clock will be updated annually in light of the most recent emissions and global temperature data, and accounting for improved estimates of the remaining carbon budget associated with these climate targets. As countries around the world move forward with climate mitigation efforts, this climate clock will be able to clearly mark our progress towards the objective of adding time to the countdown so as to ultimately avoid breaching these dangerous climate thresholds.

Spacecraft with gradual acceleration of solar panels

NASA Technical Reports Server (NTRS)

Merhav, Tamir R. (Inventor); Festa, Michael T. (Inventor); Stetson, Jr., John B. (Inventor)

1996-01-01

A spacecraft (8) includes a movable appendage such as solar panels (12) operated by a stepping motor (28) driven by pulses (311). In order to reduce vibration andor attitude error, the drive pulses are generated by a clock down-counter (312) with variable count ratio. Predetermined desired clock ratios are stored in selectable memories (314a-d), and the selected ratio (R) is coupled to a comparator (330) together with the current ratio (C). An up-down counter (340) establishes the current count-down ratio by counting toward the desired ratio under the control of the comparator; thus, a step change of solar panel speed never occurs. When a direction change is commanded, a flag signal generator (350) disables the selectable memories, and enables a further store (360), which generates a count ratio representing a very slow solar panel rotational rate, so that the rotational rate always slows to a low value before direction is changed. The principles of the invention are applicable to any movable appendage.

Comparisons of mental clocks.

PubMed

Paivio, A

1978-02-01

Subjects in three experiments were presented with pairs of clock times and were required to choose the one in which the hour and minute hand formed the smaller angle. In Experiments 1 and 2, the times were presented digitally, necessitating a transformation into symbolic representations from which the angular size difference could be inferred. The results revealed orderly symbolic distance effects so that comparison reaction time increased as the angular size difference decreased. Moreover, subjects generally reported using imagery to make the judgment, and subjects scoring high on test of imagery ability were faster than those scoring low on such tests. Experiment 3 added a direct perceptual condition in which subjects compared angles between pairs of hands on two drawn (analog) clocks, as well as a mixed condition involving one digital and one analog clock time. The results showed comparable distance effects for all conditions. In addition, reaction time increased from the perceptual, to the mixed, to the pure-digital condition. These results are consistent with predictions from an image-based dual-coding theory.

Fast Clock Recovery for Digital Communications

NASA Technical Reports Server (NTRS)

Tell, R. G.

1985-01-01

Circuit extracts clock signal from random non-return-to-zero data stream, locking onto clock within one bit period at 1-gigabitper-second data rate. Circuit used for synchronization in opticalfiber communications. Derives speed from very short response time of gallium arsenide metal/semiconductor field-effect transistors (MESFET's).

A bi-directional fixed-latency clock distribution system

NASA Astrophysics Data System (ADS)

Yang, Y.; Ó Murchadha, A.; Meures, T.; Korntheuer, M.; Hanson, K.

2013-12-01

The Askar'yan Radio Array (ARA) Collaboration is constructing a giant array of radio-frequency antennas deployed in the ice near the geographic South Pole. This experiment aims at detecting the extremely weak signal of neutrinos with energies in excess of 100 PeV from ultrahigh-energy cosmic ray interactions with the cosmic microwave background radiation. The antennas are located in shallow holes drilled to depths of 200 m and need high fidelity RF signal transmission over extended lengths to the data acquisition logic at the surface. We report on a transmission scheme whereby signals are digitized in the ice and the waveforms are digitally sent via high-speed serial links. Reconstruction algorithms require distribution of a low-jitter clock from the surface down to the digitization boards in the holes with knowledge of the overall time delay between the two clock domains. Previously, we designed a clock synchronization system using electrical signaling over CAT5. This year we have updated our solution to optical fibers using high speed transceiver blocks in Spartan-6 FPGAs. This note describes our improvements on the latter solution: technical details as well as methods of maintaining a fixed phase between two clocks after power cycles and resets.

Ultralow-Power Digital Correlator for Microwave Polarimetry

NASA Technical Reports Server (NTRS)

Piepmeier, Jeffrey R.; Hass, K. Joseph

2004-01-01

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Analysis of an all-digital maximum likelihood carrier phase and clock timing synchronizer for eight phase-shift keying modulation

NASA Astrophysics Data System (ADS)

Degaudenzi, Riccardo; Vanghi, Vieri

1994-02-01

In all-digital Trellis-Coded 8PSK (TC-8PSK) demodulator well suited for VLSI implementation, including maximum likelihood estimation decision-directed (MLE-DD) carrier phase and clock timing recovery, is introduced and analyzed. By simply removing the trellis decoder the demodulator can efficiently cope with uncoded 8PSK signals. The proposed MLE-DD synchronization algorithm requires one sample for the phase and two samples per symbol for the timing loop. The joint phase and timing discriminator characteristics are analytically derived and numerical results checked by means of computer simulations. An approximated expression for steady-state carrier phase and clock timing mean square error has been derived and successfully checked with simulation findings. Synchronizer deviation from the Cramer Rao bound is also discussed. Mean acquisition time for the digital synchronizer has also been computed and checked, using the Monte Carlo simulation technique. Finally, TC-8PSK digital demodulator performance in terms of bit error rate and mean time to lose lock, including digital interpolators and synchronization loops, is presented.

Programmable pulse generator based on programmable logic and direct digital synthesis.

PubMed

Suchenek, M; Starecki, T

2012-12-01

The paper presents a new approach of pulse generation which results in both wide range tunability and high accuracy of the output pulses. The concept is based on the use of programmable logic and direct digital synthesis. The programmable logic works as a set of programmable counters, while direct digital synthesis (DDS) as the clock source. Use of DDS as the clock source results in stability of the output pulses comparable to the stability of crystal oscillators and quasi-continuous tuning of the output frequency.

Synthesizing genetic sequential logic circuit with clock pulse generator.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang

2014-05-28

Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

Flip-Flop Digital Modulator

NASA Technical Reports Server (NTRS)

Eno, R. F.

1984-01-01

Clock switched on and off in response to data signal. Flip-flop modulator generates square-wave carrier frequency that is half clock frequency and turns carrier on and off. Final demodulator output logical inverse of data input.

Design of a delay-locked-loop-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Zhaoxin, Ma; Xuefei, Bai; Lu, Huang

2013-09-01

A time-to-digital converter (TDC) based on a reset-free and anti-harmonic delay-locked loop (DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid “false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 μm CMOS technology, and its core area occupies 0.7 × 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than ±0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

High resolution data acquisition

DOEpatents

Thornton, G.W.; Fuller, K.R.

1993-04-06

A high resolution event interval timing system measures short time intervals such as occur in high energy physics or laser ranging. Timing is provided from a clock, pulse train, and analog circuitry for generating a triangular wave synchronously with the pulse train (as seen in diagram on patent). The triangular wave has an amplitude and slope functionally related to the time elapsed during each clock pulse in the train. A converter forms a first digital value of the amplitude and slope of the triangle wave at the start of the event interval and a second digital value of the amplitude and slope of the triangle wave at the end of the event interval. A counter counts the clock pulse train during the interval to form a gross event interval time. A computer then combines the gross event interval time and the first and second digital values to output a high resolution value for the event interval.

High resolution data acquisition

DOEpatents

Thornton, Glenn W.; Fuller, Kenneth R.

1993-01-01

A high resolution event interval timing system measures short time intervals such as occur in high energy physics or laser ranging. Timing is provided from a clock (38) pulse train (37) and analog circuitry (44) for generating a triangular wave (46) synchronously with the pulse train (37). The triangular wave (46) has an amplitude and slope functionally related to the time elapsed during each clock pulse in the train. A converter (18, 32) forms a first digital value of the amplitude and slope of the triangle wave at the start of the event interval and a second digital value of the amplitude and slope of the triangle wave at the end of the event interval. A counter (26) counts the clock pulse train (37) during the interval to form a gross event interval time. A computer (52) then combines the gross event interval time and the first and second digital values to output a high resolution value for the event interval.

Processing circuit with asymmetry corrector and convolutional encoder for digital data

NASA Technical Reports Server (NTRS)

Pfiffner, Harold J. (Inventor)

1987-01-01

A processing circuit is provided for correcting for input parameter variations, such as data and clock signal symmetry, phase offset and jitter, noise and signal amplitude, in incoming data signals. An asymmetry corrector circuit performs the correcting function and furnishes the corrected data signals to a convolutional encoder circuit. The corrector circuit further forms a regenerated clock signal from clock pulses in the incoming data signals and another clock signal at a multiple of the incoming clock signal. These clock signals are furnished to the encoder circuit so that encoded data may be furnished to a modulator at a high data rate for transmission.

Synthesizing genetic sequential logic circuit with clock pulse generator

PubMed Central

2014-01-01

Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665

SpaceX Falcon Heavy Demo Flight - Press Site Activities

NASA Image and Video Library

2018-02-06

Members of the news media begin to gather near the countdown clock at NASA’s Kennedy Space Center in Florida to await liftoff of the SpaceX Falcon Heavy rocket, seen in the background at Launch Complex 39A. The demonstration flight will be a significant milestone for the world's premier multi-user spaceport. In 2014, NASA signed a property agreement with SpaceX for the use and operation of the center's pad 39A, where the company has launched Falcon 9 rockets and is preparing for the first Falcon Heavy. NASA also has Space Act Agreements in place with partners, such as SpaceX, to provide services needed to process and launch rockets and spacecraft.

KSC-05PD-1529

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. Mike Rein (right), division chief of Media Services at the NASA News Center, walks the area near the countdown clock (far right) at sunrise. The scene is the calm before the storm of journalists, photographers and television media who have descended upon KSC to capture the Return to Flight mission STS-114 to the International Space Station. This is the first Space Shuttle flight since the loss of Columbia, STS-107, on Feb. 1, 2003. Launch is scheduled for 3:51 p.m. EDT from Launch Pad 39B. The 12-day mission is expected to end with touchdown at NASA Kennedy Space Centers Shuttle Landing Facility at 11:06 a.m. July 25.

Digital Synchronizer without Metastability

NASA Technical Reports Server (NTRS)

Simle, Robert M.; Cavazos, Jose A.

2009-01-01

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Explosive Transient Camera (ETC) Program

DTIC Science & Technology

1991-10-01

VOLTAGES 4.- VIDEO OUT CCD CLOCKING UNIT UUPSTAIRS" ELECTRONICS AND ANALOG TO DIGITAL IPR OCECSSER I COMMANDS TO DATA AND STATUS INSTRUMENT INFORMATION I...and transmits digital video and status information to the "downstairs" system. The clocking unit and regulator/driver board are the only CCD dependent...A. 1001, " Video Cam-era’CC’" tandari Piells" (1(P’ll m-norartlum, unpublished). Condon,, J.J., Puckpan, M.A., and Vachalski, J. 1970, A. J., 9U, 1149

Inexpensive programmable clock for a 12-bit computer

NASA Technical Reports Server (NTRS)

Vrancik, J. E.

1972-01-01

An inexpensive programmable clock was built for a digital PDP-12 computer. The instruction list includes skip on flag; clear the flag, clear the clock, and stop the clock; and preset the counter with the contents of the accumulator and start the clock. The clock counts at a rate determined by an external oscillator and causes an interrupt and sets a flag when a 12-bit overflow occurs. An overflow can occur after 1 to 4096 counts. The clock can be built for a total parts cost of less than $100 including power supply and I/O connector. Slight modification can be made to permit its use on larger machines (16 bit, 24 bit, etc.) and logic level shifting can be made to make it compatible with any computer.

Adaptive sampler

DOEpatents

Watson, Bobby L.; Aeby, Ian

1982-01-01

An adaptive data compression device for compressing data having variable frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

Automation of extrusion of porous cable products based on a digital controller

NASA Astrophysics Data System (ADS)

Chostkovskii, B. K.; Mitroshin, V. N.

2017-07-01

This paper presents a new approach to designing an automated system for monitoring and controlling the process of applying porous insulation material on a conductive cable core, which is based on using structurally and parametrically optimized digital controllers of an arbitrary order instead of calculating typical PID controllers using known methods. The digital controller is clocked by signals from the clock length sensor of a measuring wheel, instead of a timer signal, and this provides the robust properties of the system with respect to the changing insulation speed. Digital controller parameters are tuned to provide the operating parameters of the manufactured cable using a simulation model of stochastic extrusion and are minimized by moving a regular simplex in the parameter space of the tuned controller.

A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module

NASA Astrophysics Data System (ADS)

Büchele, M.; Fischer, H.; Gorzellik, M.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

2012-03-01

The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine cards. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In contrast to common TDC concepts, the input signal is sampled by 16 equidistant phase-shifted clocks. A particular challenge of the design is the minimum skew routing of the input signals to the sampling flip-flops. We present measurement results for the differential nonlinearity and the time resolution of the TDC readout system.

Optical transmission modules for multi-channel superconducting quantum interference device readouts.

PubMed

Kim, Jin-Mok; Kwon, Hyukchan; Yu, Kwon-kyu; Lee, Yong-Ho; Kim, Kiwoong

2013-12-01

We developed an optical transmission module consisting of 16-channel analog-to-digital converter (ADC), digital-noise filter, and one-line serial transmitter, which transferred Superconducting Quantum Interference Device (SQUID) readout data to a computer by a single optical cable. A 16-channel ADC sent out SQUID readouts data with 32-bit serial data of 8-bit channel and 24-bit voltage data at a sample rate of 1.5 kSample/s. A digital-noise filter suppressed digital noises generated by digital clocks to obtain SQUID modulation as large as possible. One-line serial transmitter reformed 32-bit serial data to the modulated data that contained data and clock, and sent them through a single optical cable. When the optical transmission modules were applied to 152-channel SQUID magnetoencephalography system, this system maintained a field noise level of 3 fT/√Hz @ 100 Hz.

KSC-2011-1546

NASA Image and Video Library

2011-02-21

CAPE CANAVERAL, Fla. -- In Firing Room-4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch controllers took their posts at about 2:30 p.m. EST for space shuttle Discovery's STS-133 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 3 p.m. Scheduled to lift off Feb. 24 at 4:50 p.m. EST, Discovery and its six-member crew will deliver the Permanent Multipurpose Module, packed with supplies and critical spare parts, as well as Robonaut 2, the dexterous humanoid astronaut helper, to the orbiting outpost. For more information on the STS-133 mission, visit www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts133/. Photo credit: NASA/Frank Michaux

KSC-2011-1544

NASA Image and Video Library

2011-02-21

CAPE CANAVERAL, Fla. -- In Firing Room-4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch controllers took their posts at about 2:30 p.m. EST for space shuttle Discovery's STS-133 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 3 p.m. Scheduled to lift off Feb. 24 at 4:50 p.m. EST, Discovery and its six-member crew will deliver the Permanent Multipurpose Module, packed with supplies and critical spare parts, as well as Robonaut 2, the dexterous humanoid astronaut helper, to the orbiting outpost. For more information on the STS-133 mission, visit www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts133/. Photo credit: NASA/Frank Michaux

KSC-2011-1545

NASA Image and Video Library

2011-02-21

CAPE CANAVERAL, Fla. -- In Firing Room-4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch controllers took their posts at about 2:30 p.m. EST for space shuttle Discovery's STS-133 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 3 p.m. Scheduled to lift off Feb. 24 at 4:50 p.m. EST, Discovery and its six-member crew will deliver the Permanent Multipurpose Module, packed with supplies and critical spare parts, as well as Robonaut 2, the dexterous humanoid astronaut helper, to the orbiting outpost. For more information on the STS-133 mission, visit www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts133/. Photo credit: NASA/Frank Michaux

KSC-2011-1543

NASA Image and Video Library

2011-02-21

CAPE CANAVERAL, Fla. -- In Firing Room-4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch controllers took their posts at about 2:30 p.m. EST for space shuttle Discovery's STS-133 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 3 p.m. Scheduled to lift off Feb. 24 at 4:50 p.m. EST, Discovery and its six-member crew will deliver the Permanent Multipurpose Module, packed with supplies and critical spare parts, as well as Robonaut 2, the dexterous humanoid astronaut helper, to the orbiting outpost. For more information on the STS-133 mission, visit www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts133/. Photo credit: NASA/Frank Michaux

KSC-07pd1426

NASA Image and Video Library

2007-06-08

KENNEDY SPACE CENTER, FLA. -- Photographers crowd around the countdown clock and flag post near the NASA News Center to capture the successful on-time launch of Space Shuttle Atlantis from Launch Pad 39A at 7:38:04 p.m. EDT on mission STS-117. The shuttle is delivering a new segment to the starboard side of the International Space Station's backbone, known as the truss. Three spacewalks are planned to install the S3/S4 truss segment, deploy a set of solar arrays and prepare them for operation. STS-117 is the 118th space shuttle flight, the 21st flight to the station, the 28th flight for Atlantis and the first of four flights planned for 2007. Photo credit: NASA/Jim Grossmann

Adaptive sampler

DOEpatents

Watson, B.L.; Aeby, I.

1980-08-26

An adaptive data compression device for compressing data is described. The device has a frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

NASA Astrophysics Data System (ADS)

Park, Sungkyung; Park, Chester Sungchung

2018-03-01

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.

Clock and carrier recovery in high-speed coherent optical communication systems

NASA Astrophysics Data System (ADS)

Amado, Sofia B.; Ferreira, Ricardo; Costa, Pedro S.; Guiomar, Fernando P.; Ziaie, Somayeh; Teixeira, António L.; Muga, Nelson J.; Pinto, Armando N.

2014-08-01

In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

Development of high precision digital driver of acoustic-optical frequency shifter for ROG

NASA Astrophysics Data System (ADS)

Zhang, Rong; Kong, Mei; Xu, Yameng

2016-10-01

We develop a high precision digital driver of the acoustic-optical frequency shifter (AOFS) based on the parallel direct digital synthesizer (DDS) technology. We use an atomic clock as the phase-locked loop (PLL) reference clock, and the PLL is realized by a dual digital phase-locked loop. A DDS sampling clock up to 320 MHz with a frequency stability as low as 10-12 Hz is obtained. By constructing the RF signal measurement system, it is measured that the frequency output range of the AOFS-driver is 52-58 MHz, the center frequency of the band-pass filter is 55 MHz, the ripple in the band is less than 1 dB@3MHz, the single channel output power is up to 0.3 W, the frequency stability is 1 ppb (1 hour duration), and the frequency-shift precision is 0.1 Hz. The obtained frequency stability has two orders of improvement compared to that of the analog AOFS-drivers. For the designed binary frequency shift keying (2-FSK) and binary phase shift keying (2-PSK) modulation system, the demodulating frequency of the input TTL synchronous level signal is up to 10 kHz. The designed digital-bus coding/decoding system is compatible with many conventional digital bus protocols. It can interface with the ROG signal detecting software through the integrated drive electronics (IDE) and exchange data with the two DDS frequency-shift channels through the signal detecting software.

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution

NASA Astrophysics Data System (ADS)

Utagawa, Akira; Asai, Tetsuya; Hirose, Tetsuya; Amemiya, Yoshihito

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1], [2]. We regard neural oscillators as independent clock sources on LSIs; i. e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (<1GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-μm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

Reference clock parameters for digital communications systems applications

NASA Technical Reports Server (NTRS)

Kartaschoff, P.

1981-01-01

The basic parameters relevant to the design of network timing systems describe the random and systematic time departures of the system elements, i.e., master (or reference) clocks, transmission links, and other clocks controlled over the links. The quantitative relations between these parameters were established and illustrated by means of numerical examples based on available measured data. The examples were limited to a simple PLL control system but the analysis can eventually be applied to more sophisticated systems at the cost of increased computational effort.

Sample-Clock Phase-Control Feedback

NASA Technical Reports Server (NTRS)

Quirk, Kevin J.; Gin, Jonathan W.; Nguyen, Danh H.; Nguyen, Huy

2012-01-01

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.

Multifunction audio digitizer for communications systems

NASA Technical Reports Server (NTRS)

Monford, L. G., Jr.

1971-01-01

Digitizer accomplishes both N bit pulse code modulation /PCM/ and delta modulation, and provides modulation indicating variable signal gain and variable sidetone. Other features include - low package count, variable clock rate to optimize bandwidth, and easily expanded PCM output.

Digital Tidbits

ERIC Educational Resources Information Center

Kumaran, Maha; Geary, Joe

2011-01-01

Technology has transformed libraries. There are digital libraries, electronic collections, online databases and catalogs, ebooks, downloadable books, and much more. With free technology such as social websites, newspaper collections, downloadable online calendars, clocks and sticky notes, online scheduling, online document sharing, and online…

Coding for Single-Line Transmission

NASA Technical Reports Server (NTRS)

Madison, L. G.

1983-01-01

Digital transmission code combines data and clock signals into single waveform. MADCODE needs four standard integrated circuits in generator and converter plus five small discrete components. MADCODE allows simple coding and decoding for transmission of digital signals over single line.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

KSC-2011-7968

NASA Image and Video Library

2011-11-26

CAPE CANAVERAL, Fla. – At NASA Kennedy Space Center's Press Site in Florida, participants in NASA's Tweetup photograph the launch of the agency's Mars Science Laboratory (MSL) as the countdown clock ticks off the seconds. The tweeters will share their experiences with followers through the social networking site Twitter. The 197-foot-tall United Launch Alliance Atlas V rocket lifted off Space Launch Complex-41 on neighboring Cape Canaveral Air Force Station at 10:02 a.m. EST at the opening of the launch window. MSL's components include a car-sized rover, Curiosity, which has 10 science instruments designed to search for signs of life, including methane, and help determine if the gas is from a biological or geological source. For more information, visit http://www.nasa.gov/msl. Photo credit: NASA/Frankie Martin

STS-78 crew holds up Olympic torch at SLF

NASA Technical Reports Server (NTRS)

1996-01-01

KENNEDY SPACE CENTER, FLA. -- STS-78 Payload Commander Susan J. Helms (center) holds up an Olympic torch that was presented to the crew after they arrived at KSC's Shuttle Landing Facility. With Helms are (from left) Payload Specialist Robert Brenton Thirsk (Canadian Space Agency); Mission Specialist Charles E. Brady; Mission Commander Terence T. 'Tom' Henricks; Helms; Mission Specialist Richard M. Linnehan; Pilot Keven R. Kregel; and Payload Specialist Jean-Jacques Favier (French Space Agency). The crew will take the torch with them on their upcoming spaceflight and then present it upon their return to a representative of the Atlanta Committee for the Olympic games (ACOG). The countdown clock began ticking earlier today toward the June 20 launch of the Space Shuttle Columbia on Mission STS- 78, the fifth Shuttle flight of 1996.

All-digital phase-lock loops for noise-free signals

NASA Technical Reports Server (NTRS)

Anderson, T. O.

1973-01-01

Bit-synchronizers utilize all-digital phase-lock loops that are referenced to a high frequency digital clock. Phase-lock loop of first design acquires frequency within nominal range and tracks phase; second design is modified for random binary data by addition of simple transition detector; and third design acquires frequency over wide dynamic range.

Phase-lock-loop application for fiber optic receiver

NASA Astrophysics Data System (ADS)

Ruggles, Stephen L.; Wills, Robert W.

1991-02-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Phase-lock-loop application for fiber optic receiver

NASA Technical Reports Server (NTRS)

Ruggles, Stephen L.; Wills, Robert W.

1991-01-01

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Arbitrary digital pulse sequence generator with delay-loop timing

NASA Astrophysics Data System (ADS)

Hošák, Radim; Ježek, Miroslav

2018-04-01

We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to two clock cycles. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate its capability to produce temporal delays ranging from tens of nanoseconds to hundreds of seconds, with 24 ns timing granularity and linear scaling of delay with respect to the number of delay loop iterations. The generator is optionally synchronized with an external clock source to provide 100 ps jitter and overall sequence repeatability within the whole temporal range. The generator is fully programmable and able to produce digital sequences of high complexity. The concept of the generator can be implemented using different microcontrollers and applied for controlling of various optical, atomic, and nuclear physics measurement setups.

Methods for synchronizing a countdown routine of a timer key and electronic device

DOEpatents

Condit, Reston A.; Daniels, Michael A.; Clemens, Gregory P.; Tomberlin, Eric S.; Johnson, Joel A.

2015-06-02

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

Engineer Modeling Study. Volume II. Users Manual.

DTIC Science & Technology

1982-09-01

Distribution Center, Digital Equip- ment Corporation, 1980). The following paragraphs briefly describe each of the major input sections...abbreviation 3. A sequence number for post-processing 4. Clock time 5. Order number pointer (six digits ) 6. Job number pointer (six digits ) 7. Unit number...KIT) Users Manual (Boeing Computer % Services, Inc., 1977). S VAX/VMS Users Manual. Volume 3A (Software Distribution Center, Digital Equipment

A synchronization technique for the on-board master clock of a regenerative TDMA satellite communications system

NASA Astrophysics Data System (ADS)

Pattini, F.; Porzio Giusto, P.

The design criteria and performance of the master clock (MCK) generator and the unique word (UW) detector are examined. A narrow band phase lock loop is used for the onboard MCK generator and it is implemented with an all-digital scheme that employs a D-type flip flop as the phase detector. The performance of the MCK generator is analyzed with a computer program which considers phase offset of the digital phase comparator. The characteristics and capabilities of the UW detector which provides strobe signals for the MCK generator and synchronization signals for the onboard switching matrix are described.

Scalable Multiprocessor for High-Speed Computing in Space

NASA Technical Reports Server (NTRS)

Lux, James; Lang, Minh; Nishimoto, Kouji; Clark, Douglas; Stosic, Dorothy; Bachmann, Alex; Wilkinson, William; Steffke, Richard

2004-01-01

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

Apparatus, system, and method for synchronizing a timer key

DOEpatents

Condit, Reston A; Daniels, Michael A; Clemens, Gregory P; Tomberlin, Eric S; Johnson, Joel A

2014-04-22

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

An open source digital servo for atomic, molecular, and optical physics experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leibrandt, D. R., E-mail: david.leibrandt@nist.gov; Heidecker, J.

2015-12-15

We describe a general purpose digital servo optimized for feedback control of lasers in atomic, molecular, and optical physics experiments. The servo is capable of feedback bandwidths up to roughly 1 MHz (limited by the 320 ns total latency); loop filter shapes up to fifth order; multiple-input, multiple-output control; and automatic lock acquisition. The configuration of the servo is controlled via a graphical user interface, which also provides a rudimentary software oscilloscope and tools for measurement of system transfer functions. We illustrate the functionality of the digital servo by describing its use in two example scenarios: frequency control of themore » laser used to probe the narrow clock transition of {sup 27}Al{sup +} in an optical atomic clock, and length control of a cavity used for resonant frequency doubling of a laser.« less

An open source digital servo for atomic, molecular, and optical physics experiments.

PubMed

Leibrandt, D R; Heidecker, J

2015-12-01

We describe a general purpose digital servo optimized for feedback control of lasers in atomic, molecular, and optical physics experiments. The servo is capable of feedback bandwidths up to roughly 1 MHz (limited by the 320 ns total latency); loop filter shapes up to fifth order; multiple-input, multiple-output control; and automatic lock acquisition. The configuration of the servo is controlled via a graphical user interface, which also provides a rudimentary software oscilloscope and tools for measurement of system transfer functions. We illustrate the functionality of the digital servo by describing its use in two example scenarios: frequency control of the laser used to probe the narrow clock transition of (27)Al(+) in an optical atomic clock, and length control of a cavity used for resonant frequency doubling of a laser.

An open source digital servo for atomic, molecular, and optical physics experiments

NASA Astrophysics Data System (ADS)

Leibrandt, D. R.; Heidecker, J.

2015-12-01

We describe a general purpose digital servo optimized for feedback control of lasers in atomic, molecular, and optical physics experiments. The servo is capable of feedback bandwidths up to roughly 1 MHz (limited by the 320 ns total latency); loop filter shapes up to fifth order; multiple-input, multiple-output control; and automatic lock acquisition. The configuration of the servo is controlled via a graphical user interface, which also provides a rudimentary software oscilloscope and tools for measurement of system transfer functions. We illustrate the functionality of the digital servo by describing its use in two example scenarios: frequency control of the laser used to probe the narrow clock transition of 27Al+ in an optical atomic clock, and length control of a cavity used for resonant frequency doubling of a laser.

An open source digital servo for atomic, molecular, and optical physics experiments

PubMed Central

Leibrandt, D. R.; Heidecker, J.

2016-01-01

We describe a general purpose digital servo optimized for feedback control of lasers in atomic, molecular, and optical physics experiments. The servo is capable of feedback bandwidths up to roughly 1 MHz (limited by the 320 ns total latency); loop filter shapes up to fifth order; multiple-input, multiple-output control; and automatic lock acquisition. The configuration of the servo is controlled via a graphical user interface, which also provides a rudimentary software oscilloscope and tools for measurement of system transfer functions. We illustrate the functionality of the digital servo by describing its use in two example scenarios: frequency control of the laser used to probe the narrow clock transition of 27Al+ in an optical atomic clock, and length control of a cavity used for resonant frequency doubling of a laser. PMID:26724014

Generation of optical OFDM signals using 21.4 GS/s real time digital signal processing.

PubMed

Benlachtar, Yannis; Watts, Philip M; Bouziane, Rachid; Milder, Peter; Rangaraj, Deepak; Cartolano, Anthony; Koutsoyannis, Robert; Hoe, James C; Püschel, Markus; Glick, Madeleine; Killey, Robert I

2009-09-28

We demonstrate a field programmable gate array (FPGA) based optical orthogonal frequency division multiplexing (OFDM) transmitter implementing real time digital signal processing at a sample rate of 21.4 GS/s. The QPSK-OFDM signal is generated using an 8 bit, 128 point inverse fast Fourier transform (IFFT) core, performing one transform per clock cycle at a clock speed of 167.2 MHz and can be deployed with either a direct-detection or a coherent receiver. The hardware design and the main digital signal processing functions are described, and we show that the main performance limitation is due to the low (4-bit) resolution of the digital-to-analog converter (DAC) and the 8-bit resolution of the IFFT core used. We analyze the back-to-back performance of the transmitter generating an 8.36 Gb/s optical single sideband (SSB) OFDM signal using digital up-conversion, suitable for direct-detection. Additionally, we use the device to transmit 8.36 Gb/s SSB OFDM signals over 200 km of uncompensated standard single mode fiber achieving an overall BER<10(-3).

Development of Boolean calculus and its applications. [digital systems design

NASA Technical Reports Server (NTRS)

Tapia, M. A.

1980-01-01

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

KSC-2014-4033

NASA Image and Video Library

2014-09-21

CAPE CANAVERAL, Fla. – The countdown clock at the NASA Press Site ticks off the seconds following liftoff of the Falcon 9 rocket from Space Launch Complex 40 on Cape Canaveral Air Force Station in Florida, carrying the SpaceX CRS-4 mission to orbit. Liftoff was at 1:52 a.m. EDT. The mission is the fourth of 12 SpaceX flights NASA contracted with the company to resupply the space station. It will be the fifth trip by a Dragon spacecraft to the orbiting laboratory. The spacecraft’s 2.5 tons of supplies, science experiments, and technology demonstrations include critical materials to support 255 science and research investigations that will occur during the station's Expeditions 41 and 42. To learn more about the mission, visit http://www.nasa.gov/mission_pages/station/structure/launch/index.html. Photo credit: NASA/Frankie Martin

Wideband aperture array using RF channelizers and massively parallel digital 2D IIR filterbank

NASA Astrophysics Data System (ADS)

Sengupta, Arindam; Madanayake, Arjuna; Gómez-García, Roberto; Engeberg, Erik D.

2014-05-01

Wideband receive-mode beamforming applications in wireless location, electronically-scanned antennas for radar, RF sensing, microwave imaging and wireless communications require digital aperture arrays that offer a relatively constant far-field beam over several octaves of bandwidth. Several beamforming schemes including the well-known true time-delay and the phased array beamformers have been realized using either finite impulse response (FIR) or fast Fourier transform (FFT) digital filter-sum based techniques. These beamforming algorithms offer the desired selectivity at the cost of a high computational complexity and frequency-dependant far-field array patterns. A novel approach to receiver beamforming is the use of massively parallel 2-D infinite impulse response (IIR) fan filterbanks for the synthesis of relatively frequency independent RF beams at an order of magnitude lower multiplier complexity compared to FFT or FIR filter based conventional algorithms. The 2-D IIR filterbanks demand fast digital processing that can support several octaves of RF bandwidth, fast analog-to-digital converters (ADCs) for RF-to-bits type direct conversion of wideband antenna element signals. Fast digital implementation platforms that can realize high-precision recursive filter structures necessary for real-time beamforming, at RF radio bandwidths, are also desired. We propose a novel technique that combines a passive RF channelizer, multichannel ADC technology, and single-phase massively parallel 2-D IIR digital fan filterbanks, realized at low complexity using FPGA and/or ASIC technology. There exists native support for a larger bandwidth than the maximum clock frequency of the digital implementation technology. We also strive to achieve More-than-Moore throughput by processing a wideband RF signal having content with N-fold (B = N Fclk/2) bandwidth compared to the maximum clock frequency Fclk Hz of the digital VLSI platform under consideration. Such increase in bandwidth is achieved without use of polyphase signal processing or time-interleaved ADC methods. That is, all digital processors operate at the same Fclk clock frequency without phasing, while wideband operation is achieved by sub-sampling of narrower sub-bands at the the RF channelizer outputs.

Analysis of Circadian Leaf Movements.

PubMed

Müller, Niels A; Jiménez-Gómez, José M

2016-01-01

The circadian clock is a molecular timekeeper that controls a wide variety of biological processes. In plants, clock outputs range from the molecular level, with rhythmic gene expression and metabolite content, to physiological processes such as stomatal conductance or leaf movements. Any of these outputs can be used as markers to monitor the state of the circadian clock. In the model plant Arabidopsis thaliana, much of the current knowledge about the clock has been gained from time course experiments profiling expression of endogenous genes or reporter constructs regulated by the circadian clock. Since these methods require labor-intensive sample preparation or transformation, monitoring leaf movements is an interesting alternative, especially in non-model species and for natural variation studies. Technological improvements both in digital photography and image analysis allow cheap and easy monitoring of circadian leaf movements. In this chapter we present a protocol that uses an autonomous point and shoot camera and free software to monitor circadian leaf movements in tomato.

A precise clock distribution network for MRPC-based experiments

NASA Astrophysics Data System (ADS)

Wang, S.; Cao, P.; Shang, L.; An, Q.

2016-06-01

In high energy physics experiments, the MRPC (Multi-Gap Resistive Plate Chamber) detectors are widely used recently which can provide higher-resolution measurement for particle identification. However, the application of MRPC detectors leads to a series of challenges in electronics design with large number of front-end electronic channels, especially for distributing clock precisely. To deal with these challenges, this paper presents a universal scheme of clock transmission network for MRPC-based experiments with advantages of both precise clock distribution and global command synchronization. For precise clock distributing, the clock network is designed into a tree architecture with two stages: the first one has a point-to-multipoint long range bidirectional distribution with optical channels and the second one has a fan-out structure with copper link inside readout crates. To guarantee the precision of clock frequency or phase, the r-PTP (reduced Precision Time Protocol) and the DDMTD (digital Dual Mixer Time Difference) methods are used for frequency synthesis, phase measurement and adjustment, which is implemented by FPGA (Field Programmable Gate Array) in real-time. In addition, to synchronize global command execution, based upon this clock distribution network, synchronous signals are coded with clock for transmission. With technique of encoding/decoding and clock data recovery, signals such as global triggers or system control commands, can be distributed to all front-end channels synchronously, which greatly simplifies the system design. The experimental results show that both the clock jitter (RMS) and the clock skew can be less than 100 ps.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

PubMed Central

Sheng, Duo; Hong, Min-Rong

2016-01-01

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration. PMID:27754439

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

PubMed

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Digital Clock Drawing: differentiating "thinking" versus "doing" in younger and older adults with depression.

PubMed

Cohen, Jamie; Penney, Dana L; Davis, Randall; Libon, David J; Swenson, Rodney A; Ajilore, Olusola; Kumar, Anand; Lamar, Melissa

2014-10-01

Psychomotor slowing has been documented in depression. The digital Clock Drawing Test (dCDT) provides: (i) a novel technique to assess both cognitive and motor aspects of psychomotor speed within the same task and (ii) the potential to uncover subtleties of behavior not previously detected with non-digitized modes of data collection. Using digitized pen technology in 106 participants grouped by Age (younger/older) and Affect (euthymic/unmedicated depressed), we recorded cognitive and motor output by capturing how the clock is drawn rather than focusing on the final product. We divided time to completion (TTC) for Command and Copy conditions of the dCDT into metrics of percent of drawing (%Ink) versus non-drawing (%Think) time. We also obtained composite Z-scores of cognition, including attention/information processing (AIP), to explore associations of %Ink and %Think times to cognitive and motor performance. Despite equivalent TTC, %Ink and %Think Command times (Copy n.s.) were significant (AgeXAffect interaction: p=.03)-younger depressed spent a smaller proportion of time drawing relative to thinking compared to the older depressed group. Command %Think time negatively correlated with AIP in the older depressed group (r=-.46; p=.02). Copy %Think time negatively correlated with AIP in the younger depressed (r=-.47; p=.03) and older euthymic groups (r=-.51; p=.01). The dCDT differentiated aspects of psychomotor slowing in depression regardless of age, while dCDT/cognitive associates for younger adults with depression mimicked patterns of older euthymics.

Frequency control circuit for all-digital phase-lock loops

NASA Technical Reports Server (NTRS)

Anderson, T. O.

1973-01-01

Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate.

Childhood in a Digital Age: Creative Challenges for Educational Futures

ERIC Educational Resources Information Center

Craft, Anna

2012-01-01

The early twenty-first century is characterised by rapid change. Commentators note how permeating digital technologies engage increasing numbers of children, young people and adults as consumers and also producers. In the shifting technological landscape, childhood and youth are changing. Connectivity around the clock, with a parallel existence in…

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Synthetic aperture radar target simulator

NASA Technical Reports Server (NTRS)

Zebker, H. A.; Held, D. N.; Goldstein, R. M.; Bickler, T. C.

1984-01-01

A simulator for simulating the radar return, or echo, from a target seen by a SAR antenna mounted on a platform moving with respect to the target is described. It includes a first-in first-out memory which has digital information clocked in at a rate related to the frequency of a transmitted radar signal and digital information clocked out with a fixed delay defining range between the SAR and the simulated target, and at a rate related to the frequency of the return signal. An RF input signal having a frequency similar to that utilized by a synthetic aperture array radar is mixed with a local oscillator signal to provide a first baseband signal having a frequency considerably lower than that of the RF input signal.

Keeping a (Digital) Eye on Nature's Clock

ERIC Educational Resources Information Center

Magney, Troy; Eitel, Karla; Eitel, Jan; Jansen, Vincent; Schon, Jenny; Rittenburg, Rebecca; Vierling, Lee

2013-01-01

Many students probably take pictures daily. Whether snapshots of their friends at a Justin Bieber concert or of their latest skateboard trick, these images document changes in a student's life. Digital cameras can do more, however, than record memories to post on Facebook. They can also help students examine changes in their environment. This…

STS-103 crew wait inside Discovery for simulated countdown exercise

NASA Technical Reports Server (NTRS)

1999-01-01

Strapped into their seats inside the orbiter Discovery for a simulated countdown exercise are (left to right) STS-103 Mission Specialists Claude Nicollier of Switzerland, Steven L. Smith, and C. Michael Foale (Ph.D.). The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Jean-Fran'''ois Clervoy of France. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew wait inside Discovery for simulated countdown exercise

NASA Technical Reports Server (NTRS)

1999-01-01

Seated in the orbiter Discovery for a simulated countdown exercise is STS-103 Pilot Scott J. Kelly. The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), Jean- Fran'''ois Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew wait inside Discovery for simulated countdown exercise

NASA Technical Reports Server (NTRS)

1999-01-01

STS-103 Mission Specialist John M. Grunsfeld (Ph.D.) sits inside orbiter Discovery waiting for the start of a simulated countdown exercise. The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), Jean-Fran'''ois Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew wait inside Discovery for simulated countdown exercise

NASA Technical Reports Server (NTRS)

1999-01-01

STS-103 Mission Commander Curtis L. Brown Jr. sits inside orbiter Discovery waiting for the start of a simulated countdown exercise. The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), Jean-Fran'''ois Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew wait inside Discovery for simulated countdown exercise

NASA Technical Reports Server (NTRS)

1999-01-01

STS-103 Mission Specialists Jean-Fran'''ois Clervoy of France takes his seat inside the Space Shuttle Discovery during a practice launch countdown, part of Terminal Countdown Demonstration Test (TCDT) activities, while astronaut David 'Doc' Brown checks him out. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-78 Crew and alternates arrive at the SLF

NASA Technical Reports Server (NTRS)

1996-01-01

KENNEDY SPACE CENTER, FL. -- STS-78 Mission Commander Terence T. 'Tom' Henricks (third from left) displays an Olympic torch that was presented to the flight crew and their alternates after they arrived at KSC's Shuttle Landing Facility. With Henricks are (from left) Payload Specialist Jean-Jacques Favier (French Space Agency); Alternate Payload Specialist Luca Urbani (Italian Space Agency); Henricks; Mission Specialist Charles E. Brady Jr.; Payload Commander Susan J. Helms; Pilot Kevin R. Kregel; Mission Specialist Richard M. Linnehan; Alternate Payload Specialist Pedro Duque (European Space Agency); and Payload Specialist Robert Brenton Thirsk (Canadian Space Agency). The crew will take the torch with them on their upcoming spaceflight and then present it upon their return to a representative of the Atlanta Committee for the Olympic games (ACOG). The countdown clock began ticking earlier today toward the June 20 launch of the Space Shuttle Columbia on Mission STS-78, the fifth Shuttle flight of 1996.

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

NASA Technical Reports Server (NTRS)

Schuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li; Madala, Shridhar

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system.

PubMed

Jiang, Jia-Jia; Duan, Fa-Jie; Li, Yan-Chao; Hua, Xiang-Ning

2014-03-01

Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper.

Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system

NASA Astrophysics Data System (ADS)

Jiang, Jia-Jia; Duan, Fa-Jie; Li, Yan-Chao; Hua, Xiang-Ning

2014-03-01

Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper.

Versatile all-digital time interval measuring system

NASA Astrophysics Data System (ADS)

Vyhlidal, David; Cech, Miroslav

2011-06-01

This paper describes a design and performance of a versatile all-digital time interval measuring system. The measurement method is based on an interpolation principle. In this principle the time interval is first roughly digitized by a coarse counter driven by a high stability reference clock and the fractions between the clock periods are measured by two Time-to-Digital Converter chips TDC-GPX manufactured by Acam messelectronic. Control circuits allow programmable customization of the system to satisfy many applications such as laser range finding, event counting, or time-of-flight measurements in various physics experiments. The system has two reference clocks inputs and two independent channels for measuring start and stop events. Only one 40 MHz reference is required for the measurement. The second reference can be, for example, 1 PPS (Pulse per Second) signal from a GPS (Global Positioning System) to time tag events. Time intervals are measured using the highest resolution mode of the TDC-GPX chips. The resolution of each chip is software programmable and is PLL (Phase Locked Loop) stabilized against temperature and voltage variations. The system can achieve a timing resolution better than 15 ps rms with up to 90 kHz repetition rate. The time interval measurement range is from 0 ps up to 1 second. The power consumption of the whole system is 18 W including an embedded computer board and an LCD (Liquid Crystal Display) screen. The embedded computer controls the whole system, collects and evaluates measurement data and with the display provides a user interface. The system is implemented using commercially available components.

Digital clock drawing: Differentiating ‘thinking’ versus ‘doing’ in younger and older adults with depression

PubMed Central

Cohen, Jamie; Penney, Dana L.; Davis, Randall; Libon, David J.; Swenson, Rodney A.; Ajilore, Olusola; Kumar, Anand; Lamar, Melissa

2015-01-01

Objective Psychomotor slowing has been documented in depression. The digital Clock Drawing Test (dCDT) provides: i) a novel technique to assess both cognitive and motor aspects of psychomotor speed within the same task and ii) the potential to uncover subtleties of behavior not previously detected with non-digitized modes of data collection. Method Using digitized pen technology in 106 participants grouped by Age (younger/older) and Affect (euthymic/unmedicated depressed), we recorded cognitive and motor output by capturing how the clock is drawn rather than focusing on the final product. We divided time to completion (TTC) for Command and Copy conditions of the dCDT into metrics of percent of drawing (%Ink) versus non-drawing (%Think) time. We also obtained composite z-scores of cognition, including attention/ information processing (AIP), to explore associations of %Ink and %Think times to cognitive and motor performance. Results Despite equivalent TTC, %Ink and %Think Command times (Copy n.s.) were significant (AgeXAffect interaction:p=.03)—younger depressed spent a smaller proportion of time drawing relative to thinking compared to the older depressed group. Command %Think time negatively correlated with AIP in the older depressed group (r=−.46;p=.02). Copy %Think time negatively correlated with AIP in the younger depressed (r=−.47;p=.03) and older euthymic groups (r=−.51;p=.01). Conclusion The dCDT differentiated aspects of psychomotor slowing in depression regardless of age, while dCDT/cognitive associates for younger adults with depression mimicked patterns of older euthymics. PMID:25222513

Artifacts in Digital Coincidence Timing

PubMed Central

Moses, W. W.; Peng, Q.

2014-01-01

Digital methods are becoming increasingly popular for measuring time differences, and are the de facto standard in PET cameras. These methods usually include a master system clock and a (digital) arrival time estimate for each detector that is obtained by comparing the detector output signal to some reference portion of this clock (such as the rising edge). Time differences between detector signals are then obtained by subtracting the digitized estimates from a detector pair. A number of different methods can be used to generate the digitized arrival time of the detector output, such as sending a discriminator output into a time to digital converter (TDC) or digitizing the waveform and applying a more sophisticated algorithm to extract a timing estimator. All measurement methods are subject to error, and one generally wants to minimize these errors and so optimize the timing resolution. A common method for optimizing timing methods is to measure the coincidence timing resolution between two timing signals whose time difference should be constant (such as detecting gammas from positron annihilation) and selecting the method that minimizes the width of the distribution (i.e., the timing resolution). Unfortunately, a common form of error (a nonlinear transfer function) leads to artifacts that artificially narrow this resolution, which can lead to erroneous selection of the “optimal” method. The purpose of this note is to demonstrate the origin of this artifact and suggest that caution should be used when optimizing time digitization systems solely on timing resolution minimization. PMID:25321885

Artifacts in digital coincidence timing

DOE PAGES

Moses, W. W.; Peng, Q.

2014-10-16

Digital methods are becoming increasingly popular for measuring time differences, and are the de facto standard in PET cameras. These methods usually include a master system clock and a (digital) arrival time estimate for each detector that is obtained by comparing the detector output signal to some reference portion of this clock (such as the rising edge). Time differences between detector signals are then obtained by subtracting the digitized estimates from a detector pair. A number of different methods can be used to generate the digitized arrival time of the detector output, such as sending a discriminator output into amore » time to digital converter (TDC) or digitizing the waveform and applying a more sophisticated algorithm to extract a timing estimator.All measurement methods are subject to error, and one generally wants to minimize these errors and so optimize the timing resolution. A common method for optimizing timing methods is to measure the coincidence timing resolution between two timing signals whose time difference should be constant (such as detecting gammas from positron annihilation) and selecting the method that minimizes the width of the distribution (i.e. the timing resolution). Unfortunately, a common form of error (a nonlinear transfer function) leads to artifacts that artificially narrow this resolution, which can lead to erroneous selection of the 'optimal' method. In conclusion, the purpose of this note is to demonstrate the origin of this artifact and suggest that caution should be used when optimizing time digitization systems solely on timing resolution minimization.« less

Artifacts in digital coincidence timing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moses, W. W.; Peng, Q.

Digital methods are becoming increasingly popular for measuring time differences, and are the de facto standard in PET cameras. These methods usually include a master system clock and a (digital) arrival time estimate for each detector that is obtained by comparing the detector output signal to some reference portion of this clock (such as the rising edge). Time differences between detector signals are then obtained by subtracting the digitized estimates from a detector pair. A number of different methods can be used to generate the digitized arrival time of the detector output, such as sending a discriminator output into amore » time to digital converter (TDC) or digitizing the waveform and applying a more sophisticated algorithm to extract a timing estimator.All measurement methods are subject to error, and one generally wants to minimize these errors and so optimize the timing resolution. A common method for optimizing timing methods is to measure the coincidence timing resolution between two timing signals whose time difference should be constant (such as detecting gammas from positron annihilation) and selecting the method that minimizes the width of the distribution (i.e. the timing resolution). Unfortunately, a common form of error (a nonlinear transfer function) leads to artifacts that artificially narrow this resolution, which can lead to erroneous selection of the 'optimal' method. In conclusion, the purpose of this note is to demonstrate the origin of this artifact and suggest that caution should be used when optimizing time digitization systems solely on timing resolution minimization.« less

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

NASA Astrophysics Data System (ADS)

Li, Hangbiao; Zhang, Bo; Luo, Ping; Liao, Pengfei; Liu, Junjie; Li, Zhaoji

2015-03-01

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

NASA Astrophysics Data System (ADS)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1-2 MHz and image clock frequencies in the range 10-100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

NASA Astrophysics Data System (ADS)

Wei, Liu; Wei, Li; Peng, Ren; Qinglong, Lin; Shengdong, Zhang; Yangyuan, Wang

2009-09-01

A time-domain digitally controlled oscillator (DCO) is proposed. The DCO is composed of a free-running ring oscillator (FRO) and a two lap-selectors integrated flying-adder (FA). With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13 μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

High-speed clock recovery unit based on a phase aligner

NASA Astrophysics Data System (ADS)

Tejera, Efrain; Esper-Chain, Roberto; Tobajas, Felix; De Armas, Valentin; Sarmiento, Roberto

2003-04-01

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.

Clock recovery PLL with gated PFD for NRZ ON-OFF Modulated Signals in a retinal implant system.

PubMed

Brendler, Christian; Aryan, Naser Pour; Rieger, Viola; Rothermel, Albrecht

2013-01-01

A Clock Recovery Phase Locked Loop with Gated Phase Frequency Detector (GPLL) for NRZ ON-OFF Modulated Signals with low data transmission rates for an inductively powered subretinal implant system is presented. Low data transmission rate leads to a long absence of inductive powering in the system when zeros are transmitted. Consequently there is no possibility to extract any clock in these pauses, thus the digital circuitry can not work any more. Compared to a commonly used PLL for clock extraction, no certain amount of data transitions is needed. This is achieved by having two operating modes. In one mode the GPLL tracks the HF input signal. In the other, the GPLL is an adjustable oscillator oscillating at the last used frequency. The proposed GPLL is fabricated and measured using a 350 nm High Voltage CMOS technology.

Agile high resolution arbitrary waveform generator with jitterless frequency stepping

DOEpatents

Reilly, Peter T. A.; Koizumi, Hideya

2010-05-11

Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

A feasibility study of a data acquisition system for a silicon strip detector with a digital readout scheme

NASA Astrophysics Data System (ADS)

Ikeda, Hirokazu; Ikeda, Mitsuo; Inaba, Susumu; Tanaka, Manobu

1993-06-01

We describe a prototype data acquisition system for a silicon strip detector, which has been developed in terms of a digital readout scheme. The system consists of a master timing generator, readout controller, and a detector emulator card on which we use custom VLSI shift registers with operating clock frequency of 30 MHz.

Skylab Rescue Space Vehicle OAT No. 1 Plugs in Test

NASA Technical Reports Server (NTRS)

Jevitt, S. J.

1973-01-01

A test is described which demonstrates the compatibility of the Skylab Rescue Space Vehicle systems, the ground support equipment, and off-site support facilities by proceeding through a simulated launch countdown, liftoff, and flight. The functions of propellant loading, umbilical ejection, holddown arm release, service arm retraction, liftoff, and inflight separation are simulated. An external power source supplies transfer power to internal, and instrument unit commands are simulated by the digital command system. The test outline is presented along with a list of references, intercommunications information, radio frequency matrix, and interface control chart.

Performance Effects of Display Incogruity in a Digital and Analog Clock Reading Task

NASA Technical Reports Server (NTRS)

Comstock, J. Raymond, Jr.; Derks, Peter L.

2004-01-01

In an era of increasing automation, it is important to design displays and input devices that minimize human error. In this context, information concerning the human response to the detection of incongruous information is important. Such incongruous information can be operationalized as unexpected (perhaps erroneous) information on which a decision by the human or operation by an automated system is based. In the aviation environment, decision making when faced with inadequate, incomplete, or incongruous information may occur in a failure scenario. An additional challenge facing the human operator in automated environments is maintaining alertness or vigilance. The vigilance issue is of particular concern as a factor that may interact with performance when faced with inadequate, incomplete, or incongruous information. From the literature on eye-scan behavior we know that the time spent looking at a particular display or indicator is a function of the type of information one is trying to discern from the display. For example, quick glances are all it takes for confirming that an indicator is in a normal position or range, whereas a continuous look of several seconds may be required for confirmation that a complex control input is having the desired effect. Important to consider is that while an extended look takes place, visual input from other sources may be missed. Much like an extended look, the interpretation of incongruous information may require extra time. The present experiment was designed to explore the performance consequences of a decision making task when incongruous information was presented. For this experiment a display incongruity was created on a subset of trials of a clock reading laboratory task. Display incongruity was made possible through presentation of 'impossible' times (e.g. 1:65 or 11:90). Subjects made 'same' 'different' decisions and keyboard responses to pairings of Analog-Analog (AA), Digital-Digital (DD), and Analog- Digital (AD), display combinations. For trials during which display incongruities were not presented, based on prior research comparing digital and analog clock displays, it would be expected that the Digital-Digital condition would result in the shortest response times and the Analog-Analog and Analog-Digital conditions would have longer response times. The performance consequence expected on trials with incongruous times would be very long response times.

A Timer for Synchronous Digital Systems

NASA Technical Reports Server (NTRS)

McKenney, Elizabeth; Irwin, Philip

2003-01-01

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

Computer Program Recognizes Patterns in Time-Series Data

NASA Technical Reports Server (NTRS)

Hand, Charles

2003-01-01

A computer program recognizes selected patterns in time-series data like digitized samples of seismic or electrophysiological signals. The program implements an artificial neural network (ANN) and a set of N clocks for the purpose of determining whether N or more instances of a certain waveform, W, occur within a given time interval, T. The ANN must be trained to recognize W in the incoming stream of data. The first time the ANN recognizes W, it sets clock 1 to count down from T to zero; the second time it recognizes W, it sets clock 2 to count down from T to zero, and so forth through the Nth instance. On the N + 1st instance, the cycle is repeated, starting with clock 1. If any clock has not reached zero when it is reset, then N instances of W have been detected within time T, and the program so indicates. The program can readily be encoded in a field-programmable gate array or an application-specific integrated circuit that could be used, for example, to detect electroencephalographic or electrocardiographic waveforms indicative of epileptic seizures or heart attacks, respectively.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Sano, Y.; Horii, Y.; Ikeno, M.; Sasaki, O.; Tomoto, M.; Uchida, T.

2017-12-01

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.

A digital clock recovery algorithm based on chromatic dispersion and polarization mode dispersion feedback dual phase detection for coherent optical transmission systems

NASA Astrophysics Data System (ADS)

Liu, Bo; Xin, Xiangjun; Zhang, Lijia; Wang, Fu; Zhang, Qi

2018-02-01

A new feedback symbol timing recovery technique using timing estimation joint equalization is proposed for digital receivers with two samples/symbol or higher sampling rate. Different from traditional methods, the clock recovery algorithm in this paper adopts another algorithm distinguishing the phases of adjacent symbols, so as to accurately estimate the timing offset based on the adjacent signals with the same phase. The addition of the module for eliminating phase modulation interference before timing estimation further reduce the variance, thus resulting in a smoothed timing estimate. The Mean Square Error (MSE) and Bit Error Rate (BER) of the resulting timing estimate are simulated to allow a satisfactory estimation performance. The obtained clock tone performance is satisfactory for MQAM modulation formats and the Roll-off Factor (ROF) close to 0. In the back-to-back system, when ROF= 0, the maximum of MSE obtained with the proposed approach reaches 0 . 0125. After 100-km fiber transmission, BER decreases to 10-3 with ROF= 0 and OSNR = 11 dB. With the increase in ROF, the performances of MSE and BER become better.

Superconductor Digital Electronics: -- Current Status, Future Prospects

NASA Astrophysics Data System (ADS)

Mukhanov, Oleg

2011-03-01

Two major applications of superconductor electronics: communications and supercomputing will be presented. These areas hold a significant promise of a large impact on electronics state-of-the-art for the defense and commercial markets stemming from the fundamental advantages of superconductivity: simultaneous high speed and low power, lossless interconnect, natural quantization, and high sensitivity. The availability of relatively small cryocoolers lowered the foremost market barrier for cryogenically-cooled superconductor electronic systems. These fundamental advantages enabled a novel Digital-RF architecture - a disruptive technological approach changing wireless communications, radar, and surveillance system architectures dramatically. Practical results were achieved for Digital-RF systems in which wide-band, multi-band radio frequency signals are directly digitized and digital domain is expanded throughout the entire system. Digital-RF systems combine digital and mixed signal integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology, superconductor analog filter circuits, and semiconductor post-processing circuits. The demonstrated cryocooled Digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals, enabling multi-net data links, and performing signal acquisition from HF to L-band with 30 GHz clock frequencies. In supercomputing, superconductivity leads to the highest energy efficiencies per operation. Superconductor technology based on manipulation and ballistic transfer of magnetic flux quanta provides a superior low-power alternative to CMOS and other charge-transfer based device technologies. The fundamental energy consumption in SFQ circuits defined by flux quanta energy 2 x 10-19 J. Recently, a novel energy-efficient zero-static-power SFQ technology, eSFQ/ERSFQ was invented, which retains all advantages of standard RSFQ circuits: high-speed, dc power, internal memory. The voltage bias regulation, determined by SFQ clock, enables the zero-power at zero-activity regimes, indispensable for sensor and quantum bit readout.

USB video image controller used in CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhang, Wenxuan; Wang, Yuxia; Fan, Hong

2002-09-01

CMOS process is mainstream technique in VLSI, possesses high integration. SE402 is multifunction microcontroller, which integrates image data I/O ports, clock control, exposure control and digital signal processing into one chip. SE402 reduces the number of chips and PCB's room. The paper studies emphatically on USB video image controller used in CMOS image sensor and give the application on digital still camera.

Effects of countdown timers on driver behavior after the yellow onset at Chinese intersections.

PubMed

Long, Kejun; Han, Lee D; Yang, Qiang

2011-10-01

Few studies have focused on the effect of countdown timers at signalized intersections in China, where such timers are widely deployed for their perceived benefits of increased safety and capacity. This study examines the effect of countdown timers on driver behavior during the yellow interval. Signal phasing and traffic operations were videotaped at 4 comparable signalized intersections under normal conditions. Microscopic details were extracted manually at 25 Hz to yield 24 h of data on onset time of the yellow, onset time of the red, driver location and actions after the onset of the yellow, red light-running violations, etc. For comparable intersections with and without countdown timers, driver behavior measured by driver decision (stop or go) and vehicle entry time (when the vehicle crosses the stop line) were analyzed using binary logistical regression (BLR) and a nonparametric test, respectively. The results suggest that countdown timers can indeed influence driver behaviors, in terms of decisions to stop or cross the intersection as well as the distribution of vehicle entry times. There was a strong correlation between the presence of countdown timers and an increase in red light violations. Countdown timers may lead to increased entrance into the intersection during the later portions of the yellow and even the red. This alarming finding calls for further research as well as for serious consideration before the field deployment of countdown timers.

Programmable noise bandwidth reduction by means of digital averaging

NASA Technical Reports Server (NTRS)

Poklemba, John J. (Inventor)

1993-01-01

Predetection noise bandwidth reduction is effected by a pre-averager capable of digitally averaging the samples of an input data signal over two or more symbols, the averaging interval being defined by the input sampling rate divided by the output sampling rate. As the averaged sample is clocked to a suitable detector at a much slower rate than the input signal sampling rate the noise bandwidth at the input to the detector is reduced, the input to the detector having an improved signal to noise ratio as a result of the averaging process, and the rate at which such subsequent processing must operate is correspondingly reduced. The pre-averager forms a data filter having an output sampling rate of one sample per symbol of received data. More specifically, selected ones of a plurality of samples accumulated over two or more symbol intervals are output in response to clock signals at a rate of one sample per symbol interval. The pre-averager includes circuitry for weighting digitized signal samples using stored finite impulse response (FIR) filter coefficients. A method according to the present invention is also disclosed.

Ring-array processor distribution topology for optical interconnects

NASA Technical Reports Server (NTRS)

Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

1992-01-01

The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

The effects of pedestrian countdown timers on safety and efficiency of operations at signalized intersections.

DOT National Transportation Integrated Search

2011-12-01

Pedestrian countdown timers are becoming common at urban and suburban intersections. The added information that : pedestrian countdown timers provide to pedestrians can also be used by approaching drivers. A before-and-after case study : on the effec...

A clock steering method: using a third-order type 3 DPLL equivalent to a Kalman filter with a delay

NASA Astrophysics Data System (ADS)

Wu, Yiwei; Gong, Hang; Zhu, Xiangwei; Ou, Gang

2015-12-01

In this paper we propose a new clock steering method, which uses a third-order type 3 digital phase locked loop (DPLL) which is equivalent to a Kalman filter with a delay. A general overview of the theoretical framework is described in detail including the transfer functions, the structure and control values, the specifications, and the approach to choosing a parameter. Simulations show that the performance of the time and frequency steering errors and the frequency stability are quite desirable. Comparing with traditional clock steering methods, it is easier to work with just one parameter. The DPLL method satisfies the requirements of generating a local representation of universal time coordinated and the system time of a global navigation satellite system.

14 CFR 1215.105 - Delivery of user data.

Code of Federal Regulations, 2010 CFR

2010-01-01

... SATELLITE SYSTEM (TDRSS) Use and Reimbursement Policy for Non-U.S. Government Users § 1215.105 Delivery of... determined by NASA in the form of one or more digital or analog bit streams synchronized to associated clock...

An open-source, extensible system for laboratory timing and control

NASA Astrophysics Data System (ADS)

Gaskell, Peter E.; Thorn, Jeremy J.; Alba, Sequoia; Steck, Daniel A.

2009-11-01

We describe a simple system for timing and control, which provides control of analog, digital, and radio-frequency signals. Our system differs from most common laboratory setups in that it is open source, built from off-the-shelf components, synchronized to a common and accurate clock, and connected over an Ethernet network. A simple bus architecture facilitates creating new and specialized devices with only moderate experience in circuit design. Each device operates independently, requiring only an Ethernet network connection to the controlling computer, a clock signal, and a trigger signal. This makes the system highly robust and scalable. The devices can all be connected to a single external clock, allowing synchronous operation of a large number of devices for situations requiring precise timing of many parallel control and acquisition channels. Provided an accurate enough clock, these devices are capable of triggering events separated by one day with near-microsecond precision. We have achieved precisions of ˜0.1 ppb (parts per 109) over 16 s.

Huntingtin protein: A new option for fixing the Huntington's disease countdown clock.

PubMed

Caterino, Marco; Squillaro, Tiziana; Montesarchio, Daniela; Giordano, Antonio; Giancola, Concetta; Melone, Mariarosa A B

2018-06-01

Huntington's disease is a dreadful, incurable disorder. It springs from the autosomal dominant mutation in the first exon of the HTT gene, which encodes for the huntingtin protein (HTT) and results in progressive neurodegeneration. Thus far, all the attempted approaches to tackle the mutant HTT-induced toxicity causing this disease have failed. The mutant protein comes with the aberrantly expanded poly-glutamine tract. It is primarily to blame for the build-up of β-amyloid-like HTT aggregates, deleterious once broadened beyond the critical ∼35-37 repeats threshold. Recent experimental findings have provided valuable information on the molecular basis underlying this HTT-driven neurodegeneration. These findings indicate that the poly-glutamine siding regions and many post-translation modifications either abet or counter the poly-glutamine tract. This review provides an overall, up-to-date insight into HTT biophysics and structural biology, particularly discussing novel pharmacological options to specifically target the mutated protein and thus inhibit its functions and toxicity. Copyright © 2018 Elsevier Ltd. All rights reserved.

KSC-97pc783

NASA Image and Video Library

1997-05-11

STS-84 crew members greet press representatives and other onlookers after their arrival at KSC’s Shuttle Landing Facility Sunday evening (May 12, 1997), about an hour before the countdown clock will begin ticking toward the scheduled May 15 launch of the Space Shuttle Atlantis on Mission STS-84. From left, are Mission Specialist Carlos I. Noriega, Pilot Eileen Marie Collins, Mission Specialist C. Michael Foale, Mission Specialist Elena V. Kondakova of the Russian Space Agency, Commander Charles J. Precourt, Mission Specialist Jean-Francois Clervoy of the European Space Agency, and Mission Specialist Edward Tsang Lu. STS-84 will be the sixth docking of the Space Shuttle with the Russian Space Station Mir. During the docking, Foale will transfer to the Russian space station to become a member of the Mir 23 crew, replacing U.S. astronaut Jerry M. Linenger, who will return to Earth on Atlantis. Foale is scheduled to remain on Mir about four months until his replacement arrives on STS-86 in September

An XML-based method for astronomy software designing

NASA Astrophysics Data System (ADS)

Liao, Mingxue; Aili, Yusupu; Zhang, Jin

XML-based method for standardization of software designing is introduced and analyzed and successfully applied to renovating the hardware and software of the digital clock at Urumqi Astronomical Station. Basic strategy for eliciting time information from the new digital clock of FT206 in the antenna control program is introduced. By FT206, the need to compute how many centuries passed since a certain day with sophisticated formulas is eliminated and it is no longer necessary to set right UT time for the computer holding control over antenna because the information about year, month, day are all deduced from Julian day dwelling in FT206, rather than from computer time. With XML-based method and standard for software designing, various existing designing methods are unified, communications and collaborations between developers are facilitated, and thus Internet-based mode of developing software becomes possible. The trend of development of XML-based designing method is predicted.

QPPM receiver for free-space laser communications

NASA Technical Reports Server (NTRS)

Budinger, J. M.; Mohamed, J. H.; Nagy, L. A.; Lizanich, P. J.; Mortensen, D. J.

1994-01-01

A prototype receiver developed at NASA Lewis Research Center for direct detection and demodulation of quaternary pulse position modulated (QPPM) optical carriers is described. The receiver enables dual-channel communications at 325-Megabits per second (Mbps) per channel. The optical components of the prototype receiver are briefly described. The electronic components, comprising the analog signal conditioning, slot clock recovery, matched filter and maximum likelihood data recovery circuits are described in more detail. A novel digital symbol clock recovery technique is presented as an alternative to conventional analog methods. Simulated link degradations including noise and pointing-error induced amplitude variations are applied. The bit-error-rate performance of the electronic portion of the prototype receiver under varying optical signal-to-noise power ratios is found to be within 1.5-dB of theory. Implementation of the receiver as a hybrid of analog and digital application specific integrated circuits is planned.

All-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors

NASA Astrophysics Data System (ADS)

Dunning, Jim; Garcia, Gerald; Lundberg, Jim; Nuckolls, Ed

1995-04-01

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 micron CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4x the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.

FPGA-based RF interference reduction techniques for simultaneous PET–MRI

PubMed Central

Gebhardt, P; Wehner, J; Weissler, B; Botnar, R; Marsden, P K; Schulz, V

2016-01-01

Abstract The combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) as a multi-modal imaging technique is considered very promising and powerful with regard to in vivo disease progression examination, therapy response monitoring and drug development. However, PET–MRI system design enabling simultaneous operation with unaffected intrinsic performance of both modalities is challenging. As one of the major issues, both the PET detectors and the MRI radio-frequency (RF) subsystem are exposed to electromagnetic (EM) interference, which may lead to PET and MRI signal-to-noise ratio (SNR) deteriorations. Early digitization of electronic PET signals within the MRI bore helps to preserve PET SNR, but occurs at the expense of increased amount of PET electronics inside the MRI and associated RF field emissions. This raises the likelihood of PET-related MRI interference by coupling into the MRI RF coil unwanted spurious signals considered as RF noise, as it degrades MRI SNR and results in MR image artefacts. RF shielding of PET detectors is a commonly used technique to reduce PET-related RF interferences, but can introduce eddy-current-related MRI disturbances and hinder the highest system integration. In this paper, we present RF interference reduction methods which rely on EM field coupling–decoupling principles of RF receive coils rather than suppressing emitted fields. By modifying clock frequencies and changing clock phase relations of digital circuits, the resulting RF field emission is optimised with regard to a lower field coupling into the MRI RF coil, thereby increasing the RF silence of PET detectors. Our methods are demonstrated by performing FPGA-based clock frequency and phase shifting of digital silicon photo-multipliers (dSiPMs) used in the PET modules of our MR-compatible Hyperion IID PET insert. We present simulations and magnetic-field map scans visualising the impact of altered clock phase pattern on the spatial RF field distribution, followed by MRI noise and SNR scans performed with an operating PET module using different clock frequencies and phase patterns. The methods were implemented via firmware design changes without any hardware modifications. This introduces new means of flexibility by enabling adaptive RF interference reduction optimisations in the field, e.g. when using a PET insert with different MRI systems or when different MRI RF coil types are to be operated with the same PET detector. PMID:27049898

FPGA-based RF interference reduction techniques for simultaneous PET-MRI.

PubMed

Gebhardt, P; Wehner, J; Weissler, B; Botnar, R; Marsden, P K; Schulz, V

2016-05-07

The combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) as a multi-modal imaging technique is considered very promising and powerful with regard to in vivo disease progression examination, therapy response monitoring and drug development. However, PET-MRI system design enabling simultaneous operation with unaffected intrinsic performance of both modalities is challenging. As one of the major issues, both the PET detectors and the MRI radio-frequency (RF) subsystem are exposed to electromagnetic (EM) interference, which may lead to PET and MRI signal-to-noise ratio (SNR) deteriorations. Early digitization of electronic PET signals within the MRI bore helps to preserve PET SNR, but occurs at the expense of increased amount of PET electronics inside the MRI and associated RF field emissions. This raises the likelihood of PET-related MRI interference by coupling into the MRI RF coil unwanted spurious signals considered as RF noise, as it degrades MRI SNR and results in MR image artefacts. RF shielding of PET detectors is a commonly used technique to reduce PET-related RF interferences, but can introduce eddy-current-related MRI disturbances and hinder the highest system integration. In this paper, we present RF interference reduction methods which rely on EM field coupling-decoupling principles of RF receive coils rather than suppressing emitted fields. By modifying clock frequencies and changing clock phase relations of digital circuits, the resulting RF field emission is optimised with regard to a lower field coupling into the MRI RF coil, thereby increasing the RF silence of PET detectors. Our methods are demonstrated by performing FPGA-based clock frequency and phase shifting of digital silicon photo-multipliers (dSiPMs) used in the PET modules of our MR-compatible Hyperion II (D) PET insert. We present simulations and magnetic-field map scans visualising the impact of altered clock phase pattern on the spatial RF field distribution, followed by MRI noise and SNR scans performed with an operating PET module using different clock frequencies and phase patterns. The methods were implemented via firmware design changes without any hardware modifications. This introduces new means of flexibility by enabling adaptive RF interference reduction optimisations in the field, e.g. when using a PET insert with different MRI systems or when different MRI RF coil types are to be operated with the same PET detector.

FPGA-based RF interference reduction techniques for simultaneous PET-MRI

NASA Astrophysics Data System (ADS)

Gebhardt, P.; Wehner, J.; Weissler, B.; Botnar, R.; Marsden, P. K.; Schulz, V.

2016-05-01

The combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) as a multi-modal imaging technique is considered very promising and powerful with regard to in vivo disease progression examination, therapy response monitoring and drug development. However, PET-MRI system design enabling simultaneous operation with unaffected intrinsic performance of both modalities is challenging. As one of the major issues, both the PET detectors and the MRI radio-frequency (RF) subsystem are exposed to electromagnetic (EM) interference, which may lead to PET and MRI signal-to-noise ratio (SNR) deteriorations. Early digitization of electronic PET signals within the MRI bore helps to preserve PET SNR, but occurs at the expense of increased amount of PET electronics inside the MRI and associated RF field emissions. This raises the likelihood of PET-related MRI interference by coupling into the MRI RF coil unwanted spurious signals considered as RF noise, as it degrades MRI SNR and results in MR image artefacts. RF shielding of PET detectors is a commonly used technique to reduce PET-related RF interferences, but can introduce eddy-current-related MRI disturbances and hinder the highest system integration. In this paper, we present RF interference reduction methods which rely on EM field coupling-decoupling principles of RF receive coils rather than suppressing emitted fields. By modifying clock frequencies and changing clock phase relations of digital circuits, the resulting RF field emission is optimised with regard to a lower field coupling into the MRI RF coil, thereby increasing the RF silence of PET detectors. Our methods are demonstrated by performing FPGA-based clock frequency and phase shifting of digital silicon photo-multipliers (dSiPMs) used in the PET modules of our MR-compatible Hyperion II D PET insert. We present simulations and magnetic-field map scans visualising the impact of altered clock phase pattern on the spatial RF field distribution, followed by MRI noise and SNR scans performed with an operating PET module using different clock frequencies and phase patterns. The methods were implemented via firmware design changes without any hardware modifications. This introduces new means of flexibility by enabling adaptive RF interference reduction optimisations in the field, e.g. when using a PET insert with different MRI systems or when different MRI RF coil types are to be operated with the same PET detector.

Clock and trigger distribution for CBM-TOF quality evaluation of RPC super module detector assemblies

NASA Astrophysics Data System (ADS)

Li, C.; Huang, X.; Cao, P.; Wang, J.; An, Q.

2018-03-01

RPC Super module (SM) detector assemblies are used for charged hadron identification in the Time-of-Flight (TOF) spectrometer at the Compressed Baryonic Matter (CBM) experiment. Each SM contains several multi-gap Resistive Plate Chambers (MRPCs) and provides up to 320 electronic channels in total for high-precision time measurements. Time resolution of the Time-to-Digital Converter (TDC) is required to be better than 20 ps. During mass production, the quality of each SM needs to be evaluated. In order to meet the requirements, the system clock signal as well as the trigger signal should be distributed precisely and synchronously to all electronics modules within the evaluation readout system. In this paper, a hierarchical clock and trigger distribution method is proposed for the quality evaluation of CBM-TOF SM detectors. In a first stage, the master clock and trigger module (CTM) allocated in a 6U PXI chassis distributes the clock and trigger signals to the slave CTM in the same chassis. In a second stage, the slave CTM transmits the clock and trigger signals to the TDC readout module (TRM) through one optical link. In a third stage, the TRM distributes the clock and trigger signals synchronously to 10 individual TDC boards. Laboratory test results show that the clock jitter at the third stage is less than 4 ps (RMS) and the trigger transmission latency from the master CTM to the TDC is about 272 ns with 11 ps (RMS) jitter. The overall performance complies well with the required specifications.

Cognitive and connectome properties detectable through individual differences in graphomotor organization.

PubMed

Lamar, Melissa; Ajilore, Olusola; Leow, Alex; Charlton, Rebecca; Cohen, Jamie; GadElkarim, Johnson; Yang, Shaolin; Zhang, Aifeng; Davis, Randall; Penney, Dana; Libon, David J; Kumar, Anand

2016-05-01

We investigated whether graphomotor organization during a digitized Clock Drawing Test (dCDT) would be associated with cognitive and/or brain structural differences detected with a tractography-derived structural connectome of the brain. 72 non-demented/non-depressed adults were categorized based on whether or not they used 'anchor' digits (i.e., 12, 3, 6, 9) before any other digits while completing dCDT instructions to "draw the face of a clock with all the numbers and set the hands to 10 after 11". 'Anchorers' were compared to 'non-anchorers' across dCDT, additional cognitive measures and connectome-based metrics. In the context of grossly intact clock drawings, anchorers required fewer strokes to complete the dCDT and outperformed non-anchorers on executive functioning and learning/memory/recognition tasks. Anchorers had higher local efficiency for the left medial orbitofrontal and transverse temporal cortices as well as the right rostral anterior cingulate and superior frontal gyrus versus non-anchorers suggesting better regional integration within local networks involving these regions; select aspects of which correlated with cognition. Results also revealed that anchorers' exhibited a higher degree of modular integration among heteromodal regions of the ventral visual processing stream versus non-anchorers. Thus, an easily observable graphomotor distinction was associated with 1) better performance in specific cognitive domains, 2) higher local efficiency suggesting better regional integration, and 3) more sophisticated modular integration involving the ventral ('what') visuospatial processing stream. Taken together, these results enhance our knowledge of the brain-behavior relationships underlying unprompted graphomotor organization during dCDT. Copyright © 2016 Elsevier Ltd. All rights reserved.

Holding a country countdown to 2015 conference on Millennium Development Goals (MDGs) - the Zambian experience.

PubMed

Mukonka, Victor M; Malumo, Sarai; Kalesha, Penelope; Nambao, Mary; Mwale, Rodgers; Mwinga, Kasonde; Katepa-Bwalya, Mary; Babaniyi, Olusegan; Mason, Elizabeth; Phiri, Caroline; Wamulume, Pauline K

2014-01-21

Initiatives such as the Country Countdown to 2015 Conference on Millennium Development Goals (MDGs) have provided countries with high maternal and child deaths like Zambia a platform to assess progress, discuss challenges and share lessons learnt as a conduit for national commitment to reaching and attaining the MDGs four and five. This paper discusses and highlights the process of holding a successful country countdown conference and shares Zambia's experience with other countries planning to organise country countdown to 2015 Conferences on MDGs.

Time of flight system on a chip

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas P. (Inventor)

2006-01-01

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Immediate Effects of Clock-Turn Strategy on the Pattern and Performance of Narrow Turning in Persons With Parkinson Disease.

PubMed

Yang, Wen-Chieh; Hsu, Wei-Li; Wu, Ruey-Meei; Lin, Kwan-Hwa

2016-10-01

Turning difficulty is common in people with Parkinson disease (PD). The clock-turn strategy is a cognitive movement strategy to improve turning performance in people with PD despite its effects are unverified. Therefore, this study aimed to investigate the effects of the clock-turn strategy on the pattern of turning steps, turning performance, and freezing of gait during a narrow turning, and how these effects were influenced by concurrent performance of a cognitive task (dual task). Twenty-five people with PD were randomly assigned to the clock-turn or usual-turn group. Participants performed the Timed Up and Go test with and without concurrent cognitive task during the medication OFF period. The clock-turn group performed the Timed Up and Go test using the clock-turn strategy, whereas participants in the usual-turn group performed in their usual manner. Measurements were taken during the 180° turn of the Timed Up and Go test. The pattern of turning steps was evaluated by step time variability and step time asymmetry. Turning performance was evaluated by turning time and number of turning steps. The number and duration of freezing of gait were calculated by video review. The clock-turn group had lower step time variability and step time asymmetry than the usual-turn group. Furthermore, the clock-turn group turned faster with fewer freezing of gait episodes than the usual-turn group. Dual task increased the step time variability and step time asymmetry in both groups but did not affect turning performance and freezing severity. The clock-turn strategy reduces turning time and freezing of gait during turning, probably by lowering step time variability and asymmetry. Dual task compromises the effects of the clock-turn strategy, suggesting a competition for attentional resources.Video Abstract available for more insights from the authors (see Supplemental Digital Content 1, http://links.lww.com/JNPT/A141).

Device for modular input high-speed multi-channel digitizing of electrical data

DOEpatents

VanDeusen, Alan L.; Crist, Charles E.

1995-09-26

A multi-channel high-speed digitizer module converts a plurality of analog signals to digital signals (digitizing) and stores the signals in a memory device. The analog input channels are digitized simultaneously at high speed with a relatively large number of on-board memory data points per channel. The module provides an automated calibration based upon a single voltage reference source. Low signal noise at such a high density and sample rate is accomplished by ensuring the A/D converters are clocked at the same point in the noise cycle each time so that synchronous noise sampling occurs. This sampling process, in conjunction with an automated calibration, yields signal noise levels well below the noise level present on the analog reference voltages.

The GANDALF 128-Channel Time-to-Digital Converter

NASA Astrophysics Data System (ADS)

Büchele, M.; Fischer, H.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabric is a particular challenge of this design. We present measurement results for the time resolution and the nonlinearity of the TDC readout system.

Screening for cognitive dysfunction in Huntington's disease with the clock drawing test.

PubMed

Terwindt, Paul W; Hubers, Anna A M; Giltay, Erik J; van der Mast, Rose C; van Duijn, Erik

2016-09-01

The aim of the study is to investigate the performance of the clock drawing test as a screening tool for cognitive impairment in Huntington's disease (HD) mutation carriers. The performance of the clock drawing test was assessed in 65 mutation carriers using the Shulman and the Freund scoring systems. The mini-mental state examination, the Symbol Digit Modalities Test, the Verbal Fluency Test, and the Stroop tests were used as comparisons for the evaluation of cognitive functioning. Correlations of the clock drawing test with various cognitive tests (convergent validity), neuropsychiatric characteristics (divergent validity) and clinical characteristics were analysed using the Spearman's rank correlation coefficient. Receiver-operator characteristic analyses were performed for the clock drawing test against both the mini-mental state examination and against a composite variable for executive cognitive functioning to assess optimal cut-off scores. Inter-rater reliability was high for both the Shulman and Freund scoring systems (ICC = 0.95 and ICC = 0.90 respectively). The clock drawing tests showed moderate to high correlations with the composite variable for executive cognitive functioning (mean ρ = 0.75) and weaker correlations with the mini-mental state examination (mean ρ = 0.62). Mean sensitivity of the clock drawing tests was 0.82 and mean specificity was 0.79, whereas the mean positive predictive value was 0.66 and the mean negative predictive value was 0.87. The clock drawing test is a suitable screening instrument for cognitive dysfunction in HD, because it was shown to be accurate, particularly so with respect to executive cognitive functioning, and is easy and quick to use. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.

Capacity upgrade in short-reach optical fibre networks: simultaneous 4-PAM 20 Gbps data and polarization-modulated PPS clock signal using a single VCSEL carrier

NASA Astrophysics Data System (ADS)

Isoe, G. M.; Wassin, S.; Gamatham, R. R. G.; Leitch, A. W. R.; Gibbon, T. B.

2017-11-01

In this work, a four-level pulse amplitude modulation (4-PAM) format with a polarization-modulated pulse per second (PPS) clock signal using a single vertical cavity surface emitting laser (VCSEL) carrier is for the first time experimentally demonstrated. We propose uncomplex alternative technique for increasing capacity and flexibility in short-reach optical communication links through multi-signal modulation onto a single VCSEL carrier. A 20 Gbps 4-PAM data signal is directly modulated onto a single mode 10 GHz bandwidth VCSEL carrier at 1310 nm, therefore, doubling the network bit rate. Carrier spectral efficiency is further maximized by exploiting the inherent orthogonal polarization switching of the VCSEL carrier with changing bias in transmission of a PPS clock signal. We, therefore, simultaneously transmit a 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal using a single VCSEL carrier. It is the first time a signal VCSEL carrier is reported to simultaneously transmit a directly modulated 20 Gbps 4-PAM data signal and a polarization-based PPS clock signal. We further demonstrate on the design of a software-defined digital signal processing (DSP)-assisted receiver as an alternative to costly receiver hardware. Experimental results show that a 3.21 km fibre transmission with simultaneous 20 Gbps 4-PAM data signal and polarization-based PPS clock signal introduced a penalty of 3.76 dB. The contribution of polarization-based PPS clock signal to this penalty was found out to be 0.41 dB. Simultaneous distribution of data and timing clock signals over shared network infrastructure significantly increases the aggregated data rate at different optical network units (ONUs), without costly investment.

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

An Automatic System for Global Monitoring of ELF and VLF Radio Noise Phenomena.

DTIC Science & Technology

1985-06-01

second low-jitter synchronization signal is also provided for precise triggering of analog-to- digital conversion samples. Both the clock and the...building in 1985 are two riometers (30 MHz and 51.4 MHz), a 3-axis fluxgate magnetometer , a 3-axis micropulsation magnetometer , an all-sky camera, and...of these filters 1s continuously sampled by a computerized recording system, and statistical averages are computed on-site and recorded on digital tape

Solid-state Image Sensor with Focal-plane Digital Photon-counting Pixel Array

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Pain, Bedabrata

1997-01-01

A solid-state focal-plane imaging system comprises an NxN array of high gain. low-noise unit cells. each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultra low level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer(either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (greater than 1mV/e(-)) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e(-))generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascade amplifier. Reseting the input capacitance and initiating self-biasing of the amplifiers occurs every clock cycle of an integratng period to enable ultralow light level image detection by the may of photovoltaic detector diodes under such ultralow light level conditions that the photon flux will statistically provide only a single photon at a time incident on anyone detector diode during any clock cycle.

Formal development of a clock synchronization circuit

NASA Technical Reports Server (NTRS)

Miner, Paul S.

1995-01-01

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

GNSS software receiver sampling noise and clock jitter performance and impact analysis

NASA Astrophysics Data System (ADS)

Chen, Jian Yun; Feng, XuZhe; Li, XianBin; Wu, GuangYao

2015-02-01

In the design of a multi-frequency multi-constellation GNSS software defined radio receivers is becoming more and more popular due to its simple architecture, flexible configuration and good coherence in multi-frequency signal processing. It plays an important role in navigation signal processing and signal quality monitoring. In particular, GNSS software defined radio receivers driving the sampling clock of analogue-to-digital converter (ADC) by FPGA implies that a more flexible radio transceiver design is possible. According to the concept of software defined radio (SDR), the ideal is to digitize as close to the antenna as possible. Whereas the carrier frequency of GNSS signal is of the frequency of GHz, converting at this frequency is expensive and consumes more power. Band sampling method is a cheaper, more effective alternative. When using band sampling method, it is possible to sample a RF signal at twice the bandwidth of the signal. Unfortunately, as the other side of the coin, the introduction of SDR concept and band sampling method induce negative influence on the performance of the GNSS receivers. ADC's suffer larger sampling clock jitter generated by FPGA; and low sampling frequency introduces more noise to the receiver. Then the influence of sampling noise cannot be neglected. The paper analyzes the sampling noise, presents its influence on the carrier noise ratio, and derives the ranging error by calculating the synchronization error of the delay locked loop. Simulations aiming at each impact factors of sampling-noise-induced ranging error are performed. Simulation and experiment results show that if the target ranging accuracy is at the level of centimeter, the quantization length should be no less than 8 and the sampling clock jitter should not exceed 30ps.

The influence of pedestrian countdown signals on children's crossing behavior at school intersections.

PubMed

Fu, Lianning; Zou, Nan

2016-09-01

Previous studies have shown that pedestrian countdown signals had different influences on pedestrian crossing behavior. The purpose of this study was to examine the effects of the installation of countdown signals at school intersections on children's crossing behavior. A comparison analysis was carried out on the basis of observations at two different school intersections with or without pedestrian countdown signals in the city of Jinan, China. Four types of children's crossing behavior and child pedestrian-vehicle conflicts were analyzed in detail. The analysis results showed that using pedestrian countdown timers during the Red Man phase led to more children's violation and running behavior. Theses violators created more conflicts with vehicles. However, pedestrian countdown signals were effective at helping child pedestrian to complete crossing before the red light onset, avoid getting caught in the middle of crosswalk. No significant difference was found in children who started crossing during Flashing Green Man phase between the two types of pedestrian signals. Moreover, analysis results indicated that children who crossed the road alone had more violation and adventure crossing behavior than those had companions. Boys were found more likely to run crossing than girls, but there was no significant gender difference in other crossing behavior. Finally, it's recommended to remove countdown at the end of the Red Man phase to improve children's crossing behavior and reduce the conflicts with vehicles. Meanwhile other measures are proposed to improve children safety at school intersections. Copyright © 2016 Elsevier Ltd. All rights reserved.

Distinguishing between evidence and its explanations in the steering of atomic clocks

NASA Astrophysics Data System (ADS)

Myers, John M.; Hadi Madjid, F.

2014-11-01

Quantum theory reflects within itself a separation of evidence from explanations. This separation leads to a known proof that: (1) no wave function can be determined uniquely by evidence, and (2) any chosen wave function requires a guess reaching beyond logic to things unforeseeable. Chosen wave functions are encoded into computer-mediated feedback essential to atomic clocks, including clocks that step computers through their phases of computation and clocks in space vehicles that supply evidence of signal propagation explained by hypotheses of spacetimes with metric tensor fields. The propagation of logical symbols from one computer to another requires a shared rhythm-like a bucket brigade. Here we show how hypothesized metric tensors, dependent on guesswork, take part in the logical synchronization by which clocks are steered in rate and position toward aiming points that satisfy phase constraints, thereby linking the physics of signal propagation with the sharing of logical symbols among computers. Recognizing the dependence of the phasing of symbol arrivals on guesses about signal propagation transports logical synchronization from the engineering of digital communications to a discipline essential to physics. Within this discipline we begin to explore questions invisible under any concept of time that fails to acknowledge unforeseeable events. In particular, variation of spacetime curvature is shown to limit the bit rate of logical communication.

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Network-Physics (NP) BEC DIGITAL(#)-VULNERABILITY; ``Q-Computing"=Simple-Arithmetic;Modular-Congruences=SignalXNoise PRODUCTS=Clock-model;BEC-Factorization;RANDOM-# Definition;P=/=NP TRIVIAL Proof!!!

NASA Astrophysics Data System (ADS)

Pi, E. I.; Siegel, E.

2010-03-01

Siegel[AMS Natl.Mtg.(2002)-Abs.973-60-124] digits logarithmic- law inversion to ONLY BEQS BEC:Quanta/Bosons=#: EMP-like SEVERE VULNERABILITY of ONLY #-networks(VS.ANALOG INvulnerability) via Barabasi NP(VS.dynamics[Not.AMS(5/2009)] critique);(so called)``quantum-computing''(QC) = simple-arithmetic (sansdivision);algorithmiccomplexities:INtractibility/UNdecidabi lity/INefficiency/NONcomputability/HARDNESS(so MIScalled) ``noise''-induced-phase-transition(NIT)ACCELERATION:Cook-Levin theorem Reducibility = RG fixed-points; #-Randomness DEFINITION via WHAT? Query(VS. Goldreich[Not.AMS(2002)] How? mea culpa)= ONLY MBCS hot-plasma v #-clumping NON-random BEC; Modular-Arithmetic Congruences = Signal x Noise PRODUCTS = clock-model; NON-Shor[Physica A,341,586(04)]BEC logarithmic-law inversion factorization: Watkins #-theory U statistical- physics); P=/=NP C-S TRIVIAL Proof: Euclid!!! [(So Miscalled) computational-complexity J-O obviation(3 millennia AGO geometry: NO:CC,``CS'';``Feet of Clay!!!'']; Query WHAT?:Definition: (so MIScalled)``complexity''=UTTER-SIMPLICITY!! v COMPLICATEDNESS MEASURE(S).

Device for modular input high-speed multi-channel digitizing of electrical data

DOEpatents

VanDeusen, A.L.; Crist, C.E.

1995-09-26

A multi-channel high-speed digitizer module converts a plurality of analog signals to digital signals (digitizing) and stores the signals in a memory device. The analog input channels are digitized simultaneously at high speed with a relatively large number of on-board memory data points per channel. The module provides an automated calibration based upon a single voltage reference source. Low signal noise at such a high density and sample rate is accomplished by ensuring the A/D converters are clocked at the same point in the noise cycle each time so that synchronous noise sampling occurs. This sampling process, in conjunction with an automated calibration, yields signal noise levels well below the noise level present on the analog reference voltages. 1 fig.

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-25

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervalswhere the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Final Paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-21

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervals-where the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

TimeSet: A computer program that accesses five atomic time services on two continents

NASA Technical Reports Server (NTRS)

Petrakis, P. L.

1993-01-01

TimeSet is a shareware program for accessing digital time services by telephone. At its initial release, it was capable of capturing time signals only from the U.S. Naval Observatory to set a computer's clock. Later the ability to synchronize with the National Institute of Standards and Technology was added. Now, in Version 7.10, TimeSet is able to access three additional telephone time services in Europe - in Sweden, Austria, and Italy - making a total of five official services addressable by the program. A companion program, TimeGen, allows yet another source of telephone time data strings for callers equipped with TimeSet version 7.10. TimeGen synthesizes UTC time data strings in the Naval Observatory's format from an accurately set and maintained DOS computer clock, and transmits them to callers. This allows an unlimited number of 'freelance' time generating stations to be created. Timesetting from TimeGen is made feasible by the advent of Becker's RighTime, a shareware program that learns the drift characteristics of a computer's clock and continuously applies a correction to keep it accurate, and also brings .01 second resolution to the DOS clock. With clock regulation by RighTime and periodic update calls by the TimeGen station to an official time source via TimeSet, TimeGen offers the same degree of accuracy within the resolution of the computer clock as any official atomic time source.

Study of Potential Standardization of Digital Freeze Frame Video Codecs.

DTIC Science & Technology

1984-01-01

and MAR track an input clock over a very wide range. These are dependent on the modem used in any specific application. Interface connectors are those...terminals, 56K bit digital transmission sets). We have a limited custan capability and are not in the custom unit business. 1.,o .2e e.. , , 4g..2. . j...will) are designed for narrowband operation. We build our own modems which send .’e- pixels at a rate of 1969 pixels/second. Grey scale information is

Multifrequency zero-jitter delay-locked loop

NASA Astrophysics Data System (ADS)

Efendovich, Avner; Afek, Yachin; Sella, Coby; Bikowsky, Zeev

1994-01-01

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions.

Risetime distortion of Shuttle Ku-band payload 50 MBPS data due to coaxial cable skin effects

NASA Technical Reports Server (NTRS)

Schadelbauer, S.; Vang, H. A.

1980-01-01

This paper discusses distortion of digital signals generated in the Space Shuttle Ku-band communications systems. Specifically, the degradation considered is due to coaxial cables which interface data and clock from a source located in the payload bay to the KuSPA (Ku-Band Signal Processor Assembly) located in the avionics bay of the Shuttle. Due to the length (nearly 100 feet) and relatively narrow bandwidth of the cable, the clock and data waveforms are significantly affected by this transmission medium. This paper presents a closed form model that closely approximates the distortion of the waveforms measured in laboratory tests.

An organization of a digital subsystem for generating spacecraft timing and control signals

NASA Technical Reports Server (NTRS)

Perlman, M.

1972-01-01

A modulo-M counter (of clock pulses) is decomposed into parallel modulo-m sub i counters, where each m sub i is a prime power divisor of M. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. By this organization, every possible nontrivial data frame subperiod and delayed subperiod may be derived. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.

Data processing method for a weak, moving telemetry signal

NASA Technical Reports Server (NTRS)

Kendall, W. B.; Levy, G. S.; Nixon, D. L.; Panson, P. L.

1969-01-01

Method of processing data from a spacecraft, where the carrier has a low signal-to-noise ratio and wide unpredictable frequency shifts, consists of analogue recording of the noisy signal along with a high-frequency tone that is used as a clock to trigger a digitizer.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson follows operations in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson at her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Test Director Christine St. Germain monitors operations in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

Wet countdown demonstration and flight readiness firing

NASA Technical Reports Server (NTRS)

1981-01-01

The prelaunch tests for the Space Transportation System 1 flight are briefly described. Testing is divided into two major sections: the wet countdown demonstration test/flight readiness firing, which includes a 20 second test firing of the orbiter's three main engines, and a mission verification test, which is centered on flight and landing operations. The functions of the countdown sequence are listed and end of mission and mission abort exercises are described.

A simple second-order digital phase-locked loop.

NASA Technical Reports Server (NTRS)

Tegnelia, C. R.

1972-01-01

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

Superconducting Digital Multiplexers for Sensor Arrays

NASA Technical Reports Server (NTRS)

Kadin, Alan M.; Brock, Darren K.; Gupta, Deepnarayan

2004-01-01

Arrays of cryogenic microbolometers and other cryogenic detectors are being developed for infrared imaging. If the signal from each sensor is amplified, multiplexed, and digitized using superconducting electronics, then this data can be efficiently read out to ambient temperature with a minimum of noise and thermal load. HYPRES is developing an integrated system based on SQUID amplifiers, a high-resolution analog-to-digital converter (ADC) based on RSFQ (rapid single flux quantum) logic, and a clocked RSFQ multiplexer. The ADC and SQUIDs have already been demonstrated for other projects, so this paper will focus on new results of a digital multiplexer. Several test circuits have been fabricated using Nb Josephson technology and are about to be tested at T = 4.2 K, with a more complete prototype in preparation.

KSC-2011-5051

NASA Image and Video Library

2011-07-05

CAPE CANAVERAL, Fla. -- In Firing Room 4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch team members took their posts at about 12:30 p.m. EDT, July 5 to prepare for space shuttle Atlantis' STS-135 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 1 p.m. Atlantis and its crew of four are scheduled to lift off at 11:26 a.m. EDT on July 8 to deliver the Raffaello multi-purpose logistics module packed with supplies and spare parts to the station. The STS-135 mission also will fly a system to investigate the potential for robotically refueling existing satellites and return a failed ammonia pump module to help NASA better understand the failure mechanism and improve pump designs for future systems. STS-135 will be the 33rd flight of Atlantis, the 37th shuttle mission to the space station, and the 135th and final mission of NASA's Space Shuttle Program. For more information visit, www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts135/index.html. Photo credit: NASA/Frankie Martin

KSC-2011-5050

NASA Image and Video Library

2011-07-05

CAPE CANAVERAL, Fla. -- In Firing Room 4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch team members took their posts at about 12:30 p.m. EDT, July 5 to prepare for space shuttle Atlantis' STS-135 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 1 p.m. Atlantis and its crew of four are scheduled to lift off at 11:26 a.m. EDT on July 8 to deliver the Raffaello multi-purpose logistics module packed with supplies and spare parts to the station. The STS-135 mission also will fly a system to investigate the potential for robotically refueling existing satellites and return a failed ammonia pump module to help NASA better understand the failure mechanism and improve pump designs for future systems. STS-135 will be the 33rd flight of Atlantis, the 37th shuttle mission to the space station, and the 135th and final mission of NASA's Space Shuttle Program. For more information visit, www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts135/index.html. Photo credit: NASA/Frankie Martin

KSC-2011-5469

NASA Image and Video Library

2011-07-08

CAPE CANAVERAL, Fla. -- At the Banana River Creek VIP viewing area at NASA's Kennedy Space Center in Florida, spectators watch the countdown clock as liftoff of space shuttle Atlantis' STS-135 mission to the International Space Station ticks down to the last few seconds. Atlantis with its crew of four; Commander Chris Ferguson, Pilot Doug Hurley, Mission Specialists Sandy Magnus and Rex Walheim, lifted off at 11:29 a.m. EDT on July 8, 2011 to deliver the Raffaello multi-purpose logistics module packed with supplies and spare parts for the International Space Station. Atlantis also will fly the Robotic Refueling Mission experiment that will investigate the potential for robotically refueling existing satellites in orbit. In addition, Atlantis will return with a failed ammonia pump module to help NASA better understand the failure mechanism and improve pump designs for future systems. STS-135 is the 33rd flight of Atlantis, the 37th shuttle mission to the space station, and the 135th and final mission of NASA's Space Shuttle Program. For more information, visit www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts135/index.html. Photo credit: NASA/Chad Baumer

KSC-2011-5053

NASA Image and Video Library

2011-07-05

CAPE CANAVERAL, Fla. -- In Firing Room 4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch team members took their posts at about 12:30 p.m. EDT, July 5 to prepare for space shuttle Atlantis' STS-135 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 1 p.m. Atlantis and its crew of four are scheduled to lift off at 11:26 a.m. EDT on July 8 to deliver the Raffaello multi-purpose logistics module packed with supplies and spare parts to the station. The STS-135 mission also will fly a system to investigate the potential for robotically refueling existing satellites and return a failed ammonia pump module to help NASA better understand the failure mechanism and improve pump designs for future systems. STS-135 will be the 33rd flight of Atlantis, the 37th shuttle mission to the space station, and the 135th and final mission of NASA's Space Shuttle Program. For more information visit, www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts135/index.html. Photo credit: NASA/Frankie Martin

KSC-2011-5052

NASA Image and Video Library

2011-07-05

CAPE CANAVERAL, Fla. -- In Firing Room 4 in the Launch Control Center at NASA's Kennedy Space Center in Florida, launch team members took their posts at about 12:30 p.m. EDT, July 5 to prepare for space shuttle Atlantis' STS-135 mission to the International Space Station. The countdown clock began ticking backward from the T-43 hour mark at 1 p.m. Atlantis and its crew of four are scheduled to lift off at 11:26 a.m. EDT on July 8 to deliver the Raffaello multi-purpose logistics module packed with supplies and spare parts to the station. The STS-135 mission also will fly a system to investigate the potential for robotically refueling existing satellites and return a failed ammonia pump module to help NASA better understand the failure mechanism and improve pump designs for future systems. STS-135 will be the 33rd flight of Atlantis, the 37th shuttle mission to the space station, and the 135th and final mission of NASA's Space Shuttle Program. For more information visit, www.nasa.gov/mission_pages/shuttle/shuttlemissions/sts135/index.html. Photo credit: NASA/Frankie Martin

KSC-98pc1792

NASA Image and Video Library

1998-12-04

KENNEDY SPACE CENTER, Fla. -- As the Space Shuttle Endeavour lifts off from Launch Pad 39A on Mission STS-88, several fish believed to be mullet (at center left) "launch" themselves out of the water from one of the waterways around the pad. Liftoff of the first U.S. mission dedicated to the assembly of the International Space Station was at 3:35:34 a.m. EST on Dec. 4. During the nearly 12-day mission, the six-member crew will mate in space the first two elements of the International Space Station the already-orbiting Zarya control module with the Unity connecting module carried by Endeavour. Crew members are Commander Robert D. Cabana, Pilot Frederick W. "Rick" Sturckow, and Mission Specialists Nancy J. Currie, Jerry L. Ross, James H. Newman and Sergei Konstantinovich Krikalev, a Russian cosmonaut. This was the second launch attempt for STS-88. The first one on Dec. 3 was scrubbed when launch controllers, following an assessment of a suspect hydraulic system, were unable to resume the countdown clock in time to launch within the remaining launch window

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Operation Project Engineer Rommel Rubio monitors operations from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson follows operations at her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson stands next to her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Master console operator David Walsh monitors operations from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Senior NASA Test Director Jeff Spaulding monitors operations from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson follows operations at her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission-1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

KSC-08pd0579

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- (From top) STS-123 Mission Specialists Mike Foreman, Takao Doi and Garrett Reisman are in their seats in space shuttle Endeavour to participate in a simulated launch countdown. The countdown is the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

Infrared spectrometry studies: Spectral digital data acquisition system (1971 version)

NASA Technical Reports Server (NTRS)

Lu, L.; Lyon, R. J. P.

1971-01-01

The construction of the Stanford Spectral Digital Data Acquisition System is described. The objective of the system is to record both the spectral distribution of incoming radiation from the rock samples measured by the spectroradiometer (Exotech Model 10-34 Circular Variable Filter Infrared Spectroradiometer) together with other weather information. This system is designed for both laboratory and field measurement programs. The multichannel inputs (8 channels) of the system are as follows: Ch 1 the Spectro-radiometer, Ch 2 the radiometer (PRT-5), and Ch 3 to Ch 8 for the weather information. The system records data from channel 1 and channel 2 alternately for 48 times, before a fast sweep across the six weather channels, to form a single scan in the scan counter. The operation is illustrated in a block diagram, and the theory of operation is described. The outputs are written on a 7-track magnetic tape with IBM compatible form. The format of the tape and the playback computer programs are included. The micro-pac digital modules and a CIPHER model 70 tape recorder (Cipher Data Products) are used. One of the major characteristics of this system is that it is externally clocked by the spectroradiometer instead of taking data at intervals of various wavelengths by using internal-clocking.

Developing measures of fatigue using an alcohol comparison to validate the effects of fatigue on performance.

PubMed

Williamson, A M; Feyer, A M; Mattick, R P; Friswell, R; Finlay-Brown, S

2001-05-01

The effects of 28 h of sleep deprivation were compared with varying doses of alcohol up to 0.1% blood alcohol concentration (BAC) in the same subjects. The study was conducted in the laboratory. Twenty long-haul truck drivers and 19 people not employed as professional drivers acted as subjects. Tests were selected that were likely to be affected by fatigue, including simple reaction time, unstable tracking, dual task, Mackworth clock vigilance test, symbol digit coding, visual search, sequential spatial memory and logical reasoning. While performance effects were seen due to alcohol for all tests, sleep deprivation affected performance on most tests, but had no effect on performance on the visual search and logical reasoning tests. Some tests showed evidence of a circadian rhythm effect on performance, in particular, simple reaction time, dual task, Mackworth clock vigilance, and symbol digit coding, but only for response speed and not response accuracy. Drivers were slower but more accurate than controls on the symbol digit test, suggesting that they took a more conservative approach to performance of this test. This study demonstrated which tests are most sensitive to sleep deprivation and fatigue. The study therefore has established a set of tests that can be used in evaluations of fatigue and fatigue countermeasures.

Synchronous radio-frequency FM signal generator using direct digital synthesizers

NASA Astrophysics Data System (ADS)

Arablu, Masoud; Kafashi, Sajad; Smith, Stuart T.

2018-04-01

A novel Radio-Frequency Frequency-Modulated (RF-FM) signal generation method is introduced and a prototype circuit developed to evaluate its functionality and performance. The RF-FM signal generator uses a modulated, voltage-controlled time delay to correspondingly modulate the phase of a 10 MHz sinusoidal reference signal. This modulated reference signal is, in turn, used to clock a Direct Digital Synthesizer (DDS) circuit resulting in an FM signal at its output. The modulating signal that is input to the voltage-controlled time delay circuit is generated by another DDS that is synchronously clocked by the same 10 MHz sine wave signal before modulation. As a consequence, all of the digital components are timed from a single sine wave oscillator that forms the basis of all timing. The resultant output signal comprises a center, or carrier, frequency plus a series of phase-synchronized sidebands having exact integer harmonic frequency separation. In this study, carrier frequencies ranging from 10 MHz to 70 MHz are generated with modulation frequencies ranging from 10 kHz to 300 kHz. The captured spectra show that the FM signal characteristics, amplitude and phase, of the sidebands and the modulation depth are consistent with the Jacobi-Anger expansion for modulated harmonic signals.

Optical timing receiver for the NASA laser ranging system. Part 2: High precision time interval digitizer

NASA Technical Reports Server (NTRS)

Leskovar, B.; Turko, B.

1977-01-01

The development of a high precision time interval digitizer is described. The time digitizer is a 10 psec resolution stop watch covering a range of up to 340 msec. The measured time interval is determined as a separation between leading edges of a pair of pulses applied externally to the start input and the stop input of the digitizer. Employing an interpolation techniques and a 50 MHz high precision master oscillator, the equivalent of a 100 GHz clock frequency standard is achieved. Absolute accuracy and stability of the digitizer are determined by the external 50 MHz master oscillator, which serves as a standard time marker. The start and stop pulses are fast 1 nsec rise time signals, according to the Nuclear Instrument means of tunnel diode discriminators. Firing level of the discriminator define start and stop points between which the time interval is digitized.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

PubMed

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Master Console Operators Andrea Oneill, left and David Walsh, monitor operations from their positions in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Space Launch System and Orion launch team engineers and managers monitor operations from their console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Alex Higgins, a liquid hydrogen operations engineer with Jacobs, monitors operations from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

KSC-05PD-0894

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. STS-114 Commander Eileen Collins places a mission patch on an M-113 armored personnel carrier during Terminal Countdown Demonstration Test (TCDT) activities. Looking on are Mission Specialists Andrew Thomas, Stephen Robinson and Soichi Noguchi, who is with the Japan Aerospace Exploration Agency.. The crew is at KSC for Terminal Countdown Demonstration Test (TCDT) activities. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is designated the first Return to Flight mission, with a launch window extending from July 13 to July 31.

Unpredictability and the transmission of numbers

NASA Astrophysics Data System (ADS)

Myers, John M.; Madjid, F. Hadi

2016-03-01

Curiously overlooked in physics is its dependence on the transmission of numbers. For example, the transmission of numerical clock readings is implicit in the concept of a coordinate system. The transmission of numbers and other logical distinctions is often achieved over a computer-mediated communications network in the face of an unpredictable environment. By unpredictable we mean something stronger than the spread of probabilities over given possible outcomes, namely an opening to unforeseeable possibilities. Unpredictability, until now overlooked in theoretical physics, makes the transmission of numbers interesting. Based on recent proofs within quantum theory that provide a theoretical foundation to unpredictability, here we show how regularities in physics rest on a background of channels over which numbers are transmitted. As is known to engineers of digital communications, numerical transmissions depend on coordination reminiscent of the cycle of throwing and catching by players tossing a ball back and forth. In digital communications, the players are computers, and the required coordination involves unpredictably adjusting "live clocks" that step these computers through phases of a cycle. We show how this phasing, which we call logical synchronization, constrains number-carrying networks, and, if a spacetime manifold in invoked, put "stripes" on spacetime. Via its logically synchronized channels, a network of live clocks serves as a reference against which to locate events. Such a network in any case underpins a coordinate frame, and in some cases the direct use of a network can be tailored to investigate an unpredictable environment. Examples include explorations of gravitational variations near Earth.

A scheme for synchronizing clocks connected by a packet communication network

NASA Astrophysics Data System (ADS)

dos Santos, R. V.; Monteiro, L. H. A.

2012-07-01

Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. Here we propose an adaptive clock recovery scheme able of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop. The scheme performance is evaluated via numerical simulations performed by using realistic parameter values.

A 1024×768-12μm Digital ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim

2017-02-01

This paper reports the development of a new digital microbolometer Readout Integrated Circuit (D-ROIC), called MT10212BD. It has a format of 1024 × 768 (XGA) and a pixel pitch of 12μm. MT10212BD is Mikro Tasarim's second 12μm pitch microbolometer ROIC, which is developed specifically for surface micro machined microbolometer detector arrays with small pixel pitch using high-TCR pixel materials, such as VOx and a Si. MT10212BD has an alldigital system on-chip architecture, which generates programmable timing and biasing, and performs 14-bit analog to digital conversion (ADC). The signal processing chain in the ROIC is composed of pixel bias circuitry, integrator based programmable gain amplifier followed by column parallel ADC circuitry. MT10212BD has a serial programming interface that can be used to configure the programmable ROIC features and to load the Non-Uniformity-Correction (NUC) date to the ROIC. MT10212BD has a total of 8 high-speed serial digital video outputs, which can be programmed to operate in the 2, 4, and 8-output modes and can support frames rates above 60 fps. The high-speed serial digital outputs supports data rates as high as 400 Mega-bits/s, when operated at 50 MHz system clock frequency. There is an on-chip phase-locked-loop (PLL) based timing circuitry to generate the high speed clocks used in the ROIC. The ROIC is designed to support pixel resistance values ranging from 30KΩ to 90kΩ, with a nominal value of 60KΩ. The ROIC has a globally programmable gain in the column readout, which can be adjusted based on the detector resistance value.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Space Launch System Test Conductors Roberta Wyrick, left, and Tracy Parks, both with Jacobs, NASA's Test and Operations Support Contractor, monitor operations from their consoles in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Master Console Operator Jennifer Tschanz, left, and Master Console Operator Diego Diaz, both of Jacobs, monitor operations from their consoles in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson, above, confers with Senior NASA Test Director Jeff Spaulding, left, and Chief NASA Test Director Jeremy Graeber in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Jacobs Test Project Engineer Don Vinton, left and NASA Operations Project Engineer Doug Robertson, monitor operations from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Test Project Engineer Rick Brown, left, and Master Console Operator Jason Robinson, both with Jacobs, monitor operations from their consoles in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Roberta Wyrick, spacecraft test conductor with Jacobs, NASA's Test and Operations Support Contractor, monitors operations from her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Main Propulsion System Engineers Krista Riggs, left, and Joe Pavicic, both with Jacobs, monitor operations from their consoles in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

Liquid Oxygen Systems Engineer Quinten Jones, left and Liquid Oxygen Systems Engineer Andrew "Kody" Smitherman, both of Jacobs, monitor operation from his position in Firing Room 1 at the Kennedy Space Center's Launch Control Center during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

Accurate frequency and time dissemination in the optical domain

NASA Astrophysics Data System (ADS)

Khabarova, K. Yu; Kalganova, E. S.; Kolachevsky, N. N.

2018-02-01

The development of the optical frequency comb technique has enabled a wide use of atomic optical clocks by allowing frequency conversion from the optical to the radio frequency range. Today, the fractional instability of such clocks has reached the record eighteen-digit level, two orders of magnitude better than for cesium fountains representing the primary frequency standard. This is paralleled by the development of techniques for transferring accurate time and optical frequency signals, including fiber links. With this technology, the fractional instability of transferred frequency can be lowered to below 10‑18 with an averaging time of 1000 s for a 1000 km optical link. At a distance of 500 km, a time signal uncertainty of 250 ps has been achieved. Optical links allow comparing optical clocks and creating a synchronized time and frequency standard network at a new level of precision. Prospects for solving new problems arise, including the determination of the gravitational potential, the measurement of the continental Sagnac effect, and precise tests of fundamental theories.

The missing dimension: the relevance of people's conception of time.

PubMed

Norgate, Sarah H; Davies, Nigel; Speed, Chris; Cherrett, Tom; Dickinson, Janet

2014-02-01

While a timely conceptual innovation for the digital age, the "map" proposed by Bentley et al. would benefit from strengthening through the inclusion of a non-clock-time perspective. In this way, there could be new hypotheses developed which could be applied and tested relevant to more diverse societies, cultures, and individuals.

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

A low power biomedical signal processor ASIC based on hardware software codesign.

PubMed

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

15 pixels digital autocorrelation spectrometer system

NASA Astrophysics Data System (ADS)

Lee, Changhoon; Kim, Hyo-Ryung; Kim, Kwang-Dong; Chung, Mun-Hee; Timoc, C.

2006-06-01

In this paper describes the system configuration and the some performance test results of the 15 pixels digital autocorrelation spectrometer to be used at the Taeduk Radio Astronomy Observatory (TRAO) of Korea. This autocorrelation spectrometer instrument enclosed in a 3-slot VXI module and controlled via a USB port by a backend PC. This spectrometer system consists of the 4 band-pass filters unit, the digitizer, the 512 lags correlator, the clock distribution unit, and USB controller. And here we describe the frequency accuracy and the root-mean-square noise characteristic of this spectrometer. After some calibration procedure, this spectrometer can be use as the back-end system at TRAO for the 3x5 focal plane array receivers.

Effect of various features on the life cycle cost of the timing/synchronization subsystem of the DCS digital communications network

NASA Technical Reports Server (NTRS)

Kimsey, D. B.

1978-01-01

The effect on the life cycle cost of the timing subsystem was examined, when these optional features were included in various combinations. The features included mutual control, directed control, double-ended reference links, independence of clock error measurement and correction, phase reference combining, self-organization, smoothing for link and nodal dropouts, unequal reference weightings, and a master in a mutual control network. An overall design of a microprocessor-based timing subsystem was formulated. The microprocessor (8080) implements the digital filter portion of a digital phase locked loop, as well as other control functions such as organization of the network through communication with processors at neighboring nodes.

Hydraulic logic gates: building a digital water computer

NASA Astrophysics Data System (ADS)

Taberlet, Nicolas; Marsal, Quentin; Ferrand, Jérémy; Plihon, Nicolas

2018-03-01

In this article, we propose an easy-to-build hydraulic machine which serves as a digital binary computer. We first explain how an elementary adder can be built from test tubes and pipes (a cup filled with water representing a 1, and empty cup a 0). Using a siphon and a slow drain, the proposed setup combines AND and XOR logical gates in a single device which can add two binary digits. We then show how these elementary units can be combined to construct a full 4-bit adder. The sequencing of the computation is discussed and a water clock can be incorporated so that the machine can run without any exterior intervention.

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

NASA Technical Reports Server (NTRS)

Shu, Peter; Waczynski, Augustyn; Kan, Emily; Wen, Yiting; Rosenberry, Robert

2012-01-01

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

KSC-99pp1331

NASA Image and Video Library

1999-11-16

In the bunker at Launch Pad 39B, STS-103 Mission Specialist Jean-François Clervoy of France, who is with the European Space Agency (ESA), tries on an oxygen mask during Terminal Countdown Demonstration Test (TCDT) activities. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. Other crew members taking part are Commander Curtis L. Brown Jr. and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), plus Claude Nicollier of Switzerland, who is also with ESA. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

STS-103 MS Clervoy tries on oxygen mask

NASA Technical Reports Server (NTRS)

1999-01-01

In the bunker at Launch Pad 39B, STS-103 Mission Specialist Jean-Frangois Clervoy of France, who is with the European Space Agency (ESA), tries on an oxygen mask during Terminal Countdown Demonstration Test (TCDT) activities. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. Other crew members taking part are Commander Curtis L. Brown Jr. and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), plus Claude Nicollier of Switzerland, who is also with ESA. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

KSC-99pp1332

NASA Image and Video Library

1999-11-16

In the bunker at Launch Pad 39B, STS-103 Pilot Scott J. Kelly (left) and Mission Specialist John M. Grunsfeld (Ph.D.) (right) try on oxygen masks during Terminal Countdown Demonstration Test (TCDT) activities. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. Other crew members taking part are Commander Curtis L. Brown Jr. and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), and Jean-François Clervoy of France and Claude Nicollier of Switzerland, who are with the European Space Agency. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

KSC-99pp1342

NASA Image and Video Library

1999-11-17

Taking a break during emergency egress training at Launch Pad 39B are (left to right) STS-103 Mission Specialists Jean-François Clervoy of France, Claude Nicollier of Switzerland, Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists John M. Grunsfeld (Ph.D.), C. Michael Foale (Ph.D.) and Steven L. Smith. Clervoy and Nicollier are with the European Space Agency. The training is part of Terminal Countdown Demonstration Test (TCDT) activities that also include opportunities to inspect the mission payloads in the orbiter's payload bay and simulated countdown exercises. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

KSC-99pp1347

NASA Image and Video Library

1999-11-17

STS-103 Mission Commander Curtis L. Brown Jr. sits inside orbiter Discovery waiting for the start of a simulated countdown exercise. The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), Jean-François Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

The trigger card system for the MAJORANA DEMONSTRATOR

NASA Astrophysics Data System (ADS)

Thompson, William; Anderson, John; Howe, Mark; Meijer, Sam; Wilkerson, John; Majorana Collaboration

2014-09-01

The aim of the MAJORANA DEMONSTRATOR is to demonstrate the feasibility of providing low enough background levels to search for neutrinoless double-beta decay (0 νββ) in an array of germanium detectors enriched to 87% in 76Ge. Currently, it is unknown if this decay process occurs; however, observation of such a decay process would show that lepton number is violated, confirm that neutrinos are Majorana particles, and yield information on the absolute mass scale of the neutrino. With current experimental results indicating a half-life greater than 2 x 1025 years for this decay, the minimization of background events is of critical importance. Utilizing time correlation, coincidence testing is able to reject multi-detector events that may otherwise be mistaken for 0 νββ when viewed independently. Here, we present both the hardware and software of the trigger card system, which provides a common clock to all digitizers and the muon veto system, thereby enabling the rejection of background events through coincidence testing. Current experimental results demonstrate the accuracy of the distributed clock to be within two clock pulses (20 ns) across all system components. A test system is used to validate the data acquisition system. The aim of the MAJORANA DEMONSTRATOR is to demonstrate the feasibility of providing low enough background levels to search for neutrinoless double-beta decay (0 νββ) in an array of germanium detectors enriched to 87% in 76Ge. Currently, it is unknown if this decay process occurs; however, observation of such a decay process would show that lepton number is violated, confirm that neutrinos are Majorana particles, and yield information on the absolute mass scale of the neutrino. With current experimental results indicating a half-life greater than 2 x 1025 years for this decay, the minimization of background events is of critical importance. Utilizing time correlation, coincidence testing is able to reject multi-detector events that may otherwise be mistaken for 0 νββ when viewed independently. Here, we present both the hardware and software of the trigger card system, which provides a common clock to all digitizers and the muon veto system, thereby enabling the rejection of background events through coincidence testing. Current experimental results demonstrate the accuracy of the distributed clock to be within two clock pulses (20 ns) across all system components. A test system is used to validate the data acquisition system. We acknowledge support from the Office of Nuclear Physics in the DOE Office of Science, the Particle Astrophysics and REU Programs of the NSF, and the Sanford Underground Research Laboratory.

STS-85 crew Tryggvason and Robinson during TCDT

NASA Technical Reports Server (NTRS)

1997-01-01

STS-85 Payload Specialist Bjarni V. Tryggvason and Mission Specialist Stephen K. Robinson go through countdown procedures aboard the Space Shuttle orbiter Discovery during Terminal Countdown Demonstration Test (TCDT) activities for that mission. The TCDT includes a simulation of the final launch countdown. The primary payload aboard the Space Shuttle orbiter Discovery is the Cryogenic Infrared Spectrometers and Telescopes for the Atmosphere-2 (CRISTA-SPAS- 2). Other STS-85 payloads include the Manipulator Flight Demonstration (MFD), and Technology Applications and Science-1 (TAS-1) and International Extreme Ultraviolet Hitchhiker-2 (IEH-2) experiments.

KSC00pp1374

NASA Image and Video Library

2000-09-15

KENNEDY SPACE CENTER, FLA. -- STS-92 Commander Brian Duffy is seated at the controls of Discovery to take part in a simulated countdown. The countdown is part of Terminal Countdown Demonstration Test (TCDT) activities that he and other crew members have been performing. STS-92 is scheduled to launch Oct. 5 at 9:38 p.m. EDT on the fifth flight to the International Space Station. It will carry two elements of the Space Station, the Integrated Truss Structure Z1 and the third Pressurized Mating Adapter. The mission is also the 100th flight in the Shuttle program

KSC-00pp1374

NASA Image and Video Library

2000-09-15

KENNEDY SPACE CENTER, FLA. -- STS-92 Commander Brian Duffy is seated at the controls of Discovery to take part in a simulated countdown. The countdown is part of Terminal Countdown Demonstration Test (TCDT) activities that he and other crew members have been performing. STS-92 is scheduled to launch Oct. 5 at 9:38 p.m. EDT on the fifth flight to the International Space Station. It will carry two elements of the Space Station, the Integrated Truss Structure Z1 and the third Pressurized Mating Adapter. The mission is also the 100th flight in the Shuttle program

System and method for simultaneously collecting serial number information from numerous identity tags

DOEpatents

Doty, Michael A.

1997-01-01

A system and method for simultaneously collecting serial number information reports from numerous colliding coded-radio-frequency identity tags. Each tag has a unique multi-digit serial number that is stored in non-volatile RAM. A reader transmits an ASCII coded "D" character on a carrier of about 900 MHz and a power illumination field having a frequency of about 1.6 Ghz. A one MHz tone is modulated on the 1.6 Ghz carrier as a timing clock for a microprocessor in each of the identity tags. Over a thousand such tags may be in the vicinity and each is powered-up and clocked by the 1.6 Ghz power illumination field. Each identity tag looks for the "D" interrogator modulated on the 900 MHz carrier, and each uses a digit of its serial number to time a response. Clear responses received by the reader are repeated for verification. If no verification or a wrong number is received by any identity tag, it uses a second digital together with the first to time out a more extended period for response. Ultimately, the entire serial number will be used in the worst case collision environments; and since the serial numbers are defined as being unique, the final possibility will be successful because a clear time-slot channel will be available.

System and method for simultaneously collecting serial number information from numerous identity tags

DOEpatents

Doty, M.A.

1997-01-07

A system and method are disclosed for simultaneously collecting serial number information reports from numerous colliding coded-radio-frequency identity tags. Each tag has a unique multi-digit serial number that is stored in non-volatile RAM. A reader transmits an ASCII coded ``D`` character on a carrier of about 900 MHz and a power illumination field having a frequency of about 1.6 Ghz. A one MHz tone is modulated on the 1.6 Ghz carrier as a timing clock for a microprocessor in each of the identity tags. Over a thousand such tags may be in the vicinity and each is powered-up and clocked by the 1.6 Ghz power illumination field. Each identity tag looks for the ``D`` interrogator modulated on the 900 MHz carrier, and each uses a digit of its serial number to time a response. Clear responses received by the reader are repeated for verification. If no verification or a wrong number is received by any identity tag, it uses a second digital together with the first to time out a more extended period for response. Ultimately, the entire serial number will be used in the worst case collision environments; and since the serial numbers are defined as being unique, the final possibility will be successful because a clear time-slot channel will be available. 5 figs.

An improved adaptive interpolation clock recovery loop based on phase splitting algorithm for coherent optical communication system

NASA Astrophysics Data System (ADS)

Liu, Xuan; Liu, Bo; Zhang, Li-jia; Xin, Xiang-jun; Zhang, Qi; Wang, Yong-jun; Tian, Qing-hua; Tian, Feng; Mao, Ya-ya

2018-01-01

Traditional clock recovery scheme achieves timing adjustment by digital interpolation, thus recovering the sampling sequence. Based on this, an improved clock recovery architecture joint channel equalization for coherent optical communication system is presented in this paper. The loop is different from the traditional clock recovery. In order to reduce the interpolation error caused by the distortion in the frequency domain of the interpolator and to suppress the spectral mirroring generated by the sampling rate change, the proposed algorithm joint equalization, improves the original interpolator in the loop, along with adaptive filtering, and makes error compensation for the original signals according to the balanced pre-filtering signals. Then the signals are adaptive interpolated through the feedback loop. Furthermore, the phase splitting timing recovery algorithm is adopted in this paper. The time error is calculated according to the improved algorithm when there is no transition between the adjacent symbols, making calculated timing error more accurate. Meanwhile, Carrier coarse synchronization module is placed before the beginning of timing recovery to eliminate the larger frequency offset interference, which effectively adjust the sampling clock phase. In this paper, the simulation results show that the timing error is greatly reduced after the loop is changed. Based on the phase splitting algorithm, the BER and MSE are better than those in the unvaried architecture. In the fiber channel, using MQAM modulation format, after 100 km-transmission of single-mode fiber, especially when ROF(roll-off factor) values tends to 0, the algorithm shows a better clock performance under different ROFs. When SNR values are less than 8, the BER could achieve 10-2 to 10-1 magnitude. Furthermore, the proposed timing recovery is more suitable for the situation with low SNR values.

Distinguishing between evidence and its explanations in the steering of atomic clocks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Myers, John M., E-mail: myers@seas.harvard.edu; Hadi Madjid, F., E-mail: gmadjid@aol.com

2014-11-15

Quantum theory reflects within itself a separation of evidence from explanations. This separation leads to a known proof that: (1) no wave function can be determined uniquely by evidence, and (2) any chosen wave function requires a guess reaching beyond logic to things unforeseeable. Chosen wave functions are encoded into computer-mediated feedback essential to atomic clocks, including clocks that step computers through their phases of computation and clocks in space vehicles that supply evidence of signal propagation explained by hypotheses of spacetimes with metric tensor fields. The propagation of logical symbols from one computer to another requires a shared rhythm—likemore » a bucket brigade. Here we show how hypothesized metric tensors, dependent on guesswork, take part in the logical synchronization by which clocks are steered in rate and position toward aiming points that satisfy phase constraints, thereby linking the physics of signal propagation with the sharing of logical symbols among computers. Recognizing the dependence of the phasing of symbol arrivals on guesses about signal propagation transports logical synchronization from the engineering of digital communications to a discipline essential to physics. Within this discipline we begin to explore questions invisible under any concept of time that fails to acknowledge unforeseeable events. In particular, variation of spacetime curvature is shown to limit the bit rate of logical communication. - Highlights: • Atomic clocks are steered in frequency toward an aiming point. • The aiming point depends on a chosen wave function. • No evidence alone can determine the wave function. • The unknowability of the wave function has implications for spacetime curvature. • Variability in spacetime curvature limits the bit rate of communications.« less

Technicians close hatches on Gemini 11 spacecraft during countdown

NASA Technical Reports Server (NTRS)

1966-01-01

Technicians in the White Room atop Pad 19 prepare to close hatches on the Gemini 11 spacecraft during prelaunch countdown. Inside the spacecraft are Astronauts Charles Conrad Jr., command pilot, and Richard F. Gordon Jr., pilot.

KSC-08pd0594

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- Gathered again on the top level of the fixed service structure, the STS-123 crew poses for a photo after completing the simulated launch countdown. From left are Mission Specialists Rick Linnehan and Robert L. Behnken, Pilot Gregory H. Johnson, Commander Dominic Gorie, and Mission Specialists Mike Foreman, Garrett Reisman and Takao Doi. The countdown was the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

KSC-08pd0557

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- Before the simulated launch countdown in space shuttle Endeavour, the STS-123 crew gathers near the top of the fixed service structure on NASA Kennedy Space Center's Launch Pad 39A. Seen from left are Mission Specialists Rick Linnehan and Robert L. Behnken, Pilot Gregory H. Johnson, Commander Dominic Gorie and Mission Specialists Mike Foreman, Garrett Reisman and Takao Doi. The countdown is the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Jim Grossmann

KSC-08pd0556

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- Before the simulated launch countdown in space shuttle Endeavour, the STS-123 crew gathers near the top of the fixed service structure on NASA Kennedy Space Center's Launch Pad 39A. Seen from left are Mission Specialists Rick Linnehan and Robert L. Behnken, Pilot Gregory H. Johnson, Commander Dominic Gorie and Mission Specialists Mike Foreman, Garrett Reisman and Takao Doi. The countdown is the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Jim Grossmann

Fiber optic cable-based high-resolution, long-distance VGA extenders

NASA Astrophysics Data System (ADS)

Rhee, Jin-Geun; Lee, Iksoo; Kim, Heejoon; Kim, Sungjoon; Koh, Yeon-Wan; Kim, Hoik; Lim, Jiseok; Kim, Chur; Kim, Jungwon

2013-02-01

Remote transfer of high-resolution video information finds more applications in detached display applications for large facilities such as theaters, sports complex, airports, and security facilities. Active optical cables (AOCs) provide a promising approach for enhancing both the transmittable resolution and distance that standard copper-based cables cannot reach. In addition to the standard digital formats such as HDMI, the high-resolution, long-distance transfer of VGA format signals is important for applications where high-resolution analog video ports should be also supported, such as military/defense applications and high-resolution video camera links. In this presentation we present the development of a compressionless, high-resolution (up to WUXGA, 1920x1200), long-distance (up to 2 km) VGA extenders based on serialized technique. We employed asynchronous serial transmission and clock regeneration techniques, which enables lower cost implementation of VGA extenders by removing the necessity for clock transmission and large memory at the receiver. Two 3.125-Gbps transceivers are used in parallel to meet the required maximum video data rate of 6.25 Gbps. As the data are transmitted asynchronously, 24-bit pixel clock time stamp is employed to regenerate video pixel clock accurately at the receiver side. In parallel to the video information, stereo audio and RS-232 control signals are transmitted as well.

Clock distribution system for digital computers

DOEpatents

Wyman, Robert H.; Loomis, Jr., Herschel H.

1981-01-01

Apparatus for eliminating, in each clock distribution amplifier of a clock distribution system, sequential pulse catch-up error due to one pulse "overtaking" a prior clock pulse. The apparatus includes timing means to produce a periodic electromagnetic signal with a fundamental frequency having a fundamental frequency component V'.sub.01 (t); an array of N signal characteristic detector means, with detector means No. 1 receiving the timing means signal and producing a change-of-state signal V.sub.1 (t) in response to receipt of a signal above a predetermined threshold; N substantially identical filter means, one filter means being operatively associated with each detector means, for receiving the change-of-state signal V.sub.n (t) and producing a modified change-of-state signal V'.sub.n (t) (n=1, . . . , N) having a fundamental frequency component that is substantially proportional to V'.sub.01 (t-.theta..sub.n (t) with a cumulative phase shift .theta..sub.n (t) having a time derivative that may be made uniformly and arbitrarily small; and with the detector means n+1 (1.ltoreq.n

Enhancing Observability of Signal Composition and Error Signatures During Dynamic SEE Analog to Digital Device Testing

NASA Technical Reports Server (NTRS)

Berg, M.; Buchner, S.; Kim, H.; Friendlich, M.; Perez, C.; Phan, A.; Seidleck, C.; LaBel, K.; Kruckmeyer, K.

2010-01-01

A novel approach to dynamic SEE ADC testing is presented. The benefits of this test scheme versus prior implemented techniques include the ability to observe ADC SEE errors that are in the form of phase shifts, single bit upsets, bursts of disrupted signal composition, and device clock loss.

Non-Intrusive Pressure/Multipurpose Sensor and Method

NASA Technical Reports Server (NTRS)

Smith, William C. (Inventor)

2001-01-01

Method and apparatus are provided for determining pressure using a non-intrusive sensor that is easily attachable to the plumbing of a pressurized system. A bent mode implementation and a hoop mode implementation of the invention are disclosed. Each of these implementations is able to nonintrusively measure pressure while fluid is flowing. As well, each implementation may be used to measure mass flow rate simultaneously with pressure. An ultra low noise control system is provided for making pressure measurements during gas flow. The control system includes two tunable digital bandpass filters with center frequencies that are responsive to a clock frequency. The clock frequency is divided by a factor of N to produce a driving vibrational signal for resonating a metal sensor section.

National health policy-makers’ views on the clarity and utility of Countdown to 2015 country profiles and reports: findings from two exploratory qualitative studies

PubMed Central

2014-01-01

Background The use of sets of indicators to assess progress has become commonplace in the global health arena. Exploratory research has suggested that indicators used for global monitoring purposes can play a role in national policy-making, however, the mechanisms through which this occurs are poorly understood. This article reports findings from two qualitative studies that aimed to explore national policy-makers’ interpretation and use of indicators from country profiles and reports developed by Countdown to 2015. Methods An initial study aimed at exploring comprehension of Countdown data was conducted at the 2010 joint Women Deliver/Countdown conference. A second study was conducted at the 64th World Health Assembly in 2011, specifically targeting national policy-makers. Semi-structured interviews were carried out with 29 and 22 participants, respectively, at each event. Participants were asked about their understanding of specific graphs and indicators used or proposed for use in Countdown country profiles, and their perception of how such data can inform national policy-making. Responses were categorised using a framework analysis. Results Respondents in both studies acknowledged the importance of the profiles for tracking progress on key health indicators in and across countries, noting that they could be used to highlight changes in coverage, possible directions for future policy, for lobbying finance ministers to increase resources for health, and to stimulate competition between neighbouring or socioeconomically similar countries. However, some respondents raised questions about discrepancies between global estimates and data produced by national governments, and some struggled to understand the profile graphs shown in the absence of explanatory text. Some respondents reported that use of Countdown data in national policy-making was constrained by limited awareness of the initiative, insufficient detail in the country profiles to inform policy, and the absence of indicators felt to be more appropriate to their own country contexts. Conclusions The two studies emphasise the need for country consultations to ensure that national policy-makers understand how to interpret and use tools like the Countdown profile for planning purposes. They make clear the value of qualitative research for refining tools used to promote accountability, and the need for country level Countdown-like processes. PMID:25128385

Superconductor Digital-RF Receiver Systems

NASA Astrophysics Data System (ADS)

Mukhanov, Oleg A.; Kirichenko, Dmitri; Vernik, Igor V.; Filippov, Timur V.; Kirichenko, Alexander; Webber, Robert; Dotsenko, Vladimir; Talalaevskii, Andrei; Tang, Jia Cao; Sahu, Anubhav; Shevchenko, Pavel; Miller, Robert; Kaplan, Steven B.; Sarwana, Saad; Gupta, Deepnarayan

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ˜30GHz clock frequencies.

Digital second-order phase-locked loop

NASA Technical Reports Server (NTRS)

Holes, J. K.; Carl, C.; Tegnelia, C. R. (Inventor)

1973-01-01

A digital second-order phase-locked loop is disclosed in which a counter driven by a stable clock pulse source is used to generate a reference waveform of the same frequency as an incoming waveform, and to sample the incoming waveform at zero-crossover points. The samples are converted to digital form and accumulated over M cycles, reversing the sign of every second sample. After every M cycles, the accumulated value of samples is hard limited to a value SGN = + or - 1 and multiplied by a value delta sub 1 equal to a number of n sub 1 of fractions of a cycle. An error signal is used to advance or retard the counter according to the sign of the sum by an amount equal to the sum.

Getting the Bigger Picture With Digital Surveillance

NASA Technical Reports Server (NTRS)

2002-01-01

Through a Space Act Agreement, Diebold, Inc., acquired the exclusive rights to Glenn Research Center's patented video observation technology, originally designed to accelerate video image analysis for various ongoing and future space applications. Diebold implemented the technology into its AccuTrack digital, color video recorder, a state-of- the-art surveillance product that uses motion detection for around-the- clock monitoring. AccuTrack captures digitally signed images and transaction data in real-time. This process replaces the onerous tasks involved in operating a VCR-based surveillance system, and subsequently eliminates the need for central viewing and tape archiving locations altogether. AccuTrack can monitor an entire bank facility, including four automated teller machines, multiple teller lines, and new account areas, all from one central location.

Digital communication system

NASA Technical Reports Server (NTRS)

Monford, L. G., Jr. (Inventor)

1974-01-01

A digital communication system is reported for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup.

DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

NASA Technical Reports Server (NTRS)

Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

2013-01-01

The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

STS-71 Pilot Charles J. Precort arrival in T-38

NASA Technical Reports Server (NTRS)

1995-01-01

STS-71 Pilot Charles J. Precourt arrives at the KSC Shuttle Landing Facility in one of the T-38 aircraft traditionally flown by the astronaut corps. The seven STS-71 crew members flew into KSC from Johnson Space Center as final preparations are under way toward the scheduled liftoff on June 23 of the Space Shuttle Atlantis on the first mission to dock with the Russian Space Station Mir. KSC-95EC-870 - Mir 19 Flight Engineer Nikolai M. Budarin arrives at KSC Mir 19 Flight Engineer Nikolai M. Budarin hitches a ride with STS-71 Pilot Charles J. Precourt in a T-38. Budarin, Precourt and the rest of the STS-71 crew arrived at KSC's Shuttle Landing Facility the same day the countdown clock began ticking toward a scheduled liftoff on Friday, June 23. During the historic flight of the Space Shuttle Atlantis on STS- 71, the crew will perform the first U.S. docking with the Russian Space Station Mir. Budarin and Mir 19 Mission Commander Anatoly Solovyev will transfer to Mir during the flight, and the three crew members currently on Mir will return to Earth in the orbiter.

Advanced GPS Technologies (AGT)

DTIC Science & Technology

2015-05-01

Distribution A GPS Ill Developmental Optical Clock Deployable Antenna Concept 3 \\.J Science and Technology for GPS •:• Spacecraft • AFRL has funded a...Digital Waveform Generators New antenna concepts Supporting electronics Algorithms and new signal combining methods Satellite bus technologies...GPS Military High Gain Antenna Developing Options for Ground Testing 1) Deployable phased array • Low profile element • High efficiency phase

Self-organized synchronization of digital phase-locked loops with delayed coupling in theory and experiment

PubMed Central

Wetzel, Lucas; Jörg, David J.; Pollakis, Alexandros; Rave, Wolfgang; Fettweis, Gerhard; Jülicher, Frank

2017-01-01

Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common time reference is key to coordinate signal transmission and processing. Here we show how the self-organized synchronization of mutually coupled digital phase-locked loops (DPLLs) can provide robust clocking in large-scale systems. We develop a nonlinear phase description of individual and coupled DPLLs that takes into account filter impulse responses and delayed signal transmission. Our phase model permits analytical expressions for the collective frequencies of synchronized states, the analysis of stability properties and the time scale of synchronization. In particular, we find that signal filtering introduces stability transitions that are not found in systems without filtering. To test our theoretical predictions, we designed and carried out experiments using networks of off-the-shelf DPLL integrated circuitry. We show that the phase model can quantitatively predict the existence, frequency, and stability of synchronized states. Our results demonstrate that mutually delay-coupled DPLLs can provide robust and self-organized synchronous clocking in electronic systems. PMID:28207779

Design of the biosonar simulator for dolphin's clicks waveform reproduction

NASA Astrophysics Data System (ADS)

Ishii, Ken; Akamatsu, Tomonari; Hatakeyama, Yoshimi

1992-03-01

The emitted clicks of Dall's porpoises consist of a pulse train of burst signals with an ultrasonic carrier frequency. The authors have designed a biosonar simulator to reproduce the waveforms associated with a dolphin's clicks underwater. The total reproduction system consists of a click signal acquisition block, a waveform analysis block, a memory unit, a click simulator, and a underwater, ultrasonic wave transmitter. In operation, data stored in an EPROM (Erasable Programmable Read Only Memory) are read out sequentially by a fast clock and converted to analog output signals. Then an ultrasonic power amplifier reproduces these signals through a transmitter. The click signal replaying block is referred to as the BSS (Biosonar Simulator). This is what simulates the clicks. The details of the BSS are described in this report. A unit waveform is defined. The waveform is divided into a burst period and a waiting period. Clicks are a sequence based on a unit waveform, and digital data are sequentially read out from an EPROM of waveform data. The basic parameters of the BSS are as follows: (1) reading clock, 100 ns to 25.4 microseconds; (2) number of reading clock, 34 to 1024 times; (3) counter clock in a waiting period, 100 ns to 25.4 microseconds; (4) number of counter clock, zero to 16,777,215 times; (5) number of burst/waiting repetition cycle, one to 128 times; and (6) transmission level adjustment by a programmable attenuator, zero to 86.5 dB. These basic functions enable the BSS to replay clicks of Dall's porpoise precisely.

STS-5 crewmembers take part in countdown demonstration test (CDDT)

NASA Technical Reports Server (NTRS)

1982-01-01

STS-5 crewmembers take part in countdown demonstration test (CDDT) at the launch pad 39, Kennedy Space Center. They are, left to right, Vance D. Brand, commander; William B. Lenoir, mission specialist; Robert F. Overmyer, pilot; and Joseph P. Allen, mission specialist.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Konz, Daniel W. (Inventor); Winkelmann, Joseph P. (Inventor); Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor)

2007-01-01

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. In some embodiments, network device interfaces associated with different data channels coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Network device interface for digitally interfacing data channels to a controller via a network

NASA Technical Reports Server (NTRS)

Ellerbrock, Philip J. (Inventor); Grant, Robert L. (Inventor); Winkelmann, Joseph P. (Inventor); Konz, Daniel W. (Inventor)

2009-01-01

A communications system and method are provided for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. Network device interfaces associated with different data channels can coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Increased Diagnostic Accuracy of Digital vs. Conventional Clock Drawing Test for Discrimination of Patients in the Early Course of Alzheimer's Disease from Cognitively Healthy Individuals.

PubMed

Müller, Stephan; Preische, Oliver; Heymann, Petra; Elbing, Ulrich; Laske, Christoph

2017-01-01

The conventional Clock Drawing Test (cCDT) is a rapid and inexpensive screening tool for detection of moderate and severe dementia. However, its usage is limited due to poor diagnostic accuracy especially in patients with mild cognitive impairment (MCI). The diagnostic value of a newly developed digital Clock Drawing Test (dCDT) was evaluated and compared with the cCDT in 20 patients with early dementia due to AD (eDAT), 30 patients with amnestic MCI (aMCI) and 20 cognitively healthy controls (HCs). Parameters assessed by dCDT were time while transitioning the stylus from one stroke to the next above the surface (i.e., time-in-air), time the stylus produced a visible stroke (i.e., time-on-surface) and total-time during clock drawing. Receiver-operating characteristic (ROC) curves were calculated and logistic regression analyses have been conducted for statistical analysis. Using dCDT, time-in-air was significantly increased in eDAT (70965.8 ms) compared to aMCI (54073.7 ms; p = 0.027) and HC (32315.6 ms; p < 0.001). In addition, time-in-air was significantly longer in patients with aMCI compared to HC ( p = 0.003), even in the aMCI group with normal cCDT score (54141.8 ms; p < 0.001). Time-in-air using dCDT allowed discrimination of patients with aMCI from HCs with a sensitivity of 81.3% and a specificity of 72.2% while cCDT scoring revealed a sensitivity of 62.5% and a specificity of 83.3%. Most interestingly, time-in-air allowed even discrimination of aMCI patients with normal cCDT scores (80% from all aMCI patients) from HCs with a clinically relevant sensitivity of 80.8% and a specificity of 77.8%. A combination of dCDT variables and cCDT scores did not improve the discrimination of patients with aMCI from HC. In conclusion, assessment of time-in-air using dCDT yielded a higher diagnostic accuracy for discrimination of aMCI patients from HCs than the use of cCDT even in those aMCI patients with normal cCDT scores. Modern digitizing devices offer the opportunity to measure subtle changes of visuo-constructive demands and executive functions that may be used as a fast and easy to perform screening instrument for the early detection of cognitive impairment in primary care.

Increased Diagnostic Accuracy of Digital vs. Conventional Clock Drawing Test for Discrimination of Patients in the Early Course of Alzheimer’s Disease from Cognitively Healthy Individuals

PubMed Central

Müller, Stephan; Preische, Oliver; Heymann, Petra; Elbing, Ulrich; Laske, Christoph

2017-01-01

The conventional Clock Drawing Test (cCDT) is a rapid and inexpensive screening tool for detection of moderate and severe dementia. However, its usage is limited due to poor diagnostic accuracy especially in patients with mild cognitive impairment (MCI). The diagnostic value of a newly developed digital Clock Drawing Test (dCDT) was evaluated and compared with the cCDT in 20 patients with early dementia due to AD (eDAT), 30 patients with amnestic MCI (aMCI) and 20 cognitively healthy controls (HCs). Parameters assessed by dCDT were time while transitioning the stylus from one stroke to the next above the surface (i.e., time-in-air), time the stylus produced a visible stroke (i.e., time-on-surface) and total-time during clock drawing. Receiver-operating characteristic (ROC) curves were calculated and logistic regression analyses have been conducted for statistical analysis. Using dCDT, time-in-air was significantly increased in eDAT (70965.8 ms) compared to aMCI (54073.7 ms; p = 0.027) and HC (32315.6 ms; p < 0.001). In addition, time-in-air was significantly longer in patients with aMCI compared to HC (p = 0.003), even in the aMCI group with normal cCDT score (54141.8 ms; p < 0.001). Time-in-air using dCDT allowed discrimination of patients with aMCI from HCs with a sensitivity of 81.3% and a specificity of 72.2% while cCDT scoring revealed a sensitivity of 62.5% and a specificity of 83.3%. Most interestingly, time-in-air allowed even discrimination of aMCI patients with normal cCDT scores (80% from all aMCI patients) from HCs with a clinically relevant sensitivity of 80.8% and a specificity of 77.8%. A combination of dCDT variables and cCDT scores did not improve the discrimination of patients with aMCI from HC. In conclusion, assessment of time-in-air using dCDT yielded a higher diagnostic accuracy for discrimination of aMCI patients from HCs than the use of cCDT even in those aMCI patients with normal cCDT scores. Modern digitizing devices offer the opportunity to measure subtle changes of visuo-constructive demands and executive functions that may be used as a fast and easy to perform screening instrument for the early detection of cognitive impairment in primary care. PMID:28443019

EM-1 Countdown Simulation with Charlie Blackwell-Thompson

NASA Image and Video Library

2018-03-29

NASA Launch Director Charlie Blackwell-Thompson, center, stands next to her console in Firing Room 1 at the Kennedy Space Center's Launch Control Center. With her, from the left, are NASA intern Justin Connolly, NASA Engineering Project Manager Dan Tran, Blackwell-Thompson, Shawn Reverter, Project Manager for Red Canyon Software, Inc., and NASA Structures and Mechanisms Design Branch Chief Adam Dokos, during a countdown simulation for Exploration Mission 1. It was the agency's first simulation of a portion of the countdown for the first launch of a Space Launch System rocket and Orion spacecraft that will eventually take astronauts beyond low-Earth orbit to destinations such as the Moon and Mars.

A low jitter PLL clock used for phase change memory

NASA Astrophysics Data System (ADS)

Xiao, Hong; Houpeng, Chen; Zhitang, Song; Daolin, Cai; Xi, Li

2013-02-01

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Network-Physics(NP) Bec DIGITAL(#)-VULNERABILITY Versus Fault-Tolerant Analog

NASA Astrophysics Data System (ADS)

Alexander, G. K.; Hathaway, M.; Schmidt, H. E.; Siegel, E.

2011-03-01

Siegel[AMS Joint Mtg.(2002)-Abs.973-60-124] digits logarithmic-(Newcomb(1881)-Weyl(1914; 1916)-Benford(1938)-"NeWBe"/"OLDbe")-law algebraic-inversion to ONLY BEQS BEC:Quanta/Bosons= digits: Synthesis reveals EMP-like SEVERE VULNERABILITY of ONLY DIGITAL-networks(VS. FAULT-TOLERANT ANALOG INvulnerability) via Barabasi "Network-Physics" relative-``statics''(VS.dynamics-[Willinger-Alderson-Doyle(Not.AMS(5/09)]-]critique); (so called)"Quantum-computing is simple-arithmetic(sans division/ factorization); algorithmic-complexities: INtractibility/ UNdecidability/ INefficiency/NONcomputability / HARDNESS(so MIScalled) "noise"-induced-phase-transitions(NITS) ACCELERATION: Cook-Levin theorem Reducibility is Renormalization-(Semi)-Group fixed-points; number-Randomness DEFINITION via WHAT? Query(VS. Goldreich[Not.AMS(02)] How? mea culpa)can ONLY be MBCS "hot-plasma" versus digit-clumping NON-random BEC; Modular-arithmetic Congruences= Signal X Noise PRODUCTS = clock-model; NON-Shor[Physica A,341,586(04)] BEC logarithmic-law inversion factorization:Watkins number-thy. U stat.-phys.); P=/=NP TRIVIAL Proof: Euclid!!! [(So Miscalled) computational-complexity J-O obviation via geometry.

STS-103 crew look over payload inside Discovery

NASA Technical Reports Server (NTRS)

1999-01-01

At Launch Pad 39B, STS-103 Mission Specialist C. Michael Foale (Ph.D.) looks over the Hubble servicing cargo in the payload bay of Space Shuttle Discovery. The activity is part of the Terminal Countdown Demonstration Test (TCDT), which also provides the crew with emergency egress training and a simulated countdown exercise. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, John M. Grunsfeld (Ph.D.), Jean- Fran'''ois Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 Pilot Scott Kelly and MS John Grunsfeld try on oxygen masks

NASA Technical Reports Server (NTRS)

1999-01-01

In the bunker at Launch Pad 39B, STS-103 Pilot Scott J. Kelly (left) and Mission Specialist John M. Grunsfeld (Ph.D.) (right) try on oxygen masks during Terminal Countdown Demonstration Test (TCDT) activities. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. Other crew members taking part are Commander Curtis L. Brown Jr. and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), and Jean-Frangois Clervoy of France and Claude Nicollier of Switzerland, who are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew pose at 195-foot level of Fixed Service Structure

NASA Technical Reports Server (NTRS)

1999-01-01

At the 195-foot level of the Fixed Service Structure on Launch Pad 39B, the STS-103 crew take a break from Terminal Countdown Demonstration Test (TCDT) activities. Standing from left to right are Mission Specialists Jean-Frangois Clervoy of France and Claude Nicollier of Switzerland, who are with the European Space Agency; Commander Curtis L. Brown Jr.; Pilot Scott J. Kelly; and Mission Specialists John M. Grunsfeld (Ph.D.), C. Michael Foale (Ph.D.) and Steven L. Smith. The TCDT provides the crew with the emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

KSC-99pp1346

NASA Image and Video Library

1999-11-17

STS-103 Mission Specialist John M. Grunsfeld (Ph.D.) sits inside orbiter Discovery waiting for the start of a simulated countdown exercise. The simulation is part of Terminal Countdown Demonstration Test (TCDT) activities. The TCDT also provides the crew with emergency egress training and opportunities to inspect their mission payload in the orbiter's payload bay. Other crew members taking part in the TCDT are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), Jean-François Clervoy of France, and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

KSC-99pp1328

NASA Image and Video Library

1999-11-16

At Launch Pad 39B, STS-103 Commander Curtis L. Brown Jr. introduces the rest of the crew: (left to right) Pilot Scott J. Kelly and Mission Specialists Steven L. Smith, Jean-François Clervoy of France, who is with the European Space Agency (ESA), John M. Grunsfeld (Ph.D.), C. Michael Foale (Ph.D.), and Claude Nicollier of Switzerland, who is also with ESA. As a preparation for launch, they have been participating in Terminal Countdown Demonstration Test (TCDT) activities at KSC. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a "call-up" mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST

Countdown to 2015 and beyond: fulfilling the health agenda for women and children.

PubMed

Requejo, Jennifer Harris; Bryce, Jennifer; Barros, Aluisio J D; Berman, Peter; Bhutta, Zulfiqar; Chopra, Mickey; Daelmans, Bernadette; de Francisco, Andres; Lawn, Joy; Maliqi, Blerta; Mason, Elizabeth; Newby, Holly; Presern, Carole; Starrs, Ann; Victora, Cesar G

2015-01-31

The end of 2015 will signal the end of the Millennium Development Goal era, when the world can take stock of what has been achieved. The Countdown to 2015 for Maternal, Newborn, and Child Survival (Countdown) has focused its 2014 report on how much has been achieved in intervention coverage in these groups, and on how best to sustain, focus, and intensify efforts to progress for this and future generations. Our 2014 results show unfinished business in achievement of high, sustained, and equitable coverage of essential interventions. Progress has accelerated in the past decade in most Countdown countries, suggesting that further gains are possible with intensified actions. Some of the greatest coverage gaps are in family planning, interventions addressing newborn mortality, and case management of childhood diseases. Although inequities are pervasive, country successes in reaching of the poorest populations provide lessons for other countries to follow. As we transition to the next set of global goals, we must remember the centrality of data to accountability, and the importance of support of country capacity to collect and use high-quality data on intervention coverage and inequities for decision making. To fulfill the health agenda for women and children both now and beyond 2015 requires continued monitoring of country and global progress; Countdown is committed to playing its part in this effort. Copyright © 2015 Elsevier Ltd. All rights reserved.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

NASA Astrophysics Data System (ADS)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Clock and trigger synchronization between several chassis of digital data acquisition modules

NASA Astrophysics Data System (ADS)

Hennig, W.; Tan, H.; Walby, M.; Grudberg, P.; Fallu-Labruyere, A.; Warburton, W. K.; Vaman, C.; Starosta, K.; Miller, D.

2007-08-01

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size. The readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis. The data acquisition system is intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less than 1 ns, and can be extended to a larger number of chassis if desired.

Patterns of activity expressed by juvenile horseshoe crabs.

PubMed

Dubofsky, E A; Simpson, S D; Chabot, Christopher C; Watson, Winsor H

2013-09-01

Adult American horseshoe crabs, Limulus polyphemus, possess endogenous circadian and circatidal clocks controlling visual sensitivity and locomotion, respectively. The goal of this study was to determine the types of activity rhythms expressed by juvenile horseshoe crabs (n = 24) when exposed to a 14:10 light/dark cycle (LD) for 10 days, followed by 10 days of constant darkness (DD). Horseshoe crab activity was recorded with a digital time-lapse video system that used an infrared-sensitive camera so animals could be monitored at night. In LD, 15 animals expressed daily patterns of activity, 6 displayed a circatidal pattern, and the remaining 3 were arrhythmic. Of the 15 animals with daily patterns of locomotion, 7 had a significant preference (P < 0.05) for diurnal activity and 3 for nocturnal activity; the remainder did not express a significant preference for day or night activity. In DD, 13 horseshoe crabs expressed circatidal rhythms and 8 maintained a pattern of about 24 h. Although these results suggest the presence of a circadian clock influencing circatidal patterns of locomotion, these apparent circadian rhythms may actually represent the expression of just one of the two bouts of activity driven by the putative circalunidian clocks that control their tidal rhythms. Overall, these results indicate that, like adults, juvenile horseshoe crabs express both daily and tidal patterns of activity and that at least one, and maybe both, of these patterns is driven by endogenous clocks.

STS-5 crewmembers take part in countdown demonstration test (CDDT)

NASA Technical Reports Server (NTRS)

1982-01-01

STS-5 crewmembers take part in countdown demonstration test (CDDT) at the launch pad. Astronaut Vance D. Brand, commander, is at center, flanked by Mission Specialists William B. Lenoir, left, and Joseph P. ALlen. Mission Specialist/Astronaut Kathryn B. Sullivan, Far left, is in training for future mission.

An 11-bit and 39 ps resolution time-to-digital converter for ADPLL in digital television

NASA Astrophysics Data System (ADS)

Liu, Wei; (Ruth) Li, Wei; Ren, P.; Lin, C. L.; Zhang, Shengdong; Wang, Yangyuan

2010-04-01

We propose and demonstrate an 11-bit time-to-digital converter (TDC) for all-digital phase-locked loops (ADPLLs) in digital television. The proposed TDC converts the width of the input pulse into digital output with the tap space of the outputs of a free-running ring oscillator (FRO) being the conversion resolution. The FRO is in a structure of coiled cell array and the TDC core is symmetrical in the input structure. This leads to equally spaced taps in the reference clocks and thereby a high TDC conversion linearity. The TDC is fabricated in 0.13 μm CMOS process and the chip area is 0.025 mm2. The measurement results show that the TDC has a conversion resolution of 39 ps at 1.2 V power supply and a 4.5 ns dead time in the 11-bits output case. Both the differential non-linearity (DNL) and integral non-linearity (INL) are below 0.5 LSB. The power consumption of the whole circuit is 4.2 mW.

Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

PubMed Central

Zhou, Bo; Zhang, Kun; Zhou, Wenbiao; Zhang, Yanjun; Liu, Dake

2013-01-01

The carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in 180 nm CMOS for high reconfiguration. The proposed architecture achieves wide CF range of 2 M–1 GHz, high power efficiency of 70%, and low error vector magnitude (EVM) of 3%, with spectrum purity of 20 dB optimized in comparison to the existing designs. PMID:24223503

The mini-O, a digital superhet, or a truly low-cost Omega navigation receiver

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1975-01-01

A quartz tuning fork filter circuit and some unique CMOS clock logic methods provide a very simple OMEGA-VLF receiver with true hyperbolic station pair phase difference outputs. An experimental system was implemented on a single battery-operated circuit board requiring only an external antenna preamplifier, and LOP output recorder. A bench evaluation and preliminary navigation tests indicate the technique is viable and can provide very low-cost OMEGA measurement systems. The method is promising for marine use with small boats in the present form, but might be implemented in conjunction with digital microprocessors for airborne navigation aids.

Performance of preproduction model cesium beam frequency standards for spacecraft applications

NASA Technical Reports Server (NTRS)

Levine, M. W.

1978-01-01

A cesium beam frequency standards for spaceflight application on Navigation Development Satellites was designed and fabricated and preliminary testing was completed. The cesium standard evolved from an earlier prototype model launched aboard NTS-2 and the engineering development model to be launched aboard NTS satellites during 1979. A number of design innovations, including a hybrid analog/digital integrator and the replacement of analog filters and phase detectors by clocked digital sampling techniques are discussed. Thermal and thermal-vacuum testing was concluded and test data are presented. Stability data for 10 to 10,000 seconds averaging interval, measured under laboratory conditions, are shown.

SEU/SET Tolerant Phase-Locked Loops

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr.

2010-01-01

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

KSC-08pd2858

NASA Image and Video Library

2008-09-23

CAPE CANAVERAL, Fla. - STS-125 Pilot Gregory C. Johnson serves as a “guinea pig” to demonstrate emergency escape apparatus from the 195-foot level of the fixed service structure on Launch Pad 39A at NASA's Kennedy Space Center in Florida. Looking on are Mission Specialists Andrew Feustel, Megan McArthur and Mike Massimino. The crew is at Kennedy to take part in terminal countdown demonstration test, or TCDT, activities before launching on space shuttle Atlantis’ mission to service NASA’s Hubble Space Telescope. TCDT provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization, emergency training and a simulated launch countdown. Atlantis is targeted to launch Oct. 10. Photo credit: NASA/Kim Shiflett

Back-to-School Countdown: A Planning Guide for Time-Conscious Teachers.

ERIC Educational Resources Information Center

Spann, Mary Beth

1991-01-01

This planning guide for efficient use of the last weeks before school opens offers ideas for interactive hall and wall displays, a guide to self-made math manipulatives, a materials checklist, a four-week task planning countdown, and a listing of teacher resource books and other classroom materials. (SM)

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harold D. Anderson, John T. Williams

2009-07-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Basedmore » on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens-of-nanoseconds delay to propagate across the FPGA. This paper discusses the design, installation, and testing of the proposed system upgrade, including failure statistics and modifications to the original design.« less

The Lancet Countdown: tracking progress on health and climate change.

PubMed

Watts, Nick; Adger, W Neil; Ayeb-Karlsson, Sonja; Bai, Yuqi; Byass, Peter; Campbell-Lendrum, Diarmid; Colbourn, Tim; Cox, Peter; Davies, Michael; Depledge, Michael; Depoux, Anneliese; Dominguez-Salas, Paula; Drummond, Paul; Ekins, Paul; Flahault, Antoine; Grace, Delia; Graham, Hilary; Haines, Andy; Hamilton, Ian; Johnson, Anne; Kelman, Ilan; Kovats, Sari; Liang, Lu; Lott, Melissa; Lowe, Robert; Luo, Yong; Mace, Georgina; Maslin, Mark; Morrissey, Karyn; Murray, Kris; Neville, Tara; Nilsson, Maria; Oreszczyn, Tadj; Parthemore, Christine; Pencheon, David; Robinson, Elizabeth; Schütte, Stefanie; Shumake-Guillemot, Joy; Vineis, Paolo; Wilkinson, Paul; Wheeler, Nicola; Xu, Bing; Yang, Jun; Yin, Yongyuan; Yu, Chaoqing; Gong, Peng; Montgomery, Hugh; Costello, Anthony

2017-03-18

The Lancet Countdown: tracking progress on health and climate change is an international, multidisciplinary research collaboration between academic institutions and practitioners across the world. It follows on from the work of the 2015 Lancet Commission, which concluded that the response to climate change could be "the greatest global health opportunity of the 21st century". The Lancet Countdown aims to track the health impacts of climate hazards; health resilience and adaptation; health co-benefits of climate change mitigation; economics and finance; and political and broader engagement. These focus areas form the five thematic working groups of the Lancet Countdown and represent different aspects of the complex association between health and climate change. These thematic groups will provide indicators for a global overview of health and climate change; national case studies highlighting countries leading the way or going against the trend; and engagement with a range of stakeholders. The Lancet Countdown ultimately aims to report annually on a series of indicators across these five working groups. This paper outlines the potential indicators and indicator domains to be tracked by the collaboration, with suggestions on the methodologies and datasets available to achieve this end. The proposed indicator domains require further refinement, and mark the beginning of an ongoing consultation process-from November, 2016 to early 2017-to develop these domains, identify key areas not currently covered, and change indicators where necessary. This collaboration will actively seek to engage with existing monitoring processes, such as the UN Sustainable Development Goals and WHO's climate and health country profiles. The indicators will also evolve over time through ongoing collaboration with experts and a range of stakeholders, and be dependent on the emergence of new evidence and knowledge. During the course of its work, the Lancet Countdown will adopt a collaborative and iterative process, which aims to complement existing initiatives, welcome engagement with new partners, and be open to developing new research projects on health and climate change. Copyright © 2017 Elsevier Ltd. All rights reserved.

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Circumnutation as a visible plant action and reaction

PubMed Central

2009-01-01

Circumnutation is a helical organ movement widespread among plants. It is variable due to a different magnitude of trajectory (amplitude) outlined by the organ tip, duration of one cycle (period), circular, elliptical, pendulum-like or irregular shape and clock- and counterclockwise direction of rotation. Some of those movement parameters are regulated by circadian clock and show daily and infradian rhythms. Circumnutation is influenced by light, temperature, chemicals and can depend on organ morphology. The diversity of this phenomenon is easier to see now that the digital time-lapse video method is developing fast. Whether circumnutation is an endogenous action, a reaction to exogenous stimuli or has a combined character has been discussed for a long time. Similarly, the relationship between growth and circumnutation is still unclear. In the mechanism of circumnutation, epidermal and endodermal cells as well as plasmodesmata, plasma membrane, ions (Ca2+, K+ and Cl−), ion channels and the proton pump (H+ATPase) are engaged. Based on these data, the hypothetical electrophysiological model of the circumnutation mechanism has been proposed here. In the recent circumnutation studies, gravitropic, auxin, clock and phytochrome mutants are used and new functions of circumnutation in plants' life have been investigated and described. PMID:19816110

Evaluation of a Three-Channel High-Temperature Superconducting Magnetometer System

DTIC Science & Technology

1997-06-01

achieved by the best commercially available fluxgate magnetometers demonstrated to date and is only surpassed by low temperature superconducting...wire lines carry the analog SQUID magnetometer signal as well as dc power and ground, and the fiberoptic lines carry digital clock and data signals...with the magnetometers mounted on the three-sensor probe used in the sensor evaluated here. This probe is not highly stabilized with respect to the

Resolving Phase Ambiguities In OQPSK

NASA Technical Reports Server (NTRS)

Nguyen, Tien M.

1991-01-01

Improved design for modulator and demodulator in offset-quaternary-phase-key-shifting (OQPSK) communication system enables receiver to resolve ambiguity in estimated phase of received signal. Features include unique-code-word modulation and detection and digital implementation of Costas loop in carrier-recovery subsystem. Enchances performance of carrier-recovery subsystem, reduces complexity of receiver by removing redundant circuits from previous design, and eliminates dependence of timing in receiver upon parallel-to-serial-conversion clock.

Apparatus Tests Peeling Of Bonded Rubbery Material

NASA Technical Reports Server (NTRS)

Crook, Russell A.; Graham, Robert

1996-01-01

Instrumented hydraulic constrained blister-peel apparatus obtains data on degree of bonding between specimen of rubbery material and rigid plate. Growth of blister tracked by video camera, digital clock, pressure transducer, and piston-displacement sensor. Cylinder pressure controlled by hydraulic actuator system. Linear variable-differential transformer (LVDT) and float provide second, independent measure of change in blister volume used as more precise volume feedback in low-growth-rate test.

A reconfigurable cryogenic platform for the classical control of quantum processors

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A reconfigurable cryogenic platform for the classical control of quantum processors.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A hardware implementation of the discrete Pascal transform for image processing

NASA Astrophysics Data System (ADS)

Goodman, Thomas J.; Aburdene, Maurice F.

2006-02-01

The discrete Pascal transform is a polynomial transform with applications in pattern recognition, digital filtering, and digital image processing. It already has been shown that the Pascal transform matrix can be decomposed into a product of binary matrices. Such a factorization leads to a fast and efficient hardware implementation without the use of multipliers, which consume large amounts of hardware. We recently developed a field-programmable gate array (FPGA) implementation to compute the Pascal transform. Our goal was to demonstrate the computational efficiency of the transform while keeping hardware requirements at a minimum. Images are uploaded into memory from a remote computer prior to processing, and the transform coefficients can be offloaded from the FPGA board for analysis. Design techniques like as-soon-as-possible scheduling and adder sharing allowed us to develop a fast and efficient system. An eight-point, one-dimensional transform completes in 13 clock cycles and requires only four adders. An 8x8 two-dimensional transform completes in 240 cycles and requires only a top-level controller in addition to the one-dimensional transform hardware. Finally, through minor modifications to the controller, the transform operations can be pipelined to achieve 100% utilization of the four adders, allowing one eight-point transform to complete every seven clock cycles.

Design and Implementation of a Video-Zoom Driven Digital Audio-Zoom System for Portable Digital Imaging Devices

NASA Astrophysics Data System (ADS)

Park, Nam In; Kim, Seon Man; Kim, Hong Kook; Kim, Ji Woon; Kim, Myeong Bo; Yun, Su Won

In this paper, we propose a video-zoom driven audio-zoom algorithm in order to provide audio zooming effects in accordance with the degree of video-zoom. The proposed algorithm is designed based on a super-directive beamformer operating with a 4-channel microphone system, in conjunction with a soft masking process that considers the phase differences between microphones. Thus, the audio-zoom processed signal is obtained by multiplying an audio gain derived from a video-zoom level by the masked signal. After all, a real-time audio-zoom system is implemented on an ARM-CORETEX-A8 having a clock speed of 600 MHz after different levels of optimization are performed such as algorithmic level, C-code, and memory optimizations. To evaluate the complexity of the proposed real-time audio-zoom system, test data whose length is 21.3 seconds long is sampled at 48 kHz. As a result, it is shown from the experiments that the processing time for the proposed audio-zoom system occupies 14.6% or less of the ARM clock cycles. It is also shown from the experimental results performed in a semi-anechoic chamber that the signal with the front direction can be amplified by approximately 10 dB compared to the other directions.

A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Liu, Chong

2016-10-01

The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.

Technicians prepare to close hatches on Gemini 11 spacecraft during countdown

NASA Technical Reports Server (NTRS)

1966-01-01

Technicians in the White Room atop Pad 19 prepare to close hatches on the Gemini 11 spacecraft during prelaunch countdown. Inside the spacecraft are Astronauts Charles Conrad Jr., command pilot, and Richard F. Gordon Jr., pilot. There is a humorous sign stating 'This is ABSOLUTELY your Last Chance' being held by one of the technicians.

Ambitious STS-7 mission to feature first landing at Kennedy

NASA Technical Reports Server (NTRS)

Garrett, D.; Hess, M.; White, T.; Taylor, J.

1982-01-01

The STS-7 press briefing schedule, NASA select television schedule; launch preparations, countdown and liftoff; major countdown milestones; launch window; STS-7 flight sequence of events, landing timeline; STS-7 flight timeline; landing and post landing operations; flight objectives; Telesat's ANIK-C 2; PALAPA-B; STS-7 experiments; and spacecraft tracking and data network are presented.

KSC-97PC1613

NASA Image and Video Library

1997-11-05

STS-87 Payload Specialist Leonid Kadenyuk, at right, of the National Space Agency of Ukraine (NSAU) is assisted into his orange launch and entry spacesuit ensemble by NASA Suit Technician Al Rochford, at left, before participating in Terminal Countdown Demonstration Test (TCDT) activities. The crew of the STS-87 mission is scheduled for launch Nov. 19 aboard the Space Shuttle Columbia. The TCDT is held at KSC prior to each Space Shuttle flight providing the crew of each mission opportunities to participate in simulated countdown activities. The TCDT ends with a mock launch countdown culminating in a simulated main engine cut-off. The crew also spends time undergoing emergency egress training exercises at the pad and has an opportunity to view and inspect the payloads in the orbiter's payload bay

STS-87 Commander Kregel holds the crew patch in front of Columbia's entry hatch at LC 39B during TCD

NASA Technical Reports Server (NTRS)

1997-01-01

STS-87 Commander Kevin Kregel holds the crew patch in front of Columbia's entry hatch at Launch Pad 39B during Terminal Countdown Demonstration Test (TCDT) activities. The crew of the STS-87 mission is scheduled for launch Nov. 19 aboard the Space Shuttle Columbia. The TCDT is held at KSC prior to each Space Shuttle flight providing the crew of each mission opportunities to participate in simulated countdown activities. The TCDT ends with a mock launch countdown culminating in a simulated main engine cut-off. The crew also spends time undergoing emergency egress training exercises at the pad and has an opportunity to view and inspect the payloads in the orbiter's payload bay.

KSC-08pd3438

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Sandra Magnus is strapped into her seat in space shuttle Endeavour. She and other crew members will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3437

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Shane Kimbrough is strapped into his seat in space shuttle Endeavour signaling he is ready for the simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-05PD-0855

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Andrew Thomas is ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0854

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Pilot James Kelly is ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0846

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, the STS-114 Mission Specialist Wendy Lawrence is getting ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0848

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Stephen Robinson is getting ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

A generic readout system for astrophysical detectors

NASA Astrophysics Data System (ADS)

Doumayrou, E.; Lortholary, M.

2012-09-01

We have developed a generic digital platform to fulfill the needs for the development of new detectors in astrophysics, which is used in lab, for ground-based telescopes instruments and also in prototype versions for space instruments development. This system is based on hardware FPGA electronic board (called MISE) together with software on a PC computer (called BEAR). The MISE board generates the fast clocking which reads the detectors thanks to a programmable digital sequencer and performs data acquisition, buffering of digitalized pixels outputs and interfaces with others boards. The data are then sent to the PC via a SpaceWire or Usb link. The BEAR software sets the MISE board up, makes data acquisition and enables the visualization, processing and the storage of data in line. These software tools are made of C++ and Labview (NI) on a Linux OS. MISE and BEAR make a generic acquisition architecture, on which dedicated analog boards are plugged, so that to accommodate with detectors specificity: number of pixels, the readout channels and frequency, analog bias and clock interfaces. We have used this concept to build a camera for the P-ARTEMIS project including a 256 pixels sub-millimeter bolometer detector at 10Kpixel/s (SPIE 7741-12 (2010)). For the EUCLID project, a lab camera is now working for the test of CCDs 4Mpixels at 4*200Kpixel/s. Another is working for the testing of new near infrared detectors (NIR LFSA for the ESA TRP program) 110Kpixels at 2*100Kpixels/s. Other projects are in progress for the space missions PLATO and SPICA.

A fast-locking PLL with all-digital locked-aid circuit

NASA Astrophysics Data System (ADS)

Kao, Shao-Ku; Hsieh, Fu-Jen

2013-02-01

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

An Evaluation of optional timing/synchronization features to support selection of an optimum design for the DCS digital communication network

NASA Technical Reports Server (NTRS)

Bradley, D. B.; Cain, J. B., III; Williard, M. W.

1978-01-01

The task was to evaluate the ability of a set of timing/synchronization subsystem features to provide a set of desirable characteristics for the evolving Defense Communications System digital communications network. The set of features related to the approaches by which timing/synchronization information could be disseminated throughout the network and the manner in which this information could be utilized to provide a synchronized network. These features, which could be utilized in a large number of different combinations, included mutual control, directed control, double ended reference links, independence of clock error measurement and correction, phase reference combining, and self organizing.

Calibration techniques for a fast duo-spectrometer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chapman, J.T.; Den Hartog, D.J.

1996-06-01

The authors have completed the upgrade and calibration of the Ion Dynamics Spectrometer (IDS), a high-speed Doppler duo-spectrometer which measures ion flow and temperature in the MST Reversed-field Pinch. This paper describes an in situ calibration of the diagnostic`s phase and frequency response. A single clock was employed to generate both a digital test signal and a digitizer trigger thus avoiding frequency drift and providing a highly resolved measurement over the system bandwidth. Additionally, they review the measurement of the spectrometer instrument function and absolute intensity response. This calibration and subsequent performance demonstrate the IDS to be one of themore » fastest, highest throughput diagnostics of its kind. Typical measurements are presented.« less

New design conception and development of the synchronizer/data buffer system in CDA station for China's GMS

NASA Astrophysics Data System (ADS)

Tong, Kai; Fan, Shiming; Gong, Derong; Lu, Zuming; Liu, Jian

The synchronizer/data buffer (SDB) in the command and data acquisition station for China's future Geostationary Meteorological Satellite is described. Several computers and special microprocessors are used in tandem with minimized hardware to fulfill all of the functions. The high-accuracy digital phase locked loop is operated by computer and by controlling the count value of the 20-MHz clock to acquire and track such signals as sun pulse, scan synchronization detection pulse, and earth pulse. Sun pulse and VISSR data are recorded precisely and economically by digitizing the time relation. The VISSR scan timing and equiangular control timing, and equal time sampling on satellite are also discussed.

Signal processor for processing ultrasonic receiver signals

DOEpatents

Fasching, George E.

1980-01-01

A signal processor is provided which uses an analog integrating circuit in conjunction with a set of digital counters controlled by a precision clock for sampling timing to provide an improved presentation of an ultrasonic transmitter/receiver signal. The signal is sampled relative to the transmitter trigger signal timing at precise times, the selected number of samples are integrated and the integrated samples are transferred and held for recording on a strip chart recorder or converted to digital form for storage. By integrating multiple samples taken at precisely the same time with respect to the trigger for the ultrasonic transmitter, random noise, which is contained in the ultrasonic receiver signal, is reduced relative to the desired useful signal.

Millimeterwave and digital applications of InP-based MBE grown HEMTs and HBTs

NASA Astrophysics Data System (ADS)

Greiling, Paul

1997-05-01

Microwave and millimeterwave devices grown by MBE have significantly advanced the state of the art for RF device performance with respect to noise figure, power output, power added efficiency and extended the clock frequency of digital circuits into the millimeterwave regime. Ober the last 10-15 years, military systems have greatly benefited from the superior performance of MBE grown devices. In order to have a similar impact on the commercial marketplace, MBE growers will have to focus their efforts on a different set of performance criteria; i.e. cost, uniformity and reproducibility. This paper discusses outstanding performance achieved by MBE grown devices and outlines the criteria for commercial applications.

GET: A generic electronics system for TPCs and nuclear physics instrumentation

NASA Astrophysics Data System (ADS)

Pollacco, E. C.; Grinyer, G. F.; Abu-Nimeh, F.; Ahn, T.; Anvar, S.; Arokiaraj, A.; Ayyad, Y.; Baba, H.; Babo, M.; Baron, P.; Bazin, D.; Beceiro-Novo, S.; Belkhiria, C.; Blaizot, M.; Blank, B.; Bradt, J.; Cardella, G.; Carpenter, L.; Ceruti, S.; De Filippo, E.; Delagnes, E.; De Luca, S.; De Witte, H.; Druillole, F.; Duclos, B.; Favela, F.; Fritsch, A.; Giovinazzo, J.; Gueye, C.; Isobe, T.; Hellmuth, P.; Huss, C.; Lachacinski, B.; Laffoley, A. T.; Lebertre, G.; Legeard, L.; Lynch, W. G.; Marchi, T.; Martina, L.; Maugeais, C.; Mittig, W.; Nalpas, L.; Pagano, E. V.; Pancin, J.; Poleshchuk, O.; Pedroza, J. L.; Pibernat, J.; Primault, S.; Raabe, R.; Raine, B.; Rebii, A.; Renaud, M.; Roger, T.; Roussel-Chomaz, P.; Russotto, P.; Saccà, G.; Saillant, F.; Sizun, P.; Suzuki, D.; Swartz, J. A.; Tizon, A.; Usher, N.; Wittwer, G.; Yang, J. C.

2018-04-01

General Electronics for TPCs (GET) is a generic, reconfigurable and comprehensive electronics and data-acquisition system for nuclear physics instrumentation of up to 33792 channels. The system consists of a custom-designed ASIC for signal processing, front-end cards that each house 4 ASIC chips and digitize the data in parallel through 12-bit ADCs, concentration boards to read and process the digital data from up to 16 ASICs, a 3-level trigger and master clock module to trigger the system and synchronize the data, as well as all of the associated firmware, communication and data-acquisition software. An overview of the system including its specifications and measured performances are presented.

Programmable rate modem utilizing digital signal processing techniques

NASA Technical Reports Server (NTRS)

Bunya, George K.; Wallace, Robert L.

1989-01-01

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery.

Operation and tests of a DDC101 A/D

NASA Astrophysics Data System (ADS)

Nguyen, H.

1994-11-01

For the KTeV PMT laser monitoring system, one needs a high resolution device with a large dynamic range to be used for digitizing PIN photodiodes. The dynamic range should be wider than or comparable to the KTeV digitizer (17-bits). The Burr-Brown DDC101 is a precision, wide dynamic range, charge digitizing A/D converter with 20-bit resolution, packaged in a 28-pin plastic, double-wide DP. Low level current output devices such as photosensors can be directly connected to its input. The digital output can be clocked-out serially from the pins. For typical operations, a relatively wide gate of 1 msec should be used. The full scale charge is 500 pC for unipolar mode. The bipolar mode scale is +/- 250 pC. The advertised integral nonlinearity is 0.003% of FSR. This document describes only the basic DDC101 operations since full detail can be found in the DDC101 manual. Tests results are given in section 3.

Digital phased array beamforming using single-bit delta-sigma conversion with non-uniform oversampling.

PubMed

Kozak, M; Karaman, M

2001-07-01

Digital beamforming based on oversampled delta-sigma (delta sigma) analog-to-digital (A/D) conversion can reduce the overall cost, size, and power consumption of phased array front-end processing. The signal resampling involved in dynamic delta sigma beamforming, however, disrupts synchronization between the modulators and demodulator, causing significant degradation in the signal-to-noise ratio. As a solution to this, we have explored a new digital beamforming approach based on non-uniform oversampling delta sigma A/D conversion. Using this approach, the echo signals received by the transducer array are sampled at time instants determined by the beamforming timing and then digitized by single-bit delta sigma A/D conversion prior to the coherent beam summation. The timing information involves a non-uniform sampling scheme employing different clocks at each array channel. The delta sigma coded beamsums obtained by adding the delayed 1-bit coded RF echo signals are then processed through a decimation filter to produce final beamforming outputs. The performance and validity of the proposed beamforming approach are assessed by means of emulations using experimental raw RF data.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

STS-103 crew look over payload inside Discovery

NASA Technical Reports Server (NTRS)

1999-01-01

Members of the STS-103 crew, with representatives from Goddard Space Flight Center, look over the Hubble servicing cargo in the payload bay of Space Shuttle Discovery at Launch Pad 39B. From left are Mission Specialist Steven L. Smith and Claude Nicollier of Switzerland; Steve Pataki and Dave Southwick, with Goddard; and Mission Commander Curtis L. Brown Jr. Inspecting the payload is part of the Terminal Countdown Demonstration Test (TCDT), which also provides the crew with emergency egress training and a simulated countdown exercise. Other crew members taking part in the TCDT are Pilot Scott J. Kelly, and Mission Specialists C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Jean- Fran'''ois Clervoy of France. Clervoy and Nicollier are with the European Space Agency. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew learn about use of slideware basket at Pad 39B

NASA Technical Reports Server (NTRS)

1999-01-01

At the slidewire area of Launch Pad 39B, the STS-103 crew listen to use of the emergency egress equipment. From left are the trainer, with crew members Mission Specialists Steven L. Smith, Jean-Frangois Clervoy of France, Claude Nicollier of Switzerland, John M. Grunsfeld (Ph.D.), Pilot Steven J. Kelly, C. Michael Foale (Ph.D.), and (kneeling) Commander Curtis L. Brown Jr. Clervoy and Nicollier are both with the European Space Agency. As a preparation for launch, the crew have been participating in Terminal Countdown Demonstration Test (TCDT) activities at KSC. The TCDT provides the crew with emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

KSC-2011-7951

NASA Image and Video Library

2011-11-26

CAPE CANAVERAL, Fla. – Participants of a NASA Tweetup pose for a group portrait at NASA Kennedy Space Center's Press Site in Florida during prelaunch activities for the agency’s Mars Science Laboratory (MSL) launch. Behind them, the countdown clock ticks off the seconds to launch. Participants in the Tweetup are given the opportunity to listen to agency briefings, tour locations on the center normally off limits to visitors, and get a close-up view of Space Launch Complex-41 on Cape Canaveral Air Force Station. The tweeters will share their experiences with followers through the social networking site Twitter. The MSL mission will pioneer precision landing technology and a sky-crane touchdown to place a car-sized rover, Curiosity, near the foot of a mountain inside Gale Crater on Aug. 6, 2012. During a nearly two-year prime mission after landing, the rover will investigate whether the region has ever offered conditions favorable for microbial life, including the chemical ingredients for life. Liftoff of MSL aboard a United Launch Alliance Atlas V rocket from pad 41 is planned during a launch window which extends from 10:02 a.m. to 11:45 a.m. EST on Nov. 26. For more information, visit http://www.nasa.gov/msl. Photo credit: NASA/Frankie Martin

sts132-s-005

NASA Image and Video Library

2010-05-14

STS132-S-005 (14 May 2010) --- Witnessed by news media representatives and STS-132 Tweet-up participants on hand by the countdown clock at the Press Site, Space shuttle Atlantis and its six-member STS-132 crew head toward Earth orbit and rendezvous with the International Space Station. Liftoff was at 2:20 p.m. (EDT) on May 14, 2010, from launch pad 39A at NASA's Kennedy Space Center. Onboard are NASA astronauts Ken Ham, commander; Tony Antonelli, pilot; Garrett Reisman, Michael Good, Steve Bowen and Piers Sellers, all mission specialists. The crew will deliver the Russian-built Mini-Research Module 1 (MRM-1) to the International Space Station. Named Rassvet, Russian for "dawn," the module is the second in a series of new pressurized components for Russia and will be permanently attached to the Earth-facing port of the Zarya Functional Cargo Block (FGB). Rassvet will be used for cargo storage and will provide an additional docking port to the station. Also aboard Atlantis is an Integrated Cargo Carrier, or ICC, an unpressurized flat bed pallet and keel yoke assembly used to support the transfer of exterior cargo from the shuttle to the station. STS-132 is the 34th mission to the station and the last scheduled flight for Atlantis.

sts132-s-011

NASA Image and Video Library

2010-05-14

STS132-S-011 (14 May 2010) --- Witnessed by news media representatives and STS-132 Tweet-up participants on hand by the countdown clock at the Press Site, Space shuttle Atlantis and its six-member STS-132 crew head toward Earth orbit and rendezvous with the International Space Station. Liftoff was at 2:20 p.m. (EDT) on May 14, 2010, from launch pad 39A at NASA's Kennedy Space Center. Onboard are NASA astronauts Ken Ham, commander; Tony Antonelli, pilot; Garrett Reisman, Michael Good, Steve Bowen and Piers Sellers, all mission specialists. The crew will deliver the Russian-built Mini-Research Module 1 (MRM-1) to the International Space Station. Named Rassvet, Russian for "dawn," the module is the second in a series of new pressurized components for Russia and will be permanently attached to the Earth-facing port of the Zarya Functional Cargo Block (FGB). Rassvet will be used for cargo storage and will provide an additional docking port to the station. Also aboard Atlantis is an Integrated Cargo Carrier, or ICC, an unpressurized flat bed pallet and keel yoke assembly used to support the transfer of exterior cargo from the shuttle to the station. STS-132 is the 34th mission to the station and the last scheduled flight for Atlantis.

sts132-s-010

NASA Image and Video Library

2010-05-14

STS132-S-010 (14 May 2010) --- Witnessed by news media representatives and STS-132 Tweet-up participants on hand by the countdown clock at the Press Site, Space shuttle Atlantis and its six-member STS-132 crew head toward Earth orbit and rendezvous with the International Space Station. Liftoff was at 2:20 p.m. (EDT) on May 14, 2010, from launch pad 39A at NASA's Kennedy Space Center. Onboard are NASA astronauts Ken Ham, commander; Tony Antonelli, pilot; Garrett Reisman, Michael Good, Steve Bowen and Piers Sellers, all mission specialists. The crew will deliver the Russian-built Mini-Research Module 1 (MRM-1) to the International Space Station. Named Rassvet, Russian for "dawn," the module is the second in a series of new pressurized components for Russia and will be permanently attached to the Earth-facing port of the Zarya Functional Cargo Block (FGB). Rassvet will be used for cargo storage and will provide an additional docking port to the station. Also aboard Atlantis is an Integrated Cargo Carrier, or ICC, an unpressurized flat bed pallet and keel yoke assembly used to support the transfer of exterior cargo from the shuttle to the station. STS-132 is the 34th mission to the station and the last scheduled flight for Atlantis.

STS-27 Atlantis, OV-104, terminal countdown demonstration test (TCDT) at KSC

NASA Technical Reports Server (NTRS)

1988-01-01

STS-27 Atlantis, Orbiter Vehicle (OV) 104, crewmembers participate in the terminal countdown demonstration test (TCDT) at the Kennedy Space Center (KSC). Before TCDT, crewmembers eat breakfast. Sitting around the table (left to right) are Mission Specialist (MS) Jerry L. Ross, MS William M. Shepherd, Commander Robert L. Gibson, Pilot Guy S. Gardner, and MS Richard M. Mullane.

STS-28 Columbia, OV-102, terminal countdown demonstration test (TCDT) at KSC

NASA Technical Reports Server (NTRS)

1989-01-01

STS-28 Columbia, Orbiter Vehicle (OV) 102, crewmembers participate in the terminal countdown demonstration test (TCDT) at the Kennedy Space Center (KSC). Before TCDT, crewmembers eat breakfast. Sitting around the table (left to right) are Mission Specialist (MS) James C. Adamson, Pilot Richard N. Richards, Commander Brewster H. Shaw, Jr, MS David C. Leestma, and MS Mark N. Brown.

View of White Room atop Pad A during Apollo 9 Countdown Demonstration Test

NASA Technical Reports Server (NTRS)

1969-01-01

Interior view of the White Room atop Pad A, Launch Complex 39, Kenndy Space Center, during Apollo 9 Countdown Demonstration Test activity. Standing next to spacecraft hatch is Astronaut James A. McDivitt, commander. Also taking part in the training exercise were Astronauts David R. Scott, command module pilot; and Russell L. Schweickart, lunar module pilot.

KSC-06pd1081

NASA Image and Video Library

2006-06-15

KENNEDY SPACE CENTER, FLA. - STS-121 Mission Specialist Stephanie Wilson signals all is well after donning her launch and entry suit in preparation for the simulated countdown she and other crew members will undertake. The crew is taking part in Terminal Countdown Demonstration Test activities, including the dress rehearsal for launch. Mission STS-121 is scheduled to be launched July 1. Photo credit: NASA/Kim Shiflett

Seismic refraction profile, Kingdom of Saudi Arabia: field operations, instrumentation, and initial results

USGS Publications Warehouse

Blank, H. Richard; Healy, J.H.; Roller, John; Lamson, Ralph; Fisher, Fred; McClearn, Robert; Allen, Steve

1979-01-01

In February 1978 a seismic deep-refraction profile was recorded by the USGS along a 1000-km line across the Arabian Shield in western Saudi Arabia. The line begins in Paleozoic and Mesozoic cover rocks near Riyadh on the Arabian Platform, leads southwesterly across three major Precambrian tectonic provinces, traverses Cenozoic rocks of the coastal plain near Jizan (Tihamat Asir), and terminates at the outer edge of the Farasan Bank in the southern Red Sea. More than 500 surveyed recording sites were occupied, including 19 in the Farasan Islands. Six shot points were used--five on land, with charges placed mostly below water table in drill holes, and one at sea, with charges placed on the sea floor and fired from a ship. The total charge consumed was slightly in excess of 61 metric tons in 21 discrete firings. Seismic energy was recorded by means of a set of 100 newly developed portable seismic stations. Each station consists of a standard 2-Hz vertical geophone coupled to a self-contained analog recording instrument equipped with a magnetic-tape cassette. The stations were deployed in groups of 20 by five observer teams, each generally consisting of two scientist-technicians and a surveyor-guide. On the day prior to deployment, the instruments were calibrated and programmed for automatic operation by means of a specially designed device called a hand-held tester. At each of ten pre-selected recording time windows on a designated firing day, the instruments were programmed to turn on, stabilize, record internal calibration signals, record the seismic signals at three levels of amplification, and then deactivate. After the final window in the firing sequence, all instruments were retrieved and their data tapes removed for processing. A specially designed, field tape- dubbing system was utilized at shot point camps to organize and edit data recorded on the cassette tapes. The main functions of this system are to concatenate all data from each shot on any given day onto a single shot tape, and to provide hard copy for monitoring recorder performance so that any problems can be corrected prior to the next deployment. Composite digital record sections were produced from the dubbed tapes for each shot point by a portable processing and plotting system. The heart of this system is a DEC PDP 11VO3 computer, which controls a cassette playback unit identical to those used in the recorders and dubbers, a set of discriminators, a time-code translator, a digitizer, and a digital plotter. The system was used to maintain various informational data sets and to produce tabulations and listings of various sorts during the field operations, in addition to its main task of producing digital record sections. Two master clocks, both set to time signals broadcast by the British Broadcasting Corporation, provided absolute time for the recording operations. One was located on the ship and the other was stationed at a base camp on the mainland. The land-based master clock was used to set three additional master clocks located at the other active shot points a few days in advance of each firing, and these clocks were then used to set the internal clocks in the portable seismic stations via the hand-held tester. A master clock signal was also linked to the firing system at each shot point for determination of the absolute shot instant. It is possible to construct a generalized crustal model from examination of the six shot point composite record sections obtained in the field. Such a model rests upon a number of simplifying assumptions and will almost certainly be modified at a later stage of interpretation. The main assumptions are that the crust consists of two homogeneous isotropic layers having no velocity inversion,, that the Mohorovicic discontinuity is sharp, and that effects of surface inhomogeneities and elevation changes can be ignored. The main characteristics of the tentative model are the following: (1) The thickness of th

KSC-08pd3444

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members head for the slidewire baskets on the 195-foot level of the fixed service structure. They have taken part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3435

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Donald Pettit signals okay as he gets into his seat in space shuttle Endeavour. He and other crew members will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3429

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Commander Chris Ferguson adjusts his headset before donning his helmet. He will enter space shuttle Endeavour to take part in a simulated launch countdown with the other crew members. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3430

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Pilot Eric Boe waits to finish his suit-up. He and other crew members will take part in a simulated launch countdown after entering space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3436

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Heidemarie Stefanyshyn-Piper is strapped into her seat in space shuttle Endeavour. She and other crew members will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3433

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Shane Kimbrough gets help with his suit before entering space shuttle Endeavour. He and other crew members will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3445

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members climb into a slidewire basket on the 195-foot level of the fixed service structure. They have taken part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3442

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members head for the slidewire baskets on the 195-foot level of the fixed service structure. They have taken part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3432

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Donald Pettit adjusts his headset. He will enter space shuttle Endeavour to take part in a simulated launch countdown with the other crew members. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-05PD-0850

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Commander Eileen Collins gets ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. Behind her is Capt. George Hoggard, who is astronaut rescue team leader. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0849

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Stephen Robinson (right) practices driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. At left is Capt. George Hoggard, who is astronaut rescue team leader. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0811

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. At Kennedy Space Centers Shuttle Landing Facility, Center Director Jim Kennedy talks with STS-114 Commander Eileen Collins after her arrival. She and the rest of the crew are at KSC to take part in the Terminal Countdown Demonstration Test (TCDT) over the next three days. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. This is Collins fourth space flight and second as commander. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

STS-87 Mission Specialist Chawla is assisted with her launch and entry spacesuit at LC 39B during TC

NASA Technical Reports Server (NTRS)

1997-01-01

STS-87 Mission Specialist Kalpana Chawla, Ph.D., is assisted with her orange launch and entry spacesuit by NASA suit technicians at Launch Pad 39B during Terminal Countdown Demonstration Test (TCDT) activities. The crew of the STS-87 mission is scheduled for launch Nov. 19 aboard the Space Shuttle Columbia. The TCDT is held at KSC prior to each Space Shuttle flight providing the crew of each mission opportunities to participate in simulated countdown activities. The TCDT ends with a mock launch countdown culminating in a simulated main engine cut-off. The crew also spends time undergoing emergency egress training exercises at the pad and has an opportunity to view and inspect the payloads in the orbiter's payload bay.

KSC-08pd0592

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- Emergency egress training completed, the STS-123 crew members gather at the slidewire baskets. In front is Mission Specialist Takao Doi, who represents the Japan Aerospace Exploration Agency. The egress training followed the simulated launch countdown, which was the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

A seafloor electromagnetic receiver for marine magnetotellurics and marine controlled-source electromagnetic sounding

NASA Astrophysics Data System (ADS)

Chen, Kai; Wei, Wen-Bo; Deng, Ming; Wu, Zhong-Liang; Yu, Gang

2015-09-01

In planning and executing marine controlled-source electromagnetic methods, seafloor electromagnetic receivers must overcome the problems of noise, clock drift, and power consumption. To design a receiver that performs well and overcomes the abovementioned problems, we performed forward modeling of the E-field abnormal response and established the receiver's characteristics. We describe the design optimization and the properties of each component, that is, low-noise induction coil sensor, low-noise Ag/AgCl electrode, low-noise chopper amplifier, digital temperature-compensated crystal oscillator module, acoustic telemetry modem, and burn wire system. Finally, we discuss the results of onshore and offshore field tests to show the effectiveness of the developed seafloor electromagnetic receiver and its performance: typical E-field noise of 0.12 nV/m/rt(Hz) at 0.5 Hz, dynamic range higher than 120 dB, clock drift lower than 1 ms/day, and continuous operation of at least 21 days.

Accuracy of prospective memory tests in mild Alzheimer's disease.

PubMed

Martins, Sergilaine Pereira; Damasceno, Benito Pereira

2012-01-01

To verify the accuracy of prospective memory (ProM) tests in Alzheimer's disease (AD). Twenty mild AD patients (CDR 1), and 20 controls underwent Digit Span (DS), Trail Making (TM) A and B, visual perception, Rey Auditory-Verbal Learning tests, and Cornell Scale for Depression. AD diagnosis was based on DSM-IV and NINCDS-ADRDA criteria. ProM was assessed with the appointment and belonging subtests of Rivermead Behavioral Memory Test (RBMT); and with two new tests (the clock and animal tests). AD patients had a worse performance than controls on the majority of tests, except DS forward and TM-A. There was no correlation between RBMT and the new ProM tests. As for accuracy, the only significant difference concerned the higher sensitivity of our animal test versus the RBMT belonging test. The clock and the animal tests showed similar specificity, but higher sensitivity than the RBMT subtests.

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

NASA Astrophysics Data System (ADS)

Shimizu, Kazunori; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Process for Administering Distributed Academic Competitions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feibush, Eliot

2010-02-04

Currently, academic-type competitions are scored using a combination of timer clocks, entries on paper, and individual computers to consolidate individual entries. Such a system is unwieldy, time-consuming, and depends on the individual computer skills that might be present amount the competition administrators. The new Academic Competition Software combines digital clocks, along with a scoring system that permits different point values for different types of questions. Bonus or ‚Âœtoss-up‚ questions can be monitored during the competition, using a subtimer system. All data is consolidated on the fly and the system can be operated by a single person. Results from different sitesmore » (rooms) can be added in as well. As such, the software is extremely flexible. It is anticipated that this new software will be useful for‚Science or Science Olympiad type competitions held in many high schools and colleges, as well as for preparation and training for such competitions.« less

Formal Techniques for Synchronized Fault-Tolerant Systems

NASA Technical Reports Server (NTRS)

DiVito, Ben L.; Butler, Ricky W.

1992-01-01

We present the formal verification of synchronizing aspects of the Reliable Computing Platform (RCP), a fault-tolerant computing system for digital flight control applications. The RCP uses NMR-style redundancy to mask faults and internal majority voting to purge the effects of transient faults. The system design has been formally specified and verified using the EHDM verification system. Our formalization is based on an extended state machine model incorporating snapshots of local processors clocks.

Multifunction audio digitizer. [producing direct delta and pulse code modulation

NASA Technical Reports Server (NTRS)

Monford, L. G., Jr. (Inventor)

1974-01-01

An illustrative embodiment of the invention includes apparatus which simultaneously produces both direct delta modulation and pulse code modulation. An input signal, after amplification, is supplied to a window comparator which supplies a polarity control signal to gate the output of a clock to the appropriate input of a binary up-down counter. The control signals provide direct delta modulation while the up-down counter output provides pulse code modulation.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Hardware description ADSP-21020 40-bit floating point DSP as designed in a remotely controlled digital CW Doppler radar

NASA Astrophysics Data System (ADS)

Morrison, R. E.; Robinson, S. H.

A continuous wave Doppler radar system has been designed which is portable, easily deployed, and remotely controlled. The heart of this system is a DSP/control board using Analog Devices ADSP-21020 40-bit floating point digital signal processor (DSP) microprocessor. Two 18-bit audio A/D converters provide digital input to the DSP/controller board for near real time target detection. Program memory for the DSP is dual ported with an Intel 87C51 microcontroller allowing DSP code to be up-loaded or down-loaded from a central controlling computer. The 87C51 provides overall system control for the remote radar and includes a time-of-day/day-of-year real time clock, system identification (ID) switches, and input/output (I/O) expansion by an Intel 82C55 I/O expander.

Beam-Switch Transient Effects in the RF Path of the ICAPA Receive Phased Array Antenna

NASA Technical Reports Server (NTRS)

Sands, O. Scott

2003-01-01

When the beam of a Phased Array Antenna (PAA) is switched from one pointing direction to another, transient effects in the RF path of the antenna are observed. Testing described in the report has revealed implementation-specific transient effects in the RF channel that are associated with digital clocking pulses that occur with transfer of data from the Beam Steering Controller (BSC) to the digital electronics of the PAA under test. The testing described here provides an initial assessment of the beam-switch phenomena by digitally acquiring time series of the RF communications channel, under CW excitation, during the period of time that the beam switch transient occurs. Effects are analyzed using time-frequency distributions and instantaneous frequency estimation techniques. The results of tests conducted with CW excitation supports further Bit-Error-Rate (BER) testing of the PAA communication channel.

Distributed Timing and Localization (DiGiTaL)

NASA Technical Reports Server (NTRS)

D'Amico, Simone; Hunter, Roger C.; Baker, Christopher

2017-01-01

The Distributed Timing and Localization (DiGiTaL) system provides nano satellite formations with unprecedented,centimeter-level navigation accuracy in real time and nanosecond-level time synchronization. This is achieved through the integration of a multi-constellation Global Navigation Satellite System (GNSS) receiver, a Chip-Scale Atomic Clock (CSAC), and a dedicated Inter-Satellite Link (ISL). In comparison, traditional single spacecraft GNSS navigation solutions are accurate only to the meter-level due to the sole usage of coarse pseudo-range measurements. To meet the strict requirements of future miniaturized distributed space systems, DiGiTaL uses powerful error-cancelling combinations of raw carrier-phase measurements which are exchanged between the swarming nano satellites through a decentralized network. A reduced-dynamics estimation architecture on board each individual nano satellite processes the resulting millimeter-level noise measurements to reconstruct the fullformation state with high accuracy.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

This paper suggests a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to) zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is to demonstrate how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

The objective of this paper is to motivate a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include: (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to): zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is on demonstrating how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

2017-02-01

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

KSC-06pd1104

NASA Image and Video Library

2006-06-15

KENNEDY SPACE CENTER, FLA. - STS-121 Commander Steven Lindsey takes his turn driving an M-113, which is an armored personnel carrier. The STS-121 crew is taking turns driving the M-113 as part of Terminal Countdown Demonstration Test activities, which include emergency egress training from the pad and a simulated countdown. Mission STS-121 is designated for launch on July 1. Photo credit: NASA/Kim Shiflett

KSC-06pd1107

NASA Image and Video Library

2006-06-15

KENNEDY SPACE CENTER, FLA. - STS-121 Mission Specialist Michael Fossum takes his turn in an M-113, which is an armored personnel carrier. The STS-121 crew is taking turns driving the M-113 as part of Terminal Countdown Demonstration Test activities, which include emergency egress training from the pad and a simulated countdown. Mission STS-121 is designated for launch on July 1. Photo credit: NASA/Kim Shiflett

STS-82 Mission Specialist Steven L. Smith during TCDT

NASA Technical Reports Server (NTRS)

1997-01-01

STS-82 Mission Specialist Steven L. Smith adjusts the glove of his launch and entry space suit during a practice countdown at KSC. Smith and the other six STS-82 crew members are at KSC to participate in the Terminal Countdown Demonstration Test (TCDT), a dress rehearsal for launch. STS-82 will be the second Hubble Space Telescope servicing mission. Liftoff is targeted for February 11.

Firing Room 2 in Launch Control Center at KSC during Apollo 9 countdown test

NASA Image and Video Library

1969-02-23

S69-25880 (23 Feb. 1969) --- Overall view of Firing Room 2 in the Launch Control Center, Launch Complex 39, Kennedy Space Center, during an Apollo 9 Countdown Demonstration Test. Astronauts James A. McDivitt, David R. Scott, and Russell L. Schweickart were participating in a training exercise in preparation for their scheduled 10-day Earth-orbital space mission.

KSC-08pd3440

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialists (from left) Sandra Magnus, Shane Kimbrough and Heidemarie Stefanyshyn-Piper make their way to the slidewire baskets on the 195-foot level of the fixed service structure after taking part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3428

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialist Sandra Magnus (right) gets ready to enter space shuttle Endeavour. At left is a member of the Closeout Crew, Travis Thompson. The crew will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3439

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialists (top to bottom) Heidemarie Stefanyshyn-Piper, Shane Kimbrough and Sandra Magnus are strapped in their seats in space shuttle Endeavour. They and other crew members will take part in a simulated launch countdown. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3443

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members climb into a slidewire basket on the 195-foot level of the fixed service structure. They have taken part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-05PD-0851

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Commander Eileen Collins takes her turn at driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. Standing behind her is Capt. George Hoggard, who is astronaut rescue team leader. On the left is KSC videographer Glen Benson. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0853

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Soichi Noguchi drives an M- 113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. Behind him at left is Capt. George Hoggard, who is astronaut rescue team leader. Noguchi is with the Japan Aerospace Exploration Agency. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-08pd0508

NASA Image and Video Library

2008-02-24

KENNEDY SPACE CENTER, FLA. -- At NASA Kennedy Space Center's Launch Pad 39A, STS-123 Mission Specialist Takao Doi of the Japan Aerospace Exploration Agency receives instruction on the operation of a slidewire basket during emergency egress training. The crew is at Kennedy for a full launch dress rehearsal, known as the terminal countdown demonstration test or TCDT. The terminal countdown demonstration test provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on a 16-day mission to the International Space Station. On the mission, Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

KSC-08pd0502

NASA Image and Video Library

2008-02-23

KENNEDY SPACE CENTER, FLA. -- In NASA Kennedy Space Center's News Room, STS-123 Mission Specialist Takao Doi, of the Japan Aerospace Exploration Agency, shows his enthusiasm for his upcoming flight during an interview. The crew for space shuttle Endeavour's STS-123 mission is at Kennedy for a full launch dress rehearsal, known as the terminal countdown demonstration test or TCDT. The terminal countdown demonstration test provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on a 16-day mission to the International Space Station. On the mission, Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Amanda Diller

KSC-08pd0555

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- The crew of mission STS-123 show their readiness to take part in a simulated launch countdown, the culmination of the terminal countdown demonstration test, or TCDT. From left are Mission Specialists Rick Linnehan, Takao Doi, Robert L. Behnken and Mike Foreman, Pilot Gregory H. Johnson, Mission Specialist Garrett Reisman and Commander Dominic Gorie. The TCDT provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Space shuttle Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

Digital frequency synthesizer for radar astronomy

NASA Technical Reports Server (NTRS)

Sadr, R.; Satorius, E.; Robinett, L.; Olson, E.

1990-01-01

The digital frequency synthesizer (DFS) is an integral part of the programmable local oscillator (PLO) which is being developed for the NASA's Deep Space Network (DSN) and radar astronomy. Here, the theory of operation and the design of the DFS are discussed, and the design parameters in application for the Goldstone Solar System Radar (GSSR) are specified. The spectral purity of the DFS is evaluated by analytically evaluating the output spectrum of the DFS. A novel architecture is proposed for the design of the DFS with a frequency resolution of 1/2(exp 48) of the clock frequency (0.35 mu Hz at 100 MHz), a phase resolution of 0.0056 degrees (16 bits), and a frequency spur attenuation of -96 dBc.

Aerospace Applications Conference, Steamboat Springs, CO, Feb. 1-8, 1986, Digest

NASA Astrophysics Data System (ADS)

The present conference considers topics concerning the projected NASA Space Station's systems, digital signal and data processing applications, and space science and microwave applications. Attention is given to Space Station video and audio subsystems design, clock error, jitter, phase error and differential time-of-arrival in satellite communications, automation and robotics in space applications, target insertion into synthetic background scenes, and a novel scheme for the computation of the discrete Fourier transform on a systolic processor. Also discussed are a novel signal parameter measurement system employing digital signal processing, EEPROMS for spacecraft applications, a unique concurrent processor architecture for high speed simulation of dynamic systems, a dual polarization flat plate antenna, Fresnel diffraction, and ultralinear TWTs for high efficiency satellite communications.

Simultaneously precise frequency transfer and time synchronization using feed-forward compensation technique via 120 km fiber link.

PubMed

Chen, Xing; Lu, Jinlong; Cui, Yifan; Zhang, Jian; Lu, Xing; Tian, Xusheng; Ci, Cheng; Liu, Bo; Wu, Hong; Tang, Tingsong; Shi, Kebin; Zhang, Zhigang

2015-12-22

Precision time synchronization between two remote sites is desired in many applications such as global positioning satellite systems, long-baseline interferometry, coherent radar detection and fundamental physics constant measurements. The recently developed frequency dissemination technologies based on optical fiber link have improved the transfer instability to the level of 10(-19)/day at remote location. Therefore it is possible to keep clock oscillation at remote locations continuously corrected, or to reproduce a "virtual" clock on the remote location. However the initial alignment and the correction of 1 pps timing signal from time to time are still required, besides the highly stabilized clock frequency transfer between distant locations. Here we demonstrate a time synchronization based on an ultra-stable frequency transfer system via 120-km commercial fiber link by transferring an optical frequency comb. Both the phase noise compensation in frequency dissemination and temporal basis alignment in time synchronization were implemented by a feed-forward digital compensation (FFDC) technique. The fractional frequency instability was measured to be 6.18 × 10(-20) at 2000 s. The timing deviation of time synchronization was measured to be 0.6 ps in 1500 s. This technique also can be applied in multi-node fiber network topology.

Simultaneously precise frequency transfer and time synchronization using feed-forward compensation technique via 120 km fiber link

PubMed Central

Chen, Xing; Lu, Jinlong; Cui, Yifan; Zhang, Jian; Lu, Xing; Tian, Xusheng; Ci, Cheng; Liu, Bo; Wu, Hong; Tang, Tingsong; Shi, Kebin; Zhang, Zhigang

2015-01-01

Precision time synchronization between two remote sites is desired in many applications such as global positioning satellite systems, long-baseline interferometry, coherent radar detection and fundamental physics constant measurements. The recently developed frequency dissemination technologies based on optical fiber link have improved the transfer instability to the level of 10−19/day at remote location. Therefore it is possible to keep clock oscillation at remote locations continuously corrected, or to reproduce a “virtual” clock on the remote location. However the initial alignment and the correction of 1 pps timing signal from time to time are still required, besides the highly stabilized clock frequency transfer between distant locations. Here we demonstrate a time synchronization based on an ultra-stable frequency transfer system via 120-km commercial fiber link by transferring an optical frequency comb. Both the phase noise compensation in frequency dissemination and temporal basis alignment in time synchronization were implemented by a feed-forward digital compensation (FFDC) technique. The fractional frequency instability was measured to be 6.18 × 10−20 at 2000 s. The timing deviation of time synchronization was measured to be 0.6 ps in 1500 s. This technique also can be applied in multi-node fiber network topology. PMID:26691731

STS-27 Atlantis, OV-104, terminal countdown demonstration test (TCDT) at KSC

NASA Image and Video Library

1988-11-14

S88-53244 (14 Nov 1988) --- The crewmembers for STS-27 leave the operations and checkout (O&C) building en route to a transfer van that will take them to Launch Pad 39B for their terminal countdown demonstration test. From the front to the rear are astronauts Robert L. Gibson, Guy S. Gardner, William M. Shepherd, Richard M. (Mike) Mullane and Jerry L. Ross.

KSC-2009-4470

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Jose Hernandez takes his turn driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4471

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Jose Hernandez has completed his turn driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4465

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Nicole Stott has completed her turn at driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4466

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Patrick Forrester has completed his turn at driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4468

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist John "Danny" Olivas has completed his turn driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4469

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist John "Danny" Olivas takes his turn driving an M-113 armored personnel carrier. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

Apollo 9 crew prepares to participate in Countdown Demonstration Test

NASA Image and Video Library

1969-02-23

S69-25488 (23 Feb. 1969) --- Interior view of the White Room at Pad A, Launch Complex 39, Kennedy Space Center (KSC), during an Apollo 9 Countdown Demonstration Test (CDDT). Astronauts James A. McDivitt, commander; David R. Scott, command module pilot; and Russell L. Schweickart, lunar module pilot, were participating in a dress rehearsal in preparation for their scheduled 10-day Earth-orbital space mission.

Mineral resource of the month: cultured quartz crystal

USGS Publications Warehouse

,

2008-01-01

The article presents information on cultured quartz crystals, a mineral used in mobile phones, computers, clocks and other devices controlled by digital circuits. Cultured quartz, which is synthetically produced in large pressurized vessels known as autoclaves, is useful in electronic circuits for precise filtration, frequency control and timing for consumer and military use. Several ingredients are used in producing cultured quartz, including seed crystals, lascas, a solution of sodium hydroxide or sodium carbonate, lithium salts and deionized water.

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Method and apparatus for enhancing microchannel plate data

DOEpatents

Thoe, R.S.

1983-10-24

A method and apparatus for determining centroid channel locations are disclosed for use in a system activated by one or more multichannel plates and including a linear diode array providing channels of information 1, 2, ...,n, ..., N containing signal amplitudes A/sub n/. A source of analog A/sub n/ signals, and a source of digital clock signals n, are provided. Non-zero A/sub n/ values are detected in a discriminator. A digital signal representing p, the value of n immediately preceding that whereat A/sub n/ takes its first non-zero value, is generated in a scaler. The analog A/sub n/ signals are converted to digital in an analog to digital converter. The digital A/sub n/ signals are added to produce a digital ..sigma..A/sub n/ signal in a full adder. Digital 1, 2, ..., m signals representing the number of non-zero A/sub n/ are produced by a discriminator pulse counter. Digital signals representing 1 A/sub p+1/, 2 A/sub p+2/, ..., m A/sub p+m/ are produced by pairwise multiplication in multiplier. These signal are added in multiplier summer to produce a digital ..sigma..nA/sub n/ - p..sigma..A/sub n/ signal. This signal is divided by the digital ..sigma..A/sub n/ signal in divider to provide a digital (..sigma..nA/sub n//..sigma..A/sub n/) -p signal. Finally, this last signal is added to the digital p signal in an offset summer to provide ..sigma..nA/sub n//..sigma..A/sub n/, the centroid channel locations.

An Implantable Neural Sensing Microsystem with Fiber-Optic Data Transmission and Power Delivery

PubMed Central

Park, Sunmee; Borton, David A.; Kang, Mingyu; Nurmikko, Arto V.; Song, Yoon-Kyu

2013-01-01

We have developed a prototype cortical neural sensing microsystem for brain implantable neuroengineering applications. Its key feature is that both the transmission of broadband, multichannel neural data and power required for the embedded microelectronics are provided by optical fiber access. The fiber-optic system is aimed at enabling neural recording from rodents and primates by converting cortical signals to a digital stream of infrared light pulses. In the full microsystem whose performance is summarized in this paper, an analog-to-digital converter and a low power digital controller IC have been integrated with a low threshold, semiconductor laser to extract the digitized neural signals optically from the implantable unit. The microsystem also acquires electrical power and synchronization clocks via optical fibers from an external laser by using a highly efficient photovoltaic cell on board. The implantable unit employs a flexible polymer substrate to integrate analog and digital microelectronics and on-chip optoelectronic components, while adapting to the anatomical and physiological constraints of the environment. A low power analog CMOS chip, which includes preamplifier and multiplexing circuitry, is directly flip-chip bonded to the microelectrode array to form the cortical neurosensor device. PMID:23666130

Event management for large scale event-driven digital hardware spiking neural networks.

PubMed

Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

2013-09-01

The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

Self-Calibration Approach for Mixed Signal Circuits in Systems-on-Chip

NASA Astrophysics Data System (ADS)

Jung, In-Seok

MOSFET scaling has served industry very well for a few decades by proving improvements in transistor performance, power, and cost. However, they require high test complexity and cost due to several issues such as limited pin count and integration of analog and digital mixed circuits. Therefore, self-calibration is an excellent and promising method to improve yield and to reduce manufacturing cost by simplifying the test complexity, because it is possible to address the process variation effects by means of self-calibration technique. Since the prior published calibration techniques were developed for a specific targeted application, it is not easy to be utilized for other applications. In order to solve the aforementioned issues, in this dissertation, several novel self-calibration design techniques in mixed-signal mode circuits are proposed for an analog to digital converter (ADC) to reduce mismatch error and improve performance. These are essential components in SOCs and the proposed self-calibration approach also compensates the process variations. The proposed novel self-calibration approach targets the successive approximation (SA) ADC. First of all, the offset error of the comparator in the SA-ADC is reduced using the proposed approach by enabling the capacitor array in the input nodes for better matching. In addition, the auxiliary capacitors for each capacitor of DAC in the SA-ADC are controlled by using synthesized digital controller to minimize the mismatch error of the DAC. Since the proposed technique is applied during foreground operation, the power overhead in SA-ADC case is minimal because the calibration circuit is deactivated during normal operation time. Another benefit of the proposed technique is that the offset voltage of the comparator is continuously adjusted for every step to decide one-bit code, because not only the inherit offset voltage of the comparator but also the mismatch of DAC are compensated simultaneously. Synthesized digital calibration control circuit operates as fore-ground mode, and the controller has been highly optimized for low power and better performance with simplified structure. In addition, in order to increase the sampling clock frequency of proposed self-calibration approach, novel variable clock period method is proposed. To achieve high speed SAR operation, a variable clock time technique is used to reduce not only peak current but also die area. The technique removes conversion time waste and extends the SAR operation speed easily. To verify and demonstrate the proposed techniques, a prototype charge-redistribution SA-ADCs with the proposed self-calibration is implemented in a 130nm standard CMOS process. The prototype circuit's silicon area is 0.0715 mm 2 and consumers 4.62mW with 1.2V power supply.

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.

PubMed

Son, Hyunwoo; Cho, Hwasuk; Koo, Jahyun; Ji, Youngwoo; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

2017-06-01

This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator, and a clocked comparator is followed for quantization. Without any continuous-time feedback circuit, the converter performs a first-order noise shaping of the quantization error. In order to minimize static power consumption, the proposed circuit employs a single-ended current-steering digital-to-analog converter which flows only the same current as the input. By adopting a switching noise averaging algorithm, our dynamic element matching not only mitigates mismatch of current sources in the current-steering DAC, but also makes the effect of dynamic switching noise become an input-independent constant. The implemented circuit in 0.35 μm CMOS converts the current input with a range of 2.8 μ A to 15 b digital output in about 4 ms, showing a DNL of +0.24/-0.25 LSB and an INL of + 1.98/-1.98 LSB while consuming 16.8 μW.

KSC-2009-4472

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Christer Fuglesang takes his turn driving an M-113 armored personnel carrier. Fuglesang represents the European Space Agency. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-2009-4473

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Christer Fuglesang has completed his turn driving an M-113 armored personnel carrier. Fuglesang represents the European Space Agency. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

Air-to-Ground Target Acquisition Source Book: A Review of the Literature

DTIC Science & Technology

1974-09-30

Verbal Countdown and No- Countdown Conditions . . . ’ 5-50 S-27 The Effects on Target Recognitio Proficiency ofVarying ’ Scn’ Time and of Display Aids...Dad(D)d4Wat4ao~tt Inter’ J194 ttre’tlo vsvisbleo (1) tsit.n logo proaraiti to olulsto fixed IOv thrl"i.,l. cloture ’A tarpato at 4C1slre4 rtes (I

STS-87 Mission Specialist Chawla talks to the media during TCDT

NASA Technical Reports Server (NTRS)

1997-01-01

Kalpana Chawla, Ph.D., a mission specialist of the STS-87 crew, participates in a news briefing at Launch Pad 39B during the Terminal Countdown Demonstration Test (TCDT) at Kennedy Space Center (KSC). First-time Shuttle flier Dr. Chawla reported for training as an astronaut at Johnson Space Center in 1995. She has a doctorate in aerospace engineering from the University of Colorado. The TCDT is held at KSC prior to each Space Shuttle flight providing the crew of each mission opportunities to participate in simulated countdown activities. The TCDT ends with a mock launch countdown culminating in a simulated main engine cut-off. The crew also spends time undergoing emergency egress training exercises at the pad and has an opportunity to view and inspect the payloads in the orbiter's payload bay. STS-87 is scheduled for launch Nov. 19 aboard the Space Shuttle Columbia from pad 39B at KSC.

STS-100 crew take a group photo before walkou

NASA Technical Reports Server (NTRS)

2001-01-01

KENNEDY SPACE CENTER, Fla. - The STS-100 crew pauses for a photo before walkout and the ride to Launch Pad 39A for a simulated countdown. Standing, from left, are Mission Specialists Scott E. Parazynski, Umberto Guidoni, John L. Phillips, Yuri V. Lonchakov and Chris A. Hadfield; Commander Kent V. Rominger; and Pilot Jeffrey S. Ashby. The STS-100 crew is at KSC for Terminal Countdown Demonstration Test activities that include emergency escape training at the pad and the simulated launch countdown. The mission is carrying the Multi-Purpose Logistics Module Raffaello and the SSRMS, to the International Space Station. Raffaello carries six system racks and two storage racks for the U.S. Lab. The SSRMS is crucial to the continued assembly of the orbiting complex. Launch of mission STS-100 is scheduled for April 19 at 2:41 p.m. EDT from Launch Pad 39A.

KSC-08pd3431

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – In the White Room on Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members enjoy talking with the Closeout Crew as they suit up. In the foreground is Mission Specialist Heidemarie Stefanyshyn-Piper; behind her is Pilot Eric Boe. They and other crew members will take part in a simulated launch countdown after entering space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3441

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 Mission Specialists Sandra Magnus, Shane Kimbrough and Heidemarie Stefanyshyn-Piper have taken their seats in a slidewire basket, part of the emergency escape system on the 195-foot level of the fixed service structure. They have taken part in a simulated countdown in space shuttle Endeavour. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3446

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – On Launch Pad 39A at NASA's Kennedy Space Center in Florida, STS-126 crew members gather near the slidewire baskets on the 195-foot level of the fixed service structure. From left are Mission Specialists Donald Pettit, Sandra Magnus, Heidemarie Stefanyshyn-Piper and Steve Bowen. They have taken part in a simulated countdown in space shuttle Endeavour followed by emergency escape procedures. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Troy Cryder

KSC-08pd3425

NASA Image and Video Library

2008-10-29

CAPE CANAVERAL, Fla. – Dressed in their launch-and-entry suits, the STS-126 crew members eagerly exit the Operations and Checkout Building at NASA's Kennedy Space Center in Florida. They will head to Launch Pad 39A for a simulated countdown in space shuttle Endeavour. Clockwise from left are Pilot Eric Boe, Mission Specialists Steve Bowen, Shane Kimbrough, Sandra Magnus, Heidemarie Stefanyshyn-Piper and Donald Pettit, and Commander Chris Ferguson. The crew is at Kennedy to take part in the Terminal Countdown Demonstration Test, which includes equipment familiarization, emergency exit training and the simulated countdown. On the STS-126 mission, space shuttle Endeavour's crew will deliver equipment and supplies to the International Space Station in preparation for expansion from a three- to six-person resident crew aboard the complex. The mission also will include four spacewalks to service the station’s Solar Alpha Rotary Joints. Endeavour is targeted to launch Nov. 14. Photo credit: NASA/Kim Shiflett

KSC-05PD-0847

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Charles Camarda is getting ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. Behind him are Mission Specialist Stephen Robinson and Capt. George Hoggard, who is astronaut rescue team leader, and, at right, Commander Eileen Collins. The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-05PD-0852

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. During Terminal Countdown Demonstration Test (TCDT) activities at NASAs Kennedy Space Center, STS-114 Mission Specialist Soichi Noguchi is ready to practice driving an M-113, an armored personnel carrier that is used for speedy departure from the launch pad in an emergency. Behind him at left is Capt. George Hoggard, who is astronaut rescue team leader. Noguchi is with the Japan Aerospace Exploration Agency.The TCDT is held at KSC prior to each Space Shuttle flight. It provides the crew of each mission an opportunity to participate in simulated countdown activities. The test ends with a mock launch countdown culminating in a simulated main engine cutoff. The crew also spends time undergoing emergency egress training exercises at the launch pad. STS-114 is the first Return to Flight mission to the International Space Station. The launch window extends July 13 through July 31.

KSC-00pp0078

NASA Image and Video Library

2000-01-14

STS-99 Pilot Dominic Gorie goes through countdown procedures on the flight deck aboard the Space Shuttle Endeavour as part of Terminal Countdown Demonstration Test (TCDT) activities for the mission. The TCDT includes a simulation of the final launch countdown. STS-99 is the Shuttle Radar Topography Mission, which will chart a new course, using two antennae and a 200-foot-long section of space station-derived mast protruding from the payload bay to produce unrivaled 3-D images of the Earth's surface. The result of the Shuttle Radar Topography Mission could be close to 1 trillion measurements of the Earth's topography. Besides contributing to the production of better maps, these measurements could lead to improved water drainage modeling, more realistic flight simulators, better locations for cell phone towers, and enhanced navigation safety. Launch of Endeavour on the 11-day mission is scheduled for Jan. 31 at 12:47 p.m. EST

KSC-00pp0076

NASA Image and Video Library

2000-01-14

STS-99 Mission Specialist Mamoru Mohri (Ph.D.) takes his seat inside Space Shuttle Endeavour for a practice launch countdown during Terminal Countdown Demonstration Test (TCDT) activities for the mission. Mohri is with the National Space Development Agency (NASDA) of Japan. The TCDT includes a simulation of the final launch countdown. STS-99 is the Shuttle Radar Topography Mission, which will chart a new course, using two antennae and a 200-foot-long section of space station-derived mast protruding from the payload bay to produce unrivaled 3-D images of the Earth's surface. The result of the Shuttle Radar Topography Mission could be close to 1 trillion measurements of the Earth's topography. Besides contributing to the production of better maps, these measurements could lead to improved water drainage modeling, more realistic flight simulators, better locations for cell phone towers, and enhanced navigation safety. Launch of Endeavour on the 11-day mission is scheduled for Jan. 31 at 12:47 p.m. EST

KSC-00pp0080

NASA Image and Video Library

2000-01-14

STS-99 Commander Kevin Kregel goes through countdown procedures on the flight deck aboard the Space Shuttle Endeavour during Terminal Countdown Demonstration Test (TCDT) activities for the mission. The TCDT includes a simulation of the final launch countdown. STS-99 is the Shuttle Radar Topography Mission, which will chart a new course, using two antennae and a 200-foot-long section of space station-derived mast protruding from the payload bay to produce unrivaled 3-D images of the Earth's surface. The result of the Shuttle Radar Topography Mission could be close to 1 trillion measurements of the Earth's topography. Besides contributing to the production of better maps, these measurements could lead to improved water drainage modeling, more realistic flight simulators, better locations for cell phone towers, and enhanced navigation safety. Launch of Endeavour on the 11-day mission is scheduled for Jan. 31 at 12:47 p.m. EST

KSC-00pp0079

NASA Image and Video Library

2000-01-14

STS-99 Mission Specialist Gerhard Thiele, who is with the European Space Agency, goes through countdown procedures aboard the Space Shuttle Endeavour during Terminal Countdown Demonstration Test (TCDT) activities for the mission. The TCDT includes a simulation of the final launch countdown. STS-99 is the Shuttle Radar Topography Mission, which will chart a new course, using two antennae and a 200-foot-long section of space station-derived mast protruding from the payload bay to produce unrivaled 3-D images of the Earth's surface. The result of the Shuttle Radar Topography Mission could be close to 1 trillion measurements of the Earth's topography. Besides contributing to the production of better maps, these measurements could lead to improved water drainage modeling, more realistic flight simulators, better locations for cell phone towers, and enhanced navigation safety. Launch of Endeavour on the 11-day mission is scheduled for Jan. 31 at 12:47 p.m. EST

KSC-97PC1603

NASA Image and Video Library

1997-11-04

Kalpana Chawla, Ph.D., a mission specialist of the STS-87 crew, participates in a news briefing at Launch Pad 39B during the Terminal Countdown Demonstration Test (TCDT) at Kennedy Space Center (KSC). First-time Shuttle flier Dr. Chawla reported for training as an astronaut at Johnson Space Center in 1995. She has a doctorate in aerospace engineering from the University of Colorado. The TCDT is held at KSC prior to each Space Shuttle flight providing the crew of each mission opportunities to participate in simulated countdown activities. The TCDT ends with a mock launch countdown culminating in a simulated main engine cut-off. The crew also spends time undergoing emergency egress training exercises at the pad and has an opportunity to view and inspect the payloads in the orbiter's payload bay. STS-87 is scheduled for launch Nov. 19 aboard the Space Shuttle Columbia from pad 39B at KSC

A COMPARISON OF THE EFFECTS OF BRIEF RULES, A TIMER, AND PREFERRED TOYS ON SELF-CONTROL

PubMed Central

Newquist, Matthew H; Dozier, Claudia L; Neidert, Pamela L

2012-01-01

Some children make impulsive choices (i.e., choose a small but immediate reinforcer over a large but delayed reinforcer). Previous research has shown that delay fading, providing an alternative activity during the delay, teaching participants to repeat a rule during the delay, combining delay fading with an alternative activity, and combining delay fading with a countdown timer are effective for increasing self-control (i.e., choosing the large but delayed reinforcer over the small but immediate reinforcer). The purpose of the current study was to compare the effects of various interventions in the absence of delay fading (i.e., providing brief rules, providing a countdown timer during the delay, or providing preferred toys during the delay) on self-control. Results suggested that providing brief rules or a countdown timer during the delay was ineffective for enhancing self-control. However, providing preferred toys during the delay effectively enhanced self-control. PMID:23060664

KSC-08pd0515

NASA Image and Video Library

2008-02-24

KENNEDY SPACE CENTER, FLA. -- At NASA Kennedy Space Center's Launch Pad 39A, the crew for space shuttle Endeavour's STS-123 mission receives instruction on the operation of a slidewire basket during emergency egress training. In the basket are Mission Specialists Takao Doi of the Japan Aerospace Exploration Agency, Garrett Reisman and Rick Linnehan. The crew is at Kennedy for a full launch dress rehearsal, known as the terminal countdown demonstration test or TCDT. The terminal countdown demonstration test provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on a 16-day mission to the International Space Station. On the mission, Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

KSC-08pd0495

NASA Image and Video Library

2008-02-24

KENNEDY SPACE CENTER, FLA. -- At NASA Kennedy Space Center's Launch Pad 39A, a mission specialist on space shuttle Endeavour's STS-123 mission, Takao Doi of the Japan Aerospace Exploration Agency, prepares to take questions from the media during a break from emergency egress training. The crew is at Kennedy for a full launch dress rehearsal, known as the terminal countdown demonstration test or TCDT. The terminal countdown demonstration test provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on a 16-day mission to the International Space Station. On the mission, Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

KSC-08pd0569

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- In the White Room on NASA Kennedy Space Center's Launch Pad 39A, STS-123 Mission Specialist Takao Doi, who represents the Japan Aerospace Exploration Agency, gets help with his launch and entry suit before entering space shuttle Endeavour. Behind him is Mission Specialist Robert L. Behnken. Both are getting ready for the simulated launch countdown, which is the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Jim Grossmann

KSC-08pd0568

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- In the White Room on NASA Kennedy Space Center's Launch Pad 39A, STS-123 Mission Specialist Takao Doi, who represents the Japan Aerospace Exploration Agency, gets help with his launch and entry suit before entering space shuttle Endeavour. He and the other STS-123 crew members are getting ready for the simulated launch countdown, which is the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various countdown activities, including equipment familiarization and emergency egress training. Endeavour is targeted to launch at 2:28 a.m. EDT March 11 on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Jim Grossmann

KSC-08pd0554

NASA Image and Video Library

2008-02-25

KENNEDY SPACE CENTER, FLA. -- The crew of mission STS-123 provides a photo opportunity in front of the Astrovan for spectators before heading out to NASA Kennedy Space Center's Launch Pad 39A. From left are Mission Specialists Rick Linnehan, Takao Doi, Robert L. Behnken and Mike Foreman, Pilot Gregory H. Johnson, Mission Specialist Garrett Reisman and Commander Dominic Gorie. The crew is taking part in a simulated launch countdown, the culmination of the terminal countdown demonstration test, or TCDT. The TCDT provides astronauts and ground crews with an opportunity to participate in various simulated countdown activities, including equipment familiarization and emergency training. Space shuttle Endeavour is targeted to launch March 11 at 2:28 a.m. EDT on the 16-day STS-123 mission to the International Space Station. Endeavour and its crew will deliver the first section of the Japan Aerospace Exploration Agency's Kibo laboratory and the Canadian Space Agency's two-armed robotic system, Dextre. Photo credit: NASA/Kim Shiflett

A comparison of the effects of brief rules, a timer, and preferred toys on self-control.

PubMed

Newquist, Matthew H; Dozier, Claudia L; Neidert, Pamela L

2012-01-01

Some children make impulsive choices (i.e., choose a small but immediate reinforcer over a large but delayed reinforcer). Previous research has shown that delay fading, providing an alternative activity during the delay, teaching participants to repeat a rule during the delay, combining delay fading with an alternative activity, and combining delay fading with a countdown timer are effective for increasing self-control (i.e., choosing the large but delayed reinforcer over the small but immediate reinforcer). The purpose of the current study was to compare the effects of various interventions in the absence of delay fading (i.e., providing brief rules, providing a countdown timer during the delay, or providing preferred toys during the delay) on self-control. Results suggested that providing brief rules or a countdown timer during the delay was ineffective for enhancing self-control. However, providing preferred toys during the delay effectively enhanced self-control.

STS-92 crew leave the O&C for Launch Pad 39A

NASA Technical Reports Server (NTRS)

2000-01-01

The STS-92 crew exits the Operations and Checkout Building on their way to the Astrovan and Launch Pad 39A for a simulated countdown. Walking left to right are (foreground) Mission Specialists Koichi Wakata of Japan, Peter J.K. 'Jeff' Wisoff and Leroy Chiao; and Pilot Pamela Ann Melroy. Behind them are Mission Specialists Michael E. Lopez-Alegria and William S. McArthur Jr.; and Commander Brian Duffy. The crew is taking part in Terminal Countdown Demonstration Test activities that provide emergency egress training, opportunities to inspect the mission payload, and the simulated countdown. STS-92 is scheduled to launch Oct. 5 at 9:38 p.m. EDT on the fifth flight to the International Space Station. It will carry two elements of the Space Station, the Integrated Truss Structure Z1 and the third Pressurized Mating Adapter. The mission is also the 100th flight in the Shuttle program.

The STS-97 crew leaves O&C for Launch Pad 39B

NASA Technical Reports Server (NTRS)

2000-01-01

The STS-97 crew leaves the O&C Building on their way to Launch Pad 39B for a simulated launch countdown. Commander Brent Jett (right) leads the way with Pilot Mike Bloomfield behind him. Taking up the rear are (left) Mission Specialists Carlos Noriega, Joe Tanner and (right) Marc Garneau, who is with the Canadian Space Agency. The crew is taking part in Terminal Countdown Demonstration Test activities that include emergency egress training, familiarization with the payload, and the simulated launch countdown. Mission STS-97is the sixth construction flight to the International Space Station. Its payload includes the P6 Integrated Truss Structure and a photovoltaic (PV) module, with giant solar arrays that will provide power to the Station. The mission includes two spacewalks to complete the solar array connections. STS-97 is scheduled to launch Nov. 30 at about 10:05 p.m. EST.

STS-103 crew practice emergency egress in the slidewire basket

NASA Technical Reports Server (NTRS)

1999-01-01

In the slidewire basket on Launch Pad 39B, STS-103 Mission Specialists Jean-Frangois Clervoy of France (left) and Steven L. Smith take a break to pose for the photographer. The baskets are part of the emergency egress system for persons in the Shuttle vehicle or on the Rotating Service Structure. Seven slidewires extend from the orbiter access arm, with a netted, flatbottom basket suspended from each wire. The STS-103 crew are taking part in Terminal Countdown Demonstration Test (TCDT) activities in preparation for launch. The other crew members are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. The TCDT provides the crew with the emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 MS Clervoy and Pilot Kelly inspect slideware basket at Pad 39B

NASA Technical Reports Server (NTRS)

1999-01-01

At Launch Pad 39B. STS-103 Mission Specialist Jean-Frangois Clervoy of France, who is with the European Space Agency (ESA), and Pilot Steven J. Kelly inspect the slidewire basket, part of the emergency egress system for persons in the Shuttle vehicle or on the Rotating Service Structure. Seven slidewires extend from the orbiter access arm, with a netted, flatbottom basket suspended from each wire. The STS-103 crew have been participating in Terminal Countdown Demonstration Test (TCDT) activities at KSC. Other crew members are Commander Curtis L. Brown Jr. and Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Claude Nicollier of Switzerland, also with ESA. The TCDT provides the crew with the emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew practice emergency egress in the slidewire basket

NASA Technical Reports Server (NTRS)

1999-01-01

Standing left to right, STS-103 Pilot Scott J. Kelly, Commander Curtis L. Brown Jr., and Mission Specialist Jean-Frangois Clervoy of France take a break during practice using the slidewire baskets, part of Terminal Countdown Demonstration Test (TCDT) activities in preparation for launch. The other crew members taking part are Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. The baskets are part of the emergency egress system for persons in the Shuttle vehicle or on the Rotating Service Structure. Seven slidewires extend from the orbiter access arm, with a netted, flatbottom basket suspended from each wire. The TCDT also provides the crew with opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew practice emergency egress in the slidewire basket

NASA Technical Reports Server (NTRS)

1999-01-01

In the slidewire basket on Launch Pad 39B, STS-103 Mission Specialist Steven L. Smith reaches for the lever that will release the basket. With Smith is fellow crew member Mission Specialist Jean-Frangois Clervoy of France. The baskets are part of the emergency egress system for persons in the Shuttle vehicle or on the Rotating Service Structure. Seven slidewires extend from the orbiter access arm, with a netted, flatbottom basket suspended from each wire. The STS-103 crew are taking part in Terminal Countdown Demonstration Test (TCDT) activities in preparation for launch. The other crew members are Commander Curtis L. Brown Jr., Pilot Scott J. Kelly, and Mission Specialists C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), and Claude Nicollier of Switzerland. Clervoy and Nicollier are with the European Space Agency. The TCDT provides the crew with the emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

STS-103 crew practice emergency egress in the slidewire basket

NASA Technical Reports Server (NTRS)

1999-01-01

In the slidewire basket on Launch Pad 39B, STS-103 Commander Curtis L. Brown Jr. (left) and Pilot Scott J. Kelly (right) adjust their equipment. The baskets are part of the emergency egress system for persons in the Shuttle vehicle or on the Rotating Service Structure. Seven slidewires extend from the orbiter access arm, with a netted, flatbottom basket suspended from each wire. The other crew members are Mission Specialists Steven L. Smith, C. Michael Foale (Ph.D.), John M. Grunsfeld (Ph.D.), Claude Nicollier of Switzerland, with the European Space Agency (ESA), and Jean-Frangois Clervoy of France, also with ESA.. The STS-103 crew are taking part in Terminal Countdown Demonstration Test (TCDT) activities in preparation for launch. The TCDT provides the crew with the emergency egress training, opportunities to inspect their mission payloads in the orbiter's payload bay, and simulated countdown exercises. STS-103 is a 'call-up' mission due to the need to replace and repair portions of the Hubble Space Telescope, including the gyroscopes that allow the telescope to point at stars, galaxies and planets. The STS-103 crew will be replacing a Fine Guidance Sensor, an older computer with a new enhanced model, an older data tape recorder with a solid-state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Four EVA's are planned to make the necessary repairs and replacements on the telescope. The mission is targeted for launch Dec. 6 at 2:37 a.m. EST.

Downlink Acquisition and Tracking Procedures for the ASCAMP Satellite Communications Terminal

DTIC Science & Technology

1993-09-14

ACQUISITION AND TRACKING PROCEDURES FOR THE ASCAMP SATELLITE COMMUNICATIONS TERMINAL R.J. FIGUCIA Group 66 DM QUAIrTY INPECTED S Accesion For NTIS CRAMI...accuracy of 50 ns for clock drifts up to 100 ns/s. 1 ne spatial tracking procedure sustains a 0.250 accuraci for a typical geosynchronous orbit and is...Fishman, Private communication (15 June 1990). 2. G. Gorski-Popiel, " Architecture of ASCAMP digital hardware," 1991 IEEE MiW. Commun. Conf. Rec., 1110-1116

Microcomputer-controlled world time display for public area viewing

NASA Astrophysics Data System (ADS)

Yep, S.; Rashidian, M.

1982-05-01

The design, development, and implementation of a microcomputer-controlled world clock is discussed. The system, designated international Time Display System (ITDS), integrates a Geochron Calendar Map and a microcomputer-based digital display to automatically compensate for daylight savings time, leap year, and time zone differences. An in-depth technical description of the design and development of the electronic hardware, firmware, and software systems is provided. Reference material on the time zones, fabrication techniques, and electronic subsystems are also provided.

A Proposed Study Program for the Enhancement of Performance of Clocks in the DCS Timing system.

DTIC Science & Technology

1982-08-31

INTRODUCTION This technical note presents a proposed program of test and analysis with 𔃾 a goal of using prediction techniques to enhance the...future digital DCS and methods of satisfying them so that the reader will understand: (1) what is needed from this program to enhance the performance...over a number of years, using both simulation and analysis , have recommended that all major nodes of the DCS be referenced to Coordinated Universal Time

STS-27 Atlantis, OV-104, terminal countdown demonstration test (TCDT) at KSC

NASA Technical Reports Server (NTRS)

1988-01-01

STS-27 Atlantis, Orbiter Vehicle (OV) 104, crewmembers participate in the terminal countdown demonstration test (TCDT) at the Kennedy Space Center (KSC). Standing in front of the M113 tracked rescue vehicle (armored personnel carrier (APC)) are left to right Mission Specialist (MS) William M. Shepherd, Pilot Guy S. Gardner, Commander Robert L. Gibson, MS Richard M. Mullane, and MS Jerry L. Ross. Crewmembers are wearing orange partial pressure or launch and entry suits (LESs).

KSC-2009-4467

NASA Image and Video Library

2009-08-05

CAPE CANAVERAL, Fla. – At NASA's Kennedy Space Center in Florida, STS-128 Mission Specialist Patrick Forrester takes his turn driving an M-113 armored personnel carrier. At left is Mission Specialist John "Danny" Olivas. The crew is at Kennedy for a launch dress rehearsal called the terminal countdown demonstration test, or TCDT, which includes emergency exit training and equipment familiarization, as well as a simulated launch countdown. Launch of Discovery is targeted for late August. Photo credit: NASA/Kim Shiflett

KSC-06pd1758

NASA Image and Video Library

2006-08-08

KENNEDY SPACE CENTER, FLA. - STS-115 Mission Specialist Daniel Burbank is ready to practice driving the M-113 armored personnel carrier. The STS-115 crew are at NASA's Kennedy Space Center for Terminal Countdown Demonstration Test activities such as the M-113 training. They will also practice emergency egress from the launch pad and take part in a simulated launch countdown. Liftoff of mission STS-115 aboard Space Shuttle Atlantis is scheduled in a window beginning Aug. 27. Photo credit: NASA/Cory Huston

KSC-06pd1105

NASA Image and Video Library

2006-06-15

KENNEDY SPACE CENTER, FLA. - STS-121 Mission Specialist Thomas Reiter is taking his turn driving an M-113, which is an armored personnel carrier. Reiter is from Germany and represents the European Space Agency. The STS-121 crew is taking turns driving the M-113 as part of Terminal Countdown Demonstration Test activities, which include emergency egress training from the pad and a simulated countdown. Mission STS-121 is designated for launch on July 1. Photo credit: NASA/Kim Shiflett

KSC-06pd1752

NASA Image and Video Library

2006-08-08

KENNEDY SPACE CENTER, FLA. - STS-115 Pilot Christopher Ferguson is ready to practice driving the M-113 armored personnel carrier. The STS-115 crew are at NASA's Kennedy Space Center for Terminal Countdown Demonstration Test activities such as the M-113 training. They will also practice emergency egress from the launch pad and take part in a simulated launch countdown. Liftoff of mission STS-115 aboard Space Shuttle Atlantis is scheduled in a window beginning Aug. 27. Photo credit: NASA/Cory Huston

KSC01pp0308

NASA Image and Video Library

2001-02-13

STS-102 Commander James Wetherbee drives the M-113 armored carrier that the crew could use to exit the pad if an emergency ever occurred prior to launch. The STS-102 crew is at KSC to take part in Terminal Countdown Demonstration Test activities, which also include a simulated launch countdown. STS-102 is the eighth construction flight to the International Space Station, carrying as payload the Multi-Purpose Logistics Module Leonardo. Launch on mission STS-102 is scheduled for March 8

KSC-06pd1744

NASA Image and Video Library

2006-08-07

KENNEDY SPACE CENTER, FLA. - STS-115 Mission Specialist arrives at KSC's Shuttle Landing Facility aboard a T-38 jet aircraft. The STS-115 crew has flown to NASA's Kennedy Space Center to take part in Terminal Countdown Demonstration Test activities. The TCDT is a pre-launch preparation that includes practicing emergency egress from the pad, driving an M-113 armored personnel carrier, and simulating the launch countdown. Launch of STS-115 is currently scheduled for Aug. 27. Photo credit: NASA/George Shelton

Atomized scan strategy for high definition for VR application

NASA Astrophysics Data System (ADS)

Huang, Shuping; Ran, Feng; Ji, Yuan; Chen, Wendong

2017-10-01

Silicon-based OLED (Organic Light Emitting Display) microdisplay technology begins to attract people's attention in the emerging VR and AR devices. The high display frame refresh rate is an important solution to alleviate the dizziness in VR applications. Traditional display circuit drivers use the analog method or the digital PWM method that follow the serial scan order from the first pixel to the last pixel by using the shift registers. This paper proposes a novel atomized scan strategy based on the digital fractal scan strategy using the pseudo-random scan order. It can be used to realize the high frame refresh rate with the moderate pixel clock frequency in the high definition OLED microdisplay. The linearity of the gray level is also improved compared with the Z fractal scan strategy.

Progress in Low-Power Digital Microwave Radiometer Technologies

NASA Technical Reports Server (NTRS)

Piepmeier, Jeffrey R.; Kim, Edward J.

2004-01-01

Three component technologies were combined into a digital correlation microwave radiometer. The radiometer comprises a dual-channel X-band superheterodyne receiver, low-power high-speed cross-correlator (HSCC), three-level ADCs, and a correlated noise source (CNS). The HSCC dissipates 10 mW and operates at 500 MHz clock speed. The ADCs are implemented using ECL components and dissipate more power than desired. Thus, a low-power ADC development is underway. The new ADCs arc predicted to dissipated less than 200 mW and operate at 1 GSps with 1.5 GHz of input bandwidth. The CNS provides different input correlation values for calibration of the radiometer. The correlation channel had a null offset of 0.0008. Test results indicate that the correlation channel can be calibrated with 0.09% error in gain.

A high capacity data centre network: simultaneous 4-PAM data at 20 Gbps and 2 GHz phase modulated RF clock signal over a single VCSEL carrier

NASA Astrophysics Data System (ADS)

Isoe, G. M.; Wassin, S.; Gamatham, R. R. G.; Leitch, A. W. R.; Gibbon, T. B.

2017-11-01

Optical fibre communication technologies are playing important roles in data centre networks (DCNs). Techniques for increasing capacity and flexibility for the inter-rack/pod communications in data centres have drawn remarkable attention in recent years. In this work, we propose a low complexity, reliable, alternative technique for increasing DCN capacity and flexibility through multi-signal modulation onto a single mode VCSEL carrier. A 20 Gbps 4-PAM data signal is directly modulated on a single mode 10 GHz bandwidth VCSEL carrier at 1310 nm, therefore, doubling the network bit rate. Carrier spectral efficiency is further maximized by modulating its phase attribute with a 2 GHz reference frequency (RF) clock signal. We, therefore, simultaneously transmit a 20 Gbps 4-PAM data signal and a phase modulated 2 GHz RF signal using a single mode 10 GHz bandwidth VCSEL carrier. It is the first time a single mode 10 GHz bandwidth VCSEL carrier is reported to simultaneously transmit a directly modulated 4-PAM data signal and a phase modulated RF clock signal. A receiver sensitivity of -10. 52 dBm was attained for a 20 Gbps 4-PAM VCSEL transmission. The 2 GHz phase modulated RF clock signal introduced a power budget penalty of 0.21 dB. Simultaneous distribution of both data and timing signals over shared infrastructure significantly increases the aggregated data rate at different optical network units within the DCN, without expensive optics investment. We further demonstrate on the design of a software-defined digital signal processing assisted receiver to efficiently recover the transmitted signal without employing costly receiver hardware.

Method and apparatus for enhancing microchannel plate data

DOEpatents

Thoe, Robert S.

1987-01-01

A method and apparatus for determining centroid channel locations is disclosed for use in a system activated by one or more multichannel plates (16,18) and including a linear diode array (24) providing channels of information 1, 2, . . . , n, . . . , N containing signal amplitudes A.sub.n. A source of analog A.sub.n signals (40), and a source of digital clock signals n (48), are provided. Non-zero A.sub.n values are detected in a discriminator (42). A digital signal representing p, the value of n immediately preceding that whereat A.sub.n takes its first non-zero value, is generated in a scaler (50). The analog A.sub.n signals are converted to digital in an analog to digital converter (44). The digital A.sub.n signals are added to produce a digital .SIGMA.A.sub.n signal in a full adder (46). Digital 1, 2, . . . , m signals representing the number of non-zero A.sub.n are produced by a discriminator pulse counter (52). Digital signals representing 1 A.sub.p+ 1, 2 A.sub.p+2, . . . , m A.sub.p+m are produced by pairwise multiplication in multiplier (54). These signals are added in multiplier summer (56) to produce a digital .SIGMA.nA.sub.n -p.SIGMA.A.sub.n signal. This signal is divided by the digital .SIGMA.A.sub.n signal in divider (58) to provide a digital (.SIGMA.nA.sub.n /.SIGMA.A.sub.n) -p signal. Finally, this last signal is added to the digital p signal in an offset summer (60) to provide .SIGMA.nA.sub.n /.SIGMA.A.sub.n, the centroid channel locations.

A three-channel LED driver with single line transportation technique

NASA Astrophysics Data System (ADS)

Yu, Caideng; Du, Yiying; Jiang, Qiao; Zhou, Yun; Lv, Jian

2012-10-01

Designed a three-channel LED driver, realized the single-wire transmission of cascade signal between the drive IC of LED. Including the MCU digital interface, date register, clock synchronization, PWM grayscale adjustment circuit, as well as high voltage driver circuit for LED, etc… The driver control LED displaying 256 gray. Chip will generate synchronous sampling clock signals according to the received serial signals, when 24 bits dates have been received, the output pin begins to transport the dates followed-up which are automotive shaped to the input of the next chip. When the date receiving becomes low level that represent RESET, the red, green and blue channels will export different signals based on different input dates. Through the external MCU, it is realized the Separate luminance, and by connecting chips in series it achieved the control of outdoor big screen' colorful display. The automatic shaping forward technique makes the number of chips cascading immune to the limitations of signal transmission, but only limited by the refresh speed.

KSC-2011-7943

NASA Image and Video Library

2011-11-26

CAPE CANAVERAL, Fla. – Will.i.am, left, entertainer and member of The Black Eyed Peas, and former astronaut Leland Melvin, NASA associate administrator for Education, take part in a Tweetup at NASA Kennedy Space Center's Press Site in Florida during prelaunch activities for the agency’s Mars Science Laboratory (MSL) launch. Behind them glint the lights of the launch countdown clock. Participants in the Tweetup are given the opportunity to listen to agency briefings, tour locations on the center normally off limits to visitors, and get a close-up view of Space Launch Complex-41 on Cape Canaveral Air Force Station. The tweeters will share their experiences with followers through the social networking site Twitter. The MSL mission will pioneer precision landing technology and a sky-crane touchdown to place a car-sized rover, Curiosity, near the foot of a mountain inside Gale Crater on Aug. 6, 2012. During a nearly two-year prime mission after landing, the rover will investigate whether the region has ever offered conditions favorable for microbial life, including the chemical ingredients for life. Liftoff of MSL aboard a United Launch Alliance Atlas V rocket from pad 41 is planned during a launch window which extends from 10:02 a.m. to 11:45 a.m. EST on Nov. 26. For more information, visit http://www.nasa.gov/msl. Photo credit: NASA/Frankie Martin

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

PubMed Central

Ibrahim, Salah Hasan; Ali, Sawal Hamid Md.; Islam, Md. Shabiul

2014-01-01

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications. PMID:24991635

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

The IceCube data acquisition system: Signal capture, digitization, and timestamping

NASA Astrophysics Data System (ADS)

Abbasi, R.; Ackermann, M.; Adams, J.; Ahlers, M.; Ahrens, J.; Andeen, K.; Auffenberg, J.; Bai, X.; Baker, M.; Barwick, S. W.; Bay, R.; Bazo Alba, J. L.; Beattie, K.; Becka, T.; Becker, J. K.; Becker, K.-H.; Berghaus, P.; Berley, D.; Bernardini, E.; Bertrand, D.; Besson, D. Z.; Bingham, B.; Blaufuss, E.; Boersma, D. J.; Bohm, C.; Bolmont, J.; Böser, S.; Botner, O.; Braun, J.; Breeder, D.; Burgess, T.; Carithers, W.; Castermans, T.; Chen, H.; Chirkin, D.; Christy, B.; Clem, J.; Cowen, D. F.; D'Agostino, M. V.; Danninger, M.; Davour, A.; Day, C. T.; Depaepe, O.; De Clercq, C.; Demirörs, L.; Descamps, F.; Desiati, P.; de Vries-Uiterweerd, G.; DeYoung, T.; Diaz-Velez, J. C.; Dreyer, J.; Dumm, J. P.; Duvoort, M. R.; Edwards, W. R.; Ehrlich, R.; Eisch, J.; Ellsworth, R. W.; Engdegård, O.; Euler, S.; Evenson, P. A.; Fadiran, O.; Fazely, A. R.; Feusels, T.; Filimonov, K.; Finley, C.; Foerster, M. M.; Fox, B. D.; Franckowiak, A.; Franke, R.; Gaisser, T. K.; Gallagher, J.; Ganugapati, R.; Gerhardt, L.; Gladstone, L.; Glowacki, D.; Goldschmidt, A.; Goodman, J. A.; Gozzini, R.; Grant, D.; Griesel, T.; Groß, A.; Grullon, S.; Gunasingha, R. M.; Gurtner, M.; Ha, C.; Hallgren, A.; Halzen, F.; Han, K.; Hanson, K.; Hardtke, R.; Hasegawa, Y.; Haugen, J.; Hays, D.; Heise, J.; Helbing, K.; Hellwig, M.; Herquet, P.; Hickford, S.; Hill, G. C.; Hodges, J.; Hoffman, K. D.; Hoshina, K.; Hubert, D.; Huelsnitz, W.; Hughey, B.; Hülß, J.-P.; Hulth, P. O.; Hultqvist, K.; Hussain, S.; Imlay, R. L.; Inaba, M.; Ishihara, A.; Jacobsen, J.; Japaridze, G. S.; Johansson, H.; Jones, A.; Joseph, J. M.; Kampert, K.-H.; Kappes, A.; Karg, T.; Karle, A.; Kawai, H.; Kelley, J. L.; Kiryluk, J.; Kislat, F.; Klein, S. R.; Kleinfelder, S.; Klepser, S.; Kohnen, G.; Kolanoski, H.; Köpke, L.; Kowalski, M.; Kowarik, T.; Krasberg, M.; Kuehn, K.; Kujawski, E.; Kuwabara, T.; Labare, M.; Laihem, K.; Landsman, H.; Lauer, R.; Laundrie, A.; Leich, H.; Leier, D.; Lewis, C.; Lucke, A.; Ludvig, J.; Lundberg, J.; Lünemann, J.; Madsen, J.; Maruyama, R.; Mase, K.; Matis, H. S.; McParland, C. P.; Meagher, K.; Meli, A.; Merck, M.; Messarius, T.; Mészáros, P.; Minor, R. H.; Miyamoto, H.; Mohr, A.; Mokhtarani, A.; Montaruli, T.; Morse, R.; Movit, S. M.; Münich, K.; Muratas, A.; Nahnhauer, R.; Nam, J. W.; Nießen, P.; Nygren, D. R.; Odrowski, S.; Olivas, A.; Olivo, M.; Ono, M.; Panknin, S.; Patton, S.; Pérez de los Heros, C.; Petrovic, J.; Piegsa, A.; Pieloth, D.; Pohl, A. C.; Porrata, R.; Potthoff, N.; Pretz, J.; Price, P. B.; Przybylski, G. T.; Rawlins, K.; Razzaque, S.; Redl, P.; Resconi, E.; Rhode, W.; Ribordy, M.; Rizzo, A.; Robbins, W. J.; Rodrigues, J. P.; Roth, P.; Rothmaier, F.; Rott, C.; Roucelle, C.; Rutledge, D.; Ryckbosch, D.; Sander, H.-G.; Sarkar, S.; Satalecka, K.; Sandstrom, P.; Schlenstedt, S.; Schmidt, T.; Schneider, D.; Schulz, O.; Seckel, D.; Semburg, B.; Seo, S. H.; Sestayo, Y.; Seunarine, S.; Silvestri, A.; Smith, A. J.; Song, C.; Sopher, J. E.; Spiczak, G. M.; Spiering, C.; Stanev, T.; Stezelberger, T.; Stokstad, R. G.; Stoufer, M. C.; Stoyanov, S.; Strahler, E. A.; Straszheim, T.; Sulanke, K.-H.; Sullivan, G. W.; Swillens, Q.; Taboada, I.; Tarasova, O.; Tepe, A.; Ter-Antonyan, S.; Tilav, S.; Tluczykont, M.; Toale, P. A.; Tosi, D.; Turčan, D.; van Eijndhoven, N.; Vandenbroucke, J.; Van Overloop, A.; Viscomi, V.; Vogt, C.; Voigt, B.; Vu, C. Q.; Wahl, D.; Walck, C.; Waldenmaier, T.; Waldmann, H.; Walter, M.; Wendt, C.; Westerhof, S.; Whitehorn, N.; Wharton, D.; Wiebusch, C. H.; Wiedemann, C.; Wikström, G.; Williams, D. R.; Wischnewski, R.; Wissing, H.; Woschnagg, K.; Xu, X. W.; Yodh, G.; Yoshida, S.; IceCube Collaboration

2009-04-01

IceCube is a km-scale neutrino observatory under construction at the South Pole with sensors both in the deep ice (InIce) and on the surface (IceTop). The sensors, called Digital Optical Modules (DOMs), detect, digitize and timestamp the signals from optical Cherenkov-radiation photons. The DOM Main Board (MB) data acquisition subsystem is connected to the central DAQ in the IceCube Laboratory (ICL) by a single twisted copper wire-pair and transmits packetized data on demand. Time calibration is maintained throughout the array by regular transmission to the DOMs of precisely timed analog signals, synchronized to a central GPS-disciplined clock. The design goals and consequent features, functional capabilities, and initial performance of the DOM MB, and the operation of a combined array of DOMs as a system, are described here. Experience with the first InIce strings and the IceTop stations indicates that the system design and performance goals have been achieved.

Automated digital magnetofluidics

NASA Astrophysics Data System (ADS)

Schneider, J.; Garcia, A. A.; Marquez, M.

2008-08-01

Drops can be moved in complex patterns on superhydrophobic surfaces using a reconfigured computer-controlled x-y metrology stage with a high degree of accuracy, flexibility, and reconfigurability. The stage employs a DMC-4030 controller which has a RISC-based, clock multiplying processor with DSP functions, accepting encoder inputs up to 22 MHz, provides servo update rates as high as 32 kHz, and processes commands at rates as fast as 40 milliseconds. A 6.35 mm diameter cylindrical NdFeB magnet is translated by the stage causing water drops to move by the action of induced magnetization of coated iron microspheres that remain in the drop and are attracted to the rare earth magnet through digital magnetofluidics. Water drops are easily moved in complex patterns in automated digital magnetofluidics at an average speed of 2.8 cm/s over a superhydrophobic polyethylene surface created by solvent casting. With additional components, some potential uses for this automated microfluidic system include characterization of superhydrophobic surfaces, water quality analysis, and medical diagnostics.

STS-27 Atlantis, OV-104, terminal countdown demonstration test (TCDT) at KSC

NASA Image and Video Library

1988-11-14

S88-53086 (17 Nov 1988) --- STS-27 Atlantis, Orbiter Vehicle (OV) 104, crewmembers participate in the terminal countdown demonstration test (TCDT) at the Kennedy Space Center (KSC). Standing in front of the M113 tracked rescue vehicle (armored personnel carrier (APC)) are left to right Mission Specialist (MS) William M. Shepherd, Pilot Guy S. Gardner, Commander Robert L. Gibson, MS Richard M. Mullane, and MS Jerry L. Ross. Crewmembers are wearing orange partial pressure or launch and entry suits (LES).

STS-28 Columbia, OV-102, terminal countdown demonstration test (TCDT) at KSC

NASA Image and Video Library

1989-07-18

S89-41093 (9 Aug 1989) --- STS-28 Columbia, Orbiter Vehicle (OV) 102, mission specialist David C. Leestma relaxes in chair after donning launch and entry suit (LES) and launch and entry helmet (LEH). Technician in the background monitors LES systems. Leestma, along with fellow crewmembers, is participating in the terminal countdown demonstration test (TCDT) at the Kennedy Space Center (KSC) Operations and Checkout (O&C) Building. View provided by KSC with alternate number KSC-89PC-673.

STS-107 Payload Specialist Ilan Ramon suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. -- STS-107 Payload Specialist Ilan Ramon, the first Israeli astronaut, gets help with his suitup for Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Pilot William McCool in the cockpit of Columbia during TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. - STS-107 Pilot William 'Willie' McCool checks instructions in the cockpit of Space Shuttle Columbia during a simulated launch countdown, part of Terminal Countdown Demonstration Test activities. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-79 MISSION SPECIALIST JOHN E. BLAHA AND COMMANDER WILLIAM F. READDY CHAT DURING EMERGENCY EGRESS

NASA Technical Reports Server (NTRS)

1996-01-01

STS-79 Mission Specialist John E. Blaha (left) and Mission Commander William F. Readdy chat during emergency egress training at the 195-foot (59-meter) level of Launch Pad 39A. The training is part of their Terminal Countdown Demonstration Test (TCDT) activities. A dress rehearsal for launch, the TCDT culminates with a simulated countdown. The Space Shuttle Atlantis is undergoing preparations for liftoff on STS-79 no earlier than Sept. 12.

STS-79 Commander William Readdy arrives at SLF

NASA Technical Reports Server (NTRS)

1996-01-01

STS-79 Commander William F. Readdy arrives at KSC's Shuttle Landing Facility with five fellow astronauts, ready to participate in the Terminal Countdown Demonstration Test (TCDT). The TCDT is a dress rehearsal for launch for the flight crew and launch team. Over the next several days, the astronauts will take part in training exercises at the launch pad that will culminate in a simulated launch countdown. The Space Shuttle Atlantis is being prepared for liftoff on STS-79 around September 12.

KSC-06pd1109

NASA Image and Video Library

2006-06-15

KENNEDY SPACE CENTER, FLA. - STS-121 Mission Specialist Piers Sellers takes his turn in an M-113, which is an armored personnel carrier. Behind him are Mission Specialists Lisa Nowak and Thomas Reiter from Germany, who represents the European Space Agency. The STS-121 crew is taking turns driving the M-113 as part of Terminal Countdown Demonstration Test activities, which include emergency egress training from the pad and a simulated countdown. Mission STS-121 is designated for launch on July 1. Photo credit: NASA/Kim Shiflett

KSC-07pd2697

NASA Image and Video Library

2007-10-08

KENNEDY SPACE CENTER, FLA. -- STS-120 Pamela Melroy (front) is ready for training on the M-113 armored personnel carrier, part of emergency egress training. The training is part of terminal countdown demonstration test, or TCDT, activities the crew is undertaking at NASA's Kennedy Space Center. The TCDT also includes equipment familiarization and a simulated launch countdown. Mission STS-120, which will carry the Italian-built U.S. Node 2 to the International Space Station, is targeted for launch on Oct. 23. Photo credit: NASA/Kim Shiflett

KSC-06pd1756

NASA Image and Video Library

2006-08-08

KENNEDY SPACE CENTER, FLA. - STS-115 Mission Specialist Heidemarie Stefanyshyn-Piper is ready to practice driving the M-113 armored personnel carrier. Behind her is pilot Christopher Ferguson. The STS-115 crew are at NASA's Kennedy Space Center for Terminal Countdown Demonstration Test activities such as the M-113 training. They will also practice emergency egress from the launch pad and take part in a simulated launch countdown. Liftoff of mission STS-115 aboard Space Shuttle Atlantis is scheduled in a window beginning Aug. 27. Photo credit: NASA/Cory Huston

Gemini 6 prime crew in white room atop Pad 19 during Gemini 6 countdown

NASA Technical Reports Server (NTRS)

1965-01-01

NASA and McDonnell technicians assist the Gemini 6 prime crew into the spacecraft in the White Room atop Pad 19 during the Gemini 6 prelaunch countdown. Astronaut Walter M. Schirra Jr., command pilot, is on left; and Astronaut Thomas P. Stafford, is on the right. Between the two is a note attached to the capsule which reads 'Good Luck from 2nd Shift'. Liftoff was at 8:37 a.m., December 15, 1965.

STS-107 Mission Specialist David Brown suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. -- STS-107 Mission Specialist David Brown happily submits to suit check prior to Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Mission Specialist Laurel Clark suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. - STS-107 Mission Specialist Laurel Clark happily submits to suit check prior to Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Payload Specialist Ilan Ramon suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. - STS-107 Payload Specialist Ilan Ramon, the first Israeli astronaut, sits happily during suitup for Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Mission Specialist David Brown suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. -- STS-107 Mission Specialist David Brown waves as he completes suit check prior to Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Mission Specialist Kalpana Chawla during TCDT at LC-39A

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. - STS-107 Mission Specialist Kalpana Chawla is shown during the crew's Terminal Countdown Demonstration Test activities on Launch Pad 39A. The TCDT also includes a simulated launch countdown. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

STS-107 Mission Specialist Laurel Clark suits up for TCDT

NASA Technical Reports Server (NTRS)

2002-01-01

KENNEDY SPACE CENTER, FLA. -- STS-107 Mission Specialist Laurel Clark has her helmet checked during suitup for Terminal Countdown Demonstration Test activities, which include a simulated launch countdown at the pad. STS-107 is a mission devoted to research and will include more than 80 experiments that will study Earth and space science, advanced technology development, and astronaut health and safety. Launch is planned for Jan. 16, 2003, between 10 a.m. and 2 p.m. EST aboard Space Shuttle Columbia. .

KSC-02PD0341

NASA Image and Video Library

2002-03-20

KENNEDY SPACE CENTER, FLA. -- STS-110 Commander Michael Bloomfield waves as he gets ready to depart KSC for Houston. He and the rest of the crew were at KSC for Terminal Countdown Demonstration Test activities that included payload familiarization and a simulated launch countdown. Scheduled for launch April 4, the 11-day STS-110 mission will feature Space Shuttle Atlantis docking with the International Space Station (ISS) and delivering the S0 truss, the centerpiece-segment of the primary truss structure that will eventually extend over 300 feet

KSC-07pd2722

NASA Image and Video Library

2007-10-08

KENNEDY SPACE CENTER, FLA. -- STS-120 Mission Specialist Stephanie Wilson has her helmet adjusted during fitting of her launch and entry suit. The fitting is part of terminal countdown demonstration test, or TCDT, activities the crew is undertaking at NASA's Kennedy Space Center. The TCDT also includes emergency egress procedures, equipment familiarization and a simulated launch countdown. Mission STS-120, which will carry the Italian-built U.S. Node 2 to the International Space Station, is targeted for launch on Oct. 23. Photo credit: NASA/Kim Shiflett

KSC-07pd2717

NASA Image and Video Library

2007-10-08

KENNEDY SPACE CENTER, FLA. -- STS-120 Mission Specialist Doug Wheelock has his helmet fitted on his launch and entry suit, preparing for launch. The fitting is part of terminal countdown demonstration test, or TCDT, activities the crew is undertaking at NASA's Kennedy Space Center. The TCDT also includes emergency egress procedures, equipment familiarization and a simulated launch countdown. Mission STS-120, which will carry the Italian-built U.S. Node 2 to the International Space Station, is targeted for launch on Oct. 23. Photo credit: NASA/Kim Shiflett

KSC-07pd2719

NASA Image and Video Library

2007-10-08

KENNEDY SPACE CENTER, FLA. -- STS-120 Mission Specialist Daniel Tani tries on his helmet with his launch and entry suit, preparing for launch. The fitting is part of terminal countdown demonstration test, or TCDT, activities the crew is undertaking at NASA's Kennedy Space Center. The TCDT also includes emergency egress procedures, equipment familiarization and a simulated launch countdown. Mission STS-120, which will carry the Italian-built U.S. Node 2 to the International Space Station, is targeted for launch on Oct. 23. Photo credit: NASA/Kim Shiflett