Generalized look-ahead number conversion from signed digit to complement representation with optical logic operations

NASA Astrophysics Data System (ADS)

Qian, Feng; Li, Guoqiang

2001-12-01

In this paper a generalized look-ahead logic algorithm for number conversion from signed-digit to its complement representation is developed. By properly encoding the signed digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quaternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using electron-trapping device is employed, which is suitable for realizing complex logic functions in the form of sum-of-product. The proposed algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

Fast and robust control of nanopositioning systems: Performance limits enabled by field programmable analog arrays.

PubMed

Baranwal, Mayank; Gorugantu, Ram S; Salapaka, Srinivasa M

2015-08-01

This paper aims at control design and its implementation for robust high-bandwidth precision (nanoscale) positioning systems. Even though modern model-based control theoretic designs for robust broadband high-resolution positioning have enabled orders of magnitude improvement in performance over existing model independent designs, their scope is severely limited by the inefficacies of digital implementation of the control designs. High-order control laws that result from model-based designs typically have to be approximated with reduced-order systems to facilitate digital implementation. Digital systems, even those that have very high sampling frequencies, provide low effective control bandwidth when implementing high-order systems. In this context, field programmable analog arrays (FPAAs) provide a good alternative to the use of digital-logic based processors since they enable very high implementation speeds, moreover with cheaper resources. The superior flexibility of digital systems in terms of the implementable mathematical and logical functions does not give significant edge over FPAAs when implementing linear dynamic control laws. In this paper, we pose the control design objectives for positioning systems in different configurations as optimal control problems and demonstrate significant improvements in performance when the resulting control laws are applied using FPAAs as opposed to their digital counterparts. An improvement of over 200% in positioning bandwidth is achieved over an earlier digital signal processor (DSP) based implementation for the same system and same control design, even when for the DSP-based system, the sampling frequency is about 100 times the desired positioning bandwidth.

Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology.

PubMed

Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin

2011-10-18

Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. © 2011 Macmillan Publishers Limited. All rights reserved.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

NASA Astrophysics Data System (ADS)

Li, Guoqiang; Qian, Feng

2001-11-01

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed- digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

An Introduction to Logic Control Systems for the Behavioral Scientist, Part I, Text.

ERIC Educational Resources Information Center

Larsen, Lawrence A.

This programed instruction course gives a basic introduction to solid state programing equipment. Course objectives include giving the student (1) a working knowledge of the various types of units used in building digital logic control systems and (2) an idea of how they interconnect to perform different functions. The course has no prerequisites…

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

[The improved design of table operating box of digital subtraction angiography device].

PubMed

Qi, Xianying; Zhang, Minghai; Han, Fengtan; Tang, Feng; He, Lemin

2009-12-01

In this paper are analyzed the disadvantages of CGO-3000 digital subtraction angiography table Operating Box. The authors put forward a communication control scheme between single-chip microcomputer(SCM) and programmable logic controller(PLC). The details of hardware and software of communication are given.

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Comparison of Communication Architectures and Network Topologies for Distributed Propulsion Controls (Preprint)

DTIC Science & Technology

2013-05-01

logic to perform control function computations and are connected to the full authority digital engine control ( FADEC ) via a high-speed data...Digital Engine Control ( FADEC ) via a high speed data communication bus. The short term distributed engine control configu- rations will be core...concen- trator; and high temperature electronics, high speed communication bus between the data concentrator and the control law processor master FADEC

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Interface For Dual-Channel MIL-STD-1553 Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Heaps, Timothy L.

1992-01-01

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

Digital design using selection operations

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor); Cameron, Eric G. (Inventor)

2004-01-01

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Apollo experience report: Guidance and control systems - Digital autopilot design development

NASA Technical Reports Server (NTRS)

Peters, W. H.; Cox, K. J.

1973-01-01

The development of the Apollo digital autopilots (the primary attitude control systems that were used for all phases of the lunar landing mission) is summarized. This report includes design requirements, design constraints, and design philosophy. The development-process functions and the essential information flow paths are identified. Specific problem areas that existed during the development are included. A discussion is also presented on the benefits inherent in mechanizing attitude-controller logic and dynamic compensation in a digital computer.

Synthesizing genetic sequential logic circuit with clock pulse generator.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang

2014-05-28

Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

NASA Technical Reports Server (NTRS)

Barrett, W. J.; Rembold, J. P.; Burcham, F. W.; Myers, L.

1981-01-01

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Microscale Digital Vacuum Electronic Gates

NASA Technical Reports Server (NTRS)

Manohara, Harish (Inventor); Mojarradi, Mohammed M. (Inventor)

2014-01-01

Systems and methods in accordance with embodiments of the invention implement microscale digital vacuum electronic gates. In one embodiment, a microscale digital vacuum electronic gate includes: a microscale field emitter that can emit electrons and that is a microscale cathode; and a microscale anode; where the microscale field emitter and the microscale anode are disposed within at least a partial vacuum; where the microscale field emitter and the microscale anode are separated by a gap; and where the potential difference between the microscale field emitter and the microscale anode is controllable such that the flow of electrons between the microscale field emitter and the microscale anode is thereby controllable; where when the microscale anode receives a flow of electrons, a first logic state is defined; and where when the microscale anode does not receive a flow of electrons, a second logic state is defined.

Digital Troposcatter Performance Model

DTIC Science & Technology

1983-12-01

Dist Speia DIIBUTON STATEMR AO Approved tot public relemg ** - DistributionUnlimited __________ Communications. Control and Information Systems ...for digital troposcatter communication system design is described. Propagation and modem performance *are modeled. These include Path Loss and RSL...designing digital troposcatter systems . A User’s Manual Report discusses the use of the computer program TROPO. The description of the structure and logical

A fuzzy logic sliding mode controlled electronic differential for a direct wheel drive EV

NASA Astrophysics Data System (ADS)

Ozkop, Emre; Altas, Ismail H.; Okumus, H. Ibrahim; Sharaf, Adel M.

2015-11-01

In this study, a direct wheel drive electric vehicle based on an electronic differential system with a fuzzy logic sliding mode controller (FLSMC) is studied. The conventional sliding surface is modified using a fuzzy rule base to obtain fuzzy dynamic sliding surfaces by changing its slopes using the global error and its derivative in a fuzzy logic inference system. The controller is compared with proportional-integral-derivative (PID) and sliding mode controllers (SMCs), which are usually preferred to be used in industry. The proposed controller provides robustness and flexibility to direct wheel drive electric vehicles. The fuzzy logic sliding mode controller, electronic differential system and the overall electrical vehicle mechanism are modelled and digitally simulated by using the Matlab software. Simulation results show that the system with FLSMC has better efficiency and performance compared to those of PID and SMCs.

The design of digital-adaptive controllers for VTOL aircraft

NASA Technical Reports Server (NTRS)

Stengel, R. F.; Broussard, J. R.; Berry, P. W.

1976-01-01

Design procedures for VTOL automatic control systems have been developed and are presented. Using linear-optimal estimation and control techniques as a starting point, digital-adaptive control laws have been designed for the VALT Research Aircraft, a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. These control laws are designed to interface with velocity-command and attitude-command guidance logic, which could be used in short-haul VTOL operations. Developments reported here include new algorithms for designing non-zero-set-point digital regulators, design procedures for rate-limited systems, and algorithms for dynamic control trim setting.

Fundamentals of Digital Logic.

ERIC Educational Resources Information Center

Noell, Monica L.

This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…

A description of the thruster attitude control simulation and its application to the HEAO-C study

NASA Technical Reports Server (NTRS)

Brandon, L. B.

1971-01-01

During the design and evaluation of a reaction control system (RCS), it is desirable to have a digital computer program simulating vehicle dynamics, disturbance torques, control torques, and RCS logic. The thruster attitude control simulation (TACS) is just such a computer program. The TACS is a relatively sophisticated digital computer program that includes all the major parameters involved in the attitude control of a vehicle using an RCS for control. It includes the effects of gravity gradient torques and HEAO-C aerodynamic torques so that realistic runs can be made in the areas of fuel consumption and engine actuation rates. Also, the program is general enough that any engine configuration and logic scheme can be implemented in a reasonable amount of time. The results of the application of the TACS in the HEAO-C study are included.

Reconfigurable fuzzy cell

NASA Technical Reports Server (NTRS)

Salazar, George A. (Inventor)

1993-01-01

This invention relates to a reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing 'knowledge data' for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and recognition modes of operation are also provided.

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

NASA Technical Reports Server (NTRS)

Myers, L. P.; Baer-Riedhart, J. L.; Maxwell, M. D.

1985-01-01

The fault detection and accommodation (FDA) methodology for digital engine-control systems may range from simple comparisons of redundant parameters to the more complex and sophisticated observer models of the entire engine system. Evaluations of the various FDA schemes are done using analytical methods, simulation, and limited-altitude-facility testing. Flight testing of the FDA logic has been minimal because of the difficulty of inducing realistic faults in flight. A flight program was conducted to evaluate the fault detection and accommodation capability of a digital electronic engine control in an F-15 aircraft. The objective of the flight program was to induce selected faults and evaluate the resulting actions of the digital engine controller. Comparisons were made between the flight results and predictions. Several anomalies were found in flight and during the ground test. Simulation results showed that the inducement of dual pressure failures was not feasible since the FDA logic was not designed to accommodate these types of failures.

Synthesizing genetic sequential logic circuit with clock pulse generator

PubMed Central

2014-01-01

Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665

Biosensors with Built-In Biomolecular Logic Gates for Practical Applications

PubMed Central

Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

2014-01-01

Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

Effect of control logic modifications on airstart performance of F100 engine model derivative engines in an F-15 airplane

NASA Technical Reports Server (NTRS)

Crawford, D. B.; Burcham, F. W., Jr.

1984-01-01

A series of airstarts were conducted in an F-15 airplane with two prototype Pratt and Whitney F100 Engine Model Derivative engines equipped with Digital Electronic Engine Control (DEEC) systems. The airstart envelope and the time required for airstarts were defined. Comparisons were made between the original airstart logic, and modified logic which was designed to improve the airstart capability. Spooldown airstarts with the modified logic were more successful at lower altitudes than were those with the original logic. Spooldown airstart times ranged from 33 seconds at 250 knots to 83 seconds at 175 knots. The modified logic improved the airstart time from 31% to 53%, with the most improved times at slower airspeeds. Jet fuel starter (JFS)-assisted airstarts were conducted at 7000 m and airstart times were significantly faster than unassisted airstarts. The effect of altitude on airstart times was small.

Digital phase-locked loop speed control for a brushless dc motor

NASA Astrophysics Data System (ADS)

Wise, M. G.

1985-06-01

Speed control of d.c. motors by phase-locked loops (PLL) is becoming increasingly popular. Primary interest has been in employing PLL for constant speed control. This thesis investigates the theory and techniques of digital PLL to speed control of a brushless d.c. motor with a variable speed of operation. Addition of logic controlled count enable/disable to a synchronous up/down counter, used as a phase-frequency detector, is shown to improve the performance of previously proposed PLL control schemes.

Simulated Laboratory in Digital Logic.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

SDLDS--System for Digital Logic Design and Simulation

ERIC Educational Resources Information Center

Stanisavljevic, Z.; Pavlovic, V.; Nikolic, B.; Djordjevic, J.

2013-01-01

This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and…

Evaluation of an F100 multivariable control using a real-time engine simulation

NASA Technical Reports Server (NTRS)

Szuch, J. R.; Soeder, J. F.; Skira, C.

1977-01-01

The control evaluated has been designed for the F100-PW-100 turbofan engine. The F100 engine represents the current state-of-the-art in aircraft gas turbine technology. The control makes use of a multivariable, linear quadratic regulator. The evaluation procedure employed utilized a real-time hybrid computer simulation of the F100 engine and an implementation of the control logic on the NASA LeRC digital computer/controller. The results of the evaluation indicated that the control logic and its implementation will be capable of controlling the engine throughout its operating range.

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E.

1974-01-01

Digital transmitter designed for Manchester coded signals (and all signals with ac waveforms) generated at a rate of one megabit per second includes efficient output isolation circuit. Transmitter consists of logic control section, amplifier, and output isolation section. Output isolation circuit provides dynamic impedance at terminals as function of amplifier output level.

Digital transmitter for data bus communications system

NASA Technical Reports Server (NTRS)

Proch, G. E. (Inventor)

1975-01-01

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

Fault detection and accommodation testing on an F100 engine in an F-15 airplane. [digital engine control system

NASA Technical Reports Server (NTRS)

Myers, L. P.; Baer-Riedhart, J. L.; Maxwell, M. D.

1985-01-01

The fault detection and accommodation (FDA) methods that can be used for digital engine control systems are presently subjected to a flight test program in the case of the F-15 fighter's F100 engine electronic controls, inducing selected faults and then evaluating the resulting digital engine control responses. In general, flight test results were found to compare well with both ground tests and predictions. It is noted that the inducement of dual-pressure failures was not feasible, since FDA logic was not designed to accommodate them.

HYTESS 2: A Hypothetical Turbofan Engine Simplified Simulation with multivariable control and sensor analytical redundancy

NASA Technical Reports Server (NTRS)

Merrill, W. C.

1986-01-01

A hypothetical turbofan engine simplified simulation with a multivariable control and sensor failure detection, isolation, and accommodation logic (HYTESS II) is presented. The digital program, written in FORTRAN, is self-contained, efficient, realistic and easily used. Simulated engine dynamics were developed from linearized operating point models. However, essential nonlinear effects are retained. The simulation is representative of the hypothetical, low bypass ratio turbofan engine with an advanced control and failure detection logic. Included is a description of the engine dynamics, the control algorithm, and the sensor failure detection logic. Details of the simulation including block diagrams, variable descriptions, common block definitions, subroutine descriptions, and input requirements are given. Example simulation results are also presented.

Digital electronic engine control fault detection and accommodation flight evaluation

NASA Technical Reports Server (NTRS)

Baer-Ruedhart, J. L.

1984-01-01

The capabilities and performance of various fault detection and accommodation (FDA) schemes in existing and projected engine control systems were investigated. Flight tests of the digital electronic engine control (DEEC) in an F-15 aircraft show discrepancies between flight results and predictions based on simulation and altitude testing. The FDA methodology and logic in the DEEC system, and the results of the flight failures which occurred to date are described.

Users Guide to Direct Digital Control of Heating, Ventilating, and Air Conditioning Equipment,

DTIC Science & Technology

1985-01-01

cycles, reset, load shedding, chiller optimization , VAV fan synchronization, and optimum start/stop. The prospective buyer of a DDC system should...in Fig- ure 4. Data on setpoints , reset schedules, and event timing, such as that presented in Figure 6, are often even more difficult to find. In con...control logic, setpoint and other data are readily available. Program logic, setpoint and schedule data, and other information stored in a DDC unit

Feed-forward digital phase and amplitude correction system

DOEpatents

Yu, D.U.L.; Conway, P.H.

1994-11-15

Phase and amplitude modifications in repeatable RF pulses at the output of a high power pulsed microwave amplifier are made utilizing a digital feed-forward correction system. A controlled amount of the output power is coupled to a correction system for processing of phase and amplitude information. The correction system comprises circuitry to compare the detected phase and amplitude with the desired phase and amplitude, respectively, and a digitally programmable phase shifter and attenuator and digital logic circuitry to control the phase shifter and attenuator. The phase and amplitude of subsequent are modified by output signals from the correction system. 11 figs.

Feed-forward digital phase and amplitude correction system

DOEpatents

Yu, David U. L.; Conway, Patrick H.

1994-01-01

Phase and amplitude modifications in repeatable RF pulses at the output of a high power pulsed microwave amplifier are made utilizing a digital feed-forward correction system. A controlled amount of the output power is coupled to a correction system for processing of phase and amplitude information. The correction system comprises circuitry to compare the detected phase and amplitude with the desired phase and amplitude, respectively, and a digitally programmable phase shifter and attenuator and digital logic circuitry to control the phase shifter and attenuator. The Phase and amplitude of subsequent are modified by output signals from the correction system.

Implementation Of Fuzzy Automated Brake Controller Using TSK Algorithm

NASA Astrophysics Data System (ADS)

Mittal, Ruchi; Kaur, Magandeep

2010-11-01

In this paper an application of Fuzzy Logic for Automatic Braking system is proposed. Anti-blocking system (ABS) brake controllers pose unique challenges to the designer: a) For optimal performance, the controller must operate at an unstable equilibrium point, b) Depending on road conditions, the maximum braking torque may vary over a wide range, c) The tire slippage measurement signal, crucial for controller performance, is both highly uncertain and noisy. A digital controller design was chosen which combines a fuzzy logic element and a decision logic network. The controller identifies the current road condition and generates a command braking pressure signal Depending upon the speed and distance of train. This paper describes design criteria, and the decision and rule structure of the control system. The simulation results present the system's performance depending upon the varying speed and distance of the train.

Digital Holographic Logic

NASA Technical Reports Server (NTRS)

Preston, K., Jr.

1972-01-01

The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

Fuzzy logic particle tracking velocimetry

NASA Technical Reports Server (NTRS)

Wernet, Mark P.

1993-01-01

Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.

Precision digital control systems

NASA Astrophysics Data System (ADS)

Vyskub, V. G.; Rozov, B. S.; Savelev, V. I.

This book is concerned with the characteristics of digital control systems of great accuracy. A classification of such systems is considered along with aspects of stabilization, programmable control applications, digital tracking systems and servomechanisms, and precision systems for the control of a scanning laser beam. Other topics explored are related to systems of proportional control, linear devices and methods for increasing precision, approaches for further decreasing the response time in the case of high-speed operation, possibilities for the implementation of a logical control law, and methods for the study of precision digital control systems. A description is presented of precision automatic control systems which make use of electronic computers, taking into account the existing possibilities for an employment of computers in automatic control systems, approaches and studies required for including a computer in such control systems, and an analysis of the structure of automatic control systems with computers. Attention is also given to functional blocks in the considered systems.

A Microcomputer Interface for External Circuit Control.

ERIC Educational Resources Information Center

Gorham, D. A.

1983-01-01

Describes an interface designed to meet the requirements of an instrumentation teaching laboratory, particularly to develop computer-controlled digital circuitry while exploiting electrical drive properties of common transistor-transistor logic (TTL) devices, minimizing cost/number of components. Discusses decoding for Pet, switches, lights, and…

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2017-05-01

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Closed circuit TV system automatically guides welding arc

NASA Technical Reports Server (NTRS)

Stephans, D. L.; Wall, W. A., Jr.

1968-01-01

Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Correction And Use Of Jitter In Television Images

NASA Technical Reports Server (NTRS)

Diner, Daniel B.; Fender, Derek H.; Fender, Antony R. H.

1989-01-01

Proposed system stabilizes jittering television image and/or measures jitter to extract information on motions of objects in image. Alternative version, system controls lateral motion on camera to generate stereoscopic views to measure distances to objects. In another version, motion of camera controlled to keep object in view. Heart of system is digital image-data processor called "jitter-miser", which includes frame buffer and logic circuits to correct for jitter in image. Signals from motion sensors on camera sent to logic circuits and processed into corrections for motion along and across line of sight.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

ERIC Educational Resources Information Center

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

A Web-Based Visualization and Animation Platform for Digital Logic Design

ERIC Educational Resources Information Center

Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.

2015-01-01

This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…

Fuzzy Logic-Based Audio Pattern Recognition

NASA Astrophysics Data System (ADS)

Malcangi, M.

2008-11-01

Audio and audio-pattern recognition is becoming one of the most important technologies to automatically control embedded systems. Fuzzy logic may be the most important enabling methodology due to its ability to rapidly and economically model such application. An audio and audio-pattern recognition engine based on fuzzy logic has been developed for use in very low-cost and deeply embedded systems to automate human-to-machine and machine-to-machine interaction. This engine consists of simple digital signal-processing algorithms for feature extraction and normalization, and a set of pattern-recognition rules manually tuned or automatically tuned by a self-learning process.

Eight-Channel Digital Signal Processor and Universal Trigger Module

NASA Astrophysics Data System (ADS)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

Digital adaptive flight controller development

NASA Technical Reports Server (NTRS)

Kaufman, H.; Alag, G.; Berry, P.; Kotob, S.

1974-01-01

A design study of adaptive control logic suitable for implementation in modern airborne digital flight computers was conducted. Two designs are described for an example aircraft. Each of these designs uses a weighted least squares procedure to identify parameters defining the dynamics of the aircraft. The two designs differ in the way in which control law parameters are determined. One uses the solution of an optimal linear regulator problem to determine these parameters while the other uses a procedure called single stage optimization. Extensive simulation results and analysis leading to the designs are presented.

Propulsion control experience used in the Highly Integrated Digital Electronic Control (HIDEC) program

NASA Technical Reports Server (NTRS)

Myers, L. P.; Burcham, F. W., Jr.

1984-01-01

The highly integrated digital electronic control (HIDEC) program will integrate the propulsion and flight control systems on an F-15 airplane at NASA Ames Research Center's Dryden Flight Research Facility. Ames-Dryden has conducted several propulsion control programs that have contributed to the HIDEC program. The digital electronic engine control (DEEC) flight evaluation investigated the performance and operability of the F100 engine equipped with a full-authority digital electronic control system. Investigations of nozzle instability, fault detection and accommodation, and augmentor transient capability provided important information for the HIDEC program. The F100 engine model derivative (EMD) was also flown in the F-15 airplane, and airplane performance was significantly improved. A throttle response problem was found and solved with a software fix to the control logic. For the HIDEC program, the F100 EMD engines equipped with DEEC controls will be integrated with the digital flight control system. The control modes to be implemented are an integrated flightpath management mode and an integrated adaptive engine control system mode. The engine control experience that will be used in the HIDEC program is discussed.

Multi-enzyme logic network architectures for assessing injuries: digital processing of biomarkers.

PubMed

Halámek, Jan; Bocharova, Vera; Chinnapareddy, Soujanya; Windmiller, Joshua Ray; Strack, Guinevere; Chuang, Min-Chieh; Zhou, Jian; Santhosh, Padmanabhan; Ramirez, Gabriela V; Arugula, Mary A; Wang, Joseph; Katz, Evgeny

2010-12-01

A multi-enzyme biocatalytic cascade processing simultaneously five biomarkers characteristic of traumatic brain injury (TBI) and soft tissue injury (STI) was developed. The system operates as a digital biosensor based on concerted function of 8 Boolean AND logic gates, resulting in the decision about the physiological conditions based on the logic analysis of complex patterns of the biomarkers. The system represents the first example of a multi-step/multi-enzyme biosensor with the built-in logic for the analysis of complex combinations of biochemical inputs. The approach is based on recent advances in enzyme-based biocomputing systems and the present paper demonstrates the potential applicability of biocomputing for developing novel digital biosensor networks.

Augmentor transient capability of an F100 engine equipped with a digital electronic engine control

NASA Technical Reports Server (NTRS)

Burcham, F. W., Jr.; Pai, G. D.

1984-01-01

An F100 augmented turbofan engine equipped with digital electronic engine control (DEEC) system was evaluated. The engine was equipped with a specially modified augmentor to provide improved steady state and transient augmentor capability. The combination of the DEEC and the modified augmentor was evaluated in sea level and altitude facility tests and then in four different flight phases in an F-15 aircraft. The augmentor configuration, logic, and test results are presented.

Design of digital voice storage and playback system

NASA Astrophysics Data System (ADS)

Tang, Chao

2018-03-01

Based on STC89C52 chip, this paper presents a single chip microcomputer minimum system, which is used to realize the logic control of digital speech storage and playback system. Compared with the traditional tape voice recording system, the system has advantages of small size, low power consumption, The effective solution of traditional voice recording system is limited in the use of electronic and information processing.

Graphical approach for multiple values logic minimization

NASA Astrophysics Data System (ADS)

Awwal, Abdul Ahad S.; Iftekharuddin, Khan M.

1999-03-01

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

Programmable pulse generator based on programmable logic and direct digital synthesis.

PubMed

Suchenek, M; Starecki, T

2012-12-01

The paper presents a new approach of pulse generation which results in both wide range tunability and high accuracy of the output pulses. The concept is based on the use of programmable logic and direct digital synthesis. The programmable logic works as a set of programmable counters, while direct digital synthesis (DDS) as the clock source. Use of DDS as the clock source results in stability of the output pulses comparable to the stability of crystal oscillators and quasi-continuous tuning of the output frequency.

GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents

NASA Astrophysics Data System (ADS)

Srinivasan, Srikant

2012-02-01

Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3] S. Srinivasan, A. Sarkar, B. Behin-Aein and S. Datta, ``Unidirectional Information transfer with cascaded All Spin Logic devices: A Ring Oscillator,'' IEEE Device Research Conference (2011).[0pt] [4] A. Sarkar, S. Srinivasan, B. Behin-Aein and S. Datta, ``Multimagnet networks interacting via spin currents'' IEEE International Electron Devices Meeting 2011. (to appear).

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Microcomputer Control of a Hydraulically Actuated Piston.

DTIC Science & Technology

1987-06-01

EhhhohEohEmhhE EhhmhhhohhhhhI M1l *2 112.2 Ll 6 111111.258 MICROCOPY RESOLUfION TEST CHART NATIONAL BUREAUJ nF SIANDARDS 1963 A W* %i r f U V ~ S i V...SYSTE.M............................I( E. I REQUENCY RESPONSE TEST ........................... F. MODEL V.ALIDATION ................................. 2...O RITH M (BA SIC) ................................. 43 APPENDIX D: DIGITAL SYSTEM SIMULATION CODE (DSL) ........... 44 APPENDIX E: DIGITAL LOGIC TEST

KM3NeT Digital Optical Module electronics

NASA Astrophysics Data System (ADS)

Real, Diego

2016-04-01

The KM3NeT collaboration is currently building of a neutrino telescope with a volume of several cubic kilometres at the bottom of the Mediterranean Sea. The telescope consists of a matrix of Digital Optical Modules that will detect the Cherenkov light originated by the interaction of the neutrinos in the proximity of the detector. This contribution describes the main components of the read-out electronics of the Digital Optical Module: the Power Board, which delivers all the power supply required by the Digital Optical Molule electronics; the Central Logic Board, the main core of the read-out system, hosting 31 Time to Digital Converters with 1 ns resolution and the White Rabbit protocol embedded in the Central Logic Board Field Programmable Gate Array; the Octopus boards, that transfer the Low Voltage Digital Signals from the PMT bases to the Central Logic Board and finally the PMT bases, in charge of converting the analogue signal produced in the 31 3" PMTs into a Low Voltage Digital Signal.

Two-step digit-set-restricted modified signed-digit addition-subtraction algorithm and its optoelectronic implementation.

PubMed

Qian, F; Li, G; Ruan, H; Jing, H; Liu, L

1999-09-10

A novel, to our knowledge, two-step digit-set-restricted modified signed-digit (MSD) addition-subtraction algorithm is proposed. With the introduction of the reference digits, the operand words are mapped into an intermediate carry word with all digits restricted to the set {1, 0} and an intermediate sum word with all digits restricted to the set {0, 1}, which can be summed to form the final result without carry generation. The operation can be performed in parallel by use of binary logic. An optical system that utilizes an electron-trapping device is suggested for accomplishing the required binary logic operations. By programming of the illumination of data arrays, any complex logic operations of multiple variables can be realized without additional temporal latency of the intermediate results. This technique has a high space-bandwidth product and signal-to-noise ratio. The main structure can be stacked to construct a compact optoelectronic MSD adder-subtracter.

Ultralow-Power Digital Correlator for Microwave Polarimetry

NASA Technical Reports Server (NTRS)

Piepmeier, Jeffrey R.; Hass, K. Joseph

2004-01-01

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

High-performance image processing architecture

NASA Astrophysics Data System (ADS)

Coffield, Patrick C.

1992-04-01

The proposed architecture is a logical design specifically for image processing and other related computations. The design is a hybrid electro-optical concept consisting of three tightly coupled components: a spatial configuration processor (the optical analog portion), a weighting processor (digital), and an accumulation processor (digital). The systolic flow of data and image processing operations are directed by a control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra developed by the University of Florida. The algebra is capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution type operations to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of picture elements in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms. While a hybrid electro-optical implementation is of primary interest, the benefits and design issues of an all digital implementation are also discussed. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra's generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.

Learning fuzzy logic control system

NASA Technical Reports Server (NTRS)

Lung, Leung Kam

1994-01-01

The performance of the Learning Fuzzy Logic Control System (LFLCS), developed in this thesis, has been evaluated. The Learning Fuzzy Logic Controller (LFLC) learns to control the motor by learning the set of teaching values that are generated by a classical PI controller. It is assumed that the classical PI controller is tuned to minimize the error of a position control system of the D.C. motor. The Learning Fuzzy Logic Controller developed in this thesis is a multi-input single-output network. Training of the Learning Fuzzy Logic Controller is implemented off-line. Upon completion of the training process (using Supervised Learning, and Unsupervised Learning), the LFLC replaces the classical PI controller. In this thesis, a closed loop position control system of a D.C. motor using the LFLC is implemented. The primary focus is on the learning capabilities of the Learning Fuzzy Logic Controller. The learning includes symbolic representation of the Input Linguistic Nodes set and Output Linguistic Notes set. In addition, we investigate the knowledge-based representation for the network. As part of the design process, we implement a digital computer simulation of the LFLCS. The computer simulation program is written in 'C' computer language, and it is implemented in DOS platform. The LFLCS, designed in this thesis, has been developed on a IBM compatible 486-DX2 66 computer. First, the performance of the Learning Fuzzy Logic Controller is evaluated by comparing the angular shaft position of the D.C. motor controlled by a conventional PI controller and that controlled by the LFLC. Second, the symbolic representation of the LFLC and the knowledge-based representation for the network are investigated by observing the parameters of the Fuzzy Logic membership functions and the links at each layer of the LFLC. While there are some limitations of application with this approach, the result of the simulation shows that the LFLC is able to control the angular shaft position of the D.C. motor. Furthermore, the LFLC has better performance in rise time, settling time and steady state error than to the conventional PI controller. This abstract accurately represents the content of the candidate's thesis. I recommend its publication.

Development of ADOCS controllers and control laws. Volume 2: Literature review and preliminary analysis

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstrator aircraft which will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase as a function of ACAS characteristics; display mode switching logic. Findings from the literature review and the analysis and synthesis of desired control laws are reported in Volume 2. Conclusions drawn from pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

Development of ADOCS controllers and control laws. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstrator aircraft that will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered during the study are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase as a function of SCAS characteristics; display mode switching logic. Volume 1 is an Executive Summary of the study. Conclusions drawn from analysis of pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

Modern digital flight control system design for VTOL aircraft

NASA Technical Reports Server (NTRS)

Broussard, J. R.; Berry, P. W.; Stengel, R. F.

1979-01-01

Methods for and results from the design and evaluation of a digital flight control system (DFCS) for a CH-47B helicopter are presented. The DFCS employed proportional-integral control logic to provide rapid, precise response to automatic or manual guidance commands while following conventional or spiral-descent approach paths. It contained altitude- and velocity-command modes, and it adapted to varying flight conditions through gain scheduling. Extensive use was made of linear systems analysis techniques. The DFCS was designed, using linear-optimal estimation and control theory, and the effects of gain scheduling are assessed by examination of closed-loop eigenvalues and time responses.

A DNA Logic Gate Automaton for Detection of Rabies and Other Lyssaviruses.

PubMed

Vijayakumar, Pavithra; Macdonald, Joanne

2017-07-05

Immediate activation of biosensors is not always desirable, particularly if activation is due to non-specific interactions. Here we demonstrate the use of deoxyribozyme-based logic gate networks arranged into visual displays to precisely control activation of biosensors, and demonstrate a prototype molecular automaton able to discriminate between seven different genotypes of Lyssaviruses, including Rabies virus. The device uses novel mixed-base logic gates to enable detection of the large diversity of Lyssavirus sequence populations, while an ANDNOT logic gate prevents non-specific activation across genotypes. The resultant device provides a user-friendly digital-like, but molecule-powered, dot-matrix text output for unequivocal results read-out that is highly relevant for point of care applications. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Users manual for flight control design programs

NASA Technical Reports Server (NTRS)

Nalbandian, J. Y.

1975-01-01

Computer programs for the design of analog and digital flight control systems are documented. The program DIGADAPT uses linear-quadratic-gaussian synthesis algorithms in the design of command response controllers and state estimators, and it applies covariance propagation analysis to the selection of sampling intervals for digital systems. Program SCHED executes correlation and regression analyses for the development of gain and trim schedules to be used in open-loop explicit-adaptive control laws. A linear-time-varying simulation of aircraft motions is provided by the program TVHIS, which includes guidance and control logic, as well as models for control actuator dynamics. The programs are coded in FORTRAN and are compiled and executed on both IBM and CDC computers.

Boolean Approaches in Digital Diagnosis

DTIC Science & Technology

1989-12-04

Automation Conference, pages 64-70, 1983. 16. Barry W. Johnson. Design and A nalysis of Fault-Tolerant Digital Systems. Addison- Wesley Publishing...Mitchell. On a new algebra of logic. In C.S. Peirce, edhitor, Studies in Logic. Little, Brown. Boston. 1883. 2:3. Roger S. Pressman . Softwrare Engineering

Fundamental physics issues of multilevel logic in developing a parallel processor.

NASA Astrophysics Data System (ADS)

Bandyopadhyay, Anirban; Miki, Kazushi

2007-06-01

In the last century, On and Off physical switches, were equated with two decisions 0 and 1 to express every information in terms of binary digits and physically realize it in terms of switches connected in a circuit. Apart from memory-density increase significantly, more possible choices in particular space enables pattern-logic a reality, and manipulation of pattern would allow controlling logic, generating a new kind of processor. Neumann's computer is based on sequential logic, processing bits one by one. But as pattern-logic is generated on a surface, viewing whole pattern at a time is a truly parallel processing. Following Neumann's and Shannons fundamental thermodynamical approaches we have built compatible model based on series of single molecule based multibit logic systems of 4-12 bits in an UHV-STM. On their monolayer multilevel communication and pattern formation is experimentally verified. Furthermore, the developed intelligent monolayer is trained by Artificial Neural Network. Therefore fundamental weak interactions for the building of truly parallel processor are explored here physically and theoretically.

Digital controllers for VTOL aircraft

NASA Technical Reports Server (NTRS)

Stengel, R. F.; Broussard, J. R.; Berry, P. W.

1976-01-01

Using linear-optimal estimation and control techniques, digital-adaptive control laws have been designed for a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. Two distinct discrete-time control laws are designed to interface with velocity-command and attitude-command guidance logic, and each incorporates proportional-integral compensation for non-zero-set-point regulation, as well as reduced-order Kalman filters for sensor blending and noise rejection. Adaptation to flight condition is achieved with a novel gain-scheduling method based on correlation and regression analysis. The linear-optimal design approach is found to be a valuable tool in the development of practical multivariable control laws for vehicles which evidence significant coupling and insufficient natural stability.

Abstracts of ARI Research Publications, FY 1974 and 1975

DTIC Science & Technology

1979-10-01

may obtain these documents from the National Technical Information Service (NTIS), Department of Commerce, Springfield, Va., 22151. The six- digit AD...Siegel, A. I., Wolf, J. J., & Leahy, W. R. (Applied Psycho- logical Services, Inc.). A digital simulation model of message handling in the Tactical...inherent in the mission of interest, (b) incorporate these 28 into a logic for a digital simulation model, and (c) develop a computer program reflecting

Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

NASA Astrophysics Data System (ADS)

Ang, Yee Sin; Yang, Shengyuan A.; Zhang, C.; Ma, Zhongshui; Ang, L. K.

2017-12-01

Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over 10 000 % can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The (2 +1 ) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

Optical triple-in digital logic using nonlinear optical four-wave mixing

NASA Astrophysics Data System (ADS)

Widjaja, Joewono; Tomita, Yasuo

1995-08-01

A new programmable optical processor is proposed for implementing triple-in combinatorial digital logic that uses four-wave mixing. Binary-coded decimal-to-octal decoding is experimentally demonstrated by use of a photorefractive BaTiO 3 crystal. The result confirms the feasibility of the proposed system.

B-Plant Canyon Ventilation Control System Description

DOE Office of Scientific and Technical Information (OSTI.GOV)

MCDANIEL, K.S.

1999-08-31

Project W-059 installed a new B Plant Canyon Ventilation System. Monitoring and control of the system is implemented by the Canyon Ventilation Control System (CVCS). This document describes the CVCS system components which include a Programmable Logic Controller (PLC) coupled with an Operator Interface Unit (OIU) and application software. This document also includes an Alarm Index specifying the setpoints and technical basis for system analog and digital alarms.

Functionality and operation of fluoroscopic automatic brightness control/automatic dose rate control logic in modern cardiovascular and interventional angiography systems: A Report of Task Group 125 Radiography/Fluoroscopy Subcommittee, Imaging Physics Committee, Science Council

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rauch, Phillip; Lin, Pei-Jan Paul; Balter, Stephen

2012-05-15

Task Group 125 (TG 125) was charged with investigating the functionality of fluoroscopic automatic dose rate and image quality control logic in modern angiographic systems, paying specific attention to the spectral shaping filters and variations in the selected radiologic imaging parameters. The task group was also charged with describing the operational aspects of the imaging equipment for the purpose of assisting the clinical medical physicist with clinical set-up and performance evaluation. Although there are clear distinctions between the fluoroscopic operation of an angiographic system and its acquisition modes (digital cine, digital angiography, digital subtraction angiography, etc.), the scope of thismore » work was limited to the fluoroscopic operation of the systems studied. The use of spectral shaping filters in cardiovascular and interventional angiography equipment has been shown to reduce patient dose. If the imaging control algorithm were programmed to work in conjunction with the selected spectral filter, and if the generator parameters were optimized for the selected filter, then image quality could also be improved. Although assessment of image quality was not included as part of this report, it was recognized that for fluoroscopic imaging the parameters that influence radiation output, differential absorption, and patient dose are also the same parameters that influence image quality. Therefore, this report will utilize the terminology ''automatic dose rate and image quality'' (ADRIQ) when describing the control logic in modern interventional angiographic systems and, where relevant, will describe the influence of controlled parameters on the subsequent image quality. A total of 22 angiography units were investigated by the task group and of these one each was chosen as representative of the equipment manufactured by GE Healthcare, Philips Medical Systems, Shimadzu Medical USA, and Siemens Medical Systems. All equipment, for which measurement data were included in this report, was manufactured within the three year period from 2006 to 2008. Using polymethylmethacrylate (PMMA) plastic to simulate patient attenuation, each angiographic imaging system was evaluated by recording the following parameters: tube potential in units of kilovolts peak (kVp), tube current in units of milliamperes (mA), pulse width (PW) in units of milliseconds (ms), spectral filtration setting, and patient air kerma rate (PAKR) as a function of the attenuator thickness. Data were graphically plotted to reveal the manner in which the ADRIQ control logic responded to changes in object attenuation. There were similarities in the manner in which the ADRIQ control logic operated that allowed the four chosen devices to be divided into two groups, with two of the systems in each group. There were also unique approaches to the ADRIQ control logic that were associated with some of the systems, and these are described in the report. The evaluation revealed relevant information about the testing procedure and also about the manner in which different manufacturers approach the utilization of spectral filtration, pulsed fluoroscopy, and maximum PAKR limitation. This information should be particularly valuable to the clinical medical physicist charged with acceptance testing and performance evaluation of modern angiographic systems.« less

Functionality and operation of fluoroscopic automatic brightness control/automatic dose rate control logic in modern cardiovascular and interventional angiography systems: a report of Task Group 125 Radiography/Fluoroscopy Subcommittee, Imaging Physics Committee, Science Council.

PubMed

Rauch, Phillip; Lin, Pei-Jan Paul; Balter, Stephen; Fukuda, Atsushi; Goode, Allen; Hartwell, Gary; LaFrance, Terry; Nickoloff, Edward; Shepard, Jeff; Strauss, Keith

2012-05-01

Task Group 125 (TG 125) was charged with investigating the functionality of fluoroscopic automatic dose rate and image quality control logic in modern angiographic systems, paying specific attention to the spectral shaping filters and variations in the selected radiologic imaging parameters. The task group was also charged with describing the operational aspects of the imaging equipment for the purpose of assisting the clinical medical physicist with clinical set-up and performance evaluation. Although there are clear distinctions between the fluoroscopic operation of an angiographic system and its acquisition modes (digital cine, digital angiography, digital subtraction angiography, etc.), the scope of this work was limited to the fluoroscopic operation of the systems studied. The use of spectral shaping filters in cardiovascular and interventional angiography equipment has been shown to reduce patient dose. If the imaging control algorithm were programmed to work in conjunction with the selected spectral filter, and if the generator parameters were optimized for the selected filter, then image quality could also be improved. Although assessment of image quality was not included as part of this report, it was recognized that for fluoroscopic imaging the parameters that influence radiation output, differential absorption, and patient dose are also the same parameters that influence image quality. Therefore, this report will utilize the terminology "automatic dose rate and image quality" (ADRIQ) when describing the control logic in modern interventional angiographic systems and, where relevant, will describe the influence of controlled parameters on the subsequent image quality. A total of 22 angiography units were investigated by the task group and of these one each was chosen as representative of the equipment manufactured by GE Healthcare, Philips Medical Systems, Shimadzu Medical USA, and Siemens Medical Systems. All equipment, for which measurement data were included in this report, was manufactured within the three year period from 2006 to 2008. Using polymethylmethacrylate (PMMA) plastic to simulate patient attenuation, each angiographic imaging system was evaluated by recording the following parameters: tube potential in units of kilovolts peak (kVp), tube current in units of milliamperes (mA), pulse width (PW) in units of milliseconds (ms), spectral filtration setting, and patient air kerma rate (PAKR) as a function of the attenuator thickness. Data were graphically plotted to reveal the manner in which the ADRIQ control logic responded to changes in object attenuation. There were similarities in the manner in which the ADRIQ control logic operated that allowed the four chosen devices to be divided into two groups, with two of the systems in each group. There were also unique approaches to the ADRIQ control logic that were associated with some of the systems, and these are described in the report. The evaluation revealed relevant information about the testing procedure and also about the manner in which different manufacturers approach the utilization of spectral filtration, pulsed fluoroscopy, and maximum PAKR limitation. This information should be particularly valuable to the clinical medical physicist charged with acceptance testing and performance evaluation of modern angiographic systems.

Principles of logic and the use of digital geographic information systems

USGS Publications Warehouse

Robinove, Charles Joseph

1986-01-01

Digital geographic information systems allow many different types of data to be spatially and statistically analyzed. Logical operations can be performed on individual or multiple data planes by algorithms that can be implemented in computer systems. Users and creators of the systems should fully understand these operations. This paper describes the relationships of layers and features in geographic data bases and the principles of logic that can be applied by geographic information systems and suggests that a thorough knowledge of the data that are entered into a geographic data base and of the logical operations will produce results that are most satisfactory to the user. Methods of spatial analysis are reduced to their primitive logical operations and explained to further such understanding.

Digital temperature and velocity control of mach 0.3 atmospheric pressure durability testing burner rigs in long time, unattended cyclic testing

NASA Technical Reports Server (NTRS)

Deadmore, D. L.

1985-01-01

Hardware and software were developed to implement the hybrid digital control of two Jet A-1 fueled Mach 0.3 burners from startup to completion of a preset number of hot corrosion flame durability cycle tests of materials at 1652 F. This was accomplished by use of a basic language programmable microcomputer and data aquisition and control unit connected together by the IEEE-488 Bus. The absolute specimen temperature was controlled to + or - 3 F by use of digital adjustment of the fuel flow using a P-I-D (Proportional-Integral-Derivative) control algorithm. The specimen temperature was within + or - 2 F of the set point more than 90 percent of the time. Pressure control was achieved by digital adjustment of the combustion air flow using a proportional control algorithm. The burner pressure was controlled at 1.0 + or - 0.02 psig. Logic schemes were incorporated into the system to protect the test specimen from abnormal test conditions in the event of a hardware of software malfunction.

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

NASA Technical Reports Server (NTRS)

Athale, R. A.; Lee, S. H.

1978-01-01

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

Visual-area coding technique (VACT): optical parallel implementation of fuzzy logic and its visualization with the digital-halftoning process

NASA Astrophysics Data System (ADS)

Konishi, Tsuyoshi; Tanida, Jun; Ichioka, Yoshiki

1995-06-01

A novel technique, the visual-area coding technique (VACT), for the optical implementation of fuzzy logic with the capability of visualization of the results is presented. This technique is based on the microfont method and is considered to be an instance of digitized analog optical computing. Huge amounts of data can be processed in fuzzy logic with the VACT. In addition, real-time visualization of the processed result can be accomplished.

NASA Lewis F100 engine testing

NASA Technical Reports Server (NTRS)

Werner, R. A.; Willoh, R. G., Jr.; Abdelwahab, M.

1984-01-01

Two builds of an F100 engine model derivative (EMD) engine were evaluated for improvements in engine components and digital electronic engine control (DEEC) logic. Two DEEC flight logics were verified throughout the flight envelope in support of flight clearance for the F100 engine model derivative program (EMPD). A nozzle instability and a faster augmentor transient capability was investigated in support of the F-15 DEEC flight program. Off schedule coupled system mode fan flutter, DEEC nose-boom pressure correlation, DEEC station six pressure comparison, and a new fan inlet variable vane (CIVV) schedule are identified.

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

PubMed

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

Recognizing and engineering digital-like logic gates and switches in gene regulatory networks.

PubMed

Bradley, Robert W; Buck, Martin; Wang, Baojun

2016-10-01

A central aim of synthetic biology is to build organisms that can perform useful activities in response to specified conditions. The digital computing paradigm which has proved so successful in electrical engineering is being mapped to synthetic biological systems to allow them to make such decisions. However, stochastic molecular processes have graded input-output functions, thus, bioengineers must select those with desirable characteristics and refine their transfer functions to build logic gates with digital-like switching behaviour. Recent efforts in genome mining and the development of programmable RNA-based switches, especially CRISPRi, have greatly increased the number of parts available to synthetic biologists. Improvements to the digital characteristics of these parts are required to enable robust predictable design of deeply layered logic circuits. Copyright © 2016 The Author(s). Published by Elsevier Ltd.. All rights reserved.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

This paper suggests a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to) zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is to demonstrate how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

The objective of this paper is to motivate a new class of digital logic. OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include: (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, (5) free space leverage of GIBP (gate interconnect bandwidth product). Other well-known secondary advantages of optical logic include (but are not limited to): zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is on demonstrating how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes will be discussed only in the context of introducing the DOC III architecture.

Multi-valued logic gates based on ballistic transport in quantum point contacts.

PubMed

Seo, M; Hong, C; Lee, S-Y; Choi, H K; Kim, N; Chung, Y; Umansky, V; Mahalu, D

2014-01-22

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

Translations on Eastern Europe Scientific Affairs, Number 560

DTIC Science & Technology

1977-10-04

Miklos Szilagyi . TAPNEG; prepares digitalized printed wiring diagram control punch tape on an ADMAP-2 graphing machine with reflection on the x axis...FOKAL 16 KE; BME, Dr Zsolt Illyefalvi-Vitez; BME, Dr Miklos Szilagyi . TESTOP-10; the program provides measurement and diagnostics for logic cards

Community Digital Library Requirements for the Southern California Earthquake Center Community Modeling Environment (SCEC/CME)

NASA Astrophysics Data System (ADS)

Moore, R.; Faerman, M.; Minster, J.; Day, S. M.; Ely, G.

2003-12-01

A community digital library provides support for ingestion, organization, description, preservation, and access of digital entities. The technologies that traditionally provide these capabilities are digital libraries (ingestion, organization, description), persistent archives (preservation) and data grids (access). We present a design for the SCEC community digital library that incorporates aspects of all three systems. Multiple groups have created integrated environments that sustain large-scale scientific data collections. By examining these projects, the following stages of implementation can be identified: \\begin{itemize} Definition of semantic terms to associate with relevant information. This includes definition of uniform content descriptors to describe physical quantities relevant to the scientific discipline, and creation of concept spaces to define how the uniform content descriptors are logically related. Organization of digital entities into logical collections that make it simple to browse and manage related material. Definition of services that are used to access and manipulate material in the collection. Creation of a preservation environment for the long-term management of the collection. Each community is faced with heterogeneity that is introduced when data is distributed across multiple sites, or when multiple sets of collection semantics are used, and or when multiple scientific sub-disciplines are federated. We will present the relevant standards that simplify the implementation of the SCEC community library, the resource requirements for different types of data sets that drive the implementation, and the digital library processes that the SCEC community library will support. The SCEC community library can be viewed as the set of processing steps that are required to build the appropriate SCEC reference data sets (SCEC approved encoding format, SCEC approved descriptive metadata, SCEC approved collection organization, and SCEC managed storage location). Each digital entity that is ingested into the SCEC community library is processed and validated for conformance to SCEC standards. These steps generate provenance, descriptive, administrative, structural, and behavioral metadata. Using data grid technology, the descriptive metadata can be registered onto a logical name space that is controlled and managed by the SCEC digital library. A version of the SCEC community digital library is being implemented in the Storage Resource Broker. The SRB system provides almost all the features enumerated above. The peer-to-peer federation of metadata catalogs is planned for release in September, 2003. The SRB system is in production use in multiple projects, from high-energy physics, to astronomy, to earth systems science, to bio-informatics. The SCEC community library will be based on the definition of standard metadata attributes, the creation of logical collections within the SRB, the creation of access services, and the demonstration of a preservation environment. The use of the SRB for the SCEC digital library will sustain the expected collection size and collection capabilities.

Development of ADOCS controllers and control laws. Volume 3: Simulation results and recommendations

NASA Technical Reports Server (NTRS)

Landis, Kenneth H.; Glusman, Steven I.

1985-01-01

The Advanced Cockpit Controls/Advanced Flight Control System (ACC/AFCS) study was conducted by the Boeing Vertol Company as part of the Army's Advanced Digital/Optical Control System (ADOCS) program. Specifically, the ACC/AFCS investigation was aimed at developing the flight control laws for the ADOCS demonstator aircraft which will provide satisfactory handling qualities for an attack helicopter mission. The three major elements of design considered are as follows: Pilot's integrated Side-Stick Controller (SSC) -- Number of axes controlled; force/displacement characteristics; ergonomic design. Stability and Control Augmentation System (SCAS)--Digital flight control laws for the various mission phases; SCAS mode switching logic. Pilot's Displays--For night/adverse weather conditions, the dynamics of the superimposed symbology presented to the pilot in a format similar to the Advanced Attack Helicopter (AAH) Pilot Night Vision System (PNVS) for each mission phase is a function of SCAS characteristics; display mode switching logic. Results of the five piloted simulations conducted at the Boeing Vertol and NASA-Ames simulation facilities are presented in Volume 3. Conclusions drawn from analysis of pilot rating data and commentary were used to formulate recommendations for the ADOCS demonstrator flight control system design. The ACC/AFCS simulation data also provide an extensive data base to aid the development of advanced flight control system design for future V/STOL aircraft.

Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

NASA Astrophysics Data System (ADS)

Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

2015-02-01

A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer，a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

Wide Tuning Capability for Spacecraft Transponders

NASA Technical Reports Server (NTRS)

Lux, James; Mysoor, Narayan; Shah, Biren; Cook, Brian; Smith, Scott

2007-01-01

A document presents additional information on the means of implementing a capability for wide tuning of microwave receiver and transmitter frequencies in the development reported in the immediately preceding article, VCO PLL Frequency Synthesizers for Spacecraft Transponders (NPO- 42909). The reference frequency for a PLL-based frequency synthesizer is derived from a numerically controlled oscillator (NCO) implemented in digital logic, such that almost any reference frequency can be derived from a fixed crystal reference oscillator with microhertz precision. The frequency of the NCO is adjusted to track the received signal, then used to create another NCO frequency used to synthesize the transmitted signal coherent with, and at a specified frequency ratio to, the received signal. The frequencies can be changed, even during operation, through suitable digital programming. The NCOs and the related tracking loops and coherent turnaround logic are implemented in a field-programmable gate array (FPGA). The interface between the analog microwave receiver and transmitter circuits and the FPGA includes analog-to-digital and digital-toanalog converters, the sampling rates of which are chosen to minimize spurious signals and otherwise optimize performance. Several mixers and filters are used to properly route various signals.

Direct Digital Control of HVAC (Heating, Ventilating, and Air Conditioning).

DTIC Science & Technology

1985-01-01

controller func- tions such as time-of-day, economizer cycles, reset, load shedding, chiller optimization , VAV fan synchronization, and optimum start/stop...control system such as that illustrated in Fig- urc 4. Data on setpoints , reset schedules, and event timing, such as that presented in Figure 6, are...program code (Figure 7). In addition to the control logic, setpoint and other data are readily available. Program logi:, setpoint and schedule data, and

The research of laser marking control technology

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong

2009-08-01

In the area of Laser marking, the general control method is insert control card to computer's mother board, it can not support hot swap, it is difficult to assemble or it. Moreover, the one marking system must to equip one computer. In the system marking, the computer can not to do the other things except to transmit marking digital information. Otherwise it can affect marking precision. Based on traditional control methods existed some problems, introduced marking graphic editing and digital processing by the computer finish, high-speed digital signal processor (DSP) control marking the whole process. The laser marking controller is mainly contain DSP2812, digital memorizer, DAC (digital analog converting) transform unit circuit, USB interface control circuit, man-machine interface circuit, and other logic control circuit. Download the marking information which is processed by computer to U disk, DSP read the information by USB interface on time, then processing it, adopt the DSP inter timer control the marking time sequence, output the scanner control signal by D/A parts. Apply the technology can realize marking offline, thereby reduce the product cost, increase the product efficiency. The system have good effect in actual unit markings, the marking speed is more quickly than PCI control card to 20 percent. It has application value in practicality.

Design on the x-ray oral digital image display card

NASA Astrophysics Data System (ADS)

Wang, Liping; Gu, Guohua; Chen, Qian

2009-10-01

According to the main characteristics of X-ray imaging, the X-ray display card is successfully designed and debugged using the basic principle of correlated double sampling (CDS) and combined with embedded computer technology. CCD sensor drive circuit and the corresponding procedures have been designed. Filtering and sampling hold circuit have been designed. The data exchange with PC104 bus has been implemented. Using complex programmable logic device as a device to provide gating and timing logic, the functions which counting, reading CPU control instructions, corresponding exposure and controlling sample-and-hold have been completed. According to the image effect and noise analysis, the circuit components have been adjusted. And high-quality images have been obtained.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

Logic circuit detects both present and missing negative pulses in superimposed wave trains

NASA Technical Reports Server (NTRS)

Rice, R. E.

1967-01-01

Pulse divide and determination network provides a logical determination of pulse presence within a data train. The network uses digital logic circuitry to divide positive and negative pulses, to shape the separated pulses, and to determine, by means of coincidence logic, if negative pulses are missing from the pulse train.

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Compton suppression and event triggering in a commercial data acquisition system

NASA Astrophysics Data System (ADS)

Tabor, Samuel; Caussyn, D. D.; Tripathi, Vandana; Vonmoss, J.; Liddick, S. N.

2012-10-01

A number of groups are starting to use flash digitizer systems to directly convert the preamplifier signals of high-resolution Ge detectors to a stream of digital data. Some digitizers are also equipped with software constant fraction discriminator algorithms capable of operating on the resulting digital data stream to provide timing information. Because of the dropping cost per channel of these systems, it should now be possible to also connect outputs of the Bismuth Germanate (BGO) scintillators used for Compton suppression to other digitizer inputs so that BGO logic signals can also be available in the same system. This provides the possibility to perform all the Compton suppression and multiplicity trigger logic within the digital system, thus eliminating the need for separate timing filter amplifiers (TFA), constant fraction discriminators (CFD), logic units, and lots of cables. This talk will describe the performance of such a system based on Pixie16 modules from XIA LLC with custom field programmable gate array (FPGA) programming for an array of Compton suppressed single Ge crystal and 4-crystal ``Clover'' detector array along with optional particle detectors. Initial tests of the system have produced results comparable with the current traditional system of individual electronics and peak sensing analog to digital converters. The advantages of the all digital system will be discussed.

Three phase AC motor controller

DOEpatents

Vuckovich, Michael; Wright, Maynard K.; Burkett, John P.

1984-03-20

A motor controller for a three phase AC motor (10) which is adapted to operate bidirectionally from signals received either from a computer (30) or a manual control (32). The controller is comprised of digital logic circuit means which implement a forward and reverse command signal channel (27, 29) for the application of power through the forward and reverse power switching relays (16, 18, 20, 22). The digital logic elements are cross coupled to prevent activation of both channels simultaneously and each includes a plugging circuit (65, 67) for stopping the motor upon the removal of control signal applied to one of the two channels (27, 29) for a direction of rotation desired. Each plugging circuit (65, 67) includes a one-shot pulse signal generator (88, 102) which outputs a single pulse signal of predetermined pulsewidth which is adapted to inhibit further operation of the application of power in the channel which is being activated and to apply a reversal command signal to the other channel which provides a reversed phase application of power to the motor for a period defined by the pulse-width output of the one-shot signal generator to plug the motor (10) which will then be inoperative until another rotational command signal is applied to either of the two channels.

Implementing finite state machines in a computer-based teaching system

NASA Astrophysics Data System (ADS)

Hacker, Charles H.; Sitte, Renate

1999-09-01

Finite State Machines (FSM) are models for functions commonly implemented in digital circuits such as timers, remote controls, and vending machines. Teaching FSM is core in the curriculum of many university digital electronic or discrete mathematics subjects. Students often have difficulties grasping the theoretical concepts in the design and analysis of FSM. This has prompted the author to develop an MS-WindowsTM compatible software, WinState, that provides a tutorial style teaching aid for understanding the mechanisms of FSM. The animated computer screen is ideal for visually conveying the required design and analysis procedures. WinState complements other software for combinatorial logic previously developed by the author, and enhances the existing teaching package by adding sequential logic circuits. WinState enables the construction of a students own FSM, which can be simulated, to test the design for functionality and possible errors.

Using Software Simulators to Enhance the Learning of Digital Logic Design for the Information Technology Students

ERIC Educational Resources Information Center

Alsadoon, Abeer; Prasad, P. W. C.; Beg, Azam

2017-01-01

Making the students understand the theoretical concepts of digital logic design concepts is one of the major issues faced by the academics, therefore the teachers have tried different techniques to link the theoretical information to the practical knowledge. Use of software simulations is a technique for learning and practice that can be applied…

The MK VI - A second generation attitude control system

NASA Astrophysics Data System (ADS)

Meredith, P. J.

1986-10-01

The MK VI, a new multipurpose attitude control system for the exoatmospheric attitude control of sounding rocket payloads, is described. The system employs reprogrammable microcomputer memory for storage of basic control logic and for specific mission event control data. The paper includes descriptions of MK VI specifications and configuration; sensor characteristics; the electronic, analog, and digital sections; the pneumatic system; ground equipment; the system operation; and software. A review of the MK VI performance for the Comet Halley flight is presented. Block diagrams are included.

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

A simple second-order digital phase-locked loop.

NASA Technical Reports Server (NTRS)

Tegnelia, C. R.

1972-01-01

A simple second-order digital phase-locked loop has been designed for the Viking Orbiter 1975 command system. Excluding analog-to-digital conversion, implementation of the loop requires only an adder/subtractor, two registers, and a correctable counter with control logic. The loop considers only the polarity of phase error and corrects system clocks according to a filtered sequence of this polarity. The loop is insensitive to input gain variation, and therefore offers the advantage of stable performance over long life. Predictable performance is guaranteed by extreme reliability of acquisition, yet in the steady state the loop produces only a slight degradation with respect to analog loop performance.

All-digital GPS receiver mechanization

NASA Astrophysics Data System (ADS)

Ould, P. C.; van Wechel, R. J.

The paper describes the all-digital baseband correlation processing of GPS signals, which is characterized by (1) a potential for improved antijamming performance, (2) fast acquisition by a digital matched filter, (3) reduction of adjustment, (4) increased system reliability, and (5) provision of a basis for the realization of a high degree of VLSI potential for the development of small economical GPS sets. The basic technical approach consists of a broadband fix-tuned RF converter followed by a digitizer; digital-matched-filter acquisition section; phase- and delay-lock tracking via baseband digital correlation; software acquisition logic and loop filter implementation; and all-digital implementation of the feedback numerical controlled oscillators and code generator. Broadband in-phase and quadrature tracking is performed by an arctangent angle detector followed by a phase-unwrapping algorithm that eliminates false locks induced by sampling and data bit transitions, and yields a wide pull-in frequency range approaching one-fourth of the loop iteration frequency.

Introduction to Digital Logic Systems for Energy Monitoring and Control Systems.

DTIC Science & Technology

1985-05-01

computer were first set down by Charles Babbage in 1830. An additional criteria was proposed by Von Neumann in 1947. These criteria state: (1) An input means...criteria requirements as set down by Babbage and Von Neumann. The computer equipment ("hardware") and internal operating system ("software

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

NASA Astrophysics Data System (ADS)

Bazydło, Grzegorz; Wiśniewski, Remigiusz

2016-09-01

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

WNN 92; Proceedings of the 3rd Workshop on Neural Networks: Academic/Industrial/NASA/Defense, Auburn Univ., AL, Feb. 10-12, 1992 and South Shore Harbour, TX, Nov. 4-6, 1992

NASA Technical Reports Server (NTRS)

Padgett, Mary L. (Editor)

1993-01-01

The present conference discusses such neural networks (NN) related topics as their current development status, NN architectures, NN learning rules, NN optimization methods, NN temporal models, NN control methods, NN pattern recognition systems and applications, biological and biomedical applications of NNs, VLSI design techniques for NNs, NN systems simulation, fuzzy logic, and genetic algorithms. Attention is given to missileborne integrated NNs, adaptive-mixture NNs, implementable learning rules, an NN simulator for travelling salesman problem solutions, similarity-based forecasting, NN control of hypersonic aircraft takeoff, NN control of the Space Shuttle Arm, an adaptive NN robot manipulator controller, a synthetic approach to digital filtering, NNs for speech analysis, adaptive spline networks, an anticipatory fuzzy logic controller, and encoding operations for fuzzy associative memories.

Integration of plug-in hybrid electric vehicles (PHEV) with grid connected residential photovoltaic energy systems

NASA Astrophysics Data System (ADS)

Nagarajan, Adarsh; Shireen, Wajiha

2013-06-01

This paper proposes an approach for integrating Plug-In Hybrid Electric Vehicles (PHEV) to an existing residential photovoltaic system, to control and optimize the power consumption of residential load. Control involves determining the source from which residential load will be catered, where as optimization of power flow reduces the stress on the grid. The system built to achieve the goal is a combination of the existing residential photovoltaic system, PHEV, Power Conditioning Unit (PCU), and a controller. The PCU involves two DC-DC Boost Converters and an inverter. This paper emphasizes on developing the controller logic and its implementation in order to accommodate the flexibility and benefits of the proposed integrated system. The proposed controller logic has been simulated using MATLAB SIMULINK and further implemented using Digital Signal Processor (DSP) microcontroller, TMS320F28035, from Texas Instruments

Enhanced Control for Local Helicity Injection on the Pegasus ST

NASA Astrophysics Data System (ADS)

Pierren, C.; Bongard, M. W.; Fonck, R. J.; Lewicki, B. T.; Perry, J. M.

2017-10-01

Local helicity injection (LHI) experiments on Pegasus rely upon programmable control of a 250 MVA modular power supply system that drives the electromagnets and helicity injection systems. Precise control of the central solenoid is critical to experimental campaigns that test the LHI Taylor relaxation limit and the coupling efficiency of LHI-produced plasmas to Ohmic current drive. Enhancement and expansion of the present control system is underway using field programmable gate array (FPGA) technology for digital logic and control, coupled to new 10 MHz optical-to-digital transceivers for semiconductor level device communication. The system accepts optical command signals from existing analog feedback controllers, transmits them to multiple devices in parallel H-bridges, and aggregates their status signals for fault detection. Present device-level multiplexing/de-multiplexing and protection logic is extended to include bridge-level protections with the FPGA. An input command filter protects against erroneous and/or spurious noise generated commands that could otherwise cause device failures. Fault registration and response times with the FPGA system are 25 ns. Initial system testing indicates an increased immunity to power supply induced noise, enabling plasma operations at higher working capacitor bank voltage. This can increase the applied helicity injection drive voltage, enable longer pulse lengths and improve Ohmic loop voltage control. Work supported by US DOE Grant DE-FG02-96ER54375.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

A reconfigurable cryogenic platform for the classical control of quantum processors

NASA Astrophysics Data System (ADS)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

A reconfigurable cryogenic platform for the classical control of quantum processors.

PubMed

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Ferrari, Giorgio; Prati, Enrico; Sebastiano, Fabio; Charbon, Edoardo

2017-04-01

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

Direct Digital Control of HVAC (Heating, Ventilating, and Air Conditioning Equipment (User’s Guide)

DTIC Science & Technology

1985-01-01

reset, load shedding, chiller optimization , VAV fan synchronization, and optimum start/stop. The prospective buyer of a DDC system should investigate...current and accurate drawings for a conventional, built-up control system such as that illustrated in Fig- ure 4. Data on setpoints , reset schedules, and...are always available in the form of the computer program code (Figure 7). In addition to the control logic, setpoint and other data are readily

Digital Poetry: A Narrow Relation between Poetics and the Codes of the Computational Logic

NASA Astrophysics Data System (ADS)

Laurentiz, Silvia

The project "Percorrendo Escrituras" (Walking Through Writings Project) has been developed at ECA-USP Fine Arts Department. Summarizing, it intends to study different structures of digital information that share the same universe and are generators of a new aesthetics condition. The aim is to search which are the expressive possibilities of the computer among the algorithm functions and other of its specific properties. It is a practical, theoretical and interdisciplinary project where the study of programming evolutionary language, logic and mathematics take us to poetic experimentations. The focus of this research is the digital poetry, and it comes from poetics of permutation combinations and culminates with dynamic and complex systems, autonomous, multi-user and interactive, through agents generation derivations, filtration and emergent standards. This lecture will present artworks that use some mechanisms introduced by cybernetics and the notion of system in digital poetry that demonstrate the narrow relationship between poetics and the codes of computational logic.

Synthetic mixed-signal computation in living cells

PubMed Central

Rubens, Jacob R.; Selvaggio, Gianluca; Lu, Timothy K.

2016-01-01

Living cells implement complex computations on the continuous environmental signals that they encounter. These computations involve both analogue- and digital-like processing of signals to give rise to complex developmental programs, context-dependent behaviours and homeostatic activities. In contrast to natural biological systems, synthetic biological systems have largely focused on either digital or analogue computation separately. Here we integrate analogue and digital computation to implement complex hybrid synthetic genetic programs in living cells. We present a framework for building comparator gene circuits to digitize analogue inputs based on different thresholds. We then demonstrate that comparators can be predictably composed together to build band-pass filters, ternary logic systems and multi-level analogue-to-digital converters. In addition, we interface these analogue-to-digital circuits with other digital gene circuits to enable concentration-dependent logic. We expect that this hybrid computational paradigm will enable new industrial, diagnostic and therapeutic applications with engineered cells. PMID:27255669

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1997-11-04

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a ``hardwired`` processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer. 19 figs.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1997-01-01

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a "hardwired" processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer.

A psychometric evaluation of the digital logic concept inventory

NASA Astrophysics Data System (ADS)

Herman, Geoffrey L.; Zilles, Craig; Loui, Michael C.

2014-10-01

Concept inventories hold tremendous promise for promoting the rigorous evaluation of teaching methods that might remedy common student misconceptions and promote deep learning. The measurements from concept inventories can be trusted only if the concept inventories are evaluated both by expert feedback and statistical scrutiny (psychometric evaluation). Classical Test Theory and Item Response Theory provide two psychometric frameworks for evaluating the quality of assessment tools. We discuss how these theories can be applied to assessment tools generally and then apply them to the Digital Logic Concept Inventory (DLCI). We demonstrate that the DLCI is sufficiently reliable for research purposes when used in its entirety and as a post-course assessment of students' conceptual understanding of digital logic. The DLCI can also discriminate between students across a wide range of ability levels, providing the most information about weaker students' ability levels.

Digitized synchronous demodulator

NASA Technical Reports Server (NTRS)

Woodhouse, Christopher E. (Inventor)

1990-01-01

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

PubMed Central

Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. PMID:24574913

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

ECL gate array with integrated PLL-based clock recovery and synthesis for high-speed data and telecom applications

NASA Astrophysics Data System (ADS)

Rosky, David S.; Coy, Bruce H.; Friedmann, Marc D.

1992-03-01

A 2500 gate mixed signal gate array has been developed that integrates custom PLL-based clock recovery and clock synthesis functions with 2500 gates of configurable logic cells to provide a single chip solution for 200 - 1244 MHz fiber based digital interface applications. By customizing the digital logic cells, any of the popular telecom and datacom standards may be implemented.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Variable current speed controller for eddy current motors

DOEpatents

Gerth, H.L.; Bailey, J.M.; Casstevens, J.M.; Dixon, J.H.; Griffith, B.O.; Igou, R.E.

1982-03-12

A speed control system for eddy current motors is provided in which the current to the motor from a constant frequency power source is varied by comparing the actual motor speed signal with a setpoint speed signal to control the motor speed according to the selected setpoint speed. A three-phase variable voltage autotransformer is provided for controlling the voltage from a three-phase power supply. A corresponding plurality of current control resistors is provided in series with each phase of the autotransformer output connected to inputs of a three-phase motor. Each resistor is connected in parallel with a set of normally closed contacts of plurality of relays which are operated by control logic. A logic circuit compares the selected speed with the actual motor speed obtained from a digital tachometer monitoring the motor spindle speed and operated the relays to add or substract resistance equally in each phase of the motor input to vary the motor current to control the motor at the selected speed.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

Ideas in Practice (3): A Simulated Laboratory Experience in Digital Design.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

1988-01-01

Gives an example of the use of a simplified logic simulator in a logic design course. Discusses some problems in logic design classes, commercially available software, and software problems. Describes computer-aided engineering (CAE) software. Lists 14 experiments in the simulated laboratory and presents students' evaluation of the course. (YP)

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

Encoding Schemes For A Digital Optical Multiplier Using The Modified Signed-Digit Number Representation

NASA Astrophysics Data System (ADS)

Lasher, Mark E.; Henderson, Thomas B.; Drake, Barry L.; Bocker, Richard P.

1986-09-01

The modified signed-digit (MSD) number representation offers full parallel, carry-free addition. A MSD adder has been described by the authors. This paper describes how the adder can be used in a tree structure to implement an optical multiply algorithm. Three different optical schemes, involving position, polarization, and intensity encoding, are proposed for realizing the trinary logic system. When configured in the generic multiplier architecture, these schemes yield the combinatorial logic necessary to carry out the multiplication algorithm. The optical systems are essentially three dimensional arrangements composed of modular units. Of course, this modularity is important for design considerations, while the parallelism and noninterfering communication channels of optical systems are important from the standpoint of reduced complexity. The authors have also designed electronic hardware to demonstrate and model the combinatorial logic required to carry out the algorithm. The electronic and proposed optical systems will be compared in terms of complexity and speed.

Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter

NASA Astrophysics Data System (ADS)

Sun, Degui; Wang, Na-Xin; He, Li-Ming; Weng, Zhao-Heng; Wang, Daheng; Chen, Ray T.

1996-06-01

A space-position-logic-encoding scheme is proposed and demonstrated. This encoding scheme not only makes the best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed- digit (MSD) numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtractor is built using optoelectronic switch technologies in conjunction with fiber-multistage 3D optoelectronic interconnects. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. In addition, the performance of the optoelectronic switches used in this system is experimentally studied and verified. Both the 3-bit experimental model and the experimental results of a parallel addition and a parallel subtraction are provided and discussed. Finally, the speed ratio between the MSD adder and binary adders is discussed and the advantage of the MSD in operating speed is demonstrated.

The effect of prior education on students' competency in digital logic: the case of ultraorthodox Jewish students

NASA Astrophysics Data System (ADS)

Ben-David Kolikant, Yifat; Genut, Sara

2017-10-01

In line with the growing interest in extending the diversity of CS students, we examined the performance of a unique group of students studying an introductory course in Digital logic: ultraorthodox Jewish men, whose previous education was based mostly on studying Talmud and who lacked a conventional high-school education. We used questions from the Digital Logic Concept Inventory . We compared the results to those of religious Jewish men with a conventional high-school education, and to the results reported in the literature. The ultraorthodox group performed better than the other groups in tasks that concerned number representation. No other statistically significant differences were found. Talk-aloud protocols revealed that the ultraorthodox students utilized a viable conceptual understanding in their performance. We can conclude that students' unique, alternative prior education should not be merely viewed as an obstacle to their academic studies, but also as a potential source for strengths.

Precision electronic speed controller for an alternating-current motor

DOEpatents

Bolie, V.W.

A high precision controller for an alternating-current multi-phase electrical motor that is subject to a large inertial load. The controller was developed for controlling, in a neutron chopper system, a heavy spinning rotor that must be rotated in phase-locked synchronism with a reference pulse train that is representative of an ac power supply signal having a meandering line frequency. The controller includes a shaft revolution sensor which provides a feedback pulse train representative of the actual speed of the motor. An internal digital timing signal generator provides a reference signal which is compared with the feedback signal in a computing unit to provide a motor control signal. The motor control signal is a weighted linear sum of a speed error voltage, a phase error voltage, and a drift error voltage, each of which is computed anew with each revolution of the motor shaft. The speed error signal is generated by a novel vernier-logic circuit which is drift-free and highly sensitive to small speed changes. The phase error is also computed by digital logic, with adjustable sensitivity around a 0 mid-scale value. The drift error signal, generated by long-term counting of the phase error, is used to compensate for any slow changes in the average friction drag on the motor. An auxillary drift-byte status sensor prevents any disruptive overflow or underflow of the drift-error counter. An adjustable clocked-delay unit is inserted between the controller and the source of the reference pulse train to permit phase alignment of the rotor to any desired offset angle. The stator windings of the motor are driven by two amplifiers which are provided with input signals having the proper quadrature relationship by an exciter unit consisting of a voltage controlled oscillator, a binary counter, a pair of read-only memories, and a pair of digital-to-analog converters.

Separating Business Logic from Medical Knowledge in Digital Clinical Workflows Using Business Process Model and Notation and Arden Syntax.

PubMed

de Bruin, Jeroen S; Adlassnig, Klaus-Peter; Leitich, Harald; Rappelsberger, Andrea

2018-01-01

Evidence-based clinical guidelines have a major positive effect on the physician's decision-making process. Computer-executable clinical guidelines allow for automated guideline marshalling during a clinical diagnostic process, thus improving the decision-making process. Implementation of a digital clinical guideline for the prevention of mother-to-child transmission of hepatitis B as a computerized workflow, thereby separating business logic from medical knowledge and decision-making. We used the Business Process Model and Notation language system Activiti for business logic and workflow modeling. Medical decision-making was performed by an Arden-Syntax-based medical rule engine, which is part of the ARDENSUITE software. We succeeded in creating an electronic clinical workflow for the prevention of mother-to-child transmission of hepatitis B, where institution-specific medical decision-making processes could be adapted without modifying the workflow business logic. Separation of business logic and medical decision-making results in more easily reusable electronic clinical workflows.

Test and evaluation of the HIDEC engine uptrim algorithm. [Highly Integrated Digital Electronic Control for aircraft

NASA Technical Reports Server (NTRS)

Ray, R. J.; Myers, L. P.

1986-01-01

The highly integrated digital electronic control (HIDEC) program will demonstrate and evaluate the improvements in performance and mission effectiveness that result from integrated engine-airframe control systems. Performance improvements will result from an adaptive engine stall margin mode, a highly integrated mode that uses the airplane flight conditions and the resulting inlet distortion to continuously compute engine stall margin. When there is excessive stall margin, the engine is uptrimmed for more thrust by increasing engine pressure ratio (EPR). The EPR uptrim logic has been evaluated and implemente into computer simulations. Thrust improvements over 10 percent are predicted for subsonic flight conditions. The EPR uptrim was successfully demonstrated during engine ground tests. Test results verify model predictions at the conditions tested.

A molecular-sized optical logic circuit for digital modulation of a fluorescence signal

NASA Astrophysics Data System (ADS)

Nishimura, Takahiro; Tsuchida, Karin; Ogura, Yusuke; Tanida, Jun

2018-03-01

Fluorescence measurement allows simultaneous detection of multiple molecular species by using spectrally distinct fluorescence probes. However, due to the broad spectra of fluorescence emission, the multiplicity of fluorescence measurement is generally limited. To overcome this limitation, we propose a method to digitally modulate fluorescence output signals with a molecular-sized optical logic circuit by using optical control of fluorescence resonance energy transfer (FRET). The circuit receives a set of optical inputs represented with different light wavelengths, and then it switches high and low fluorescence intensity from a reporting molecule according to the result of the logic operation. By using combinational optical inputs in readout of fluorescence signals, the number of biomolecular species that can be identified is increased. To implement the FRET-based circuits, we designed two types of basic elements, YES and NOT switches. An YES switch produces a high-level output intensity when receiving a designated light wavelength input and a low-level intensity without the light irradiation. A NOT switch operates inversely to the YES switch. In experiments, we investigated the operation of the YES and NOT switches that receive a 532-nm light input and modulate the fluorescence intensity of Alexa Fluor 488. The experimental result demonstrates that the switches can modulate fluorescence signals according to the optical input.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

NASA Astrophysics Data System (ADS)

Wei, Liu; Wei, Li; Peng, Ren; Qinglong, Lin; Shengdong, Zhang; Yangyuan, Wang

2009-09-01

A time-domain digitally controlled oscillator (DCO) is proposed. The DCO is composed of a free-running ring oscillator (FRO) and a two lap-selectors integrated flying-adder (FA). With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13 μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

System for adjusting frequency of electrical output pulses derived from an oscillator

DOEpatents

Bartholomew, David B.

2006-11-14

A system for setting and adjusting a frequency of electrical output pulses derived from an oscillator in a network is disclosed. The system comprises an accumulator module configured to receive pulses from an oscillator and to output an accumulated value. An adjustor module is configured to store an adjustor value used to correct local oscillator drift. A digital adder adds values from the accumulator module to values stored in the adjustor module and outputs their sums to the accumulator module, where they are stored. The digital adder also outputs an electrical pulse to a logic module. The logic module is in electrical communication with the adjustor module and the network. The logic module may change the value stored in the adjustor module to compensate for local oscillator drift or change the frequency of output pulses. The logic module may also keep time and calculate drift.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Logical design of a decision support system to forecast technology, prices and costs for the national communications system

NASA Astrophysics Data System (ADS)

Williams, K. A.; Partridge, E. C., III

1984-09-01

Originally envisioned as a means to integrate the many systems found throughout the government, the general mission of the NCS continues to be to ensure the survivability of communications during and subsequent to any national emergency. In order to accomplish this mission the NCS is an arrangement of heterogeneous telecommunications systems which are provided by their sponsor Federal agencies. The physical components of Federal telecommunications systems and networks include telephone and digital data switching facilities and primary common user communications centers; Special purpose local delivery message switching and exchange facilities; Government owned or leased radio systems; Technical control facilities which are under exclusive control of a government agency. This thesis describes the logical design of a proposed decision support system for use by the National Communications System in forecasting technology, prices, and costs. It is general in nature and only includes those forecasting models which are suitable for computer implementation. Because it is a logical design it can be coded and applied in many different hardware and/or software configurations.

Fuzzy Logic Module of Convolutional Neural Network for Handwritten Digits Recognition

NASA Astrophysics Data System (ADS)

Popko, E. A.; Weinstein, I. A.

2016-08-01

Optical character recognition is one of the important issues in the field of pattern recognition. This paper presents a method for recognizing handwritten digits based on the modeling of convolutional neural network. The integrated fuzzy logic module based on a structural approach was developed. Used system architecture adjusted the output of the neural network to improve quality of symbol identification. It was shown that proposed algorithm was flexible and high recognition rate of 99.23% was achieved.

Lyceum: A Multi-Protocol Digital Library Gateway

NASA Technical Reports Server (NTRS)

Maa, Ming-Hokng; Nelson, Michael L.; Esler, Sandra L.

1997-01-01

Lyceum is a prototype scalable query gateway that provides a logically central interface to multi-protocol and physically distributed, digital libraries of scientific and technical information. Lyceum processes queries to multiple syntactically distinct search engines used by various distributed information servers from a single logically central interface without modification of the remote search engines. A working prototype (http://www.larc.nasa.gov/lyceum/) demonstrates the capabilities, potentials, and advantages of this type of meta-search engine by providing access to over 50 servers covering over 20 disciplines.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

The Effects of Web-Based and Face-to-Face Discussion on Computer Engineering Majors' Performance on the Karnaugh Map

ERIC Educational Resources Information Center

Hung, Yen-Chu

2011-01-01

This study investigates the different effects of web-based and face-to-face discussion on computer engineering majors' performance using the Karnaugh map in digital logic design. Pretest and posttest scores for two treatment groups (web-based discussion and face-to-face discussion) and a control group were compared and subjected to covariance…

Closed Loop Real-Time Evaluation of Missile Guidance and Control Components: Simulator Hardware/Software Characteristics and Use

DTIC Science & Technology

1974-08-01

Node Control Logic 2-27 2.16 Pitch Channel Frequence Response 2-36 2.17 Yaw Channel Frequency Response 2-37 K 4 2.18 Analog Computer Mechanlzation of...8217S 0 121 £l1:c IL-I. TABLE I Elements of the Slgma 5 Digital Computer System Xerox Model- Performance MIOP Channel Description Number Characteristics...transfer control signals to or from the CPU. The MIOP can handle up to 32 I/0 channels each operating simultaneously, provided the overall data

Reconfigurable modular computer networks for spacecraft on-board processing

NASA Technical Reports Server (NTRS)

Rennels, D. A.

1978-01-01

The core electronics subsystems on unmanned spacecraft, which have been sent over the last 20 years to investigate the moon, Mars, Venus, and Mercury, have progressed through an evolution from simple fixed controllers and analog computers in the 1960's to general-purpose digital computers in current designs. This evolution is now moving in the direction of distributed computer networks. Current Voyager spacecraft already use three on-board computers. One is used to store commands and provide overall spacecraft management. Another is used for instrument control and telemetry collection, and the third computer is used for attitude control and scientific instrument pointing. An examination of the control logic in the instruments shows that, for many, it is cost-effective to replace the sequencing logic with a microcomputer. The Unified Data System architecture considered consists of a set of standard microcomputers connected by several redundant buses. A typical self-checking computer module will contain 23 RAMs, two microprocessors, one memory interface, three bus interfaces, and one core building block.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

Digital Ratiometer

NASA Technical Reports Server (NTRS)

Beer, R.

1985-01-01

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

On the impact of `smart tyres' on existing ABS/EBD control systems

NASA Astrophysics Data System (ADS)

Cheli, Federico; Leo, Elisbetta; Melzi, Stefano; Sabbioni, Edoardo

2010-12-01

The paper focuses on the possibility of enhancing the performances of the ABS (Antilock Braking System)/EBD (electronic braking distribution) control system by using the additional information provided by 'smart tyres' (i.e. tyres with embedded sensors and digital-computing capability). In particular, on the basis of previous works [Braghin et al., Future car active controls through the measurement of contact forces and patch features, Veh. Syst. Dyn. 44 (2006), pp. 3-13], the authors assumed that these components should be able to provide estimates for the normal loads acting on the four wheels and for the tyre-road friction coefficient. The benefits produced by the introduction of these additional channels into the existing ABS/EBD control logic were evaluated through simulations carried out with a validated 14 degrees of freedom (dofs) vehicle + ABS/EBD control logic numerical model. The performance of the ABS control system was evaluated through a series of braking manoeuvres on straight track focusing the attention on μ -jump conditions, while the performance of the EBD control system was assessed by means of braking manoeuvres carried out considering several weight distributions.

Hydraulic logic gates: building a digital water computer

NASA Astrophysics Data System (ADS)

Taberlet, Nicolas; Marsal, Quentin; Ferrand, Jérémy; Plihon, Nicolas

2018-03-01

In this article, we propose an easy-to-build hydraulic machine which serves as a digital binary computer. We first explain how an elementary adder can be built from test tubes and pipes (a cup filled with water representing a 1, and empty cup a 0). Using a siphon and a slow drain, the proposed setup combines AND and XOR logical gates in a single device which can add two binary digits. We then show how these elementary units can be combined to construct a full 4-bit adder. The sequencing of the computation is discussed and a water clock can be incorporated so that the machine can run without any exterior intervention.

Developing measures of fatigue using an alcohol comparison to validate the effects of fatigue on performance.

PubMed

Williamson, A M; Feyer, A M; Mattick, R P; Friswell, R; Finlay-Brown, S

2001-05-01

The effects of 28 h of sleep deprivation were compared with varying doses of alcohol up to 0.1% blood alcohol concentration (BAC) in the same subjects. The study was conducted in the laboratory. Twenty long-haul truck drivers and 19 people not employed as professional drivers acted as subjects. Tests were selected that were likely to be affected by fatigue, including simple reaction time, unstable tracking, dual task, Mackworth clock vigilance test, symbol digit coding, visual search, sequential spatial memory and logical reasoning. While performance effects were seen due to alcohol for all tests, sleep deprivation affected performance on most tests, but had no effect on performance on the visual search and logical reasoning tests. Some tests showed evidence of a circadian rhythm effect on performance, in particular, simple reaction time, dual task, Mackworth clock vigilance, and symbol digit coding, but only for response speed and not response accuracy. Drivers were slower but more accurate than controls on the symbol digit test, suggesting that they took a more conservative approach to performance of this test. This study demonstrated which tests are most sensitive to sleep deprivation and fatigue. The study therefore has established a set of tests that can be used in evaluations of fatigue and fatigue countermeasures.

High-sensitivity assay for Hg (II) and Ag (I) ion detection: A new class of droplet digital PCR logic gates for an intelligent DNA calculator.

PubMed

Cheng, Nan; Zhu, Pengyu; Xu, Yuancong; Huang, Kunlun; Luo, Yunbo; Yang, Zhansen; Xu, Wentao

2016-10-15

The first example of droplet digital PCR logic gates ("YES", "OR" and "AND") for Hg (II) and Ag (I) ion detection has been constructed based on two amplification events triggered by a metal-ion-mediated base mispairing (T-Hg(II)-T and C-Ag(I)-C). In this work, Hg(II) and Ag(I) were used as the input, and the "true" hierarchical colors or "false" green were the output. Through accurate molecular recognition and high sensitivity amplification, positive droplets were generated by droplet digital PCR and viewed as the basis of hierarchical digital signals. Based on this principle, YES gate for Hg(II) (or Ag(I)) detection, OR gate for Hg(II) or Ag(I) detection and AND gate for Hg(II) and Ag(I) detection were developed, and their sensitively and selectivity were reported. The results indicate that the ddPCR logic system developed based on the different indicators for Hg(II) and Ag(I) ions provides a useful strategy for developing advanced detection methods, which are promising for multiplex metal ion analysis and intelligent DNA calculator design applications. Copyright © 2016 Elsevier B.V. All rights reserved.

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Data Grid Management Systems

NASA Technical Reports Server (NTRS)

Moore, Reagan W.; Jagatheesan, Arun; Rajasekar, Arcot; Wan, Michael; Schroeder, Wayne

2004-01-01

The "Grid" is an emerging infrastructure for coordinating access across autonomous organizations to distributed, heterogeneous computation and data resources. Data grids are being built around the world as the next generation data handling systems for sharing, publishing, and preserving data residing on storage systems located in multiple administrative domains. A data grid provides logical namespaces for users, digital entities and storage resources to create persistent identifiers for controlling access, enabling discovery, and managing wide area latencies. This paper introduces data grids and describes data grid use cases. The relevance of data grids to digital libraries and persistent archives is demonstrated, and research issues in data grids and grid dataflow management systems are discussed.

Evolutions in food marketing, quantifying the impact, and policy implications.

PubMed

Cairns, Georgina

2013-03-01

A case study on interactive digital marketing examined the adequacy of extant policy controls and their underpinning paradigms to constrain the effects of this rapidly emerging practice. Findings were interactive digital marketing is expanding the strategies available to promote products, brands and consumer behaviours. It facilitates relational marketing; the collection of personal data for marketing; integration of the marketing mix, and provides a platform for consumers to engage in the co-creation of marketing communications. The paradigmatic logic of current policies to constrain youth-oriented food marketing does not address the interactive nature of digital marketing. The evidence base on the effects of HFSS marketing and policy interventions is based on conceptualizations of marketing as a force promoting transactions rather than interactions. Digital technologies are generating rich consumer data. Interactive digital technologies increase the complexity of the task of quantifying the impact of marketing. The rapidity of its uptake also increases urgency of need to identify appropriate effects measures. Independent analysis of commercial consumer data (appropriately transformed to protect commercial confidentiality and personal privacy) would provide evidence sources for policy on the impacts of commercial food and beverage marketing and policy controls. Copyright © 2012 Elsevier Ltd. All rights reserved.

Adaptive sampler

DOEpatents

Watson, Bobby L.; Aeby, Ian

1982-01-01

An adaptive data compression device for compressing data having variable frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

Information storage and retrieval in a single levitating colloidal particle

NASA Astrophysics Data System (ADS)

Myers, Christopher J.; Celebrano, Michele; Krishnan, Madhavi

2015-10-01

The binary switch is a basic component of digital information. From phase-change alloys to nanomechanical beams, molecules and atoms, new strategies for controlled bistability hold great interest for emerging technologies. We present a generic methodology for precise and parallel spatiotemporal control of nanometre-scale matter in a fluid, and demonstrate the ability to attain digital functionalities such as switching, gating and data storage in a single colloid, with further implications for signal amplification and logic operations. This fluid-phase bit can be arrayed at high densities, manipulated by either electrical or optical fields, supports low-energy, high-speed operation and marks a first step toward ‘colloidal information’. The principle generalizes to any system where spatial perturbation of a particle elicits a differential response amenable to readout.

Information storage and retrieval in a single levitating colloidal particle.

PubMed

Myers, Christopher J; Celebrano, Michele; Krishnan, Madhavi

2015-10-01

The binary switch is a basic component of digital information. From phase-change alloys to nanomechanical beams, molecules and atoms, new strategies for controlled bistability hold great interest for emerging technologies. We present a generic methodology for precise and parallel spatiotemporal control of nanometre-scale matter in a fluid, and demonstrate the ability to attain digital functionalities such as switching, gating and data storage in a single colloid, with further implications for signal amplification and logic operations. This fluid-phase bit can be arrayed at high densities, manipulated by either electrical or optical fields, supports low-energy, high-speed operation and marks a first step toward 'colloidal information'. The principle generalizes to any system where spatial perturbation of a particle elicits a differential response amenable to readout.

Qubits and quantum Hamiltonian computing performances for operating a digital Boolean 1/2-adder

NASA Astrophysics Data System (ADS)

Dridi, Ghassen; Faizy Namarvar, Omid; Joachim, Christian

2018-04-01

Quantum Boolean (1 + 1) digits 1/2-adders are designed with 3 qubits for the quantum computing (Qubits) and 4 quantum states for the quantum Hamiltonian computing (QHC) approaches. Detailed analytical solutions are provided to analyse the time operation of those different 1/2-adder gates. QHC is more robust to noise than Qubits and requires about the same amount of energy for running its 1/2-adder logical operations. QHC is faster in time than Qubits but its logical output measurement takes longer.

Neuropsychological correlates of sustained attention in schizophrenia.

PubMed

Chen, E Y; Lam, L C; Chen, R Y; Nguyen, D G; Chan, C K; Wilkins, A J

1997-04-11

We employed a simple and relatively undemanding task of monotone counting for the assessment of sustained attention in schizophrenic patients. The monotone counting task has been validated neuropsychologically and is particularly sensitive to right prefrontal lesions. We compared the performance of schizophrenic patients with age- and education-matched controls. We then explored the extent to which a range of commonly employed neuropsychological tasks in schizophrenia research are related to attentional impairment as measured in this way. Monotone counting performance was found to be correlated with digit span (WAIS-R-HK), information (WAIS-R-HK), comprehension (WAIS-R-HK), logical memory (immediate recall) (Weschler Memory Scale, WMS), and visual reproduction (WMS). Multiple regression analysis also identified visual reproduction, digit span and comprehension as significant predictors of attention performance. In contrast, logical memory (delay recall) (WMS), similarity (WAIS-R-HK), semantic fluency, and Wisconsin Card Sorting Test (perseverative errors) were not correlated with attention. In addition, no significant correlation between sustained attention and symptoms was found. These findings are discussed in the context of a weakly modular cognitive system where attentional impairment may contribute selectively to a range of other cognitive deficits.

WTEC panel report on European nuclear instrumentation and controls

NASA Technical Reports Server (NTRS)

White, James D.; Lanning, David D.; Beltracchi, Leo; Best, Fred R.; Easter, James R.; Oakes, Lester C.; Sudduth, A. L.

1991-01-01

Control and instrumentation systems might be called the 'brain' and 'senses' of a nuclear power plant. As such they become the key elements in the integrated operation of these plants. Recent developments in digital equipment have allowed a dramatic change in the design of these instrument and control (I&C) systems. New designs are evolving with cathode ray tube (CRT)-based control rooms, more automation, and better logical information for the human operators. As these new advanced systems are developed, various decisions must be made about the degree of automation and the human-to-machine interface. Different stages of the development of control automation and of advanced digital systems can be found in various countries. The purpose of this technology assessment is to make a comparative evaluation of the control and instrumentation systems that are being used for commercial nuclear power plants in Europe and the United States. This study is limited to pressurized water reactors (PWR's). Part of the evaluation includes comparisons with a previous similar study assessing Japanese technology.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Programmable logic controller optical fibre sensor interface module

NASA Astrophysics Data System (ADS)

Allwood, Gary; Wild, Graham; Hinckley, Steven

2011-12-01

Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Airstart performance of a digital electronic engine control system in an F-15 airplane

NASA Technical Reports Server (NTRS)

Licata, S. J.; Burcham, F. W., Jr.

1983-01-01

The airstart performance of the F100 engine equipped with a digital electronic engine control (DEEC) system was evaluated in an F-15 airplane. The DEEC system incorporates closed-loop airstart logic for improved capability. Spooldown and jet fuel starter-assisted airstarts were made over a range of airspeeds and altitudes. All jet fuel starter-assisted airstarts were successful, with airstart time varying from 35 to 60 sec. All spooldown airstarts at airspeeds of 200 knots and higher were successful; airstart times ranged from 45 sec at 250 knots to 135 sec at 200 knots. The effects of altitude on airstart success and time were small. The flight results agreed closely with previous altitude facility test results. The DEEC system provided successful airstarts at airspeeds at least 50 knots lower than the standard F100 engine control system.

Picoliter DNA Sequencing Chemistry on an Electrowetting-based Digital Microfluidic Platform

PubMed Central

Ferguson Welch, Erin R.; Lin, Yan-You; Madison, Andrew; Fair, R.B.

2011-01-01

The results of investigations into performing DNA sequencing chemistry on a picoliter-scale electrowetting digital microfluidic platform are reported. Pyrosequencing utilizes pyrophosphate produced during nucleotide base addition to initiate a process ending with detection through a chemiluminescence reaction using firefly luciferase. The intensity of light produced during the reaction can be quantified to determine the number of bases added to the DNA strand. The logic-based control and discrete fluid droplets of a digital microfluidic device lend themselves well to the pyrosequencing process. Bead-bound DNA is magnetically held in a single location, and wash or reagent droplets added or split from it to circumvent product dilution. Here we discuss the dispensing, control, and magnetic manipulation of the paramagnetic beads used to hold target DNA. We also demonstrate and characterize the picoliter-scale reaction of luciferase with adenosine triphosphate to represent the detection steps of pyrosequencing and all necessary alterations for working on this scale. PMID:21298802

Modified-Signed-Digit Optical Computing Using Fan-Out

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Zhou, Shaomin; Yeh, Pochi

1996-01-01

Experimental optical computing system containing optical fan-out elements implements modified signed-digit (MSD) arithmetic and logic. In comparison with previous optical implementations of MSD arithmetic, this one characterized by larger throughput, greater flexibility, and simpler optics.

A Multi-Discipline, Multi-Genre Digital Library for Research and Education

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.

2004-01-01

We describe NCSTRL+, a unified, canonical digital library for educational and scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 100 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing "buckets". We have extended the Dienst protocol, the protocol underlying NCSTRL, to provide the ability to "cluster" independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The concept of "buckets" provides a mechanism for publishing and managing logically linked entities with multiple data formats. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information.

Comparing Online to Face-To-Face Delivery of Undergraduate Digital Circuits Content

ERIC Educational Resources Information Center

LaMeres, Brock J.; Plumb, Carolyn

2014-01-01

This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of…

Digital microfluidics: Droplet based logic gates

NASA Astrophysics Data System (ADS)

Cheow, Lih Feng; Yobas, Levent; Kwong, Dim-Lee

2007-01-01

The authors present microfluidic logic gates based on two-phase flows at low Reynold's number. The presence and the absence of a dispersed phase liquid (slug) in a continuous phase liquid represent 1 and 0, respectively. The working principle of these devices is based on the change in hydrodynamic resistance for a channel containing droplets. Logical operations including AND, OR, and NOT are demonstrated, and may pave the way for microfludic system automation and computation.

Biomolecular logic systems: applications to biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Katz, Evgeny

2014-05-01

The paper presents an overview of recent advances in biosensors and bioactuators based on the biocomputing concept. Novel biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce output in the form of YES/NO response. Compared to traditional single-analyte sensing devices, biocomputing approach enables a high-fidelity multi-analyte biosensing, particularly beneficial for biomedical applications. Multi-signal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert to medical emergencies, along with an immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly exemplified for liver injury. Wide-ranging applications of multi-analyte digital biosensors in medicine, environmental monitoring and homeland security are anticipated. "Smart" bioactuators, for example for signal-triggered drug release, were designed by interfacing switchable electrodes and biocomputing systems. Integration of novel biosensing and bioactuating systems with the biomolecular information processing systems keeps promise for further scientific advances and numerous practical applications.

Role of biomolecular logic systems in biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Mailloux, Shay; Katz, Evgeny

2014-09-01

An overview of recent advances in biosensors and bioactuators based on biocomputing systems is presented. Biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce an output in the form of a YES/NO response. Compared to traditional single-analyte sensing devices, the biocomputing approach enables high-fidelity multianalyte biosensing, which is particularly beneficial for biomedical applications. Multisignal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert medical personnel of medical emergencies together with immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly as exemplified for liver injury. Wide-ranging applications of multianalyte digital biosensors in medicine, environmental monitoring, and homeland security are anticipated. "Smart" bioactuators, for signal-triggered drug release, for example, were designed by interfacing switchable electrodes with biocomputing systems. Integration of biosensing and bioactuating systems with biomolecular information processing systems advances the potential for further scientific innovations and various practical applications.

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Diamond turning machine controller implementation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Garrard, K.P.; Taylor, L.W.; Knight, B.F.

The standard controller for a Pnuemo ASG 2500 Diamond Turning Machine, an Allen Bradley 8200, has been replaced with a custom high-performance design. This controller consists of four major components. Axis position feedback information is provided by a Zygo Axiom 2/20 laser interferometer with 0.1 micro-inch resolution. Hardware interface logic couples the computers digital and analog I/O channels to the diamond turning machine`s analog motor controllers, the laser interferometer, and other machine status and control information. It also provides front panel switches for operator override of the computer controller and implement the emergency stop sequence. The remaining two components, themore » control computer hardware and software, are discussed in detail below.« less

Adaptive sampler

DOEpatents

Watson, B.L.; Aeby, I.

1980-08-26

An adaptive data compression device for compressing data is described. The device has a frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard; Day, John H. (Technical Monitor)

2001-01-01

This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

ERIC Educational Resources Information Center

Todorovich, E.; Marone, J. A.; Vazquez, M.

2012-01-01

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

Motivation for DOC III: 64-bit digital optical computer

NASA Astrophysics Data System (ADS)

Guilfoyle, Peter S.

1991-09-01

OptiComp has focused on a digital optical logic family in order to capitalize on the inherent benefits of optical computing, which include (1) high FAN-IN and FAN-OUT, (2) low power consumption, (3) high noise margin, (4) high algorithmic efficiency using 'smart' interconnects, and (5) free-space leverage of gate interconnect bandwidth product. Other well-known secondary advantages of optical logic include zero capacitive loading of signals at a detector, zero cross-talk between signals, zero signal dispersion, and minimal clock skew (a few picoseconds or less in an imaging system). The primary focus of this paper is to demonstrate how each of the five advantages can be used to leverage other logic family performance such as GaAs; the secondary attributes are discussed only in the context of introducing the DOC III architecture.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Design of a modular digital computer system, CDRL no. D001, final design plan

NASA Technical Reports Server (NTRS)

Easton, R. A.

1975-01-01

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Digital logic circuit based on two component molecular systems of BSA and salen

NASA Astrophysics Data System (ADS)

Hai-Bin, Lin; Feng, Chen; Hong-Xu, Guo

2018-02-01

A new fluorescent molecular probe 1 was designed and constructed by combining bovine serum albumin (BSA) and N,N‧-bis(salicylidene)ethylenediamine (salen). Stimulated by Zn2 +, tris, or EDTAH2Na2, the distance between BSA and salen was regulated, which was accompanied by an obvious change in the fluorescence intensity at 350 or 445 nm based on Förster resonance energy transfer. Moreover, based on the encoding binary digits in these inputs and outputs applying positive logic conventions, a monomolecular circuit integrating one OR, three NOT, and three YES gates, was successfully achieved.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors.

PubMed

Tremblay, Noah J; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E

2011-11-22

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards 'intelligent sensors' that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations.

Digital Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors

PubMed Central

Tremblay, Noah J.; Jung, Byung Jun; Breysse, Patrick; Katz, Howard E.

2013-01-01

Chemiresistors and sensitive OFETs have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Here we report higher order logic circuits utilizing OFETs sensitive to amine vapors. The circuits depend on the synergistic responses of paired p- and n-channel organic semiconductors, including an unprecedented analyte-induced current increase by the n-channel semiconductor. This represents the first step towards ‘intelligent sensors’ that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations. PMID:23754969

A low complexity, low spur digital IF conversion circuit for high-fidelity GNSS signal playback

NASA Astrophysics Data System (ADS)

Su, Fei; Ying, Rendong

2016-01-01

A low complexity high efficiency and low spur digital intermediate frequency (IF) conversion circuit is discussed in the paper. This circuit is key element in high-fidelity GNSS signal playback instrument. We analyze the spur performance of a finite state machine (FSM) based numerically controlled oscillators (NCO), by optimization of the control algorithm, a FSM based NCO with 3 quantization stage can achieves 65dB SFDR in the range of the seventh harmonic. Compare with traditional lookup table based NCO design with the same Spurious Free Dynamic Range (SFDR) performance, the logic resource require to implemented the NCO is reduced to 1/3. The proposed design method can be extended to the IF conversion system with good SFDR in the range of higher harmonic components by increasing the quantization stage.

Development Status of the NSTAR Ion Propulsion System Power Processor

NASA Technical Reports Server (NTRS)

Hamley, John A.; Pinero, Luis R.; Rawlin, Vincent K.; Miller, John R.; Cartier, Kevin C.; Bowers, Glen E.

1995-01-01

A 0.5-2.3 kW xenon ion propulsion system is presently being developed under the NASA Solar Electric Propulsion Technology Application Readiness (NSTAR) program. This propulsion system includes a 30 cm diameter xenon ion thruster, a Digital Control Interface Unit, a xenon feed system, and a power processing unit (PPU). The PPU consists of the power supply assemblies which operate the thruster neutralizer, main discharge chamber, and ion optics. Also included are recycle logic and a digital microcontroller. The neutralizer and discharge power supplies employ a dual use configuration which combines the functions of two power supplies into one, significantly simplifying the PPU. Further simplification was realized by implementing a single thruster control loop which regulates the beam current via the discharge current. Continuous throttling is possible over a 0.5-2.3 kW output power range. All three power supplies have been fabricated and tested with resistive loads, and have been combined into a single breadboard unit with the recycle logic and microcontroller. All line and load regulation test results show the power supplies to be within the NSTAR flight PPU specified power output of 1.98 kW. The overall efficiency of the PPU, calculated as the combined efficiencies of the power supplies and controller, at 2.3 kW delivered to resistive loads was 0.90. The component was 6.16 kg. Integration testing of the neutralizer and discharge power supplies with a functional model thruster revealed no issues with discharge ignition or steady state operation.

Controls in new construction reactors-factory testing of the non-safety portion of the Lungmen nuclear power plant distributed control system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Y. S.; Dick, J. W.; Tetirick, C. W.

2006-07-01

The construction permit for Taipower's Lungmen Nuclear Units 1 and 2, two ABWR plants, was issued on March 17, 1999[1], The construction of these units is progressing actively at site. The digital I and C system supplied by GE, which is designated as the Distributed Control and Information System (DCIS) in this project, is being implemented primarily at one vendor facility. In order to ensure the reliability, safety and availability of the DCIS, it is required to comprehensively test the whole DCIS in factory. This article describes the test requirements and acceptance criteria for functional testing of the Non-Safety Distributedmore » Control and Information system (DCIS) for Taiwan Power's Lungmen Units 1 and 2 GE selected Invensys as the equipment supplier for this Non-Safety portion of DCIS. The DCIS system of the Lungmen Units is a physically distributed control system. Field transmitters are connected to hard I/O terminal inputs on the Invensys I/A system. Once the signal is digitized on FBMs (Field Bus Modules) in Remote Multiplexing Units (RMUs), the signal is passed into an integrated control software environment. Control is based on the concept of compounds and blocks where each compound is a logical collection of blocks that performs a control function. Each point identified by control compound and block can be individually used throughout the DCIS system by referencing its unique name. In the Lungmen Project control logic and HSI (Human System Interface) requirements are divided into individual process systems called MPLs (Master Parts List). Higher-level Plant Computer System (PCS) algorithms access control compounds and blocks in these MPLs to develop functions. The test requirements and acceptance criteria for the DCIS system of the Lungmen Project are divided into three general categories (see 1,2,3 below) of verification, which in turn are divided into several specific tests: 1. DCIS System Physical Checks a) RMU Test - To confirm that the hard I/O database is installed on the DCIS and is physically addressed correctly. Test process is injecting a signal at each DCIS hard I/O terminal boundary and verifying correct receipt on the DCIS. b) DCIS Network Stress Test - Confirms system viability under extreme high load conditions beyond the plant could ever experience. Load conditions include alarm showers on the DCIS system to emulate plant upsets. c) System Hardware Configuration Test - These are typical checks of the DCIS system hardware including fault reporting, redundancy, and normal computer functions. d) Performance Test - Test confirms high level hardware and system capability attributes such as control system time response, 'cold start' reboots, and processor loading e) Electromagnetic compatibility tests - To verify the electromagnetic viability of the system and individual components 2. Implementation of Plant Systems and Systems Integration a) MPL Logic Tests -To confirm control functions implemented to system logic performs as expected, and that parameters are passed correctly between system control schemes. b) Data Link (Gateway) Tests- To verify third party interfaces to the DCIS. c) Plant Computer System (PCS) Logic Tests- Tests to verify that higher-level PCS logic is correctly implemented, performs as expected, and parameters are passed correctly between PCS sub-systems and MPL systems. Included the PCS sub-systems, Safety Parameter Display System, Historian, Alarms, Maintenance monitoring etc. 3. Unique Third Party Interfacing and Integration into the DCIS The set of controls for Automatic Power Regulation, Feedwater, and Recirculation Flow are specific in that these systems are implemented on third party Triple Modular Redundant (TMR) hardware, which was connected to the DCIS and are tested via full simulation. The TMR system is supplied by GE Control Solutions on the Mark Vie platform. (authors)« less

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

Digital signal conditioning for flight test instrumentation

NASA Technical Reports Server (NTRS)

Bever, Glenn A.

1991-01-01

An introduction to digital measurement processes on aircraft is provided. Flight test instrumentation systems are rapidly evolving from analog-intensive to digital intensive systems, including the use of onboard digital computers. The topics include measurements that are digital in origin, as well as sampling, encoding, transmitting, and storing data. Particular emphasis is placed on modern avionic data bus architectures and what to be aware of when extracting data from them. Examples of data extraction techniques are given. Tradeoffs between digital logic families, trends in digital development, and design testing techniques are discussed. An introduction to digital filtering is also covered.

Turbulence simulation mechanization for Space Shuttle Orbiter dynamics and control studies

NASA Technical Reports Server (NTRS)

Tatom, F. B.; King, R. L.

1977-01-01

The current version of the NASA turbulent simulation model in the form of a digital computer program, TBMOD, is described. The logic of the program is discussed and all inputs and outputs are defined. An alternate method of shear simulation suitable for incorporation into the model is presented. The simulation is based on a von Karman spectrum and the assumption of isotropy. The resulting spectral density functions for the shear model are included.

A proposed magnetic digital temperature transducer, volume 1

NASA Technical Reports Server (NTRS)

Collier, T. E.; Tchernev, D. I.; Hartwig, W. H.

1972-01-01

A study has been made of the feasibility of using the discontinuous permeability versus temperature characteristics of some magnetic materials for a digital temperature transducer and a thermally controlled ON-OFF switch. Simple logic converts the number of output pulse to a digital word recognizable by the system. Efforts have been concentrated on materials with Curie temperatures between 0 and 100 C. One compound has the composition Mn(5-x)Fe(x)Ge3 where the amount of iron determines the transition temperature. The other compound is Ni-Zn ferrite and has the compositon Ni(1-x)Zn(x)Fe(1.95)O4 where the nickel: zinc ratio determines the transition temperature. A detailed report of materials prepared is presented. Toroidal inductors of the material have been constructed and the change in inductance with temperature measured. In view of these initial measurements, it is felt that a transducer utilizing the permeability versus temperature characteristics of these materials has promise as a reliable and sensitive solid state digital temperature transducer.

Digital PCM bit synchronizer and detector

NASA Astrophysics Data System (ADS)

Moghazy, A. E.; Maral, G.; Blanchard, A.

1980-08-01

A theoretical analysis of a digital self-bit synchronizer and detector is presented and supported by the implementation of an experimental model that utilizes standard TTL logic circuits. This synchronizer is based on the generation of spectral line components by nonlinear filtering of the received bit stream, and extracting the line by a digital phase-locked loop (DPLL). The extracted reference signal instructs a digital matched filter (DMF) data detector. This realization features a short acquisition time and an all-digital structure.

Implementation of a new fuzzy vector control of induction motor.

PubMed

Rafa, Souad; Larabi, Abdelkader; Barazane, Linda; Manceur, Malik; Essounbouli, Najib; Hamzaoui, Abdelaziz

2014-05-01

The aim of this paper is to present a new approach to control an induction motor using type-1 fuzzy logic. The induction motor has a nonlinear model, uncertain and strongly coupled. The vector control technique, which is based on the inverse model of the induction motors, solves the coupling problem. Unfortunately, in practice this is not checked because of model uncertainties. Indeed, the presence of the uncertainties led us to use human expertise such as the fuzzy logic techniques. In order to maintain the decoupling and to overcome the problem of the sensitivity to the parametric variations, the field-oriented control is replaced by a new block control. The simulation results show that the both control schemes provide in their basic configuration, comparable performances regarding the decoupling. However, the fuzzy vector control provides the insensitivity to the parametric variations compared to the classical one. The fuzzy vector control scheme is successfully implemented in real-time using a digital signal processor board dSPACE 1104. The efficiency of this technique is verified as well as experimentally at different dynamic operating conditions such as sudden loads change, parameter variations, speed changes, etc. The fuzzy vector control is found to be a best control for application in an induction motor. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

GaAs integrated circuits and heterojunction devices

NASA Astrophysics Data System (ADS)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Biological Signal Processing with a Genetic Toggle Switch

PubMed Central

Hillenbrand, Patrick; Fritz, Georg; Gerland, Ulrich

2013-01-01

Complex gene regulation requires responses that depend not only on the current levels of input signals but also on signals received in the past. In digital electronics, logic circuits with this property are referred to as sequential logic, in contrast to the simpler combinatorial logic without such internal memory. In molecular biology, memory is implemented in various forms such as biochemical modification of proteins or multistable gene circuits, but the design of the regulatory interface, which processes the input signals and the memory content, is often not well understood. Here, we explore design constraints for such regulatory interfaces using coarse-grained nonlinear models and stochastic simulations of detailed biochemical reaction networks. We test different designs for biological analogs of the most versatile memory element in digital electronics, the JK-latch. Our analysis shows that simple protein-protein interactions and protein-DNA binding are sufficient, in principle, to implement genetic circuits with the capabilities of a JK-latch. However, it also exposes fundamental limitations to its reliability, due to the fact that biological signal processing is asynchronous, in contrast to most digital electronics systems that feature a central clock to orchestrate the timing of all operations. We describe a seemingly natural way to improve the reliability by invoking the master-slave concept from digital electronics design. This concept could be useful to interpret the design of natural regulatory circuits, and for the design of synthetic biological systems. PMID:23874595

Development of Boolean calculus and its applications. [digital systems design

NASA Technical Reports Server (NTRS)

Tapia, M. A.

1980-01-01

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

DDL:Digital systems design language

NASA Technical Reports Server (NTRS)

Shival, S. G.

1980-01-01

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

PubMed Central

Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

2017-01-01

Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

The development of a digital logic concept inventory

NASA Astrophysics Data System (ADS)

Herman, Geoffrey Lindsay

Instructors in electrical and computer engineering and in computer science have developed innovative methods to teach digital logic circuits. These methods attempt to increase student learning, satisfaction, and retention. Although there are readily accessible and accepted means for measuring satisfaction and retention, there are no widely accepted means for assessing student learning. Rigorous assessment of learning is elusive because differences in topic coverage, curriculum and course goals, and exam content prevent direct comparison of two teaching methods when using tools such as final exam scores or course grades. Because of these difficulties, computing educators have issued a general call for the adoption of assessment tools to critically evaluate and compare the various teaching methods. Science, Technology, Engineering, and Mathematics (STEM) education researchers commonly measure students' conceptual learning to compare how much different pedagogies improve learning. Conceptual knowledge is often preferred because all engineering courses should teach a fundamental set of concepts even if they emphasize design or analysis to different degrees. Increasing conceptual learning is also important, because students who can organize facts and ideas within a consistent conceptual framework are able to learn new information quickly and can apply what they know in new situations. If instructors can accurately assess their students' conceptual knowledge, they can target instructional interventions to remedy common problems. To properly assess conceptual learning, several researchers have developed concept inventories (CIs) for core subjects in engineering sciences. CIs are multiple-choice assessment tools that evaluate how well a student's conceptual framework matches the accepted conceptual framework of a discipline or common faulty conceptual frameworks. We present how we created and evaluated the digital logic concept inventory (DLCI).We used a Delphi process to identify the important and difficult concepts to include on the DLCI. To discover and describe common student misconceptions, we interviewed students who had completed a digital logic course. Students vocalized their thoughts as they solved digital logic problems. We analyzed the interview data using a qualitative grounded theory approach. We have administered the DLCI at several institutions and have checked the validity, reliability, and bias of the DLCI with classical testing theory procedures. These procedures consisted of follow-up interviews with students, analysis of administration results with statistical procedures, and expert feedback. We discuss these results and present the DLCI's potential for providing a meaningful tool for comparing student learning at different institutions.

Digital circuits for computer applications: A compilation

NASA Technical Reports Server (NTRS)

1972-01-01

The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.

Magnon-based logic in a multi-terminal YIG/Pt nanostructure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ganzhorn, Kathrin, E-mail: kathrin.ganzhorn@wmi.badw.de; Klingler, Stefan; Wimmer, Tobias

2016-07-11

Boolean logic is the foundation of modern digital information processing. Recently, there has been a growing interest in phenomena based on pure spin currents, which allows to move from charge to spin based logic gates. We study a proof-of-principle logic device based on the ferrimagnetic insulator Yttrium Iron Garnet, with Pt strips acting as injectors and detectors for non-equilibrium magnons. We experimentally observe incoherent superposition of magnons generated by different injectors. This allows to implement a fully functional majority gate, enabling multiple logic operations (AND and OR) in one and the same device. Clocking frequencies of the order of severalmore » GHz and straightforward down-scaling make our device promising for applications.« less

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

NASA Astrophysics Data System (ADS)

Ayala, Christopher Lawrence

Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using RSFQ logic and prototype chips have been fabricated. As a joint work with HYPRES, a 20 GHz 8-bit Kogge-Stone ALU consisting of 7,950 JJs total has been fabricated using a 1.5 μm 4.5 kA/cm2 process and fully demonstrated. An 8-bit sparse-tree ALU (8,832 JJs total) and a 16-bit sparse-tree adder (12,785 JJs total) have also been fabricated using a 1.0 μm 10 kA/cm 2 process and demonstrated under collaboration with Yokohama National University and Nagoya University (Japan).

Statechart-based design controllers for FPGA partial reconfiguration

NASA Astrophysics Data System (ADS)

Łabiak, Grzegorz; Wegrzyn, Marek; Rosado Muñoz, Alfredo

2015-09-01

Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in author's proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

Technical advances of interventional fluoroscopy and flat panel image receptor.

PubMed

Lin, Pei-Jan Paul

2008-11-01

In the past decade, various radiation reducing devices and control circuits have been implemented on fluoroscopic imaging equipment. Because of the potential for lengthy fluoroscopic procedures in interventional cardiovascular angiography, these devices and control circuits have been developed for the cardiac catheterization laboratories and interventional angiography suites. Additionally, fluoroscopic systems equipped with image intensifiers have benefited from technological advances in x-ray tube, x-ray generator, and spectral shaping filter technologies. The high heat capacity x-ray tube, the medium frequency inverter generator with high performance switching capability, and the patient dose reduction spectral shaping filter had already been implemented on the image intensified fluoroscopy systems. These three underlying technologies together with the automatic dose rate and image quality (ADRIQ) control logic allow patients undergoing cardiovascular angiography procedures to benefit from "lower patient dose" with "high image quality." While photoconductor (or phosphor plate) x-ray detectors and signal capture thin film transistor (TFT) and charge coupled device (CCD) arrays are analog in nature, the advent of the flat panel image receptor allowed for fluoroscopy procedures to become more streamlined. With the analog-to-digital converter built into the data lines, the flat panel image receptor appears to become a digital device. While the transition from image intensified fluoroscopy systems to flat panel image receptor fluoroscopy systems is part of the on-going "digitization of imaging," the value of a flat panel image receptor may have to be evaluated with respect to patient dose, image quality, and clinical application capabilities. The advantage of flat panel image receptors has yet to be fully explored. For instance, the flat panel image receptor has its disadvantages as compared to the image intensifiers; the cost of the equipment is probably the most obvious. On the other hand, due to its wide dynamic range and linearity, lowering of patient dose beyond current practice could be achieved through the calibration process of the flat panel input dose rate being set to, for example, one half or less of current values. In this article various radiation saving devices and control circuits are briefly described. This includes various types of fluoroscopic systems designed to strive for reduction of patient exposure with the application of spectral shaping filters. The main thrust is to understand the ADRIQ control logic, through equipment testing, as it relates to clinical applications, and to show how this ADRIQ control logic "ties" those three technological advancements together to provide low radiation dose to the patient with high quality fluoroscopic images. Finally, rotational angiography with computed tomography (CT) and three dimensional (3-D) images utilizing flat panel technology will be reviewed as they pertain to diagnostic imaging in cardiovascular disease.

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

ERIC Educational Resources Information Center

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

A Simple and Effective Remedial Learning System with a Fuzzy Expert System

ERIC Educational Resources Information Center

Lin, C.-C.; Guo, K.-H.; Lin, Y.-C.

2016-01-01

This study aims at implementing a simple and effective remedial learning system. Based on fuzzy inference, a remedial learning material selection system is proposed for a digital logic course. Two learning concepts of the course have been used in the proposed system: number systems and combinational logic. We conducted an experiment to validate…

A m-ary linear feedback shift register with binary logic

NASA Technical Reports Server (NTRS)

Perlman, M. (Inventor)

1973-01-01

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers.

Superconducting Qubit with Integrated Single Flux Quantum Controller Part I: Theory and Fabrication

NASA Astrophysics Data System (ADS)

Beck, Matthew; Leonard, Edward, Jr.; Thorbeck, Ted; Zhu, Shaojiang; Howington, Caleb; Nelson, Jj; Plourde, Britton; McDermott, Robert

As the size of quantum processors grow, so do the classical control requirements. The single flux quantum (SFQ) Josephson digital logic family offers an attractive route to proximal classical control of multi-qubit processors. Here we describe coherent control of qubits via trains of SFQ pulses. We discuss the fabrication of an SFQ-based pulse generator and a superconducting transmon qubit on a single chip. Sources of excess microwave loss stemming from the complex multilayer fabrication of the SFQ circuit are discussed. We show how to mitigate this loss through judicious choice of process workflow and appropriate use of sacrificial protection layers. Present address: IBM T.J. Watson Research Center.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Na; Wu, Yu-Ping; Min, Hao

A radio-frequency (RF) source designed for cold atom experiments is presented. The source uses AD9858, a direct digital synthesizer, to generate the sine wave directly, up to 400 MHz, with sub-Hz resolution. An amplitude control circuit consisting of wideband variable gain amplifier and high speed digital to analog converter is integrated into the source, capable of 70 dB off isolation and 4 ns on-off keying. A field programmable gate array is used to implement a versatile frequency and amplitude co-sweep logic. Owing to modular design, the RF sources have been used on many cold atom experiments to generate various complicatedmore » RF sequences, enriching the operation schemes of cold atoms, which cannot be done by standard RF source instruments.« less

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Logic gate scanner focus control in high-volume manufacturing using scatterometry

NASA Astrophysics Data System (ADS)

Dare, Richard J.; Swain, Bryan; Laughery, Michael

2004-05-01

Tool matching and optimal process control are critical requirements for success in semiconductor manufacturing. It is imperative that a tool"s operating conditions are understood and controlled in order to create a process that is repeatable and produces devices within specifications. Likewise, it is important where possible to match multiple systems using some methodology, so that regardless of which tool is used the process remains in control. Agere Systems is currently using Timbre Technologies" Optical Digital Profilometry (ODP) scatterometry for controlling Nikon scanner focus at the most critical lithography layer; logic gate. By adjusting focus settings and verifying the resultant changes in resist profile shape using ODP, it becomes possible to actively control scanner focus to achieve a desired resist profile. Since many critical lithography processes are designed to produce slightly re-entrant resist profiles, this type of focus control is not possible via Critical Dimension Scanning Electron Microscopy (CDSEM) where reentrant profiles cannot be accurately determined. Additionally, the high throughput and non-destructive nature of this measurement technique saves both cycle time and wafer costs compared to cross-section SEM. By implementing an ODP daily process check and after any maintenance on a scanner, Agere successfully enabled focus drift control, i.e. making necessary focus or equipment changes in order to maintain a desired resist profile.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Room temperature operation of electro-optical bistability in the edge-emitting tunneling-collector transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Wang, C. Y.

2017-09-01

Optical bistable devices are fundamental to digital photonics as building blocks of switches, logic gates, and memories in future computer systems. Here, we demonstrate both optical and electrical bistability and capability for switching in a single transistor operated at room temperature. The electro-optical hysteresis is explained by the interaction of electron-hole (e-h) generation and recombination dynamics with the cavity photon modulation in different switching paths. The switch-UP and switch-DOWN threshold voltages are determined by the rate difference of photon generation at the base quantum-well and the photon absorption via intra-cavity photon-assisted tunneling controlled by the collector voltage. Thus, the transistor laser electro-optical bistable switching is programmable with base current and collector voltage, and the basis for high speed optical logic processors.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

The Semiautomated Test System: A Tool for Standardized Performance Testing.

ERIC Educational Resources Information Center

Ramsey, H. Rudy

For performance tests to be truly standardized, they must be administered in a way that will minimize variation due to operator intervention and errors. Through such technological developments as low-cost digital computers and digital logic modules, automatic test administration without restriction of test content has become possible. A…

An Undergraduate Experiment in Alarm System Design.

ERIC Educational Resources Information Center

Martini, R. A.; And Others

1988-01-01

Describes an experiment involving data acquisition by a computer, digital signal transmission from the computer to a digital logic circuit and signal interpretation by this circuit. The system is being used at the Illinois Institute of Technology. Discusses the fundamental concepts involved. Demonstrates the alarm experiment as it is used in…

Coding Skills as a Success Factor for a Society

ERIC Educational Resources Information Center

Tuomi, Pauliina; Multisilta, Jari Antero; Saarikoski, Petri; Suominen, Jaakko

2018-01-01

Digitalization is one of the most promising ways to increase productivity in the public sector and is needed to reform the economy by creating new innovation related jobs. The implementation of digital services requires problem solving, design skills, logical thinking, an understanding of how computers and networks operate, and programming…

Music, Technology, and an Evolving Curriculum.

ERIC Educational Resources Information Center

Moore, Brian

1992-01-01

Mechanical examples of musical technology, like the Steinway piano, are well known and accepted. Use of computers and electronic technology is the next logical step in developing art of music. MIDI (Musical Instrument Digital Interface) is explained, along with digital devices (such as synthesizers, sequencers, music notation software, multimedia,…

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

NASA Astrophysics Data System (ADS)

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

2015-11-01

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

The past, present and future of cyber-physical systems: a focus on models.

PubMed

Lee, Edward A

2015-02-26

This paper is about better engineering of cyber-physical systems (CPSs) through better models. Deterministic models have historically proven extremely useful and arguably form the kingpin of the industrial revolution and the digital and information technology revolutions. Key deterministic models that have proven successful include differential equations, synchronous digital logic and single-threaded imperative programs. Cyber-physical systems, however, combine these models in such a way that determinism is not preserved. Two projects show that deterministic CPS models with faithful physical realizations are possible and practical. The first project is PRET, which shows that the timing precision of synchronous digital logic can be practically made available at the software level of abstraction. The second project is Ptides (programming temporally-integrated distributed embedded systems), which shows that deterministic models for distributed cyber-physical systems have practical faithful realizations. These projects are existence proofs that deterministic CPS models are possible and practical.

NCSTRL+: Adding Multi-Discipline and Multi-Genre Support to the Dienst Protocol Using Clusters and Buckets

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.; Zubair, Mohammad

1998-01-01

We describe NCSTRL+, a unified, canonical digital library for scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 100 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing buckets. We have extended Dienst, the protocol underlying NCSTRL, to provide the ability to cluster independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The bucket construct provides a mechanism for publishing and managing logically linked entities with multiple data forms as a single object. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information.

The Past, Present and Future of Cyber-Physical Systems: A Focus on Models

PubMed Central

Lee, Edward A.

2015-01-01

This paper is about better engineering of cyber-physical systems (CPSs) through better models. Deterministic models have historically proven extremely useful and arguably form the kingpin of the industrial revolution and the digital and information technology revolutions. Key deterministic models that have proven successful include differential equations, synchronous digital logic and single-threaded imperative programs. Cyber-physical systems, however, combine these models in such a way that determinism is not preserved. Two projects show that deterministic CPS models with faithful physical realizations are possible and practical. The first project is PRET, which shows that the timing precision of synchronous digital logic can be practically made available at the software level of abstraction. The second project is Ptides (programming temporally-integrated distributed embedded systems), which shows that deterministic models for distributed cyber-physical systems have practical faithful realizations. These projects are existence proofs that deterministic CPS models are possible and practical. PMID:25730486

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

600 C Logic Gates Using Silicon Carbide JFET's

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Beheim, Glenn M.; Salupo, Carl S.a

2000-01-01

Complex electronics and sensors are increasingly being relied on to enhance the capabilities and efficiency of modernjet aircraft. Some of these electronics and sensors monitor and control vital engine components and aerosurfaces that operate at high temperatures above 300 C. However, since today's silicon-based electronics technology cannot function at such high temperatures, these electronics must reside in environmentally controlled areas. This necessitates either the use of long wire runs between sheltered electronics and hot-area sensors and controls, or the fuel cooling of electronics and sensors located in high-temperature areas. Both of these low-temperature-electronics approaches suffer from serious drawbacks in terms of increased weight, decreased fuel efficiency, and reduction of aircraft reliability. A family of high-temperature electronics and sensors that could function in hot areas would enable substantial aircraft performance gains. Especially since, in the future, some turbine-engine electronics may need to function at temperatures as high as 600 C. This paper reports the fabrication and demonstration of the first semiconductor digital logic gates ever to function at 600 C. Key obstacles blocking the realization of useful 600 C turbine engine integrated sensor and control electronics are outlined.

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Current Controller for Multi-level Front-end Converter and Its Digital Implementation Considerations on Three-level Flying Capacitor Topology

NASA Astrophysics Data System (ADS)

Tekwani, P. N.; Shah, M. T.

2017-10-01

This paper presents behaviour analysis and digital implementation of current error space phasor based hysteresis controller applied to three-phase three-level flying capacitor converter as front-end topology. The controller is self-adaptive in nature, and takes the converter from three-level to two-level mode of operation and vice versa, following various trajectories of sector change with the change in reference dc-link voltage demanded by the load. It keeps current error space phasor within the prescribed hexagonal boundary. During the contingencies, the proposed controller takes the converter in over modulation mode to meet the load demand, and once the need is satisfied, controller brings back the converter in normal operating range. Simulation results are presented to validate behaviour of controller to meet the said contingencies. Unity power factor is assured by proposed controller with low current harmonic distortion satisfying limits prescribed in IEEE 519-2014. Proposed controller is implemented using TMS320LF2407 16-bit fixed-point digital signal processor. Detailed analysis of numerical format to avoid overflow of sensed variables in processor, and per-unit model implementation in software are discussed and hardware results are presented at various stages of signal conditioning to validate the experimental setup. Control logic for the generation of reference currents is implemented in TMS320LF2407A using assembly language and experimental results are also presented for the same.

Application of Nonlinear Systems Inverses to Automatic Flight Control Design: System Concepts and Flight Evaluations

NASA Technical Reports Server (NTRS)

Meyer, G.; Cicolani, L.

1981-01-01

A practical method for the design of automatic flight control systems for aircraft with complex characteristics and operational requirements, such as the powered lift STOL and V/STOL configurations, is presented. The method is effective for a large class of dynamic systems requiring multi-axis control which have highly coupled nonlinearities, redundant controls, and complex multidimensional operational envelopes. It exploits the concept of inverse dynamic systems, and an algorithm for the construction of inverse is given. A hierarchic structure for the total control logic with inverses is presented. The method is illustrated with an application to the Augmentor Wing Jet STOL Research Aircraft equipped with a digital flight control system. Results of flight evaluation of the control concept on this aircraft are presented.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Fundamentals of Digital Logic, 7-1. Military Curriculum Materials for Vocational and Technical Education.

ERIC Educational Resources Information Center

Marine Corps, Washington, DC.

Targeted for grades 10 through adult, these military-developed curriculum materials consist of a student lesson book with text readings and review exercises designed to prepare electronic personnel for further training in digital techniques. Covered in the five lessons are binary arithmetic (number systems, decimal systems, the mathematical form…

Evolving Digital Ecological Networks

PubMed Central

Wagner, Aaron P.; Ofria, Charles

2013-01-01

“It is hard to realize that the living world as we know it is just one among many possibilities” [1]. Evolving digital ecological networks are webs of interacting, self-replicating, and evolving computer programs (i.e., digital organisms) that experience the same major ecological interactions as biological organisms (e.g., competition, predation, parasitism, and mutualism). Despite being computational, these programs evolve quickly in an open-ended way, and starting from only one or two ancestral organisms, the formation of ecological networks can be observed in real-time by tracking interactions between the constantly evolving organism phenotypes. These phenotypes may be defined by combinations of logical computations (hereafter tasks) that digital organisms perform and by expressed behaviors that have evolved. The types and outcomes of interactions between phenotypes are determined by task overlap for logic-defined phenotypes and by responses to encounters in the case of behavioral phenotypes. Biologists use these evolving networks to study active and fundamental topics within evolutionary ecology (e.g., the extent to which the architecture of multispecies networks shape coevolutionary outcomes, and the processes involved). PMID:23533370

Method and apparatus for digitally based high speed x-ray spectrometer for direct coupled use with continuous discharge preamplifiers

DOEpatents

Warburton, W.K.

1998-06-30

A high speed, digitally based, signal processing system is disclosed which accepts directly coupled input data from a detector with a continuous discharge type preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system`s principal elements are an analog signal conditioning section, a combinatorial logic section which implements digital triangular filtering and pileup inspection, and a microprocessor which accepts values captured by the logic section and uses them to compute x-ray energy values. Operating without pole-zero correction, the system achieves high resolution by capturing, in conjunction with each peak value from the digital filter, an associated value of the unfiltered signal, and using this latter signal to correct the former for errors which arise from its local slope terms. This correction greatly reduces both energy resolution degradation and peak centroid shifting in the output spectrum as a function of input count rate. When the noise of this correction is excessive, a modification allows two filtered averages of the signal to be captured and a corrected peak amplitude computed therefrom. 14 figs.

Method and apparatus for digitally based high speed x-ray spectrometer for direct coupled use with continuous discharge preamplifiers

DOEpatents

Warburton, William K.

1998-01-01

A high speed, digitally based, signal processing system which accepts directly coupled input data from a detector with a continuous discharge type preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system's principal elements are an analog signal conditioning section, a combinatorial logic section which implements digital triangular filtering and pileup inspection, and a microprocessor which accepts values captured by the logic section and uses them to compute x-ray energy values. Operating without pole-zero correction, the system achieves high resolution by capturing, in conjunction with each peak value from the digital filter, an associated value of the unfiltered signal, and using this latter signal to correct the former for errors which arise from its local slope terms. This correction greatly reduces both energy resolution degradation and peak centroid shifting in the output spectrum as a function of input count rate. When the noise of this correction is excessive, a modification allows two filtered averages of the signal to be captured and a corrected peak amplitude computed therefrom.

Hypertext and Multimedia for Functional Enhancement of USARIEM Medical Handbooks and Biomedical Simulation Software.

DTIC Science & Technology

1994-12-01

complex Internet addresses. Hypertext and hypermedia documents have logical and physical structure (Shneiderman, 1993). The logical structure delineates...Rubra, Miliaria Profunda , Anhidrotic Heat Exhaustion, Heat Syncope, Heat Edema, Sunburn, and Heat Tetany. The user may return to the main document...military or scientific organizations via digital communications networks such as the Internet . Access clearance would first be obtained from the USARIEM

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Flight evaluation of a hydromechanical backup control for the digital electronic engine control system in an F100 engine

NASA Technical Reports Server (NTRS)

Walsh, K. R.; Burcham, F. W.

1984-01-01

The backup control (BUC) features, the operation of the BUC system, the BUC control logic, and the BUC flight test results are described. The flight test results include: (1) transfers to the BUC at military and maximum power settings; (2) a military power acceleration showing comparisons bvetween flight and simulation for BUC and primary modes; (3) steady-state idle power showing idle compressor speeds at different flight conditions; and (4) idle-to-military power BUC transients showing where cpmpressor stalls occurred for different ramp rates and idle speeds. All the BUC transfers which occur during the DEEC flight program are initiated by the pilot. Automatic transfers to the BUC do not occur.

Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architectures

NASA Technical Reports Server (NTRS)

Choi, Gwan S.; Iyer, Ravishankar K.; Carreno, Victor A.

1990-01-01

A simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

Rubbery computing

NASA Astrophysics Data System (ADS)

Wilson, Katherine E.; Henke, E.-F. Markus; Slipher, Geoffrey A.; Anderson, Iain A.

2017-04-01

Electromechanically coupled dielectric elastomer actuators (DEAs) and dielectric elastomer switches (DESs) may form digital logic circuitry made entirely of soft and flexible materials. The expansion in planar area of a DEA exerts force across a DES, which is a soft electrode with strain-dependent resistivity. When compressed, the DES drops steeply in resistance and changes state from non-conducting to conducting. Logic operators may be achieved with different arrangements of interacting DE actuators and switches. We demonstrate combinatorial logic elements, including the fundamental Boolean logic gates, as well as sequential logic elements, including latches and flip-flops. With both data storage and signal processing abilities, the necessary calculating components of a soft computer are available. A noteworthy advantage of a soft computer with mechanosensitive DESs is the potential for responding to environmental strains while locally processing information and generating a reaction, like a muscle reflex.

Reconfigurable firmware-defined radios synthesized from standard digital logic cells

NASA Astrophysics Data System (ADS)

Faisal, Muhammad; Park, Youngmin; Wentzloff, David D.

2011-06-01

This paper presents recent work on reconfigurable all-digital radio architectures. We leverage the flexibility and scalability of synthesized digital cells to construct reconfigurable radio architectures that consume significantly less power than a software defined radio implementing similar architectures. We present two prototypes of such architectures that can receive and demodulate FM and FRS band signals. Moreover, a radio architecture based on a reconfigurable alldigital phase-locked loop for coherent demodulation is presented.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

Modernization of B-2 Data, Video, and Control Systems Infrastructure

NASA Technical Reports Server (NTRS)

Cmar, Mark D.; Maloney, Christian T.; Butala, Vishal D.

2012-01-01

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) Plum Brook Station (PBS) Spacecraft Propulsion Research Facility, commonly referred to as B-2, is NASA s third largest thermal-vacuum facility with propellant systems capability. B-2 has completed a modernization effort of its facility legacy data, video and control systems infrastructure to accommodate modern integrated testing and Information Technology (IT) Security requirements. Integrated systems tests have been conducted to demonstrate the new data, video and control systems functionality and capability. Discrete analog signal conditioners have been replaced by new programmable, signal processing hardware that is integrated with the data system. This integration supports automated calibration and verification of the analog subsystem. Modern measurement systems analysis (MSA) tools are being developed to help verify system health and measurement integrity. Legacy hard wired digital data systems have been replaced by distributed Fibre Channel (FC) network connected digitizers where high speed sampling rates have increased to 256,000 samples per second. Several analog video cameras have been replaced by digital image and storage systems. Hard-wired analog control systems have been replaced by Programmable Logic Controllers (PLC), fiber optic networks (FON) infrastructure and human machine interface (HMI) operator screens. New modern IT Security procedures and schemes have been employed to control data access and process control flows. Due to the nature of testing possible at B-2, flexibility and configurability of systems has been central to the architecture during modernization.

Modernization of B-2 Data, Video, and Control Systems Infrastructure

NASA Technical Reports Server (NTRS)

Cmar, Mark D.; Maloney, Christian T.; Butala, Vishal D.

2012-01-01

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) Plum Brook Station (PBS) Spacecraft Propulsion Research Facility, commonly referred to as B-2, is NASA's third largest thermal-vacuum facility with propellant systems capability. B-2 has completed a modernization effort of its facility legacy data, video and control systems infrastructure to accommodate modern integrated testing and Information Technology (IT) Security requirements. Integrated systems tests have been conducted to demonstrate the new data, video and control systems functionality and capability. Discrete analog signal conditioners have been replaced by new programmable, signal processing hardware that is integrated with the data system. This integration supports automated calibration and verification of the analog subsystem. Modern measurement systems analysis (MSA) tools are being developed to help verify system health and measurement integrity. Legacy hard wired digital data systems have been replaced by distributed Fibre Channel (FC) network connected digitizers where high speed sampling rates have increased to 256,000 samples per second. Several analog video cameras have been replaced by digital image and storage systems. Hard-wired analog control systems have been replaced by Programmable Logic Controllers (PLC), fiber optic networks (FON) infrastructure and human machine interface (HMI) operator screens. New modern IT Security procedures and schemes have been employed to control data access and process control flows. Due to the nature of testing possible at B-2, flexibility and configurability of systems has been central to the architecture during modernization.

Automation of the 1.3-meter Robotically Controlled Telescope (RCT)

NASA Astrophysics Data System (ADS)

Gelderman, Richard; Treffers, Richard R.

2011-03-01

This poster describes the automation for the Robotically Controlled Telescope (RCT) Consortium of the 50-inch telescope at Kitt Peak National Observatory. Building upon the work of the previous contractor the telescope, dome and instrument were wired for totally autonomous (robotic) observations. The existing motors, encoders, limit switches and cables were connected to an open industrial panel that allows easy interconnection, troubleshooting and modifications. A sixteen axis Delta Tau Turbo PMAC controller is used to control all motors, encoders, flat field lights and many of the digital functions of the telescope. ADAM industrial I/O bricks are used for additional digital and analog I/O functions. Complex relay logic problems, such as the mirror cover opening sequence and the slit control, are managed using Allen Bradley Pico PLDs. Most of the low level software is written in C using the GNU compiler. The basic functionality uses an ASCII protocol communicating over Berkeley sockets. Early versions of this software were developed at U.C. Berkeley, for what was to become the Katzman Automatic Imaging Telescope (KAIT) at Lick Observatory. ASCII communications are useful for control, testing and easy to debug by looking at the log files; C-shell scripts are written to form more complex orchestrations.

Cognitive impairments in poly-drug ketamine users.

PubMed

Liang, H J; Lau, C G; Tang, A; Chan, F; Ungvari, G S; Tang, W K

2013-11-01

Cognitive impairment has been found to be reversible in people with substance abuse, particularly those using ketamine. Ketamine users are often poly-substance users. This study compared the cognitive functions of current and former ketamine users who were also abusing other psychoactive substances with those of non-users of illicit drugs as controls. One hundred ketamine poly-drug users and 100 controls were recruited. Drug users were divided into current (n = 32) and ex-users (n = 64) according to the duration of abstinence from ketamine (>30 days). The Beck Depression Inventory (BDI), the Hospital Anxiety Depression Scale (HADSA) and the Severity of Dependence Scale (SDS) were used to evaluate depression and anxiety symptoms and the severity of drug use, respectively. The cognitive test battery comprised verbal memory (Wechsler Memory Scale III: Logic Memory and Word List), visual memory (Rey-Osterrieth Complex Figure, ROCF), executive function (Stroop, Wisconsin Card Sorting Test, and Modified Verbal Fluency Test), working memory (Digit Span Backward), and general intelligence (Information, Arithmetic and Digit-Symbol Coding) tests. Current users had higher BDI and HADSA scores than ex-users (p < 0.001 for BDI and p = 0.022 for HADSA) and controls (p < 0.001 for BDI and p = 0.002 for HADSA). Ex-users had higher BDI (p = 0.006) but equal HADSA scores (p = 1.000) compared to controls. Both current and ex-users had lower scores on Logical Memory delayed recall (p = 0.038 for current users and p = 0.032 for ex-users) and ROCF delayed recall (p = 0.033 for current users and p = 0.014 for ex-users) than controls. Current users also performed worse on ROCF recognition than controls (p = 0.002). No difference was found between the cognitive functions of current and ex-users. Ketamine poly-drug users displayed predominantly verbal and visual memory impairments, which persisted in ex-users. The interactive effect of ketamine and poly-drug use on memory needs further investigation. © 2013 Elsevier Ltd. All rights reserved.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Procedure for extraction of disparate data from maps into computerized data bases

NASA Technical Reports Server (NTRS)

Junkin, B. G.

1979-01-01

A procedure is presented for extracting disparate sources of data from geographic maps and for the conversion of these data into a suitable format for processing on a computer-oriented information system. Several graphic digitizing considerations are included and related to the NASA Earth Resources Laboratory's Digitizer System. Current operating procedures for the Digitizer System are given in a simplified and logical manner. The report serves as a guide to those organizations interested in converting map-based data by using a comparable map digitizing system.

Fuzzy logic controller optimization

DOEpatents

Sepe, Jr., Raymond B; Miller, John Michael

2004-03-23

A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.

Computer-automated opponent for manned air-to-air combat simulations

NASA Technical Reports Server (NTRS)

Hankins, W. W., III

1979-01-01

Two versions of a real-time digital-computer program that operates a fighter airplane interactively against a human pilot in simulated air combat were evaluated. They function by replacing one of two pilots in the Langley differential maneuvering simulator. Both versions make maneuvering decisions from identical information and logic; they differ essentially in the aerodynamic models that they control. One is very complete, but the other is much simpler, primarily characterizing the airplane's performance (lift, drag, and thrust). Both models competed extremely well against highly trained U.S. fighter pilots.

Economical Implementation of a Filter Engine in an FPGA

NASA Technical Reports Server (NTRS)

Kowalski, James E.

2009-01-01

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

An Undergraduate Design Experience in Digital Logic Design Course of Special Purpose Arithmetic Logic Unit Using Multisim, Ultiboard and Print Circuit Board

ERIC Educational Resources Information Center

Al-Haija, Qasem Abu; Al-Amri, Hasan; Al-Nashri, Mohamed; Al-Muhaisen, Sultan

2013-01-01

Project-Based Curriculum (PBC) is considered one of the most powerful methods in the engineering education where each course or courses-cluster is assigned a design project which considers a series of inter-related concepts that have been shown theoretically for the students. Using this approach, the student will gain the required knowledge in an…

Low power signal processing research at Stanford

NASA Technical Reports Server (NTRS)

Burr, J.; Williamson, P. R.; Peterson, A.

1991-01-01

This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

The Matter of New Media Making: An Intra-Action Analysis of Adolescents Making a Digital Book Trailer

ERIC Educational Resources Information Center

Ehret, Christian; Hollett, Ty; Jocius, Robin

2016-01-01

Representational logic cannot account for the entanglements of all that matters in making new media: feeling bodies, vibrant matter, feeling bodies and vibrant matter all moving and at different rates. In the currently shifting communicative landscape, where mobile technologies are the primary means for youths' digital production, all this…

Integrated flight/propulsion control - Adaptive engine control system mode

NASA Technical Reports Server (NTRS)

Yonke, W. A.; Terrell, L. A.; Meyers, L. P.

1985-01-01

The adaptive engine control system mode (ADECS) which is developed and tested on an F-15 aircraft with PW1128 engines, using the NASA sponsored highly integrated digital electronic control program, is examined. The operation of the ADECS mode, as well as the basic control logic, the avionic architecture, and the airframe/engine interface are described. By increasing engine pressure ratio (EPR) additional thrust is obtained at intermediate power and above. To modulate the amount of EPR uptrim and to prevent engine stall, information from the flight control system is used. The performance benefits, anticipated from control integration are shown for a range of flight conditions and power settings. It is found that at higher altitudes, the ADECS mode can increase thrust as much as 12 percent, which is used for improved acceleration, improved turn rate, or sustained turn angle.

Biomolecular filters for improved separation of output signals in enzyme logic systems applied to biomedical analysis.

PubMed

Halámek, Jan; Zhou, Jian; Halámková, Lenka; Bocharova, Vera; Privman, Vladimir; Wang, Joseph; Katz, Evgeny

2011-11-15

Biomolecular logic systems processing biochemical input signals and producing "digital" outputs in the form of YES/NO were developed for analysis of physiological conditions characteristic of liver injury, soft tissue injury, and abdominal trauma. Injury biomarkers were used as input signals for activating the logic systems. Their normal physiological concentrations were defined as logic-0 level, while their pathologically elevated concentrations were defined as logic-1 values. Since the input concentrations applied as logic 0 and 1 values were not sufficiently different, the output signals being at low and high values (0, 1 outputs) were separated with a short gap making their discrimination difficult. Coupled enzymatic reactions functioning as a biomolecular signal processing system with a built-in filter property were developed. The filter process involves a partial back-conversion of the optical-output-signal-yielding product, but only at its low concentrations, thus allowing the proper discrimination between 0 and 1 output values.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Design Architecture and Initial Results from an FPGA Based Digital Receiver for Multistatic Meteor Measurements

NASA Astrophysics Data System (ADS)

Palo, Scott; Vaudrin, Cody

Defined by a minimal RF front-end followed by an analog-to-digital converter (ADC) and con-trolled by a reconfigurable logic device (FPGA), the digital receiver will replace conventional heterodyning analog receivers currently in use by the COBRA meteor radar. A basic hardware overview touches on the major digital receiver components, theory of operation and data han-dling strategies. We address concerns within the community regarding the implementation of digital receivers in small-scale scientific radars, and outline the numerous benefits with a focus on reconfigurability. From a remote sensing viewpoint, having complete visibility into a band of the EM spectrum allows an experiment designer to focus on parameter estimation rather than hardware limitations. Finally, we show some basic multistatic receiver configurations enabled through GPS time synchronization. Currently, the digital receiver is configured to facilitate range and radial velocity determination of meteors in the MLT region for use with the COBRA meteor radar. Initial measurements from data acquired at Platteville, Colorado and Tierra Del Fuego in Argentina will be presented. We show an improvement in detection rates compared to conventional analog systems. Scientific justification for a digital receiver is clearly made by the presentation of RTI plots created using data acquired from the receiver. These plots reveal an interesting phenomenon concerning vacillating power structures in a select number of meteor trails.

Optical implementation of a parallel out-of-band controller for large broadband ATM switch applications

NASA Astrophysics Data System (ADS)

Cloonan, Thomas J.; Richards, Gaylord W.; Lentine, Anthony L.

1996-03-01

Asynchronous transfer mode (ATM) is rapidly becoming the transport mechanism of choice for the information superhighway, because it promises the bandwidth and flexibility needed for many voice, video and data service offerings. Some industry experts project that the required sizes for ATM switching equipment in the public-switched environment will reach the Tbps range by the beginning of the next decade. This paper analyzes the problems associated with controlling the flow of packets within a broadband ATM switch of this size. The analysis is based on the requirements of the growable packet switch architecture. The paper proposes a novel solution to the problem of hunting paths within an ATM packet switch network. The resulting control scheme is unconventional in two ways. First, it uses an out-of-band control algorithm instead of the more common self-routing approach. In particular, we explore the benefits of using a parallel processor as an out-of-band controller for a growable packet switch distribution network. The processor permits additional levels of parallelism to be added to the out-of-band control function so that path hunts can be performed for all N of the input ports within a single cell interval. The proposed approach is also unconventional because it uses free-space digital optics to guide signals between successive stages of the controller. The paper describes the underlying motivations for implementing an optical out-of-band controller for an ATM switch, and it also describes the logic within a controller node that has been fabricated using a hybrid Si CMOS/GaAs SEED technology. The node uses optical detectors (in GaAs), amplifiers and digital control logic (in Si), and optical modulators (in GaAs). Free-space optical connections between successive device arrays can be provided using either bulk optical elements or micro-optics, but the optical interconnects must provide massive fanout capability. An architectural analysis studying the feasibility of applying free-space optics in this proposed ATM switch controller also is presented.

Building Multi-Discipline, Multi-Format Digital Libraries Using Clusters and Buckets. Degree rewarded by Old Dominion Univ. on Aug. 1997

NASA Technical Reports Server (NTRS)

Nelson, Michael L.

1997-01-01

Our objective was to study the feasibility of extending the Dienst protocol to enable a multi-discipline, multi-format digital library. We implemented two new technologies: cluster functionality and publishing buckets. We have designed a possible implementation of clusters and buckets, and have prototyped some aspects of the resultant digital library. Currently, digital libraries are segregated by the disciplines they serve (computer science, aeronautics, etc.), and by the format of their holdings (reports, software, datasets, etc.). NCSTRL+ is a multi-discipline, multi-format digital library (DL) prototype created to explore the feasibility of the design and implementation issues involved with created a unified, canonical scientific and technical information (STI) DL. NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible DL that provides access to over 80 university departments and laboratories. We have extended the Dienst protocol (version 4.1.8), the protocol underlying NCSTRL, to provide the ability to cluster independent collections into a logically centralized DL based upon subject category classification, type of organization, and genre of material. The concept of buckets provides a mechanism for publishing and managing logically linked entities with multiple data formats.

Simultaneous G-Quadruplex DNA Logic.

PubMed

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takeuchi, Naoki, E-mail: takeuchi-naoki-kx@ynu.jp; Yamanashi, Yuki; Yoshikawa, Nobuyuki

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells inmore » the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.« less

Adiabatic quantum-flux-parametron cell library adopting minimalist design

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2015-05-01

We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

Demonstration of the Dynamic Flowgraph Methodology using the Titan 2 Space Launch Vehicle Digital Flight Control System

NASA Technical Reports Server (NTRS)

Yau, M.; Guarro, S.; Apostolakis, G.

1993-01-01

Dynamic Flowgraph Methodology (DFM) is a new approach developed to integrate the modeling and analysis of the hardware and software components of an embedded system. The objective is to complement the traditional approaches which generally follow the philosophy of separating out the hardware and software portions of the assurance analysis. In this paper, the DFM approach is demonstrated using the Titan 2 Space Launch Vehicle Digital Flight Control System. The hardware and software portions of this embedded system are modeled in an integrated framework. In addition, the time dependent behavior and the switching logic can be captured by this DFM model. In the modeling process, it is found that constructing decision tables for software subroutines is very time consuming. A possible solution is suggested. This approach makes use of a well-known numerical method, the Newton-Raphson method, to solve the equations implemented in the subroutines in reverse. Convergence can be achieved in a few steps.

Buckets, Clusters and Dienst

NASA Technical Reports Server (NTRS)

Nelson, Michael L.; Maly, Kurt; Shen, Stewart N. T.

1997-01-01

In this paper we describe NCSTRL+, a unified, canonical digital library for scientific and technical information (STI). NCSTRL+ is based on the Networked Computer Science Technical Report Library (NCSTRL), a World Wide Web (WWW) accessible digital library (DL) that provides access to over 80 university departments and laboratories. NCSTRL+ implements two new technologies: cluster functionality and publishing "buckets." We have extended the Dienst protocol, the protocol underlying NCSTRL, to provide the ability to "cluster" independent collections into a logically centralized digital library based upon subject category classification, type of organization, and genres of material. The concept of "buckets" provides a mechanism for publishing and managing logically linked entities with multiple data formats. The NCSTRL+ prototype DL contains the holdings of NCSTRL and the NASA Technical Report Server (NTRS). The prototype demonstrates the feasibility of publishing into a multi-cluster DL, searching across clusters, and storing and presenting buckets of information. We show that the overhead for these additional capabilities is minimal to both the author and the user when compared to the equivalent process within NCSTRL.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Event related potentials to digit learning: tracking neurophysiologic changes accompanying recall performance.

PubMed

Jongsma, Marijtje L A; Gerrits, Niels J H M; van Rijn, Clementina M; Quiroga, Rodrigo Quian; Maes, Joseph H R

2012-07-01

The aim of this study was to track recall performance and event-related potentials (ERPs) across multiple trials in a digit-learning task. When a sequence is practiced by repetition, the number of errors typically decreases and a learning curve emerges. Until now, almost all ERP learning and memory research has focused on effects after a single presentation and, therefore, fails to capture the dynamic changes that characterize a learning process. However, the current study used a free-recall task in which a sequence of ten auditory digits was presented repeatedly. Auditory sequences of ten digits were presented in a logical order (control sequences) or in a random order (experimental sequences). Each sequence was presented six times. Participants had to reproduce the sequence after each presentation. EEG recordings were made at the time of the digit presentations. Recall performance for the control sequences was close to asymptote right after the first learning trial, whereas performance for the experimental sequences initially displayed primacy and recency effects. However, these latter effects gradually disappeared over the six repetitions, resulting in near-asymptotic recall performance for all digits. The performance improvement for the middle items of the list was accompanied by an increase in P300 amplitude, implying a close correspondence between this ERP component and the behavioral data. These results, which were discussed in the framework of theories on the functional significance of the P300 amplitude, add to the scarce empirical data on the dynamics of ERP responses in the process of intentional learning. Copyright © 2011 Elsevier B.V. All rights reserved.

Current Trend Towards Using Soft Computing Approaches to Phase Synchronization in Communication Systems

NASA Technical Reports Server (NTRS)

Drake, Jeffrey T.; Prasad, Nadipuram R.

1999-01-01

This paper surveys recent advances in communications that utilize soft computing approaches to phase synchronization. Soft computing, as opposed to hard computing, is a collection of complementary methodologies that act in producing the most desirable control, decision, or estimation strategies. Recently, the communications area has explored the use of the principal constituents of soft computing, namely, fuzzy logic, neural networks, and genetic algorithms, for modeling, control, and most recently for the estimation of phase in phase-coherent communications. If the receiver in a digital communications system is phase-coherent, as is often the case, phase synchronization is required. Synchronization thus requires estimation and/or control at the receiver of an unknown or random phase offset.

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

PubMed

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

NASA Technical Reports Server (NTRS)

Timoc, C.; Tran, T.; Wongso, J.

1992-01-01

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Nonlinear dynamics based digital logic and circuits.

PubMed

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Neighborhood comparison operator

NASA Technical Reports Server (NTRS)

Gennery, Donald B. (Inventor)

1987-01-01

Digital values in a moving window are compared by an operator having nine comparators (18) connected to line buffers (16) for receiving a succession of central pixels together with eight neighborhood pixels. A single bit of program control determines whether the neighborhood pixels are to be compared with the central pixel or a threshold value. The central pixel is always compared with the threshold. The comparator output, plus 2 bits indicating odd-even pixel/line information about the central pixel, addresses a lookup table (20) to provide 14 bits of information, including 2 bits which control a selector (22) to pass either the central pixel value, the other 12 bits of table information, or the bit-wise logic OR of all neighboring pixels.

4-GHz counters bring synthesizers up to speed

NASA Astrophysics Data System (ADS)

Lee, F.; Miller, R.

1984-06-01

The availability of digital IC counters built on GaAs makes direct frequency division in microwave synthesizers possible. Four GHz is the highest clock rate achievable in production designs. These devices have the ability to drive TTL/CMOS logic, and the counter can be connected directly to single-chip frequency synthesizers controllers. A complete microwave sythesizer is formed by two chips and a voltage-controlled oscillator (VCO). The advantages of GaAs are discussed along with flip-flop basics, aspects of device fabrication, and the characteristics of GaAs MESAFETs. Attention is given to a GaAs prescaler usable for direct conversion, four kinds of flip-flops in a divide-by-two mode, and seven-stage binary ripple counters.

Implementation of an optimum profile guidance system on STOLAND

NASA Technical Reports Server (NTRS)

Flanagan, P. F.

1978-01-01

The implementation on the STOLAND airborne digital computer of an optimum profile guidance system for the augmentor wing jet STOL research aircraft is described. Major tasks were to implement the guidance and control logic to airborne computer software and to integrate the module with the existing STOLAND navigation, display, and autopilot routines. The optimum profile guidance system comprises an algorithm for synthesizing mimimum fuel trajectories for a wide range of starting positions in the terminal area and a control law for flying the aircraft automatically along the trajectory. The avionics software developed is described along with a FORTRAN program that was constructed to reflect the modular nature and algorthms implemented in the avionics software.

Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

NASA Technical Reports Server (NTRS)

Shiva, S. G.; Shah, A. M.

1980-01-01

The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

NASA Technical Reports Server (NTRS)

Shah, A. M.; Shiva, S. G.

1981-01-01

The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

TREAT Reactor Control and Protection System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lipinski, W.C.; Brookshier, W.K.; Burrows, D.R.

1985-01-01

The main control algorithm of the Transient Reactor Test Facility (TREAT) Automatic Reactor Control System (ARCS) resides in Read Only Memory (ROM) and only experiment specific parameters are input via keyboard entry. Prior to executing an experiment, the software and hardware of the control computer is tested by a closed loop real-time simulation. Two computers with parallel processing are used for the reactor simulation and another computer is used for simulation of the control rod system. A monitor computer, used as a redundant diverse reactor protection channel, uses more conservative setpoints and reduces challenges to the Reactor Trip System (RTS).more » The RTS consists of triplicated hardwired channels with one out of three logic. The RTS is automatically tested by a digital Dedicated Microprocessor Tester (DMT) prior to the execution of an experiment. 6 refs., 5 figs., 1 tab.« less

High density, multi-range analog output Versa Module Europa board for control system applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Kundan, E-mail: kundan@iuac.res.in; Das, Ajit Lal

2014-01-15

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the controlmore » system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.« less

Local rollback for fault-tolerance in parallel computing systems

DOEpatents

Blumrich, Matthias A [Yorktown Heights, NY; Chen, Dong [Yorktown Heights, NY; Gara, Alan [Yorktown Heights, NY; Giampapa, Mark E [Yorktown Heights, NY; Heidelberger, Philip [Yorktown Heights, NY; Ohmacht, Martin [Yorktown Heights, NY; Steinmacher-Burow, Burkhard [Boeblingen, DE; Sugavanam, Krishnan [Yorktown Heights, NY

2012-01-24

A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.

Designing learning apparatus to promote twelfth grade students’ understanding of digital technology concept: A preliminary studies

NASA Astrophysics Data System (ADS)

Marlius; Kaniawati, I.; Feranie, S.

2018-05-01

A preliminary learning design using relay to promote twelfth grade student’s understanding of logic gates concept is implemented to see how well it’s to adopted by six high school students, three male students and three female students of twelfth grade. This learning design is considered for next learning of digital technology concept i.e. data digital transmition and analog. This work is a preliminary study to design the learning for large class. So far just a few researches designing learning design related to digital technology with relay. It may due to this concept inserted in Indonesian twelfth grade curriculum recently. This analysis is focus on student difficulties trough video analysis to learn the concept. Based on our analysis, the recommended thing for redesigning learning is: students understand first about symbols and electrical circuits; the Student Worksheet is made in more detail on the assembly steps to the project board; mark with symbols at points in certain places in the circuit for easy assembly; assembly using relays by students is enough until is the NOT’s logic gates and the others that have been assembled so that effective time. The design of learning using relays can make the relay a liaison between the abstract on the digital with the real thing of it, especially in the circuit of symbols and real circuits. Besides it is expected to also enrich the ability of teachers in classroom learning about digital technology.

Reasoning About Digital Circuits.

DTIC Science & Technology

1983-07-01

The dissertation will later examine the logic’s formal syntax and semantics in great depth. Below are a few English - language statements and...function have a fixed point. Temporal lolc as a programming langua " Temporal logic can be used directly a a propamuing language . For example, the ...for a separate "sertion language ." For example, the formula S[(I+- );(I + i -- I) (I+2- I) states that if the variable I twice increaes by I in an

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Planning an Integrated On-Line Library system (IOLS)

DTIC Science & Technology

1989-03-01

Logical Workflow for Circulation of Library Materials ............. 14 Figure 9. Detail of Circulation of Libary Materials ...................... 15...Operating Honolulu, HI 96826 System (808) 947-4441 DATA RESEARCH ASSOCIATES, Inc. (ATLAS) 9270 Olive Blvd. St. Louis, MO 01775 DIGITAL EQUIPMENT CORP... DIGITAL EQUIPMENT CORP. Stow, MA 01775 (617) 897-7163 EYRING LIBRARY SYSTEMS (CARL) 5280 S. West, Suite E260 Salt Lake City, UT 84107 TANDEM SYSTEMS

Mutation Testing for Effective Verification of Digital Components of Physical Systems

NASA Astrophysics Data System (ADS)

Kushik, N. G.; Evtushenko, N. V.; Torgaev, S. N.

2015-12-01

Digital components of modern physical systems are often designed applying circuitry solutions based on the field programmable gate array technology (FPGA). Such (embedded) digital components should be carefully tested. In this paper, an approach for the verification of digital physical system components based on mutation testing is proposed. The reference description of the behavior of a digital component in the hardware description language (HDL) is mutated by introducing into it the most probable errors and, unlike mutants in high-level programming languages, the corresponding test case is effectively derived based on a comparison of special scalable representations of the specification and the constructed mutant using various logic synthesis and verification systems.

Design and implementation of fuzzy logic controllers. Thesis Final Report, 27 Jul. 1992 - 1 Jan. 1993

NASA Technical Reports Server (NTRS)

Abihana, Osama A.; Gonzalez, Oscar R.

1993-01-01

The main objectives of our research are to present a self-contained overview of fuzzy sets and fuzzy logic, develop a methodology for control system design using fuzzy logic controllers, and to design and implement a fuzzy logic controller for a real system. We first present the fundamental concepts of fuzzy sets and fuzzy logic. Fuzzy sets and basic fuzzy operations are defined. In addition, for control systems, it is important to understand the concepts of linguistic values, term sets, fuzzy rule base, inference methods, and defuzzification methods. Second, we introduce a four-step fuzzy logic control system design procedure. The design procedure is illustrated via four examples, showing the capabilities and robustness of fuzzy logic control systems. This is followed by a tuning procedure that we developed from our design experience. Third, we present two Lyapunov based techniques for stability analysis. Finally, we present our design and implementation of a fuzzy logic controller for a linear actuator to be used to control the direction of the Free Flight Rotorcraft Research Vehicle at LaRC.

Telerobotic control of a mobile coordinated robotic server. M.S. Thesis Annual Technical Report

NASA Technical Reports Server (NTRS)

Lee, Gordon

1993-01-01

The annual report on telerobotic control of a mobile coordinated robotic server is presented. The goal of this effort is to develop advanced control methods for flexible space manipulator systems. As such, an adaptive fuzzy logic controller was developed in which model structure as well as parameter constraints are not required for compensation. The work builds upon previous work on fuzzy logic controllers. Fuzzy logic controllers have been growing in importance in the field of automatic feedback control. Hardware controllers using fuzzy logic have become available as an alternative to the traditional PID controllers. Software has also been introduced to aid in the development of fuzzy logic rule-bases. The advantages of using fuzzy logic controllers include the ability to merge the experience and intuition of expert operators into the rule-base and that a model of the system is not required to construct the controller. A drawback of the classical fuzzy logic controller, however, is the many parameters needed to be turned off-line prior to application in the closed-loop. In this report, an adaptive fuzzy logic controller is developed requiring no system model or model structure. The rule-base is defined to approximate a state-feedback controller while a second fuzzy logic algorithm varies, on-line, parameters of the defining controller. Results indicate the approach is viable for on-line adaptive control of systems when the model is too complex or uncertain for application of other more classical control techniques.

One output function: a misconception of students studying digital systems - a case study

NASA Astrophysics Data System (ADS)

Trotskovsky, E.; Sabag, N.

2015-05-01

Background:Learning processes are usually characterized by students' misunderstandings and misconceptions. Engineering educators intend to help their students overcome their misconceptions and achieve correct understanding of the concept. This paper describes a misconception in digital systems held by many students who believe that combinational logic circuits should have only one output. Purpose:The current study aims to investigate the roots of the misconception about one-output function and the pedagogical methods that can help students overcome the misconception. Sample:Three hundred and eighty-one students in the Departments of Electrical and Electronics and Mechanical Engineering at an academic engineering college, who learned the same topics of a digital combinational system, participated in the research. Design and method:In the initial research stage, students were taught according to traditional method - first to design a one-output combinational logic system, and then to implement a system with a number of output functions. In the main stage, an experimental group was taught using a new method whereby they were shown how to implement a system with several output functions, prior to learning about one-output systems. A control group was taught using the traditional method. In the replication stage (the third stage), an experimental group was taught using the new method. A mixed research methodology was used to examine the results of the new learning method. Results:Quantitative research showed that the new teaching approach resulted in a statistically significant decrease in student errors, and qualitative research revealed students' erroneous thinking patterns. Conclusions:It can be assumed that the traditional teaching method generates an incorrect mental model of the one-output function among students. The new pedagogical approach prevented the creation of an erroneous mental model and helped students develop the correct conceptual understanding.

Robust Fuzzy Controllers Using FPGAs

NASA Technical Reports Server (NTRS)

Monroe, Author Gene S., Jr.

2007-01-01

Electro-mechanical device controllers typically come in one of three forms, proportional (P), Proportional Derivative (PD), and Proportional Integral Derivative (PID). Two methods of control are discussed in this paper; they are (1) the classical technique that requires an in-depth mathematical use of poles and zeros, and (2) the fuzzy logic (FL) technique that is similar to the way humans think and make decisions. FL controllers are used in multiple industries; examples include control engineering, computer vision, pattern recognition, statistics, and data analysis. Presented is a study on the development of a PD motor controller written in very high speed hardware description language (VHDL), and implemented in FL. Four distinct abstractions compose the FL controller, they are the fuzzifier, the rule-base, the fuzzy inference system (FIS), and the defuzzifier. FL is similar to, but different from, Boolean logic; where the output value may be equal to 0 or 1, but it could also be equal to any decimal value between them. This controller is unique because of its VHDL implementation, which uses integer mathematics. To compensate for VHDL's inability to synthesis floating point numbers, a scale factor equal to 10(sup (N/4) is utilized; where N is equal to data word size. The scaling factor shifts the decimal digits to the left of the decimal point for increased precision. PD controllers are ideal for use with servo motors, where position control is effective. This paper discusses control methods for motion-base platforms where a constant velocity equivalent to a spectral resolution of 0.25 cm(exp -1) is required; however, the control capability of this controller extends to various other platforms.

A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

PubMed

Bayindir, Ramazan; Cetinceviz, Yucel

2011-04-01

This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. Copyright © 2010 ISA. Published by Elsevier Ltd. All rights reserved.

Scalable digital hardware for a trapped ion quantum computer

NASA Astrophysics Data System (ADS)

Mount, Emily; Gaultney, Daniel; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

2016-12-01

Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for loading, cooling, initialization, and detection of the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

Flip-Flop Digital Modulator

NASA Technical Reports Server (NTRS)

Eno, R. F.

1984-01-01

Clock switched on and off in response to data signal. Flip-flop modulator generates square-wave carrier frequency that is half clock frequency and turns carrier on and off. Final demodulator output logical inverse of data input.

C code generation from Petri-net-based logic controller specification

NASA Astrophysics Data System (ADS)

Grobelny, Michał; Grobelna, Iwona; Karatkevich, Andrei

2017-08-01

The article focuses on programming of logic controllers. It is important that a programming code of a logic controller is executed flawlessly according to the primary specification. In the presented approach we generate C code for an AVR microcontroller from a rule-based logical model of a control process derived from a control interpreted Petri net. The same logical model is also used for formal verification of the specification by means of the model checking technique. The proposed rule-based logical model and formal rules of transformation ensure that the obtained implementation is consistent with the already verified specification. The approach is validated by practical experiments.

NULL Convention Floating Point Multiplier

PubMed Central

Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation. PMID:25879069

NULL convention floating point multiplier.

PubMed

Albert, Anitha Juliette; Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Complex logic functions implemented with quantum dot bionanophotonic circuits.

PubMed

Claussen, Jonathan C; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2014-03-26

We combine quantum dots (QDs) with long-lifetime terbium complexes (Tb), a near-IR Alexa Fluor dye (A647), and self-assembling peptides to demonstrate combinatorial and sequential bionanophotonic logic devices that function by time-gated Förster resonance energy transfer (FRET). Upon excitation, the Tb-QD-A647 FRET-complex produces time-dependent photoluminescent signatures from multi-FRET pathways enabled by the capacitor-like behavior of the Tb. The unique photoluminescent signatures are manipulated by ratiometrically varying dye/Tb inputs and collection time. Fluorescent output is converted into Boolean logic states to create complex arithmetic circuits including the half-adder/half-subtractor, 2:1 multiplexer/1:2 demultiplexer, and a 3-digit, 16-combination keypad lock.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Diagnostic emulation: Implementation and user's guide

NASA Technical Reports Server (NTRS)

Becher, Bernice

1987-01-01

The Diagnostic Emulation Technique was developed within the System Validation Methods Branch as a part of the development of methods for the analysis of the reliability of highly reliable, fault tolerant digital avionics systems. This is a general technique which allows for the emulation of a digital hardware system. The technique is general in the sense that it is completely independent of the particular target hardware which is being emulated. Parts of the system are described and emulated at the logic or gate level, while other parts of the system are described and emulated at the functional level. This algorithm allows for the insertion of faults into the system, and for the observation of the response of the system to these faults. This allows for controlled and accelerated testing of system reaction to hardware failures in the target machine. This document describes in detail how the algorithm was implemented at NASA Langley Research Center and gives instructions for using the system.

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

NASA Technical Reports Server (NTRS)

Hamilton, M. H.

1972-01-01

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

The DIRC front-end electronics chain for BaBar

NASA Astrophysics Data System (ADS)

Bailly, P.; Beigbeder, C.; Bernier, R.; Breton, D.; Bonneaud, G.; Caceres, T.; Chase, R.; Chauveau, J.; Del Buono, L.; Dohou, F.; Ducorps, A.; Gastaldi, F.; Genat, J. F.; Hrisoho, A.; Imbert, P.; Lebbolo, H.; Matricon, P.; Oxoby, G.; Renard, C.; Roos, L.; Sen, S.; Thiebaux, C.; Truong, K.; Tocut, V.; Vasileiadis, G.; Va'Vra, J.; Verderi, M.; Warner, D.; Wilson, R. J.; Wormser, G.; Zhang, B.; Zomer, F.

2000-12-01

Recent results from the Front-End electronics of the Detector of Internally Reflected Cerenkov light (DIRC) for the BaBar experiment at SLAC (Stanford, USA) are presented. It measures to better than 1 ns the arrival time of Cerenkov photoelectrons detected in a 11000 phototubes array and their amplitude spectra. It mainly comprises 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom digital time to digital chips (TDC) for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected front up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of the pre-production chips are presented, as well as system tests.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Automating Access Control Logics in Simple Type Theory with LEO-II

NASA Astrophysics Data System (ADS)

Benzmüller, Christoph

Garg and Abadi recently proved that prominent access control logics can be translated in a sound and complete way into modal logic S4. We have previously outlined how normal multimodal logics, including monomodal logics K and S4, can be embedded in simple type theory and we have demonstrated that the higher-order theorem prover LEO-II can automate reasoning in and about them. In this paper we combine these results and describe a sound (and complete) embedding of different access control logics in simple type theory. Employing this framework we show that the off the shelf theorem prover LEO-II can be applied to automate reasoning in and about prominent access control logics.

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

NASA Technical Reports Server (NTRS)

Harper, Michael; Miller, Joseph; Shen, Yuzhong

2011-01-01

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Memory device for two-dimensional radiant energy array computers

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1977-01-01

A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

The development of an interim generalized gate logic software simulator

NASA Technical Reports Server (NTRS)

Mcgough, J. G.; Nemeroff, S.

1985-01-01

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

A Web application for the management of clinical workflow in image-guided and adaptive proton therapy for prostate cancer treatments.

PubMed

Yeung, Daniel; Boes, Peter; Ho, Meng Wei; Li, Zuofeng

2015-05-08

Image-guided radiotherapy (IGRT), based on radiopaque markers placed in the prostate gland, was used for proton therapy of prostate patients. Orthogonal X-rays and the IBA Digital Image Positioning System (DIPS) were used for setup correction prior to treatment and were repeated after treatment delivery. Following a rationale for margin estimates similar to that of van Herk,(1) the daily post-treatment DIPS data were analyzed to determine if an adaptive radiotherapy plan was necessary. A Web application using ASP.NET MVC5, Entity Framework, and an SQL database was designed to automate this process. The designed features included state-of-the-art Web technologies, a domain model closely matching the workflow, a database-supporting concurrency and data mining, access to the DIPS database, secured user access and roles management, and graphing and analysis tools. The Model-View-Controller (MVC) paradigm allowed clean domain logic, unit testing, and extensibility. Client-side technologies, such as jQuery, jQuery Plug-ins, and Ajax, were adopted to achieve a rich user environment and fast response. Data models included patients, staff, treatment fields and records, correction vectors, DIPS images, and association logics. Data entry, analysis, workflow logics, and notifications were implemented. The system effectively modeled the clinical workflow and IGRT process.

Development of Fuzzy Logic Controller for Quanser Bench-Top Helicopter

NASA Astrophysics Data System (ADS)

Jafri, M. H.; Mansor, H.; Gunawan, T. S.

2017-11-01

Bench-top helicopter is a laboratory scale helicopter that usually used as a testing bench of the real helicopter behavior. This helicopter is a 3 Degree of Freedom (DOF) helicopter which works by three different axes wshich are elevation, pitch and travel. Thus, fuzzy logic controller has been proposed to be implemented into Quanser bench-top helicopter because of its ability to work with non-linear system. The objective for this project is to design and apply fuzzy logic controller for Quanser bench-top helicopter. Other than that, fuzzy logic controller performance system has been simulated to analyze and verify its behavior over existing PID controller by using Matlab & Simulink software. In this research, fuzzy logic controller has been designed to control the elevation angle. After simulation has been performed, it can be seen that simulation result shows that fuzzy logic elevation control is working for 4°, 5° and 6°. These three angles produce zero steady state error and has a fast response. Other than that, performance comparisons have been performed between fuzzy logic controller and PID controller. Fuzzy logic elevation control has a better performance compared to PID controller where lower percentage overshoot and faster settling time have been achieved in 4°, 5° and 6° step response test. Both controller are have zero steady state error but fuzzy logic controller is managed to produce a better performance in term of settling time and percentage overshoot which make the proposed controller is reliable compared to the existing PID controller.

Failure detection and identification for a reconfigurable flight control system

NASA Technical Reports Server (NTRS)

Dallery, Francois

1987-01-01

Failure detection and identification logic for a fault-tolerant longitudinal control system were investigated. Aircraft dynamics were based upon the cruise condition for a hypothetical transonic business jet transport configuration. The fault-tolerant control system consists of conventional control and estimation plus a new outer loop containing failure detection, identification, and reconfiguration (FDIR) logic. It is assumed that the additional logic has access to all measurements, as well as to the outputs of the control and estimation logic. The pilot may also command the FDIR logic to perform special tests.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

NASA Astrophysics Data System (ADS)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Parallel database search and prime factorization with magnonic holographic memory devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khitun, Alexander

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploitmore » wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.« less

FPGA Implementation of Metastability-Based True Random Number Generator

NASA Astrophysics Data System (ADS)

Hata, Hisashi; Ichikawa, Shuichi

True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

Parallel database search and prime factorization with magnonic holographic memory devices

NASA Astrophysics Data System (ADS)

Khitun, Alexander

2015-12-01

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

Neighborhood comparison operator

NASA Technical Reports Server (NTRS)

Gennery, D. B. (Inventor)

1985-01-01

Digital values in a moving window are compared by an operator having nine comparators connected to line buffers for receiving a succession of central pixels together with eight neighborhood pixels. A single bit of program control determines whether the neighborhood pixels are to be compared with the central pixel or a threshold value. The central pixel is always compared with the threshold. The omparator output plus 2 bits indicating odd-even pixel/line information about the central pixel addresses a lookup table to provide 14 bits of information, including 2 bits which control a selector to pass either the central pixel value, the other 12 bits of table information, or the bit-wise logical OR of all nine pixels through circuit that implements a very wide OR gate.

Test and evaluation of the HIDEC engine uptrim algorithm

NASA Technical Reports Server (NTRS)

Ray, R. J.; Myers, L. P.

1986-01-01

The highly integrated digital electronic control (HIDEC) program will demonstrate and evaluate the improvements in performance and mission effectiveness that result from integrated engine-airframe control systems. Performance improvements will result from an adaptive engine stall margin mode, a highly integrated mode that uses the airplane flight conditions and the resulting inlet distortion to continuously compute engine stall margin. When there is excessive stall margin, the engine is uptrimmed for more thrust by increasing engine pressure ratio (EPR). The EPR uptrim logic has been evaluated and implemented into computer simulations. Thrust improvements over 10 percent are predicted for subsonic flight conditions. The EPR uptrim was successfully demonstrated during engine ground tests. Test results verify model predictions at the conditions tested.

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

Bio-logic analysis of injury biomarker patterns in human serum samples.

PubMed

Zhou, Jian; Halámek, Jan; Bocharova, Vera; Wang, Joseph; Katz, Evgeny

2011-01-15

Digital biosensor systems analyzing biomarkers characteristic of liver injury (LI), soft tissue injury (STI) and abdominal trauma (ABT) were developed and optimized for their performance in serum solutions spiked with injury biomarkers in order to mimic real medical samples. The systems produced 'Alert'-type optical output signals in the form of "YES-NO" separated by a threshold value. The new approach aims at the reliable detection of injury biomarkers for making autonomous decisions towards timely therapeutic interventions, particularly in conditions when a hospital treatment is not possible. The enzyme-catalyzed reactions performing Boolean AND/NAND logic operations in the presence of different combinations of the injury biomarkers allowed high-fidelity biosensing. Robustness of the systems was confirmed by their operation in serum solutions, representing the first example of chemically performed logic analysis of biological fluids and a step closer towards practical biomedical applications of enzyme-logic bioassays. Copyright © 2010 Elsevier B.V. All rights reserved.

Control of electrochemical signals from quantum dots conjugated to organic materials by using DNA structure in an analog logic gate.

PubMed

Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo

2016-10-01

Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system. Copyright © 2016 Elsevier B.V. All rights reserved.

The evolvability of programmable hardware.

PubMed

Raman, Karthik; Wagner, Andreas

2011-02-06

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected 'neutral networks' in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10(45) logic circuits ('genotypes') and 10(19) logic functions ('phenotypes'). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.

The evolvability of programmable hardware

PubMed Central

Raman, Karthik; Wagner, Andreas

2011-01-01

In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

Biofabricated film with enzymatic and redox-capacitor functionalities to harvest and store electrons.

PubMed

Liba, Benjamin D; Kim, Eunkyoung; Martin, Alexandra N; Liu, Yi; Bentley, William E; Payne, Gregory F

2013-03-01

Exciting opportunities in bioelectronics will be facilitated by materials that can bridge the chemical logic of biology and the digital logic of electronics. Here we report the fabrication of a dual functional hydrogel film that can harvest electrons from its chemical environment and store these electrons by switching the film's redox-state. The hydrogel scaffold was formed by the anodic deposition of the aminopolysaccharide chitosan. Electron-harvesting function was conferred by co-depositing the enzyme glucose dehydrogenase (GDH) with chitosan. GDH catalyzes the transfer of electrons from glucose to the soluble redox-shuttle NADP(+). Electron-storage function was conferred by the redox-active food phenolic chlorogenic acid (CA) that was enzymatically grafted to the chitosan scaffold using tyrosinase. The grafted CA undergoes redox-cycling reactions with NADPH resulting in the net transfer of electrons to the film where they are stored in the reduced state of CA. The individual and dual functionalities of these films were demonstrated experimentally. There are three general conclusions from this proof-of-concept study. First, enzymatically-grafted catecholic moieties confer redox-capacitor function to the chitosan scaffold. Second, biological materials (i.e. chitosan and CA) and mechanisms (i.e. tyrosinase-mediated grafting) allow the reagentless fabrication of functional films that should be environmentally-friendly, safe and potentially even edible. Finally, the film's ability to mediate the transfer of electrons from a biological metabolite to an electrode suggests an approach to bridge the chemical logic of biology with the digital logic of electronics.

Improving learning performance with happiness by interactive scenarios.

PubMed

Chuang, Chi-Hung; Chen, Ying-Nong; Tsai, Luo-Wei; Lee, Chun-Chieh; Tsai, Hsin-Chun

2014-01-01

Recently, digital learning has attracted a lot of researchers to improve the problems of learning carelessness, low learning ability, lack of concentration, and difficulties in comprehending the logic of math. In this study, a digital learning system based on Kinect somatosensory system is proposed to make children and teenagers happily learn in the course of the games and improve the learning performance. We propose two interactive geometry and puzzle games. The proposed somatosensory games can make learners feel curious and raise their motivation to find solutions for boring problems via abundant physical expressions and interactive operations. The players are asked to select particular operation by gestures and physical expressions within a certain time. By doing so, the learners can feel the fun of game playing and train their logic ability before they are aware. Experimental results demonstrate that the proposed somatosensory system can effectively improve the students' learning performance.

Using software simulators to enhance the learning of digital logic design for the information technology students

NASA Astrophysics Data System (ADS)

Alsadoon, Abeer; Prasad, P. W. C.; Beg, Azam

2017-09-01

Making the students understand the theoretical concepts of digital logic design concepts is one of the major issues faced by the academics, therefore the teachers have tried different techniques to link the theoretical information to the practical knowledge. Use of software simulations is a technique for learning and practice that can be applied to many different disciplines. Experimentation of different computer hardware components/integrated circuits with the use of the simulators enhances the student learning. The simulators can be rather simplistic or quite complex. This paper reports our evaluation of different simulators available for use in the higher education institutions. We also provide the experience of incorporating some selected tools in teaching introductory courses in computer systems. We justified the effectiveness of incorporating the simulators into the computer system courses by use of student survey and final grade results.

Improving Learning Performance with Happiness by Interactive Scenarios

PubMed Central

Chuang, Chi-Hung; Chen, Ying-Nong; Tsai, Luo-Wei; Lee, Chun-Chieh; Tsai, Hsin-Chun

2014-01-01

Recently, digital learning has attracted a lot of researchers to improve the problems of learning carelessness, low learning ability, lack of concentration, and difficulties in comprehending the logic of math. In this study, a digital learning system based on Kinect somatosensory system is proposed to make children and teenagers happily learn in the course of the games and improve the learning performance. We propose two interactive geometry and puzzle games. The proposed somatosensory games can make learners feel curious and raise their motivation to find solutions for boring problems via abundant physical expressions and interactive operations. The players are asked to select particular operation by gestures and physical expressions within a certain time. By doing so, the learners can feel the fun of game playing and train their logic ability before they are aware. Experimental results demonstrate that the proposed somatosensory system can effectively improve the students' learning performance. PMID:24558331

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Boolean Logic Tree of Label-Free Dual-Signal Electrochemical Aptasensor System for Biosensing, Three-State Logic Computation, and Keypad Lock Security Operation.

PubMed

Lu, Jiao Yang; Zhang, Xin Xing; Huang, Wei Tao; Zhu, Qiu Yan; Ding, Xue Zhi; Xia, Li Qiu; Luo, Hong Qun; Li, Nian Bing

2017-09-19

The most serious and yet unsolved problems of molecular logic computing consist in how to connect molecular events in complex systems into a usable device with specific functions and how to selectively control branchy logic processes from the cascading logic systems. This report demonstrates that a Boolean logic tree is utilized to organize and connect "plug and play" chemical events DNA, nanomaterials, organic dye, biomolecule, and denaturant for developing the dual-signal electrochemical evolution aptasensor system with good resettability for amplification detection of thrombin, controllable and selectable three-state logic computation, and keypad lock security operation. The aptasensor system combines the merits of DNA-functionalized nanoamplification architecture and simple dual-signal electroactive dye brilliant cresyl blue for sensitive and selective detection of thrombin with a wide linear response range of 0.02-100 nM and a detection limit of 1.92 pM. By using these aforementioned chemical events as inputs and the differential pulse voltammetry current changes at different voltages as dual outputs, a resettable three-input biomolecular keypad lock based on sequential logic is established. Moreover, the first example of controllable and selectable three-state molecular logic computation with active-high and active-low logic functions can be implemented and allows the output ports to assume a high impediment or nothing (Z) state in addition to the 0 and 1 logic levels, effectively controlling subsequent branchy logic computation processes. Our approach is helpful in developing the advanced controllable and selectable logic computing and sensing system in large-scale integration circuits for application in biomedical engineering, intelligent sensing, and control.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation.

PubMed

Dutta, Sourav; Zografos, Odysseas; Gurunarayanan, Surya; Radu, Iuliana; Soree, Bart; Catthoor, Francky; Naeemi, Azad

2017-12-19

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm 2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

The Greenwich Photo-heliographic Results (1874 - 1976): Initial Corrections to the Printed Publications

NASA Astrophysics Data System (ADS)

Erwin, E. H.; Coffey, H. E.; Denig, W. F.; Willis, D. M.; Henwood, R.; Wild, M. N.

2013-11-01

A new sunspot and faculae digital dataset for the interval 1874 - 1955 has been prepared under the auspices of the NOAA National Geophysical Data Center (NGDC). This digital dataset contains measurements of the positions and areas of both sunspots and faculae published initially by the Royal Observatory, Greenwich, and subsequently by the Royal Greenwich Observatory (RGO), under the title Greenwich Photo-heliographic Results ( GPR) , 1874 - 1976. Quality control (QC) procedures based on logical consistency have been used to identify the more obvious errors in the RGO publications. Typical examples of identifiable errors are North versus South errors in specifying heliographic latitude, errors in specifying heliographic (Carrington) longitude, errors in the dates and times, errors in sunspot group numbers, arithmetic errors in the summation process, and the occasional omission of solar ephemerides. Although the number of errors in the RGO publications is remarkably small, an initial table of necessary corrections is provided for the interval 1874 - 1917. Moreover, as noted in the preceding companion papers, the existence of two independently prepared digital datasets, which both contain information on sunspot positions and areas, makes it possible to outline a preliminary strategy for the development of an even more accurate digital dataset. Further work is in progress to generate an extremely reliable sunspot digital dataset, based on the long programme of solar observations supported first by the Royal Observatory, Greenwich, and then by the Royal Greenwich Observatory.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

The cognitive bases for the design of a new class of fuzzy logic controllers: The clearness transformation fuzzy logic controller

NASA Technical Reports Server (NTRS)

Sultan, Labib; Janabi, Talib

1992-01-01

This paper analyses the internal operation of fuzzy logic controllers as referenced to the human cognitive tasks of control and decision making. Two goals are targeted. The first goal focuses on the cognitive interpretation of the mechanisms employed in the current design of fuzzy logic controllers. This analysis helps to create a ground to explore the potential of enhancing the functional intelligence of fuzzy controllers. The second goal is to outline the features of a new class of fuzzy controllers, the Clearness Transformation Fuzzy Logic Controller (CT-FLC), whereby some new concepts are advanced to qualify fuzzy controllers as 'cognitive devices' rather than 'expert system devices'. The operation of the CT-FLC, as a fuzzy pattern processing controller, is explored, simulated, and evaluated.

Fuzzy logic in control systems: Fuzzy logic controller. I, II

NASA Technical Reports Server (NTRS)

Lee, Chuen Chien

1990-01-01

Recent advances in the theory and applications of fuzzy-logic controllers (FLCs) are examined in an analytical review. The fundamental principles of fuzzy sets and fuzzy logic are recalled; the basic FLC components (fuzzification and defuzzification interfaces, knowledge base, and decision-making logic) are described; and the advantages of FLCs for incorporating expert knowledge into a control system are indicated. Particular attention is given to fuzzy implication functions, the interpretation of sentence connectives (and, also), compositional operators, and inference mechanisms. Applications discussed include the FLC-guided automobile developed by Sugeno and Nishida (1985), FLC hardware systems, FLCs for subway trains and ship-loading cranes, fuzzy-logic chips, and fuzzy computers.

Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

NASA Astrophysics Data System (ADS)

Chang, S. S. L.

State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Digital Architecture for a Trace Gas Sensor Platform

NASA Technical Reports Server (NTRS)

Gonzales, Paula; Casias, Miguel; Vakhtin, Andrei; Pilgrim, Jeffrey

2012-01-01

A digital architecture has been implemented for a trace gas sensor platform, as a companion to standard analog control electronics, which accommodates optical absorption whose fractional absorbance equivalent would result in excess error if assumed to be linear. In cases where the absorption (1-transmission) is not equivalent to the fractional absorbance within a few percent error, it is necessary to accommodate the actual measured absorption while reporting the measured concentration of a target analyte with reasonable accuracy. This requires incorporation of programmable intelligence into the sensor platform so that flexible interpretation of the acquired data may be accomplished. Several different digital component architectures were tested and implemented. Commercial off-the-shelf digital electronics including data acquisition cards (DAQs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), and microcontrollers have been used to achieve the desired outcome. The most completely integrated architecture achieved during the project used the CPLD along with a microcontroller. The CPLD provides the initial digital demodulation of the raw sensor signal, and then communicates over a parallel communications interface with a microcontroller. The microcontroller analyzes the digital signal from the CPLD, and applies a non-linear correction obtained through extensive data analysis at the various relevant EVA operating pressures. The microcontroller then presents the quantitatively accurate carbon dioxide partial pressure regardless of optical density. This technique could extend the linear dynamic range of typical absorption spectrometers, particularly those whose low end noise equivalent absorbance is below one-part-in-100,000. In the EVA application, it allows introduction of a path-length-enhancing architecture whose optical interference effects are well understood and quantified without sacrificing the dynamic range that allows quantitative detection at the higher carbon dioxide partial pressures. The digital components are compact and allow reasonably complete integration with separately developed analog control electronics without sacrificing size, mass, or power draw.

SWARM: A Compact High Resolution Correlator and Wideband VLBI Phased Array Upgrade for SMA

NASA Astrophysics Data System (ADS)

Weintroub, Jonathan

2014-06-01

A new digital back end (DBE) is being commissioned on Mauna Kea. The “SMA Wideband Astronomical ROACH2 Machine”, or SWARM, processes a 4 GHz usable band in single polarization mode and is flexibly reconfigurable for 2 GHz full Stokes dual polarization. The hardware is based on the open source Reconfigurable Open Architecture Computing Hardware 2 (ROACH2) platform from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER). A 5 GSps quad-core analog-to-digital converter board uses a commercial chip from e2v installed on a CASPER-standard printed circuit board designed by Homin Jiang’s group at ASIAA. Two ADC channels are provided per ROACH2, each sampling a 2.3 GHz Nyquist band generated by a custom wideband block downconverter (BDC). The ROACH2 logic includes 16k-channel Polyphase Filterbank (F-engine) per input followed by a 10 GbE switch based corner-turn which feeds into correlator-accumulator logic (X-engines) co-located with the F-engines. This arrangement makes very effective use of a small amount of digital hardware (just 8 ROACH2s in 1U rack mount enclosures). The primary challenge now is to meet timing at full speed for a large and very complex FPGA bit code. Design of the VLBI phased sum and recorder interface logic is also in process. Our poster will describe the instrument design, with the focus on the particular challenges of ultra wideband signal processing. Early connected commissioning and science verification data will be presented.

Modified signed-digit trinary addition using synthetic wavelet filter

NASA Astrophysics Data System (ADS)

Iftekharuddin, K. M.; Razzaque, M. A.

2000-09-01

The modified signed-digit (MSD) number system has been a topic of interest as it allows for parallel carry-free addition of two numbers for digital optical computing. In this paper, harmonic wavelet joint transform (HWJT)-based correlation technique is introduced for optical implementation of MSD trinary adder implementation. The realization of the carry-propagation-free addition of MSD trinary numerals is demonstrated using synthetic HWJT correlator model. It is also shown that the proposed synthetic wavelet filter-based correlator shows high performance in logic processing. Simulation results are presented to validate the performance of the proposed technique.

Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits

NASA Astrophysics Data System (ADS)

Sutton, Akil K.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

The service telemetry and control device for space experiment “GRIS”

NASA Astrophysics Data System (ADS)

Glyanenko, A. S.

2016-02-01

Problems of scientific devices control (for example, fine control of measuring paths), collecting auxiliary (service information about working capacity, conditions of experiment carrying out, etc.) and preliminary data processing are actual for any space device. Modern devices for space research it is impossible to imagine without devices that didn't use digital data processing methods and specialized or standard interfaces and computing facilities. For realization of these functions in “GRIS” experiment onboard ISS for purposes minimization of dimensions, power consumption, the concept “system-on-chip” was chosen and realized. In the programmable logical integrated scheme by Microsemi from ProASIC3 family with maximum capacity up to 3M system gates, the computing kernel and all necessary peripherals are created. In this paper we discuss structure, possibilities and resources the service telemetry and control device for “GRIS” space experiment.

Simulation model for a seven-phase BLDCM drive system

NASA Astrophysics Data System (ADS)

Park, Sang-Hoon; Lee, Won-Cheol; Lee, Jung-Hyo; Yu, Jae-Sung; Kim, Gyu-Sik; Won, Chung-Yuen

2007-12-01

BLDC motors have many advantages over brushed DC motors and induction motors. So, BLDC motors extend their application to many industrial fields. In this paper, the digital simulation and modeling of a 7-phase brushless DC motor have been presented. The 14-switch inverter and a 7-phase brushless DC motor drive system are simulated using hysteresis current controller and logic of switching pattern with the Boolean¡s function. Through some simulations, we found that our modeling and analysis of a 7-phase BLDCM with PWM inverter would be helpful for the further studies of the multi-phase BLDCM drive systems.

Small Interactive Image Processing System (SMIPS) system description

NASA Technical Reports Server (NTRS)

Moik, J. G.

1973-01-01

The Small Interactive Image Processing System (SMIPS) operates under control of the IBM-OS/MVT operating system and uses an IBM-2250 model 1 display unit as interactive graphic device. The input language in the form of character strings or attentions from keys and light pen is interpreted and causes processing of built-in image processing functions as well as execution of a variable number of application programs kept on a private disk file. A description of design considerations is given and characteristics, structure and logic flow of SMIPS are summarized. Data management and graphic programming techniques used for the interactive manipulation and display of digital pictures are also discussed.

PSC algorithm description

NASA Technical Reports Server (NTRS)

Nobbs, Steven G.

1995-01-01

An overview of the performance seeking control (PSC) algorithm and details of the important components of the algorithm are given. The onboard propulsion system models, the linear programming optimization, and engine control interface are described. The PSC algorithm receives input from various computers on the aircraft including the digital flight computer, digital engine control, and electronic inlet control. The PSC algorithm contains compact models of the propulsion system including the inlet, engine, and nozzle. The models compute propulsion system parameters, such as inlet drag and fan stall margin, which are not directly measurable in flight. The compact models also compute sensitivities of the propulsion system parameters to change in control variables. The engine model consists of a linear steady state variable model (SSVM) and a nonlinear model. The SSVM is updated with efficiency factors calculated in the engine model update logic, or Kalman filter. The efficiency factors are used to adjust the SSVM to match the actual engine. The propulsion system models are mathematically integrated to form an overall propulsion system model. The propulsion system model is then optimized using a linear programming optimization scheme. The goal of the optimization is determined from the selected PSC mode of operation. The resulting trims are used to compute a new operating point about which the optimization process is repeated. This process is continued until an overall (global) optimum is reached before applying the trims to the controllers.

Field-programmable logic devices with optical input-output.

PubMed

Szymanski, T H; Saint-Laurent, M; Tyan, V; Au, A; Supmonchai, B

2000-02-10

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

Pulse stretcher for narrow pulses

NASA Technical Reports Server (NTRS)

Lindsey, R. S., Jr. (Inventor)

1974-01-01

A pulse stretcher for narrow pulses is presented. The stretcher is composed of an analog section for processing each arriving analog pulse and a digital section with logic for providing command signals to the gates and switches in the analog section.

A new approach of active compliance control via fuzzy logic control for multifingered robot hand

NASA Astrophysics Data System (ADS)

Jamil, M. F. A.; Jalani, J.; Ahmad, A.

2016-07-01

Safety is a vital issue in Human-Robot Interaction (HRI). In order to guarantee safety in HRI, a model reference impedance control can be a very useful approach introducing a compliant control. In particular, this paper establishes a fuzzy logic compliance control (i.e. active compliance control) to reduce impact and forces during physical interaction between humans/objects and robots. Exploiting a virtual mass-spring-damper system allows us to determine a desired compliant level by understanding the behavior of the model reference impedance control. The performance of fuzzy logic compliant control is tested in simulation for a robotic hand known as the RED Hand. The results show that the fuzzy logic is a feasible control approach, particularly to control position and to provide compliant control. In addition, the fuzzy logic control allows us to simplify the controller design process (i.e. avoid complex computation) when dealing with nonlinearities and uncertainties.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Stochastic p -Bits for Invertible Logic

NASA Astrophysics Data System (ADS)

Camsari, Kerem Yunus; Faria, Rafatul; Sutton, Brian M.; Datta, Supriyo

2017-07-01

Conventional semiconductor-based logic and nanomagnet-based memory devices are built out of stable, deterministic units such as standard metal-oxide semiconductor transistors, or nanomagnets with energy barriers in excess of ≈40 - 60 kT . In this paper, we show that unstable, stochastic units, which we call "p -bits," can be interconnected to create robust correlations that implement precise Boolean functions with impressive accuracy, comparable to standard digital circuits. At the same time, they are invertible, a unique property that is absent in standard digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among all possible inputs that are consistent with that output. First, we present a detailed implementation of an invertible gate to bring out the key role of a single three-terminal transistorlike building block to enable the construction of correlated p -bit networks. The results for this specific, CMOS-assisted nanomagnet-based hardware implementation agree well with those from a universal model for p -bits, showing that p -bits need not be magnet based: any three-terminal tunable random bit generator should be suitable. We present a general algorithm for designing a Boltzmann machine (BM) with a symmetric connection matrix [J ] (Ji j=Jj i) that implements a given truth table with p -bits. The [J ] matrices are relatively sparse with a few unique weights for convenient hardware implementation. We then show how BM full adders can be interconnected in a partially directed manner (Ji j≠Jj i) to implement large logic operations such as 32-bit binary addition. Hundreds of stochastic p -bits get precisely correlated such that the correct answer out of 233 (≈8 ×1 09) possibilities can be extracted by looking at the statistical mode or majority vote of a number of time samples. With perfect directivity (Jj i=0 ) a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case logical invertibility is largely preserved. This combination of digital accuracy and logical invertibility is enabled by the hybrid design that uses bidirectional BM units to construct circuits with partially directed interunit connections. We establish this key result with extensive examples including a 4-bit multiplier which in inverted mode functions as a factorizer.

Brain training for silver gamers: effects of age and game form on effectiveness, efficiency, self-assessment, and gameplay experience.

PubMed

Nacke, Lennart E; Nacke, Anne; Lindley, Craig A

2009-10-01

In recent years, an aging demographic majority in the Western world has come to the attention of the game industry. The recently released "brain-training" games target this population, and research investigating gameplay experience of the elderly using this game form is lacking. This study employs a 2 x 2 mixed factorial design (age group: young and old x game form: paper and Nintendo DS) to investigate effects of age and game form on usability, self-assessment, and gameplay experience in a supervised field study. Effectiveness was evaluated in task completion time, efficiency as error rate, together with self-assessment measures (arousal, pleasure, dominance) and game experience (challenge, flow, competence, tension, positive and negative affect). Results indicate players, regardless of age, are more effective and efficient using pen-and-paper than using a Nintendo DS console. However, the game is more arousing and induces a heightened sense of flow in digital form for gamers of all ages. Logic problem-solving challenges within digital games may be associated with positive feelings for the elderly but with negative feelings for the young. Thus, digital logic-training games may provide positive gameplay experience for an aging Western civilization.

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Digital Synchronizer without Metastability

NASA Technical Reports Server (NTRS)

Simle, Robert M.; Cavazos, Jose A.

2009-01-01

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Virtual reality simulation of fuzzy-logic control during underwater dynamic positioning

NASA Astrophysics Data System (ADS)

Thekkedan, Midhin Das; Chin, Cheng Siong; Woo, Wai Lok

2015-03-01

In this paper, graphical-user-interface (GUI) software for simulation and fuzzy-logic control of a remotely operated vehicle (ROV) using MATLAB™ GUI Designing Environment is proposed. The proposed ROV's GUI platform allows the controller such as fuzzy-logic control systems design to be compared with other controllers such as proportional-integral-derivative (PID) and sliding-mode controller (SMC) systematically and interactively. External disturbance such as sea current can be added to improve the modelling in actual underwater environment. The simulated results showed the position responses of the fuzzy-logic control exhibit reasonable performance under the sea current disturbance.

Short circuit protection for a power distribution system

NASA Technical Reports Server (NTRS)

Owen, J. R., III

1969-01-01

Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

Maximizing Accessibility to Spatially Referenced Digital Data.

ERIC Educational Resources Information Center

Hunt, Li; Joselyn, Mark

1995-01-01

Discusses some widely available spatially referenced datasets, including raster and vector datasets. Strategies for improving accessibility include: acquisition of data in a software-dependent format; reorganization of data into logical geographic units; acquisition of intelligent retrieval software; improving computer hardware; and intelligent…

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

PubMed Central

Castillo, E.; Morales, D. P.; García, A.; Parrilla, L.; Todorovich, E.; Meyer-Baese, U.

2015-01-01

HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time. PMID:25861681

A Web application for the management of clinical workflow in image‐guided and adaptive proton therapy for prostate cancer treatments

PubMed Central

Boes, Peter; Ho, Meng Wei; Li, Zuofeng

2015-01-01

Image‐guided radiotherapy (IGRT), based on radiopaque markers placed in the prostate gland, was used for proton therapy of prostate patients. Orthogonal X‐rays and the IBA Digital Image Positioning System (DIPS) were used for setup correction prior to treatment and were repeated after treatment delivery. Following a rationale for margin estimates similar to that of van Herk,(1) the daily post‐treatment DIPS data were analyzed to determine if an adaptive radiotherapy plan was necessary. A Web application using ASP.NET MVC5, Entity Framework, and an SQL database was designed to automate this process. The designed features included state‐of‐the‐art Web technologies, a domain model closely matching the workflow, a database‐supporting concurrency and data mining, access to the DIPS database, secured user access and roles management, and graphing and analysis tools. The Model‐View‐Controller (MVC) paradigm allowed clean domain logic, unit testing, and extensibility. Client‐side technologies, such as jQuery, jQuery Plug‐ins, and Ajax, were adopted to achieve a rich user environment and fast response. Data models included patients, staff, treatment fields and records, correction vectors, DIPS images, and association logics. Data entry, analysis, workflow logics, and notifications were implemented. The system effectively modeled the clinical workflow and IGRT process. PACS number: 87 PMID:26103504

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Stroboscope Controller for Imaging Helicopter Rotors

NASA Technical Reports Server (NTRS)

Jensen, Scott; Marmie, John; Mai, Nghia

2004-01-01

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

The GS (genetic selection) Principle.

PubMed

Abel, David L

2009-01-01

The GS (Genetic Selection) Principle states that biological selection must occur at the nucleotide-sequencing molecular-genetic level of 3'5' phosphodiester bond formation. After-the-fact differential survival and reproduction of already-living phenotypic organisms (ordinary natural selection) does not explain polynucleotide prescription and coding. All life depends upon literal genetic algorithms. Even epigenetic and "genomic" factors such as regulation by DNA methylation, histone proteins and microRNAs are ultimately instructed by prior linear digital programming. Biological control requires selection of particular configurable switch-settings to achieve potential function. This occurs largely at the level of nucleotide selection, prior to the realization of any integrated biofunction. Each selection of a nucleotide corresponds to the setting of two formal binary logic gates. The setting of these switches only later determines folding and binding function through minimum-free-energy sinks. These sinks are determined by the primary structure of both the protein itself and the independently prescribed sequencing of chaperones. The GS Principle distinguishes selection of existing function (natural selection) from selection for potential function (formal selection at decision nodes, logic gates and configurable switch-settings).

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Superconducting Digital Multiplexers for Sensor Arrays

NASA Technical Reports Server (NTRS)

Kadin, Alan M.; Brock, Darren K.; Gupta, Deepnarayan

2004-01-01

Arrays of cryogenic microbolometers and other cryogenic detectors are being developed for infrared imaging. If the signal from each sensor is amplified, multiplexed, and digitized using superconducting electronics, then this data can be efficiently read out to ambient temperature with a minimum of noise and thermal load. HYPRES is developing an integrated system based on SQUID amplifiers, a high-resolution analog-to-digital converter (ADC) based on RSFQ (rapid single flux quantum) logic, and a clocked RSFQ multiplexer. The ADC and SQUIDs have already been demonstrated for other projects, so this paper will focus on new results of a digital multiplexer. Several test circuits have been fabricated using Nb Josephson technology and are about to be tested at T = 4.2 K, with a more complete prototype in preparation.

A cylindrical SPECT camera with de-centralized readout scheme

NASA Astrophysics Data System (ADS)

Habte, F.; Stenström, P.; Rillbert, A.; Bousselham, A.; Bohm, C.; Larsson, S. A.

2001-09-01

An optimized brain single photon emission computed tomograph (SPECT) camera is being designed at Stockholm University and Karolinska Hospital. The design goal is to achieve high sensitivity, high-count rate and high spatial resolution. The sensitivity is achieved by using a cylindrical crystal, which gives a closed geometry with large solid angles. A de-centralized readout scheme where only a local environment around the light excitation is readout supports high-count rates. The high resolution is achieved by using an optimized crystal configuration. A 12 mm crystal plus 12 mm light guide combination gave an intrinsic spatial resolution better than 3.5 mm (140 keV) in a prototype system. Simulations show that a modified configuration can improve this value. A cylindrical configuration with a rotating collimator significantly simplifies the mechanical design of the gantry. The data acquisition and control system uses early digitization and subsequent digital signal processing to extract timing and amplitude information, and monitors the position of the collimator. The readout system consists of 12 or more modules each based on programmable logic and a digital signal processor. The modules send data to a PC file server-reconstruction engine via a Firewire (IEEE-1394) network.

Optical modulator system

NASA Technical Reports Server (NTRS)

Brand, J.

1972-01-01

The fabrication, test, and delivery of an optical modulator system which will operate with a mode-locked Nd:YAG laser indicating at either 1.06 or 0.53 micrometers is discussed. The delivered hardware operates at data rates up to 400 Mbps and includes a 0.53 micrometer electrooptic modulator, a 1.06 micrometer electrooptic modulator with power supply and signal processing electronics with power supply. The modulators contain solid state drivers which accept digital signals with MECL logic levels, temperature controllers to maintain a stable thermal environment for the modulator crystals, and automatic electronic compensation to maximize the extinction ratio. The modulators use two lithium tantalate crystals cascaded in a double pass configuration. The signal processing electronics include encoding electronics which are capable of digitizing analog signals between the limit of + or - 0.75 volts at a maximum rate of 80 megasamples per second with 5 bit resolution. The digital samples are serialized and made available as a 400 Mbps serial NRZ data source for the modulators. A pseudorandom (PN) generator is also included in the signal processing electronics. This data source generates PN sequences with lengths between 31 bits and 32,767 bits in a serial NRZ format at rates up to 400 Mbps.

MIRAGE: The data acquisition, analysis, and display system

NASA Technical Reports Server (NTRS)

Rosser, Robert S.; Rahman, Hasan H.

1993-01-01

Developed for the NASA Johnson Space Center and Life Sciences Directorate by GE Government Services, the Microcomputer Integrated Real-time Acquisition Ground Equipment (MIRAGE) system is a portable ground support system for Spacelab life sciences experiments. The MIRAGE system can acquire digital or analog data. Digital data may be NRZ-formatted telemetry packets of packets from a network interface. Analog signal are digitized and stored in experimental packet format. Data packets from any acquisition source are archived to a disk as they are received. Meta-parameters are generated from the data packet parameters by applying mathematical and logical operators. Parameters are displayed in text and graphical form or output to analog devices. Experiment data packets may be retransmitted through the network interface. Data stream definition, experiment parameter format, parameter displays, and other variables are configured using spreadsheet database. A database can be developed to support virtually any data packet format. The user interface provides menu- and icon-driven program control. The MIRAGE system can be integrated with other workstations to perform a variety of functions. The generic capabilities, adaptability and ease of use make the MIRAGE a cost-effective solution to many experimental data processing requirements.

FUZZY LOGIC CONTROL OF ELECTRIC MOTORS AND MOTOR DRIVES: FEASIBILITY STUDY

EPA Science Inventory

The report gives results of a study (part 1) of fuzzy logic motor control (FLMC). The study included: 1) reviews of existing applications of fuzzy logic, of motor operation, and of motor control; 2) a description of motor control schemes that can utilize FLMC; 3) selection of a m...

Divide and control: split design of multi-input DNA logic gates.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2015-01-18

Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.

Programmable Logic Controllers.

ERIC Educational Resources Information Center

Insolia, Gerard; Anderson, Kathleen

This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…

77 FR 16919 - Airworthiness Directives; Bombardier, Inc. Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-23

... door from opening. It was found that the existing airstair door pneumatic shut-off valve control logic... Control Logic Change] to prevent the above-mentioned failure conditions. You may obtain further... Off Valve Control Logic Change, in accordance with the Accomplishment Instructions of Bombardier...

Distinguishing between evidence and its explanations in the steering of atomic clocks

NASA Astrophysics Data System (ADS)

Myers, John M.; Hadi Madjid, F.

2014-11-01

Quantum theory reflects within itself a separation of evidence from explanations. This separation leads to a known proof that: (1) no wave function can be determined uniquely by evidence, and (2) any chosen wave function requires a guess reaching beyond logic to things unforeseeable. Chosen wave functions are encoded into computer-mediated feedback essential to atomic clocks, including clocks that step computers through their phases of computation and clocks in space vehicles that supply evidence of signal propagation explained by hypotheses of spacetimes with metric tensor fields. The propagation of logical symbols from one computer to another requires a shared rhythm-like a bucket brigade. Here we show how hypothesized metric tensors, dependent on guesswork, take part in the logical synchronization by which clocks are steered in rate and position toward aiming points that satisfy phase constraints, thereby linking the physics of signal propagation with the sharing of logical symbols among computers. Recognizing the dependence of the phasing of symbol arrivals on guesses about signal propagation transports logical synchronization from the engineering of digital communications to a discipline essential to physics. Within this discipline we begin to explore questions invisible under any concept of time that fails to acknowledge unforeseeable events. In particular, variation of spacetime curvature is shown to limit the bit rate of logical communication.

Characterization of the faulted behavior of digital computers and fault tolerant systems

NASA Technical Reports Server (NTRS)

Bavuso, Salvatore J.; Miner, Paul S.

1989-01-01

A development status evaluation is presented for efforts conducted at NASA-Langley since 1977, toward the characterization of the latent fault in digital fault-tolerant systems. Attention is given to the practical, high speed, generalized gate-level logic system simulator developed, as well as to the validation methodology used for the simulator, on the basis of faultable software and hardware simulations employing a prototype MIL-STD-1750A processor. After validation, latency tests will be performed.

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1993-07-01

Saul Levy, Chun Liew, Masoud Majidi , Donald Smith, and Thomas Stone Final Report for Grant #N00014-90-J-4018 Period Covered: 5/1/90 - 4/30/93 Miles...Logic Arrays," Applied Optics, 27, pp. 1651-1660, (May 1, 1988). [5] Murdocca, M. J., V. Gupta, and M. Majidi , "New Approaches to Digital Optical...Lanzl, F., H.-J. Preuss and G. Wiegelt, eds., Proc. SPIE, vol. 319, Garmisch, Bavaria, pp. 126-127, (1990). Murdocca, M. J., V. Gupta, and M. Majidi

GTEX: An expert system for diagnosing faults in satellite ground stations

NASA Technical Reports Server (NTRS)

Schlegelmilch, Richard F.; Durkin, John; Petrik, Edward J.

1991-01-01

A proof of concept expert system called Ground Terminal Expert (GTEX) was developed at The University of Akron in collaboration with NASA Lewis Research Center. The objective of GTEX is to aid in diagnosing data faults occurring with a digital ground terminal. This strategy can also be applied to the Very Small Aperture Terminal (VSAT) technology. An expert system which detects and diagnoses faults would enhance the performance of the VSAT by improving reliability and reducing maintenance time. GTEX is capable of detecting faults, isolating the cause and recommending appropriate actions. Isolation of faults is completed to board-level modules. A graphical user interface provides control and a medium where data can be requested and cryptic information logically displayed. Interaction with GTEX consists of user responses and input from data files. The use of data files provides a method of simulating dynamic interaction between the digital ground terminal and the expert system. GTEX as described is capable of both improving reliability and reducing the time required for necessary maintenance.

Extravehicular mobility unit thermal simulator

NASA Technical Reports Server (NTRS)

Hixon, C. W.; Phillips, M. A.

1973-01-01

The analytical methods, thermal model, and user's instructions for the SIM bay extravehicular mobility unit (EMU) routine are presented. This digital computer program was developed for detailed thermal performance predictions of the crewman performing a command module extravehicular activity during transearth coast. It accounts for conductive, convective, and radiative heat transfer as well as fluid flow and associated flow control components. The program is a derivative of the Apollo lunar surface EMU digital simulator. It has the operational flexibility to accept card or magnetic tape for both the input data and program logic. Output can be tabular and/or plotted and the mission simulation can be stopped and restarted at the discretion of the user. The program was developed for the NASA-JSC Univac 1108 computer system and several of the capabilities represent utilization of unique features of that system. Analytical methods used in the computer routine are based on finite difference approximations to differential heat and mass balance equations which account for temperature or time dependent thermo-physical properties.

Cosmic Radiation Detection and Observations

NASA Astrophysics Data System (ADS)

Ramirez Chavez, Juan; Troncoso, Maria

Cosmic rays consist of high-energy particles accelerated from remote supernova remnant explosions and travel vast distances throughout the universe. Upon arriving at earth, the majority of these particles ionize gases in the upper atmosphere, while others interact with gas molecules in the troposphere and producing secondary cosmic rays, which are the main focus of this research. To observe these secondary cosmic rays, a detector telescope was designed and equipped with two silicon photomultipliers (SiPMs). Each SiPM is coupled to a bundle of 4 wavelength shifting optical fibers that are embedded inside a plastic scintillator sheet. The SiPM signals were amplified using a fast preamplifier with coincidence between detectors established using a binary logic gate. The coincidence events were recorded with two devices; a digital counter and an Arduino micro-controller. For detailed analysis of the SiPM waveforms, a DRS4 sensory digitizer captured the waveforms for offline analysis with the CERN software package Physics Analysis Workstation in a Linux environment. Results from our experiments would be presented. Hartnell College STEM Internship Program.

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

NASA Technical Reports Server (NTRS)

Lindgren, R. W.; Tarbell, T. D.

1981-01-01

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Optical flip-flops and sequential logic circuits using a liquid crystal light valve

NASA Technical Reports Server (NTRS)

Fatehi, M. T.; Collins, S. A., Jr.; Wasmundt, K. C.

1984-01-01

This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.

GTEX: An expert system for diagnosing faults in satellite ground stations

NASA Astrophysics Data System (ADS)

Schlegelmilch, Richard F.; Durkin, John; Petrik, Edward J.

1991-11-01

A proof of concept expert system called Ground Terminal Expert (GTEX) was developed at The University of Akron in collaboration with NASA Lewis Research Center. The objective of GTEX is to aid in diagnosing data faults occurring with a digital ground terminal. This strategy can also be applied to the Very Small Aperture Terminal (VSAT) technology. An expert system which detects and diagnoses faults would enhance the performance of the VSAT by improving reliability and reducing maintenance time. GTEX is capable of detecting faults, isolating the cause and recommending appropriate actions. Isolation of faults is completed to board-level modules. A graphical user interface provides control and a medium where data can be requested and cryptic information logically displayed. Interaction with GTEX consists of user responses and input from data files. The use of data files provides a method of simulating dynamic interaction between the digital ground terminal and the expert system. GTEX as described is capable of both improving reliability and reducing the time required for necessary maintenance.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Steering the conversation: A linguistic exploration of natural language interactions with a digital assistant during simulated driving.

PubMed

Large, David R; Clark, Leigh; Quandt, Annie; Burnett, Gary; Skrypchuk, Lee

2017-09-01

Given the proliferation of 'intelligent' and 'socially-aware' digital assistants embodying everyday mobile technology - and the undeniable logic that utilising voice-activated controls and interfaces in cars reduces the visual and manual distraction of interacting with in-vehicle devices - it appears inevitable that next generation vehicles will be embodied by digital assistants and utilise spoken language as a method of interaction. From a design perspective, defining the language and interaction style that a digital driving assistant should adopt is contingent on the role that they play within the social fabric and context in which they are situated. We therefore conducted a qualitative, Wizard-of-Oz study to explore how drivers might interact linguistically with a natural language digital driving assistant. Twenty-five participants drove for 10 min in a medium-fidelity driving simulator while interacting with a state-of-the-art, high-functioning, conversational digital driving assistant. All exchanges were transcribed and analysed using recognised linguistic techniques, such as discourse and conversation analysis, normally reserved for interpersonal investigation. Language usage patterns demonstrate that interactions with the digital assistant were fundamentally social in nature, with participants affording the assistant equal social status and high-level cognitive processing capability. For example, participants were polite, actively controlled turn-taking during the conversation, and used back-channelling, fillers and hesitation, as they might in human communication. Furthermore, participants expected the digital assistant to understand and process complex requests mitigated with hedging words and expressions, and peppered with vague language and deictic references requiring shared contextual information and mutual understanding. Findings are presented in six themes which emerged during the analysis - formulating responses; turn-taking; back-channelling, fillers and hesitation; vague language; mitigating requests and politeness and praise. The results can be used to inform the design of future in-vehicle natural language systems, in particular to help manage the tension between designing for an engaging dialogue (important for technology acceptance) and designing for an effective dialogue (important to minimise distraction in a driving context). Copyright © 2017 Elsevier Ltd. All rights reserved.

Testing of the on-board attitude determination and control algorithms for SAMPEX

NASA Technical Reports Server (NTRS)

Mccullough, Jon D.; Flatley, Thomas W.; Henretty, Debra A.; Markley, F. Landis; San, Josephine K.

1993-01-01

Algorithms for on-board attitude determination and control of the Solar, Anomalous, and Magnetospheric Particle Explorer (SAMPEX) have been expanded to include a constant gain Kalman filter for the spacecraft angular momentum, pulse width modulation for the reaction wheel command, an algorithm to avoid pointing the Heavy Ion Large Telescope (HILT) instrument boresight along the spacecraft velocity vector, and the addition of digital sun sensor (DSS) failure detection logic. These improved algorithms were tested in a closed-loop environment for three orbit geometries, one with the sun perpendicular to the orbit plane, and two with the sun near the orbit plane - at Autumnal Equinox and at Winter Solstice. The closed-loop simulator was enhanced and used as a truth model for the control systems' performance evaluation and sensor/actuator contingency analysis. The simulations were performed on a VAX 8830 using a prototype version of the on-board software.

Built-in-test by signature inspection (bitsi)

DOEpatents

Bergeson, Gary C.; Morneau, Richard A.

1991-01-01

A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

Intelligent neural network and fuzzy logic control of industrial and power systems

NASA Astrophysics Data System (ADS)

Kuljaca, Ognjen

The main role played by neural network and fuzzy logic intelligent control algorithms today is to identify and compensate unknown nonlinear system dynamics. There are a number of methods developed, but often the stability analysis of neural network and fuzzy control systems was not provided. This work will meet those problems for the several algorithms. Some more complicated control algorithms included backstepping and adaptive critics will be designed. Nonlinear fuzzy control with nonadaptive fuzzy controllers is also analyzed. An experimental method for determining describing function of SISO fuzzy controller is given. The adaptive neural network tracking controller for an autonomous underwater vehicle is analyzed. A novel stability proof is provided. The implementation of the backstepping neural network controller for the coupled motor drives is described. Analysis and synthesis of adaptive critic neural network control is also provided in the work. Novel tuning laws for the system with action generating neural network and adaptive fuzzy critic are given. Stability proofs are derived for all those control methods. It is shown how these control algorithms and approaches can be used in practical engineering control. Stability proofs are given. Adaptive fuzzy logic control is analyzed. Simulation study is conducted to analyze the behavior of the adaptive fuzzy system on the different environment changes. A novel stability proof for adaptive fuzzy logic systems is given. Also, adaptive elastic fuzzy logic control architecture is described and analyzed. A novel membership function is used for elastic fuzzy logic system. The stability proof is proffered. Adaptive elastic fuzzy logic control is compared with the adaptive nonelastic fuzzy logic control. The work described in this dissertation serves as foundation on which analysis of particular representative industrial systems will be conducted. Also, it gives a good starting point for analysis of learning abilities of adaptive and neural network control systems, as well as for the analysis of the different algorithms such as elastic fuzzy systems.

LSI logic for phase-control rectifiers

NASA Technical Reports Server (NTRS)

Dolland, C.

1980-01-01

Signals for controlling phase-controlled rectifier circuit are generated by combinatorial logic than can be implemented in large-scale integration (LSI). LSI circuit saves space, weight, and assembly time compared to previous controls that employ one-shot multivibrators, latches, and capacitors. LSI logic functions by sensing three phases of ac power source and by comparing actual currents with intended currents.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Programmable Logic Controllers. Teacher Edition.

ERIC Educational Resources Information Center

Rauh, Bob; Kaltwasser, Stan

These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…

Fuzzy and neural control

NASA Technical Reports Server (NTRS)

Berenji, Hamid R.

1992-01-01

Fuzzy logic and neural networks provide new methods for designing control systems. Fuzzy logic controllers do not require a complete analytical model of a dynamic system and can provide knowledge-based heuristic controllers for ill-defined and complex systems. Neural networks can be used for learning control. In this chapter, we discuss hybrid methods using fuzzy logic and neural networks which can start with an approximate control knowledge base and refine it through reinforcement learning.

Automotive Electronics. Teacher Edition (Revised).

ERIC Educational Resources Information Center

Mackert, Howard C.; Heiserman, Russell L.

This learning module addresses computers and their applications in contemporary automobiles. The text provides students with information on automotive microcomputers and hands-on activities that will help them see how semiconductors and digital logic devices fit into the modern repair facility. The module contains nine instructional units that…

Students' Misconceptions about Medium-Scale Integrated Circuits

ERIC Educational Resources Information Center

Herman, G. L.; Loui, M. C.; Zilles, C.

2011-01-01

To improve instruction in computer engineering and computer science, instructors must better understand how their students learn. Unfortunately, little is known about how students learn the fundamental concepts in computing. To investigate student conceptions and misconceptions about digital logic concepts, the authors conducted a qualitative…

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Fuzzy Logic Enhanced Digital PIV Processing Software

NASA Technical Reports Server (NTRS)

Wernet, Mark P.

1999-01-01

Digital Particle Image Velocimetry (DPIV) is an instantaneous, planar velocity measurement technique that is ideally suited for studying transient flow phenomena in high speed turbomachinery. DPIV is being actively used at the NASA Glenn Research Center to study both stable and unstable operating conditions in a high speed centrifugal compressor. Commercial PIV systems are readily available which provide near real time feedback of the PIV image data quality. These commercial systems are well designed to facilitate the expedient acquisition of PIV image data. However, as with any general purpose system, these commercial PIV systems do not meet all of the data processing needs required for PIV image data reduction in our compressor research program. An in-house PIV PROCessing (PIVPROC) code has been developed for reducing PIV data. The PIVPROC software incorporates fuzzy logic data validation for maximum information recovery from PIV image data. PIVPROC enables combined cross-correlation/particle tracking wherein the highest possible spatial resolution velocity measurements are obtained.

Performance of the Versatile Array of Neutron Detectors at Low Energy (VANDLE)

DOE PAGES

Peters, W. A.; Ilyushkin, S.; Madurga, M.; ...

2016-08-26

The Versatile Array of Neutron Detectors at Low Energy (VANDLE) is a new, highly efficient plastic-scintillator array constructed for decay and transfer reaction experimental setups that require neutron detection. The versatile and modular design allows for customizable experimental setups including beta-delayed neutron spectroscopy and (d,n) transfer reactions in normal and inverse kinematics. The neutron energy and prompt-photon discrimination is determined through the time of flight technique. Fully digital data acquisition electronics and integrated triggering logic enables some VANDLE modules to achieve an intrinsic efficiency over 70% for 300-keV neutrons, measured through two different methods. A custom Geant4 simulation models aspectsmore » of the detector array and the experimental setups to determine efficiency and detector response. Lastly, a low detection threshold, due to the trigger logic and digitizing data acquisition, allowed us to measure the light-yield response curve from elastically scattered carbon nuclei inside the scintillating plastic from incident neutrons with kinetic energies below 2 MeV.« less

Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, D.S.; Seong, P.H.

1995-08-01

In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines` logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF themore » proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets.« less

A Simple Memristor Model for Circuit Simulations

NASA Astrophysics Data System (ADS)

Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team

This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

A new design approach to achieve a minimum impulse limit cycle in the presence of significant measurement uncertainties

NASA Technical Reports Server (NTRS)

Martin, M. W.; Kubiak, E. T.

1982-01-01

A new design was developed for the Space Shuttle Transition Phase Digital Autopilot to reduce the impact of large measurement uncertainties in the rate signal during attitude control. The signal source, which was dictated by early computer constraints, is characterized by large quantization, noise, bias, and transport lag which produce a measurement uncertainty larger than the minimum impulse rate change. To ensure convergence to a minimum impulse limit cycle, the design employed bias and transport lag compensation and a switching logic with hysteresis, rate deadzone, and 'walking' switching line. The design background, the rate measurement uncertainties, and the design solution are documented.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

NASA Astrophysics Data System (ADS)

Yang, Jiaqi; Li, Ting; Yu, Mingyuan; Zhang, Shuangshuang; Lin, Fujiang; He, Lin

2017-08-01

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203 μW. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

Studies in optical parallel processing. [All optical and electro-optic approaches

NASA Technical Reports Server (NTRS)

Lee, S. H.

1978-01-01

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

NASA Astrophysics Data System (ADS)

Manikandan, J.; Jayaraman, M.; Jayachandran, M.

2011-02-01

This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Lazarev, Alexander A.; Nikitovich, Diana V.

2017-10-01

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The SMC ADCs based on CL BC and CM opens new prospects for realization of linear and matrix IP and photo-electronic structures with matrix operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers.

Fuzzy Logic Controlled Solar Module for Driving Three- Phase Induction Motor

NASA Astrophysics Data System (ADS)

Afiqah Zainal, Nurul; Sooi Tat, Chan; Ajisman

2016-02-01

Renewable energy produced by solar module gives advantages for generated three- phase induction motor in remote area. But, solar module's ou tput is uncertain and complex. Fuzzy logic controller is one of controllers that can handle non-linear system and maximum power of solar module. Fuzzy logic controller used for Maximum Power Point Tracking (MPPT) technique to control Pulse-Width Modulation (PWM) for switching power electronics circuit. DC-DC boost converter used to boost up photovoltaic voltage to desired output and supply voltage source inverter which controlled by three-phase PWM generated by microcontroller. IGBT switched Voltage source inverter (VSI) produced alternating current (AC) voltage from direct current (DC) source to control speed of three-phase induction motor from boost converter output. Results showed that, the output power of solar module is optimized and controlled by using fuzzy logic controller. Besides that, the three-phase induction motor can be drive and control using VSI switching by the PWM signal generated by the fuzzy logic controller. This concluded that the non-linear system can be controlled and used in driving three-phase induction motor.

Fuzzy logic feedback control for fed-batch enzymatic hydrolysis of lignocellulosic biomass.

PubMed

Tai, Chao; Voltan, Diego S; Keshwani, Deepak R; Meyer, George E; Kuhar, Pankaj S

2016-06-01

A fuzzy logic feedback control system was developed for process monitoring and feeding control in fed-batch enzymatic hydrolysis of a lignocellulosic biomass, dilute acid-pretreated corn stover. Digested glucose from hydrolysis reaction was assigned as input while doser feeding time and speed of pretreated biomass were responses from fuzzy logic control system. Membership functions for these three variables and rule-base were created based on batch hydrolysis data. The system response was first tested in LabVIEW environment then the performance was evaluated through real-time hydrolysis reaction. The feeding operations were determined timely by fuzzy logic control system and efficient responses were shown to plateau phases during hydrolysis. Feeding of proper amount of cellulose and maintaining solids content was well balanced. Fuzzy logic proved to be a robust and effective online feeding control tool for fed-batch enzymatic hydrolysis.

Genetic algorithm based fuzzy control of spacecraft autonomous rendezvous

NASA Technical Reports Server (NTRS)

Karr, C. L.; Freeman, L. M.; Meredith, D. L.

1990-01-01

The U.S. Bureau of Mines is currently investigating ways to combine the control capabilities of fuzzy logic with the learning capabilities of genetic algorithms. Fuzzy logic allows for the uncertainty inherent in most control problems to be incorporated into conventional expert systems. Although fuzzy logic based expert systems have been used successfully for controlling a number of physical systems, the selection of acceptable fuzzy membership functions has generally been a subjective decision. High performance fuzzy membership functions for a fuzzy logic controller that manipulates a mathematical model simulating the autonomous rendezvous of spacecraft are learned using a genetic algorithm, a search technique based on the mechanics of natural genetics. The membership functions learned by the genetic algorithm provide for a more efficient fuzzy logic controller than membership functions selected by the authors for the rendezvous problem. Thus, genetic algorithms are potentially an effective and structured approach for learning fuzzy membership functions.

A Compton suppressed detector multiplicity trigger based digital DAQ for gamma-ray spectroscopy

NASA Astrophysics Data System (ADS)

Das, S.; Samanta, S.; Banik, R.; Bhattacharjee, R.; Basu, K.; Raut, R.; Ghugre, S. S.; Sinha, A. K.; Bhattacharya, S.; Imran, S.; Mukherjee, G.; Bhattacharyya, S.; Goswami, A.; Palit, R.; Tan, H.

2018-06-01

The development of a digitizer based pulse processing and data acquisition system for γ-ray spectroscopy with large detector arrays is presented. The system is based on 250 MHz 12-bit digitizers, and is triggered by a user chosen multiplicity of Compton suppressed detectors. The logic for trigger generation is similar to the one practised for analog (NIM/CAMAC) pulse processing electronics, while retaining the fast processing merits of the digitizer system. Codes for reduction of data acquired from the system have also been developed. The system has been tested with offline studies using radioactive sources as well as in the in-beam experiments with an array of Compton suppressed Clover detectors. The results obtained therefrom validate its use in spectroscopic efforts for nuclear structure investigations.

Active quench and reset integrated circuit with novel hold-off time control logic for Geiger-mode avalanche photodiodes.

PubMed

Deng, Shijie; Morrison, Alan P

2012-09-15

This Letter presents an active quench-and-reset circuit for Geiger-mode avalanche photodiodes (GM-APDs). The integrated circuit was fabricated using a conventional 0.35 μm complementary metal oxide semiconductor process. Experimental results show that the circuit is capable of linearly setting the hold-off time from several nanoseconds to microseconds with a resolution of 6.5 ns. This allows the selection of the optimal afterpulse-free hold-off time for the GM-APD via external digital inputs or additional signal processing circuitry. Moreover, this circuit resets the APD automatically following the end of the hold-off period, thus simplifying the control for the end user. Results also show that a minimum dead time of 28.4 ns is achieved, demonstrating a saturated photon-counting rate of 35.2 Mcounts/s.

The new MSFC Solar vector magnetograph. Center director's discretionary fund

NASA Technical Reports Server (NTRS)

Hagyard, M. J.; West, E. A.; Cumings, N. P.

1984-01-01

The unique MSFC solar vector magnetograph allows measurements of all three components of the Sun's photospheric magnetic field over a wide field-of-view with spatial resolution determined by a 2.7 x 2.7 arc second pixel size. This system underwent extensive modifications to improve its sensitivity and temporal response. The modifications included replacing an SEC vidicon detector with a solid-state CCD camera; replacing the original digital logic circuitry with an electronic controller and a computer to provide complete, programmable control over the entire operation of the magnetograph; and installing a new polarimeter which consists of a single electro-optical modulator coupled with interchangeable waveplates mounted on a rotating assembly. The system is described and results of calibrations and tests are presented. Initial observations of solar magnetic fields with the new magnetograph are presented.

Boolean integral calculus for digital systems

NASA Technical Reports Server (NTRS)

Tucker, J. H.; Tapia, M. A.; Bennett, A. W.

1985-01-01

The concept of Boolean integration is introduced and developed. When the changes in a desired function are specified in terms of changes in its arguments, then ways of 'integrating' (i.e., realizing) the function, if it exists, are presented. Boolean integral calculus has applications in design of logic circuits.

Data system for multiplexed water-current meters

NASA Technical Reports Server (NTRS)

Ramsey, C. R.

1977-01-01

Flow rates at 32 flood plain locations are measured simultaneously by single digital logic unit with high noise immunity. Water flowing through pygmy current meters rotates element that closes electrical contact once every resolution, so flow rate is measured by counting number of closures in time interval.

PLATO--AN AUTOMATED TEACHING DEVICE.

ERIC Educational Resources Information Center

BITZER, D.; AND OTHERS

PLATO (PROGRAMED LOGIC FOR AUTOMATIC TEACHING OPERATION) IS A DEVICE FOR TEACHING A NUMBER OF STUDENTS INDIVIDUALLY BY MEANS OF A SINGLE, CENTRAL PURPOSE, DIGITAL COMPUTER. THE GENERAL ORGANIZATION OF EQUIPMENT CONSISTS OF A KEYSET FOR STUDENT RESPONSES, THE COMPUTER, STORAGE DEVICE (ELECTRIC BLACKBOARD), SLIDE SELECTOR (ELECTRICAL BOOK), AND TV…

A Psychometric Evaluation of the Digital Logic Concept Inventory

ERIC Educational Resources Information Center

Herman, Geoffrey L.; Zilles, Craig; Loui, Michael C.

2014-01-01

Concept inventories hold tremendous promise for promoting the rigorous evaluation of teaching methods that might remedy common student misconceptions and promote deep learning. The measurements from concept inventories can be trusted only if the concept inventories are evaluated both by expert feedback and statistical scrutiny (psychometric…

CEDS Addresses: Rubric Elements

ERIC Educational Resources Information Center

US Department of Education, 2015

2015-01-01

Common Education Data Standards (CEDS) Version 4 introduced a common data vocabulary for defining rubrics in a data system. The CEDS elements support digital representations of both holistic and analytic rubrics. This document shares examples of holistic and analytic project rubrics, available CEDS Connections, and a logical model showing the…

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

An Amazing Algorithm

ERIC Educational Resources Information Center

Snapp, Robert R.; Neumann, Maureen D.

2015-01-01

The rapid growth of digital technology, including the worldwide adoption of mobile and embedded computers, places new demands on K-grade 12 educators and their students. Young people should have an opportunity to learn the technical knowledge of computer science (e.g., computer programming, mathematical logic, and discrete mathematics) in order to…

The Application of LOGO! in Control System of a Transmission and Sorting Mechanism

NASA Astrophysics Data System (ADS)

Liu, Jian; Lv, Yuan-Jun

Logic programming of general logic control module LOGO! has been recommended the application in transmission and sorting mechanism. First, the structure and operating principle of the mechanism had been introduced. Then the pneumatic loop of the mechanism had been plotted in the software of FluidSIM-P. At last, pneumatic loop and motors had been control by LOGO!, which makes the control process simple and clear instead of the complicated control of ordinary relay. LOGO! can achieve the complicated interlock control composed of inter relays and time relays. In the control process, the logic control function of LOGO! is fully used to logic programming so that the system realizes the control of air cylinder and motor. It is reliable and adjustable mechanism after application.

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

NASA Astrophysics Data System (ADS)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Evolution of Scientific and Technical Information Distribution

NASA Technical Reports Server (NTRS)

Esler, Sandra; Nelson, Michael L.

1998-01-01

World Wide Web (WWW) and related information technologies are transforming the distribution of scientific and technical information (STI). We examine 11 recent, functioning digital libraries focusing on the distribution of STI publications, including journal articles, conference papers, and technical reports. We introduce 4 main categories of digital library projects: based on the architecture (distributed vs. centralized) and the contributor (traditional publisher vs. authoring individual/organization). Many digital library prototypes merely automate existing publishing practices or focus solely on the digitization of the publishing cycle output, not sampling and capturing elements of the input. Still others do not consider for distribution the large body of "gray literature." We address these deficiencies in the current model of STI exchange by suggesting methods for expanding the scope and target of digital libraries by focusing on a greater source of technical publications and using "buckets," an object-oriented construct for grouping logically related information objects, to include holdings other than technical publications.

75 FR 39798 - Airworthiness Directives; Bombardier, Inc. Model DHC-8-400, -401, and -402 Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-13

.... 1 hydraulic system. In one case, the hydraulic system control logic did not shut down the PTU and... unit (PTU) control logic, including the provision of automatic PTU shutdown in the event of loss of... one case, the hydraulic system control logic did not shut down the PTU and the overspeed condition...

UML activity diagrams in requirements specification of logic controllers

NASA Astrophysics Data System (ADS)

Grobelna, Iwona; Grobelny, Michał

2015-12-01

Logic controller specification can be prepared using various techniques. One of them is the wide understandable and user-friendly UML language and its activity diagrams. Using formal methods during the design phase increases the assurance that implemented system meets the project requirements. In the approach we use the model checking technique to formally verify a specification against user-defined behavioral requirements. The properties are usually defined as temporal logic formulas. In the paper we propose to use UML activity diagrams in requirements definition and then to formalize them as temporal logic formulas. As a result, UML activity diagrams can be used both for logic controller specification and for requirements definition, what simplifies the specification and verification process.

Facilitating Autonomy and Creativity in Second Language Learning through Cyber-Tasks, Hyperlinks and Net-Surfing

ERIC Educational Resources Information Center

Akinwamide, T. K.; Adedara, O. G.

2012-01-01

The digitalization of academic interactions and collaborations in this present technologically conscious world is making collaborations between technology and pedagogy in the teaching and learning processes to display logical and systematic reasoning rather than the usual stereotyped informed decisions. This simply means, pedagogically, learning…

Preservation Health Check: Monitoring Threats to Digital Repository Content

ERIC Educational Resources Information Center

Kool, Wouter; van der Werf, Titia; Lavoie, Brian

2014-01-01

The Preservation Health Check (PHC) project, undertaken as a joint effort by Open Planets Foundation (OPF) and OCLC Research, aims to evaluate the usefulness of the preservation metadata created and maintained by operational repositories for assessing basic preservation properties. The PHC project seeks to develop an implementable logic to support…

Computers in Electrical Engineering Education at Virginia Polytechnic Institute.

ERIC Educational Resources Information Center

Bennett, A. Wayne

1982-01-01

Discusses use of computers in Electrical Engineering (EE) at Virginia Polytechnic Institute. Topics include: departmental background, level of computing power using large scale systems, mini and microcomputers, use of digital logic trainers and analog/hybrid computers, comments on integrating computers into EE curricula, and computer use in…

Highest integration in microelectronics: Development of digital ASICs for PARS3-LR

NASA Astrophysics Data System (ADS)

Scholler, Peter; Vonlutz, Rainer

Essential electronic system components by PARS3-LR, show high requirements in calculation power, power consumption and reliability, by immediately increasing integration thicknesses. These problems are solved by using integrated circuits, developed by LSI LOGIC, that uses the technical and economic advantages of this leading edge technology.

Noncollinear generation of optical spatiotemporal solitons and application to ultrafast digital logic

NASA Astrophysics Data System (ADS)

Liu, Xiang; Beckwitt, Kale; Wise, Frank

2000-05-01

We demonstrate theoretically and experimentally that spatiotemporal solitons can be generated through noncollinear second-harmonic generation. The resulting Y geometry could be used to implement an optical AND gate with ultrafast, high-contrast operation but without sensitivity to the phases of the input pulses.

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

Robust Fuzzy Logic Stabilization with Disturbance Elimination

PubMed Central

Danapalasingam, Kumeresan A.

2014-01-01

A robust fuzzy logic controller is proposed for stabilization and disturbance rejection in nonlinear control systems of a particular type. The dynamic feedback controller is designed as a combination of a control law that compensates for nonlinear terms in a control system and a dynamic fuzzy logic controller that addresses unknown model uncertainties and an unmeasured disturbance. Since it is challenging to derive a highly accurate mathematical model, the proposed controller requires only nominal functions of a control system. In this paper, a mathematical derivation is carried out to prove that the controller is able to achieve asymptotic stability by processing state measurements. Robustness here refers to the ability of the controller to asymptotically steer the state vector towards the origin in the presence of model uncertainties and a disturbance input. Simulation results of the robust fuzzy logic controller application in a magnetic levitation system demonstrate the feasibility of the control design. PMID:25177713

Automatic ranging circuit for a digital panel meter

DOEpatents

Mueller, Theodore R.; Ross, Harley H.

1976-01-01

This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.

Advanced reliability modeling of fault-tolerant computer-based systems

NASA Technical Reports Server (NTRS)

Bavuso, S. J.

1982-01-01

Two methodologies for the reliability assessment of fault tolerant digital computer based systems are discussed. The computer-aided reliability estimation 3 (CARE 3) and gate logic software simulation (GLOSS) are assessment technologies that were developed to mitigate a serious weakness in the design and evaluation process of ultrareliable digital systems. The weak link is based on the unavailability of a sufficiently powerful modeling technique for comparing the stochastic attributes of one system against others. Some of the more interesting attributes are reliability, system survival, safety, and mission success.

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Zhou, Zhiquing

1999-01-01

A high speed, digitally based, signal processing system which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system livetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired.

Molecular computational elements encode large populations of small objects

NASA Astrophysics Data System (ADS)

Prasanna de Silva, A.; James, Mark R.; McKinney, Bernadine O. F.; Pears, David A.; Weir, Sheenagh M.

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1nm) and large `on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100μm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a `wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

Molecular computational elements encode large populations of small objects.

PubMed

de Silva, A Prasanna; James, Mark R; McKinney, Bernadine O F; Pears, David A; Weir, Sheenagh M

2006-10-01

Since the introduction of molecular computation, experimental molecular computational elements have grown to encompass small-scale integration, arithmetic and games, among others. However, the need for a practical application has been pressing. Here we present molecular computational identification (MCID), a demonstration that molecular logic and computation can be applied to a widely relevant issue. Examples of populations that need encoding in the microscopic world are cells in diagnostics or beads in combinatorial chemistry (tags). Taking advantage of the small size (about 1 nm) and large 'on/off' output ratios of molecular logic gates and using the great variety of logic types, input chemical combinations, switching thresholds and even gate arrays in addition to colours, we produce unique identifiers for members of populations of small polymer beads (about 100 microm) used for synthesis of combinatorial libraries. Many millions of distinguishable tags become available. This method should be extensible to far smaller objects, with the only requirement being a 'wash and watch' protocol. Our focus on converting molecular science into technology concerning analog sensors, turns to digital logic devices in the present work.

Fuzzy logic controllers: A knowledge-based system perspective

NASA Technical Reports Server (NTRS)

Bonissone, Piero P.

1993-01-01

Over the last few years we have seen an increasing number of applications of Fuzzy Logic Controllers. These applications range from the development of auto-focus cameras, to the control of subway trains, cranes, automobile subsystems (automatic transmissions), domestic appliances, and various consumer electronic products. In summary, we consider a Fuzzy Logic Controller to be a high level language with its local semantics, interpreter, and compiler, which enables us to quickly synthesize non-linear controllers for dynamic systems.

An Embedded Reconfigurable Logic Module

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

2002-01-01

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulle; Robinson, Daryl C.; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

75 FR 20787 - Airworthiness Directives; Bombardier, Inc. Model DHC-8-400, -401, and -402 Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-21

... increased fluid flow within the No. 1 hydraulic system. In one case, the hydraulic system control logic did... (PTU) control logic, including the provision of automatic PTU shutdown in the event of loss of fluid in... one case, the hydraulic system control logic did not shut down the PTU and the overspeed condition...

Fuzzy logic applications to control engineering

NASA Astrophysics Data System (ADS)

Langari, Reza

1993-12-01

This paper presents the results of a project presently under way at Texas A&M which focuses on the use of fuzzy logic in integrated control of manufacturing systems. The specific problems investigated here include diagnosis of critical tool wear in machining of metals via a neuro-fuzzy algorithm, as well as compensation of friction in mechanical positioning systems via an adaptive fuzzy logic algorithm. The results indicate that fuzzy logic in conjunction with conventional algorithmic based approaches or neural nets can prove useful in dealing with the intricacies of control/monitoring of manufacturing systems and can potentially play an active role in multi-modal integrated control systems of the future.

Gate-Controlled BP-WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.

PubMed

Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing

2017-06-01

p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe 2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe 2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe 2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

New mode switching algorithm for the JPL 70-meter antenna servo controller

NASA Technical Reports Server (NTRS)

Nickerson, J. A.

1988-01-01

The design of control mode switching algorithms and logic for JPL's 70 m antenna servo controller are described. The old control mode switching logic was reviewed and perturbation problems were identified. Design approaches for mode switching are presented and the final design is described. Simulations used to compare old and new mode switching algorithms and logic show that the new mode switching techniques will significantly reduce perturbation problems.

Directional passability and quadratic steering logic for pyramid-type single gimbal control moment gyros

NASA Astrophysics Data System (ADS)

Yamada, Katsuhiko; Jikuya, Ichiro

2014-09-01

Singularity analysis and the steering logic of pyramid-type single gimbal control moment gyros are studied. First, a new concept of directional passability in a specified direction is introduced to investigate the structure of an elliptic singular surface. The differences between passability and directional passability are discussed in detail and are visualized for 0H, 2H, and 4H singular surfaces. Second, quadratic steering logic (QSL), a new steering logic for passing the singular surface, is investigated. The algorithm is based on the quadratic constrained quadratic optimization problem and is reduced to the Newton method by using Gröbner bases. The proposed steering logic is demonstrated through numerical simulations for both constant torque maneuvering examples and attitude control examples.

A fast and low-cost genotyping method for hepatitis B virus based on pattern recognition in point-of-care settings

PubMed Central

Qiu, Xianbo; Song, Liuwei; Yang, Shuo; Guo, Meng; Yuan, Quan; Ge, Shengxiang; Min, Xiaoping; Xia, Ningshao

2016-01-01

A fast and low-cost method for HBV genotyping especially for genotypes A, B, C and D was developed and tested. A classifier was used to detect and analyze a one-step immunoassay lateral flow strip functionalized with genotype-specific monoclonal antibodies (mAbs) on multiple capture lines in the form of pattern recognition for point-of-care (POC) diagnostics. The fluorescent signals from the capture lines and the background of the strip were collected via multiple optical channels in parallel. A digital HBV genotyping model, whose inputs are the fluorescent signals and outputs are a group of genotype-specific digital binary codes (0/1), was developed based on the HBV genotyping strategy. Meanwhile, a companion decoding table was established to cover all possible pairing cases between the states of a group of genotype-specific digital binary codes and the HBV genotyping results. A logical analyzing module was constructed to process the detected signals in parallel without program control, and its outputs were used to drive a set of LED indicators, which determine the HBV genotype. Comparing to the nucleic acid analysis to HBV viruses, much faster HBV genotyping with significantly lower cost can be obtained with the developed method. PMID:27306485

Hardware realization of an SVM algorithm implemented in FPGAs

NASA Astrophysics Data System (ADS)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Scalable hybrid computation with spikes.

PubMed

Sarpeshkar, Rahul; O'Halloran, Micah

2002-09-01

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.

Lamp control using the principles of mathematical logic

NASA Astrophysics Data System (ADS)

Yudianto, E.; Firmansyah, F. F.; Akbar, P. S. B. S.; Nisyak, R.; Maudi, F. A.; Saputri, A. N.

2018-03-01

Along with the rapid development of technology, there are so many innovations on tools that can facilitate human’s work, one of which is a remote lamp controller. This light controller can provide convenience and comfort for people in turning on or off lights, especially they are traveling. The way remote light controller is used applies the principle of mathematical logic, particularly biimplication. The principle of mathematical logic (biimplication) on this light controller is applied to GSM module (gprs) and SMS.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

An automated system for liquid-liquid extraction in monosegmented flow analysis

PubMed Central

Facchin, Ileana; Pasquini, Celio

1997-01-01

An automated system to perform liquid-liquid extraction in monosegmented flow analysis is described. The system is controlled by a microcomputer that can track the localization of the aqueous monosegmented sample in the manifold. Optical switches are employed to sense the gas-liquid interface of the air bubbles that define the monosegment. The logical level changes, generated by the switches, are flagged by the computer through a home-made interface that also contains the analogue-to-digital converter for signal acquisition. The sequence of operations, necessary for a single extraction or for concentration of the analyte in the organic phase, is triggered by these logical transitions. The system was evaluated for extraction of Cd(II), Cu(II) and Zn(II) and concentration of Cd(II) from aqueous solutions at pH 9.9 (NH3/NH4Cl buffer) into chloroform containing PAN (1-(2-pyridylazo)-2-naphthol) . The results show a mean repeatability of 3% (rsd) for a 2.0 mg l-1 Cd(II) solution and a linear increase of the concentration factor for a 0.5mg l-1 Cd(II) solution observed for up to nine extraction cycles. PMID:18924792

Deep Space Network Antenna Logic Controller

NASA Technical Reports Server (NTRS)

Ahlstrom, Harlow; Morgan, Scott; Hames, Peter; Strain, Martha; Owen, Christopher; Shimizu, Kenneth; Wilson, Karen; Shaller, David; Doktomomtaz, Said; Leung, Patrick

2007-01-01

The Antenna Logic Controller (ALC) software controls and monitors the motion control equipment of the 4,000-metric-ton structure of the Deep Space Network 70-meter antenna. This program coordinates the control of 42 hydraulic pumps, while monitoring several interlocks for personnel and equipment safety. Remote operation of the ALC runs via the Antenna Monitor & Control (AMC) computer, which orchestrates the tracking functions of the entire antenna. This software provides a graphical user interface for local control, monitoring, and identification of faults as well as, at a high level, providing for the digital control of the axis brakes so that the servo of the AMC may control the motion of the antenna. Specific functions of the ALC also include routines for startup in cold weather, controlled shutdown for both normal and fault situations, and pump switching on failure. The increased monitoring, the ability to trend key performance characteristics, the improved fault detection and recovery, the centralization of all control at a single panel, and the simplification of the user interface have all reduced the required workforce to run 70-meter antennas. The ALC also increases the antenna availability by reducing the time required to start up the antenna, to diagnose faults, and by providing additional insight into the performance of key parameters that aid in preventive maintenance to avoid key element failure. The ALC User Display (AUD) is a graphical user interface with hierarchical display structure, which provides high-level status information to the operation of the ALC, as well as detailed information for virtually all aspects of the ALC via drill-down displays. The operational status of an item, be it a function or assembly, is shown in the higher-level display. By pressing the item on the display screen, a new screen opens to show more detail of the function/assembly. Navigation tools and the map button allow immediate access to all screens.

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Home Diabetes Monitoring through Touch-Tone Computer Data Entry and Voice Synthesizer Response

PubMed Central

Arbogast, James G.; Dodrill, William H.

1984-01-01

Current studies suggest that the control of Diabetes mellitus can be improved with home monitoring of blood sugars. Voice synthesizers and recent technology, allowing decoding of Touch-Tone® pulses into their digital equivalents, make it possible for diabetics with no more sophisticated equipment than a Touch-Tone® telephone to enter their blood sugars directly into a medical office computer. A working prototype that can provide physicians with timely, logically oriented information about their diabetics is discussed along with plans to expand this concept into giving the patients uncomplicated therapeutic advice without the need for a direct patient/physician interaction. The potential impact on health care costs and the management of other chronic diseases is presented.

Implant for in-vivo parameter monitoring, processing and transmitting

DOEpatents

Ericson, Milton N [Knoxville, TN; McKnight, Timothy E [Greenback, TN; Smith, Stephen F [London, TN; Hylton, James O [Clinton, TN

2009-11-24

The present invention relates to a completely implantable intracranial pressure monitor, which can couple to existing fluid shunting systems as well as other internal monitoring probes. The implant sensor produces an analog data signal which is then converted electronically to a digital pulse by generation of a spreading code signal and then transmitted to a location outside the patient by a radio-frequency transmitter to an external receiver. The implanted device can receive power from an internal source as well as an inductive external source. Remote control of the implant is also provided by a control receiver which passes commands from an external source to the implant system logic. Alarm parameters can be programmed into the device which are capable of producing an audible or visual alarm signal. The utility of the monitor can be greatly expanded by using multiple pressure sensors simultaneously or by combining sensors of various physiological types.

Implantable device for in-vivo intracranial and cerebrospinal fluid pressure monitoring

DOEpatents

Ericson, Milton N.; McKnight, Timothy E.; Smith, Stephen F.; Hylton, James O.

2003-01-01

The present invention relates to a completely implantable intracranial pressure monitor, which can couple to existing fluid shunting systems as well as other internal monitoring probes. The implant sensor produces an analog data signal which is then converted electronically to a digital pulse by generation of a spreading code signal and then transmitted to a location outside the patient by a radio-frequency transmitter to an external receiver. The implanted device can receive power from an internal source as well as an inductive external source. Remote control of the implant is also provided by a control receiver which passes commands from an external source to the implant system logic. Alarm parameters can be programmed into the device which are capable of producing an audible or visual alarm signal. The utility of the monitor can be greatly expanded by using multiple pressure sensors simultaneously or by combining sensors of various physiological types.

Origami mechanologic.

PubMed

Treml, Benjamin; Gillman, Andrew; Buskohl, Philip; Vaia, Richard

2018-06-18

Robots autonomously interact with their environment through a continual sense-decide-respond control loop. Most commonly, the decide step occurs in a central processing unit; however, the stiffness mismatch between rigid electronics and the compliant bodies of soft robots can impede integration of these systems. We develop a framework for programmable mechanical computation embedded into the structure of soft robots that can augment conventional digital electronic control schemes. Using an origami waterbomb as an experimental platform, we demonstrate a 1-bit mechanical storage device that writes, erases, and rewrites itself in response to a time-varying environmental signal. Further, we show that mechanical coupling between connected origami units can be used to program the behavior of a mechanical bit, produce logic gates such as AND, OR, and three input majority gates, and transmit signals between mechanologic gates. Embedded mechanologic provides a route to add autonomy and intelligence in soft robots and machines. Copyright © 2018 the Author(s). Published by PNAS.

Differential comparator cirucit

DOEpatents

Hickling, Ronald M.

1996-01-01

A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application includes a plurality of differential comparators and a plurality of offset voltage generators. Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage. The number of offset voltage generators required in an ADC application can be reduced by a factor of approximately two by applying the offset voltage from each offset voltage generator to two comparators with opposite logical sense such that positive and negative offset voltages are produced by each offset voltage generator.

A Functional Description of a Digital Flight Test System for Navigation and Guidance Research in the Terminal Area

NASA Technical Reports Server (NTRS)

Hegarty, D. M.

1974-01-01

A guidance, navigation, and control system, the Simulated Shuttle Flight Test System (SS-FTS), when interfaced with existing aircraft systems, provides a research facility for studying concepts for landing the space shuttle orbiter and conventional jet aircraft. The SS-FTS, which includes a general-purpose computer, performs all computations for precisely following a prescribed approach trajectory while properly managing the vehicle energy to allow safe arrival at the runway and landing within prescribed dispersions. The system contains hardware and software provisions for navigation with several combinations of possible navigation aids that have been suggested for the shuttle. The SS-FTS can be reconfigured to study different guidance and navigation concepts by changing only the computer software, and adapted to receive different radio navigation information through minimum hardware changes. All control laws, logic, and mode interlocks reside solely in the computer software.

Assessing Cultural Validity in Standardized Tests in STEM Education

ERIC Educational Resources Information Center

Gassant, Lunes

2013-01-01

This quantitative ex post facto study examined how race and gender, as elements of culture, influence the development of common misconceptions among STEM students. Primary data came from a standardized test: the Digital Logic Concept Inventory (DLCI) developed by Drs. Geoffrey L. Herman, Michael C. Louis, and Craig Zilles from the University of…

From Prosumer to Prodesigner: Participatory News Consumption

ERIC Educational Resources Information Center

Hernández-Serrano, María-José; Renés-Arellano, Paula; Graham, Gary; Greenhill, Anita

2017-01-01

New democratic participation forms and collaborative productions of diverse audiences have emerged as a result of digital innovations in the online access to and consumption of news. The aim of this paper is to propose a conceptual framework based on the possibilities of Web 2.0. outlining the construction of a "social logic," which…

ASIC For Complex Fixed-Point Arithmetic

NASA Technical Reports Server (NTRS)

Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

1995-01-01

Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

A Descriptive Study Examining the Impact of Digital Writing Environments on Communication and Mathematical Reasoning for Students with Learning Disabilities

ERIC Educational Resources Information Center

Huscroft-D'Angelo, Jacqueline; Higgins, Kristina N.; Crawford, Lindy L.

2014-01-01

Proficiency in mathematics, including mathematical reasoning skills, requires students to communicate their mathematical thinking. Mathematical reasoning involves making sense of mathematical concepts in a logical way to form conclusions or judgments, and is often underdeveloped in students with learning disabilities. Technology-based environments…

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Digital logic optimization using selection operators

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

Relationships between behavioral syndromes and cognitive domains in Alzheimer disease: the impact of mood and psychosis.

PubMed

Koppel, Jeremy; Goldberg, Terry E; Gordon, Marc L; Huey, Edward; Davies, Peter; Keehlisen, Linda; Huet, Sara; Christen, Erica; Greenwald, Blaine S

2012-11-01

Behavioral disturbances occur in nearly all Alzheimer disease (AD) patients together with an array of cognitive impairments. Prior investigations have failed to demonstrate specific associations between them, suggesting an independent, rather than shared, pathophysiology. The objective of this study was to reexamine this issue using an extensive cognitive battery together with a sensitive neurobehavioral and functional rating scale to correlate behavioral syndromes and cognitive domains across the spectrum of impairment in dementia. Cross-sectional study of comprehensive cognitive and behavioral ratings in subjects with AD and mild cognitive impairment. Memory disorders research center. Fifty subjects with AD and 26 subjects with mild cognitive impairment; and their caregivers. Cognitive rating scales administered included the Mini-Mental State Examination; the Modified Mini-Mental State Examination; the Boston Naming Test; the Benton Visual Retention Test; the Consortium to Establish a Registry for Alzheimer's Disease Neuropsychology Assessment; the Controlled Oral Word Test; the Wechsler Memory Scale logical memory I and logical memory II task; the Wechsler Memory Scale-Revised digit span; the Wechsler Adult Intelligence Scale-Revised digit symbol task; and the Clock Drawing Task together with the Clinical Dementia Rating Scale and the Neuropsychiatric Inventory. Stepwise regression of cognitive domains with symptom domains revealed significant associations of mood with impaired executive function/speed of processing (Δr = 0.22); impaired working memory (Δr = 0.05); impaired visual memory (Δr = 0.07); and worsened Clinical Dementia Rating Scale (Δr = 0.08). Psychosis was significantly associated with impaired working memory (Δr = 0.13). Mood symptoms appear to impact diverse cognitive realms and to compromise functional performance. Among neuropsychological indices, the unique relationship between working memory and psychosis suggests a possible common underlying neurobiology. 2012 American Association for Geriatric Psychiatry

Application of Fuzzy-Logic Controller and Neural Networks Controller in Gas Turbine Speed Control and Overheating Control and Surge Control on Transient Performance

NASA Astrophysics Data System (ADS)

Torghabeh, A. A.; Tousi, A. M.

2007-08-01

This paper presents Fuzzy Logic and Neural Networks approach to Gas Turbine Fuel schedules. Modeling of non-linear system using feed forward artificial Neural Networks using data generated by a simulated gas turbine program is introduced. Two artificial Neural Networks are used , depicting the non-linear relationship between gas generator speed and fuel flow, and turbine inlet temperature and fuel flow respectively . Off-line fast simulations are used for engine controller design for turbojet engine based on repeated simulation. The Mamdani and Sugeno models are used to expression the Fuzzy system . The linguistic Fuzzy rules and membership functions are presents and a Fuzzy controller will be proposed to provide an Open-Loop control for the gas turbine engine during acceleration and deceleration . MATLAB Simulink was used to apply the Fuzzy Logic and Neural Networks analysis. Both systems were able to approximate functions characterizing the acceleration and deceleration schedules . Surge and Flame-out avoidance during acceleration and deceleration phases are then checked . Turbine Inlet Temperature also checked and controls by Neural Networks controller. This Fuzzy Logic and Neural Network Controllers output results are validated and evaluated by GSP software . The validation results are used to evaluate the generalization ability of these artificial Neural Networks and Fuzzy Logic controllers.

77 FR 23385 - Airworthiness Directives; Fokker Services B.V. Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-19

... modifying the crossfeed valve control and power supply, the crossfeed indication logic and power supply, and... supply, of the crossfeed indication logic and power supply and of the fuel fire shut-off valve indication... this AD, modify the crossfeed valve control and power supply, the crossfeed indication logic and power...

Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers

NASA Astrophysics Data System (ADS)

Kondo, Hideaki; Sawada, Masaru; Murakami, Norio; Masui, Shoichi

This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than ±3.5% and lower a peaking in the passband filter characteristics. An experimental complex BPF using 0.18µm CMOS technology can successfully reduce the tuning error from an initial value of -20% to less than ±2.5% after tuning. The filter block dimensions are 1.22mm × 1.01mm; and in measurement results of the developed complex BPF with the automatic digital tuning circuit, current consumption is 705µA and the image rejection ratio is 40.3dB. Complete evaluation of the BPF indicates that this technique can be applied to low-power, low-cost transceivers.

Risk-Informed Safety Assurance and Probabilistic Assessment of Mission-Critical Software-Intensive Systems

NASA Technical Reports Server (NTRS)

Guarro, Sergio B.

2010-01-01

This report validates and documents the detailed features and practical application of the framework for software intensive digital systems risk assessment and risk-informed safety assurance presented in the NASA PRA Procedures Guide for Managers and Practitioner. This framework, called herein the "Context-based Software Risk Model" (CSRM), enables the assessment of the contribution of software and software-intensive digital systems to overall system risk, in a manner which is entirely compatible and integrated with the format of a "standard" Probabilistic Risk Assessment (PRA), as currently documented and applied for NASA missions and applications. The CSRM also provides a risk-informed path and criteria for conducting organized and systematic digital system and software testing so that, within this risk-informed paradigm, the achievement of a quantitatively defined level of safety and mission success assurance may be targeted and demonstrated. The framework is based on the concept of context-dependent software risk scenarios and on the modeling of such scenarios via the use of traditional PRA techniques - i.e., event trees and fault trees - in combination with more advanced modeling devices such as the Dynamic Flowgraph Methodology (DFM) or other dynamic logic-modeling representations. The scenarios can be synthesized and quantified in a conditional logic and probabilistic formulation. The application of the CSRM method documented in this report refers to the MiniAERCam system designed and developed by the NASA Johnson Space Center.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, V.R.; Miller, D.R.

1982-05-18

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistane heaters. Temperature-sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive-heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct tempertures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional-frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electrons is required to operate the instrument.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, Vanston R.; Miller, Donald R.

1984-01-01

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistance heaters. Temperature sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct temperatures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electronics is required to operate the instrument.

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Unpredictability and the transmission of numbers

NASA Astrophysics Data System (ADS)

Myers, John M.; Madjid, F. Hadi

2016-03-01

Curiously overlooked in physics is its dependence on the transmission of numbers. For example, the transmission of numerical clock readings is implicit in the concept of a coordinate system. The transmission of numbers and other logical distinctions is often achieved over a computer-mediated communications network in the face of an unpredictable environment. By unpredictable we mean something stronger than the spread of probabilities over given possible outcomes, namely an opening to unforeseeable possibilities. Unpredictability, until now overlooked in theoretical physics, makes the transmission of numbers interesting. Based on recent proofs within quantum theory that provide a theoretical foundation to unpredictability, here we show how regularities in physics rest on a background of channels over which numbers are transmitted. As is known to engineers of digital communications, numerical transmissions depend on coordination reminiscent of the cycle of throwing and catching by players tossing a ball back and forth. In digital communications, the players are computers, and the required coordination involves unpredictably adjusting "live clocks" that step these computers through phases of a cycle. We show how this phasing, which we call logical synchronization, constrains number-carrying networks, and, if a spacetime manifold in invoked, put "stripes" on spacetime. Via its logically synchronized channels, a network of live clocks serves as a reference against which to locate events. Such a network in any case underpins a coordinate frame, and in some cases the direct use of a network can be tailored to investigate an unpredictable environment. Examples include explorations of gravitational variations near Earth.

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

NASA Technical Reports Server (NTRS)

Shu, Peter; Waczynski, Augustyn; Kan, Emily; Wen, Yiting; Rosenberry, Robert

2012-01-01

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

Simulation and experiment of a fuzzy logic based MPPT controller for a small wind turbine system

NASA Astrophysics Data System (ADS)

Petrila, Diana; Muntean, Nicolae

2012-09-01

This paper describes the development of a fuzzy logic based maximum power point tracking (MPPT) strategy for a variable speed wind turbine system (VSWT). For this scope, a fuzzy logic controller (FLC) was described, simulated and tested on a real time "hardware in the loop" wind turbine emulator. Simulation and experimental results show that the controller is able to track the maximum power point for various wind conditions and validate the proposed control strategy.