Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Utilization of Tabula Rasa to Stabilize Bulk Lifetimes in n-Cz Silicon for High-Performance Solar Cell Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

LaSalvia, Vincenzo; Jensen, Mallory Ann; Youssef, Amanda

2016-11-21

We investigate a high temperature, high cooling-rate anneal Tabula Rasa (TR) and report its implications on n-type Czochralski-grown silicon (n-Cz Si) for photovoltaic fabrication. Tabula Rasa aims at dissolving and homogenizing oxygen precipitate nuclei that can grow during the cell process steps and degrade the cell performance due to their high internal gettering and recombination activity. The Tabula Rasa thermal treatment is performed in a clean tube furnace with cooling rates >100 degrees C/s. We characterize the bulk lifetime by Sinton lifetime and photoluminescence mapping just after Tabula Rasa, and after the subsequent cell processing. After TR, the bulk lifetimemore » surprisingly degrades to <; 0.1ms, only to recover to values equal or higher than the initial non-treated wafer (several ms), after typical high temperature cell process steps. Those include boron diffusion and oxidation; phosphorus diffusion/oxidation; ambient annealing at 850 degrees C; and crystallization annealing of tunneling-passivating contacts (doped polycrystalline silicon on 1.5 nm thermal oxide). The drastic lifetime improvement during high temperature cell processing is attributed to improved external gettering of metal impurities and annealing of intrinsic point defects. Time and injection dependent lifetime spectroscopy further reveals the mechanisms of lifetime improvement after Tabula Rasa treatment. Additionally, we report the efficacy of Tabula Rasa on n-type Cz-Si wafers and its dependence on oxygen concentration, correlated to position within the ingot.« less

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Control of cavitation using dissolved carbon dioxide for damage-free megasonic cleaning of wafers

NASA Astrophysics Data System (ADS)

Kumari, Sangita

This dissertation describes the finding that dissolved carbon dioxide is a potent inhibitor of sonoluminescence and describes the implications of the finding in the development of improved megasonic cleaning formulations. Megasonic cleaning, or the removal of contaminants particles from wafer surfaces using sound-irradiated cleaning fluids, has been traditionally used in the semiconductor industry for cleaning of wafers. A critical challenge in the field is to achieve removal of small particles (22 nm to 200 nm) without causing damage to fine wafer features. The work described here addresses this challenge by identifying sonoluminescence and solution pH as two key factors affecting damage and cleaning efficiency, respectively and establishing novel means to control them using CO2(aq) release compounds in the presence of acids and bases. Sonoluminescence (SL) behavior of the major dissolved gases such as Ar, Air, N2, O2 and CO2 was determined using a newly designed Cavitation Threshold Cell (CT Cell). SL, which is the phenomenon of release of light in sound-irradiated liquids, is a sensitive indicator of cavitation, primarily transient cavitation. It was found that all the tested dissolved gases such as Ar, Air, N2 and O2, generated SL signal efficiently. However, dissolved CO2 was found to be completely incapable of generating SL signal. Based on this interesting result, gradual suppression of SL signal was demonstrated using CO2(aq). It was further demonstrated that CO2(aq) is not only incapable but is also a potent inhibitor of SL. The inhibitory role of CO2(aq) was established using a novel method of controlled in-situ release of CO 2 from NH4HCO3. ~130 ppm CO2(aq) was shown to be necessary and sufficient for complete suppression of SL generation in air saturated DI water. The method however required acidification of solution for significant release of CO2, making it unsuitable for the design of cleaning solutions at high pH. Analysis of the underlying ionic equilibria revealed that the loss of released CO2(aq) upon increase in pH can be compensated by moderate increase in added NH4HCO3. Using this method, simultaneous control of SL and solution pH was demonstrated in two systems, NH4HCO3/HCl and NH4OH/CO2, at two nominal pH values; 5.7 and 7.0. Damage studies were performed on wafer samples with line/space patterns donated by IMEC and FSI International bearing Si/metal/a-Si gate stacks of thickness ~36 nm and Si/Poly-Si gate stacks of thickness ~67 nm, respectively. A single wafer spin cleaning tool MegPieRTM was used for the generation of megasonic energy for inducing damage to the structures. It was demonstrated that CO2 dissolution in DI water suppresses damage to the gate stacks in a dose-dependent manner. Together, these studies establish a systematic and strong correlation between CO2(aq) concentration, SL suppression and damage suppression. Significant damage reduction (~50 % to ~90 %) was observed at [CO2(aq)] > ~300 ppm. It was also demonstrated that CO2(aq) suppresses damage under alkaline pH condition too. This demonstration was made possible by the successful design of two new cleaning systems NH4HCO3/NH4OH and CO2/NH 4OH that could generate CO2(aq) under alkaline conditions. Damage suppressing ability of the newly designed cleaning systems were compared to the standard cleaning system NH4OH at pH 8.2 and it was found that NH4HCO3/NH4OH and CO2/NH 4OH systems were 80 % more efficient in suppressing damage compared to the standard NH4OH cleaning system. Finally, megasonic cleaning studies were conducted in the same single wafer spin cleaning tool MegPieRTM, using SiO2 particles (size 185 nm) deposited on 200 mm oxide Si wafers, as the contaminant. It was found that the standard cleaning chemical, NH4OH, pH 8.2, was effective in achieving > 95 % particle removal for 2 min irradiation of megasonic energy at power densities > 0.7 W/cm2. Based on these results, a new system, NH4HCO3/NH4OH, was designed with an aim to release ~300 ppm CO2 at pH 8.2. It was demonstrated that newly designed system NH4HCO3/NH 4OH, allowed significant suppression of damage in comparison to NH 4OH while maintaining > 90 % cleaning efficiency that was comparable to NH4OH solution, at the same acoustic power densities. Taken together, these studies establish a potent and flexible means for the inhibition of SL generation over a wide pH range and acoustic power densities and demonstrate its use in suppression of wafer damage without compromising megasonic cleaning efficiency. (Abstract shortened by UMI.)

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Behavior of Particle Depots in Molten Silicon During Float-Zone Growth in Strong Magnetic Fields

NASA Technical Reports Server (NTRS)

Jauss, T.; Croell, A.; SorgenFrei, T.; Azizi, M.; Reimann, C.; Friedrich, J.; Volz, M. P.

2014-01-01

Solar cells made from directionally solidified silicon cover 57% of the photovoltaic industry's market [1]. One major issue during directional solidification of silicon is the precipitation of foreign phase particles. These particles, mainly SiC and Si3N4, are precipitated from the dissolved crucible coating, which is made of silicon nitride, and the dissolution of carbon monoxide from the furnace atmosphere. Due to their hardness and size of several hundred micrometers, those particles can lead to severe problems during the wire sawing process for wafering the ingots. Additionally, SiC particles can act as a shunt, short circuiting the solar cell. Even if the particles are too small to disturb the wafering process, they can lead to a grit structure of silicon micro grains and serve as sources for dislocations. All of this lowers the yield of solar cells and reduces the performance of cells and modules. We studied the behaviour of SiC particle depots during float-zone growth under an oxide skin, and strong static magnetic fields. For high field strengths of 3T and above and an oxide layer on the sample surface, convection is sufficiently suppressed to create a diffusive like regime, with strongly dampened convection [2, 3]. To investigate the difference between atomically rough phase boundaries and facetted growth, samples with [100] and [111] orientation were processed.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Nano-imprint lithography using poly (methyl methacrylate) (PMMA) and polystyrene (PS) polymers

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2016-04-01

Nano-imprinting lithography (NIL) technology, as one of the most promising fabrication technologies, has been demonstrated to be a powerful tool for large-area replication up to wafer-level, with features down to nanometer scale. The cost of resists used for NIL is important for wafer-level large-area replication. This study aims to develop capabilities in patterning larger area structure using thermal NIL. The commercial available Poly (Methyl Methacrylate) (PMMA) and Polystyrene (PS) polymers possess a variety of characteristics desirable for NIL, such as low material cost, low bulkvolumetric shrinkage, high spin coating thickness uniformity, high process stability, and acceptable dry-etch resistance. PMMA materials have been utilized for positive electron beam lithography for many years, offering high resolution capability and wide process latitude. In addition, it is preferable to have a negative resist like PMMA, which is a simple polymer with low cost and practically unlimited shelf life, and can be dissolved easily using commercial available Propylene glycol methyl ether acetate (PGMEA) safer solvent to give the preferred film thickness. PS is such a resist, as it undergoes crosslinking when exposed to deep UV light or an electron beam and can be used for NIL. The result is a cost effective patterning larger area structure using thermal nano-imprint lithography (NIL) by using commercial available PMMA and PS ploymers as NIL resists.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2002-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2000-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Alternative method for steam generation for thermal oxidation of silicon

NASA Astrophysics Data System (ADS)

Spiegelman, Jeffrey J.

2010-02-01

Thermal oxidation of silicon is an important process step in MEMS device fabrication. Thicker oxide layers are often used as structural components and can take days or weeks to grow, causing high gas costs, maintenance issues, and a process bottleneck. Pyrolytic steam, which is generated from hydrogen and oxygen combustion, was the default process, but has serious drawbacks: cost, safety, particles, permitting, reduced growth rate, rapid hydrogen consumption, component breakdown and limited steam flow rates. Results from data collected over a 24 month period by a MEMS manufacturer supports replacement of pyrolytic torches with RASIRC Steamer technology to reduce process cycle time and enable expansion previously limited by local hydrogen permitting. Data was gathered to determine whether Steamers can meet or exceed pyrolytic torch performance. The RASIRC Steamer uses de-ionized water as its steam source, eliminating dependence on hydrogen and oxygen. A non-porous hydrophilic membrane selectively allows water vapor to pass. All other molecules are greatly restricted, so contaminants in water such as dissolved gases, ions, total organic compounds (TOC), particles, and metals can be removed in the steam phase. The MEMS manufacturer improved growth rate by 7% over the growth range from 1μm to 3.5μm. Over a four month period, wafer uniformity, refractive index, wafer stress, and etch rate were tracked with no significant difference found. The elimination of hydrogen generated a four-month return on investment (ROI). Mean time between failure (MTBF) was increased from 3 weeks to 32 weeks based on three Steamers operating over eight months.

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

SEMICONDUCTOR TECHNOLOGY Texturization of mono-crystalline silicon solar cells in TMAH without the addition of surfactant

NASA Astrophysics Data System (ADS)

Weiying, Ou; Yao, Zhang; Hailing, Li; Lei, Zhao; Chunlan, Zhou; Hongwei, Diao; Min, Liu; Weiming, Lu; Jun, Zhang; Wenjing, Wang

2010-10-01

Etching was performed on (100) silicon wafers using silicon-dissolved tetramethylammonium hydroxide (TMAH) solutions without the addition of surfactant. Experiments were carried out in different TMAH concentrations at different temperatures for different etching times. The surface phenomena, etching rates, surface morphology and surface reflectance were analyzed. Experimental results show that the resulting surface covered with uniform pyramids can be realized with a small change in etching rates during the etching process. The etching mechanism is explained based on the experimental results and the theoretical considerations. It is suggested that all the components in the TMAH solutions play important roles in the etching process. Moreover, TMA+ ions may increase the wettability of the textured surface. A good textured surface can be obtained in conditions where the absorption of OH-/H2O is in equilibrium with that of TMA+/SiO2 (OH)22-.

Submicron patterned metal hole etching

DOEpatents

McCarthy, Anthony M.; Contolini, Robert J.; Liberman, Vladimir; Morse, Jeffrey

2000-01-01

A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Measurement and reduction of micro-bubble formation in high-viscosity fluids

NASA Astrophysics Data System (ADS)

Tom, Glenn; Liu, Wei

2012-03-01

Gases at high drive pressure can initially dissolve into the fluids used in lithography and other critical processes during the fabrication of integrated circuits. In the low pressure portion of the dispense train, the dissolved gases can revert to bubbles. These bubbles can: 1. Affect the compressibility of the working fluid and change the flow characteristics of the dispense heads which require frequent re-tuning of the coating tools. 2. Contribute to defect formation if the bubbles are trapped on the surface of the wafer. Photosensitive Polyimides (PI) have high viscosities (1000 to 20,000 cP). Because of the high viscosity, high-powered, expensive pumps are needed to effectively remove the fluid from its container. Suction from the pump filling cycle easily causes cavitation, which can create flow rate variability, and micro-bubble formation. It is a common practice to apply pressure to the PI resists to minimize cavitation in the pump. The trade-off to this practice is the entrainment (dissolution) of the drive gas into the resist and the risk of micro-bubbles forming later in the dispense train. In the current study, ATMI measured the effects of two methods of pressure dispense from the container on the amount of gas entrained in a viscous fluid: (1) indirect pressure dispense and (2) direct pressure dispense. The main analytical method employed to measure the amount of dissolved gases is a gas chromatograph (GC), which can measure the concentration of gases dissolved in a volatile fluid. It is not suitable to measure gases in low volatility fluids. The new test method developed, however, is capable of measuring dissolved gases in low volatility fluids.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

CD and defect improvement challenges for immersion processes

NASA Astrophysics Data System (ADS)

Ehara, Keisuke; Ema, Tatsuhiko; Yamasaki, Toshinari; Nakagawa, Seiji; Ishitani, Seiji; Morita, Akihiko; Kim, Jeonghun; Kanaoka, Masashi; Yasuda, Shuichi; Asai, Masaya

2009-03-01

The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

1984-01-01

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Microbial biofilms for the removal of Cu²⁺ from CMP wastewater.

PubMed

Mosier, Aaron P; Behnke, Jason; Jin, Eileen T; Cady, Nathaniel C

2015-09-01

The modern semiconductor industry relies heavily on a process known as chemical mechanical planarization, which uses physical and chemical processes to remove excess material from the surface of silicon wafers during microchip fabrication. This process results in large volumes of wastewater containing dissolved metals including copper (Cu(2+)), which must then be filtered and treated before release into municipal waste systems. We have investigated the potential use of bacterial and fungal biomass as an alternative to the currently used ion-exchange resins for the adsorption of dissolved Cu(2+) from high-throughput industrial waste streams. A library of candidate microorganisms, including Lactobacillus casei and Pichia pastoris, was screened for ability to bind Cu(2+) from solution and to form static biofilm communities within packed-bed adsorption columns. The binding efficiency of these biomass-based adsorption columns was assessed under various flow conditions and compared to that of industrially used ion-exchange resins. We demonstrated the potential to regenerate the biomass within the adsorption columns through the use of a hydrochloric acid wash, and subsequently reuse the columns for additional copper binding. While the binding efficiency and capacity of the developed L. casei/P. pastoris biomass filters was inferior to ion-exchange resin, the potential for repeated reuse of these filters, coupled with the advantages of a more sustainable "green" adsorption process, make this technique an attractive candidate for use in industrial-scale CMP wastewater treatment. Copyright © 2015 Elsevier Ltd. All rights reserved.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic

NASA Astrophysics Data System (ADS)

Cramer, Hugo; Mc Namara, Elliott; van Laarhoven, Rik; Jaganatharaja, Ram; de la Fuente, Isabel; Hsu, Sharon; Belletti, Filippo; Popadic, Milos; Tu, Ward; Huang, Wade

2017-03-01

The logic manufacturing process requires small in-device metrology targets to exploit the full dose correction potential of the modern scanners and process tools. A high-NA angular resolved scatterometer (YieldStar S-1250D) was modified to demonstrate the possibility of OCD measurements on 5x5µm2 targets. The results obtained on test wafers in a logic manufacturing environment, measured after litho and after core etch, showed a good correlation to larger reference targets and AEI to ADI intra-field CDU correlation, thereby demonstrating the feasibility of OCD on such small targets. The data was used to determine a reduction potential of 55% for the intra-field CD variation, using 145 points per field on a few inner fields, and 33% of the process induced across wafer CD variation using 16 points per field full wafer. In addition, the OCD measurements reveal valuable information on wafer-to-wafer layer height variations within a lot.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

NASA Astrophysics Data System (ADS)

Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

2000-06-01

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface particle/residual contamination, (2) wafer flatness, and (3) control of contaminant materials such as copper (Cu). Data associated with the SpCE process, optimized for flatness improvement, particle removal, and Cu contamination control is presented in this paper, as it relates to excessive consumption of the usable depth of focus (UDOF) and comprehensive yield enhancement in photolithography. Additionally, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ SpCE clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

NASA Astrophysics Data System (ADS)

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

NASA Astrophysics Data System (ADS)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Implantable Wireless MEMS Sensors for Medical Uses

NASA Technical Reports Server (NTRS)

Chimbayo, Alexander

2006-01-01

Sensors designed and fabricated according to the principles of microelectromechanical systems (MEMS) are being developed for several medical applications in outer space and on Earth. The designs of these sensors are based on a core design family of pressure sensors, small enough to fit into the eye of a needle, that are fabricated by a "dissolved wafer" process. The sensors are expected to be implantable, batteryless, and wireless. They would be both powered and interrogated by hand-held radio transceivers from distances up to about 6 in. (about 15 cm). One type of sensor would be used to measure blood pressure, particularly for congestive heart failure. Another type would be used to monitor fluids in patients who have hydrocephalus (high brain pressure). Still other types would be used to detect errors in delivery of drugs and to help patients having congestive heart failure.

The Effects of Boron Doping on Residual Stress of Hfcvd Diamond Film for Mems Applications

NASA Astrophysics Data System (ADS)

Zhao, Tianqi; Wang, Xinchang; Sun, Fanghong

In this study, the residual stress of boron-doped diamond (BDD) films is investigated as a function of boron doping level using X-ray diffraction (XRD) analysis. Boron doping level is controlled from 1000ppm to 9000ppm by dissolving trimethyl borate into acetone. BDD films are deposited on silicon wafers using a bias-enhanced hot filament chemical vapor deposition (BE-HFCVD) system. Residual stress calculated by sin2 ψ method varies linearly from -2.4GPa to -1.1GPa with increasing boron doping level. On the BDD film of -1.75GPa, free standing BDD cantilevers are fabricated by photolithography and ICP-RIE processes, then tested by laser Doppler vibrometer (LDV). A cantilever with resonant frequency of 183KHz and Q factor of 261 in the air is fabricated.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

A dynamic scheduling algorithm for singe-arm two-cluster tools with flexible processing times

NASA Astrophysics Data System (ADS)

Li, Xin; Fung, Richard Y. K.

2018-02-01

This article presents a dynamic algorithm for job scheduling in two-cluster tools producing multi-type wafers with flexible processing times. Flexible processing times mean that the actual times for processing wafers should be within given time intervals. The objective of the work is to minimize the completion time of the newly inserted wafer. To deal with this issue, a two-cluster tool is decomposed into three reduced single-cluster tools (RCTs) in a series based on a decomposition approach proposed in this article. For each single-cluster tool, a dynamic scheduling algorithm based on temporal constraints is developed to schedule the newly inserted wafer. Three experiments have been carried out to test the dynamic scheduling algorithm proposed, comparing with the results the 'earliest starting time' heuristic (EST) adopted in previous literature. The results show that the dynamic algorithm proposed in this article is effective and practical.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Industrial implementation of spatial variability control by real-time SPC

NASA Astrophysics Data System (ADS)

Roule, O.; Pasqualini, F.; Borde, M.

2016-10-01

Advanced technology nodes require more and more information to get the wafer process well setup. The critical dimension of components decreases following Moore's law. At the same time, the intra-wafer dispersion linked to the spatial non-uniformity of tool's processes is not capable to decrease in the same proportions. APC systems (Advanced Process Control) are being developed in waferfab to automatically adjust and tune wafer processing, based on a lot of process context information. It can generate and monitor complex intrawafer process profile corrections between different process steps. It leads us to put under control the spatial variability, in real time by our SPC system (Statistical Process Control). This paper will outline the architecture of an integrated process control system for shape monitoring in 3D, implemented in waferfab.

Extending i-line capabilities through variance characterization and tool enhancement

NASA Astrophysics Data System (ADS)

Miller, Dan; Salinas, Adrian; Peterson, Joel; Vickers, David; Williams, Dan

2006-03-01

Continuous economic pressures have moved a large percent of integrated device manufacturing (IDM) operations either overseas or to foundry operations over the last 10 years. These pressures have left the IDM fabs in the U.S. with required COO improvements in order to maintain operations domestically. While the assets of many of these factories are at a very favorable point in the depreciation life cycle, the equipment and processes are constrained to the quality of the equipment in its original state and the degradation over its installed life. With the objective to enhance output and improve process performance, this factory and their primary lithography process tool supplier have been able to extend the usable life of the existing process tools, increase the output of the tool base, and improve the distribution of the CDs on the product produced. Texas Instruments Incorporated lead an investigation with the POLARIS ® Systems & Services business of FSI International to determine the sources of variance in the i-line processing of a wide array of IC device types. Data from the sources of variance were investigated such as PEB temp, PEB delay time, develop recipe, develop time, and develop programming. While PEB processes are a primary driver of acid catalyzed resists, the develop mode is shown in this work to have an overwhelming impact on the wafer to wafer and across wafer CD performance of these i-line processes. These changes have been able to improve the wafer to wafer CD distribution by more than 80 %, and the within wafer CD distribution by more than 50 % while enabling a greater than 50 % increase in lithography cluster throughput. The paper will discuss the contribution from each of the sources of variance and their importance in overall system performance.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Residual Stress and Fracture of PECVD Thick Oxide Films for Power MEMS Structures and Devices

DTIC Science & Technology

2007-06-01

Residual stress leads to large overall wafer bow, which makes further processing difficult. For example some microfabrication machines , such as chemical...curvature will be measured across the wafer surface in 12 scans, rotating 24 the wafer by 300 between each scan. In situ wafer curvature will be...SiOx. 4.1. Introduction As introduced earlier (Sec.1), in Power MEMS (micro energy- harvesting devices such as micro heat engines and related components

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Photolithography and Selective Etching of an Array of Quartz Tuning Fork Resonators with Improved Impact Resistance Characteristics

NASA Astrophysics Data System (ADS)

Lee, Sungkyu

2001-08-01

Quartz tuning fork blanks with improved impact-resistant characteristics for use in Qualcomm mobile station modem (MSM)-3000 central processing unit (CPU) chips for code division multiple access (CDMA), personal communication system (PCS), and global system for mobile communication (GSM) systems were designed using finite element method (FEM) analysis and suitable processing conditions were determined for the reproducible precision etching of a Z-cut quartz wafer into an array of tuning forks. Negative photoresist photolithography for the additive process was used in preference to positive photoresist photolithography for the subtractive process to etch the array of quartz tuning forks. The tuning fork pattern was transferred via a conventional photolithographical chromium/quartz glass template using a standard single-sided aligner and subsequent negative photoresist development. A tightly adhering and pinhole-free 600/2000 Å chromium/gold mask was coated over the developed photoresist pattern which was subsequently stripped in acetone. This procedure was repeated on the back surface of the wafer. With the protective metallization area of the tuning fork geometry thus formed, etching through the quartz wafer was performed at 80°C in a ± 1.5°C controlled bath containing a concentrated solution of ammonium bifluoride to remove the unwanted areas of the quartz wafer. The quality of the quartz wafer surface finish after quartz etching depended primarily on the surface finish of the quartz wafer prior to etching and the quality of quartz crystals used. Selective etching of a 100 μm quartz wafer could be achieved within 90 min at 80°C. A selective etching procedure with reproducible precision has thus been established and enables the photolithographic mass production of miniature tuning fork resonators.

Manufacturing of High-Efficiency Bi-Facial Tandem Concentrator Solar Cells: February 20, 2009--August 20, 2010

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojtczuk , S.

2011-06-01

Spire Semiconductor made concentrator photovoltaic (CPV) cells using a new bi-facial growth process and met both main program goals: a) 42.5% efficiency 500X (AM1.5D, 25C, 100mW/cm2); and b) Ready to supply at least 3MW/year of such cells at end of program. We explored a unique simple fabrication process to make a N/P 3-junction InGaP/GaAs/InGaAs tandem cells . First, the InGaAs bottom cell is grown on the back of a GaAs wafer. The wafers are then loaded into a cassette, spin-rinsed to remove particles, dipped in dilute NH4OH and spin-dried. The wafers are then removed from the cassette loaded the reactormore » for GaAs middle and InGaP top cell growth on the opposite wafer face (bi-facial growth). By making the epitaxial growth process a bit more complex, we are able to avoid more complex processing (such as large area wafer bonding or epitaxial liftoff) used in the inverted metamorphic (IMM) approach to make similar tandem stacks. We believe the yield is improved compared to an IMM process. After bi-facial epigrowth, standard III-V cell steps (back metal, photolithography for front grid, cap etch, AR coat, dice) are used in the remainder of the process.« less

Forming n/p Junctions With An Excimer Laser

NASA Technical Reports Server (NTRS)

Alexander, Paul, Jr.; Campbell, Robert B.; Wong, David C.; Bottenberg, William L.; Byron, Stanley

1988-01-01

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Method for nanomachining high aspect ratio structures

DOEpatents

Yun, Wenbing; Spence, John; Padmore, Howard A.; MacDowell, Alastair A.; Howells, Malcolm R.

2004-11-09

A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Overlay improvements using a real time machine learning algorithm

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Kubis, Michael; Henke, Wolfgang; Slotboom, Daan; Hoogenboom, Tom; Mulkens, Jan; Coogans, Martyn; ten Berge, Peter; Verkleij, Dick; van de Mast, Frank

2014-04-01

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Advanced overlay: sampling and modeling for optimized run-to-run control

NASA Astrophysics Data System (ADS)

Subramany, Lokesh; Chung, WoongJae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Gutjahr, Karsten; Park, DongSuk; Snow, Patrick; Garcia-Medina, Miguel; Yap, Lipkong; Demirer, Onur Nihat; Pierson, Bill; Robinson, John C.

2016-03-01

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the "sample plan" of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-03-01

This report describes work to advance the manufacturing line capabilities in crystal growth and laser cutting of Mobil Solar's unique edge-defined film-fed growth (EFG) octagon technology and to reduce the manufacturing costs of 10 cm x 10 cm polycrystalline silicon EFG wafers. The report summarizes the significant technical improvements in EFG technology achieved in the first 6 months of the PVMaT Phase 2 and the success in meeting program milestones. Technical results are reported for each of the three main pregrain areas: Task 5 -- Thin octagon growth (crystal growth) to reduce the thickness of the octagon to 200 microns; Task 6 -- Laser cutting-to improve the laser cutting process so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and Task 7 -- Process control and product specification to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

NASA Astrophysics Data System (ADS)

Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

2003-09-01

As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Real-Time Plasma Process Condition Sensing and Abnormal Process Detection

PubMed Central

Yang, Ryan; Chen, Rongshun

2010-01-01

The plasma process is often used in the fabrication of semiconductor wafers. However, due to the lack of real-time etching control, this may result in some unacceptable process performances and thus leads to significant waste and lower wafer yield. In order to maximize the product wafer yield, a timely and accurately process fault or abnormal detection in a plasma reactor is needed. Optical emission spectroscopy (OES) is one of the most frequently used metrologies in in-situ process monitoring. Even though OES has the advantage of non-invasiveness, it is required to provide a huge amount of information. As a result, the data analysis of OES becomes a big challenge. To accomplish real-time detection, this work employed the sigma matching method technique, which is the time series of OES full spectrum intensity. First, the response model of a healthy plasma spectrum was developed. Then, we defined a matching rate as an indictor for comparing the difference between the tested wafers response and the health sigma model. The experimental results showed that this proposal method can detect process faults in real-time, even in plasma etching tools. PMID:22219683

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

A novel approach of chemical mechanical polishing using environment-friendly slurry for mercury cadmium telluride semiconductors

PubMed Central

Zhang, Zhenyu; Wang, Bo; Zhou, Ping; Guo, Dongming; Kang, Renke; Zhang, Bi

2016-01-01

A novel approach of chemical mechanical polishing (CMP) is developed for mercury cadmium telluride (HgCdTe or MCT) semiconductors. Firstly, fixed-abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water. Secondly, the MCT wafers are polished using the developed CMP slurry. The CMP slurry consists of mainly SiO2 nanospheres, H2O2, and malic and citric acids, which are different from previous CMP slurries, in which corrosive and toxic chemical reagents are usually employed. Finally, the polished MCT wafers are cleaned and dried by deionized water and compressed air, respectively. The novel approach of CMP is environment-friendly. Surface roughness Ra, and peak-to-valley (PV) values of 0.45, and 4.74 nm are achieved, respectively on MCT wafers after CMP. The first and second passivating processes are observed in electrochemical measurements on MCT wafers. The fundamental mechanisms of CMP are proposed according to the X-ray photoelectron spectroscopy (XPS) and electrochemical measurements. Malic and citric acids dominate the first passivating process, and the CMP slurry governs the second process. Te4+3d peaks are absent after CMP induced by the developed CMP slurry, indicating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2 and malic and citric acids solutions. PMID:26926622

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Effect of dissolved gases in water on acoustic cavitation and bubble growth rate in 0.83 MHz megasonic of interest to wafer cleaning.

PubMed

Kang, Bong-Kyun; Kim, Min-Su; Park, Jin-Goo

2014-07-01

Changes in the cavitation intensity of gases dissolved in water, including H2, N2, and Ar, have been established in studies of acoustic bubble growth rates under ultrasonic fields. Variations in the acoustic properties of dissolved gases in water affect the cavitation intensity at a high frequency (0.83 MHz) due to changes in the rectified diffusion and bubble coalescence rate. It has been proposed that acoustic bubble growth rates rapidly increase when water contains a gas, such as hydrogen faster single bubble growth due to rectified diffusion, and a higher rate of coalescence under Bjerknes forces. The change of acoustic bubble growth rate in rectified diffusion has an effect on the damping constant and diffusivity of gas at the acoustic bubble and liquid interface. It has been suggested that the coalescence reaction of bubbles under Bjerknes forces is a reaction determined by the compressibility and density of dissolved gas in water associated with sound velocity and density in acoustic bubbles. High acoustic bubble growth rates also contribute to enhanced cavitation effects in terms of dissolved gas in water. On the other hand, when Ar gas dissolves into water under ultrasound field, cavitation behavior was reduced remarkably due to its lower acoustic bubble growth rate. It is shown that change of cavitation intensity in various dissolved gases were verified through cleaning experiments in the single type of cleaning tool such as particle removal and pattern damage based on numerically calculated acoustic bubble growth rates. Copyright © 2014 Elsevier B.V. All rights reserved.

Environmentally benign processing of YAG transparent wafers

NASA Astrophysics Data System (ADS)

Yang, Yan; Wu, Yiquan

2015-12-01

Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

Advanced FTIR technology for the chemical characterization of product wafers

NASA Astrophysics Data System (ADS)

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by employing broadband quartz rod-transducer assembles). Experimental results, as predicted by prior rigorous simulations, prove that the temperature measurement accuracy obtained through several dynamic runs using the above specified approach, is better than +/-2°C. Furthermore, these results are highly repeatable and independent of wafer treatment conditions, thereby extolling the versatility and immunity of the new method from environmental conditions.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

NASA Astrophysics Data System (ADS)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Disc resonator gyroscope fabrication process requiring no bonding alignment

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor)

2010-01-01

A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Progress and challenges for cost effective kerfless Silicon crystal growth for PV application

NASA Astrophysics Data System (ADS)

Serra, J. M.; Alves, J. Maia; Vallera, A. M.

2017-06-01

The major barrier for PV penetration is cost. And the single most important cost factor in silicon technology is the wafer (≈35% of the module cost). Although tremendous progress on cell processing has been reported in recent years, a much smaller evolution is seen on what should be the key point to address - the wafer. The ingot-slicing process is reaching its limits as the wafer thickness is reduced in an effort to lower material costs. Kerf losses of ≈50% and an increase in breakage of a high value added material are putting a lower bound to this approach. New ideas are therefore needed for producing wafers in a way to overcome these limitations. In this paper we present three new concepts being developed in our laboratory that have one thing in common: they all are zero kerf loss processes, aiming at significant reductions in material loss. One explores the concept of exfoliation, the other two aim at the growth of silicon directly into ribbons. These were conceived as continuous processes, based on a floating molten zone concept, to avoid impurity contamination during crystallization.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

PubMed

Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

2003-12-01

Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jankowski, A.F.; Hayes, J.P.; Kanna, R.L.

The formation of high energy density, storage devices is achievable using composite material systems. Alternate layering of carbon aerogel wafers and Ni foils with rnicroporous separators is a prospective composite for capacitor applications. An inherent problem exists to form a physical bond between Ni and the porous carbon wafer. The bonding process must be limited to temperatures less than 1000{degrees}C, at which point the aerogel begins to degrade. The advantage of a low temperature eutectic in the Ni-Ti alloy system solves this problem. Ti, a carbide former, is readily adherent as a sputter deposited thin film onto the carbon wafer.more » A vacuum bonding process is then used to join the Ni foil and Ti coating through eutectic phase formation. The parameters required for successfld bonding are described along with a structural characterization of the Ni foil-carbon aerogel wafer interface.« less

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Mobil Solar Energy Corporation thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program at Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 (mu)m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE PAGES

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis; ...

2018-03-09

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Astrophysics Data System (ADS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

2016-08-01

Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

Development of a plan for automating integrated circuit processing

NASA Technical Reports Server (NTRS)

1971-01-01

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Technical Reports Server (NTRS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.;

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

NASA Technical Reports Server (NTRS)

Redfield, D.

1981-01-01

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Applications of colored petri net and genetic algorithms to cluster tool scheduling

NASA Astrophysics Data System (ADS)

Liu, Tung-Kuan; Kuo, Chih-Jen; Hsiao, Yung-Chin; Tsai, Jinn-Tsong; Chou, Jyh-Horng

2005-12-01

In this paper, we propose a method, which uses Coloured Petri Net (CPN) and genetic algorithm (GA) to obtain an optimal deadlock-free schedule and to solve re-entrant problem for the flexible process of the cluster tool. The process of the cluster tool for producing a wafer usually can be classified into three types: 1) sequential process, 2) parallel process, and 3) sequential parallel process. But these processes are not economical enough to produce a variety of wafers in small volume. Therefore, this paper will propose the flexible process where the operations of fabricating wafers are randomly arranged to achieve the best utilization of the cluster tool. However, the flexible process may have deadlock and re-entrant problems which can be detected by CPN. On the other hand, GAs have been applied to find the optimal schedule for many types of manufacturing processes. Therefore, we successfully integrate CPN and GAs to obtain an optimal schedule with the deadlock and re-entrant problems for the flexible process of the cluster tool.

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Quantum Dots obtained by LPE from under-saturated In-As liquid phases on GaAs substrates

NASA Astrophysics Data System (ADS)

Ortiz, F. E.; Mishurnyi, V.; Gorbatchev, A.; De Anda, F.; Prutskij, T.

2011-01-01

In this work we inform about quantum dots (QD) obtained by Liquid Phase Epitaxy (LPE) on GaAs substrates from under-saturated In-As liquid phases. In our processes, we have prepared saturated In-rich liquid phases by dissolving an InAs wafer at one of the temperatures interval from 450 to 414 C for 60 minutes. The contact between In-As liquid phase and the GaAs substrate was always done at a constant temperature of 444 C for 5 seconds. Thus, the growth temperature for most of the samples was higher than the liquidus temperature. We think that the growth driving force is related to a transient process that occurs when the system is trying to reach equilibrium. Under the atom force microscope (AFM) we have observed nano-islands on the surfaces of the samples obtained from under-saturated liquid phases prepared at 438, 432 and 426 C. The 25 K photoluminescence spectrum shows a peak at a 1.33 eV, in addition to the GaAs related line.

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

NASA Technical Reports Server (NTRS)

Routh, D. E.; Sharma, G. C. (Inventor)

1984-01-01

An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

NASA Technical Reports Server (NTRS)

Routh, D. E.; Sharma, G. C. (Inventor)

1982-01-01

The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps.

Mechanics of wafer bonding: Effect of clamping

NASA Astrophysics Data System (ADS)

Turner, K. T.; Thouless, M. D.; Spearing, S. M.

2004-01-01

A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Measurement and thermal modeling of sapphire substrate temperature at III-Nitride MOVPE conditions

DOE PAGES

Creighton, J. Randall; Coltrin, Michael E.; Figiel, Jeffrey J.

2017-04-01

Here, growth rates and alloy composition of AlGaN grown by MOVPE is often very temperature dependent due to the presence of gas-phase parasitic chemical processes. These processes make wafer temperature measurement highly important, but in fact such measurements are very difficult because of substrate transparency in the near- IR (~900 nm) where conventional pyrometers detect radiation. The transparency problem can be solved by using a mid-IR pyrometer operating at a wavelength (~7500 nm) where sapphire is opaque. We employ a mid- IR pyrometer to measure the sapphire wafer temperature and simultaneously a near-IR pyrometer to measure wafer pocket temperature, whilemore » varying reactor pressure in both a N 2 and H 2 ambient. Near 1300 °C, as the reactor pressure is lowered from 300 Torr to 10 Torr the wafer temperature drops dramatically, and the ΔT between the pocket and wafer increases from ~20 °C to ~250 °C. Without the mid-IR pyrometer the large wafer temperature change with pressure would not have been noted. In order to explain this behavior we have developed a quasi-2D thermal model that includes a proper accounting of the pressure-dependent thermal contact resistance, and also accounts for sapphire optical transmission. The model and experimental results demonstrate that at most growth conditions the majority of the heat is transported from the wafer pocket to the wafer via gas conduction, in the free molecular flow limit. In this limit gas conductivity is independent of gap size but first order in pressure, and can quantitatively explain results from 20 to 300 Torr. Further analysis yields a measure of the thermal accommodation coefficients; α(H 2) =0.23, α(N 2) =0.50, which are in the range typically measured.« less

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Optical processing furnace with quartz muffle and diffuser plate

DOEpatents

Sopori, B.L.

1996-11-19

An optical furnace for annealing a process wafer is disclosed comprising a source of optical energy, a quartz muffle having a door to hold the wafer for processing, and a quartz diffuser plate to diffuse the light impinging on the quartz muffle; a feedback system with a light sensor located in the wall of the muffle is also provided for controlling the source of optical energy. 5 figs.

Analysis and Evaluation of Processes and Equipment in Tasks 2 and 4 of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Goldman, H.; Wolf, M.

1978-01-01

The significant economic data for the current production multiblade wafering and inner diameter slicing processes were tabulated and compared to data on the experimental and projected multiblade slurry, STC ID diamond coated blade, multiwire slurry and crystal systems fixed abrasive multiwire slicing methods. Cost calculations were performed for current production processes and for 1982 and 1986 projected wafering techniques.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Vertical and lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Okuno, Yae L.; Bowers, John E.; Jayaraman, Vijay

2001-09-01

A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Fluxless eutectic bonding of GaAs-on-Si by using Ag/Sn solder

NASA Astrophysics Data System (ADS)

Eo, Sung-Hwa; Kim, Dae-Seon; Jeong, Ho-Jung; Jang, Jae-Hyung

2013-11-01

Fluxless GaAs-on-Si wafer bonding using Ag/Sn solder was investigated to realize uniform and void-free heterogeneous material integration. The effects of the diffusion barrier, Ag/Sn thickness, and Ar plasma treatment were studied to achieve the optimal fluxless bonding process. Pt on a GaAs wafer and Mo on a Si wafer act as diffusion barriers by preventing the flow of Ag/Sn solder into both the wafers. The bonding strength is closely related to the Ag/Sn thickness and Ar plasma treatment. A shear strength test was carried out to investigate the bonding strength. Under identical bonding conditions, the Ag/Sn thickness was optimized to achieve higher bonding strength and to avoid the formation of voids due to thermal stress. An Ar plasma pretreatment process improved the bonding strength because the Ar plasma removed carbon contaminants and metal-oxide bonds from the metal surface.

Advances in process overlay on 300-mm wafers

NASA Astrophysics Data System (ADS)

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

BCB Bonding Technology of Back-Side Illuminated COMS Device

NASA Astrophysics Data System (ADS)

Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

2018-03-01

Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

Non-Invasive Optical Characterization of Defects in Gallium Arsenide.

NASA Astrophysics Data System (ADS)

Cao, Xuezhong

This work is concerned with the development of a non-invasive comprehensive defect analysis system based on computer-assisted near infrared (NIR) microscopy. Focus was placed on the development of software for quantitative image analysis, contrast enhancement, automated defects density counting, and two-dimensional defect density mapping. Bright field, dark field, phase contrast, and polarized light imaging modes were explored for the analysis of striations, precipitates, decorated and undecorated dislocations, surface and subsurface damage, and local residual strain in GaAs wafers. The origin of the contrast associated with defect image formation in NIR microscopy was analyzed. The local change in the index of refraction about a defect was modelled as a mini-lens. This model can explain reversal of image contrast for dislocations in heavily doped n-type GaAs during defocusing. Defect structures in GaAs crystals grown by the conventional liquid encapsulated Czochralski (LEC) method are found to differ significantly from those grown by the horizontal Bridgman (HB) or vertical gradient freeze (VGF) method. Dislocation densities in HB and VGF GaAs are one to two orders of magnitude lower compared to those in conventional LEC GaAs. The dislocations in HB and VGF GaAs remain predominantly on the {111}/<1 |10> primary slip system and tend to form small-angle subboundaries. Much more complicated dislocation structures are found in conventional LEC GaAs. Dislocation loops, dipoles, and helices were observed, indicating strong interaction between dislocations and point defects in these materials. Precipitates were observed in bulk GaAs grown by the LEC, HB, and VGF methods. Precipitation was found to occur predominantly along dislocation lines, however, discrete particles were also observed in dislocation-free regions of the GaAs matrix. The size of discrete precipitates is much smaller than that of the precipitates along dislocations. Quenching after high temperature annealing at 1150^ circC was found effective in dissolving the precipitates but glide dislocations are generated during the quenching process. STEM/EDX analysis showed that the precipitates are essentially pure arsenic in both undoped and doped GaAs. NIR phase contrast transmission microscopy was found to be very sensitive in detecting surface and subsurface damage on commercial GaAs wafers. Wafers from a number of GaAs manufacturers were examined. It was shown that some GaAs wafers exhibit perfect surface quality, but in many instances they exhibit, to various extents, subsurface damage. Computer-assisted NIR transmission microscopy in a variety of modes is found to be a rapid and non-invasive technique suitable for wafer characterization in a fabline environment. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.) (Abstract shortened by UMI.).

In-situ sensing using mass spectrometry and its use for run-to-run control on a W-CVD cluster tool

NASA Astrophysics Data System (ADS)

Gougousi, T.; Sreenivasan, R.; Xu, Y.; Henn-Lecordier, L.; Rubloff, G. W.; Kidder, , J. N.; Zafiriou, E.

2001-01-01

A 300 amu closed-ion-source RGA (Leybold-Inficon Transpector 2) sampling gases directly from the reactor of an ULVAC ERA-1000 cluster tool has been used for real time process monitoring of a W CVD process. The process involves H2 reduction of WF6 at a total pressure of 67 Pa (0.5 torr) to produce W films on Si wafers heated at temperatures around 350 °C. The normalized RGA signals for the H2 reagent depletion and the HF product generation were correlated with the W film weight as measured post-process with an electronic microbalance for the establishment of thin-film weight (thickness) metrology. The metrology uncertainty (about 7% for the HF product) was limited primarily by the very low conversion efficiency of the W CVD process (around 2-3%). The HF metrology was then used to drive a robust run-to-run control algorithm, with the deposition time selected as the manipulated (or controlled) variable. For that purpose, during a 10 wafer run, a systematic process drift was introduced as a -5 °C processing temperature change for each successive wafer, in an otherwise unchanged process recipe. Without adjustment of the deposition time the W film weight (thickness) would have declined by about 50% by the 10th wafer. With the aid of the process control algorithm, an adjusted deposition time was computed so as to maintain constant HF sensing signal, resulting in weight (thickness) control comparable to the accuracy of the thickness metrology. These results suggest that in-situ chemical sensing, and particularly mass spectrometry, provide the basis for wafer state metrology as needed to achieve run-to-run control. Furthermore, since the control accuracy was consistent with the metrology accuracy, we anticipate significant improvements for processes as used in manufacturing, where conversion rates are much higher (40-50%) and corresponding signals for metrology will be much larger.

Mobil Solar Energy Corporation thin EFG octagons. Final subcontract report, 1 April 1992--31 January 1994

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kalejs, J.P.

1994-06-01

Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program atmore » Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 {mu}m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.« less

Particle-free microchip processing

DOEpatents

Geller, Anthony S.; Rader, Daniel J.

1996-01-01

Method and apparatus for reducing particulate contamination in microchip processing are disclosed. The method and apparatus comprise means to reduce particle velocity toward the wafer before the particles can be deposited on the wafer surface. A reactor using electric fields to reduce particle velocity and prevent particulate contamination is disclosed. A reactor using a porous showerhead to reduce particle velocities and prevent particulate contamination is disclosed.

Microeconomics of process control in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.

2003-06-01

Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

MOCVD process technology for affordable, high-yield, high-performance MESFET structures. Phase 3: MIMIC

NASA Astrophysics Data System (ADS)

1993-01-01

Under the MIMIC Program, Spire has pursued improvements in the manufacturing of low cost, high quality gallium arsenide MOCVD wafers for advanced MIMIC FET applications. As a demonstration of such improvements, Spire was tasked to supply MOCVD wafers for comparison to MBE wafers in the fabrication of millimeter and microwave integrated circuits. In this, the final technical report for Spire's two-year MIMIC contract, we report the results of our work. The main objectives of Spire's MIMIC Phase 3 Program, as outlined in the Statement of Work, were as follows: Optimize the MOCVD growth conditions for the best possible electrical and morphological gallium arsenide. Optimization should include substrate and source qualification as well as determination of the optimum reactor growth conditions; Perform all work on 75 millimeter diameter wafers, using a reactor capable of at least three wafers per run; and Evaluate epitaxial layers using electrical, optical, and morphological tests to obtain thickness, carrier concentration, and mobility data across wafers.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Comparison of line shortening assessed by aerial image and wafer measurements

NASA Astrophysics Data System (ADS)

Ziegler, Wolfram; Pforr, Rainer; Thiele, Joerg; Maurer, Wilhelm

1997-02-01

Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

Interferometric surface mapping with variable sensitivity.

PubMed

Jaerisch, W; Makosch, G

1978-03-01

In the photolithographic process, presently employed for the production of integrated circuits, sets of correlated masks are used for exposing the photoresist on silicon wafers. Various sets of masks which are printed in different printing tools must be aligned correctly with respect to the structures produced on the wafer in previous process steps. Even when perfect alignment is considered, displacements and distortions of the printed wafer patterns occur. They are caused by imperfections of the printing tools or/and wafer deformations resulting from high temperature processes. Since the electrical properties of the final integrated circuits and therefore the manufacturing yield depend to a great extent on the precision at which such patterns are superimposed, simple and fast overlay measurements and flatness measurements as well are very important in IC-manufacturing. A simple optical interference method for flatness measurements will be described which can be used under manufacturing conditions. This method permits testing of surface height variations by nearly grazing light incidence by absence of a physical reference plane. It can be applied to polished surfaces and rough surfaces as well.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less

Feed-forward alignment correction for advanced overlay process control using a standalone alignment station "Litho Booster"

NASA Astrophysics Data System (ADS)

Yahiro, Takehisa; Sawamura, Junpei; Dosho, Tomonori; Shiba, Yuji; Ando, Satoshi; Ishikawa, Jun; Morita, Masahiro; Shibazaki, Yuichi

2018-03-01

One of the main components of an On-Product Overlay (OPO) error budget is the process induced wafer error. This necessitates wafer-to-wafer correction in order to optimize overlay accuracy. This paper introduces the Litho Booster (LB), standalone alignment station as a solution to improving OPO. LB can execute high speed alignment measurements without throughput (THP) loss. LB can be installed in any lithography process control loop as a metrology tool, and is then able to provide feed-forward (FF) corrections to the scanners. In this paper, the detailed LB design is described and basic LB performance and OPO improvement is demonstrated. Litho Booster's extendibility and applicability as a solution for next generation manufacturing accuracy and productivity challenges are also outlined

A new fabrication technique for back-to-back varactor diodes

NASA Technical Reports Server (NTRS)

Smith, R. Peter; Choudhury, Debabani; Martin, Suzanne; Frerking, Margaret A.; Liu, John K.; Grunthaner, Frank A.

1992-01-01

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

NASA Astrophysics Data System (ADS)

Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

2016-08-01

This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

Modeling physical vapor deposition of energetic materials

DOE PAGES

Shirvan, Koroush; Forrest, Eric C.

2018-03-28

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Modeling physical vapor deposition of energetic materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shirvan, Koroush; Forrest, Eric C.

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

Computational overlay metrology with adaptive data analytics

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Subramony, Venky; Ullah, Zakir; Matsunobu, Masazumi; Somasundaram, Ravin; Thomas, Joel; Zhang, Linmiao; Thul, Klaus; Bhattacharyya, Kaustuve; Goossens, Ronald; Lambregts, Cees; Tel, Wim; de Ruiter, Chris

2017-03-01

With photolithography as the fundamental patterning step in the modern nanofabrication process, every wafer within a semiconductor fab will pass through a lithographic apparatus multiple times. With more than 20,000 sensors producing more than 700GB of data per day across multiple subsystems, the combination of a light source and lithographic apparatus provide a massive amount of information for data analytics. This paper outlines how data analysis tools and techniques that extend insight into data that traditionally had been considered unmanageably large, known as adaptive analytics, can be used to show how data collected before the wafer is exposed can be used to detect small process dependent wafer-towafer changes in overlay.

Particle-free microchip processing

DOEpatents

Geller, A.S.; Rader, D.J.

1996-06-04

Method and apparatus for reducing particulate contamination in microchip processing are disclosed. The method and apparatus comprise means to reduce particle velocity toward the wafer before the particles can be deposited on the wafer surface. A reactor using electric fields to reduce particle velocity and prevent particulate contamination is disclosed. A reactor using a porous showerhead to reduce particle velocities and prevent particulate contamination is disclosed. 5 figs.

Automated aerial image based CD metrology initiated by pattern marking with photomask layout data

NASA Astrophysics Data System (ADS)

Davis, Grant; Choi, Sun Young; Jung, Eui Hee; Seyfarth, Arne; van Doornmalen, Hans; Poortinga, Eric

2007-05-01

The photomask is a critical element in the lithographic image transfer process from the drawn layout to the final structures on the wafer. The non-linearity of the imaging process and the related MEEF impose a tight control requirement on the photomask critical dimensions. Critical dimensions can be measured in aerial images with hardware emulation. This is a more recent complement to the standard scanning electron microscope measurement of wafers and photomasks. Aerial image measurement includes non-linear, 3-dimensional, and materials effects on imaging that cannot be observed directly by SEM measurement of the mask. Aerial image measurement excludes the processing effects of printing and etching on the wafer. This presents a unique contribution to the difficult process control and modeling tasks in mask making. In the past, aerial image measurements have been used mainly to characterize the printability of mask repair sites. Development of photomask CD characterization with the AIMS TM tool was motivated by the benefit of MEEF sensitivity and the shorter feedback loop compared to wafer exposures. This paper describes a new application that includes: an improved interface for the selection of meaningful locations using the photomask and design layout data with the Calibre TM Metrology Interface, an automated recipe generation process, an automated measurement process, and automated analysis and result reporting on a Carl Zeiss AIMS TM system.

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Poly(vinyl acetate)/clay nanocomposite materials for organic thin film transistor application.

PubMed

Park, B J; Sung, J H; Park, J H; Choi, J S; Choi, H J

2008-05-01

Nanocomposite materials of poly(vinyl acetate) (PVAc) and organoclay were fabricated, in order to be utilized as dielectric materials of the organic thin film transistor (OTFT). Spin coating condition of the nanocomposite solution was examined considering shear viscosity of the composite materials dissolved in chloroform. Intercalated structure of the PVAc/clay nanocomposites was characterized using both wide-angle X-ray diffraction and TEM. Fracture morphology of the composite film on silicon wafer was also observed by SEM. Dielectric constant (4.15) of the nanocomposite materials shows that the PVAc/clay nanocomposites are applicable for the gate dielectric materials.

Organ-on-a-Chip for Aerospace Physiology and Toxicology

DTIC Science & Technology

2014-12-15

Products (Chicago, IL) supplied the Laboratory Corona Treater. Silicon wafers, 3” with > orientation were obtained from Wafer World Incorporated...was flowed at a process pressure of 500 mT. The plasma was ignited at discharge power of 250 W at 30 kHz and allowed to run for 1 minute. The wafer...slide and PDMS channel surfaces was performed one of two ways. Either using a handheld corona tool operated in a chemical safety hood or the PDMS slabs

A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

NASA Technical Reports Server (NTRS)

Horowitz, Stephen; Chen, Tai-An; Chandrasekaran, Venkataraman; Tedjojuwono, Ken; Cattafesta, Louis; Nishida, Toshikazu; Sheplak, Mark

2004-01-01

This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Enhanced capture rate for haze defects in production wafer inspection

NASA Astrophysics Data System (ADS)

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

Nanostructured Porous Silicon: The Winding Road from Photonics to Cell Scaffolds – A Review

PubMed Central

Hernández-Montelongo, Jacobo; Muñoz-Noval, Alvaro; García-Ruíz, Josefa Predestinación; Torres-Costa, Vicente; Martín-Palma, Raul J.; Manso-Silván, Miguel

2015-01-01

For over 20 years, nanostructured porous silicon (nanoPS) has found a vast number of applications in the broad fields of photonics and optoelectronics, triggered by the discovery of its photoluminescent behavior in 1990. Besides, its biocompatibility, biodegradability, and bioresorbability make porous silicon (PSi) an appealing biomaterial. These properties are largely a consequence of its particular susceptibility to oxidation, leading to the formation of silicon oxide, which is readily dissolved by body fluids. This paper reviews the evolution of the applications of PSi and nanoPS from photonics through biophotonics, to their use as cell scaffolds, whether as an implantable substitute biomaterial, mainly for bony and ophthalmological tissues, or as an in vitro cell conditioning support, especially for pluripotent cells. For any of these applications, PSi/nanoPS can be used directly after synthesis from Si wafers, upon appropriate surface modification processes, or as a composite biomaterial. Unedited studies of fluorescently active PSi structures for cell culture are brought to evidence the margin for new developments. PMID:26029688

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

NASA Astrophysics Data System (ADS)

Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

2006-03-01

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

Remotely adjustable check-valves with an electrochemical release mechanism for implantable biomedical microsystems.

PubMed

Pan, Tingrui; Baldi, Antonio; Ziaie, Babak

2007-06-01

In this paper, we present two remotely adjustable check-valves with an electrochemical release mechanism for implantable biomedical microsystems. These valves allow one to vary the opening pressure set-point and flow resistance over a period of time. The first design consists of a micromachined check-valve array using a SU-8 polymer structural layer deposited on the top of a gold sacrificial layer. The second design is based on a variable length cantilever beam structure with a gold sacrificial layer. The adjustable cantilever-beam structure is fabricated by gold thermo-compression bond of a thin silicon wafer over a glass substrate. In both designs, the evaporated gold can be electrochemically dissolved using a constant DC current via a telemetry link. In the first design the dissolution simply opens up individual outlets, while in the second design, gold anchors are sequentially dissolved hence increasing the effective length of the cantilever beam (reducing the opening pressure). A current density of 35 mA/cm(2) is used to dissolve the gold sacrificial layers. Both gravity and syringe-pump driven flow are used to characterize the valve performance. A multi-stage fluidic performance (e.g. flow resistance and opening pressure) is clearly demonstrated.

Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

NASA Astrophysics Data System (ADS)

Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

2017-04-01

Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

NASA Astrophysics Data System (ADS)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

NASA Astrophysics Data System (ADS)

Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

2018-04-01

A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

NASA Astrophysics Data System (ADS)

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

PubMed

Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-17

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

PubMed Central

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-01-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

First 65nm tape-out using inverse lithography technology (ILT)

NASA Astrophysics Data System (ADS)

Hung, Chi-Yuan; Zhang, Bin; Tang, Deming; Guo, Eric; Pang, Linyong; Liu, Yong; Moore, Andrew; Wang, Kechang

2005-11-01

This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

NASA Astrophysics Data System (ADS)

Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

2018-01-01

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

Bunker, S.

1981-01-01

A solar cell junction processing system was developed and fabricated. A pulsed electron beam for the four inch wafers is being assembled and tested, wafers were successfully pulsed, and solar cells fabricated. Assembly of the transport locks is completed. The transport was operated successfully but not with sufficient reproducibility. An experiment test facility to examine potential scaleup problems associated with the proposed ion implanter design was constructed and operated. Cells were implanted and found to have efficiency identical to the normal Spire implant process.

Optical processing furnace with quartz muffle and diffuser plate

DOEpatents

Sopori, Bhushan L.

1995-01-01

An optical furnace for annealing a process wafer comprising a source of optical energy, a quartz muffle having a door to hold the wafer for processing, and a quartz diffuser plate to diffuse the light impinging on the quartz muffle; a feedback system with a light sensor located in the door or wall of the muffle is also provided for controlling the source of optical energy. The quartz for the diffuser plate is surface etched (to give the quartz diffusive qualities) in the furnace during a high intensity burn-in process.

Power MEMS Development

DTIC Science & Technology

2011-05-01

wafer pair through further processing. Initial cracking issues were identified due to liquid penetration between the wafers during wet processing...free-standing MCD films we needed to address crack formation in the diamond and the Si substrate, which we observed during our initial growths due to...NCD film grown using the heated stage, and finally the thick MCD film grown on the cooled stage. We also found that the control of cracking in the

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

PubMed

Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

2004-07-01

A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

NASA Astrophysics Data System (ADS)

Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

2016-03-01

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

NASA Astrophysics Data System (ADS)

Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

2010-10-01

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

Reduction of across-wafer CDU via constrained optimization of a multichannel PEB plate controller based on in-situ measurements of thermal time constants

NASA Astrophysics Data System (ADS)

Tiffany, Jason E.; Cohen, Barney M.

2004-05-01

As line widths approach 90nm node in volume production, post exposure bake (PEB) uniformity becomes a much larger component of the across wafer critical dimension uniformity (CDU). In production, the need for PEB plate matching has led to novel solutions such as plate specific dose offsets. This type of correction does not help across wafer CDU. Due to unequal activation energies of the critical PEB processes, any thermal history difference can result in a corresponding CD variation. The rise time of the resist to the target temperature has been shown to affect CD, with the most critical time being the first 5-7 seconds. A typical PEB plate has multi-zone thermal control with one thermal sensor per zone. The current practice is to setup each plate to match the steady-state target temperature, ignoring any dynamic performance. Using an in-situ wireless RTD wafer, it is possible to characterize the dynamic performance, or time constant, of each RTD location on the sensing wafer. Constrained by the zone structure of the PEB plate, the proportional, integral and derivative (PID) settings of each controller channel could be optimized to reduce the variations in rise time across the RTD wafer, thereby reducing the PEB component of across wafer CDU.

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

NASA Technical Reports Server (NTRS)

Finkbeiner, F. m.; Chervenak, J. A.; Bandler, S. R.; Brekosky, R.; Brown, A. D.; Figueroa-Feliciano, E.; Iyomoto, N.; Kelley, R. L.; Kilbourne, C. A.; Porter, F. S.;

Integral resonator gyroscope

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor); Challoner, A. Dorian (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor); Yee, Karl Y. (Inventor)

2008-01-01

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Method of producing an integral resonator sensor and case

NASA Technical Reports Server (NTRS)

Challoner, A. Dorian (Inventor); Yee, Karl Y. (Inventor); Shcheglov, Kirill V. (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor)

2005-01-01

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

NASA Astrophysics Data System (ADS)

Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

2003-09-01

The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

On-line photolithography modeling using spectrophotometry and Prolith/2

NASA Astrophysics Data System (ADS)

Engstrom, Herbert L.; Beacham, Jeanne E.

1994-05-01

Spectrophotometry has been applied to optimizing photolithography processes in semiconductor manufacturing. For many years thin film measurement systems have been used in manufacturing for controlling film deposition processes. The combination of film thickness mapping with photolithography modeling has expanded the applications of this technology. Experimental measurements of dose-to-clear, the minimum light exposure dose required to fully develop a photoresist, are described. It is shown how dose-to-clear and photoresist contrast may be determined rapidly and conveniently from measurements of a dose exposure matrix on a monitor wafer. Such experimental measurements may underestimate the dose-to- clear because of thickness variations of the photoresist and underlying layers on the product wafer. Online modeling of the photolithographic process together with film thickness maps of the entire wafer can overcome this problem. Such modeling also provides maps of dose-to- clear and resist linewidth that can be used to estimate and optimize yield.

Throughput increase by adjustment of the BARC drying time with coat track process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Long, Ryan

2005-05-01

Throughput of a coater module within the coater track is related to the solvent evaporation rate from the material that is being coated. Evaporation rate is controlled by the spin dynamics of the wafer and airflow dynamics over the wafer. Balancing these effects is the key to achieving very uniform coatings across a flat unpatterned wafer. As today"s coat tracks are being pushed to higher throughputs to match the scanner, the coat module throughput must be increased as well. For chemical manufacturers the evaporation rate of the material depends on the solvent used. One measure of relative evaporation rates is to compare flash points of a solvent. The lower the flash point, the quicker the solvent will evaporate. It is possible to formulate products with these volatile solvents although at a price. Shipping and manufacturing a more flammable product increase chances of fire, thereby increasing insurance premiums. Also, the end user of these chemicals will have to take extra precautions in the fab and in storage of these more flammable chemicals. An alternative coat process is possible which would allow higher throughput in a distinct coat module without sacrificing safety. A tradeoff is required for this process, that being a more complicated coat process and a higher viscosity chemical. The coat process uses the fact that evaporation rate depends on the spin dynamics of the wafer by utilizing a series of spin speeds that first would set the thickness of the material followed by a high spin speed to remove the residual solvent. This new process can yield a throughput of over 150 wafers per hour (wph) given two coat modules. The thickness uniformity of less than 2 nm (3 sigma) is still excellent, while drying times are shorter than 10 seconds to achieve the 150 wph throughput targets.

Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

NASA Astrophysics Data System (ADS)

Weatherwax Scott, Caroline; Tsareff, Christopher R.

1990-06-01

One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles played by the process engineering expert and the knowledge engineer are discussed. The features of the systems are shown, particularly the interactive quality of the consultations and the ease of system use.

Warpage Measurement of Thin Wafers by Reflectometry

NASA Astrophysics Data System (ADS)

Ng, Chi Seng; Asundi, Anand Krishna

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Structurally stable, thin silicon solar cells

NASA Technical Reports Server (NTRS)

Arndt, R. A.; Meulenberg, A.

1984-01-01

A fabrication process for structurally stable thin solar cell wafers that produce good power output after irradiation is described. The fabrication process is as follows. A 6 mil, circular wafer is oxidized on both sides. One side is then patterned with a rectangular array of holes in the oxide that are nominally 75 mils square and separated by 2 mil spacings. Wells are then etched into the silicon with KOH to a depth of 4 mils, leaving a 2 mil, unetched thickness. Two areas on the surface are left unetched to provide pads for bonding or testing. All oxide is then removed and the rest of the processing is normal; the unetched face is used as the illuminated face. When all other processing is complete, a 2 X 2 cm cell is sawed from the starting wafer leaving a border that is approximately 10 mils wide. The effective thickness, determined by weighing an unmetallized sample, of such a cell is about 2.4 mil.

Improving scanner wafer alignment performance by target optimization

NASA Astrophysics Data System (ADS)

Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

2016-03-01

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

Wafer-level colinearity monitoring for TFH applications

NASA Astrophysics Data System (ADS)

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

Wafer level reliability for high-performance VLSI design

NASA Technical Reports Server (NTRS)

Root, Bryan J.; Seefeldt, James D.

1987-01-01

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Carbon mediated reduction of silicon dioxide and growth of copper silicide particles in uniform width channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pizzocchero, Filippo; Bøggild, Peter; Booth, Timothy J.

We show that surface arc-discharge deposited carbon plays a critical intermediary role in the breakdown of thermally grown oxide diffusion barriers of 90 nm on a silicon wafer at 1035 °C in an Ar/H{sub 2} atmosphere, resulting in the formation of epitaxial copper silicide particles in ≈ 10 μm wide channels, which are aligned with the intersections of the (100) surface of the wafer and the (110) planes on an oxidized silicon wafer, as well as endotaxial copper silicide nanoparticles within the wafer bulk. We apply energy dispersive x-ray spectroscopy, in combination with scanning and transmission electron microscopy of focusedmore » ion beam fabricated lammelas and trenches in the structure to elucidate the process of their formation.« less

Process tool monitoring and matching using interferometry technique

NASA Astrophysics Data System (ADS)

Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

The opportunity and challenge of spin coat based nanoimprint lithography

NASA Astrophysics Data System (ADS)

Jung, Wooyung; Cho, Jungbin; Choi, Eunhyuk; Lim, Yonghyun; Bok, Cheolkyu; Tsuji, Masatoshi; Kobayashi, Kei; Kono, Takuya; Nakasugi, Tetsuro

2017-03-01

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Charge-carrier relaxation in sonochemically fabricated dendronized CaSiO3-SiO2-Si nanoheterostructures

NASA Astrophysics Data System (ADS)

Savkina, Rada; Smirnov, Aleksey; Kirilova, Svitlana; Shmid, Volodymyr; Podolian, Artem; Nadtochiy, Andriy; Odarych, Volodymyr; Korotchenkov, Oleg

2018-04-01

We present systematic studies of charge-carrier relaxation processes in sonochemically nanostructured silicon wafers. Impedance spectroscopy and transient photovoltage techniques are employed. It is found that interface potential in Si wafers remarkably increases upon their exposure to sonochemical treatments in Ca-rich environments. In contrast, the density of fast interface electron states remains almost unchanged. It is found that the initial photovoltage decay, taken before ultrasonic treatments, exhibits the involvement of shorter- and longer time recombination and trapping centers. The decay speeds up remarkably due to cavitation treatments, which is accompanied by a substantial quenching of the photovoltage magnitude. It is also found that, before the treatments, the photovoltage magnitude is markedly non-uniform over the wafer surface, implying the existence of distributed sites affecting distribution of photoexcited carriers. The treatments cause an overall broadening of the photovoltage distribution. Furthermore, impedance measurements monitor the progress in surface structuring relevant to several relaxation processes. We believe that sonochemical nanostructuring of silicon wafers with dendronized CaSiO3 may enable new promising avenue towards low-cost solar energy efficiency multilayered solar cell device structures.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Iles, P. A.; Leung, D. C.

1982-01-01

For UCP Si, randomly selected wafers and wafers cut from two specific ingots were studied. For the randomly selected wafers, a moderate gettering diffusion had little effect. Moreover, an efficiency up to 14% AMI was achieved with advanced processes. For the two specific UCP ingots, ingot #5848-13C displayed severe impurity effects as shown by lower 3sc in the middle of the ingot and low CFF in the top of the ingot. Also the middle portions of this ingot responded to a series of progressively more severe gettering diffusion. Unexplained was the fact that severely gettered samples of this ingot displayed a negative light biased effect on the minority carrier diffusion length while the nongettered or moderately gettered ones had the more conventional positive light biased effect on diffusion length. On the other hand, ingot C-4-21A did not have the problem of ingot 5848-13C and behaved like to the randomly selected wafers. The top half of the ingot was shown to be slightly superior to the bottom half, but moderate gettering helped to narrow the gap.

Wafer-shape metrics based foundry lithography

NASA Astrophysics Data System (ADS)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Interactions of double patterning technology with wafer processing, OPC and design flows

NASA Astrophysics Data System (ADS)

Lucas, Kevin; Cork, Chris; Miloslavsky, Alex; Luk-Pat, Gerry; Barnes, Levi; Hapli, John; Lewellen, John; Rollins, Greg; Wiaux, Vincent; Verhaegen, Staf

2008-03-01

Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

CZT sensors for Computed Tomography: from crystal growth to image quality

NASA Astrophysics Data System (ADS)

Iniewski, K.

2016-12-01

Recent advances in Traveling Heater Method (THM) growth and device fabrication that require additional processing steps have enabled to dramatically improve hole transport properties and reduce polarization effects in Cadmium Zinc Telluride (CZT) material. As a result high flux operation of CZT sensors at rates in excess of 200 Mcps/mm2 is now possible and has enabled multiple medical imaging companies to start building prototype Computed Tomography (CT) scanners. CZT sensors are also finding new commercial applications in non-destructive testing (NDT) and baggage scanning. In order to prepare for high volume commercial production we are moving from individual tile processing to whole wafer processing using silicon methodologies, such as waxless processing, cassette based/touchless wafer handling. We have been developing parametric level screening at the wafer stage to ensure high wafer quality before detector fabrication in order to maximize production yields. These process improvements enable us, and other CZT manufacturers who pursue similar developments, to provide high volume production for photon counting applications in an economically feasible manner. CZT sensors are capable of delivering both high count rates and high-resolution spectroscopic performance, although it is challenging to achieve both of these attributes simultaneously. The paper discusses material challenges, detector design trade-offs and ASIC architectures required to build cost-effective CZT based detection systems. Photon counting ASICs are essential part of the integrated module platforms as charge-sensitive electronics needs to deal with charge-sharing and pile-up effects.

Overlay leaves litho: impact of non-litho processes on overlay and compensation

NASA Astrophysics Data System (ADS)

Ruhm, Matthias; Schulz, Bernd; Cotte, Eric; Seltmann, Rolf; Hertzsch, Tino

2014-10-01

According to the ITRS roadmap [1], the overlay requirement for the 28nm node is 8nm. If we compare this number with the performance given by tool vendors for their most advanced immersion systems (which is < 3nm), there seems to remain a large margin. Does that mean that today's leading edge Fab has an easy life? Unfortunately not, as other contributors affecting overlay are emerging. Mask contributions and so-called non-linear wafer distortions are known effects that can impact overlay quite significantly. Furthermore, it is often forgotten that downstream (post-litho) processes can impact the overlay as well. Thus, it can be required to compensate for the effects of subsequent processes already at the lithography operation. Within our paper, we will briefly touch on the wafer distortion topic and discuss the limitations of lithography compensation techniques such as higher order corrections versus solving the root cause of the distortions. The primary focus will be on the impact of the etch processes on the pattern placement error. We will show how individual layers can get affected differently by showing typical wafer signatures. However, in contrast to the above-mentioned wafer distortion topic, lithographic compensation techniques can be highly effective to reduce the placement error significantly towards acceptable levels (see Figure 1). Finally we will discuss the overall overlay budget for a 28nm contact to gate case by taking the impact of the individual process contributors into account.

Advances in photonic MOEMS-MEMS device thinning and polishing

NASA Astrophysics Data System (ADS)

McAneny, James J.; Kennedy, Mark; McGroggan, Tom

2010-02-01

As devices continue to increase in density and complexity, ever more stringent specifications are placed on the wafer scale equipment manufacturers to produce higher quality and higher output. This results in greater investment and more resource being diverted into producing tools and processes which can meet the latest demanding criteria. Substrate materials employed in the fabrication process range from Silicon through InP and include GaAs, InSb and other optical networking or waveguide materials. With this diversity of substrate materials presented, controlling the geometries and surfaces grows progressively more challenging. This article highlights the key parameters which require close monitoring and control in order to produce highly precise wafers as part of the fabrication process. Several as cut and commercially available standard polished wafer materials were used in empirical trials to test tooling options in generating high levels of geometric control over the dimensions while producing high quality surface finishes. Specific attention was given to the measurement and control of: flatness; parallelism/TTV; surface roughness and final target thickness as common specifications required by the industry. By combining the process variables of: plate speed, download pressure, slurry flow rate and concentration, pad type and wafer travel path across the polish pad, the effect of altering these variables was recorded and analysed to realize the optimum process conditions for the materials under test. The results being then used to design improved methods and tooling for the thinning and polishing of photonic materials applied to MOEMS-MEMS device fabrication.

Overlay degradation induced by film stress

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Luo, Shing-Ann; Yang, Mars; Yang, Elvis; Hung, Yung-Tai; Luoh, Tuung; Yang, T. H.; Chen, K. C.

2017-03-01

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn't directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

A Summary of Lightpipe Radiation Thermometry Research at NIST

PubMed Central

Tsai, Benjamin K.

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed. PMID:27274914

A Summary of Lightpipe Radiation Thermometry Research at NIST.

PubMed

Tsai, Benjamin K

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed.

Plasma etched surface scanning inspection recipe creation based on bidirectional reflectance distribution function and polystyrene latex spheres

NASA Astrophysics Data System (ADS)

Saldana, Tiffany; McGarvey, Steve; Ayres, Steve

2014-04-01

The continual increasing demands upon Plasma Etching systems to self-clean and continue Plasma Etching with minimal downtime allows for the examination of SiCN, SiO2 and SiN defectivity based upon Surface Scanning Inspection Systems (SSIS) wafer scan results. Historically all Surface Scanning Inspection System wafer scanning recipes have been based upon Polystyrene Spheres wafer deposition for each film stack and the subsequent creation of light scattering sizing response curves. This paper explores the feasibility of the elimination of Polystyrene Latex Sphere (PSL) and/or process particle deposition on both filmed and bare Silicon wafers prior to Surface Scanning Inspection System recipe creation. The study will explore the theoretical maximal Surface Scanning Inspection System sensitivity based on PSL recipe creation in conjunction with the maximal sensitivity derived from Bidirectional Reflectance Distribution Function (BRDF) maximal sensitivity modeling recipe creation. The surface roughness (Root Mean Square) of plasma etched wafers varies dependent upon the process film stack. Decrease of the root mean square value of the wafer sample surface equates to higher surface scanning inspection system sensitivity. Maximal sensitivity SSIS scan results from bare and filmed wafers inspected with recipes created based upon Polystyrene/Particle Deposition and recipes created based upon BRDF modeling will be overlaid against each other to determine maximal sensitivity and capture rate for each type of recipe that was created with differing recipe creation modes. A statistically valid sample of defects from each Surface Scanning Inspection system recipe creation mode and each bare wafer/filmed substrate will be reviewed post SSIS System processing on a Defect Review Scanning Electron Microscope (DRSEM). Native defects, Polystyrene Latex Spheres will be collected from each statistically valid defect bin category/size. The data collected from the DRSEM will be utilized to determine the maximum sensitivity capture rate for each recipe creation mode. Emphasis will be placed upon the sizing accuracy of PSL versus BRDF modeling results based upon automated DRSEM defect sizing. An examination the scattering response for both Mie and Rayleigh will be explored in relationship to the reported sizing variance of the SSIS to make a determination of the absolute sizing accuracy of the recipes there were generated based upon BRDF modeling. This paper explores both the commercial and technical considerations of the elimination of PSL deposition as a precursor to SSIS recipe creation. Successful integration of BRDF modeling into the technical aspect of SSIS recipe creation process has the potential to dramatically reduce the recipe creation timeline and vetting period. Integration of BRDF modeling has the potential to greatly reduce the overhead operation costs for High Volume Manufacturing sites by eliminating the associated costs of third party PSL deposition.

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

NASA Technical Reports Server (NTRS)

Anthony, Thomas R. (Inventor)

1983-01-01

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Beyond G-band : a 235 GHz InP MMIC amplifier

NASA Technical Reports Server (NTRS)

Dawson, Douglas; Samoska, Lorene; Fung, A. K.; Lee, Karen; Lai, Richard; Grundbacher, Ronald; Liu, Po-Hsin; Raja, Rohit

2005-01-01

We present results on an InP monolithic millimeter- wave integrated circuit (MMIC) amplifier having 10-dB gain at 235 GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technology's (NGST) 0.07- m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325 GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for -parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230 GHz.

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1993-01-01

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Characterization of Atomic-Layer-Deposited (ALD) Al2O3-Passivated Sub-50-μm-thick Kerf-less Si Wafers by Controlled Spalling

NASA Astrophysics Data System (ADS)

Lee, Yong Hwan; Cha, Hamchorom; Choi, Sunho; Chang, Hyo Sik; Jang, Boyun; Oh, Jihun

2018-05-01

A systematic characterization of sub-50-μm-thick, kerf-less monocrystalline Si wafers fabricated by a controlled fracture method is presented. The spalling process introduces various defects on the Si surface, which result in high surface roughness levels, residual stress, and low effective minority carrier lifetimes. In addition, metals used to induce fracturing in Si diffuse in the Si at room temperature and degrade the effective minority carrier lifetime. Selective removal of these defected Si regions improves the residual stress and effective lifetimes of spalled Si wafers.

Calligraphic Poling of Ferroelectric Material

NASA Technical Reports Server (NTRS)

Mohageg, Makan; Strekalov, Dmitry; Savchenkov, Anatoliy; Matsko, Adrey; Maleki, Lute; Iltchenko, Vladimir

2007-01-01

Calligraphic poling is a technique for generating an arbitrary, possibly complex pattern of localized reversal in the direction of permanent polarization in a wafer of LiNbO3 or other ferroelectric material. The technique is so named because it involves a writing process in which a sharp electrode tip is moved across a surface of the wafer to expose the wafer to a polarizing electric field in the desired pattern. The technique is implemented by use of an apparatus, denoted a calligraphic poling machine (CPM), that includes the electrode and other components as described in more detail below.

Strain Engineering of Epitaxially Transferred, Ultrathin Layers of III-V Semiconductor on Insulator

DTIC Science & Technology

2011-01-01

The structure of the source wafer is shown schematically in Fig. 2a, with both InAs and AlGaSb layers coherently strained to the GaSb 001...is due to the surface plasmon-LO phonon FIG. 2. Color online a The structure of GaSb /AlGaSb/InAs source wafer with an assumed strain state for...insulator layers obtained from an epitaxial transfer process is studied. The as-grown InAs epilayer 10–20 nm thick on the GaSb /AlGaSb source wafer has the

WAMA: a method of optimizing reticle/die placement to increase litho cell productivity

NASA Astrophysics Data System (ADS)

Dor, Amos; Schwarz, Yoram

2005-05-01

This paper focuses on reticle/field placement methodology issues, the disadvantages of typical methods used in the industry, and the innovative way that the WAMA software solution achieves optimized placement. Typical wafer placement methodologies used in the semiconductor industry considers a very limited number of parameters, like placing the maximum amount of die on the wafer circle and manually modifying die placement to minimize edge yield degradation. This paper describes how WAMA software takes into account process characteristics, manufacturing constraints and business objectives to optimize placement for maximum stepper productivity and maximum good die (yield) on the wafer.

Wafer plane inspection with soft resist thresholding

NASA Astrophysics Data System (ADS)

Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

2008-10-01

Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just finishing beta testing with a customer developing advanced node designs.

Influence of Si wafer thinning processes on (sub)surface defects

NASA Astrophysics Data System (ADS)

Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

2017-05-01

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

NASA Technical Reports Server (NTRS)

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Epitaxial gallium arsenide wafers

NASA Technical Reports Server (NTRS)

Black, J. F.; Robinson, L. B.

1971-01-01

The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Semiconductor Laser Joint Study Program with Rome Laboratory

DTIC Science & Technology

1994-09-01

VCSELs 3.3 Laser Wafer Growth by Molecular Beam Epitaxy 8 The VCSEL structures were grown by molecular beam ...cavity surface emittimg lasers ( VCSEL ), Optical 40 interconnects, Moelcular beam epitaxy It CECOOE 17. SECURfTY CLASWICATION SECURFlY CLASSIFICATION 1 Q...7 3.3 Laser Wafer Growth by Molecular Beam Epitax. ............ 8 3.4 VCSEL Fabrication Process ................................................

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Commercial silicon-on-insulator (SOI) wafers as a versatile substrate for laser desorption/ionization mass spectrometry.

PubMed

Kim, Shin Hye; Kim, Jeongkwon; Moon, Dae Won; Han, Sang Yun

2013-01-01

We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.

Pulse plating of Pt on n-GaAs ( 1 0 0 ) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

NASA Astrophysics Data System (ADS)

Ensling, D.; Hunger, R.; Kraft, D.; Mayer, Th.; Jaegermann, W.; Rodriguez-Girones, M.; Ichizli, V.; Hartnagel, H. L.

2003-01-01

Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation of hν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH 3 etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered.

Reducing the substrate dependent scanner leveling effect in low-k1 contact printing

NASA Astrophysics Data System (ADS)

Chang, C. S.; Tseng, C. F.; Huang, C. H.; Yang, Elvis; Yang, T. H.; Chen, K. C.

2015-03-01

As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure. In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn't get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn't show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.

Results Of Automating A Photolithography Cell In A Clean Tunnel

NASA Astrophysics Data System (ADS)

June, David H.

1987-01-01

A prototype automated photobay was installed in an existing fab area utilizing flexible material handling techniques within a clean tunnel. The project objective was to prove design concepts of automated cassette-to-cassette handling within a clean tunnel that isolated operators from the wafers being processed. Material handling was by monorail track transport system to feed cassettes to pick and place robots. The robots loaded and unloaded cassettes of wafers to each of the various pieces of process equipment. The material handling algorithms, recipe downloading and statistical process control functions were all performed by custom software on the photobay cell controller.

Material removal effect of microchannel processing by femtosecond laser

NASA Astrophysics Data System (ADS)

Zhang, Pan; Chen, Lei; Chen, Jianxiong; Tu, Yiliu

2017-11-01

Material processing using ultra-short-pulse laser is widely used in the field of micromachining, especially for the precision processing of hard and brittle materials. This paper reports a theoretical and experimental study of the ablation characteristics of a silicon wafer under micromachining using a femtosecond laser. The ablation morphology of the silicon wafer surface is surveyed by a detection test with an optical microscope. First, according to the relationship between the diameter of the ablation holes and the incident laser power, the ablation threshold of the silicon wafer is found to be 0.227 J/cm2. Second, the influence of various laser parameters on the size of the ablation microstructure is studied and the ablation morphology is analyzed. Furthermore, a mathematical model is proposed that can calculate the ablation depth per time for a given laser fluence and scanning velocity. Finally, a microchannel milling test is carried out on the micromachining center. The effectiveness and accuracy of the proposed models are verified by comparing the estimated depth to the actual measured results.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

A Lorentz force actuated magnetic field sensor with capacitive read-out

NASA Astrophysics Data System (ADS)

Stifter, M.; Steiner, H.; Kainz, A.; Keplinger, F.; Hortschitz, W.; Sauter, T.

2013-05-01

We present a novel design of a resonant magnetic field sensor with capacitive read-out permitting wafer level production. The device consists of a single-crystal silicon cantilever manufactured from the device layer of an SOI wafer. Cantilevers represent a very simple structure with respect to manufacturing and function. On the top of the structure, a gold lead carries AC currents that generate alternating Lorentz forces in an external magnetic field. The free end oscillation of the actuated cantilever depends on the eigenfrequencies of the structure. Particularly, the specific design of a U-shaped structure provides a larger force-to-stiffness-ratio than standard cantilevers. The electrodes for detecting cantilever deflections are separately fabricated on a Pyrex glass-wafer. They form the counterpart to the lead on the freely vibrating planar structure. Both wafers are mounted on top of each other. A custom SU-8 bonding process on wafer level creates a gap which defines the equilibrium distance between sensing electrodes and the vibrating structure. Additionally to the capacitive read-out, the cantilever oscillation was simultaneously measured with laser Doppler vibrometry through proper windows in the SOI handle wafer. Advantages and disadvantages of the asynchronous capacitive measurement configuration are discussed quantitatively and presented by a comprehensive experimental characterization of the device under test.

Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

Relation between sick leave and selected exposure variables among women semiconductor workers in Malaysia

PubMed Central

Chee, H; Rampal, K

2003-01-01

Aims: To determine the relation between sick leave and selected exposure variables among women semiconductor workers. Methods: This was a cross sectional survey of production workers from 18 semiconductor factories. Those selected had to be women, direct production operators up to the level of line leader, and Malaysian citizens. Sick leave and exposure to physical and chemical hazards were determined by self reporting. Three sick leave variables were used; number of sick leave days taken in the past year was the variable of interest in logistic regression models where the effects of age, marital status, work task, work schedule, work section, and duration of work in factory and work section were also explored. Results: Marital status was strongly linked to the taking of sick leave. Age, work schedule, and duration of work in the factory were significant confounders only in certain cases. After adjusting for these confounders, chemical and physical exposures, with the exception of poor ventilation and smelling chemicals, showed no significant relation to the taking of sick leave within the past year. Work section was a good predictor for taking sick leave, as wafer polishing workers faced higher odds of taking sick leave for each of the three cut off points of seven days, three days, and not at all, while parts assembly workers also faced significantly higher odds of taking sick leave. Conclusion: In Malaysia, the wafer fabrication factories only carry out a limited portion of the work processes, in particular, wafer polishing and the processes immediately prior to and following it. This study, in showing higher illness rates for workers in wafer polishing compared to semiconductor assembly, has implications for the governmental policy of encouraging the setting up of wafer fabrication plants with the full range of work processes. PMID:12660374

Consideration of correlativity between litho and etching shape

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Shinoda, Shinichi; Toyoda, Yasutaka

2012-03-01

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

Reducing bottom anti-reflective coating (BARC) defects: optimizing and decoupling the filtration and dispense process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Martin, Gary; Simmons, Sean; Batchelder, Traci

2006-03-01

Semiconductor device manufacturing is one of the cleanest manufacturing operations that can be found in the world today. It has to be that way; a particle on a wafer today can kill an entire device, which raises the costs, and therefore reduces the profits, of the manufacturing company in two ways: it must produce extra wafers to make up for the lost die, and it has less product to sell. In today's state-of-the-art fab, everything is filtered to the lowest pore size available. This practice is fairly easy for gases because a gas molecule is very small compared to the pore size of the filter. Filtering liquids, especially photochemicals such as photoresists and BARCs, can be much harder because the molecules that form the polymers used to manufacture the photochemicals are approaching the filter pore size. As a result, filters may plug up, filtration rates may drop, pressure drops across the filter may increase, or a filter may degrade. These conditions can then cause polymer shearing, microbubble formation, gel particle formation, and BARC chemical changes to occur before the BARC reaches the wafer. To investigate these possible interactions, an Entegris(R) IntelliGen(R) pump was installed on a TEL Mk8 TM track to see if the filtration process would have an effect on the BARC chemistry and coating defects. Various BARC chemicals such as DUV112 and DUV42P were pumped through various filter media having a variety of pore sizes at different filtration rates to investigate the interaction between the dispense process and the filtration process. The IntelliGen2 pump has the capability to filter the BARC independent of the dispense process. By using a designed experiment to look at various parameters such as dispense rate, filtration rate, and dispense volume, the effects of the complete pump system can be learned, and appropriate conditions can be applied to yield the cleanest BARC coating process. Results indicate that filtration rate and filter pore size play a dramatic role in the defect density on a coated wafer with the actual dispense properties such as dispense wafer speed and dispense time playing a lesser role.

Chemical vapor deposition of epitaxial silicon

DOEpatents

Berkman, Samuel

1984-01-01

A single chamber continuous chemical vapor deposition (CVD) reactor is described for depositing continuously on flat substrates, for example, epitaxial layers of semiconductor materials. The single chamber reactor is formed into three separate zones by baffles or tubes carrying chemical source material and a carrier gas in one gas stream and hydrogen gas in the other stream without interaction while the wafers are heated to deposition temperature. Diffusion of the two gas streams on heated wafers effects the epitaxial deposition in the intermediate zone and the wafers are cooled in the final zone by coolant gases. A CVD reactor for batch processing is also described embodying the deposition principles of the continuous reactor.

Computational metrology: enabling full-lot high-density fingerprint information without adding wafer metrology budget, and driving improved monitoring and process control

NASA Astrophysics Data System (ADS)

Kim, Hyun-Sok; Hyun, Min-Sung; Ju, Jae-Wuk; Kim, Young-Sik; Lambregts, Cees; van Rhee, Peter; Kim, Johan; McNamara, Elliott; Tel, Wim; Böcker, Paul; Oh, Nang-Lyeom; Lee, Jun-Hyung

2018-03-01

Computational metrology has been proposed as the way forward to resolve the need for increased metrology density, resulting from extending correction capabilities, without adding actual metrology budget. By exploiting TWINSCAN based metrology information, dense overlay fingerprints for every wafer can be computed. This extended metrology dataset enables new use cases, such as monitoring and control based on fingerprints for every wafer of the lot. This paper gives a detailed description, discusses the accuracy of the fingerprints computed, and will show results obtained in a DRAM HVM manufacturing environment. Also an outlook for improvements and extensions will be shared.

Sputtered Thin Film Research

DTIC Science & Technology

1974-11-01

yield (100) oriented wafers, which were lapped and chemi-mechanically polished in sulf uric-peroxide or sodium hypochlorite etches. Prior to mounting...This material will viot oxidize, melt, or diffuse during the subsequent high temperature processing. Platinum silicide contacts are used because...formation of the platinum silicide contacts, the gate region was opened and the wafer was placed in the sput- tering chamber. The same deposition

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2005-01-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2004-12-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Modifications of Fabrication of Vibratory Microgyroscopes

NASA Technical Reports Server (NTRS)

Bae, Sam Y.; Yee, Karl Y.; Wiberg, Dean

2005-01-01

A micromachining process for the fabrication of vibratory microgyroscopes from silicon wafers, and aspects of the microgyroscope design that are inextricably linked with the fabrication process, have been modified in an effort to increase production yields from perspectives of both quantity and quality. Prior to the modifications, the effective production yield of working microgyroscopes was limited to one or less per wafer. The modifications are part of a continuing effort to improve the design and increase production yields to more than 30 working microgyroscopes per wafer. A discussion of pertinent aspects of the unmodified design and the unmodified fabrication process is prerequisite to a meaningful description of the modifications. The design of the microgyroscope package was not conducive to high yield and rapid testing of many microgyroscopes. One of the major impediments to high yield and testing was found to lie in vibration- isolation beams around the four edges of each microgyroscope, which beams were found to be unnecessary for achieving high resonance quality factors (Q values) characterizing the vibrations of petallike cantilevers. The fabrication process included an 8- m-deep plasma etch. The purpose of the etch was to create 8- m vertical gaps, below which were to be placed large gold evaporated electrodes and sensing pads to drive and sense resonant vibrations of the "petals." The process also included a step in which bridges between dies were cut to separate the dies. The etched areas must be kept clean and smooth (free of debris and spikes), because any object close to 8 m high in those areas would stop the vibrations. However, it was found that after the etch, there remained some spikes with heights that were, variously, almost as high or as high as the etch depth. It also was found that the cutting of bridges created silicon debris, some of which lodged in the 8- m gaps and some of which landed on top of the petals. The masses added to the petals by the debris altered resonance frequencies and/or Q values to unacceptable degrees. Hence, the spikes and the debris have been conjectured to cause most of the observed malfunctions of newly fabricated microgyroscopes. Another pertinent aspect of the unmodified design and process was the fabrication of electrodes and the 8- m capacitance gap on a 500- m-thick wafer, and the fabrication of a 3-mm-thick baseplate from another wafer. It was necessary to bond these wafers to each other in an assembly step that was later found to be superfluous in that it could be eliminated by a suitable modification of the design.

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

NASA Astrophysics Data System (ADS)

Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

2015-03-01

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

PubMed

Nativ, Amit; Feldman, Haim; Shaked, Natan T

2018-05-01

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

NASA Astrophysics Data System (ADS)

Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

2016-04-01

A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

Process Performance of Optima XEx Single Wafer High Energy Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.

2011-01-07

To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstreammore » dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.« less

Development of graphene process control by industrial optical spectroscopy setup

NASA Astrophysics Data System (ADS)

Fursenko, O.; Lukosius, M.; Lupina, G.; Bauer, J.; Villringer, C.; Mai, A.

2017-06-01

The successful integration of graphene into microelectronic devices depends strongly on the availability of fast and nondestructive characterization methods of graphene grown by CVD on large diameter production wafers [1-3] which are in the interest of the semiconductor industry. Here, a high-throughput optical metrology method for measuring the thickness and uniformity of large-area graphene sheets is demonstrated. The method is based on the combination of spectroscopic ellipsometry and normal incidence reflectometry in UV-Vis wavelength range (200-800 nm) with small light spots ( 30 μm2) realized in wafer optical metrology tool. In the first step graphene layers were transferred on a SiO2/Si substrate in order to determine the optical constants of graphene by the combination of multi-angle ellipsometry and reflectometry. Then these data were used for the development of a process control recipe of CVD graphene on 200 mm Ge(100)/Si(100) wafers. The graphene layer quality was additionally monitored by Raman spectroscopy. Atomic force microscopy measurements were performed for micro topography evaluation. In consequence, a robust recipe for unambiguous thickness monitoring of all components of a multilayer film stack, including graphene, surface residuals or interface layer underneath graphene and surface roughness is developed. Optical monitoring of graphene thickness uniformity over a wafer has shown an excellent long term stability (s=0.004 nm) regardless of the growth of interfacial GeO2 and surface roughness. The sensitivity of the optical identification of graphene during microelectronic processing was evaluated. This optical metrology technique with combined data collection exhibit a fast and highly precise method allowing one an unambiguous detection of graphene after transferring as well as after the CVD deposition process on a Ge(100)/Si(100) wafer. This approach is well suited for industrial applications due to its repeatability and flexibility.

ArF scanner performance improvement by using track integrated CD optimization

NASA Astrophysics Data System (ADS)

Huang, Jacky; Yu, Shinn-Sheng; Ke, Chih-Ming; Wu, Timothy; Wang, Yu-Hsi; Gau, Tsai-Sheng; Wang, Dennis; Li, Allen; Yang, Wenge; Kaoru, Araki

2006-03-01

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

Determination of the implantation dose in silicon wafers by X-ray fluorescence analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klockenkaemper, R.; Becker, M.; Bubert, H.

1990-08-01

The ion dose implanted in silicon wafers was determined by X-ray fluorescence analysis after the implantation process. As only near-surface layers below 1-{mu}m thickness were considered, the calibration could be carried out with external standards consisting of thin films of doped gelatine spread on pure wafers. Dose values for Cr and Co were determined between 4 {times} 10{sup 15} and 2 {times} 10{sup 17} atoms/cm{sup 2}, the detection limits being about 3 {times} 10{sup 14} atoms/cm{sup 2}. The results are precise and accurate apart from a residual scatter of less than 7%. This was confirmed by flame atomic absorption spectrometrymore » after volatilization of the silicon matrix as SiF{sub 4}. It was found that ion-current measurements carried out during the implantation process can have considerable systematic errors.« less

High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2015-03-01

While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

Uniform lateral etching of tungsten in deep trenches utilizing reaction-limited NF3 plasma process

NASA Astrophysics Data System (ADS)

Kofuji, Naoyuki; Mori, Masahito; Nishida, Toshiaki

2017-06-01

The reaction-limited etching of tungsten (W) with NF3 plasma was performed in an attempt to achieve the uniform lateral etching of W in a deep trench, a capability required by manufacturing processes for three-dimensional NAND flash memory. Reaction-limited etching was found to be possible at high pressures without ion irradiation. An almost constant etching rate that showed no dependence on NF3 pressure was obtained. The effect of varying the wafer temperature was also examined. A higher wafer temperature reduced the threshold pressure for reaction-limited etching and also increased the etching rate in the reaction-limited region. Therefore, the control of the wafer temperature is crucial to controlling the etching amount by this method. We found that the uniform lateral etching of W was possible even in a deep trench where the F radical concentration was low.

Investigation of hyper-NA scanner emulation for photomask CDU performance

NASA Astrophysics Data System (ADS)

Poortinga, Eric; Scheruebl, Thomas; Conley, Will; Sundermann, Frank

2007-02-01

As the semiconductor industry moves toward immersion lithography using numerical apertures above 1.0 the quality of the photomask becomes even more crucial. Photomask specifications are driven by the critical dimension (CD) metrology within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately, tolerances of device electrical properties drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process, and photomask quality. Tightening of photomask specifications is one mechanism for meeting the wafer CD targets. The challenge lies in determining how photomask level metrology results influence wafer level imaging performance. Can it be inferred that photomask level CD performance is the direct contributor to wafer level CD performance? With respect to phase shift masks, criteria such as phase and transmission control are generally tightened with each technology node. Are there other photomask relevant influences that effect wafer CD performance? A comprehensive study is presented supporting the use of scanner emulation based photomask CD metrology to predict wafer level within chip CD uniformity (CDU). Using scanner emulation with the photomask can provide more accurate wafer level prediction because it inherently includes all contributors to image formation related to the 3D topography such as the physical CD, phase, transmission, sidewall angle, surface roughness, and other material properties. Emulated images from different photomask types were captured to provide CD values across chip. Emulated scanner image measurements were completed using an AIMS TM45-193i with its hyper-NA, through-pellicle data acquisition capability including the Global CDU Map TM software option for AIMS TM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CDU data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using scanner emulation based photomask CD metrology.

Examining the free radical bonding mechanism of benzoquinone- and hydroquinone-methanol passivation of silicon surfaces

NASA Astrophysics Data System (ADS)

Kotulak, Nicole A.; Chen, Meixi; Schreiber, Nikolas; Jones, Kevin; Opila, Robert L.

2015-11-01

The surface passivation of p-benzoquinone (BQ) and hydroquinone (HQ) when dissolved in methanol (ME) has been examined through effective lifetime testing of crystalline silicon (c-Si) wafers treated with the aforementioned solutions. Changes in the availability of both photons and protons in the solutions were demonstrated to affect the level of passivation achieved. The requirement of both excess protons and ambient light exposure to maintain high effective lifetimes supports the presence of a free radical species that drives the surface passivation. Surface analysis suggests a 1:1 ratio of HQ-like bonds to methoxy bonds on the c-Si surface after treatment with a BQ/ME solution.

Thermally grown oxide and diffusions for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1979-01-01

A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.

Geometry-based across wafer process control in a dual damascene scenario

NASA Astrophysics Data System (ADS)

Krause, Gerd; Hofmann, Detlef; Habets, Boris; Buhl, Stefan; Gutsch, Manuela; Lopez-Gomez, Alberto; Thrun, Xaver

2018-03-01

Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.

The influence of flash lamp annealing on the minority carrier lifetime of Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Kissinger, G.; Kot, D.; Sattler, A.

2014-02-01

Flash lamp annealing of moderately B-doped CZ silicon wafers for 20 ms with a normalized irradiance of about 0.9 was used to efficiently suppress oxygen precipitation during subsequent thermal processing. In this way, the minority carrier lifetime measured at high injection level by microwave-detected photo-conductance decay (μ-PCD) was increased from about 30 microseconds to about 300 microseconds after a thermal process consisting of 780 °C 3 h + 1000 °C 16 h. The grown-in oxide precipitate nuclei were shrunken to a subcritical size during the flash lamp anneal which prevents further growth during subsequent thermal processing.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Temperature measuring device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lauf, R.J.; Bible, D.W.; Sohns, C.W.

1999-10-19

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

Temperature measuring device

DOEpatents

Lauf, Robert J.; Bible, Don W.; Sohns, Carl W.

1999-01-01

Systems and methods are described for a wireless instrumented silicon wafer that can measure temperatures at various points and transmit those temperature readings to an external receiver. The device has particular utility in the processing of semiconductor wafers, where it can be used to map thermal uniformity on hot plates, cold plates, spin bowl chucks, etc. without the inconvenience of wires or the inevitable thermal perturbations attendant with them.

Three-dimensional magnetic induction model of an octagonal edge-defined film-fed growth system

NASA Astrophysics Data System (ADS)

Rajendran, S.; Holmes, K.; Menna, A.

1994-03-01

Silicon wafers for the photovoltaic industry are produced by growing thin octagonal tubes by the edge-defined film-fed growth (EFG) process. The thermal origin of the wafer thickness variations was studied with a three-dimensional (3D) magnetic induction model. The implementation of the computer code and the significance of the computed results for improving the thickness uniformity are discussed.

Embossed Teflon AF Laminate Membrane Microfluidic Diaphragm Valves

NASA Technical Reports Server (NTRS)

Willis, Peter; Hunt, Brian; White,Victor; Grunthaner, Frank

2008-01-01

A microfluidic system has been designed to survive spaceflight and to function autonomously on the Martian surface. It manipulates microscopic quantities of liquid water and performs chemical analyses on these samples to assay for the presence of molecules associated with past or present living processes. This technology lies at the core of the Urey Instrument, which is scheduled for inclusion on the Pasteur Payload of the ESA ExoMars rover mission in 2013. Fabrication processes have been developed to make the microfabricated Teflon-AF microfluidic diaphragm pumps capable of surviving extreme temperature excursions before and after exposure to liquid water. Two glass wafers are etched with features and a continuous Teflon membrane is sandwiched between them (see figure). Single valves are constructed using this geometry. The microfabricated devices are then post processed by heating the assembled device while applying pneumatic pressure to force the Teflon diaphragm against the valve seat while it is softened. After cooling the device, the embossed membrane retains this new shape. This solves previous problems with bubble introduction into the fluid flow where deformations of the membrane at the valve seat occurred during device bonding at elevated temperatures (100-150 C). The use of laminated membranes containing commercial Teflon AF 2400 sheet sandwiched between spun Teflon AF 1600 layers performed best, and were less gas permeable than Teflon AF 1600 membranes on their own. Spinning Teflon AF 1600 solution (6 percent in FLOURINERT(Registered TradeMark) FC40 solvent, 3M Company) at 500 rpm for 1.5 seconds, followed by 1,000 rpm for 3 seconds onto Borofloat glass wafers, results in a 10-micron-thick film of extremely smooth Teflon AF. This spinning process is repeated several times on flat, blank, glass wafers in order to gradually build a thick, smooth membrane. After running this process at least five times, the wafer and Teflon coating are heated under vacuum at 220 C for one hour in order to drive off any residual solvent present in the composite film. After this, a second blank, glass wafer is brought down from above and the stack is held under vacuum at 3 atm mechanical pressure for ten 10 hours.

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Reducing the overlay metrology sensitivity to perturbations of the measurement stack

NASA Astrophysics Data System (ADS)

Zhou, Yue; Park, DeNeil; Gutjahr, Karsten; Gottipati, Abhishek; Vuong, Tam; Bae, Sung Yong; Stokes, Nicholas; Jiang, Aiqin; Hsu, Po Ya; O'Mahony, Mark; Donini, Andrea; Visser, Bart; de Ruiter, Chris; Grzela, Grzegorz; van der Laan, Hans; Jak, Martin; Izikson, Pavel; Morgan, Stephen

2017-03-01

Overlay metrology setup today faces a continuously changing landscape of process steps. During Diffraction Based Overlay (DBO) metrology setup, many different metrology target designs are evaluated in order to cover the full process window. The standard method for overlay metrology setup consists of single-wafer optimization in which the performance of all available metrology targets is evaluated. Without the availability of external reference data or multiwafer measurements it is hard to predict the metrology accuracy and robustness against process variations which naturally occur from wafer-to-wafer and lot-to-lot. In this paper, the capabilities of the Holistic Metrology Qualification (HMQ) setup flow are outlined, in particular with respect to overlay metrology accuracy and process robustness. The significance of robustness and its impact on overlay measurements is discussed using multiple examples. Measurement differences caused by slight stack variations across the target area, called grating imbalance, are shown to cause significant errors in the overlay calculation in case the recipe and target have not been selected properly. To this point, an overlay sensitivity check on perturbations of the measurement stack is presented for improvement of the overlay metrology setup flow. An extensive analysis on Key Performance Indicators (KPIs) from HMQ recipe optimization is performed on µDBO measurements of product wafers. The key parameters describing the sensitivity to perturbations of the measurement stack are based on an intra-target analysis. Using advanced image analysis, which is only possible for image plane detection of μDBO instead of pupil plane detection of DBO, the process robustness performance of a recipe can be determined. Intra-target analysis can be applied for a wide range of applications, independent of layers and devices.

Maskless wafer-level microfabrication of optical penetrating neural arrays out of soda-lime glass: Utah Optrode Array.

PubMed

Boutte, Ronald W; Blair, Steve

2016-12-01

Borrowing from the wafer-level fabrication techniques of the Utah Electrode Array, an optical array capable of delivering light for neural optogenetic studies is presented in this paper: the Utah Optrode Array. Utah Optrode Arrays are micromachined out of sheet soda-lime-silica glass using standard backend processes of the semiconductor and microelectronics packaging industries such as precision diamond grinding and wet etching. 9 × 9 arrays with 1100μ m × 100μ m optrodes and a 500μ m back-plane are repeatably reproduced on 2i n wafers 169 arrays at a time. This paper describes the steps and some of the common errors of optrode fabrication.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

Wafer-level manufacturing technology of glass microlenses

NASA Astrophysics Data System (ADS)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Extension of optical lithography by mask-litho integration with computational lithography

NASA Astrophysics Data System (ADS)

Takigawa, T.; Gronlund, K.; Wiley, J.

2010-05-01

Wafer lithography process windows can be enlarged by using source mask co-optimization (SMO). Recently, SMO including freeform wafer scanner illumination sources has been developed. Freeform sources are generated by a programmable illumination system using a micro-mirror array or by custom Diffractive Optical Elements (DOE). The combination of freeform sources and complex masks generated by SMO show increased wafer lithography process window and reduced MEEF. Full-chip mask optimization using source optimized by SMO can generate complex masks with small variable feature size sub-resolution assist features (SRAF). These complex masks create challenges for accurate mask pattern writing and low false-defect inspection. The accuracy of the small variable-sized mask SRAF patterns is degraded by short range mask process proximity effects. To address the accuracy needed for these complex masks, we developed a highly accurate mask process correction (MPC) capability. It is also difficult to achieve low false-defect inspections of complex masks with conventional mask defect inspection systems. A printability check system, Mask Lithography Manufacturability Check (M-LMC), is developed and integrated with 199-nm high NA inspection system, NPI. M-LMC successfully identifies printable defects from all of the masses of raw defect images collected during the inspection of a complex mask. Long range mask CD uniformity errors are compensated by scanner dose control. A mask CD uniformity error map obtained by mask metrology system is used as input data to the scanner. Using this method, wafer CD uniformity is improved. As reviewed above, mask-litho integration technology with computational lithography is becoming increasingly important.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Implications of the Differential Toxicological Effects of III-V Ionic and Particulate Materials for Hazard Assessment of Semiconductor Slurries.

PubMed

Jiang, Wen; Lin, Sijie; Chang, Chong Hyun; Ji, Zhaoxia; Sun, Bingbing; Wang, Xiang; Li, Ruibin; Pon, Nanetta; Xia, Tian; Nel, André E

2015-12-22

Because of tunable band gaps, high carrier mobility, and low-energy consumption rates, III-V materials are attractive for use in semiconductor wafers. However, these wafers require chemical mechanical planarization (CMP) for polishing, which leads to the generation of large quantities of hazardous waste including particulate and ionic III-V debris. Although the toxic effects of micron-sized III-V materials have been studied in vivo, no comprehensive assessment has been undertaken to elucidate the hazardous effects of submicron particulates and released III-V ionic components. Since III-V materials may contribute disproportionately to the hazard of CMP slurries, we obtained GaP, InP, GaAs, and InAs as micron- (0.2-3 μm) and nanoscale (<100 nm) particles for comparative studies of their cytotoxic potential in macrophage (THP-1) and lung epithelial (BEAS-2B) cell lines. We found that nanosized III-V arsenides, including GaAs and InAs, could induce significantly more cytotoxicity over a 24-72 h observation period. In contrast, GaP and InP particulates of all sizes as well as ionic GaCl3 and InCl3 were substantially less hazardous. The principal mechanism of III-V arsenide nanoparticle toxicity is dissolution and shedding of toxic As(III) and, to a lesser extent, As(V) ions. GaAs dissolves in the cell culture medium as well as in acidifying intracellular compartments, while InAs dissolves (more slowly) inside cells. Chelation of released As by 2,3-dimercapto-1-propanesulfonic acid interfered in GaAs toxicity. Collectively, these results demonstrate that III-V arsenides, GaAs and InAs nanoparticles, contribute in a major way to the toxicity of III-V materials that could appear in slurries. This finding is of importance for considering how to deal with the hazard potential of CMP slurries.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

CMUT Fabrication Based On A Thick Buried Oxide Layer.

PubMed

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O; Khuri-Yakub, Butrus T

2010-10-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required - in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

PubMed

Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

2017-07-25

It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

Process margin enhancement for 0.25-μm metal etch process

NASA Astrophysics Data System (ADS)

Lee, Chung Y.; Ma, Wei Wen; Lim, Eng H.; Cheng, Alex T.; Joy, Raymond; Ross, Matthew F.; Wong, Selmer S.; Marlowe, Trey

2000-06-01

This study evaluates electron beam stabilization of UV6, a positive tone Deep-UV (DUV) resist from Shipley, for a 0.25 micrometer metal etch application. Results are compared between untreated resist and resist treated with different levels of electron beam stabilization. The electron beam processing was carried out in an ElectronCureTM flood electron beam exposure system from Honeywell International Inc., Electron Vision. The ElectronCureTM system utilizes a flood electron beam source which is larger in diameter than the substrate being processed, and is capable of variable energy so that the electron range is matched to the resist film thickness. Changes in the UV6 resist material as a result of the electron beam stabilization are monitored via spectroscopic ellipsometry for film thickness and index of refraction changes and FTIR for analysis of chemical changes. Thermal flow stability is evaluated by applying hot plate bakes of 150 degrees Celsius and 200 degrees Celsius, to patterned resist wafers with no treatment and with an electron beam dose level of 2000 (mu) C/cm2. A significant improvement in the thermal flow stability of the patterned UV6 resist features is achieved with the electron beam stabilization process. Etch process performance of the UV6 resist was evaluated by performing a metal pattern transfer process on wafers with untreated resist and comparing these with etch results on wafers with different levels of electron beam stabilization. The etch processing was carried out in an Applied Materials reactor with an etch chemistry including BCl3 and Cl2. All wafers were etched under the same conditions and the resist was treated after etch to prevent further erosion after etch but before SEM analysis. Post metal etch SEM cross-sections show the enhancement in etch resistance provided by the electron beam stabilization process. Enhanced process margin is achieved as a result of the improved etch resistance, and is observed in reduced resist side-wall angles after etch. Only a slight improvement is observed in the isolated to dense bias effects of the etch process. Improved CD control is also achieved by applying the electron beam process, as more consistent CDs are observed after etch.

Array automated assembly task, phase 2. Low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Rhee, S. S.; Jones, G. T.; Allison, K. T.

1978-01-01

Several modifications instituted in the wafer surface preparation process served to significantly reduce the process cost to 1.55 cents per peak watt in 1975 cents. Performance verification tests of a laser scanning system showed a limited capability to detect hidden cracks or defects, but with potential equipment modifications this cost effective system could be rendered suitable for applications. Installation of electroless nickel plating system was completed along with an optimization of the wafer plating process. The solder coating and flux removal process verification test was completed. An optimum temperature range of 500-550 C was found to produce uniform solder coating with the restriction that a modified dipping procedure is utilized. Finally, the construction of the spray-on dopant equipment was completed.

Contact electrification induced interfacial reactions and direct electrochemical nanoimprint lithography in n-type gallium arsenate wafer.

PubMed

Zhang, Jie; Zhang, Lin; Wang, Wei; Han, Lianhuan; Jia, Jing-Chun; Tian, Zhao-Wu; Tian, Zhong-Qun; Zhan, Dongping

2017-03-01

Although metal assisted chemical etching (MacEtch) has emerged as a versatile micro-nanofabrication method for semiconductors, the chemical mechanism remains ambiguous in terms of both thermodynamics and kinetics. Here we demonstrate an innovative phenomenon, i.e. , the contact electrification between platinum (Pt) and an n-type gallium arsenide (100) wafer (n-GaAs) can induce interfacial redox reactions. Because of their different work functions, when the Pt electrode comes into contact with n-GaAs, electrons will move from n-GaAs to Pt and form a contact electric field at the Pt/n-GaAs junction until their electron Fermi levels ( E F ) become equal. In the presence of an electrolyte, the potential of the Pt/electrolyte interface will shift due to the contact electricity and induce the spontaneous reduction of MnO 4 - anions on the Pt surface. Because the equilibrium of contact electrification is disturbed, electrons will transfer from n-GaAs to Pt through the tunneling effect. Thus, the accumulated positive holes at the n-GaAs/electrolyte interface make n-GaAs dissolve anodically along the Pt/n-GaAs/electrolyte 3-phase interface. Based on this principle, we developed a direct electrochemical nanoimprint lithography method applicable to crystalline semiconductors.

Mechanism of amino acid interaction with silicon nitride surface during chemical mechanical planarization

NASA Astrophysics Data System (ADS)

America, William George

Chemical-Mechanical Planarization (CMP) has become an essential technology for making modern semiconductor devices. This technique was originally applied to overcome the depth of focus limitations of lithography tools during pattern development of metal and dielectric films. As features of the semiconductor device became smaller the lithographic process shifted to shorter exposure wavelengths and the useable depth of focus became smaller. The topography differences on the wafer's surface from all of the previous processing steps became greater than the exposure tools could properly project. CMP helped solve this problem by bringing the features of the wafer surface to the same plane. As semiconductor fabrication technology progressed further, CMP was applied to other areas of the process, including shallow trench isolation and metal line Damascene processing. In its simplest application, CMP polishes on features projecting upward and higher than the average surface. These projections experience more work and are polished faster. Given sufficient time the surface becomes essentially flat, on a micro-scale, and the lithographic projection tools has the same plane onto which to focus. Thus, the pattern is properly and uniformly exposed and subsequent reactive ion etching (RIE) steps are executed. This technique was initially applied to later steps in the wafer processing scheme to render a new flat surface at each metal layer. Building on this success, CMP has been applied to a broad range of steps in the wafer processing particularly where surface topography warrants and when RIE of dielectric or metallic films is not practical. CMP has seen its greatest application in semiconductor logic and memory devices and most recently, a Damascene processing for copper lines and shallow trench isolation. This pattern dependent CMP issue is explored in this thesis as it pertains primarily to shallow trench isolation CMP coupled with a highly selective slurry chemistry.

Advanced lithographic filtration and contamination control for 14nm node and beyond semiconductor processes

NASA Astrophysics Data System (ADS)

Varanasi, Rao; Mesawich, Michael; Connor, Patrick; Johnson, Lawrence

2017-03-01

Two versions of a specific 2nm rated filter containing filtration medium and all other components produced from high density polyethylene (HDPE), one subjected to standard cleaning, the other to specialized ultra-cleaning, were evaluated in terms of their cleanliness characteristics, and also defectivity of wafers processed with photoresist filtered through each. With respect to inherent cleanliness, the ultraclean version exhibited a 70% reduction in total metal extractables and 90% reduction in organics extractables compared to the standard clean version. In terms of particulate cleanliness, the ultraclean version achieved stability of effluent particles 30nm and larger in about half the time required by the standard clean version, also exhibiting effluent levels at stability almost 90% lower. In evaluating defectivity of blanket wafers processed with photoresist filtered through either version, initial defect density while using the ultraclean version was about half that observed when the standard clean version was in service, with defectivity also falling more rapidly during subsequent usage of the ultraclean version compared to the standard clean version. Similar behavior was observed for patterned wafers, where the enhanced defect reduction was primarily of bridging defects. The filter evaluation and actual process-oriented results demonstrate the extreme value in using filtration designed possessing the optimal intrinsic characteristics, but with further improvements possible through enhanced cleaning processes

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Resonance ultrasonic diagnostics of defects in full-size silicon wafers

NASA Astrophysics Data System (ADS)

Belyaev, A.; Ostapenko, S.

2001-12-01

A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

Full wafer size investigation of N+ and P+ co-implanted layers in 4H-SiC

NASA Astrophysics Data System (ADS)

Blanqué, S.; Lyonnet, J.; Pérez, R.; Terziyska, P.; Contreras, S.; Godignon, P.; Mestres, N.; Pascual, J.; Camassel, J.

2005-03-01

We report a full wafer size investigation of the homogeneity of electrical properties in the case of co-implanted nitrogen and phosphorus ions in 4H-SiC semi-insulating wafers. To match standard industrial requirements, implantation was done at room temperature. To achieve a detailed electrical knowledge, we worked on a 35 mm wafer on which 77 different reticules have been processed. Every reticule includes one Hall cross, one Van der Pauw test structure and different TLM patterns. Hall measurements have been made on all 77 different reticules, using an Accent HL5500 Hall System® from BioRad fitted with an home-made support to collect data from room temperature down to about 150 K. At room temperature, we find that the sheet carrier concentration is only 1/4 of the total implanted dose while the average mobility is 80.6 cm2/Vs. The standard deviation is, typically, 1.5 cm2/Vs.

Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

NASA Astrophysics Data System (ADS)

de Buttet, Côme; Prevost, Emilie; Campo, Alain; Garnier, Philippe; Zoll, Stephane; Vallier, Laurent; Cunge, Gilles; Maury, Patrick; Massin, Thomas; Chhun, Sonarith

2017-03-01

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

NASA Astrophysics Data System (ADS)

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Large scale integration of graphene transistors for potential applications in the back end of the line

NASA Astrophysics Data System (ADS)

Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

2015-06-01

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Chemical Vapor Deposition Of Silicon Carbide

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Larkin, David J.; Matus, Lawrence G.; Petit, Jeremy B.

1993-01-01

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

PubMed

Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

2014-12-07

We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

Microelectromechanical Systems (MEMS) Photoacoustic (PA) Detector of Terahertz (THz) Radiation for Chemical Sensing

DTIC Science & Technology

2014-03-01

26 Feb 2014 Ivan Medvedev, PhD (Member) Date iv AFIT-ENG-14-M-58 Abstract In this research effort, a Microelectromechanical...7. Separation by implantation of oxygen (SIMOX) is a process of creating silicon- on-insulator (SOI) wafers. Oxygen ions are implanted into a silicon...wafer. The depth of the insulating layer is dependent upon the power used during ion implantation [14]. .............................. 16  Figure 8

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Stability and imaging of the ASML EUV alpha demo tool

NASA Astrophysics Data System (ADS)

Hermans, Jan V.; Baudemprez, Bart; Lorusso, Gian; Hendrickx, Eric; van Dijk, Andre; Jonckheere, Rik; Goethals, Anne-Marie

2009-03-01

Extreme Ultra-Violet (EUV) lithography is the leading candidate for semiconductor manufacturing of the 22nm technology node and beyond, due to the very short wavelength of 13.5nm. However, reducing the wavelength adds complexity to the lithographic process. The impact of the EUV specific conditions on lithographic performance needs to be understood, before bringing EUV lithography into pre-production. To provide early learning on EUV, an EUV fullfield scanner, the Alpha Demo Tool (ADT) from ASML was installed at IMEC, using a Numerical Aperture (NA) of 0.25. In this paper we report on different aspects of the ADT: the imaging and overlay performance and both short and long-term stability. For 40nm dense Lines-Spaces (LS), the ADT shows an across field overlapping process window of 270nm Depth Of Focus (DOF) at 10% Exposure Latitude (EL) and a wafer CD Uniformity (CDU) of 3nm 3σ, without any corrections for process or reticle. The wafer CDU is correlated to different factors that are known to influence the CD fingerprint from traditional lithography: slit intensity uniformity, focus plane deviation and reticle CD error. Taking these contributions into account, the CD through slit fingerprint for 40nm LS is simulated with excellent agreement to experimental data. The ADT shows good CD stability over 9 months of operation, both intrafield and across wafer. The projection optics reflectivity has not degraded over 9 months. Measured overlay performance with respect to a dry tool shows |Mean|+3σ below 20nm with more correction potential by applying field-by-field corrections (|Mean|+3σ <=10nm). For 22nm SRAM application, both contact hole and metal layer were printed in EUV with 10% CD and 15nm overlay control. Below 40nm, the ADT shows good wafer CDU for 30nm dense and isolated lines (on the same wafer) and 38nm dense Contact Holes (CH). First 28nm dense line CDU data are achieved. The results indicate that the ADT can be used effectively for EUV process development before installation of the pre-production tool, the ASML NXE Gen. 1 at IMEC.

Application of overlay modeling and control with Zernike polynomials in an HVM environment

NASA Astrophysics Data System (ADS)

Ju, JaeWuk; Kim, MinGyu; Lee, JuHan; Nabeth, Jeremy; Jeon, Sanghuck; Heo, Hoyoung; Robinson, John C.; Pierson, Bill

2016-03-01

Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field and inter-field models and the model coefficients are sent to an advanced process control (APC) system operating in an XY Cartesian basis. Dampened overlay corrections, typically via exponentially or linearly weighted moving average in time, are then retrieved from the APC system to apply on the scanner in XY Cartesian form for subsequent lot exposure. The goal of the above method is to process lots with corrections that target the least possible overlay misregistration in steady state as well as in change point situations. In this study, we model overlay errors on product using Zernike polynomials with same fitting capability as the process of reference (POR) to represent the wafer-level terms, and use the standard Cartesian polynomials to represent the field-level terms. APC calculations for wafer-level correction are performed in Zernike basis while field-level calculations use standard XY Cartesian basis. Finally, weighted wafer-level correction terms are converted to XY Cartesian space in order to be applied on the scanner, along with field-level corrections, for future wafer exposures. Since Zernike polynomials have the property of being orthogonal in the unit disk we are able to reduce the amount of collinearity between terms and improve overlay stability. Our real time Zernike modeling and feedback evaluation was performed on a 20-lot dataset in a high volume manufacturing (HVM) environment. The measured on-product results were compared to POR and showed a 7% reduction in overlay variation including a 22% terms variation. This led to an on-product raw overlay Mean + 3Sigma X&Y improvement of 5% and resulted in 0.1% yield improvement.

Maskless lithography using off-the-shelf inkjet printer

NASA Astrophysics Data System (ADS)

Seng, Leo Cheng; Chollet, Franck

2006-12-01

Photolithography is the most important process used to pattern the surface of silicon wafers in IC fabrication. It has shown high performance but its use is not cost-effective for small series or prototyping as it necessitates a costly infrastructure (mask aligner) and requires the fabrication of masks which can be expensive and timeconsuming. Recently, the high resolution achieved by ink-jet printer (> 1200 DPI) starts to make an interesting alternative to obtain a patterned protective layer instead of using photolithography. This is particularly true for MEMS which often need a resolution of only 10 to 20 μm. After studying the different architecture of inkjet printer available in the market, a commercial S$100-printer was selected and modified to allow printing on a rigid silicon wafer. We then developed three different patterning processes using the printer. In a first process the ink was directly used as a protective layer for patterning. A second process modified the photolithography by using the printed ink as a photo-mask on a spun layer of photoresist. In each case we had to modify the surface energy of the wafer by surface treatment to improve the resolution. Finally we replaced the ink with a modified photoresist solution and directly printed a protective mask onto the wafer. Design of Experiment (DOE) methods were systematically employed to study the main and interaction effects of the parameters on the lithography and on the pattern transfer. The series of experiment showed that off-the-shelf ink-jet printer could be used easily for pattern with a resolution below 50 μm, but could not yet reach the 20 μm range.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2001-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2001-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discemible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2000-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2002-07-16

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

NASA Astrophysics Data System (ADS)

Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

2013-09-01

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

Increasing reticle inspection efficiency and reducing wafer printchecks at 14nm using automated defect classification and simulation

NASA Astrophysics Data System (ADS)

Paracha, Shazad; Goodman, Eliot; Eynon, Benjamin G.; Noyes, Ben F.; Ha, Steven; Kim, Jong-Min; Lee, Dong-Seok; Lee, Dong-Heok; Cho, Sang-Soo; Ham, Young M.; Vacca, Anthony D.; Fiekowsky, Peter J.; Fiekowsky, Daniel I.

2014-10-01

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect's printability under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the results of both AIMS optical simulation and to actual wafer prints.

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

PubMed

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

A thermal microprobe fabricated with wafer-stage processing

NASA Astrophysics Data System (ADS)

Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

1998-05-01

A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

Advanced in-production hotspot prediction and monitoring with micro-topography

NASA Astrophysics Data System (ADS)

Fanton, P.; Hasan, T.; Lakcher, A.; Le-Gratiet, B.; Prentice, C.; Simiz, J.-G.; La Greca, R.; Depre, L.; Hunsche, S.

2017-03-01

At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%

40 CFR Table I-16 to Subpart I of... - Default Emission Destruction or Removal Efficiency (DRE) Factors for Electronics Manufacturing

Code of Federal Regulations, 2014 CFR

2014-07-01

... Manufacturing: Plasma Etch/Wafer Clean Process Type: CF4 75 CH3F 97 CHF3 97 CH2F2 97 C2F6 97 C3F8 97 C4F6 97 C4F8 97 C5F8 97 SF6 97 NF3 96 All other carbon-based plasma etch/wafer clean fluorinated GHG 60 Chamber...

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

NASA Astrophysics Data System (ADS)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

Microfabrication Method using a Combination of Local Ion Implantation and Magnetorheological Finishing

NASA Astrophysics Data System (ADS)

Han, Jin; Kim, Jong-Wook; Lee, Hiwon; Min, Byung-Kwon; Lee, Sang Jo

2009-02-01

A new microfabrication method that combines localized ion implantation and magnetorheological finishing is proposed. The proposed technique involves two steps. First, selected regions of a silicon wafer are irradiated with gallium ions by using a focused ion beam system. The mechanical properties of the irradiated regions are altered as a result of the ion implantation. Second, the wafer is processed by using a magnetorheological finishing method. During the finishing process, the regions not implanted with ion are preferentially removed. The material removal rate difference is utilized for microfabrication. The mechanisms of the proposed method are discussed, and applications are presented.

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

Transforming information from silicon testing and design characterization into numerical data sets for yield learning

NASA Astrophysics Data System (ADS)

Yang, Thomas; Shen, Yang; Zhang, Yifan; Sweis, Jason; Lai, Ya-Chieh

2017-03-01

Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from test result diagnostics. Product engineers will analyze the diagnostic results and perform a number of physical failure analyses to detect systematic defects which cause yield loss for these sets of wafers in order to feedback the information to process engineers for process improvements. Most of time, the systematic defects that are detected are major issues or just one of the causes for the overall yield loss. This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.

Context-based automated defect classification system using multiple morphological masks

DOEpatents

Gleason, Shaun S.; Hunt, Martin A.; Sari-Sarraf, Hamed

2002-01-01

Automatic detection of defects during the fabrication of semiconductor wafers is largely automated, but the classification of those defects is still performed manually by technicians. This invention includes novel digital image analysis techniques that generate unique feature vector descriptions of semiconductor defects as well as classifiers that use these descriptions to automatically categorize the defects into one of a set of pre-defined classes. Feature extraction techniques based on multiple-focus images, multiple-defect mask images, and segmented semiconductor wafer images are used to create unique feature-based descriptions of the semiconductor defects. These feature-based defect descriptions are subsequently classified by a defect classifier into categories that depend on defect characteristics and defect contextual information, that is, the semiconductor process layer(s) with which the defect comes in contact. At the heart of the system is a knowledge database that stores and distributes historical semiconductor wafer and defect data to guide the feature extraction and classification processes. In summary, this invention takes as its input a set of images containing semiconductor defect information, and generates as its output a classification for the defect that describes not only the defect itself, but also the location of that defect with respect to the semiconductor process layers.

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Hybrid overlay metrology for high order correction by using CDSEM

NASA Astrophysics Data System (ADS)

Leray, Philippe; Halder, Sandip; Lorusso, Gian; Baudemprez, Bart; Inoue, Osamu; Okagawa, Yutaka

2016-03-01

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

Real-time detection of laser-GaAs interaction process

NASA Astrophysics Data System (ADS)

Jia, Zhichao; Li, Zewen; Lv, Xueming; Ni, Xiaowu

2017-05-01

A real-time method based on laser scattering technology was used to detect the interaction process of GaAs with a 1080 nm laser. The detector collected the scattered laser beam from the GaAs wafer. The main scattering sources were back surface at first, later turn into front surface and vapor, so scattering signal contained much information of the interaction process. The surface morphologies of GaAs with different irradiation times were observed using an optical microscope to confirm occurrence of various phenomena. The proposed method is shown to be effective for the real-time detection of GaAs. By choosing a proper wavelength, the scattering technology can be promoted in detection of thicker GaAs wafer or other materials.

Investigation of Backside Textures for Genesis Solar Wind Silicon Collectors

NASA Technical Reports Server (NTRS)

Gonzalez, C. P.; Burkett, P. J.; Rodriguez, M. C.; Allton, J. H.

2014-01-01

Genesis solar wind collectors were comprised of a suite of 15 types of ultrapure materials. The single crystal, pure silicon collectors were fabricated by two methods: float zone (FZ) and Czochralski (CZ). Because of slight differences in bulk purity and surface cleanliness among the fabrication processes and the specific vendor, it is desirable to know which variety of silicon and identity of vendor, so that appropriate reference materials can be used. The Czochralski method results in a bulk composition with slightly higher oxygen, for example. The CZ silicon array wafers that were Genesis-flown were purchased from MEMC Electronics. Most of the Genesis-flown FZ silicon was purchased from Unisil and cleaned by MEMC, although a few FZ wafers were acquired from International Wafer Service (IWS).

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

ROI on yield data analysis systems through a business process management strategy

NASA Astrophysics Data System (ADS)

Rehani, Manu; Strader, Nathan; Hanson, Jeff

2005-05-01

The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

In-cell overlay metrology by using optical metrology tool

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Hong, Minhyung; Kim, Seungyoung; Lee, Jieun; Lee, DongYoung; Oh, Eungryong; Choi, Ahlin; Park, Hyowon; Liang, Waley; Choi, DongSub; Kim, Nakyoon; Lee, Jeongpyo; Pandev, Stilian; Jeon, Sanghuck; Robinson, John C.

2018-03-01

Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after litho control loop typically involves high frequency sampling: every lot or nearly every lot. An after etch overlay metrology step is often included, at a lower sampling frequency, in order to characterize and compensate for bias. The after etch metrology step often involves CD-SEM metrology, in this case in-cell and ondevice. This work explores an alternative approach using spectroscopic ellipsometry (SE) metrology and a machine learning analysis technique. Advanced 1x nm DRAM wafers were prepared, including both nominal (POR) wafers with mean overlay offsets, as well as DOE wafers with intentional across wafer overlay modulation. After litho metrology was measured using optical imaging metrology, as well as after etch metrology using both SE and CD-SEM for comparison. We investigate 2 types of machine learning techniques with SE data: model-less and model-based, showing excellent performance for after etch in-cell on-device overlay metrology.

Surface characteristics and damage distributions of diamond wire sawn wafers for silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Devayajanam, Srinivas; Basnyat, Prakash

2016-01-01

This paper describes surface characteristics, in terms of its morphology, roughness and near-surface damage of Si wafers cut by diamond wire sawing (DWS) of Si ingots under different cutting conditions. Diamond wire sawn Si wafers exhibit nearly-periodic surface features of different spatial wavelengths, which correspond to kinematics of various movements during wafering, such as ingot feed, wire reciprocation, and wire snap. The surface damage occurs in the form of frozen-in dislocations, phase changes, and microcracks. The in-depth damage was determined by conventional methods such as TEM, SEM and angle-polishing/defect-etching. However, because these methods only provide local information, we have alsomore » applied a new technique that determines average damage depth over a large area. This technique uses sequential measurement of the minority carrier lifetime after etching thin layers from the surfaces. The lateral spatial damage variations, which seem to be mainly related to wire reciprocation process, were observed by photoluminescence and minority carrier lifetime mapping. Our results show a strong correlation of damage depth on the diamond grit size and wire usage.« less

A micro-scale plasma spectrometer for space and plasma edge applications (invited)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scime, E. E., E-mail: escime@wvu.edu; Keesee, A. M.; Elliott, D.

2016-11-15

A plasma spectrometer design based on advances in lithography and microchip stacking technologies is described. A series of curved plate energy analyzers, with an integrated collimator, is etched into a silicon wafer. Tests of spectrometer elements, the energy analyzer and collimator, were performed with a 5 keV electron beam. The measured collimator transmission and energy selectivity were in good agreement with design targets. A single wafer element could be used as a plasma processing or fusion first wall diagnostic.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

CDU improvement technology of etching pattern using photo lithography

NASA Astrophysics Data System (ADS)

Tadokoro, Masahide; Shinozuka, Shinichi; Jyousaka, Megumi; Ogata, Kunie; Morimoto, Tamotsu; Konishi, Yoshitaka

2008-03-01

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB) temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU, etcher-specific CD variation needs to be controlled. In this evaluation, 1. We verified whether etcher-specific CD variation can be controlled and consequently Etching Pattern CDU can be further improved by controlling resist patterns through PEB control. 2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in wiring resistance variation. The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared. 2. Resist patterns were created on them. 3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning off the resist and BARC, CD of etched D-Poly was measured. 4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer temperature distribution in the PEB process was modified. 5. Resist patterns were created again, followed by the second etching and cleaning, which was followed by CD measurement. We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as OCD is minimally affected by Line Edge Roughness (LER). As a result, 1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in etcher-specific CD variation and the improvement in Etching Pattern CDU. 2. The improvement in Etching Pattern CDU has an effect on the reduction in wiring resistance variation. The method for Etching Pattern CDU improvement through PEB control reduces within-wafer variation of MOS transistor's gate length. Therefore, with this method, we can expect to observe uniform within-wafer MOS transistor characteristics.

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

Chemical etching for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1981-01-01

Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

0.15 {mu}m InGaAs/AlGaAs/GaAs HEMT production process for high performance and high yield v-band power MMICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lai, R.; Biedenbender, M.; Lee, J.

1995-12-31

The authors present a unique high yield, high performance 0.15 {mu}m HEMT production process which supports fabrication of MMW power MMICs up to 70 GHz. This process has been transferred successfully from an R&D process to TRW`s GaAs production line. This paper reports the on-wafer test results of more than 1300 V-band MMIC PA circuits measured over 24 wafers. The best 2-stage V-band power MMICs have demonstrated state-of-the-art performance with 9 dB power gain, 20% PAE and 330 mW output power. An excellent RF yield of 60% was achieved with an 8 dB power gain and 250 mW output powermore » specification.« less

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Big data driven cycle time parallel prediction for production planning in wafer manufacturing

NASA Astrophysics Data System (ADS)

Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

2018-07-01

Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

Cryogenic plasma-processed silicon microspikes as a high-performance anode material for lithium ion-batteries

NASA Astrophysics Data System (ADS)

Sakai, Joe; Luais, Erwann; Wolfman, Jérôme; Tillocher, Thomas; Dussart, Rémi; Tran-Van, Francois; Ghamouss, Fouad

2017-10-01

Micro- or nano-structuring is essential in order to use Si as an anode material for lithium ion batteries. In the present study, we attempted to use Si wafers with a spiky microstructure (SMS), the so-called black-Si, prepared by a cryogenic reactive ion etching process with an SF6/O2 gas mixture, for Li half-cells. The SMS with various sizes of spikes from 2.0 μm (height) × 0.2 μm (width) to 21 μm × 1.0 μm was etched by varying the SF6/O2 gas flow ratio. An anode of SMS of 11 μm-height in average showed stable charge/discharge capacity and Coulombic efficiency higher than 99% for more than 300 cycles, causing no destruction to any part of the Si wafer. The spiky structure turned columnar after cycles, suggesting graded lithiation levels along the length. The present results suggest a strategy to utilize a wafer-based Si material for an anode of a lithium ion battery durable against repetitive lithiation/delithiation cycles.

Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

NASA Astrophysics Data System (ADS)

Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

1998-06-01

Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

Nonepitaxial Thin-Film InP for Scalable and Efficient Photocathodes.

PubMed

Hettick, Mark; Zheng, Maxwell; Lin, Yongjing; Sutter-Fella, Carolin M; Ager, Joel W; Javey, Ali

2015-06-18

To date, some of the highest performance photocathodes of a photoelectrochemical (PEC) cell have been shown with single-crystalline p-type InP wafers, exhibiting half-cell solar-to-hydrogen conversion efficiencies of over 14%. However, the high cost of single-crystalline InP wafers may present a challenge for future large-scale industrial deployment. Analogous to solar cells, a thin-film approach could address the cost challenges by utilizing the benefits of the InP material while decreasing the use of expensive materials and processes. Here, we demonstrate this approach, using the newly developed thin-film vapor-liquid-solid (TF-VLS) nonepitaxial growth method combined with an atomic-layer deposition protection process to create thin-film InP photocathodes with large grain size and high performance, in the first reported solar device configuration generated by materials grown with this technique. Current-voltage measurements show a photocurrent (29.4 mA/cm(2)) and onset potential (630 mV) approaching single-crystalline wafers and an overall power conversion efficiency of 11.6%, making TF-VLS InP a promising photocathode for scalable and efficient solar hydrogen generation.

Cancer mortality among US workers employed in semiconductor wafer fabrication.

PubMed

Boice, John D; Marano, Donald E; Munro, Heather M; Chadda, Bandana K; Signorello, Lisa B; Tarone, Robert E; Blot, William J; McLaughlin, Joseph K

2010-11-01

To evaluate potential cancer risks in the US semiconductor wafer fabrication industry. A cohort of 100,081 semiconductor workers employed between 1968 and 2002 was studied. Standardized mortality ratios and relative risks (RRs) were estimated. Standardized mortality ratios were similar and significantly low among fabrication and nonfabrication workers for all causes (0.54 and 0.54) and all cancers (0.74 and 0.72). Internal comparisons also showed similar overall cancer risks among fabrication workers (RR = 0.98), including process equipment operators and process equipment service technicians (OP/EST) employed in cleanrooms (RR = 0.97), compared with nonfabrication workers. Nonsignificantly elevated RRs were observed for a few cancer sites among OP/EST workers, but the numbers of deaths were small and there were no trends of increasing risk with duration of employment. Work in the US semiconductor industry, including semiconductor wafer fabrication in cleanrooms, was not associated with increased cancer mortality overall or mortality from any specific form of cancer. However, due to the young average age of this cohort and its associated relatively low numbers of deaths, regular mortality updates of this semiconductor worker cohort are warranted.

EFG Ribbon Technology

NASA Astrophysics Data System (ADS)

Schwirtlich, I. A.

Since the beginning of solar cell development based on crystalline silicon, there have been efforts to produce wafers directly from the melt instead of through crystallization of ingots. Ingots require slicing into the blocs and wafers which form the basis of solar cells. In the last 30 years, several dozen processes have been published that describe a variety of concepts. Only few of these processes could be developed to an acceptable degree of technical maturity. Among those successful technologies are the Dendritic Web process, the Edge Supported Pulling (ESP) process and the Edge-Defined-Film-Fed-Growth (EFG) process. The EFG Process was originally developed by Mobil Solar and, since the mid-1990s, belongs to SCHOTT Solar GmbH and its predecessors, respectively. The Ribbon Growth on Substrate (RGS) process was originally developed by Bayer AG and is now in a pilot project at the ECN, Petten. Considering the past 20 to 30 years, the EFG process has reached the most advanced state in terms of industrialization.

Lyophilised wafers as vehicles for the topical release of chlorhexidine digluconate--release kinetics and efficacy against Pseudomonas aeruginosa.

PubMed

Labovitiadi, Olga; Lamb, Andrew J; Matthews, Kerr H

2012-12-15

There is a requirement to deliver accurate amounts of broad spectrum antimicrobial compounds locally to exuding wounds. Varying amounts of exudate complicates this process by limiting the residence and therefore efficacy of active substances. Minimum bactericidal concentrations (MBC) of antimicrobials are necessary to suppress infection and lessen the chances of resistant strains of potentially pathogenic bacteria from prevailing. Polysaccharide wafers can adhere to exudating wound beds, absorbing fluids and forming highly viscous gels that remain in situ for prolonged periods of time to release sustained amounts of antimicrobial. In this study, five different formulations were produced containing the antimicrobial, chlorhexidine digluconate (CHD). Absorption of simulated wound fluid, resultant rheological properties of gels and efficacy against plated cultures of Pseudomonas aeruginosa were measured and compared. CHD reduced the 'water uptake' of wafers by 11-50% (w/w) and decreased the rheological consistency of non-SA containing gels by 10-65%. Release studies indicated that karaya wafers gave the highest sustained release of CHD, >60 μg/mL in 24 h, well in excess of the MBC for P. aeruginosa. Release kinetics indicated an anomalous diffusion mechanism according to Korsmeyer-Peppas, with diffusion exponents varying from 0.31 to 0.41 for most wafers except xanthan (0.65). Copyright © 2012 Elsevier B.V. All rights reserved.

SiC Seeded Crystal Growth

NASA Astrophysics Data System (ADS)

Glass, R. C.; Henshall, D.; Tsvetkov, V. F.; Carter, C. H., Jr.

1997-07-01

The availability of relatively large (30 mm) SiC wafers has been a primary reason for the renewed high level of interest in SiC semiconductor technology. Projections that 75 mm SiC wafers will be available in 2 to 3 years have further peaked this interest. Now both 4H and 6H polytypes are available, however, the micropipe defects that occur to a varying extent in all wafers produced to date are seen by many as preventing the commercialization of many types of SiC devices, especially high current power devices. Most views on micropipe formation are based around Frank's theory of a micropipe being the hollow core of a screw dislocation with a huge Burgers vector (several times the unit cell) and with the diameter of the core having a direct relationship with the magnitude of the Burgers vector. Our results show that there are several mechanisms or combinations of these mechanisms which cause micropipes in SiC boules grown by the seeded sublimation method. Additional considerations such as polytype variations, dislocations and both impurity and diameter control add to the complexity of producing high quality wafers. Recent results at Cree Research, Inc., including wafers with micropipe densities of less than 1 cm - 2 (with 1 cm2 areas void of micropipes), indicate that micropipes will be reduced to a level that makes high current devices viable and that they may be totally eliminated in the next few years. Additionally, efforts towards larger diameter high quality substrates have led to production of 50 mm diameter 4H and 6H wafers for fabrication of LEDs and the demonstration of 75 mm wafers. Low resistivity and semi-insulating electrical properties have also been attained through improved process and impurity control. Although challenges remain, the industry continues to make significant progress towards large volume SiC-based semiconductor fabrication.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Making High-Pass Filters For Submillimeter Waves

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Lichtenberger, John A.

1991-01-01

Micromachining-and-electroforming process makes rigid metal meshes with cells ranging in size from 0.002 in. to 0.05 in. square. Series of steps involving cutting, grinding, vapor deposition, and electroforming creates self-supporting, electrically thick mesh. Width of holes typically 1.2 times cutoff wavelength of dominant waveguide mode in hole. To obtain sharp frequency-cutoff characteristic, thickness of mesh made greater than one-half of guide wavelength of mode in hole. Meshes used as high-pass filters (dichroic plates) for submillimeter electromagnetic waves. Process not limited to square silicon wafers. Round wafers also used, with slightly more complication in grinding periphery. Grid in any pattern produced in electroforming mandrel. Any platable metal or alloy used for mesh.

Development of SiC Large Tapered Crystal Growth

NASA Technical Reports Server (NTRS)

Neudeck, Phil

2011-01-01

Research Focus Area: Power Electronics, Temperature Tolerant Devices. Demonstrate initial feasibility of totally new "Large Tapered Crystal" (LTC) process for growing vastly improved large-diameter wide-band gap wafers. Addresses Targets: The goal of this research is to experimentally investigate and demonstrate feasibility of the key unproven LTC growth processes in SiC. Laser-assisted growth of long SiC fiber seeds. Radial epitaxial growth enlargement of seeds into large SiC boules. Uniqueness and Impacts open a new technology path to large-diameter SiC and GaN wafers with 1000-fold defect density improvement at 2-4 fold lower cost. Leapfrog improvement in wide band gap power device capability and cost.

A comparison of the mechanical and sensory properties of baked and extruded confectionery products

NASA Astrophysics Data System (ADS)

Butt, Saba; Charalambides, Maria; Mohammed, Idris K.; Powell, Hugh

2017-10-01

Traditional baking is the most common way of producing confectionery wafers, however over the past few decades, the extrusion process has become an increasingly important food manufacturing method and is commonly used in the manufacturing of breakfast cereals and filled snack products. This study aims to characterise products made via each of these manufacturing processes in order to understand the important parameters involved in the resulting texture of confectionery products such as wafers. Both of the named processes result in brittle, cellular foams comprising of cell walls and cell pores which may contain some of the confectionery filling. The mechanical response of the cell wall material and the geometry of the products influence the consumer perception and preference. X-Ray micro tomography (XRT) was used to generate geometry of the microstructure which was then fed to Finite Element (FE) for numerical analysis on both products. The FE models were used to determine properties such as solid modulus of the cell walls, Young's modulus of the entire foam and to investigate and compare the microstructural damage of baked wafers and extruded products. A sensory analysis study was performed on both products by a qualified sensory panel. The results of this study were then used to draw links between the mechanical behaviour and sensory perception of a consumer. The extruded product was found to be made up of a stiffer solid material and had a higher compressive modulus and fracture stress when compared to the baked wafer. The sensory panel observed textural differences between the baked and extruded products which were also found in the differences of the mechanical properties of the two products.

Increasing minority carrier lifetime in as-grown multicrystalline silicon by low temperature internal gettering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Amin, M., E-mail: m.al-amin@warwick.ac.uk; Murphy, J. D., E-mail: john.d.murphy@warwick.ac.uk

2016-06-21

We report a systematic study into the effects of long low temperature (≤500 °C) annealing on the lifetime and interstitial iron distributions in as-grown multicrystalline silicon (mc-Si) from different ingot height positions. Samples are characterised in terms of dislocation density, and lifetime and interstitial iron concentration measurements are made at every stage using a temporary room temperature iodine-ethanol surface passivation scheme. Our measurement procedure allows these properties to be monitored during processing in a pseudo in situ way. Sufficient annealing at 300 °C and 400 °C increases lifetime in all cases studied, and annealing at 500 °C was only found to improve relatively poormore » wafers from the top and bottom of the block. We demonstrate that lifetime in poor as-grown wafers can be improved substantially by a low cost process in the absence of any bulk passivation which might result from a dielectric surface film. Substantial improvements are found in bottom wafers, for which annealing at 400 °C for 35 h increases lifetime from 5.5 μs to 38.7 μs. The lifetime of top wafers is improved from 12.1 μs to 23.8 μs under the same conditions. A correlation between interstitial iron concentration reduction and lifetime improvement is found in these cases. Surprisingly, although the interstitial iron concentration exceeds the expected solubility values, low temperature annealing seems to result in an initial increase in interstitial iron concentration, and any subsequent decay is a complex process driven not only by diffusion of interstitial iron.« less

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

NASA Astrophysics Data System (ADS)

Qiusheng, Y.; Senkai, C.; Jisheng, P.

2015-03-01

Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

NASA Astrophysics Data System (ADS)

Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

2007-08-01

This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Performance improvements of binary diffractive structures via optimization of the photolithography and dry etch processes

NASA Astrophysics Data System (ADS)

Welch, Kevin; Leonard, Jerry; Jones, Richard D.

2010-08-01

Increasingly stringent requirements on the performance of diffractive optical elements (DOEs) used in wafer scanner illumination systems are driving continuous improvements in their associated manufacturing processes. Specifically, these processes are designed to improve the output pattern uniformity of off-axis illumination systems to minimize degradation in the ultimate imaging performance of a lithographic tool. In this paper, we discuss performance improvements in both photolithographic patterning and RIE etching of fused silica diffractive optical structures. In summary, optimized photolithographic processes were developed to increase critical dimension uniformity and featuresize linearity across the substrate. The photoresist film thickness was also optimized for integration with an improved etch process. This etch process was itself optimized for pattern transfer fidelity, sidewall profile (wall angle, trench bottom flatness), and across-wafer etch depth uniformity. Improvements observed with these processes on idealized test structures (for ease of analysis) led to their implementation in product flows, with comparable increases in performance and yield on customer designs.

Aqueous-based thick photoresist removal for bumping applications

NASA Astrophysics Data System (ADS)

Moore, John C.; Brewer, Alex J.; Law, Alman; Pettit, Jared M.

2015-03-01

Cleaning processes account for over 25% of processing in microelectronic manufacturing [1], suggesting electronics to be one of the most chemical intensive markets in commerce. Industry roadmaps exist to reduce chemical exposure, usage, and waste [2]. Companies are encouraged to create a safer working environment, or green factory, and ultimately become certified similar to LEED in the building industry [3]. A significant step in this direction is the integration of aqueous-based photoresist (PR) strippers which eliminate regulatory risks and cut costs by over 50%. One of the largest organic solvent usages is based upon thick PR removal during bumping processes [4-6]. Using market projections and the benefits of recycling, it is estimated that over 1,000 metric tons (mt) of residuals originating from bumping processes are incinerated or sent to a landfill. Aqueous-based stripping would eliminate this disposal while also reducing the daily risks to workers and added permitting costs. Positive-tone PR dissolves in aqueous strippers while negative-tone systems are lifted-off from the substrate, bumps, pillars, and redistribution layers (RDL). While the wafers are further processed and rinsed, the lifted-off PR is pumped from the tank, collected onto a filter, and periodically back-flushed to the trash. The PR solids become a non-hazardous plastic waste while the liquids are mixed with the developer stream, neutralized, filtered, and in most cases, disposed to the sewer. Regardless of PR thickness, removal processes may be tuned to perform in <15min, performing at rates nearly 10X faster than solvents with higher bath lives. A balanced formula is safe for metals, dielectrics, and may be customized to any fab.

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

NASA Technical Reports Server (NTRS)

Powell, J. Anthony

2001-01-01

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Integration of an Axcelis Optima HD Single Wafer High Current Implanter for p- and n-S/D Implants in an Existing Batch Implanter Production Line

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmeide, Matthias; Kontratenko, Serguei; Krimbacher, Bernhard

2008-11-03

This paper is focused on the integration and qualification of an Axcelis Optima HD single wafer high current spot beam implanter in an existing 200 mm production line with different types of Axcelis batch implanters for high current applications. Both the design of the beamline and the beam shape are comparable between single wafer and batch high current spot beam implanters. In contrast to the single wafer high current ribbon beam implanter, energy contamination is not a concern for the considered spot beam tool because the drift mode can be used down to energies in the 2 keV region. Themore » most important difference between single wafer and batch high current implanters is the significantly higher dose rate and, therefore, the higher damage rate for the single wafer tool due to the different scanning architecture. The results of the integration of high dose implantations, mainly for p- and n-S/D formation, for DRAM 110 nm without pre-amorphization implantation (PAI), CMOS Logic from around 250 nm down to 90 nm without and with PAI, are presented and discussed. Dopant concentration profile analysis using SIMS was performed for different technologies and implantation conditions. The impurity activation was measured using sheet resistance and in some cases spreading resistance technique was applied. The amorphous layer thickness was measured using TEM. Finally, device data are presented in combination with dose, energy and beam current variations. The results have shown that the integration of implantation processes into crystalline structure without PAI is more complex and time consuming than implantations into amorphous layer where the damage difference due to the different dose rates is negligible.« less

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Design Considerations in Capacitively Coupled Plasmas

NASA Astrophysics Data System (ADS)

Song, Sang-Heon; Ventzek, Peter; Ranjan, Alok

2015-11-01

Microelectronics industry has driven transistor feature size scaling from 10-6 m to 10-9 m during the past 50 years, which is often referred to as Moore's law. It cannot be overstated that today's information technology would not have been so successful without plasma material processing. One of the major plasma sources for the microelectronics fabrication is capacitively coupled plasmas (CCPs). The CCP reactor has been intensively studied and developed for the deposition and etching of different films on the silicon wafer. As the feature size gets to around 10 nm, the requirement for the process uniformity is less than 1-2 nm across the wafer (300 mm). In order to achieve the desired uniformity, the hardware design should be as precise as possible before the fine tuning of process condition is applied to make it even better. In doing this procedure, the computer simulation can save a significant amount of resources such as time and money which are critical in the semiconductor business. In this presentation, we compare plasma properties using a 2-dimensional plasma hydrodynamics model for different kinds of design factors that can affect the plasma uniformity. The parameters studied in this presentation include chamber accessing port, pumping port, focus ring around wafer substrate, and the geometry of electrodes of CCP.

Scheduling revisited workstations in integrated-circuit fabrication

NASA Technical Reports Server (NTRS)

Kline, Paul J.

1992-01-01

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

NASA Technical Reports Server (NTRS)

Allen, Christine; Benford, Dominic; Miller, Timothy; Staguhn, Johannes; Wollack, Edward; Moseley, Harvey

2007-01-01

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Propagation of resist heating mask error to wafer level

NASA Astrophysics Data System (ADS)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the mask error budget - the resist heating CD error. In simulation of exposure using a stepper, variable MEEF was considered.

Single closed contact for 0.18-micron photolithography process

NASA Astrophysics Data System (ADS)

Cheung, Cristina; Phan, Khoi A.; Chiu, Robert J.

2000-06-01

With the rapid advances of deep submicron semiconductor technology, identifying defects is converted into a challenge for different modules in the fabrication of chips. Yield engineers often do bitmap on a memory circuit array (SRAM) to identify the failure bits. This is followed by a wafer stripback to look for visual defects at each deprocessed layer for feedback to the Fab. However, to identify the root cause of a problem, Fab engineers must be able to detect similar defects either on the product wafers in process or some short loop test wafers. In the photolithography process, we recognize that the detection of defects is becoming as important as satisfying the critical dimension (CD) of the device. For a multi-level metallization chemically mechanical polish backend process, it is very difficult to detect missing contacts or via at the masking steps due to metal grain roughness, film color variation and/or previous layer defects. Often, photolithography engineer must depend on Photo Cell Monitor (PCM) and short loop experiments for controlling baseline defects and improvement. In this paper, we discuss the findings on the Poly mask PCM and the Contact mask PCM. We present the comparison between the Poly mask and the Contact mask of the I-line Phase Shifted Via mask and DUV mask process for a 0.18 micron process technology. The correlation and the different type of defects between the Contact PCM and the Poly Mask are discussed. The Contact PCM was found to be more sensitive and correlated to contact failure at sort yield better. We also dedicate to study the root cause of a single closed contact hole in the Contact mask short loop experiment for a 0.18 micron process technology. A single closed contact defect was often caused by the developer process, such as bubbles in the line, resist residue left behind, and the rinse mechanism. We also found surfactant solution helps to improve the surface tension of the wafer for the developer process and this prevents/eliminates a single closed contact hole defects. The applications and effects of using different substrates like SiON, different thicknesses of Oxides, and Poly in the Contact Photo Mask is shown. Finally, some defect troubleshooting techniques and the root cause analysis are also discussed.

A Knowledge Database on Thermal Control in Manufacturing Processes

NASA Astrophysics Data System (ADS)

Hirasawa, Shigeki; Satoh, Isao

A prototype version of a knowledge database on thermal control in manufacturing processes, specifically, molding, semiconductor manufacturing, and micro-scale manufacturing has been developed. The knowledge database has search functions for technical data, evaluated benchmark data, academic papers, and patents. The database also displays trends and future roadmaps for research topics. It has quick-calculation functions for basic design. This paper summarizes present research topics and future research on thermal control in manufacturing engineering to collate the information to the knowledge database. In the molding process, the initial mold and melt temperatures are very important parameters. In addition, thermal control is related to many semiconductor processes, and the main parameter is temperature variation in wafers. Accurate in-situ temperature measurment of wafers is important. And many technologies are being developed to manufacture micro-structures. Accordingly, the knowledge database will help further advance these technologies.

Superconductivity devices: Commercial use of space

NASA Technical Reports Server (NTRS)

Haertling, Gene; Furman, Eugene; Hsi, Chi-Shiung; Li, Guang

1993-01-01

The processing and screen printing of the superconducting BSCCO and 123 YBCO materials on substrates is described. The resulting superconducting properties and the use of these materials as possible electrode materials for ferroelectrics at 77 K are evaluated. Also, work performed in the development of solid-state electromechanical actuators is reported. Specific details include the fabrication and processing of high strain PBZT and PLZT electrostrictive materials, the development of PSZT and PMN-based ceramics, and the testing and evaluation of these electrostrictive materials. Finally, the results of studies on a new processing technology for preparing piezoelectric and electrostrictive ceramic materials are summarized. The process involves a high temperature chemical reduction which leads to an internal pre-stressing of the oxide wafer. These reduced and internally biased oxide wafers (RAINBOW) can produce bending-mode actuator devices which possess a factor of ten more displacement and load bearing capacity than present-day benders.

ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

NASA Astrophysics Data System (ADS)

Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

2016-05-01

At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre's simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMSTM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Recombination activity of grain boundaries in high-performance multicrystalline Si during solar cell processing

NASA Astrophysics Data System (ADS)

Adamczyk, Krzysztof; Søndenâ, Rune; Stokkan, Gaute; Looney, Erin; Jensen, Mallory; Lai, Barry; Rinio, Markus; Di Sabatino, Marisa

2018-02-01

In this work, we applied internal quantum efficiency mapping to study the recombination activity of grain boundaries in High Performance Multicrystalline Silicon under different processing conditions. Wafers were divided into groups and underwent different thermal processing, consisting of phosphorus diffusion gettering and surface passivation with hydrogen rich layers. After these thermal treatments, wafers were processed into heterojunction with intrinsic thin layer solar cells. Light Beam Induced Current and Electron Backscatter Diffraction were applied to analyse the influence of thermal treatment during standard solar cell processing on different types of grain boundaries. The results show that after cell processing, most random-angle grain boundaries in the material are well passivated, but small-angle grain boundaries are not well passivated. Special cases of coincidence site lattice grain boundaries with high recombination activity are also found. Based on micro-X-ray fluorescence measurements, a change in the contamination level is suggested as the reason behind their increased activity.

High-density plasma deposition manufacturing productivity improvement

NASA Astrophysics Data System (ADS)

Olmer, Leonard J.; Hudson, Chris P.

1999-09-01

High Density Plasma (HDP) deposition provides a means to deposit high quality dielectrics meeting submicron gap fill requirements. But, compared to traditional PECVD processing, HDP is relatively expensive due to the higher capital cost of the equipment. In order to keep processing costs low, it became necessary to maximize the wafer throughput of HDP processing without degrading the film properties. The approach taken was to optimize the post deposition microwave in-situ clean efficiency. A regression model, based on actual data, indicated that number of wafers processed before a chamber clean was the dominant factor. Furthermore, a design change in the ceramic hardware, surrounding the electrostatic chuck, provided thermal isolation resulting in an enhanced clean rate of the chamber process kit. An infra-red detector located in the chamber exhaust line provided a means to endpoint the clean and in-film particle data confirmed the infra-red results. The combination of increased chamber clean frequency, optimized clean time and improved process.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Improvements To Micro Contact Performance And Reliability

DTIC Science & Technology

2016-12-22

BAKE : □ 1 min 110°C hot plate bake OPTIONAL - For Grayscale Lithography: 1818 COAT: □ Flood wafer with 1818 □ 4 sec spread at 500 rpm...30 sec spin at 4,000 rpm, ramp=200 □ 75 sec 110°C hot plate bake GRAYSCALE PATTERNING: □ Follow grayscale patterning process for patterns...8217 □ 2 min 200°C hot plate bake 1818 COAT: □ Flood wafer with 1818 □ 4 sec spread at 500 rpm □ 30 sec spin at 4,000 rpm, ramp=200 □ 75 sec 110

A Micromachined Geometric Moire Interferometric Floating-Element Shear Stress Sensor

NASA Technical Reports Server (NTRS)

Horowitz, S.; Chen, T.; Chandrasekaran, V.; Tedjojuwono, K.; Nishida, T.; Cattafesta, L.; Sheplak, M.

2004-01-01

This paper presents the development of a floating-element shear stress sensor that permits the direct measurement of skin friction based on geometric Moir interferometry. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Experimental characterization indicates a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

THz quantum cascade lasers with wafer bonded active regions.

PubMed

Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

2012-10-08

We demonstrate terahertz quantum-cascade lasers with a 30 μm thick double-metal waveguide, which are fabricated by stacking two 15 μm thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current.

High throughput laser processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harley, Gabriel; Pass, Thomas; Cousins, Peter John

A solar cell is formed using a solar cell ablation system. The ablation system includes a single laser source and several laser scanners. The laser scanners include a master laser scanner, with the rest of the laser scanners being slaved to the master laser scanner. A laser beam from the laser source is split into several laser beams, with the laser beams being scanned onto corresponding wafers using the laser scanners in accordance with one or more patterns. The laser beams may be scanned on the wafers using the same or different power levels of the laser source.

Through-wafer optical probe characterization for microelectromechanical systems positional state monitoring and feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

2000-12-01

Implementation of closed-loop microelectromechanical system (MEMS) control enables mechanical microsystems to adapt to the demands of the environment that they are actuating, opening a broad range of new opportunities for future MEMS applications. Integrated optical microsystems have the potential to enable continuous in situ optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation that is necessary for realization of feedback control. We present the results of initial research evaluating through-wafer optical microprobes for surface micromachined MEMS integrated optical position monitoring. Results from the through-wafer free-space optical probe of a lateral comb resonator fabricated using the multiuser MEMS process service (MUMPS) indicate significant positional information content with an achievable return probe signal dynamic range of up to 80% arising from film transmission contrast. Static and dynamic deflection analysis and experimental results indicate a through-wafer probe positional signal sensitivity of 40 mV/micrometers for the present setup or 10% signal change per micrometer. A simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure given the availability of positional state information.

Planning for the semiconductor manufacturer of the future

NASA Technical Reports Server (NTRS)

Fargher, Hugh E.; Smith, Richard A.

1992-01-01

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Ward, Pamela Denise Peardon; Stevenson, Joel O'Don

2002-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). Another aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system. A final aspect of the present invention relates to a network a plurality of plasma monitoring systems, including with remote capabilities (i.e., outside of the clean room).

Micro-scale heat-exchangers for Joule-Thomson cooling.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gross, Andrew John

2014-01-01

This project focused on developing a micro-scale counter flow heat exchangers for Joule-Thomson cooling with the potential for both chip and wafer scale integration. This project is differentiated from previous work by focusing on planar, thin film micromachining instead of bulk materials. A process will be developed for fabricating all the devices mentioned above, allowing for highly integrated micro heat exchangers. The use of thin film dielectrics provides thermal isolation, increasing efficiency of the coolers compared to designs based on bulk materials, and it will allow for wafer-scale fabrication and integration. The process is intended to implement a CFHX asmore » part of a Joule-Thomson cooling system for applications with heat loads less than 1mW. This report presents simulation results and investigation of a fabrication process for such devices.« less

Manufacturability of the X Architecture at the 90-nm technology node

NASA Astrophysics Data System (ADS)

Smayling, Michael C.; Sarma, Robin C.; Nagata, Toshiyuki; Arora, Narain; Duane, Michael P.; Oemardani, Shiany; Shah, Santosh

2004-05-01

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon"s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials" wafer inspection and metrology systems.

Through-wafer interrogation of microstructure motion for MEMS feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

1999-09-01

Closed-loop MEMS control enables mechanical microsystems to adapt to the demands of the environment which they are actuating opening a new window of opportunity for future MEMS applications. Planar diffractive optical microsystems have the potential to enable the integrated optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation which is central to realization of feedback control. This paper presents the results of initial research evaluating through-wafer optical microsystems for MEMS integrated optical monitoring. Positional monitoring results obtained from a 1.3 micrometer wavelength through- wafer free-space optical probe of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS) are presented. Given the availability of positional information via probe signal feedback, a simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Method and device for predicting wavelength dependent radiation influences in thermal systems

DOEpatents

Kee, Robert J.; Ting, Aili

1996-01-01

A method and apparatus for predicting the spectral (wavelength-dependent) radiation transport in thermal systems including interaction by the radiation with partially transmitting medium. The predicted model of the thermal system is used to design and control the thermal system. The predictions are well suited to be implemented in design and control of rapid thermal processing (RTP) reactors. The method involves generating a spectral thermal radiation transport model of an RTP reactor. The method also involves specifying a desired wafer time dependent temperature profile. The method further involves calculating an inverse of the generated model using the desired wafer time dependent temperature to determine heating element parameters required to produce the desired profile. The method also involves controlling the heating elements of the RTP reactor in accordance with the heating element parameters to heat the wafer in accordance with the desired profile.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

PubMed

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Composite germanium monochromators - Results for the TriCS single-crystal diffractometer at SINQ

NASA Astrophysics Data System (ADS)

Schefer, J.; Fischer, S.; Böhm, M.; Keller, L.; Horisberger, M.; Medarde, M.; Fischer, P.

Composite germanium monochromators are foremost in application in neutron diffraction due to their good scattering properties, low absorption values and the diamond structure which avoids second-order contamination when using hhk reflections (all odd). Our slices for the monochromator are built from 24 wafers, each 0.4 mm thick. The alignment of the wafers within the final composite wafer package has been improved by adding tin for the soldering process with a sputtering method instead of foils. Nine slices, each 12.5 mm high, are mounted on separate miniature goniometer heads to the focusing monochromator. The focusing angle is controlled by only one motor/digitizer by using a sophisticated mechanism. Turning the monochromator by 9° around overlineω allow access of the 311 (primary) and 511 (secondary) reflection. We also show the importance of permanent quality control with neutrons. The monochromator will be used on the single-crystal diffractometer TriCS at SINQ.

Optical cavity furnace for semiconductor wafer processing

DOEpatents

Sopori, Bhushan L.

2014-08-05

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

High-efficiency neutron detectors and methods of making same

DOEpatents

McGregor, Douglas S.; Klann, Raymond

2007-01-16

Neutron detectors, advanced detector process techniques and advanced compound film designs have greatly increased neutron-detection efficiency. One embodiment of the detectors utilizes a semiconductor wafer with a matrix of spaced cavities filled with one or more types of neutron reactive material such as ¹⁰B or ⁶LiF. The cavities are etched into both the front and back surfaces of the device such that the cavities from one side surround the cavities from the other side. The cavities may be etched via holes or etched slots or trenches. In another embodiment, the cavities are different-sized and the smaller cavities extend into the wafer from the lower surfaces of the larger cavities. In a third embodiment, multiple layers of different neutron-responsive material are formed on one or more sides of the wafer. The new devices operate at room temperature, are compact, rugged, and reliable in design.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

NASA Astrophysics Data System (ADS)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Graphene-Si heterogeneous nanotechnology

NASA Astrophysics Data System (ADS)

Akinwande, Deji; Tao, Li

2013-05-01

It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

Reliable four-point flexion test and model for die-to-wafer direct bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.

2015-07-07

For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, bothmore » D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.« less

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Consequences of atomic layer etching on wafer scale uniformity in inductively coupled plasmas

NASA Astrophysics Data System (ADS)

Huard, Chad M.; Lanham, Steven J.; Kushner, Mark J.

2018-04-01

Atomic layer etching (ALE) typically divides the etching process into two self-limited reactions. One reaction passivates a single layer of material while the second preferentially removes the passivated layer. As such, under ideal conditions the wafer scale uniformity of ALE should be independent of the uniformity of the reactant fluxes onto the wafers, provided all surface reactions are saturated. The passivation and etch steps should individually asymptotically saturate after a characteristic fluence of reactants has been delivered to each site. In this paper, results from a computational investigation are discussed regarding the uniformity of ALE of Si in Cl2 containing inductively coupled plasmas when the reactant fluxes are both non-uniform and non-ideal. In the parameter space investigated for inductively coupled plasmas, the local etch rate for continuous processing was proportional to the ion flux. When operated with saturated conditions (that is, both ALE steps are allowed to self-terminate), the ALE process is less sensitive to non-uniformities in the incoming ion flux than continuous etching. Operating ALE in a sub-saturation regime resulted in less uniform etching. It was also found that ALE processing with saturated steps requires a larger total ion fluence than continuous etching to achieve the same etch depth. This condition may result in increased resist erosion and/or damage to stopping layers using ALE. While these results demonstrate that ALE provides increased etch depth uniformity, they do not show an improved critical dimension uniformity in all cases. These possible limitations to ALE processing, as well as increased processing time, will be part of the process optimization that includes the benefits of atomic resolution and improved uniformity.

Comparison of binary mask defect printability analysis using virtual stepper system and aerial image microscope system

NASA Astrophysics Data System (ADS)

Phan, Khoi A.; Spence, Chris A.; Dakshina-Murthy, S.; Bala, Vidya; Williams, Alvina M.; Strener, Steve; Eandi, Richard D.; Li, Junling; Karklin, Linard

1999-12-01

As advanced process technologies in the wafer fabs push the patterning processes toward lower k1 factor for sub-wavelength resolution printing, reticles are required to use optical proximity correction (OPC) and phase-shifted mask (PSM) for resolution enhancement. For OPC/PSM mask technology, defect printability is one of the major concerns. Current reticle inspection tools available on the market sometimes are not capable of consistently differentiating between an OPC feature and a true random defect. Due to the process complexity and high cost associated with the making of OPC/PSM reticles, it is important for both mask shops and lithography engineers to understand the impact of different defect types and sizes to the printability. Aerial Image Measurement System (AIMS) has been used in the mask shops for a number of years for reticle applications such as aerial image simulation and transmission measurement of repaired defects. The Virtual Stepper System (VSS) provides an alternative method to do defect printability simulation and analysis using reticle images captured by an optical inspection or review system. In this paper, pre- programmed defects and repairs from a Defect Sensitivity Monitor (DSM) reticle with 200 nm minimum features (at 1x) will be studied for printability. The simulated resist lines by AIMS and VSS are both compared to SEM images of resist wafers qualitatively and quantitatively using CD verification.Process window comparison between unrepaired and repaired defects for both good and bad repair cases will be shown. The effect of mask repairs to resist pattern images for the binary mask case will be discussed. AIMS simulation was done at the International Sematech, Virtual stepper simulation at Zygo and resist wafers were processed at AMD-Submicron Development Center using a DUV lithographic process for 0.18 micrometer Logic process technology.

Evaluation of anti-sticking layers performances for 200mm wafer scale Smart NILTM process through surface and defectivity characterizations

NASA Astrophysics Data System (ADS)

Delachat, F.; Phillipe, J.-C.; Larrey, V.; Fournel, F.; Bos, S.; Teyssèdre, H.; Chevalier, Xavier; Nicolet, Célia; Navarro, Christophe; Cayrefourcq, Ian

2018-03-01

In this work, an evaluation of various ASL processes for 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti through the INSPIRE program is reported. The surface and adherence energies were correlated to the AFM and defectivity results in order to select the most promising ASL process for high resolution etch mask applications. The ASL performances of the selected process were evaluated by multiple working stamp fabrication using unpatterned and patterned masters though defectivity monitoring on optical based-inspection tools. Optical and SEM defect reviews were systematically performed. Multiple working stamps fabrication without degradation of the master defectivity was witnessed. This evaluation enabled to benchmark several ASL solutions based on the grafted technology develop by ARKEMA in order to reduce and optimize the soft stamp defectivity prior to its replication and therefore considerably reduce the final imprint defectivity for the Smart NIL process.

Internal gas and liquid distributor for electrodeionization device

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Henry, Michael P.; Datta, Saurav

2016-05-17

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The gas and aqueous fluid are introduced into each basic wafer via a porous gas distributor which disperses the gas as micro-sized bubbles laterally throughout the distributor before entering the wafer. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme or inorganic catalyst to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Single Crystal DMs for Space-Based Observatories

NASA Astrophysics Data System (ADS)

Bierden, Paul

We propose to demonstrate the feasibility of a new manufacturing process for large aperture, high-actuator count microelectromechanical deformable mirrors (MEMS-DMs). These DMs are designed to fill a critical technology gap in NASA s plan for high- contrast space-based exoplanet observatories. We will manufacture a prototype DM with a continuous mirror facesheet, having an active aperture of 50mm diameter, supported by 2040 electrostatic actuators (50 across the diameter of the active aperture), spaced at a pitch of 1mm. The DM will be manufactured using silicon microfabrication tools. The strategic motivation for the proposed project is to advance MEMS DMs as an enabling technology in NASA s rapidly emerging program for extrasolar planet exploration. That goal is supported by an Astro2010 white paper on Technologies for Direct Optical Imaging of Exoplanets, which concluded that DMs are a critical component for all proposed internal coronagraph instrument concepts. That white paper pointed to great strides made by DM developers in the past decade, and acknowledged the components made by Boston Micromachines Corporation to be the most notable MEMS-based technology option. The principal manufacturing innovation in this project will be assembly of the DM through fusion bonding of three separate single crystal silicon wafers comprising the device s substrate, actuator array, and facesheet. The most significant challenge of this project will be to develop processes that allow reliable fusion bonds between multiple compliant silicon layers while yielding an optically flat surface and a robust electromechanical system. The compliance of the DM, which is required for its electromechanical function, will make it challenging to achieve the intimate, planar contact that is generally needed for success in fusion bonding. The manufacturing approach will use photolithography and reactive ion etching to pattern structural layers. Three wafer-scale devices will be patterned and etched independently: one for the substrate and fixed electrode layer, one for the actuator layer, and one for the mirror layer. Subsequently, each of these wafers will be bonded through a thermal fusion process to the others. In an innovative new processing technique, we will employ sacrificial oxide pillars to add temporary support to the otherwise compliant device structures. These pillars will be dissolved after assembly. The result will be a stress-free, single crystal silicon device with broadly expanded design space for geometric parameters such as actuator pitch, mirror diameter, array size, and actuator gap. Consequently, this approach will allow us to make devices with characteristics that are needed for some important NASA applications in space-based coronography, especially where larger array sizes, greater actuator pitch, and better optical surface quality are needed. The significance of this work is that it will provide a technology platform that meets or exceeds the superb optical performance that has been demonstrated in conventional pizezoelectrically actuated DMs, while retaining the advantages in cost, repeatability, and thermal insensitivity that have been demonstrated in the newer generation of MEMS electrostatically actuated DMs. The shift to bonded single-crystal structures will eliminate the single biggest drawback in previously reported NASA-fielded MEMS DM technology: device susceptibility to stress-induced scalloping and print through artifacts resulting from polycrystalline thin film surface micromachining. With single crystal structures bonded at atomic scales, uncorrected surface topography can be controlled to subnanometer levels, enabling the advancement of NASA s next-generation space-based coronagraphs.

Water quality and processes affecting dissolved oxygen concentrations in the Blackwater River, Canaan Valley, West Virginia

USGS Publications Warehouse

Waldron, M.C.; Wiley, J.B.

1996-01-01

The water quality and environmental processes affecting dissolved oxygen were determined for the Blackwater River in Canaan Valley, West Virginia. Canaan Valley is oval-shaped (14 miles by 5 miles) and is located in the Allegheny Mountains at an average elevation of 3,200 feet above sea level. Tourism, population, and real estate development have increased in the past two decades. Most streams in Canaan Valley are a dilute calcium magnesium bicarbonate-type water. Streamwater typicaly was soft and low in alkalinity and dissolved solids. Maximum values for specific conductance, hardness, alkalinity, and dissolved solids occurred during low-flow periods when streamflow was at or near baseflow. Dissolved oxygen concentrations are most sensitive to processes affecting the rate of reaeration. The reaeration is affected by solubility (atmospheric pressure, water temperature, humidity, and cloud cover) and processes that determine stream turbulence (stream depth, width, velocity, and roughness). In the headwaters, photosynthetic dissolved oxygen production by benthic algae can result in supersaturated dissolved oxygen concentrations. In beaver pools, dissolved oxygen consumption from sediment oxygen demand and carbonaceous biochemical oxygen demand can result in dissolved oxygen deficits.

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Empirical OPC rule inference for rapid RET application

NASA Astrophysics Data System (ADS)

Kulkarni, Anand P.

2006-10-01

A given technological node (45 nm, 65 nm) can be expected to process thousands of individual designs. Iterative methods applied at the node consume valuable days in determining proper placement of OPC features, and manufacturing and testing mask correspondence to wafer patterns in a trial-and-error fashion for each design. Repeating this fabrication process for each individual design is a time-consuming and expensive process. We present a novel technique which sidesteps the requirement to iterate through the model-based OPC analysis and pattern verification cycle on subsequent designs at the same node. Our approach relies on the inference of rules from a correct pattern at the wafer surface it relates to the OPC and pre-OPC pattern layout files. We begin with an offline phase where we obtain a "gold standard" design file that has been fab-tested at the node with a prepared, post-OPC layout file that corresponds to the intended on-wafer pattern. We then run an offline analysis to infer rules to be used in this method. During the analysis, our method implicitly identifies contextual OPC strategies for optimal placement of RET features on any design at that node. Using these strategies, we can apply OPC to subsequent designs at the same node with accuracy comparable to the original design file but significantly smaller expected runtimes. The technique promises to offer a rapid and accurate complement to existing RET application strategies.

Distinguishing dose, focus, and blur for lithography characterization and control

NASA Astrophysics Data System (ADS)

Ausschnitt, Christopher P.; Brunner, Timothy A.

2007-03-01

We derive a physical model to describe the dependence of pattern dimensions on dose, defocus and blur. The coefficients of our model are constants of a given lithographic process. Model inversion applied to dimensional measurements then determines effective dose, defocus and blur for wafers patterned with the same process. In practice, our approach entails the measurement of proximate grating targets of differing dose and focus sensitivity. In our embodiment, the measured attribute of one target is exclusively sensitive to dose, whereas the measured attributes of a second target are distinctly sensitive to defocus and blur. On step-and-scan exposure tools, z-blur is varied in a controlled manner by adjusting the across slit tilt of the image plane. The effects of z-blur and x,y-blur are shown to be equivalent. Furthermore, the exposure slit width is shown to determine the tilt response of the grating attributes. Thus, the response of the measured attributes can be characterized by a conventional focus-exposure matrix (FEM), over which the exposure tool settings are intentionally changed. The model coefficients are determined by a fit to the measured FEM response. The model then fully defines the response for wafers processed under "fixed" dose, focus and blur conditions. Model inversion applied to measurements from the same targets on all such wafers enables the simultaneous determination of effective dose and focus/tilt (DaFT) at each measurement site.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to achieving millisecond lifetimes in kerfless silicon materials. Laser fired contacts to n-Si were developed for the first time using a Al/Sb/Ti metal stack giving contact resistances < 5 mOhm-cm2 when fired through several different dielectric layers. A new 2 step laser+chemical etch isolation technique was developed using a sacrificial top coating which avoids laser damage to Si passivation. Regarding the heterojunction emitter, analysis of front FHJ (1D) and IBC (2D) cells with range of p-layer conditions found that a 2-stage high/low doped p-layer was optimum: the low doped region has lower defects giving higher Voc and the high doped region gave a better contact to the metal. A significant effort was spent studying the patterning process and its contribution to degradation of passivation and reproducibility. Several promising new cleaning, contact and deposition patterning and processing approaches were implemented leading to fabrication of several runs with cells having 19-20% efficiency which were stable over several months. This program resulted in the training and support of 12 graduate students, publication of 21 journal papers and 14 conference papers.« less

Honeycomb Films with Core-Shell Dispersed Phases Prepared by the Combination of Breath Figures and Phase Separation Process of Ternary Blends.

PubMed

Del Campo, A; de León, A S; Rodríguez-Hernández, J; Muñoz-Bonilla, A

2017-03-21

Herein, we propose a strategy to fabricate core-shell microstructures ordered in hexagonal arrays by combining the breath figures approach and phase separation of immiscible ternary blends. This simple strategy to fabricate these structures involves only the solvent casting of a ternary polymer blend under moist atmosphere, which provides a facile and low-cost fabrication method to obtain the porous structures with a core-shell morphology. For this purpose, blends consisting of polystyrene (PS) as a major component and PS 40 -b-P(PEGMA300) 48 amphiphilic copolymer and polydimethylsiloxane (PDMS) as minor components were dissolved in tetrahydrofuran and cast onto glass wafers under humid conditions, 70% of relative humidity. The resulting porous morphologies were characterized by optical and confocal Raman microscopy. In particular, confocal Raman results demonstrated the formation of core-shell morphologies into the ordered pores, in which the PS forms the continuous matrix, whereas the other two phases are located into the cavities (PDMS is the core while the amphiphilic copolymer is the shell). Besides, by controlling the weight ratio of the polymer blends, the structural parameters of the porous structure such as pore diameter and the size of the core can be effectively tuned.

Chemical vapor deposition for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1980-01-01

Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

Superconducting Vacuum-Gap Crossovers for High Performance Microwave Applications

NASA Technical Reports Server (NTRS)

Denis, Kevin L.; Brown, Ari D.; Chang, Meng-Ping; Hu, Ron; U-Yen, Kongpop; Wollack, Edward J.

2016-01-01

The design and fabrication of low-loss wide-bandwidth superconducting vacuum-gap crossovers for high performance millimeter wave applications are described. In order to reduce ohmic and parasitic losses at millimeter wavelengths a vacuum gap is preferred relative to dielectric spacer. Here, vacuum-gap crossovers were realized by using a sacrificial polymer layer followed by niobium sputter deposition optimized for coating coverage over an underlying niobium signal layer. Both coplanar waveguide and microstrip crossover topologies have been explored in detail. The resulting fabrication process is compatible with a bulk micro-machining process for realizing waveguide coupled detectors, which includes sacrificial wax bonding, and wafer backside deep reactive ion etching for creation of leg isolated silicon membrane structures. Release of the vacuum gap structures along with the wax bonded wafer after DRIE is implemented in the same process step used to complete the detector fabrication. ?

Silicon solar cell process development, fabrication, and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Work has progressed in fabrication and characterization of solar cells from ubiquitous crystallization process (UCP) wafers and LASS ribbons. Gettering tests applied to UCP wafers made little change on their performance compared with corresponding baseline data. Advanced processes such as shallow junction (SJ), back surface field (BSF), and multilayer antireflection (MLAR) were also applied. While BSF by Al paste had shunting problems, cells with SJ and BSF by evaporated Al, and MLAR did achieve 14.1% AMI on UCP silicon. The study of LASS material was very preliminary. Only a few cells with SJ, BSR, (no BSF) and MLAR were completed due to mechanical yield problems after lapping the material. Average efficiency was 10.7% AMI with 13.4% AMI for CZ controls. Relatively high minority carrier diffusion lengths were obtained. The lower than expected Jsc could be partially explained by low active area due to irregular sizes.

Design Study of Wafer Seals for Future Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Investigating Students' Understanding of the Dissolving Process

ERIC Educational Resources Information Center

Naah, Basil M.; Sanger, Michael J.

2013-01-01

In a previous study, the authors identified several student misconceptions regarding the process of dissolving ionic compounds in water. The present study used multiple-choice questions whose distractors were derived from these misconceptions to assess students' understanding of the dissolving process at the symbolic and particulate levels. The…

Demonstration of lithography patterns using reflective e-beam direct write

NASA Astrophysics Data System (ADS)

Freed, Regina; Sun, Jeff; Brodie, Alan; Petric, Paul; McCord, Mark; Ronse, Kurt; Haspeslagh, Luc; Vereecke, Bart

2011-04-01

Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this work, we report on the development and current status of a new maskless, direct write e-beam lithography tool which has the potential for high volume lithography at and below the 22 nm technology node. A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The lens elements on the DPG are fabricated at IMEC (Leuven, Belgium) under IMEC's CMORE program. The CMOS fabricated DPG contains ~ 1,000,000 lens elements, allowing for 1,000,000 individually controllable beamlets. A single lens element consists of 5 electrodes, each of which can be set at controlled voltage levels to either absorb or reflect the electron beam. A system using a linear movable stage and the DPG integrated into the electron optics module was used to expose patterns on device representative wafers. Results of these exposure tests are discussed.

Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

NASA Technical Reports Server (NTRS)

Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

1996-01-01

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

Concurrent design of an RTP chamber and advanced control system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spence, P.; Schaper, C.; Kermani, A.

1995-12-31

A concurrent-engineering approach is applied to the development of an axisymmetric rapid-thermal-processing (RTP) reactor and its associated temperature controller. Using a detailed finite-element thermal model as a surrogate for actual hardware, the authors have developed and tested a multi-input multi-output (MIMO) controller. Closed-loop simulations are performed by linking the control algorithm with the finite-element code. Simulations show that good temperature uniformity is maintained on the wafer during both steady and transient conditions. A numerical study shows the effect of ramp rate, feedback gain, sensor placement, and wafer-emissivity patterns on system performance.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.