Hetero-Material Gate Doping-Less Tunnel FET and Its Misalignment Effects on Analog/RF Parameters

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2018-03-01

In this paper, with the use of a hetero-material gate technique, a tunnel field-effect transistor (TFET) subject to charge plasma technique is proposed, named as hetero-material gate doping-less tunnel FET (HMG-DLTFET) and a brief study has been done on the effects due to misalignment of the bottom gate towards drain (GMAD) and towards source (GMAS). The proposed devices provide better performance as the drive current increased by three times as compared to conventional doping-less TFET (DLTFET). The results are then analyzed and compared with conventional doped hetero-material gate double-gate tunnel FET (HMG-DGTFET). The analog/radiofrequency (RF) performance has been studied for both devices and comparative analysis has been done for different parameters such as drain current (I D), transconductance (g m), output conductance (g d), total gate capacitance (C gg) and cutoff frequency (f T). Both devices performed similarly in different misalignment configurations. When the bottom gate is perfectly aligned, the best performance is observed for both devices, but the doping-less device gives slightly more freedom for fabrication engineers as the amount of tolerance for HMG-DLTFET is better than that of HMG-DGTFET.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Analog and RF performance of a multigate FinFET at nano scale

NASA Astrophysics Data System (ADS)

Kumar, Abhishek

2016-12-01

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

NASA Astrophysics Data System (ADS)

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

2015-09-01

A carrier-based analytical drain current model for negative capacitance symmetric double-gate field effect transistors (NC-SDG FETs) is proposed by solving the differential equation of the carrier, the Pao-Sah current formulation, and the Landau-Khalatnikov equation. The carrier equation is derived from Poisson’s equation and the Boltzmann distribution law. According to the model, an amplified semiconductor surface potential and a steeper subthreshold slope could be obtained with suitable thicknesses of the ferroelectric film and insulator layer at room temperature. Results predicted by the analytical model agree well with those of the numerical simulation from a 2D simulator without any fitting parameters. The analytical model is valid for all operation regions and captures the transitions between them without any auxiliary variables or functions. This model can be used to explore the operating mechanisms of NC-SDG FETs and to optimize device performance.

Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

PubMed

Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

2014-02-25

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

MEMS based highly sensitive dual FET gas sensor using graphene decorated Pd-Ag alloy nanoparticles for H2 detection.

PubMed

Sharma, Bharat; Kim, Jung-Sik

2018-04-12

A low power, dual-gate field-effect transistor (FET) hydrogen gas sensor with graphene decorated Pd-Ag for hydrogen sensing applications was developed. The FET hydrogen sensor was integrated with a graphene-Pd-Ag-gate FET (GPA-FET) as hydrogen sensor coupled with Pt-gate FET as a reference sensor on a single sensor platform. The sensing gate electrode was modified with graphene by an e-spray technique followed by Pd-Ag DC/MF sputtering. Morphological and structural properties were studied by FESEM and Raman spectroscopy. FEM simulations were performed to confirm the uniform temperature control at the sensing gate electrode. The GPA-FET showed a high sensing response to hydrogen gas at the temperature of 25~254.5 °C. The as-proposed FET H 2 sensor showed the fast response time and recovery time of 16 s, 14 s, respectively at the operating temperature of 245 °C. The variation in drain current was positively related with increased working temperature and hydrogen concentration. The proposed dual-gate FET gas sensor in this study has potential applications in various fields, such as electronic noses and automobiles, owing to its low-power consumption, easy integration, good thermal stability and enhanced hydrogen sensing properties.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

NASA Astrophysics Data System (ADS)

Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.

2016-08-01

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p+-p-p+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2-4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 105. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

PubMed

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Gate length scaling optimization of FinFETs

NASA Astrophysics Data System (ADS)

Chen, Shoumian; Shang, Enming; Hu, Shaojian

2018-06-01

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (Ioff) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (Isat) of the PMOS. In order to sustain Ioff, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with Ioff = 1 nA/um, the best performance Isat = 856 uA/um is at L = 34 nm for 14 nm FinFET and Isat = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

Trilayer TMDC Heterostructures for MOSFETs and Nanobiosensors

NASA Astrophysics Data System (ADS)

Datta, Kanak; Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-02-01

Two dimensional materials such as transition metal dichalcogenides (TMDC) and their bi-layer/tri-layer heterostructures have become the focus of intense research and investigation in recent years due to their promising applications in electronics and optoelectronics. In this work, we have explored device level performance of trilayer TMDC heterostructure (MoS2/MX2/MoS2; M = Mo or, W and X = S or, Se) metal oxide semiconductor field effect transistors (MOSFETs) in the quantum ballistic regime. Our simulation shows that device `on' current can be improved by inserting a WS2 monolayer between two MoS2 monolayers. Application of biaxial tensile strain reveals a reduction in drain current which can be attributed to the lowering of carrier effective mass with increased tensile strain. In addition, it is found that gate underlap geometry improves electrostatic device performance by improving sub-threshold swing. However, increase in channel resistance reduces drain current. Besides exploring the prospect of these materials in device performance, novel trilayer TMDC heterostructure double gate field effect transistors (FETs) are proposed for sensing Nano biomolecules as well as for pH sensing. Bottom gate operation ensures these FETs operating beyond Nernst limit of 59 mV/pH. Simulation results found in this work reveal that scaling of bottom gate oxide results in better sensitivity while top oxide scaling exhibits an opposite trend. It is also found that, for identical operating conditions, proposed TMDC FET pH sensors show super-Nernst sensitivity indicating these materials as potential candidates in implementing such sensor. Besides pH sensing, all these materials show high sensitivity in the sub-threshold region as a channel material in nanobiosensor while MoS2/WS2/MoS2 FET shows the least sensitivity among them.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gasparyan, F.; Forschungszentrum Jülich, Peter Grünberg Institute; Khondkaryan, H.

2016-08-14

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p{sup +}-p-p{sup +} field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculatingmore » the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10{sup 5}. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.« less

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Development of molecularly imprinted polymer-based field effect transistor for sugar chain sensing

NASA Astrophysics Data System (ADS)

Nishitani, Shoichi; Kajisa, Taira; Sakata, Toshiya

2017-04-01

In this study, we developed a molecularly imprinted polymer-based field-effect transistor (MIP-gate FET) for selectively detecting sugar chains in aqueous media, focusing on 3‧-sialyllactose (3SLac) and 6‧-sialyllactose (6SLac). The FET biosensor enables the detection of small molecules as long as they have intrinsic charges. Additionally, the MIP gels include the template for the target molecule, which is selectively trapped without requiring enzyme-target molecule reaction. The MIP gels were synthesized on the gate surface of the FET device, including phenylboronic acid (PBA), which enables binding to sugar chains. Firstly, the 3SLac-MIP-gate FET quantitatively detected 3SLac at µM levels. This is because the FET device recognized the change in molecular charges on the basis of PBA-3SLac binding in the MIP gel. Moreover, 3SLac was selectively detected using the 3SLac- and 6SLac-MIP-gate FETs to some extent, where the detecting signal from the competent was suppressed by 40% at maximum. Therefore, a platform based on the MIP-coupled FET biosensor is suitable for a selective biosensing system in an enzyme-free manner, which can be applied widely in medical fields. However, we need to further improve the selectivity of MIP-gate FETs to discriminate more clearly between similar structures of sugar chains such as 3SLac and 6SLac.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

NASA Astrophysics Data System (ADS)

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito; Fujii, Eiji; Tsujimura, Ayumu

2013-04-01

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Inrush Current Suppression Circuit and Method for Controlling When a Load May Be Fully Energized

NASA Technical Reports Server (NTRS)

Schwerman, Paul (Inventor)

2017-01-01

A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.

Four-gate transistor analog multiplier circuit

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Ka-band Ga-As FET noise receiver/device development

NASA Technical Reports Server (NTRS)

Schellenberg, J. M.; Feng, M.; Hackett, L. H.; Watkins, E. T.; Yamasaki, H.

1982-01-01

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.

Improving subthreshold swing to thermionic emission limit in carbon nanotube network film-based field-effect

NASA Astrophysics Data System (ADS)

Zhao, Chenyi; Zhong, Donglai; Qiu, Chenguang; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2018-01-01

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3 nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2 μm) that exhibit an SS of approximately 60 mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7 nm and 10 nm, simultaneously yielding an excellent SS (<80 mV/decade) and low gate leakage. However, because of the statistical fluctuations of the network CNT channel, the lateral scaling of CNT network film-based FETs is more difficult than that of conventional FETs. Experiments suggest that excellent SS is difficult to achieve statistically in CNT network film FETs with a small channel length (smaller than the mean length of the CNTs), which eventually limits the further scaling down of this kind of CNT FET to the sub-micrometer regime.

Tunable Electrical and Optical Characteristics in Monolayer Graphene and Few-Layer MoS2 Heterostructure Devices.

PubMed

Rathi, Servin; Lee, Inyeal; Lim, Dongsuk; Wang, Jianwei; Ochiai, Yuichi; Aoki, Nobuyuki; Watanabe, Kenji; Taniguchi, Takashi; Lee, Gwan-Hyoung; Yu, Young-Jun; Kim, Philip; Kim, Gil-Ho

2015-08-12

Lateral and vertical two-dimensional heterostructure devices, in particular graphene-MoS2, have attracted profound interest as they offer additional functionalities over normal two-dimensional devices. Here, we have carried out electrical and optical characterization of graphene-MoS2 heterostructure. The few-layer MoS2 devices with metal electrode at one end and monolayer graphene electrode at the other end show nonlinearity in drain current with drain voltage sweep due to asymmetrical Schottky barrier height at the contacts and can be modulated with an external gate field. The doping effect of MoS2 on graphene was observed as double Dirac points in the transfer characteristics of the graphene field-effect transistor (FET) with a few-layer MoS2 overlapping the middle part of the channel, whereas the underlapping of graphene have negligible effect on MoS2 FET characteristics, which showed typical n-type behavior. The heterostructure also exhibits a strongest optical response for 520 nm wavelength, which decreases with higher wavelengths. Another distinct feature observed in the heterostructure is the peak in the photocurrent around zero gate voltage. This peak is distinguished from conventional MoS2 FETs, which show a continuous increase in photocurrent with back-gate voltage. These results offer significant insight and further enhance the understanding of the graphene-MoS2 heterostructure.

Fabrication, testing and reliability modeling of copper/titanium-metallized GaAs MESFETs and HEMTs for low-noise applications

NASA Astrophysics Data System (ADS)

Feng, Ting

Today, GaAs based field effect transistors (FETs) have been used in a broad range of high-speed electronic military and commercial applications. However, their reliability still needs to be improved. Particularly the hydrogen induced degradation is a large remaining issue in the reliability of GaAs FETs, because hydrogen can easily be incorporated into devices during the crystal growth and virtually every device processing step. The main objective of this research work is to develop a new gate metallization system in order to reduce the hydrogen induced degradation from the gate region for GaAs based MESFETs and HEMTs. Cu/Ti gate metallization has been introduced into the GaAs MESFETs and HEMTs in our work in order to solve the hydrogen problem. The purpose of the use of copper is to tie up the hydrogen atoms and prevent hydrogen penetration into the device active region as well as to keep a low gate resistance for low noise applications. In this work, the fabrication technology of GaAs MESFETs and AlGaAs/GaAs HEMTs with Cu/Ti metallized gates have been successfully developed and the fabricated Cu/Ti FETs have shown comparable DC performance with similar Au-based GaAs FETs. The Cu/Ti FETs were subjected to temperature accelerated testing at NOT under 5% hydrogen forming gas and the experimental results show the hydrogen induced degradation has been reduced for the Cu/Ti FETs compared to commonly used AuPtTi based GaAs FETs. A long-term reliability testing for Cu/Ti FETs has also been carried out at 200°C and up to 1000hours and testing results show Cu/Ti FETs performed with adequate reliability. The failure modes were found to consist of a decrease in drain saturation current and pinch-off voltage and an increase in source ohmic contact resistance. Material characterization tools including Rutherford backscattering spectroscopy and a back etching technique were used in Cu/Ti GaAs FETs, and pronounced gate metal copper in-diffusion and intermixing compounds at the interface between the gate and GaAs channel layer were found. A quantifying gate sinking degradation model was developed in order to extend device physics models to reliability testing results of Cu/Ti GaAs FETs. The gate sinking degradation model includes the gate metal and hydrogen in-diffusion effect, decrease of effective channel due to the formation of interfacial compounds, decrease of electron mobility due to the increase of in-diffused impurities, and donor compensation from in-diffused metal impurity acceptors or hydrogen passivation. A variational charge control model was applied to simulate and understand the degradation mechanisms of Cu/Ti HEMTs, including hydrogen induced degradation due to the neutralization of donors. The degradation model established in this study is also applicable to other Au or Al metallized GaAs FETs for understanding the failure mechanisms induced by gate sinking and hydrogen neutralization of donors and con-elating the device physics model with reliability testing results.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

Large electron concentration modulation using capacitance enhancement in SrTiO{sub 3}/SmTiO{sub 3} Fin-field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verma, Amit, E-mail: averma@cornell.edu; Nomoto, Kazuki; School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853

2016-05-02

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 10{sup 14 }cm{sup −2}) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO{sub 3}/GdTiO{sub 3} or SrTiO{sub 3}/SmTiO{sub 3}) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO{sub 3}/5 nm SmTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance comparedmore » to planar FETs. By scaling down the SrTiO{sub 3}/SmTiO{sub 3} fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 10{sup 14 }cm{sup −2}.« less

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography.

PubMed

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-01-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

NASA Astrophysics Data System (ADS)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Bias-stress characterization of solution-processed organic field-effect transistor based on highly ordered liquid crystals

NASA Astrophysics Data System (ADS)

Kunii, M.; Iino, H.; Hanna, J.

2017-06-01

Bias-stress effects in solution-processed, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) field effect transistors (FETs) are studied under negative and positive direct current bias. The bottom gate, bottom contact polycrystalline Ph-BTBT-10 FET with a hybrid gate dielectric of polystyrene and SiO2 shows high field effect mobility as well as a steep subthreshold slope when fabricated with a highly ordered smectic E liquid crystalline (SmE) film as a precursor. Negative gate bias-stress causes negative threshold voltage shift (ΔVth) for Ph-BTBT-10 FET in ambient air, but ΔVth rapidly decreases as the gate bias decreases and approaches to near zero when the gate bias goes down to 9 V in amplitude. In contrast, positive gate bias-stress causes negligible ΔVth even with a relatively high bias voltage. These results conclude that Ph-BTBT-10 FET has excellent bias-stress stability in ambient air in the range of low to moderate operating voltages.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

The physical analysis on electrical junction of junctionless FET

NASA Astrophysics Data System (ADS)

Chen, Lun-Chun; Yeh, Mu-Shih; Lin, Yu-Ru; Lin, Ko-Wei; Wu, Min-Hsin; Thirunavukkarasu, Vasanthan; Wu, Yung-Chun

2017-02-01

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization.

Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability

NASA Astrophysics Data System (ADS)

Ko, Kyul; Son, Dokyun; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this work, work-function variation (WFV) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire FET (NWFET) and FinFET devices are studied for 6-T SRAM cells through 3D technology computer-aided design (TCAD) simulation. The NWFET devices have strong immunity for the unprecedented short channel effects (SCEs) compared with the FinFET devices owing to increased gate controllability. However, due to the narrow gate area, the single NWFET is more vulnerable to WFV effects than FinFET devices. Our results show that the WFV effects on single NWFETs are larger than the FinFETs by 45-55%. In the case of standard SRAM bit cells (high density: 111 bit cell), the variation of read stability (read static noise margin) on single NWFETs are larger than the FinFETs by 65-75%. Therefore, to improve the performance and having immunity to WFV effects, it is important to analyze the degree of variability in 3D stacked device architectures without area penalty. Moreover, we investigated the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of 3D stacked NWFET in 6-T SRAM bit cells.

Flexure-FET biosensor to break the fundamental sensitivity limits of nanobiosensors using nonlinear electromechanical coupling

PubMed Central

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad A.

2012-01-01

In this article, we propose a Flexure-FET (flexure sensitive field effect transistor) ultrasensitive biosensor that utilizes the nonlinear electromechanical coupling to overcome the fundamental sensitivity limits of classical electrical or mechanical nanoscale biosensors. The stiffness of the suspended gate of Flexure-FET changes with the capture of the target biomolecules, and the corresponding change in the gate shape or deflection is reflected in the drain current of FET. The Flexure-FET is configured to operate such that the gate is biased near pull-in instability, and the FET-channel is biased in the subthreshold regime. In this coupled nonlinear operating mode, the sensitivity (S) of Flexure-FET with respect to the captured molecule density (Ns) is shown to be exponentially higher than that of any other electrical or mechanical biosensor. In other words, while , classical electrical or mechanical biosensors are limited to Sclassical ∼ γ3NS or γ4 ln(NS), where γi are sensor-specific constants. In addition, the proposed sensor can detect both charged and charge-neutral biomolecules, without requiring a reference electrode or any sophisticated instrumentation, making it a potential candidate for various low-cost, point-of-care applications. PMID:22623527

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

NASA Astrophysics Data System (ADS)

McGuire, Felicia A.; Cheng, Zhihui; Price, Katherine; Franklin, Aaron D.

2016-08-01

There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric is studied and shown to be critical. These 2D NC-FETs exhibit a decrease in subthreshold swing from 113 mV/decade down to 11.7 mV/decade at room temperature with sub-60 mV/decade switching occurring over more than 4 decades of current. The P(VDF-TrFE) proves to be an unstable option for a device technology, yet the superb switching behavior observed herein opens the way for further exploration of nanomaterials for extremely low-voltage NC-FETs.

Molecule counting with alkanethiol and DNA immobilized on gold microplates for extended gate FET.

PubMed

Cao, Zhong; Xiao, Zhong-Liang; Zhang, Ling; Luo, Dong-Mei; Kamahori, Masao; Shimoda, Maki

2013-04-01

Several molecule counting methods based on electrochemical characterization of alkanethiol and thiolated single-stranded oligonucleotide (HS-ssDNA) immobilized on gold microplates, which were used as extended gates of field effect transistors (FETs), have been investigated in this paper. The surface density of alkanethiol and DNA monolayers on gold microplates were quantitatively evaluated from the reductive desorption charge by using cyclic voltammetry (CV) and fast CV (FCV) methods in strong alkali solution. Typically, the surface density of 6-hydroxy-1-hexanethiol (6-HHT) was evaluated to be 4.639 molecules/nm(2), and the 28 base-pair dsDNA about 1.226-4.849 molecules/100 nm(2) on Au microplates after post-treatment with 6-HHT. The behaviors on surface potential and capacitance of different aminoalkanethiols on Au microplates were measured in 0.1 mol/L Na2SO4 and 10 mmol/L Tris-HCl (pH=7.4) solutions, indicating that the surface potential increases and the double-layer capacitance decreases with the length of carbon chain increased for the thiol monolayers, which obey a physics relationship for a capacitor. Comparably, a simple sensing method based on the electronic signals of biochemical reaction events on DNA immobilization and hybridization at the Au surface of the extended gate FET (EGFET) was developed, with which the surface density of the hybridized dsDNA on the gold surface of the EGFET was evaluated to be 1.36 molecules per 100 nm(2), showing that the EGFET is a promising sensing biochip for DNA molecule counting. Copyright © 2012 Elsevier B.V. All rights reserved.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

GIDL analysis of the process variation effect in gate-all-around nanowire FET

NASA Astrophysics Data System (ADS)

Kim, Shinkeun; Seo, Youngsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, the gate-induced drain leakage (GIDL) is analyzed on gate-all-around (GAA) Nanowire FET (NW FET) with ellipse-shaped channel induced by process variation effect (PVE). The fabrication process of nanowire can lead to change the shape of channel cross section from circle to ellipse. The effect of distorted channel shape is investigated and verified by technology computer-aided design (TCAD) simulation in terms of the GIDL current. The simulation results demonstrate that the components of GIDL current are two mechanisms of longitudinal band-to-band tunneling (L-BTBT) at body/drain junction and transverse band-to-band tunneling (T-BTBT) at gate/drain junction. These two mechanisms are investigated on channel radius (rnw) and aspect ratio of ellipse-shape respectively and together.

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

NASA Astrophysics Data System (ADS)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A lifetime projection is carried out assuming that HCI is the major degradation mechanism and it is shown that a 3.4x improvement in device lifetime is possible over symmetric underlapped n-FinFET.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts

NASA Astrophysics Data System (ADS)

Cho, Sang-Hyeok; Cho, Kwanghee; Park, No-Won; Park, Soonyong; Koh, Jung-Hyuk; Lee, Sang-Kwon

2017-05-01

We report p-type tin monoselenide (SnSe) single crystals, grown in double-sealed quartz ampoules using a modified Bridgman technique at 920 °C. X-ray powder diffraction (XRD) and energy dispersive X-ray spectroscopy (EDX) measurements clearly confirm that the grown SnSe consists of single-crystal SnSe. Electrical transport of multi-layer SnSe nanoflakes, which were prepared by exfoliation from bulk single crystals, was conducted using back-gated field-effect transistor (FET) structures with Au and Ti contacts on SiO2/Si substrates, revealing that multi-layer SnSe nanoflakes exhibit p-type semiconductor characteristics owing to the Sn vacancies on the surfaces of SnSe nanoflakes. In addition, a strong carrier screening effect was observed in 70-90-nm-thick SnSe nanoflake FETs. Furthermore, the effect of the metal contacts to multi-layer SnSe nanoflake-based FETs is also discussed with two different metals, such as Ti/Au and Au contacts.

Direct detector for terahertz radiation

DOEpatents

Wanke, Michael C [Albuquerque, NM; Lee, Mark [Albuquerque, NM; Shaner, Eric A [Albuquerque, NM; Allen, S James [Santa Barbara, CA

2008-09-02

A direct detector for terahertz radiation comprises a grating-gated field-effect transistor with one or more quantum wells that provide a two-dimensional electron gas in the channel region. The grating gate can be a split-grating gate having at least one finger that can be individually biased. Biasing an individual finger of the split-grating gate to near pinch-off greatly increases the detector's resonant response magnitude over prior QW FET detectors while maintaining frequency selectivity. The split-grating-gated QW FET shows a tunable resonant plasmon response to FIR radiation that makes possible an electrically sweepable spectrometer-on-a-chip with no moving mechanical optical parts. Further, the narrow spectral response and signal-to-noise are adequate for use of the split-grating-gated QW FET in a passive, multispectral terahertz imaging system. The detector can be operated in a photoconductive or a photovoltaic mode. Other embodiments include uniform front and back gates to independently vary the carrier densities in the channel region, a thinned substrate to increase bolometric responsivity, and a resistive shunt to connect the fingers of the grating gate in parallel and provide a uniform gate-channel voltage along the length of the channel to increase the responsivity and improve the spectral resolution.

Four-Quadrant Analog Multipliers Using G4-FETs

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Blalock, Benjamin; Christoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

2006-01-01

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

A convenient method of manufacturing liquid-gated MoS2 field effect transistors

NASA Astrophysics Data System (ADS)

Lin, Kabin; Yuan, Zhishan; Yu, Yu; Li, Kun; Li, Zhongwu; Sha, Jingjie; Li, Tie; Chen, Yunfei

2017-10-01

In this paper, we present a simple and convenient method of manufacturing liquid-gated MoS2 field effect transistors (FETs). A Si3N4 chip is firstly fabricated by the semiconductor manufacturing process, then the mechanical exfoliation MoS2 is transferred onto the Si3N4 chip and is connected with the gold electrodes by depositing platinum to construct the MoS2 FETs. The liquid-gated is formed by injecting 0.1 M NaCl solution into reservoir to contact the back side of the Si3N4. Our measured results show that the contact properties between MoS2 and electrodes are in well condition and the liquid-gated MoS2 FETs have a high mobility that can reach up to 109 cm2 V-1 s-1.

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

NASA Astrophysics Data System (ADS)

Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

2016-04-01

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

Metal-semiconductor barrier modulation for high photoresponse in transition metal dichalcogenide field effect transistors.

PubMed

Li, Hua-Min; Lee, Dae-Yeong; Choi, Min Sup; Qu, Deshun; Liu, Xiaochi; Ra, Chang-Ho; Yoo, Won Jong

2014-02-10

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

Effects of protein inter-layers on cell-diamond FET characteristics.

PubMed

Rezek, Bohuslav; Krátká, Marie; Kromka, Alexander; Kalbacova, Marie

2010-12-15

Diamond is recognized as an attractive material for merging solid-state and biological systems. The advantage of diamond field-effect transistors (FET) is that they are chemically resistant, bio-compatible, and can operate without gate oxides. Solution-gated FETs based on H-terminated nanocrystalline diamond films exhibiting surface conductivity are employed here for studying effects of fetal bovine serum (FBS) proteins and osteoblastic SAOS-2 cells on diamond electronic properties. FBS proteins adsorbed on the diamond FETs permanently decrease diamond conductivity as reflected by the -45 mV shift of the FET transfer characteristics. Cell cultivation for 2 days results in a further shift by another -78 mV. We attribute it to a change of diamond material properties rather than purely to the field-effect. Increase in gate leakage currents (by a factor of 4) indicates that the FBS proteins also decrease the diamond-electrolyte electronic barrier induced by C-H surface dipoles. We propose a model where the proteins replace ions in the very vicinity of the H-terminated diamond surface. Copyright © 2010 Elsevier B.V. All rights reserved.

A novel radiation hard pixel design for space applications

NASA Astrophysics Data System (ADS)

Aurora, A. M.; Marochkin, V. V.; Tuuva, T.

2017-11-01

We have developed a novel radiation hard photon detector concept based on Modified Internal Gate Field Effect Transistor (MIGFET) wherein a buried Modified Internal Gate (MIG) is implanted underneath a channel of a FET. In between the MIG and the channel of the FET there is depleted semiconductor material forming a potential barrier between charges in the channel and similar type signal charges located in the MIG. The signal charges in the MIG have a measurable effect on the conductance of the channel. In this paper a radiation hard double MIGFET pixel is investigated comprising two MIGFETs. By transferring the signal charges between the two MIGs Non-Destructive Correlated Double Sampling Readout (NDCDSR) is enabled. The radiation hardness of the proposed double MIGFET structure stems from the fact that interface related issues can be considerably mitigated. The reason for this is, first of all, that interface generated dark noise can be completely avoided and secondly, that interface generated 1/f noise can be considerably reduced due to a deep buried channel readout configuration. Electrical parameters of the double MIGFET pixel have been evaluated by 3D TCAD simulation study. Simulation results show the absence of interface generated dark noise, significantly reduced interface generated 1/f noise, well performing NDCDSR operation, and blooming protection due to an inherent vertical anti-blooming structure. In addition, the backside illuminated thick fully depleted pixel design results in low crosstalk due to lack of diffusion and good quantum efficiency from visible to Near Infra-Red (NIR) light. These facts result in excellent Signal-to-Noise Ratio (SNR) and very low crosstalk enabling thus excellent image quality. The simulation demonstrates the charge to current conversion gain for source current read-out to be 1.4 nA/e.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

NASA Astrophysics Data System (ADS)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

NASA Astrophysics Data System (ADS)

Karmakar, Supriya; Suarez, Ernesto; Jain, Faquir C.

2011-08-01

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high- κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO x -Ge quantum dots.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

The 30-GHz monolithic receive module

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Bauhahn, P.

1983-01-01

Key requirements for a 30 GHz GaAs monolithic receive module for spaceborne communication antenna feed array applications include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five-bit phase shifter, and a maximum power consumption of 250 mW. The RF designs for each of the four submodules (low noise amplifier, some gain control, phase shifter, and RF to IF sub-module) are presented. Except for the phase shifter, high frequency, low noise FETs with sub-half micron gate lengths are employed in the submodules. For the gain control, a two stage dual gate FET amplifier is used. The phase shifter is of the passive switched line type and consists of 5-bits. It uses relatively large gate width FETs (with zero drain to source bias) as the switching elements. A 20 GHz local oscillator buffer amplifier, a FET compatible balanced mixer, and a 5-8 GHz IF amplifier constitute the RF/IF sub-module. Phase shifter fabrication using ion implantation and a self-aligned gate technique is described. Preliminary RF results obtained on such phase shifters are included.

Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

NASA Astrophysics Data System (ADS)

Chatterjee, Sulagna; Chattopadhyay, Sanatan

2016-10-01

An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

Toward Quantifying the Electrostatic Transduction Mechanism in Carbon Nanotube Biomolecular Sensors

NASA Astrophysics Data System (ADS)

Lerner, Mitchell; Kybert, Nicholas; Mendoza, Ryan; Dailey, Jennifer; Johnson, A. T. Charlie

2013-03-01

Despite the great promise of carbon nanotube field-effect transistors (CNT FETs) for applications in chemical and biochemical detection, a quantitative understanding of sensor responses is lacking. To explore the role of electrostatics in sensor transduction, experiments were conducted with a set of similar compounds designed to adsorb onto the CNT FET via a pyrene linker group and take on a set of known charge states under ambient conditions. Acidic and basic species were observed to induce threshold voltage shifts of opposite sign, consistent with gating of the CNT FET by local charges due to protonation or deprotonation of the pyrene compounds by interfacial water. The magnitude of the gate voltage shift was controlled by the distance between the charged group and the CNT. Additionally, functionalization with an uncharged pyrene compound showed a threshold shift ascribed to its molecular dipole moment. This work illustrates a method for producing CNT FETs with controlled values of the turnoff gate voltage, and more generally, these results will inform the development of quantitative models for the response of CNT FET chemical and biochemical sensors. As an example, the results of an experiment detecting biomarkers of Lyme disease will be discussed in the context of this model.

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

PubMed

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Glucose-responsive hydrogel electrode for biocompatible glucose transistor

NASA Astrophysics Data System (ADS)

Kajisa, Taira; Sakata, Toshiya

2017-12-01

In this paper, we propose a highly sensitive and biocompatible glucose sensor using a semiconductor-based field effect transistor (FET) with a functionalized hydrogel. The principle of the FET device contributes to the easy detection of ionic charges with high sensitivity, and the hydrogel coated on the electrode enables the specific detection of glucose with biocompatibility. The copolymerized hydrogel on the Au gate electrode of the FET device is optimized by controlling the mixture ratio of biocompatible 2-hydroxyethylmethacrylate (HEMA) as the main monomer and vinylphenylboronic acid (VPBA) as a glucose-responsive monomer. The gate surface potential of the hydrogel FETs shifts in the negative direction with increasing glucose concentration from 10 μM to 40 mM, which results from the increase in the negative charges on the basis of the diol-binding of PBA derivatives with glucose molecules in the hydrogel. Moreover, the hydrogel coated on the gate suppresses the signal noise caused by the nonspecific adsorption of proteins such as albumin. The hydrogel FET can serve as a highly sensitive and biocompatible glucose sensor in in vivo or ex vivo applications such as eye contact lenses and sheets adhering to the skin.

Investigation of Electronic and Opto-Electronic Properties of Two-Dimensional (2D) Layers of Copper Indium Selenide Field Effect Transistors

NASA Astrophysics Data System (ADS)

Patil, Prasanna Dnyaneshwar

Investigations performed in order to understand the electronic and optoelectronic properties of field effect transistors based on few layers of 2D Copper Indium Selenide (CuIn7Se11) are reported. In general, field effect transistors (FETs), electric double layer field effect transistors (EDL-FETs), and photodetectors are crucial part of several electronics based applications such as tele-communication, bio-sensing, and opto-electronic industry. After the discovery of graphene, several 2D semiconductor materials like TMDs (MoS2, WS2, and MoSe2 etc.), group III-VI materials (InSe, GaSe, and SnS2 etc.) are being studied rigorously in order to develop them as components in next generation FETs. Traditionally, thin films of ternary system of Copper Indium Selenide have been extensively studied and used in optoelectronics industry as photoactive component in solar cells. Thus, it is expected that atomically thin 2D layered structure of Copper Indium Selenide can have optical properties that could potentially be more advantageous than its thin film counterpart and could find use for developing next generation nano devices with utility in opto/nano electronics. Field effect transistors were fabricated using few-layers of CuIn7Se11 flakes, which were mechanically exfoliated from bulk crystals grown using chemical vapor transport technique. Our FET transport characterization measurements indicate n-type behavior with electron field effect mobility microFE ≈ 36 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. We found that in such back gated field effect transistor an on/off ratio of 104 and a subthreshold swing ≈ 1 V/dec can be obtained. Our investigations further indicate that Electronic performance of these materials can be increased significantly when gated from top using an ionic liquid electrolyte [1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6)]. We found that electron field effect mobility microFE can be increased from 3 cm2 V-1 s-11 in SiO2 back gated device to 18 cm2 V-1 s-11 in top gated electrolyte devices. Similarly, subthreshold swing can be improved from 30 V/dec to 0.2 V/dec and on/off ratio can be increased from 102 to 103 by using an electrolyte as a top gate. These FETs were also tested as phototransistors. Our photo-response characterization indicate photo-responsivity 32 A/W with external quantum efficiency exceeding 103 % when excited with a 658 nm wavelength laser at room temperature. Our phototransistor also exhibit response times tens of micros with specific detectivity (D*) values reaching 1012 Jones. The CuIn7Se11 phototransistor properties can be further tuned & enhanced by applying a back gate voltage along with increased source drain bias. For example, photo-responsivity can gain substantial improvement up to 320 A/W upon application of a gate voltage (Vg = 30 V) and/or increased source-drain bias. The photo-responsivity exhibited by these photo detectors are at least an order of magnitude better than commercially available conventional Si based photo detectors coupled with response times that are orders of magnitude better than several other family of layered materials investigated so far. Further photocurrent generation mechanisms, effect of traps is discussed in detail.

Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

2017-01-01

Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

Method for disclosing invisible physical properties in metal-ferroelectric-insulator-semiconductor gate stacks

NASA Astrophysics Data System (ADS)

Sakai, Shigeki; Zhang, Wei; Takahashi, Mitsue

2017-04-01

In metal-ferroelectric-insulator-semiconductor gate stacks of ferroelectric-gate field effect transistors (FeFETs), it is impossible to directly obtain curves of polarization versus electric field (P f-E f) in the ferroelectric layer. The P f-E f behavior is not simple, i.e. the P f-E f curves are hysteretic and nonlinear, and the hysteresis curve width depends on the electric field scan amplitude. Unless the P f-E f relation is known, the field E f strength cannot be solved when the voltage is applied between the gate meal and the semiconductor substrate, and thus P f-E f cannot be obtained after all. In this paper, the method for disclosing the relationships among the polarization peak-to-peak amplitude (2P mm_av), the electric field peak-to-peak amplitude (2E mm_av), and the memory window (E w) in units of the electric field is presented. To get P mm_av versus E mm_av, FeFETs with different ferroelectric-layer thicknesses should be prepared. Knowing such essential physical parameters is helpful and in many cases enough to quantitatively understand the behavior of FeFETs. The method is applied to three groups. The first one consists of SrBi2Ta2O9-based FeFETs. The second and third ones consist of Ca x Sr1-x Bi2Ta2O9-based FeFETs made by two kinds of annealing. The method can clearly differentiate the characters of the three groups. By applying the method, ferroelectric relationships among P mm_av, E mm_av, and E w are well classified in the three groups according to the difference of the material kinds and the annealing conditions. The method also evaluates equivalent oxide thickness (EOT) of a dual layer of a deposited high-k insulator and a thermally-grown SiO2-like interfacial layer (IL). The IL thickness calculated by the method is consistent with cross-sectional image of the FeFETs observed by a transmission electron microscope. The method successfully discloses individual characteristics of the ferroelectric and the insulator layers hidden in the gate stack of a FeFET.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Nonequilibrium Green's function theory of resonant steady state photoconduction in a double quantum well FET subject to THz radiation at plasmon frequency

NASA Astrophysics Data System (ADS)

Morgenstern Horing, Norman J.; Popov, Vyacheslav V.

2006-04-01

Recent experimental observations by X.G. Peralta and S.J. Allen, et al. of dc photoconductivity resonances in steady source-drain current subject to terahertz radiation in a grid-gated double-quantum well FET suggested an association with plasmon resonances. This association was definitively confirmed for some parameter ranges in our detailed electrodynamic absorbance calculations. In this paper we propose that the reason that the dc photoconductance resonances match the plasmon resonances in semiconductors is based on a nonlinear dynamic screening mechanism. In this, we employ a shielded potential approximation that is nonlinear in the terahertz field to determine the nonequilibrium Green's function and associated density perturbation that govern the nonequilibrium dielectric polarization of the medium. This ''conditioning'' of the system by the incident THz radiation results in resonant polarization response at the plasmon frequencies which, in turn, causes a sharp drop of the resistive shielded impurity scattering potentials and attendant increase of the dc source-drain current. This amounts to disabling the impurity scattering mechanism by plasmon resonant behavior in nonlinear screening.

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

NASA Astrophysics Data System (ADS)

Lizzit, D.; Badami, O.; Specogna, R.; Esseni, D.

2017-06-01

We present a new model for surface roughness (SR) scattering in n-type multi-gate FETs (MuGFETs) and gate-all-around nanowire FETs with fairly arbitrary cross-sections, its implementation in a complete device simulator, and the validation against experimental electron mobility data. The model describes the SR scattering matrix elements as non-linear transformations of interface fluctuations, which strongly influences the root mean square value of the roughness required to reproduce experimental mobility data. Mobility simulations are performed via the deterministic solution of the Boltzmann transport equation for a 1D-electron gas and including the most relevant scattering mechanisms for electronic transport, such as acoustic, polar, and non-polar optical phonon scattering, Coulomb scattering, and SR scattering. Simulation results show the importance of accounting for arbitrary cross-sections and biasing conditions when compared to experimental data. We also discuss how mobility is affected by the shape of the cross-section as well as by its area in gate-all-around and tri-gate MuGFETs.

Characterizing Radio Emission From Extensive Air Showers with the SLAC-T510 Experiment, with Applications to ANITA

NASA Astrophysics Data System (ADS)

McGuire, Felicia Ann

Essential to metal-oxide-semiconductor field-effect transistor (MOSFET) scaling is the reduction of the supply voltage to mitigate the power consumption and corresponding heat dissipation. Conventional dielectric materials are subject to the thermal limit imposed by the Boltzmann factor in the subthreshold swing, which places an absolute minimum on the supply voltage required to modulate the current. Furthermore, as technology approaches the 5 nm node, electrostatic control of a silicon channel becomes exceedingly difficult, regardless of the gating technique. This notion of "the end of silicon scaling" has rapidly increased research into more scalable channel materials as well as new methods of transistor operation. Among the many promising options are two-dimensional (2D) FETs and negative capacitance (NC) FETs. 2D-FETs make use of atomically thin semiconducting channels that have enabled demonstrated scalability beyond what silicon can offer. NC-FETs demonstrate an effective negative capacitance arising from the integration of a ferroelectric into the transistor gate stack, allowing sub-60 mV/dec switching. While both of these devices provide significant advantages, neither can accomplish the ultimate goal of a FET that is both low-voltage and scalable. However, an appropriate fusion of the 2D-FET and NC-FET into a 2D NC-FET has the potential of enabling a steep-switching device that is dimensionally scalable beyond the 5 nm technology node. In this work, the motivation for and operation of 2D NC-FETs is presented. Experimental realization of 2D NC-FETs using 2D transition metal dichalcogenide molybdenum disulfide (MoS2) as the channel is shown with two different ferroelectric materials: 1) a solution-processed, polymeric poly(vinylidene difluoride trifluoroethylene) ferroelectric and 2) an atomic layer deposition (ALD) grown hafnium zirconium oxide (HfZrO2) ferroelectric. Each ferroelectric was integrated into the gate stack of a 2D-FET having either a top-gate (polymeric ferroelectric) or bottom-gate (HfZrO2 ferroelectric) configuration. HfZrO 2 devices with metallic interfacial layers (between ferroelectric and dielectric) and thinner ferroelectric layers were found to reduce both the hysteresis and the threshold voltage. Detailed characterization of the devices was performed and, most significantly, the 2D NC-FETs with HfZrO2 reproducibly yielded subthreshold swings well below the thermal limit with over more than four orders of magnitude in drain current modulation. HfZrO 2 devices without metallic interfacial layers were utilized to explore the impact of ferroelectric thickness, dielectric thickness, and dielectric composition on device performance. The impact of an interfacial metallic layer on the device operation was investigated in devices with HfZrO2 and shown to be crucial at enabling sub-60 mV/dec switching and large internal voltage gains. The significance of dielectric material choice on device performance was explored and found to be a critical factor in 2D NC-FET transistor operation. These successful results pave the way for future integration of this new device structure into existing technology markets.

Origin of noise in liquid-gated Si nanowire troponin biosensors.

PubMed

Kutovyi, Y; Zadorozhnyi, I; Hlukhova, H; Handziuk, V; Petrychuk, M; Ivanchuk, Andriy; Vitusevich, S

2018-04-27

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

Origin of noise in liquid-gated Si nanowire troponin biosensors

NASA Astrophysics Data System (ADS)

Kutovyi, Y.; Zadorozhnyi, I.; Hlukhova, H.; Handziuk, V.; Petrychuk, M.; Ivanchuk, Andriy; Vitusevich, S.

2018-04-01

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

A scanning probe mounted on a field-effect transistor: Characterization of ion damage in Si.

PubMed

Shin, Kumjae; Lee, Hoontaek; Sung, Min; Lee, Sang Hoon; Shin, Hyunjung; Moon, Wonkyu

2017-10-01

We have examined the capabilities of a Tip-On-Gate of Field-Effect Transistor (ToGoFET) probe for characterization of FIB-induced damage in Si surface. A ToGoFET probe is the SPM probe which the Field Effect Transistor(FET) is embedded at the end of a cantilever and a Pt tip was mounted at the gate of FET. The ToGoFET probe can detect the surface electrical properties by measuring source-drain current directly modulated by the charge on the tip. In this study, a Si specimen whose surface was processed with Ga+ ion beam was prepared. Irradiation and implantation with Ga+ ions induce highly localized modifications to the contact potential. The FET embedded on ToGoFET probe detected the surface electric field profile generated by schottky contact between the Pt tip and the sample surface. Experimentally, it was shown that significant differences of electric field due to the contact potential barrier in differently processed specimens were observed using ToGOFET probe. This result shows the potential that the local contact potential difference can be measured by simple working principle with high sensitivity. Copyright © 2017 Elsevier Ltd. All rights reserved.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Complementary Paired G4FETs as Voltage-Controlled NDR Device

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Chen, Suheng; Blalock, Ben; Britton, Chuck; Prothro, Ben; Vandersand, James; Schrimph, Ron; Cristoloveanu, Sorin; Akavardar, Kerem; Gentil, P.

2009-01-01

It is possible to synthesize a voltage-controlled negative-differential-resistance (NDR) device or circuit by use of a pair of complementary G4FETs (four-gate field-effect transistors). [For more information about G4FETs, please see the immediately preceding article]. As shown in Figure 1, the present voltage-controlled NDR device or circuit is an updated version of a prior NDR device or circuit, known as a lambda diode, that contains a pair of complementary junction field-effect transistors (JFETs). (The lambda diode is so named because its current-versus- voltage plot bears some resemblance to an upper-case lambda.) The present version can be derived from the prior version by substituting G4FETs for the JFETs and connecting both JFET gates of each G4FET together. The front gate terminals of the G4FETs constitute additional terminals (that is, terminals not available in the older JFET version) to which one can apply control voltages VN and VP. Circuits in which NDR devices have been used include (1) Schmitt triggers and (2) oscillators containing inductance/ capacitance (LC) resonant circuits. Figure 2 depicts such circuits containing G4FET NDR devices like that of Figure 1. In the Schmitt trigger shown here, the G4FET NDR is loaded with an ordinary inversion-mode, p-channel, metal oxide/semiconductor field-effect transistor (inversion-mode PMOSFET), the VN terminal of the G4FET NDR device is used as an input terminal, and the input terminals of the PMOSFET and the G4FET NDR device are connected. VP can be used as an extra control voltage (that is, a control voltage not available in a typical prior Schmitt trigger) for adjusting the pinch-off voltage of the p-channel G4FET and thereby adjusting the trigger-voltage window. In the oscillator, a G4FET NDR device is loaded with a conventional LC tank circuit. As in other LC NDR oscillators, oscillation occurs because the NDR counteracts the resistance in the tank circuit. The advantage of this G4FET-NDR LC oscillator over a conventional LC NDR oscillator is that one can apply a time-varying signal to one of the extra control input terminals (VN or VP) to modulate the conductance of the NDR device and thereby amplitude-modulate the output signal.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Development of paper-gate transistor toward direct detection from microbiological fluids

NASA Astrophysics Data System (ADS)

Kajisa, Taira; Sakata, Toshiya

2017-04-01

In this study, a paper-gate transistor was developed to detect glucose using an extended-gate field-effect transistor (FET). A filter paper was used as an extended gate electrode, in which Au nanoparticles (AuNPs) modified with phenylboronic acids (PBAs) were included. PBA-AuNPs play an important role as a support to not only be entrapped in cellulose fibrils but also bind to the targeted glucose in a paper. The surface properties of PBA-AuNPs were investigated to elucidate the electrical properties of the paper-gate electrode using an absorption spectrum and a zeta potential analysis. Moreover, the paper-gate electrode enabled us to detect glucose at the micromolar level on the basis of the principle of FET devices. A platform based on the paper-gate transistor is suitable for a highly sensitive system to detect glucose in trace samples such as tears, sweat, and saliva in the future.

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

NASA Astrophysics Data System (ADS)

Dash, S.; Mishra, G. P.

2015-09-01

A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-TFET) based on the solution of Laplace’s equation is proposed. The band-to-band tunneling (BTBT) current is derived by the help of lateral electric field and the shortest tunneling distance. However, the analysis is extended to obtain the subthreshold swing (SS) and transfer characteristics of the device. The dependency of drain current, SS and transconductance on gate voltage and shortest tunneling distance is discussed. Also, the effect of scaling the gate oxide thickness and the cylindrical body diameter on the electrical parameters of the device is analyzed.

A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism

NASA Astrophysics Data System (ADS)

Nigam, Kaushal; Kondekar, Pravin; Sharma, Dheeraj; Raad, Bhagwan Ram

2016-10-01

For the first time, a distinctive approach based on electrically doped concept is used for the formation of novel double gate tunnel field effect transistor (TFET). For this, the initially heavily doped n+ substrate is converted into n+-i-n+-i (Drain-Channel-Source) by the selection of appropriate work functions of control gate (CG) and polarity gate (PG) as 4.7 eV. Further, the formation of p+ region for source is performed by applying -1.2 V at PG. Hence, the structure behave like a n+-i-n+-p+ gated TFET, whereas, the control gate is used to modulate the effective tunneling barrier width. The physical realization of delta doped n+ layer near to source region is a challenging task for improving the device performance in terms of ON current and subthreshold slope. So, the proposed work will provide a better platform for fabrication of n+-i-n+-p+ TFET with low cost and suppressed random dopant fluctuation (RDF) effects. ATLAS TCAD device simulator is used to carry out the simulation work.

Rhenium Disulfide Depletion-Load Inverter

NASA Astrophysics Data System (ADS)

McClellan, Connor; Corbet, Chris; Rai, Amritesh; Movva, Hema C. P.; Tutuc, Emanuel; Banerjee, Sanjay K.

2015-03-01

Many semiconducting Transition Metal Dichalcogenide (TMD) materials have been effectively used to create Field-Effect Transistor (FET) devices but have yet to be used in logic designs. We constructed a depletion-load voltage inverter using ultrathin layers of Rhenium Disulfide (ReS2) as the semiconducting channel. This ReS2 inverter was fabricated on a single micromechanically-exfoliated flake of ReS2. Electron beam lithography and physical vapor deposition were used to construct Cr/Au electrical contacts, an Alumina top-gate dielectric, and metal top-gate electrodes. By using both low (Aluminum) and high (Palladium) work-function metals as two separate top-gates on a single ReS2 flake, we create a dual-gated depletion mode (D-mode) and enhancement mode (E-mode) FETs in series. Both FETs displayed current saturation in the output characteristics as a result of the FET ``pinch-off'' mechanism and On/Off current ratios of 105. Field-effect mobilities of 23 and 17 cm2V-1s-1 and subthreshold swings of 97 and 551 mV/decade were calculated for the E-mode and D-mode FETs, respectively. With a supply voltage of 1V, at low/negative input voltages the inverter output was at a high logic state of 900 mV. Conversely with high/positive input voltages, the inverter output was at a low logic state of 500 mV. The inversion of the input signal demonstrates the potential for using ReS2 in future integrated circuit designs and the versatility of depletion-load logic devices for TMD research. NRI SWAN Center and ARL STTR Program.

Dual-Input AND Gate From Single-Channel Thin-Film FET

NASA Technical Reports Server (NTRS)

Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.

2008-01-01

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

NASA Astrophysics Data System (ADS)

Garg, Shelly; Saurabh, Sneh

2018-01-01

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration.

Monolithic GaAs Dual-Gate FET Phase Shifter.

DTIC Science & Technology

1981-01-01

r ADAO 6 8 CA LABS PRINCETON NJ F/6 9/5 MNOLC4ITHIC SAAS DUAL-GATE FET PHASE SHIFTER.(U) UNC AN 81 M KUMAR, R HENNA, S N SUBBARAO NOOOI’-79-C-0568...PHASNT NUMBERls) M./Kumar S. N./ Subbarao G. T./Taylor -N 4 C 8 R./Menna H./Huang . 9. PERFORMING ORGANIZATION NAME AND ADDRESS 10. PROGRAM ELEMENT...PROGRESS ........................................................... 1 A. Development of Discrete 3600 Phase Shifter ....................... 2 B . Development

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Carrier mobility and scattering lifetime in electric double-layer gated few-layer graphene

NASA Astrophysics Data System (ADS)

Piatti, E.; Galasso, S.; Tortello, M.; Nair, J. R.; Gerbaldi, C.; Bruna, M.; Borini, S.; Daghero, D.; Gonnelli, R. S.

2017-02-01

We fabricate electric double-layer field-effect transistor (EDL-FET) devices on mechanically exfoliated few-layer graphene. We exploit the large capacitance of a polymeric electrolyte to study the transport properties of three, four and five-layer samples under a large induced surface charge density both above and below the glass transition temperature of the polymer. We find that the carrier mobility shows a strong asymmetry between the hole and electron doping regime. We then employ ab initio density functional theory (DFT) calculations to determine the average scattering lifetime from the experimental data. We explain its peculiar dependence on the carrier density in terms of the specific properties of the electrolyte we used in our experiments.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Attofarad resolution capacitance-voltage measurement of nanometer scale field effect transistors utilizing ambient noise.

PubMed

Gokirmak, Ali; Inaltekin, Hazer; Tiwari, Sandip

2009-08-19

A high resolution capacitance-voltage (C-V) characterization technique, enabling direct measurement of electronic properties at the nanoscale in devices such as nanowire field effect transistors (FETs) through the use of random fluctuations, is described. The minimum noise level required for achieving sub-aF (10(-18) F) resolution, the leveraging of stochastic resonance, and the effect of higher levels of noise are illustrated through simulations. The non-linear DeltaC(gate-source/drain)-V(gate) response of FETs is utilized to determine the inversion layer capacitance (C(inv)) and carrier mobility. The technique is demonstrated by extracting the carrier concentration and effective electron mobility in a nanoscale Si FET with C(inv) = 60 aF.

Enhanced performance CCD output amplifier

DOEpatents

Dunham, Mark E.; Morley, David W.

1996-01-01

A low-noise FET amplifier is connected to amplify output charge from a che coupled device (CCD). The FET has its gate connected to the CCD in common source configuration for receiving the output charge signal from the CCD and output an intermediate signal at a drain of the FET. An intermediate amplifier is connected to the drain of the FET for receiving the intermediate signal and outputting a low-noise signal functionally related to the output charge signal from the CCD. The amplifier is preferably connected as a virtual ground to the FET drain. The inherent shunt capacitance of the FET is selected to be at least equal to the sum of the remaining capacitances.

Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM

NASA Astrophysics Data System (ADS)

Zhang, Xiaoxiao; Zhou, Hua; Ge, Zhenhua; Vaid, Alok; Konduparthi, Deepasree; Osorio, Carmen; Ventola, Stefano; Meir, Roi; Shoval, Ori; Kris, Roman; Adan, Ofer; Bar-Zvi, Maayan

2014-04-01

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

NASA Astrophysics Data System (ADS)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Monolithic GaAs dual-gate FET phase shifter

NASA Astrophysics Data System (ADS)

Kumar, M.; Subbarao, S. N.; Menna, R.

1981-09-01

The objective of this program is to develop a monolithic GaAs dual-gate FET phase shifter, operating over the 4- to 8-GHz frequency band and capable of a continuously programmable phase shift from 0 deg through N times 360 deg where N is an integer. The phase shift is to be controllable to within +3 deg. This phase shifter will be capable of delivering an output power up to 0 dBm with an input and output VSWR of less than 1.5:1. Progress 1: The photomask of a 0 to 90 deg monolithic GaAs dual-gate FET phase shifter has been procured, and we are in the process of fabricating the phase shifter. 2: We have designed and fabricated a 50 ohm, 4-line interdigitated coupler. Also, we have designed and fabricated a 25-ohm, 6-line interdigitated coupler. The performance of both couplers agrees quite well with the theoretical results. Technical Problems: there was no major problem during this period.

The ZnO-FET Biosensor for Cardiac Troponin I

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md; Nuzaihan, M. N. M.; Gopinath, Subash C. B.; Ruslinda, A. R.; Hashim, U.

2018-03-01

This paper investigates the influence of substrate-gate coupling on the ZnO-FET biosensor’s sensitivity for detection of cardiac troponin I (cTnI), a ‘gold standard’ biomarker for acute myocardial infarction (AMI). The FET-based device with introduction of substrate-gate coupling on p-type silicon-on-insulator (SOI) substrate is fabricated using conventional lithography processes. An n-type zinc oxide (ZnO) thin film deposited via electron-beam evaporator is used as transducer for bridging the source and drain regions. Surface modifications via functionalization with 3-aminopropyltriethoxysilane (APTES) and glutaraldehyde (GA) as chemical linkers, followed by immobilization of cTnI monoclonal antibody (MAb-cTnI) as bio-receptor on the ZnO thin film allow different concentration of cTnI detection with high selectivity. The device’s sensitivity increases up to 9 %·(g/ml)-1 with the increase of the substrate-gate voltage (VSG) up to -10 V at very low limit of detection (LOD) down to 1.6 fg/ml.

Dependence of Mobility on Density of Gap States in Organics by GAMEaS - Gate Modulated Activation Energy Spectroscopy

NASA Astrophysics Data System (ADS)

So, Woo-Young; Lang, David; Ramirez, Arthur

2008-03-01

We develop a spectroscopic method for determining the density of states (DOS) in the energy gap - GAte Modulated activation Energy Spectroscopy (GAMEaS), We also report the relationship of these gap states to the mobility of organic field-effect-transistors (FETs). We find that the field-effect mobility is parameterized by two factors: (1) the free-carrier mobility and (2) the ratio of the free carrier density to the total carrier density induced by the gate bias. We show that the highest mobility FETs have shallow exponential band tails of localized states with characteristic slope of 1/kT at 300K. Most remarkably, state-of-the-art crystalline FETs fabricated from rubrene, pentacene, and tetracene all have a very high free-carrier mobility, up to 200cm2/Vsec at 300K, with the somewhat lower effective mobilities dominated by localized gap states. This strongly suggests that further improvements in device performance could be possible with enhanced material quality.

Advanced Silicon Technology for Microwave Circuits

DTIC Science & Technology

1994-03-08

MICROX FET I-V BEHAVIOR ................. 80 APPENDIX C MICROX FOR POWER MOS FROM L TO X BAND ................ 100 APPENDIX D MICROX PRESENTATION...High transconductance behavior for a typical grounded source n-channel MICROX FET (no LDD) with an effective gate length of 0.55 um...modeled MAG/MSG behavior for the best performing MICROX FET which was characterized ............. 45 Figure 33. RF performance of a 4 x 50-micron wide

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

In situ monitoring of myenteric neuron activity using acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors.

PubMed

Müntze, Gesche Mareike; Pouokam, Ervice; Steidle, Julia; Schäfer, Wladimir; Sasse, Alexander; Röth, Kai; Diener, Martin; Eickhoff, Martin

2016-03-15

The response characteristics of acetylcholinesterase-modified AlGaN/GaN solution-gate field-effect transistors (AcFETs) are quantitatively analyzed by means of a kinetic model. The characterization shows that the covalent enzyme immobilization process yields reproducible AcFET characteristics with a Michaelis constant KM of (122 ± 4) μM for the immobilized enzyme layer. The increase of KM by a factor of 2.4 during the first four measurement cycles is attributed to partial denaturation of the enzyme. The AcFETs were used to record the release of acetylcholine (ACh) by neuronal tissue cultivated on the gate area upon stimulation by rising the extracellular K(+) concentration. The neuronal tissue constituted of isolated myenteric neurons from four to 12 days old Wistar rats, or sections from the muscularis propria containing the myenteric plexus from adult rats. For both cases the AcFET response was demonstrated to be related to the activity of the immobilized acetylcholinesterase using the reversible acetylcholinesterase blocker donepezil. A concentration response curve of this blocking agent revealed a half maximal inhibitory concentration of 40 nM which is comparable to values measured by complementary in vitro methods. Copyright © 2015 Elsevier B.V. All rights reserved.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Field Effect Transistors Using Atomically Thin Layers of Copper Indium Selenide (CuInSe)

NASA Astrophysics Data System (ADS)

Patil, Prasanna; Ghosh, Sujoy; Wasala, Milinda; Lei, Sidong; Vajtai, Robert; Ajayan, Pulickel; Talapatra, Saikat

We will report fabrication of field-effect transistors (FETs) using few-layers of Copper Indium Selenide (CuInSe) flakes exfoliated from crystals grown using chemical vapor transport technique. Our transport measurements indicate n-type FET with electron mobility µ ~ 3 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. Mobility can be further increased significantly when ionic liquid 1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6) is used as top gate. Similarly subthreshold swing can be further improved from 103 V/dec to 0.55 V/dec by using ionic liquid as a top gate. We also found ON/OFF ratio of ~ 102 for both top and back gate. Comparison between ionic liquid top gate and SiO2 back gate will be presented and discussed. This work is supported by the U.S. Army Research Office through a MURI Grant # W911NF-11-1-0362.

Quantum confinement effects in lithographic sub-5 nm Silicon nanowire fets and integration of si nanograting fet biosensors

NASA Astrophysics Data System (ADS)

Trivedi, Krutarth B.

In recent years, widespread accessibility to reliable nanofabrication techniques such as high resolution electron beam lithography as well as development of innovative techniques such as nanoimprint lithography and chemically grown nano-materials like carbon nanotubes and graphene have spurred a boom in many fields of research involving nanoscale features and devices. The breadth of fields in which nanoscale features represent a new paradigm is staggering. Scaling down device dimensions to nanoscale enables non-classical quantum behavior and allows for interaction with similarly sized natural materials, like proteins and DNA, as never before, affording an unprecedented level of performance and control and fostering a seemingly boundless array of unique applications. Much of the research effort has been directed toward understanding such interactions to leverage the potential of nanoscale devices to enhance electronic and medical technology. In keeping with the spirit of application based research, my graduate research career has spanned the development of nanoimprint techniques and devices for novel applications, demonstration and study of sub-5 nm Si nanowire FETs exhibiting tangible performance enhancement over conventional MOSFETs, and development of an integrated Si nanograting FET based biosensor and related framework. The following dissertation details my work in fabrication of sub-5 nm Si nanowire FETs and characterization of quantum confinement effects in charge transport of FETs with 2D and 1D channel geometry, fabrication and characterization of schottky contact Si nanograting FET sensors, integration of miniaturized Si nanograting FET biosensors into Chip-in-Strip(c) packaging, development of an automated microfluidic sensing system, and investigation of electrochemical considerations in the Si nanograting FET biosensor gate stack followed by development of a novel patent-pending strategy for a lithographically patterned on-chip gate electrode.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Catching the electron in action in real space inside a Ge-Si core-shell nanowire transistor.

PubMed

Jaishi, Meghnath; Pati, Ranjit

2017-09-21

Catching the electron in action in real space inside a semiconductor Ge-Si core-shell nanowire field effect transistor (FET), which has been demonstrated (J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature, 2006, 441, 489) to outperform the state-of-the-art metal oxide semiconductor FET, is central to gaining unfathomable access into the origin of its functionality. Here, using a quantum transport approach that does not make any assumptions on electronic structure, charge, and potential profile of the device, we unravel the most probable tunneling pathway for electrons in a Ge-Si core-shell nanowire FET with orbital level spatial resolution, which demonstrates gate bias induced decoupling of electron transport between the core and the shell region. Our calculation yields excellent transistor characteristics as noticed in the experiment. Upon increasing the gate bias beyond a threshold value, we observe a rapid drop in drain current resulting in a gate bias driven negative differential resistance behavior and switching in the sign of trans-conductance. We attribute this anomalous behavior in drain current to the gate bias induced modification of the carrier transport pathway from the Ge core to the Si shell region of the nanowire channel. A new experiment involving a four probe junction is proposed to confirm our prediction on gate bias induced decoupling.

Field Effect Transistor /FET/ circuit for variable gin amplifiers

NASA Technical Reports Server (NTRS)

Spaid, G. H.

1969-01-01

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Graphene-Based Liquid-Gated Field Effect Transistor for Biosensing: Theory and Experiments

PubMed Central

Reiner-Rozman, Ciril; Larisika, Melanie; Nowak, Christoph; Knoll, Wolfgang

2015-01-01

We present an experimental and theoretical characterization for reduced Graphene-Oxide (rGO) based FETs used for biosensing applications. The presented approach shows a complete result analysis and theoretically predictable electrical properties. The formulation was tested for the analysis of the device performance in the liquid gate mode of operation with variation of the ionic strength and pH-values of the electrolytes in contact with the FET. The dependence on the Debye length was confirmed experimentally and theoretically, utilizing the Debye length as a working parameter and thus defining the limits of applicability for the presented rGO-FETs. Furthermore, the FETs were tested for the sensing of biomolecules (bovine serum albumin (BSA) as reference) binding to gate-immobilized anti-BSA antibodies and analyzed using the Langmuir binding theory for the description of the equilibrium surface coverage as a function of the bulk (analyte) concentration. The obtained binding coefficients for BSA are found to be same as in results from literature, hence confirming the applicability of the devices. The FETs used in the experiments were fabricated using wet-chemically synthesized graphene, displaying high electron and hole mobility (μ) and provide the strong sensitivity also for low potential changes (by change of pH, ion concentration, or molecule adsorption). The binding coefficient for BSA-anti-BSA interaction shows a behavior corresponding to the Langmuir adsorption theory with a Limit of Detection (LOD) in the picomolar concentration range. The presented approach shows high reproducibility and sensitivity and a good agreement of the experimental results with the calculated data. PMID:25791463

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

A Mathematical Model of a Simple Amplifier Using a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Sayyah, Rana; Hunt, Mitchell; MacLeod, Todd C.; Ho, Fat D.

2009-01-01

This paper presents a mathematical model characterizing the behavior of a simple amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the amplifier is the basis of many circuit configurations, a mathematical model that describes the behavior of a FeFET-based amplifier will help in the integration of FeFETs into many other circuits.

Electrochemical gating-induced reversible and drastic resistance switching in VO2 nanowires

PubMed Central

Sasaki, Tsubasa; Ueda, Hiroki; Kanki, Teruo; Tanaka, Hidekazu

2015-01-01

Reversible and drastic modulation of the transport properties in vanadium dioxide (VO2) nanowires by electric field-induced hydrogenation at room temperature was demonstrated using the nanogaps separated by humid air in field-effect transistors with planer-type gates (PG-FET). These PG-FETs allowed us to investigate behavior of revealed hydrogen intercalation and diffusion aspects with time and spatial evolutions in nanowires. These results show that air nanogaps can operate as an electrochemical reaction field, even in a gaseous atmosphere, and offer new directions to explore emerging functions for electronic and energy devices in oxides. PMID:26584679

A Survey of Solid-State Microwave Power Devices

DTIC Science & Technology

1977-04-29

from the channel by a thin oxide layer (insulated gate FET or IGFET), it may be a diffused junction at the top of the channel (junction FET or JFET...greater than 100 GHz. YIG-tuned units are finding increasing use as extremely stable sources, whereas varactor tuning is used where tuning speed is

Modeling a Common-Source Amplifier Using a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Sayyah, Rana; Hunt, Mitchell; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

High efficiency FET microwave detector design

NASA Astrophysics Data System (ADS)

Luglio, Juan; Ishii, Thomas Koryu

1990-12-01

The work is based on an assumption that very little microwave power would be consumed at a negatively biased gate of a microwave FET, yet significant detected signals would be obtained at the drain if the bias is given. By analyzing a Taylor-series expansion of the drain-current equation in the vicinity of a fixed gate-bias voltage, the bias voltage is found to maximize the second derivative of the drain current, the gate-bias voltage characteristic curve for the maximum detected drain current under a given fixed drain-bias voltage. Based on these findings, a high-efficiency microwave detector is designed, fabricated, and tested at 8.6 GHz, and it is shown that the audio power over absorbed microwave power ratio of the detector is 135 percent due to the positive gain.

Gate-Tunable Electron Transport Phenomena in Al-Ge⟨111⟩-Al Nanowire Heterostructures.

PubMed

Brunbauer, Florian M; Bertagnolli, Emmerich; Lugstein, Alois

2015-11-11

Electrostatically tunable negative differential resistance (NDR) is demonstrated in monolithic metal-semiconductor-metal (Al-Ge-Al) nanowire (NW) heterostructures integrated in back-gated field-effect transistors (FETs). Unambiguous signatures of NDR even at room temperature are attributed to intervalley electron transfer. At yet higher electric fields, impact ionization leads to an exponential increase of the current in the ⟨111⟩ oriented Ge NW segments. Modulation of the transfer rates, manifested as a large tunability of the peak-to-valley ratio (PVR) and the onset of impact ionization is achieved by the combined influences of electrostatic gating, geometric confinement, and heterojunction shape on hot electron transfer and by electron-electron scattering rates that can be altered by varying the charge carrier concentration in the NW FETs.

Instrumentation for measurement of aircraft noise and sonic boom

NASA Technical Reports Server (NTRS)

Zuckerwar, A. J. (Inventor)

1975-01-01

A jet aircraft noise and sonic boom measuring device which converts sound pressure into electric current is described. An electric current proportional to the sound pressure level at a condenser microphone is produced and transmitted over a cable, amplified by a zero drive amplifier and recorded on magnetic tape. The converter is comprised of a local oscillator, a dual-gate field-effect transistor (FET) mixer and a voltage regulator/impedance translator. A carrier voltage that is applied to one of the gates of the FET mixer is generated by the local oscillator. The microphone signal is mixed with the carrier to produce an electrical current at the frequency of vibration of the microphone diaphragm by the FET mixer. The voltage of the local oscillator and mixer stages is regulated, the carrier at the output is eliminated, and a low output impedance at the cable terminals is provided by the voltage regulator/impedance translator.

Impact of random discrete dopant in extension induced fluctuation in gate-source/drain underlap FinFET

NASA Astrophysics Data System (ADS)

Wang, Yijiao; Huang, Peng; Xin, Zheng; Zeng, Lang; Liu, Xiaoyan; Du, Gang; Kang, Jinfeng

2014-01-01

In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate-source/drain (G-S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (Vth), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (Ion), and leakage current (Ioff) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and Ion and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

MEMS Gate Structures for Electric Propulsion Applications

DTIC Science & Technology

2006-07-12

distance between gates of dual gate system V = grid voltage Dsheath = sheath thickness Va = anode voltage E = electric field Vemitter = emitter voltage Es...minutes. A hot pressed boron nitride target (4N) in the hexagonal phase (h- BN) was sputtered in a RF magnetron sputtering gun. To promote the nucleation...and nanoFETs. This paper concludes with a discussion on using MEMS gates for dual -grid electron field emission applications. II. Gate Design I I

Investigation of thermal effects on FinFETs in the quasi-ballistic regime

NASA Astrophysics Data System (ADS)

Yin, Longxiang; Shen, Lei; Di, Shaoyan; Du, Gang; Liu, Xiaoyan

2018-04-01

In this work, the thermal effects of FinFETs in the quasi-ballistic regime are investigated using the Monte Carlo method. Bulk Si nFinFETs with the same fin structure and two different gate lengths L g = 20 and 80 nm are investigated and compared to evaluate the thermal effects on the performance of FinFETs in the quasi-ballistic regime. The on current of the 20 nm FinFET with V gs = 0.7 V does not decrease with increasing lattice temperature (T L) at a high V ds. The electrostatic properties in the 20 nm FinFET are more affected by T L than those in the 80 nm FinFET. However, the electron transport in the 20 nm FinFET is less affected by T L than that in the 80 nm FinFET. The electrostatic properties being more sensitive and the electron transport being less sensitive to thermal effects in the quasi-ballistic regime than in the diffusive regime should be considered for effective device modeling and design.

Structured-gate organic field-effect transistors

NASA Astrophysics Data System (ADS)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

PubMed

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Subthreshold characteristics of pentacene field-effect transistors influenced by grain boundaries

NASA Astrophysics Data System (ADS)

Park, Jaehoon; Jeong, Ye-Sul; Park, Kun-Sik; Do, Lee-Mi; Bae, Jin-Hyuk; Sun Choi, Jong; Pearson, Christopher; Petty, Michael

2012-05-01

Grain boundaries in polycrystalline pentacene films significantly affect the electrical characteristics of pentacene field-effect transistors (FETs). Upon reversal of the gate voltage sweep direction, pentacene FETs exhibited hysteretic behaviours in the subthreshold region, which was more pronounced for the FET having smaller pentacene grains. No shift in the flat-band voltage of the metal-insulator-semiconductor capacitor elucidates that the observed hysteresis was mainly caused by the influence of localized trap states existing at pentacene grain boundaries. From the results of continuous on/off switching operation of the pentacene FETs, hole depletion during the off period is found to be limited by pentacene grain boundaries. It is suggested that the polycrystalline nature of a pentacene film plays an important role on the dynamic characteristics of pentacene FETs.

Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Vu, Quoc An; Fan, Sidi; Hyup Lee, Sang; Joo, Min-Kyu; Jong Yu, Woo; Lee, Young Hee

2018-07-01

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2  ×  109 cm‑2 eV‑1, a thousand times smaller than previously reported values.

C-H surface diamond field effect transistors for high temperature (400 °C) and high voltage (500 V) operation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawarada, H., E-mail: kawarada@waseda.jp; Institute of Nano-Science and Nano-Engineering, Waseda University, Shinjuku, Tokyo 169-8555; Kagami Memorial Laboratory for Material Science and Technology, Waseda University, Shinjuku, Tokyo 169-0051

2014-07-07

By forming a highly stable Al{sub 2}O{sub 3} gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (V{sub B}) of the MOSFET without a field plate is 600 V at a gate-drain distance (L{sub GD}) of 7 μm. We fabricated some MOSFETs for which V{sub B}/L{sub GD} > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al{sub 2}O{sub 3} was deposited on the C-Hmore » surface by atomic layer deposition (ALD) at 450 °C using H{sub 2}O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.« less

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

pH measurements of FET-based (bio)chemical sensors using portable measurement system.

PubMed

Voitsekhivska, T; Zorgiebel, F; Suthau, E; Wolter, K-J; Bock, K; Cuniberti, G

2015-01-01

In this study we demonstrate the sensing capabilities of a portable multiplex measurement system for FET-based (bio)chemical sensors with an integrated microfluidic interface. We therefore conducted pH measurements with Silicon Nanoribbon FET-based Sensors using different measurement procedures that are suitable for various applications. We have shown multiplexed measurements in aqueous medium for three different modes that are mutually specialized in fast data acquisition (constant drain current), calibration-less sensing (constant gate voltage) and in providing full information content (sweeping mode). Our system therefore allows surface charge sensing for a wide range of applications and is easily adaptable for multiplexed sensing with novel FET-based (bio)chemical sensors.

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors.

PubMed

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; Kisslinger, Kim; Stach, Eric A; Shahrjerdi, Davood

2017-07-25

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). Here, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increases proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. These findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.

A comparative study of graphene and graphite-based field effect transistor on flexible substrate

NASA Astrophysics Data System (ADS)

Bhatt, Kapil; Rani, Cheenu; Vaid, Monika; Kapoor, Ankit; Kumar, Pramod; Kumar, Sandeep; Shriwastawa, Shilpi; Sharma, Sandeep; Singh, Randhir; Tripathi, C. C.

2018-06-01

In the present era, there has been a great demand of cost-effective, biodegradable, flexible and wearable electronics which may open the gate to many applications like flexible displays, RFID tags, health monitoring devices, etc. Due to the versatile nature of plastic substrates, they have been extensively used in packaging, printing, etc. However, the fabrication of electronic devices requires specially prepared substrates with high quality surfaces, chemical compositions and solutions to the related fabrication issues along with its non-biodegradable nature. Therefore, in this report, a cost-effective, biodegradable cellulose paper as an alternative dielectric substrate material for the fabrication of flexible field effect transistor (FET) is presented. The graphite and liquid phase exfoliated graphene have been used as the material for the realisation of source, drain and channel on cellulose paper substrate for its comparative analysis. The mobility of fabricated FETs was calculated to be 83 cm2/V s (holes) and 33 cm2/V s (electrons) for graphite FET and 100 cm2/V s (holes) and 52 cm2/V s (electrons) for graphene FET, respectively. The output characteristic of the device demonstrates the linear behaviour and a comprehensive increase in conductance as a function of gate voltages. The fabricated FETs may be used for strain sensing, health care monitoring devices, human motion detection, etc.

Submicron FETs Using Molecular Beam Epitaxy.

DTIC Science & Technology

1981-01-01

2rin w2Cgs Req + 2(rw 2Cg2 Req + rin 2Reqgs Podell 9 has found empirically for one-micron gate length FETs that R =1.25 (10) eq gm Using Eq. (10) in...Transmission, Modulation, and Noise (McGraw- Hill, NY, 1959), p. 223. 9. A. Podell , to be published. 10. P. Wolf, "Microwave Properties of Schottky-Barrier

Detection of Avian Influenza Virus from Cloacal Swabs Using a Disposable Well Gate FET Sensor.

PubMed

Park, Sungwook; Choi, Jaebin; Jeun, Minhong; Kim, Yongdeok; Yuk, Seong-Su; Kim, Sang Kyung; Song, Chang-Seon; Lee, Seok; Lee, Kwan Hyi

2017-07-01

Current methods to detect avian influenza viruses (AIV) are time consuming and lo inw sensitivity, necessitating a faster and more sensitive sensor for on-site epidemic detection in poultry farms and urban population centers. This study reports a field effect transistor (FET) based AIV sensor that detects nucleoproteins (NP) within 30 minutes, down to an LOD of 10 3 EID 50 mL -1 from a live animal cloacal swab. Previously reported FET sensors for AIV detection have not targeted NPs, an internal protein shared across multiple strains, due to the difficulty of field-effect sensing in a highly ionic lysis buffer. The AIV sensor overcomes the sensitivity limit with an FET-based platform enhanced with a disposable well gate (DWG) that is readily replaceable after each measurement. In a single procedure, the virus-containing sample is immersed in a lysis buffer mixture to expose NPs to the DWG surface. In comparison with commercial AIV rapid kits, the AIV sensor is proved to be highly sensitive, fast, and compact, proving its potential effectiveness as a portable biosensor. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

PubMed

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Tuning on-off current ratio and field-effect mobility in a MoS(2)-graphene heterostructure via Schottky barrier modulation.

PubMed

Shih, Chih-Jen; Wang, Qing Hua; Son, Youngwoo; Jin, Zhong; Blankschtein, Daniel; Strano, Michael S

2014-06-24

Field-effect transistor (FET) devices composed of a MoS2-graphene heterostructure can combine the advantages of high carrier mobility in graphene with the permanent band gap of MoS2 for digital applications. Herein, we investigate the electron transfer, photoluminescence, and gate-controlled carrier transport in such a heterostructure. We show that the junction is a Schottky barrier, whose height can be artificially controlled by gating or doping graphene. When the applied gate voltage (or the doping level) is zero, the photoexcited electron-hole pairs in monolayer MoS2 can be split by the heterojunction, significantly reducing the photoluminescence. By applying negative gate voltage (or p-doping) in graphene, the interlayer impedance formed between MoS2 and graphene exhibits an 100-fold increase. For the first time, we show that the gate-controlled interlayer Schottky impedance can be utilized to modulate carrier transport in graphene, significantly depleting the hole transport, but preserving the electron transport. Accordingly, we demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics. In the NMOS digital regime, we report a very high room temperature on/off current ratio (ION/IOFF ∼ 36) in comparison to graphene-based FET devices without sacrificing the field-effect electron mobilities in graphene. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered. The device architecture presented here may enable semiconducting behavior in graphene for digital and analogue electronics.

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

NASA Astrophysics Data System (ADS)

Huynh-Bao, Trong; Ryckaert, Julien; Sakhare, Sushil; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet

2016-03-01

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Strain effects in low-dimensional silicon MOS and AlGaN/GaN HEMT devices

NASA Astrophysics Data System (ADS)

Baykan, Mehmet Onur

Strained silicon technology is a well established method to enhance sub-100nm MOSFET performance. With the scalability of process-induced strain, strained silicon channels have been used in every advanced CMOS technology since the 90nm node. At the 22nm node, due to the detrimental short channel effects, non-planar silicon CMOS has emerged as a viable solution to sustain transistor scaling without compromising the device performance. Therefore, it is necessary to conduct a physics based investigation of the effects of mechanical strain in silicon MOS device performance enhancement, as the transverse and longitudinal device dimensions scale down for future technology nodes. While silicon is widely used as the material basis for logic transistors, AlGaN/GaN HEMTs promise a superior device platform over silicon based power MOSFETs for high-frequency and high-power applications. In contrast to the mature Si crystal growth technology, the abundance of defects in the GaN material system creates obstacles for the realization of a reliable AlGaN/GaN HEMT device technology. Due to the high levels of internal mechanical strain present in AlGaN/GaN HEMTs, it is of utmost importance to understand the impact of mechanical stress on AlGaN/GaN trap generation. First, we have investigated the underlying physics of the comparable electron mobility observed in (100) and (110) sidewall silicon double-gate FinFETs, which is different from the observed planar (100) and (110) electron mobility. By conducting a systematic experimental study, it is shown that the undoped body, metal gate induced stress, and volume-inversion effects do not explain the comparable electron mobility. Using a self-consistent double-gate FinFET simulator, we have showed that for (110) FinFETs, an increased population of electrons is obtained for the Delta2 valley due to the heavy nonparabolic confinement mass, leading to a comparable average electron transport effective mass for both orientations. The width dependent strain response of tri-gate p-type FinFETs are experimentally extracted using a 4-point bending jig. It is found that the low-field piezoresistance coefficient of p-type FinFETs can be modeled by using a weighted conductance average of the top and sidewall bulk piezoresistance coefficients. Next, the strain enhancement of p-type ballistic silicon nanowire MOSFETs is studied using sp3d 5s* basis nearest-neighbor tight-binding simulations coupled with a semiclassical top-of-the-barrier transport model. Size and orientation dependent strain enhancement of ballistic hole transport is explained by the strain-induced modification of the 1D nanowire valence band density-of-states. Further insights are provided for future p-type high-performance silicon nanowire logic devices. A physics based investigation is conducted to understand the strain effects on surface roughness limited electron mobility in silicon inversion layers. Based on the evidence from electrical and material characterization, a strain-induced surface morphology change is hypothesized. To model the observed electrical characteristics, we have employed a self-consistent MOSFET mobility simulator coupled with an ad hoc strain-induced roughness modification. The strain induced surface morphology change is found to be consistent among electrical and materials characterization, as well as transport simulations. In order to bridge the gap between the drift-diffusion based models for long-channel devices and the quasi-ballistic models for nanoscale channels, a unified carrier transport model is developed using an updated one-flux theory. Including the high-field and carrier confinement effects, a surface-potential based analytical transmission expression is obtained for the entire MOSFET operation range. With the new channel transmission equation and average carrier drift velocity, a new expression for channel ballisticity is defined. Impact of mechanical strain on carrier transport for both nMOSFETs and pMOSFETs in both linear and saturation regimes is explained using the new channel transmission definitions. To understand the impact of mechanical strain on AlGaN/GaN HEMT trap generation, we have devised an experimental method to obtain the photon flux-normalized relative areal trap density distribution using photoionization spectroscopy technique. The details of the trap extraction method and the experimental setup are given. Using this setup, the trap characteristics are extracted for both ungated transmission line module (TLM) and gated HEMT devices from both Si and SiC substrates. The changes in the device trap characteristics are emphasized before and after electrical stressing. It is found through the step-voltage stressing of the AlGaN/GaN HEMT gate stack that the device degradation is due to the near bandgap trap generation, which are shown to be related to the structural defects in GaN.

Hydrodynamic electronic fluid instability in GaAs MESFETs at terahertz frequencies

NASA Astrophysics Data System (ADS)

Li, Kang; Hao, Yue; Jin, Xiaoqi; Lu, Wu

2018-01-01

III-V compound semiconductor field effect transistors (FETs) are potential candidates as solid state THz emitters and detectors due to plasma wave instability in these devices. Using a 2D hydrodynamic model, here we present the numerical studies of electron fluid instability in a FET structure. The model is implemented in a GaAs MESFET structure with a gate length of 0.2 µm as a testbed by taking into account the non-equilibrium transport and multi-valley non-parabolicity energy bands. The results show that the electronic density instability in the channel can produce stable periodic oscillations at THz frequencies. Along with stable oscillations, negative differential resistance in output characteristics is observed. The THz emission energy density increases monotonically with the drain bias. The emission frequency of electron density oscillations can be tuned by both gate and drain biases. The results suggest that III-V FETs can be a kind of versatile THz devices with good tunability on both radiative power and emission frequency.

Improved performance of graphene transistors by strain engineering.

PubMed

Nguyen, V Hung; Nguyen, Huy-Viet; Dollfus, P

2014-04-25

By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.

Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate

NASA Astrophysics Data System (ADS)

Hori, Yasuko; Kuzuhara, Masaaki; Ando, Yuji; Mizuta, Masashi

2000-04-01

Electric field distribution in the channel of a field effect transistor (FET) with a field-modulating plate (FP) has been theoretically investigated using a two-dimensional ensemble Monte Carlo simulation. This analysis revealed that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric field intensity at the drain side of the gate edge under pinch-off bias conditions. This study also found that a partial overlap of the high-field region under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal-semiconductor FET with FP (FPFET) (LGF˜0.2 μm) exhibited a much lower peak electric field intensity than a conventional metal-semiconductor FET. Based on these numerically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while maintaining reasonable gain performance.

High performance dendrimer functionalized single-walled carbon nanotubes field effect transistor biosensor for protein detection

NASA Astrophysics Data System (ADS)

Rajesh, Sharma, Vikash; Puri, Nitin K.; Mulchandani, Ashok; Kotnala, Ravinder K.

2016-12-01

We report a single-walled carbon nanotube (SWNT) field-effect transistor (FET) functionalized with Polyamidoamine (PAMAM) dendrimer with 128 carboxyl groups as anchors for site specific biomolecular immobilization of protein antibody for C-reactive protein (CRP) detection. The FET device was characterized by scanning electron microscopy and current-gate voltage (I-Vg) characteristic studies. A concentration-dependent decrease in the source-drain current was observed in the regime of clinical significance, with a detection limit of ˜85 pM and a high sensitivity of 20% change in current (ΔI/I) per decade CRP concentration, showing SWNT being locally gated by the binding of CRP to antibody (anti-CRP) on the FET device. The low value of the dissociation constant (Kd = 0.31 ± 0.13 μg ml-1) indicated a high affinity of the device towards CRP analyte arising due to high anti-CRP loading with a better probe orientation on the 3-dimensional PAMAM structure.

A ZnO nanowire-based photo-inverter with pulse-induced fast recovery.

PubMed

Raza, Syed Raza Ali; Lee, Young Tack; Hosseini Shokouh, Seyed Hossein; Ha, Ryong; Choi, Heon-Jin; Im, Seongil

2013-11-21

We demonstrate a fast response photo-inverter comprised of one transparent gated ZnO nanowire field-effect transistor (FET) and one opaque FET respectively as the driver and load. Under ultraviolet (UV) light the transfer curve of the transparent gate FET shifts to the negative side and so does the voltage transfer curve (VTC) of the inverter. After termination of UV exposure the recovery of photo-induced current takes a long time in general. This persistent photoconductivity (PPC) is due to hole trapping on the surface of ZnO NWs. Here, we used a positive voltage short pulse after UV exposure, for the first time resolving the PPC issue in nanowire-based photo-detectors by accumulating electrons at the ZnO/dielectric interface. We found that a pulse duration as small as 200 ns was sufficient to reach a full recovery to the dark state from the UV induced state, realizing a fast UV detector with a voltage output.

2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET

NASA Astrophysics Data System (ADS)

Saha, Priyanka; Banerjee, Pritha; Sarkar, Subir Kumar

2018-06-01

The paper aims to develop two dimensional analytical model of the proposed dual material (DM) Vertical Super Thin Body (VSTB) strained Field Effect Transistor (FET) with focus on its short channel behaviour in nanometer regime. Electrostatic potential across gate/channel and dielectric wall/channel interface is derived by solving 2D Poisson's equation with parabolic approximation method by applying appropriate boundary conditions. Threshold voltage is then calculated by using the criteria of minimum surface potential considering both gate and dielectric wall side potential. Performance analysis of the present structure is demonstrated in terms of potential, electric field, threshold voltage characteristics and subthreshold behaviour by varying various device parameters and applied biases. Effect of application of strain in channel is further explored to establish the superiority of the proposed device in comparison to conventional VSTB FET counterpart. All analytical results are compared with Silvaco ATLAS device simulated data to substantiate the accuracy of our derived model.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

Catalytic activity of enzymes immobilized on AlGaN /GaN solution gate field-effect transistors

NASA Astrophysics Data System (ADS)

Baur, B.; Howgate, J.; von Ribbeck, H.-G.; Gawlina, Y.; Bandalo, V.; Steinhoff, G.; Stutzmann, M.; Eickhoff, M.

2006-10-01

Enzyme-modified field-effect transistors (EnFETs) were prepared by immobilization of penicillinase on AlGaN /GaN solution gate field-effect transistors. The influence of the immobilization process on enzyme functionality was analyzed by comparing covalent immobilization and physisorption. Covalent immobilization by Schiff base formation on GaN surfaces modified with an aminopropyltriethoxysilane monolayer exhibits high reproducibility with respect to the enzyme/substrate affinity. Reductive amination of the Schiff base bonds to secondary amines significantly increases the stability of the enzyme layer. Electronic characterization of the EnFET response to penicillin G indicates that covalent immobilization leads to the formation of an enzyme (sub)monolayer.

Electrical Spin-Injection into Silicon and Spin FET

DTIC Science & Technology

2010-02-18

differential conductance ( NDC ), which saw the limelight with the realization of the Esaki tunneling diode, had been predicted and observed to occur in a...collector current of a tunneling emitter bipolar transistor, i.e., negative differential transconductance NDTC. Gate controlled NDC had been observed in...measurement and simulation results are relevant as well for other NDC geometries such as FET style tunnel transistors since they offer crucial

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Irradiation of MOS-FET devices to provide desired logic functions

NASA Technical Reports Server (NTRS)

Danchenko, V.; Schaefer, D. H.

1972-01-01

Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

NASA Astrophysics Data System (ADS)

Navlakha, Nupur; Kranti, Abhinav

2017-11-01

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ˜1.2 μA μm-1 along with a longer retention time (RT) of ˜1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

One-dimensional array of gold nanoparticles fabricated using biotemplate and its application to fine FET

NASA Astrophysics Data System (ADS)

Ban, Takahiko; Uenuma, Mutsunori; Migita, Shinji; Okamoto, Naofumi; Ishikawa, Yasuaki; Uraoka, Yukiharu; Yamashita, Ichiro; Yamamoto, Shin-ichi

2018-06-01

By synthesizing AuS nanoparticles (NPs) with spherical shell protein (ferritin) and using a V-groove, a one-dimensional array of NPs was formed at the bottom of the V-groove. It has been reported that AuS NPs are converted to Au NPs by UV/ozone treatment. Floating gate memory (FGM) was fabricated by applying this one-dimensional array to V-grooved junctionless (JL) FETs, V-grooved nin-like-type FETs, and pip-like-type FETs, which are fine FETs. In JL-FETs, it is considered that conversion occurred because of good charge storage efficiency, and operation in the opposite direction to normal FGM operation was seen. In the nin-like and pip-like types devices, the same operation as in conventional FGM was shown, and the width of the memory window was about the same size as when one electron entered one NP. The one-dimensional arrangement of the metal NPs used in this study is considered to be applicable to various fields of nanotechnology.

Self-Assembled Films of Dendrimers and Metallophthalocyanines as FET-Based Glucose Biosensors

PubMed Central

Vieira, Nirton C.S.; Figueiredo, Alessandra; de Queiroz, Alvaro A.A.; Zucolotto, Valtencir; Guimarães, Francisco E.G.

2011-01-01

Separative extended gate field effect transistor (SEGFET) type devices have been used as an ion sensor or biosensor as an alternative to traditional ion sensitive field effect transistors (ISFETs) due to their robustness, ease of fabrication, low cost and possibility of FET isolation from the chemical environment. The layer-by-layer technique allows the combination of different materials with suitable properties for enzyme immobilization on simple platforms such as the extended gate of SEGFET devices enabling the fabrication of biosensors. Here, glucose biosensors based on dendrimers and metallophthalocyanines (MPcs) in the form of layer-by-layer (LbL) films, assembled on indium tin oxide (ITO) as separative extended gate material, has been produced. NH3+ groups in the dendrimer allow electrostatic interactions or covalent bonds with the enzyme (glucose oxidase). Relevant parameters such as optimum pH, buffer concentration and presence of serum bovine albumin (BSA) in the immobilization process were analyzed. The relationship between the output voltage and glucose concentration shows that upon detection of a specific analyte, the sub-products of the enzymatic reaction change the pH locally, affecting the output signal of the FET transducer. In addition, dendritic layers offer a nanoporous environment, which may be permeable to H+ ions, improving the sensibility as modified electrodes for glucose biosensing. PMID:22163704

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness

NASA Astrophysics Data System (ADS)

Nagy, Daniel; Aldegunde, Manuel; Elmessary, Muhammad A.; García-Loureiro, Antonio J.; Seoane, Natalia; Kalna, Karol

2018-04-01

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando’s and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height (Δ_RMS ). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando’s model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with <1 1 0> channel orientation are affected more by the IRS than those with the <1 0 0> crystal orientation. Finally, Λ and Δ_RMS are shown to affect the device performance similarly. A change in values by 30% (Λ) or 20% (Δ_RMS ) results in an increase (decrease) of up to 13% in the drive current.

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness.

PubMed

Nagy, Daniel; Aldegunde, Manuel; Elmessary, Muhammad A; García-Loureiro, Antonio J; Seoane, Natalia; Kalna, Karol

2018-04-11

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando's and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height ([Formula: see text]). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando's model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with [Formula: see text] channel orientation are affected more by the IRS than those with the [Formula: see text] crystal orientation. Finally, Λ and [Formula: see text] are shown to affect the device performance similarly. A change in values by 30% (Λ) or [Formula: see text] ([Formula: see text]) results in an increase (decrease) of up to [Formula: see text] in the drive current.

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE PAGES

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; ...

2017-06-21

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Integrated Balanced FETs for Broadband Millimeter Wave Amplifiers.

DTIC Science & Technology

1981-08-01

F. Podell , "A Functional GaAs FET Noise Model," IEEE Trans. ED- 28, 511 (1981). 4. H. Fukui, "Optimal Noise Figure of Microwave GaAs MESFETs," IEEE...Nm = rl Cs2 Req Cgs2 eq rll gs eq) where gmLs rl=r + ms - real part ofZlCgs m d r r req =4kTBgm2 Podell has found empirically for one-micron gate

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

NASA Astrophysics Data System (ADS)

Afzalian, Aryan; Colinge, Jean-Pierre; Flandre, Denis

2011-05-01

A new concept of nanoscale MOSFET, the Gate Modulated Resonant Tunneling Transistor (RT-FET), is presented and modeled using 3D Non-Equilibrium Green's Function simulations enlightening the main physical mechanisms. Owing to the additional tunnel barriers and the related longitudinal confinement present in the device, the density of state is reduced in its off-state, while remaining comparable in its on-state, to that of a MOS transistor without barriers. The RT-FET thus features both a lower RT-limited off-current and a faster increase of the current with V G, i.e. an improved slope characteristic, and hence an improved Ion/ Ioff ratio. Such improvement of the slope can happen in subthreshold regime, and therefore lead to subthreshold slope below the kT/q limit. In addition, faster increase of current and improved slope occur above threshold and lead to high thermionic on-current and significant Ion/ Ioff ratio improvement, even with threshold voltage below 0.2 V and supply voltage V dd of a few hundreds of mV as critically needed for future technology nodes. Finally RT-FETs are intrinsically immune to source-drain tunneling and are therefore promising candidate for extending the roadmap below 10 nm.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs.

PubMed

Pachauri, Vivek; Ingebrandt, Sven

2016-06-30

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. © 2016 The Author(s). Published by Portland Press Limited on behalf of the Biochemical Society.

Biologically sensitive field-effect transistors: from ISFETs to NanoFETs

PubMed Central

Pachauri, Vivek

2016-01-01

Biologically sensitive field-effect transistors (BioFETs) are one of the most abundant classes of electronic sensors for biomolecular detection. Most of the time these sensors are realized as classical ion-sensitive field-effect transistors (ISFETs) having non-metallized gate dielectrics facing an electrolyte solution. In ISFETs, a semiconductor material is used as the active transducer element covered by a gate dielectric layer which is electronically sensitive to the (bio-)chemical changes that occur on its surface. This review will provide a brief overview of the history of ISFET biosensors with general operation concepts and sensing mechanisms. We also discuss silicon nanowire-based ISFETs (SiNW FETs) as the modern nanoscale version of classical ISFETs, as well as strategies to functionalize them with biologically sensitive layers. We include in our discussion other ISFET types based on nanomaterials such as carbon nanotubes, metal oxides and so on. The latest examples of highly sensitive label-free detection of deoxyribonucleic acid (DNA) molecules using SiNW FETs and single-cell recordings for drug screening and other applications of ISFETs will be highlighted. Finally, we suggest new device platforms and newly developed, miniaturized read-out tools with multichannel potentiometric and impedimetric measurement capabilities for future biomedical applications. PMID:27365038

Hybrid Synthetic Receptors on MOSFET Devices for Detection of Prostate Specific Antigen in Human Plasma.

PubMed

Tamboli, Vibha K; Bhalla, Nikhil; Jolly, Pawan; Bowen, Chris R; Taylor, John T; Bowen, Jenna L; Allender, Chris J; Estrela, Pedro

2016-12-06

The study reports the use of extended gate field-effect transistors (FET) for the label-free and sensitive detection of prostate cancer (PCa) biomarkers in human plasma. The approach integrates for the first time hybrid synthetic receptors comprising of highly selective aptamer-lined pockets (apta-MIP) with FETs for sensitive detection of prostate specific antigen (PSA) at clinically relevant concentrations. The hybrid synthetic receptors were constructed by immobilizing an aptamer-PSA complex on gold and subjecting it to 13 cycles of dopamine electropolymerization. The polymerization resulted in the creation of highly selective polymeric cavities that retained the ability to recognize PSA post removal of the protein. The hybrid synthetic receptors were subsequently used in an extended gate FET setup for electrochemical detection of PSA. The sensor was reported to have a limit of detection of 0.1 pg/mL with a linear detection range from 0.1 pg/mL to 1 ng/mL PSA. Detection of 1-10 pg/mL PSA was also achieved in diluted human plasma. The present apta-MIP sensor developed in conjunction with FET devices demonstrates the potential for clinical application of synthetic hybrid receptors for the detection of clinically relevant biomarkers in complex samples.

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

NASA Astrophysics Data System (ADS)

Hsu, Sheng-Chia; Li, Yiming

2014-11-01

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state ( D it). The variability of the off-state current ( I off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D it varying from 5 × 1012 to 5 × 1013 eV-1 cm-2 owing to significant threshold voltage ( V th) fluctuation. The results of this study indicate that if the level of D it is lower than 1 × 1012 eV-1 cm-2, the normalized variability of the on-state current, I off, V th, DIBL, and subthreshold swing is within 5%.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Development and fabrication of low ON resistance high current vertical VMOS power FETs

NASA Technical Reports Server (NTRS)

Kay, S.

1979-01-01

The design of a VMOS Power FET exhibiting low ON resistance, high current as well as high breakdown voltage and fast switching speeds is described. The design which is based on a 1st-order device model, features a novel polysilicon-gate structure and fieldplated groove termination to achieve high packing density and high breakdown voltage, respectively. One test chip, named VNTKI, can block 180 V at an ON resistence of 2.5 ohm. A 150 mil x 200 mil (.19 sq cm) experimental chip has demonstrated a breakdown voltage of 200v, an ON resistance of 0.12 ohm, a switching time of less than 100 ns, and a pulse drain - current of 50 A with 10 V gate drive.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

Cell adhesion monitoring of human induced pluripotent stem cell based on intrinsic molecular charges

NASA Astrophysics Data System (ADS)

Sugimoto, Haruyo; Sakata, Toshiya

2014-01-01

We have shown a simple way for real-time, quantitative, non-invasive, and non-label monitoring of human induced pluripotent stem (iPS) cell adhesion by use of a biologically coupled-gate field effect transistor (bio-FET), which is based on detection of molecular charges at cell membrane. The electrical behavior revealed quantitatively the electrical contacts of integrin-receptor at the cell membrane with RGDS peptide immobilized at the gate sensing surface, because that binding site was based on cationic α chain of integrin. The platform based on the bio-FET would provide substantial information to evaluate cell/material bio-interface and elucidate biding mechanism of adhesion molecules, which could not be interpreted by microscopic observation.

A Single Polyaniline Nanofiber Field Effect Transistor and Its Gas Sensing Mechanisms

PubMed Central

Chen, Dajing; Lei, Sheng; Chen, Yuquan

2011-01-01

A single polyaniline nanofiber field effect transistor (FET) gas sensor fabricated by means of electrospinning was investigated to understand its sensing mechanisms and optimize its performance. We studied the morphology, field effect characteristics and gas sensitivity of conductive nanofibers. The fibers showed Schottky and Ohmic contacts based on different electrode materials. Higher applied gate voltage contributes to an increase in gas sensitivity. The nanofiber transistor showed a 7% reversible resistance change to 1 ppm NH3 with 10 V gate voltage. The FET characteristics of the sensor when exposed to different gas concentrations indicate that adsorption of NH3 molecules reduces the carrier mobility in the polyaniline nanofiber. As such, nanofiber-based sensors could be promising for environmental and industrial applications. PMID:22163969

Terahertz radiation mixer

DOEpatents

Wanke, Michael C [Albuquerque, NM; Allen, S James [Santa Barbara, CA; Lee, Mark [Albuquerque, NM

2008-05-20

A terahertz radiation mixer comprises a heterodyned field-effect transistor (FET) having a high electron mobility heterostructure that provides a gatable two-dimensional electron gas in the channel region of the FET. The mixer can operate in either a broadband pinch-off mode or a narrowband resonant plasmon mode by changing a grating gate bias of the FET. The mixer can beat an RF signal frequency against a local oscillator frequency to generate an intermediate frequency difference signal in the microwave region. The mixer can have a low local oscillator power requirement and a large intermediate frequency bandwidth. The terahertz radiation mixer is particularly useful for terahertz applications requiring high resolution.

Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

PubMed

Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

2015-12-15

A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements. Copyright © 2015 Elsevier B.V. All rights reserved.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Saptarshi; Roelofs, Andreas; Dubey, Madan

2014-08-25

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for themore » NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.« less

Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications

PubMed Central

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dechen; Tsuboi, Hidetoshi; Kitabayashi, Yuya; Matsumura, Daisuke; Shibata, Masanobu; Kudo, Takuya; Inaba, Masafumi; Hiraiwa, Atsushi

2017-01-01

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al2O3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and VB. PMID:28218234

Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications.

PubMed

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dechen; Tsuboi, Hidetoshi; Kitabayashi, Yuya; Matsumura, Daisuke; Shibata, Masanobu; Kudo, Takuya; Inaba, Masafumi; Hiraiwa, Atsushi

2017-02-20

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al 2 O 3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and V B .

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, Jun-Sik; Rim, Taiuk; Kim, Jungsik; Kim, Kihyun; Baek, Chang-Ki; Jeong, Yoon-Ha

2015-03-01

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Biomolecular Doping of Single-Walled Carbon Nanotubes by Thyroid Hormone

NASA Astrophysics Data System (ADS)

Rojas, Enrique; Paulson, Scott; Stern, Mike; Staii, Cristian; Dratman, Mary; Johnson, Alan

2004-03-01

Electron doping of semiconducting single-walled carbon nanotubes (SWNTs) by the thyroid hormone triiodothyronine (T3) is observed. T3 is applied locally, in solution, to SWNT field effect transistors (FETs) and binds along the length of the nanotube. T3 acts as an electron donor, shifting the I-V gate characteristics towards negative values of gate voltage. Shifts in the characteristics are measured as a function of the concentration of the solution. The effect is nearly reversible by rinsing the FETs with the solvent. Several days after application of T3, with no solvent rinsing, the gate characteristics are also nearly reversed. Experiments with a similar molecule for which the phenol ring is brominated as well as experiments with the de-iodinated molecule (T0) are performed to inform the effect of the iodine. The interaction of T3 with SWNTs may suggest a electronic interaction of T3 with other one-dimensional systems such as DNA.

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Quantifying the effect of ionic screening with protein-decorated graphene transistors

PubMed Central

Ping, Jinglei; Xi, Jin; Saven, Jeffery G.; Liu, Renyu; Charlie Johnson, A. T.

2015-01-01

Liquid-based applications of biomolecule-decorated field-effect transistors (FETs) range from biosensors to in vivo implants. A critical scientific challenge is to develop a quantitative understanding of the gating effect of charged biomolecules in ionic solution and how this influences the readout of the FETs. To address this issue, we fabricated protein-decorated graphene FETs and measured their electrical properties, specifically the shift in Dirac voltage, in solutions of varying ionic strength. We found excellent quantitative agreement with a model that accounts for both the graphene polarization charge and ionic screening of ions adsorbed on the graphene as well as charged amino acids associated with the immobilized protein. The technique and analysis presented here directly couple the charging status of bound biomolecules to readout of liquid-phase FETs fabricated with graphene or other two-dimensional materials. PMID:26626969

Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Boomer, Kristen; Hammoud, Ahmad

2015-01-01

Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Single-Event Effect Report for EPC Series eGaN FETs: Comparison of EPC1000 and EPC2000 Series Devices for Destructive SEE

NASA Technical Reports Server (NTRS)

Scheick, Leif

2014-01-01

Recent testing of the EPC1000 series eGaN FETs has shown sensitivity to Single Event Effects (SEE) that are destructive. These effects are most likely the failure of the very thin gate structure in HEMT architecture. EPC has recently changed the doping of the substrate to improve the performance and the SEE response. This testing compares the SEE response of both devices.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Exceptionally High Electric Double Layer Capacitances of Oligomeric Ionic Liquids.

PubMed

Matsumoto, Michio; Shimizu, Sunao; Sotoike, Rina; Watanabe, Masayoshi; Iwasa, Yoshihiro; Itoh, Yoshimitsu; Aida, Takuzo

2017-11-15

Electric double layer (EDL) capacitors are promising as next-generation energy accumulators if their capacitances and operation voltages are both high. However, only few electrolytes can simultaneously fulfill these two requisites. Here we report that an oligomeric ionic liquid such as IL4 TFSI with four imidazolium ion units in its structure provides a wide electrochemical window of ∼5.0 V, similar to monomeric ionic liquids. Furthermore, electrochemical impedance measurements using Au working electrodes demonstrated that IL4 TFSI exhibits an exceptionally high EDL capacitance of ∼66 μF/cm 2 , which is ∼6 times as high as those of monomeric ionic liquids so far reported. We also found that an EDL-based field effect transistor (FET) using IL4 TFSI as a gate dielectric material and SrTiO 3 as a channel material displays a very sharp transfer curve with an enhanced carrier accumulation capability of ∼64 μF/cm 2 , as determined by Hall-effect measurements.

MCTs and IGBTs - A comparison of performance in power electronic circuits

NASA Technical Reports Server (NTRS)

Sul, S. K.; Profumo, F.; Cho, G. H.; Lipo, T. A.

1989-01-01

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Total Ionizing Dose Effects on Strained Ge pMOS FinFETs on Bulk Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, En Xia; Fleetwood, Daniel M.; Hachtel, Jordan A.

2016-12-02

In this paper, we have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO 2) show minimal transconductance degradation (less than 5%), very small V th shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p MOS FinFETs is far superior to that of past generations of planar Ge pmore » MOS devices. Finally, these improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology.« less

High-performance field-effect transistors based on gadolinium doped indium oxide nanofibers and their application in logic gate

NASA Astrophysics Data System (ADS)

Wang, Chao; Meng, You; Guo, Zidong; Shin, Byoungchul; Liu, Guoxia; Shan, Fukai

2018-05-01

One-dimensional metal oxide nanofibers have been regarded as promising building blocks for large area low cost electronic devices. As one of the representative metal oxide semiconducting materials, In2O3 based materials have attracted much interest due to their excellent electrical and optical properties. However, most of the field-effect transistors (FETs) based on In2O3 nanofibers usually operate in a depletion mode, which lead to large power consumption and a complicated integrated circuit design. In this report, gadolinium (Gd) doped In2O3 (InGdO) nanofibers were fabricated by electrospinning and applied as channels in the FETs. By optimizing the doping concentration and the nanofiber density, the device performance could be precisely manipulated. It was found that the FETs based on InGdO nanofibers, with a Gd doping concentration of 3% and a nanofiber density of 2.9 μm-1, exhibited the best device performance, including a field-effect mobility (μFE) of 2.83 cm2/V s, an on/off current ratio of ˜4 × 108, a threshold voltage (VTH) of 5.8 V, and a subthreshold swing (SS) of 2.4 V/decade. By employing the high-k ZrOx thin films as the gate dielectrics in the FETs, the μFE, VTH and SS can be further improved to be 17.4 cm2/V s, 0.7 V and 160 mV/decade, respectively. Finally, an inverter based on the InGdO nanofibers/ZrOx FETs was constructed and a gain of ˜11 was achieved.

1.8V Operation Power Amplifier IC for Bluetooth Class 1 Utilizing p+-GaAs Gate Hetero-Junction FET

NASA Astrophysics Data System (ADS)

Harima, Fumio; Bito, Yasunori; Takahashi, Hidemasa; Iwata, Naotaka

We have developed a power amplifier IC for Bluetooth Class 1 operating at single low voltage of 1.8V for both control and drain voltages. We can realize it due to fully enhancement-mode hetero-junction FETs utilizing a re-grown p+-GaAs gate technology. The power amplifier is a highly compact design as a small package of 1.5mm×1.5mm×0.4mm with fully integrated gain control and shutdown functions. An impressive power added efficiency of 52% at an output power of 20dBm is achieved with an associated gain of 22dB. Also, sufficiently low leakage current of 0.25μA at 27°C is exhibited, which is comparable to conventional HBT power amplifiers.

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, John D.; Patel, Jagdish; Liu, S. T.; Reed, Robert A.; Mojarradi, Mohammad M.; Blalock, Benjamin J.

2003-06-01

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

NASA Astrophysics Data System (ADS)

Xu, Huifang; Dai, Yuehua

2017-02-01

A two-dimensional analytical model of double-gate (DG) tunneling field-effect transistors (TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results. Project supported by the National Natural Science Foundation of China (No. 61376106), the University Natural Science Research Key Project of Anhui Province (No. KJ2016A169), and the Introduced Talents Project of Anhui Science and Technology University.

Single Schottky junction FETs based on Si:P nanowires with axially graded doping

NASA Astrophysics Data System (ADS)

Barreda, Jorge; Keiper, Timothy; Zhang, Mei; Xiong, Peng

2015-03-01

Si nanowires (NWs) with a systematic axial increase in phosphorus doping have been synthesized via a vapor-liquid-solid method. Silane and phosphine precursor gases are utilized for the growth and doping, respectively. The phosphorous doping profile is controlled by the flow ratio of the precursor gases. After the as-grown product is ultrasonically agitated into a solution, the Si NWs are dispersed on a SiO2 substrate with a highly doped Si back gate. Individual NWs are identified for the fabrication of field-effect transistors (FETs) with multiple Cr/Ag contacts along the NW. Two-probe and four-probe measurements are taken systematically under vacuum conditions at room temperature and the contribution from each contact and each NW section between adjacent contacts is determined. The graded doping level, produced by a systematic reduction in dopant density along the length of the NWs, is manifested in the regular increases in the channel and contact resistances. Our Si NWs facilitate the fabrication of asymmetric FETs with one ohmic and one Schottky contact. A significant increase in gate modulation is obtained due to the single Schottky-barrier contact. Characterization details and the applicability for sensing purposes will be discussed.

Real-time detection of mercury ions in water using a reduced graphene oxide/DNA field-effect transistor with assistance of a passivation layer

DOE PAGES

Chang, Jingbo; Zhou, Guihua; Gao, Xianfeng; ...

2015-08-01

Field-effect transistor (FET) sensors based on reduced graphene oxide (rGO) for detecting chemical species provide a number of distinct advantages, such as ultrasensitivity, label-free, and real-time response. However, without a passivation layer, channel materials directly exposed to an ionic solution could generate multiple signals from ionic conduction through the solution droplet, doping effect, and gating effect. Therefore, a method that provides a passivation layer on the surface of rGO without degrading device performance will significantly improve device sensitivity, in which the conductivity changes solely with the gating effect. In this work, we report rGO FET sensor devices with Hg 2+-dependentmore » DNA as a probe and the use of an Al 2O 3 layer to separate analytes from conducting channel materials. The device shows good electronic stability, excellent lower detection limit (1 nM), and high sensitivity for real-time detection of Hg 2+ in an underwater environment. Our work shows that optimization of an rGO FET structure can provide significant performance enhancement and profound fundamental understanding for the sensor mechanism.« less

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

NASA Astrophysics Data System (ADS)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

Electrical and optical properties of diketopyrrolopyrrole-based copolymer interfaces in thin film devices.

PubMed

Adil, Danish; Kanimozhi, Catherine; Ukah, Ndubuisi; Paudel, Keshab; Patil, Satish; Guha, Suchi

2011-05-01

Two donor-acceptor diketopyrrolopyrrole (DPP)-based copolymers (PDPP-BBT and TDPP-BBT) have been synthesized for their application in organic devices such as metal-insulator semiconductor (MIS) diodes and field-effect transistors (FETs). The semiconductor-dielectric interface was characterized by capacitance-voltage and conductance-voltage methods. These measurements yield an interface trap density of 4.2 × 10(12) eV⁻¹ cm⁻² in TDPP-BBT and 3.5 × 10¹² eV⁻¹ cm⁻² in PDPP-BBT at the flat-band voltage. The FETs based on these spincoated DPP copolymers display p-channel behavior with hole mobilities of the order 10⁻³ cm²/(Vs). Light scattering studies from PDPP-BBT FETs show almost no change in the Raman spectrum after the devices are allowed to operate at a gate voltage, indicating that the FETs suffer minimal damage due to the metal-polymer contact or the application of an electric field. As a comparison Raman intensity profile from the channel-Au contact layer in pentacene FETs are presented, which show a distinct change before and after biasing.

Liquid crystals for organic thin-film transistors

PubMed Central

Iino, Hiroaki; Usui, Takayuki; Hanna, Jun-ichi

2015-01-01

Crystalline thin films of organic semiconductors are a good candidate for field effect transistor (FET) materials in printed electronics. However, there are currently two main problems, which are associated with inhomogeneity and poor thermal durability of these films. Here we report that liquid crystalline materials exhibiting a highly ordered liquid crystal phase of smectic E (SmE) can solve both these problems. We design a SmE liquid crystalline material, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10), for FETs and synthesize it. This material provides uniform and molecularly flat polycrystalline thin films reproducibly when SmE precursor thin films are crystallized, and also exhibits high durability of films up to 200 °C. In addition, the mobility of FETs is dramatically enhanced by about one order of magnitude (over 10 cm2 V−1 s−1) after thermal annealing at 120 °C in bottom-gate-bottom-contact FETs. We anticipate the use of SmE liquid crystals in solution-processed FETs may help overcome upcoming difficulties with novel technologies for printed electronics. PMID:25857435

Liquid crystals for organic thin-film transistors.

PubMed

Iino, Hiroaki; Usui, Takayuki; Hanna, Jun-ichi

2015-04-10

Crystalline thin films of organic semiconductors are a good candidate for field effect transistor (FET) materials in printed electronics. However, there are currently two main problems, which are associated with inhomogeneity and poor thermal durability of these films. Here we report that liquid crystalline materials exhibiting a highly ordered liquid crystal phase of smectic E (SmE) can solve both these problems. We design a SmE liquid crystalline material, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10), for FETs and synthesize it. This material provides uniform and molecularly flat polycrystalline thin films reproducibly when SmE precursor thin films are crystallized, and also exhibits high durability of films up to 200 °C. In addition, the mobility of FETs is dramatically enhanced by about one order of magnitude (over 10 cm(2) V(-1) s(-1)) after thermal annealing at 120 °C in bottom-gate-bottom-contact FETs. We anticipate the use of SmE liquid crystals in solution-processed FETs may help overcome upcoming difficulties with novel technologies for printed electronics.

Liquid crystals for organic thin-film transistors

NASA Astrophysics Data System (ADS)

Iino, Hiroaki; Usui, Takayuki; Hanna, Jun-Ichi

2015-04-01

Crystalline thin films of organic semiconductors are a good candidate for field effect transistor (FET) materials in printed electronics. However, there are currently two main problems, which are associated with inhomogeneity and poor thermal durability of these films. Here we report that liquid crystalline materials exhibiting a highly ordered liquid crystal phase of smectic E (SmE) can solve both these problems. We design a SmE liquid crystalline material, 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10), for FETs and synthesize it. This material provides uniform and molecularly flat polycrystalline thin films reproducibly when SmE precursor thin films are crystallized, and also exhibits high durability of films up to 200 °C. In addition, the mobility of FETs is dramatically enhanced by about one order of magnitude (over 10 cm2 V-1 s-1) after thermal annealing at 120 °C in bottom-gate-bottom-contact FETs. We anticipate the use of SmE liquid crystals in solution-processed FETs may help overcome upcoming difficulties with novel technologies for printed electronics.

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor.

PubMed

Wenga, G; Jacques, E; Salaün, A-C; Rogel, R; Pichon, L; Geneste, F

2013-02-15

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology. Copyright © 2012 Elsevier B.V. All rights reserved.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM

NASA Astrophysics Data System (ADS)

Seo, Youngsoo; Kim, Shinkeun; Ko, Kyul; Woo, Changbeom; Kim, Minsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, electrical characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were analyzed for single transistor and 6T-SRAM cell through 3D technology computer-aided design (TCAD) simulation. In VFET, gate and extension lengths are not limited by the area of device because theses lengths are vertically located. The height of NP is assumed in 40 nm considering device fabrication method (top-down approach). According to the sizes of devices, we analyzed the performances of device such as total resistance, capacitance, intrinsic gate delay, sub-threshold swing (S.S), drain-induced barrier lowering (DIBL) and static noise margin (SNM). As the gate length becomes larger, the resistance should be smaller because the total height of NP is fixed in 40 nm. Also, when the channel thickness becomes thicker, the total resistance becomes smaller since the sheet resistances of channel and extension become smaller and the contact resistance becomes smaller due to the increasing contact area. In addition, as the length of channel pitch increases, the parasitic capacitance comes to be larger due to the increasing area of gate-drain and gate-source. The performance of RC delay is best in the shortest gate length (12 nm), the thickest channel (6 nm) and the shortest channel pitch (17 nm) owing to the reduced resistance and parasitic capacitance. However, the other performances such as DIBL, S.S, on/off ratio and SNM are worst because the short channel effect is highest in this situation. Also, we investigated the performance of the multi-channel device. As the number of channels increases, the performance of device and the reliability of SRAM improve because of reduced contact resistance, increased gate dimension and multi-channel compensation effect.

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Label-free SnO2 nanowire FET biosensor for protein detection

NASA Astrophysics Data System (ADS)

Jakob, Markus H.; Dong, Bo; Gutsch, Sebastian; Chatelle, Claire; Krishnaraja, Abinaya; Weber, Wilfried; Zacharias, Margit

2017-06-01

Novel tin oxide field-effect-transistors (SnO2 NW-FET) for pH and protein detection applicable in the healthcare sector are reported. With a SnO2 NW-FET the proof-of-concept of a bio-sensing device is demonstrated using the carrier transport control of the FET channel by a (bio-) liquid modulated gate. Ultra-thin Al2O3 fabricated by a low temperature atomic layer deposition (ALD) process represents a sensitive layer to H+ ions safeguarding the nanowire at the same time. Successful pH sensitivity is demonstrated for pH ranging from 3 to 10. For protein detection, the SnO2 NW-FET is functionalized with a receptor molecule which specifically interacts with the protein of interest to be detected. The feasibility of this approach is demonstrated via the detection of a biotinylated protein using a NW-FET functionalized with streptavidin. An immediate label-free electronic read-out of the signal is shown. The well-established Enzyme-Linked Immunosorbent Assay (ELISA) method is used to determine the optimal experimental procedure which would enable molecular binding events to occur while being compatible with a final label-free electronic read-out on a NW-FET. Integration of the bottom-up fabricated SnO2 NW-FET pH- and biosensor into a microfluidic system (lab-on-a-chip) allows the automated analysis of small volumes in the 400 μl range as would be desired in portable on-site point-of-care (POC) devices for medical diagnosis.

Signal and Noise in FET-Nanopore Devices.

PubMed

Parkin, William M; Drndić, Marija

2018-02-23

The combination of a nanopore with a local field-effect transistor (FET-nanopore), like a nanoribbon, nanotube, or nanowire, in order to sense single molecules translocating through the pore is promising for DNA sequencing at megahertz bandwidths. Previously, it was experimentally determined that the detection mechanism was due to local potential fluctuations that arise when an analyte enters a nanopore and constricts ion flow through it, rather than the theoretically proposed mechanism of direct charge coupling between the DNA and nanowire. However, there has been little discussion on the experimentally observed detection mechanism and its relation to the operation of real devices. We model the intrinsic signal and noise in such an FET-nanopore device and compare the results to the ionic current signal. The physical dimensions of DNA molecules limit the change in gate voltage on the FET to below 40 mV. We discuss the low-frequency flicker noise (<10 kHz), medium-frequency thermal noise (<100 kHz), and high-frequency capacitive noise (>100 kHz) in FET-nanopore devices. At bandwidths dominated by thermal noise, the signal-to-noise ratio in FET-nanopore devices is lower than in the ionic current signal. At high frequencies, where noise due to parasitic capacitances in the amplifier and chip is the dominant source of noise in ionic current measurements, high-transconductance FET-nanopore devices can outperform ionic current measurements.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

The fundamental downscaling limit of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis, E-mail: mamaluy@sandia.gov; Gao, Xujiao

2015-05-11

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

The fundamental downscaling limit of field effect transistors

DOE PAGES

Mamaluy, Denis; Gao, Xujiao

2015-05-12

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Andrade, M. G. C.; Sahu, P. K.

2016-12-01

The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better immunity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to-gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay.

Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET

NASA Astrophysics Data System (ADS)

Ueda, Daiki; Takeuchi, Kiyoshi; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

A new circuit model that provides a clear guide on designing a MOS-gated thyristor (MGT) is reported. MGT plays a significant role in achieving a steep subthreshold slope of a PN-body tied silicon-on-insulator (SOI) FET (PNBTFET), which is an SOI MOSFET merged with an MGT. The effects of design parameters on MGT and the proposed equivalent circuit model are examined to determine how to regulate the voltage response of MGT and how to suppress power dissipation. It is demonstrated that MGT with low threshold voltages, small hysteresis widths, and small power dissipation can be designed by tuning design parameters. The temperature dependence of MGT is also examined, and it is confirmed that hysteresis width decreases with the average threshold voltage kept nearly constant as temperature rises. The equivalent circuit model can be conveniently used to design low-power PNBTFET.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Biologically templated assembly of hybrid semiconducting nanomesh for high performance field effect transistors and sensors

NASA Astrophysics Data System (ADS)

Byeon, Hye-Hyeon; Lee, Seung-Woo; Lee, Eun-Hee; Kim, Woong; Yi, Hyunjung

2016-10-01

Delicately assembled composites of semiconducting nanomaterials and biological materials provide an attractive interface for emerging applications, such as chemical/biological sensors, wearable health monitoring devices, and therapeutic agent releasing devices. The nanostructure of composites as a channel and a sensing material plays a critical role in the performance of field effect transistors (FETs). Therefore, it is highly desirable to prepare elaborate composite that can allow the fabrication of high performance FETs and also provide high sensitivity and selectivity in detecting specific chemical/biological targets. In this work, we demonstrate that high performance FETs can be fabricated with a hydrodynamically assembled composite, a semiconducting nanomesh, of semiconducting single-walled carbon nanotubes (S-SWNTs) and a genetically engineered M13 phage to show strong binding affinity toward SWNTs. The semiconducting nanomesh enables a high on/off ratio (~104) of FETs. We also show that the threshold voltage and the channel current of the nanomesh FETs are sensitive to the change of the M13 phage surface charge. This biological gate effect of the phage enables the detection of biologically important molecules such as dopamine and bisphenol A using nanomesh-based FETs. Our results provide a new insight for the preparation of composite material platform for highly controllable bio/electronics interfaces.

Non-classical logic inverter coupling a ZnO nanowire-based Schottky barrier transistor and adjacent Schottky diode.

PubMed

Hosseini Shokouh, Seyed Hossein; Raza, Syed Raza Ali; Lee, Hee Sung; Im, Seongil

2014-08-21

On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

Large Area CVD MoS2 RF transistors with GHz performance

NASA Astrophysics Data System (ADS)

Nagavalli Yogeesh, Maruthi; Sanne, Atresh; Park, Saungeun; Akinwade, Deji; Banerjee, Sanjay

Molybdenum disulfide (MoS2) is a 2D semiconductor in the family of transition metal dichalcogenides (TMDs). Its single layer direct bandgap of 1.8 eV allows for high ION/IOFF metal-oxide semiconducting field-effect transistors (FETs). More relevant for radio frequency (RF) wireless applications, theoretical studies predict MoS2 to have saturation velocities, vsat >3×106 cm/s. Facilitated by cm-scale CVD MoS2, here we design and fabricate both top-gated and embedded gate short channel MoS2 RF transistors, and provide a systematic comparison of channel length scaling, extrinsic doping from oxygen-deficient dielectrics, and a gate-first gate-last process flow. The intrinsic fT (fmax) obtained from the embedded gate transistors shows 3X (2X) improvement over top-gated CVD MoS2 RF FETs, and the largest high-field saturation velocity, vsat = 1.88 ×106 cm/s, in MoS2 reported so far. The gate-first approach, offers enhancement mode operation, ION/IOFF ratio of 10, 8< and the highest reported transconductance (gm) of 70 μS/ μm. By manipulating the interfacial oxygen vacancies in atomic layer deposited (ALD) HfO2-x we are able to achieve 2X current density over stoichiometric Al2O3. We demonstrate a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

Optimization of transition-metal dichalcogenides based field-effecttransistors via contact engineering

NASA Astrophysics Data System (ADS)

Perera, Meeghage Madusanka

Layered transition Metal Dichalcogenides (TMDs) have demonstrated a wide range of remarkable properties for applications in next generation nano-electronics. These systems have displayed many "graphene-like" properties including a relatively high carrier mobility, mechanical flexibility, chemical and thermal stability, and moreover offer the significant advantage of a substantial band gap. However, the fabrication of high performance field-effect transistors (FETs) of TMDs is challenging mainly due to the formation of a significant Schottky barrier at metal/TMD interface in most cases. The main goal of this study is to develop novel contact engineering strategies to achieve low-resistance Ohmic contacts. Our first approach is to use Ionic Liquid (IL) gating of metal contacted MoS2 FETs to achieve highly transparent tunneling contacts due to the strong band banding at metal/MoS2 interface. The substantially reduced contact resistance in ionic-liquid-gated bilayer and few-layer MoS 2 FETs results in an ambipolar behavior with high ON/OFF ratios, a near-ideal subthreshold swing, and significantly improved field-effect mobility. Remarkably, the mobility of a 3-nm-thick MoS2 FET with an IL gate was found to increase from ˜ 100 cm2V-1s-1 to ˜ 220 cm2V-1s-1 as the temperature decreased from 180 K to 77 K. This finding is in quantitative agreement with the true channel mobility measured by four-terminal measurement, suggesting that the mobility is predominantly limited by phonon-scattering. To further improve the contacts of TMD devices, graphene was used as work function tunable electrodes. In order to achieve low Schottky barrier height, both IL gating and surface charge transfer doping were used to tune the work function of graphene electrodes close to the conduction band edge of MoS 2. As a result, the performance of our graphene contacted MoS2 FETs is limited by the channel rather than contacts, which is further verified by four-terminal measurements. Finally, degenerately doped TMDs are used as drain/source electrodes to form 2D/2D van der Waals contacts, which are air and thermally stable. WSe2 devices with 2D/2D contacts and 0.01% Nb doped WSe2 channel show a high ON/OFF ratio and high field-effect mobility of 175 cm2 V-1S-1 at room temperature, which increases to 654 cm2V-1S-1 at cryogenic temperatures. As the doping concentration increases, both the ON/OFF ratio and mobility decrease. These contact engineering strategies overcome a major challenge in the development of electronics based on 2D materials beyond graphene.

Time-dependent observation of individual cellular binding events to field-effect transistors.

PubMed

Schäfer, S; Eick, S; Hofmann, B; Dufaux, T; Stockmann, R; Wrobel, G; Offenhäusser, A; Ingebrandt, S

2009-01-01

Electrolyte-gate field-effect transistors (EG-FETs) gained continuously more importance in the field of bioelectronics. The reasons for this are the intrinsic properties of these FETs. Binding of analysts or changes in the electrolyte composition are leading to variations of the drain-source current. Furthermore, due to the signal amplification upon voltage-to-current conversion even small extracellular signals can be detected. Here we report about impedance spectroscopy with an FET array to characterize passive components of a cell attached to the transistor gate. We developed a 16-channel readout system, which provides a simultaneous, lock-in based readout. A test signal of known amplitude and phase was applied via the reference electrode. We monitored the electronic transfer function of the FETs with the attached cell. The resulting frequency spectrum was used to investigate the surface adhesion of individual HEK293 cells. We applied different chemical treatments with either the serinpeptidase trypsin or the ionophor amphotericin B (AmpB). Binding studies can be realized by a time-dependent readout of the lock-in amplifier at a constant frequency. We observed cell detachment upon trypsin activity as well as membrane decomposition induced by AmpB. The results were interpreted in terms of an equivalent electrical circuit model of the complete system. The presented method could in future be applied to monitor more relevant biomedical manipulations of individual cells. Due to the utilization of the silicon technology, our method could be easily up-scaled to many output channels for high throughput pharmacological screening.

Wafer-scale, massively parallel carbon nanotube arrays for realizing field effect transistors with current density exceeding silicon and gallium arsenide

NASA Astrophysics Data System (ADS)

Arnold, Michael

Calculations have indicated that aligned arrays of semiconducting carbon nanotubes (CNTs) promise to outperform conventional semiconducting materials in short-channel, aggressively scaled field effect transistors (FETs) like those used in semiconductor logic and high frequency amplifier technologies. These calculations have been based on extrapolation of measurements of FETs based on one CNT, in which ballistic transport approaching the quantum conductance limit of 2Go = 4e2/h has been achieved. However, constraints in CNT sorting, processing, alignment, and contacts give rise to non-idealities when CNTs are implemented in densely-packed parallel arrays, which has resulted in a conductance per CNT far from 2Go. The consequence has been that it has been very difficult to create high performance CNT array FETs, and CNT array FETs have not outperformed but rather underperformed channel materials such as Si by 6 x or more. Here, we report nearly ballistic CNT array FETs at a density of 50 CNTs um-1, created via CNT sorting, wafer-scale alignment and assembly, and treatment. The on-state conductance in the arrays is as high as 0.46 Go per CNT, and the conductance of the arrays reaches 1.7 mS um-1, which is 7 x higher than previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density reaches 900 uA um-1 and is similar to or exceeds that of Si FETs when compared at equivalent gate oxide thickness, off-state current density, and channel length. The on-state current density exceeds that of GaAs FETs, as well. This leap in CNT FET array performance is a significant advance towards the exploitation of CNTs in high-performance semiconductor electronics technologies.

Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

PubMed

Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

2016-08-23

We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

NASA Astrophysics Data System (ADS)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Unraveling the mechanism of ultraviolet-induced optical gating in Zn1-x Mg x O nanocrystal solid solution field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Park, Byoungnam

2018-03-01

We report ultraviolet (UV)-induced optical gating in a Zn1-x Mg x O nanocrystal solid solution (NCSS) field effect transistor (FET) through a systematic study in which UV-induced charge transport properties are probed as a function of Mg composition. Change in the electrical properties of Zn1-x Mg x O NCSS associated with electronic traps is investigated by field effect-modulated current-voltage characteristic curves in the dark and under illumination. Under UV illumination, significant threshold voltage shift to a more negative value in an n-channel Zn1-x Mg x O NCSS FET is observed. Importantly, as the Mg composition increases, the effect of UV illumination on the threshold voltage shift is alleviated. We found that threshold voltage shift as a function of Mg composition in the dark and under illumination is due to difference in the deep trap density in the Zn1-x Mg x O NCSS. This is supported by Mg composition dependent photoluminescence intensity in the visible range and reduced FET mobility with Mg addition. The presence of the deep traps and the corresponding trap energy levels in the Zn1-x Mg x O NCSS are ensured by photoelectron spectroscopy in air.

Investigating the Mobility of Trilayer Graphene Nanoribbon in Nanoscale FETs

NASA Astrophysics Data System (ADS)

Rahmani, Meisam; Ghafoori Fard, Hassan; Ahmadi, Mohammad Taghi; Rahbarpour, Saeideh; Habibiyan, Hamidreza; Varmazyari, Vali; Rahmani, Komeil

2017-10-01

The aim of the present paper is to investigate the scaling behaviors of charge carrier mobility as one of the most remarkable characteristics for modeling of nanoscale field-effect transistors (FETs). Many research groups in academia and industry are contributing to the model development and experimental identification of multi-layer graphene FET-based devices. The approach in the present work is to provide an analytical model for carrier mobility of tri-layer graphene nanoribbon (TGN) FET. In order to do so, one starts by identifying the analytical modeling of TGN carrier velocity and ballistic conductance. At the end, a model of charge carrier mobility with numerical solution is analytically derived for TGN FET, in which the carrier concentration, temperature and channel length characteristics dependence are highlighted. Moreover, variation of band gap and gate voltage during the proposed device operation and its effect on carrier mobility is investigated. To evaluate the nanoscale FET performance, the carrier mobility model is also adopted to obtain the I-V characteristics of the device. In order to verify the accuracy of the proposed analytical model for TGN mobility, it is compared to the existing experimental data, and a satisfactory agreement is reported for analogous ambient conditions. Moreover, the proposed model is compared with the published data of single-layer graphene and bi-layer graphene, in which the obtained results demonstrate significant insights into the importance of charge carrier mobility impact in high-performance TGN FET. The work presented here is one step towards an applicable model for real-world nanoscale FETs.

Current trends in nanomaterial embedded field effect transistor-based biosensor.

PubMed

Nehra, Anuj; Pal Singh, Krishna

2015-12-15

Recently, as metal-, polymer-, and carbon-based biocompatible nanomaterials have been increasingly incorporated into biosensing applications, with various nanostructures having been used to increase the efficacy and sensitivity of most of the detecting devices, including field effect transistor (FET)-based devices. These nanomaterial-based methods also became the ideal for the amalgamation of biomolecules, especially for the fabrication of ultrasensitive, low-cost, and robust FET-based biosensors; these are categorically very successful at binding the target specified entities in the confined gated micro-region for high functionality. Furthermore, the contemplation of nanomaterial-based FET biosensors to various applications encompasses the desire for detection of many targets with high selectivity, and specificity. We assess how such devices have empowered the achievement of elevated biosensor performance in terms of high sensitivity, selectivity and low detection limits. We review the recent literature here to illustrate the diversity of FET-based biosensors, based on various kinds of nanomaterials in different applications and sum up that graphene or its assisted composite based FET devices are comparatively more efficient and sensitive with highest signal to noise ratio. Lastly, the future prospects and limitations of the field are also discussed. Copyright © 2015 Elsevier B.V. All rights reserved.

Energetic mapping of oxide traps in MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Illarionov, Yury Yu; Knobloch, Theresia; Waltl, Michael; Rzepa, Gerhard; Pospischil, Andreas; Polyushkin, Dmitry K.; Furchi, Marco M.; Mueller, Thomas; Grasser, Tibor

2017-06-01

The performance of MoS2 transistors is strongly affected by charge trapping in oxide traps with very broad distributions of time constants. These defects degrade the mobility and additionally lead to the hysteresis of the gate transfer characteristics, which presents a crucial performance and reliability issue for these new technologies. Here we perform a detailed study of the hysteresis in double-gated MoS2 FETs and show that this issue is nothing else than a combination of threshold voltage shifts resulting from positive and negative bias-temperature instabilities. While these instabilities are well known from silicon devices, they are even more important in 2D devices given the considerably larger defect densities. Most importantly, the magnitudes of these threshold voltage shifts depend strongly on the density and energetic alignment of the active oxide traps. Based on this, we introduce the incremental hysteresis sweep method which allows for an accurate mapping of these defects and extract their energy distributions from simulations. By applying our method to analyze the impact of oxide traps situated in the Al2O3 top gate of several devices, we confirm its versatility. Since all 2D devices investigated so far suffer from a similar hysteresis behavior, the incremental hysteresis sweep method provides a unique and powerful way for the detailed characterization of their defect bands.

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

NASA Astrophysics Data System (ADS)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

NASA Astrophysics Data System (ADS)

Anand, Sunny; Sarin, R. K.

2016-09-01

In this paper for the first time, InAs based doping-less Tunnel FET is proposed and investigated. This paper also demonstrates and discusses the impact of gate stacking (SiO2 + HfO2) with equivalent oxide thickness EOT = 0.8 for analog/RF performance. The charge plasma technique is used to form source/drain region on an intrinsic InAs body by selecting proper work function of metal electrode. The paper compares different combinations of gate stacking (SiO2 and HfO2) on the basis of different analog and RF parameters such as transconductance (gm), transconductance to drive current ratio (gm/ID), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg) and unity-gain cutoff frequency (fT). The proposed device produces an ON state current of ION ∼6 mA along with ION/IOFF ∼1012, point subthreshold slope (SS ∼ 1.9 mV/dec), average subthreshold slope (AV-SS ∼ 14.2 mV/dec) and cut-off frequency in Terahertz. The focus of this work is to eliminate the fabrication issues and providing the enhanced performance compared to doped device.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Tunable and sizable band gap in silicene by surface adsorption

PubMed Central

Quhe, Ruge; Fei, Ruixiang; Liu, Qihang; Zheng, Jiaxin; Li, Hong; Xu, Chengyong; Ni, Zeyuan; Wang, Yangyang; Yu, Dapeng; Gao, Zhengxiang; Lu, Jing

2012-01-01

Opening a sizable band gap without degrading its high carrier mobility is as vital for silicene as for graphene to its application as a high-performance field effect transistor (FET). Our density functional theory calculations predict that a band gap is opened in silicene by single-side adsorption of alkali atom as a result of sublattice or bond symmetry breaking. The band gap size is controllable by changing the adsorption coverage, with an impressive maximum band gap up to 0.50 eV. The ab initio quantum transport simulation of a bottom-gated FET based on a sodium-covered silicene reveals a transport gap, which is consistent with the band gap, and the resulting on/off current ratio is up to 108. Therefore, a way is paved for silicene as the channel of a high-performance FET. PMID:23152944

Self aligned hysteresis free carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Shlafman, M.; Tabachnik, T.; Shtempluk, O.; Razin, A.; Kochetkov, V.; Yaish, Y. E.

2016-04-01

Hysteresis phenomenon in the transfer characteristics of carbon nanotube field effect transistor (CNT FET) is being considered as the main obstacle for successful realization of electronic devices based on CNTs. In this study, we prepare four kinds of CNTFETs and explore their hysteretic behavior. Two kinds of devices comprise on-surface CNTs (type I) and suspended CNTs (type II) with thin insulating layer underneath and a single global gate which modulates the CNT conductance. The third and fourth types (types III and IV) consist of suspended CNT over a metallic local gate underneath, where for type IV the local gate was patterned self aligned with the source and drain electrodes. The first two types of devices, i.e., type I and II, exhibit substantial hysteresis which increases with scanning range and sweeping time. Under high vacuum conditions and moderate electric fields ( |E |>4 ×106 V /cm ), the hysteresis for on-surface devices cannot be eliminated, as opposed to suspended devices. Interestingly, type IV devices exhibit no hysteresis at all at ambient conditions, and from the different roles which the global and local gates play for the four types of devices, we could learn about the hysteresis mechanism of this system. We believe that these self aligned hysteresis free FETs will enable the realization of different electronic devices and sensors based on CNTs.

Gate Tuning of Förster Resonance Energy Transfer in a Graphene - Quantum Dot FET Photo-Detector.

PubMed

Li, Ruifeng; Schneider, Lorenz Maximilian; Heimbrodt, Wolfram; Wu, Huizhen; Koch, Martin; Rahimi-Iman, Arash

2016-06-20

Graphene photo-detectors functionalized by colloidal quantum dots (cQDs) have been demonstrated to show effective photo-detection. Although the transfer of charge carriers or energy from the cQDs to graphene is not sufficiently understood, it is clear that the mechanism and efficiency of the transfer depends on the morphology of the interface between cQDs and graphene, which is determined by the shell of the cQDs in combination with its ligands. Here, we present a study of a graphene field-effect transistor (FET), which is functionalized by long-ligand CdSe/ZnS core/shell cQDs. Time-resolved photo-luminescence from the cQDs as a function of the applied gate voltage has been investigated in order to probe transfer dynamics in this system. Thereby, a clear modification of the photo-luminescence lifetime has been observed, indicating a change of the decay channels. Furthermore, we provide responsivities under a Förster-like energy transfer model as a function of the gate voltage in support of our findings. The model shows that by applying a back-gate voltage to the photo-detector, the absorption can be tuned with respect to the photo-luminescence of the cQDs. This leads to a tunable energy transfer rate across the interface of the photo-detector, which offers an opportunity to optimize the photo-detection.

Structure-Property Relationships of Semiconducting Polymers for Flexible and Durable Polymer Field-Effect Transistors.

PubMed

Kim, Min Je; Jung, A-Ra; Lee, Myeongjae; Kim, Dongjin; Ro, Suhee; Jin, Seon-Mi; Nguyen, Hieu Dinh; Yang, Jeehye; Lee, Kyung-Koo; Lee, Eunji; Kang, Moon Sung; Kim, Hyunjung; Choi, Jong-Ho; Kim, BongSoo; Cho, Jeong Ho

2017-11-22

We report high-performance top-gate bottom-contact flexible polymer field-effect transistors (FETs) fabricated by flow-coating diketopyrrolopyrrole (DPP)-based and naphthalene diimide (NDI)-based polymers (P(DPP2DT-T2), P(DPP2DT-TT), P(DPP2DT-DTT), P(NDI2OD-T2), P(NDI2OD-F2T2), and P(NDI2OD-Se2)) as semiconducting channel materials. All of the polymers displayed good FET characteristics with on/off current ratios exceeding 10 7 . The highest hole mobility of 1.51 cm 2 V -1 s -1 and the highest electron mobility of 0.85 cm 2 V -1 s -1 were obtained from the P(DPP2DT-T2) and P(NDI2OD-Se2) polymer FETs, respectively. The impacts of the polymer structures on the FET performance are well-explained by the interplay between the crystallinity, the tendency of the polymer backbone to adopt an edge-on orientation, and the interconnectivity of polymer fibrils in the film state. Additionally, we demonstrated that all of the flexible polymer-based FETs were highly resistant to tensile stress, with negligible changes in their carrier mobilities and on/off ratios after a bending test. Conclusively, these high-performance, flexible, and durable FETs demonstrate the potential of semiconducting conjugated polymers for use in flexible electronic applications.

Source-drain burnout mechanism of GaAs power MESFETS: Three terminal effects

NASA Astrophysics Data System (ADS)

Takamiya, Saburo; Sonoda, Takuji; Yamanouchi, Masahide; Fujioka, Takashi; Kohno, Masaki

1997-03-01

Theoretical expressions for thermal and electrical feedback effects are derived. These limit the power capability of a power FET and lead a device to catastrophic breakdown (source-drain burnout) when the loop gain of the former reaches unity. Field emission of thermally excited electrons at the Schottky gate plays the key role in thermal feedback, while holes being impact ionized by the drain current play a similar role in the electrical feedback. Thermal feedback is dominant in a high temperature and low drain voltage area. Electrical feedback is dominant in a high drain voltage and low temperature area. In the first area, a high junction temperature is the main factor causing the thermal runaway of the device. In the second area, the electrcal feedback increases the drain current and the temperature and gives a trigger to the thermal feedback so that it reaches unity more easily. Both effects become significant in proportion to transconductance and gate bias resistance, and cause simultaneous runaway of the gate and drain currents. The expressions of the loop gains clearly indicate the safe operating conditions for a power FET. C-band 4 W (1 chip) and 16 W (4 chip) GaAs MESFETs were used as the experimental samples. With these devices the simultaneous runaway of the gate and the drain currents, apparent dependence of the three teminal breakdown voltage on the gate bias resistance in the region dominated by electrical feedback, the rapid increase of the field emitted current at the critical temperature and clear coincidence between the measured and calculated three terminal gate currents both in the thermal feedback dominant region, etc. are demonstrated. The theory explains the experimental results well.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Anisotropic Negative Differential Resistance in Monolayer Black Phosphorus

NASA Astrophysics Data System (ADS)

Zhang, Wanting; Kang, Peng; Chen, Huahui

2018-01-01

The tremendous potential application in emerging two-dimensional layered materials such as black phosphorus (BP) has attracted great attention as nanoscale devices. In this paper, the effect of anisotropic negative differential resistance (NDR) in monolayer black phosphorus field-effect transistors (FETs) is reported by the first-principles computational study based on the non-equilibrium Green’s function approach combined with density functional theory. The transport properties including current-voltage (I-V) relation and transmission spectrum of monolayer BP are investigated at different gate voltages (Vg). Further studies indicate that NDR occurs at a specific gate voltage in the armchair direction rather than in the zigzag direction. The decrease of current in I-V characteristics can be understood from the generation of non-conducting states region moving towards the Fermi level resulting in a reduction of the integration within corresponding energy range in the transmission spectrum. Our results offer useful guidance for designing FETs and other potential applications in nanoelectronic devices based on BP.

P-Channel InGaN/GaN heterostructure metal-oxide-semiconductor field effect transistor based on polarization-induced two-dimensional hole gas

PubMed Central

Zhang, Kexiong; Sumiya, Masatomo; Liao, Meiyong; Koide, Yasuo; Sang, Liwen

2016-01-01

The concept of p-channel InGaN/GaN heterostructure field effect transistor (FET) using a two-dimensional hole gas (2DHG) induced by polarization effect is demonstrated. The existence of 2DHG near the lower interface of InGaN/GaN heterostructure is verified by theoretical simulation and capacitance-voltage profiling. The metal-oxide-semiconductor FET (MOSFET) with Al2O3 gate dielectric shows a drain-source current density of 0.51 mA/mm at the gate voltage of −2 V and drain bias of −15 V, an ON/OFF ratio of two orders of magnitude and effective hole mobility of 10 cm2/Vs at room temperature. The normal operation of MOSFET without freeze-out at 8 K further proves that the p-channel behavior is originated from the polarization-induced 2DHG. PMID:27021054

Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

NASA Astrophysics Data System (ADS)

Zainudin, M. F.; Hussin, H.; Halim, A. K.; Karim, J.

2018-03-01

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.

Suspending effect on low-frequency charge noise in graphene quantum dot.

PubMed

Song, Xiang-Xiang; Li, Hai-Ou; You, Jie; Han, Tian-Yi; Cao, Gang; Tu, Tao; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

2015-01-30

Charge noise is critical in the performance of gate-controlled quantum dots (QDs). Such information is not yet available for QDs made out of the new material graphene, where both substrate and edge states are known to have important effects. Here we show the 1/f noise for a microscopic graphene QD is substantially larger than that for a macroscopic graphene field-effect transistor (FET), increasing linearly with temperature. To understand its origin, we suspended the graphene QD above the substrate. In contrast to large area graphene FETs, we find that a suspended graphene QD has an almost-identical noise level as an unsuspended one. Tracking noise levels around the Coulomb blockade peak as a function of gate voltage yields potential fluctuations of order 1 μeV, almost one order larger than in GaAs/GaAlAs QDs. Edge states and surface impurities rather than substrate-induced disorders, appear to dominate the 1/f noise, thus affecting the coherency of graphene nano-devices.

Suspending Effect on Low-Frequency Charge Noise in Graphene Quantum Dot

PubMed Central

Song, Xiang-Xiang; Li, Hai-Ou; You, Jie; Han, Tian-Yi; Cao, Gang; Tu, Tao; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

2015-01-01

Charge noise is critical in the performance of gate-controlled quantum dots (QDs). Such information is not yet available for QDs made out of the new material graphene, where both substrate and edge states are known to have important effects. Here we show the 1/f noise for a microscopic graphene QD is substantially larger than that for a macroscopic graphene field-effect transistor (FET), increasing linearly with temperature. To understand its origin, we suspended the graphene QD above the substrate. In contrast to large area graphene FETs, we find that a suspended graphene QD has an almost-identical noise level as an unsuspended one. Tracking noise levels around the Coulomb blockade peak as a function of gate voltage yields potential fluctuations of order 1 μeV, almost one order larger than in GaAs/GaAlAs QDs. Edge states and surface impurities rather than substrate-induced disorders, appear to dominate the 1/f noise, thus affecting the coherency of graphene nano-devices. PMID:25634250

Enhanced and continuous electrostatic carrier doping on the SrTiO3 surface

PubMed Central

Eyvazov, A. B.; Inoue, I. H.; Stoliar, P.; Rozenberg, M. J.; Panagopoulos, C.

2013-01-01

Paraelectrical tuning of a charge carrier density as high as 1013 cm−2 in the presence of a high electronic carrier mobility on the delicate surfaces of correlated oxides, is a key to the technological breakthrough of a field effect transistor (FET) utilising the metal-nonmetal transition. Here we introduce the Parylene-C/Ta2O5 hybrid gate insulator and fabricate FET devices on single-crystalline SrTiO3, which has been regarded as a bedrock material for oxide electronics. The gate insulator accumulates up to ~1013cm−2 carriers, while the field-effect mobility is kept at 10 cm2/Vs even at room temperature. Further to the exceptional performance of our devices, the enhanced compatibility of high carrier density and high mobility revealed the mechanism for the long standing puzzle of the distribution of electrostatically doped carriers on the surface of SrTiO3. Namely, the formation and continuous evolution of field domains and current filaments.

Gas Sensors Based on Semiconducting Nanowire Field-Effect Transistors

PubMed Central

Feng, Ping; Shao, Feng; Shi, Yi; Wan, Qing

2014-01-01

One-dimensional semiconductor nanostructures are unique sensing materials for the fabrication of gas sensors. In this article, gas sensors based on semiconducting nanowire field-effect transistors (FETs) are comprehensively reviewed. Individual nanowires or nanowire network films are usually used as the active detecting channels. In these sensors, a third electrode, which serves as the gate, is used to tune the carrier concentration of the nanowires to realize better sensing performance, including sensitivity, selectivity and response time, etc. The FET parameters can be modulated by the presence of the target gases and their change relate closely to the type and concentration of the gas molecules. In addition, extra controls such as metal decoration, local heating and light irradiation can be combined with the gate electrode to tune the nanowire channel and realize more effective gas sensing. With the help of micro-fabrication techniques, these sensors can be integrated into smart systems. Finally, some challenges for the future investigation and application of nanowire field-effect gas sensors are discussed. PMID:25232915

Effect of Polymer Gate Dielectrics on Charge Transport in Carbon Nanotube Network Transistors: Low-k Insulator for Favorable Active Interface.

PubMed

Lee, Seung-Hoon; Xu, Yong; Khim, Dongyoon; Park, Won-Tae; Kim, Dong-Yu; Noh, Yong-Young

2016-11-30

Charge transport in carbon nanotube network transistors strongly depends on the properties of the gate dielectric that is in direct contact with the semiconducting carbon nanotubes. In this work, we investigate the dielectric effects on charge transport in polymer-sorted semiconducting single-walled carbon nanotube field-effect transistors (s-SWNT-FETs) by using three different polymer insulators: A low-permittivity (ε r ) fluoropolymer (CYTOP, ε r = 1.8), poly(methyl methacrylate) (PMMA, ε r = 3.3), and a high-ε r ferroelectric relaxor [P(VDF-TrFE-CTFE), ε r = 14.2]. The s-SWNT-FETs with polymer dielectrics show typical ambipolar charge transport with high ON/OFF ratios (up to ∼10 5 ) and mobilities (hole mobility up to 6.77 cm 2 V -1 s -1 for CYTOP). The s-SWNT-FET with the lowest-k dielectric, CYTOP, exhibits the highest mobility owing to formation of a favorable interface for charge transport, which is confirmed by the lowest activation energies, evaluated by the fluctuation-induced tunneling model (FIT) and the traditional Arrhenius model (E aFIT = 60.2 meV and E aArr = 10 meV). The operational stability of the devices showed a good agreement with the activation energies trend (drain current decay ∼14%, threshold voltage shift ∼0.26 V in p-type regime of CYTOP devices). The poor performance in high-ε r devices is accounted for by a large energetic disorder caused by the randomly oriented dipoles in high-k dielectrics. In conclusion, the low-k dielectric forms a favorable interface with s-SWNTs for efficient charge transport in s-SWNT-FETs.

Intrinsic Electron Mobility Exceeding 10³ cm²/(V s) in Multilayer InSe FETs.

PubMed

Sucharitakul, Sukrit; Goble, Nicholas J; Kumar, U Rajesh; Sankar, Raman; Bogorad, Zachary A; Chou, Fang-Cheng; Chen, Yit-Tsong; Gao, Xuan P A

2015-06-10

Graphene-like two-dimensional (2D) materials not only are interesting for their exotic electronic structure and fundamental electronic transport or optical properties but also hold promises for device miniaturization down to atomic thickness. As one material belonging to this category, InSe, a III-VI semiconductor, not only is a promising candidate for optoelectronic devices but also has potential for ultrathin field effect transistor (FET) with high mobility transport. In this work, various substrates such as PMMA, bare silicon oxide, passivated silicon oxide, and silicon nitride were used to fabricate multilayer InSe FET devices. Through back gating and Hall measurement in four-probe configuration, the device's field effect mobility and intrinsic Hall mobility were extracted at various temperatures to study the material's intrinsic transport behavior and the effect of dielectric substrate. The sample's field effect and Hall mobilities over the range of 20-300 K fall in the range of 0.1-2.0 × 10(3) cm(2)/(V s), which are comparable or better than the state of the art FETs made of widely studied 2D transition metal dichalcogenides.

Coupling p+n Field-Effect Transistor Circuits for Low Concentration Methane Gas Detection

PubMed Central

Zhou, Xinyuan; Yang, Liping; Bian, Yuzhi; Ma, Xiang; Chen, Yunfa

2018-01-01

Nowadays, the detection of low concentration combustible methane gas has attracted great concern. In this paper, a coupling p+n field effect transistor (FET) amplification circuit is designed to detect methane gas. By optimizing the load resistance (RL), the response to methane of the commercial MP-4 sensor can be magnified ~15 times using this coupling circuit. At the same time, it decreases the limit of detection (LOD) from several hundred ppm to ~10 ppm methane, with the apparent response of 7.0 ± 0.2 and voltage signal of 1.1 ± 0.1 V. This is promising for the detection of trace concentrations of methane gas to avoid an accidental explosion because its lower explosion limit (LEL) is ~5%. The mechanism of this coupling circuit is that the n-type FET firstly generates an output voltage (VOUT) amplification process caused by the gate voltage-induced resistance change of the FET. Then, the p-type FET continues to amplify the signal based on the previous VOUT amplification process. PMID:29509659

Coupling p+n Field-Effect Transistor Circuits for Low Concentration Methane Gas Detection.

PubMed

Zhou, Xinyuan; Yang, Liping; Bian, Yuzhi; Ma, Xiang; Han, Ning; Chen, Yunfa

2018-03-06

Nowadays, the detection of low concentration combustible methane gas has attracted great concern. In this paper, a coupling p+n field effect transistor (FET) amplification circuit is designed to detect methane gas. By optimizing the load resistance ( R L ), the response to methane of the commercial MP-4 sensor can be magnified ~15 times using this coupling circuit. At the same time, it decreases the limit of detection (LOD) from several hundred ppm to ~10 ppm methane, with the apparent response of 7.0 ± 0.2 and voltage signal of 1.1 ± 0.1 V. This is promising for the detection of trace concentrations of methane gas to avoid an accidental explosion because its lower explosion limit (LEL) is ~5%. The mechanism of this coupling circuit is that the n-type FET firstly generates an output voltage ( V OUT ) amplification process caused by the gate voltage-induced resistance change of the FET. Then, the p-type FET continues to amplify the signal based on the previous V OUT amplification process.

ESSDERC (European Solid State Device Research Conference) 17th Held in Bologna, Italy on 14-17 September 1987

DTIC Science & Technology

1987-09-17

T. J. Watson Research Center, Yorktown Heights, N.Y. 10598 Processing, design , and characterization issues are discussed for advanced field-effect...Graded-gate FET (GFET) Jan. 1969. designed to overcome these problems, was presented. The differential gate bias allows control [3] D. Misra, T.R...structure, the degree of freedom in zation [7) of the partially restricted active circuit or system design circuit layout, and area is to control the

Research on InGaAs FETs.

DTIC Science & Technology

1981-09-01

is to reduce resistance and to allow wirebonding. Finally, the excess p-region is etched away (Figs. 2f and 2g) using 25 citric acid (50% by weight...found to be parallel to the grains. Gates etched in the citric acid /hydrogen perioxide etch that are oriented parallel to the grains have the cross...occur at IV reverse bias (i.e., negative gate voltage and IDSS is typically z 45 mA. After 60 sec of etch- ing in the citric acid etch (i.e., 25 citric

Creation of reduced graphene oxide based field effect transistors and their utilization in the detection and discrimination of nucleoside triphosphates.

PubMed

Yu, Chunmeng; Chang, Xingmao; Liu, Jing; Ding, Liping; Peng, Junxia; Fang, Yu

2015-05-27

Two low-cost, micropatterned, solution-gated field effect transistors (modified FET and unmodified FET) based on reduced graphene oxide (RGO) were developed and used for detection and discrimination of nucleoside triphosphates (NTPs). The modified FET was realized by simple deposition of a positively charged bis-pyrenyl derivative, py-diIM-py, onto the conducting RGO strips of the unmodified FET. The electrical properties and sensing behaviors of the as-prepared devices were studied comprehensively. Electrical transfer property tests revealed that both of the two FETs exhibit V-shaped ambipolar field effect behavior from p-type region to n-type region. Sensing performance studies demonstrated that modification of the native FET with py-diIM-py improves its sensing ability to NTPs-GTP and ATP in particular. The detection limit of GTP and ATP was as low as 400 nM, which is the lowest value for graphene-based electronic sensors reported so far. Furthermore, based on the cross-reactive responses of the two devices to NTPs, NTPs can be conveniently distinguished via combining use of the two devices. The enhancement of the modifier (py-diIM-py) to the sensing performance of the FET is tentatively attributed to its possible mediation role in sticking onto RGO strips and accumulating analytes by electrostatic association with the relevant species. Because they are sensitive and fast in response, simple and low-cost in preparation, and possibly useful in sensor-array fabrication, the developed sensors show great potential in real-life application.

Black Phosphorus Transistors with Near Band Edge Contact Schottky Barrier.

PubMed

Ling, Zhi-Peng; Sakar, Soumya; Mathew, Sinu; Zhu, Jun-Tao; Gopinadhan, K; Venkatesan, T; Ang, Kah-Wee

2015-12-15

Black phosphorus (BP) is a new class of 2D material which holds promise for next generation transistor applications owing to its intrinsically superior carrier mobility properties. Among other issues, achieving good ohmic contacts with low source-drain parasitic resistance in BP field-effect transistors (FET) remains a challenge. For the first time, we report a new contact technology that employs the use of high work function nickel (Ni) and thermal anneal to produce a metal alloy that effectively reduces the contact Schottky barrier height (ΦB) in a BP FET. When annealed at 300 °C, the Ni electrode was found to react with the underlying BP crystal and resulted in the formation of nickel-phosphide (Ni2P) alloy. This serves to de-pin the metal Fermi level close to the valence band edge and realizes a record low hole ΦB of merely ~12 meV. The ΦB at the valence band has also been shown to be thickness-dependent, wherein increasing BP multi-layers results in a smaller ΦB due to bandgap energy shrinkage. The integration of hafnium-dioxide high-k gate dielectric additionally enables a significantly improved subthreshold swing (SS ~ 200 mV/dec), surpassing previously reported BP FETs with conventional SiO2 gate dielectric (SS > 1 V/dec).

FET-biosensor for cardiac troponin biomarker

NASA Astrophysics Data System (ADS)

Arshad, Mohd Khairuddin Md; Faris Mohamad Fathil, Mohamad; Hashim, Uda

2017-11-01

Acute myocardial infarction or myocardial infarction (MI) is a major health problem, due to diminished flow of blood to the heart, leads to higher rates of mortality and morbidity. The most specific markers for cardiac injury are cardiac troponin I (cTnI) and cardiac troponin T (cTnT) which have been considered as `gold standard'. Due to higher specificity, determination of the level of cardiac troponins became a predominant indicator for MI. Currently, field-effect transistor (FET)-based biosensors have been main interest to be implemented in portable sensors with the ultimate application in point-of-care testing (POCT). In this paper, we review on the FET-based biosensor based on its principle of operation, integration with nanomaterial, surface functionalization as well as immobilization, and the introduction of additional gate (for ambipolar conduction) on the device architecture for the detection of cardiac troponin I (cTnI) biomarker.

FET charge sensor and voltage probe

NASA Technical Reports Server (NTRS)

Robinson, P. A., Jr. (Inventor)

1986-01-01

A MOSFET structure having a biased gate covered with an insulator is described. The insulator is of such a thickness as to render the structure capable of giving a measure of accumulated charge. The structure is also capable of being used in a stacked structure as a particle spectrometer.

Fully Printed High-Frequency Phased-Array Antenna on Flexible Substrate

NASA Technical Reports Server (NTRS)

Chen, Yihong; Lu, Xuejun

2010-01-01

To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

A randomized double-blinded controlled trial of hCG as luteal phase support in natural cycle frozen embryo transfer.

PubMed

Lee, Vivian Chi Yan; Li, Raymond Hang Wun; Yeung, William Shu Biu; Pak Chung, H O; Ng, Ernest Hung Yu

2017-05-01

Does the use of hCG as luteal phase support in natural cycle frozen embryo transfer (FET) increase the ongoing pregnancy rate? The use of hCG in natural cycle FET did not improve the ongoing pregnancy rate. The use of luteal phase support in stimulated cycles has been associated with higher live-birth rates and the results are similar when using hCG or progesterone. This is a randomized double-blinded controlled trial of 450 women recruited between August 2013 and October 2015. Women with regular cycles undergoing natural cycle FET were recruited. Serial serum hormonal concentrations were used to time natural ovulation and at least Day 2 cleavage embryos were replaced. Patients were randomized into either: (i) the treatment group, receiving 1500 IU hCG on the day of FET and 6 days after FET, or (ii) the control group, receiving normal saline on these 2 days. The ongoing pregnancy rate [60/225 (26.7%) in the treatment group vs 70/225 (31.3%) in the control group, odds ratio 1.242 (95% CI 0.825-1.869)], implantation rate and miscarriage rate were comparable between the two groups. In the treatment group, there were significantly more cycles with top quality embryos transferred and a significantly higher serum oestradiol level, but a comparable serum progesterone level, 6 days after FET. However, no significant differences were observed in serum oestradiol and progesterone levels 6 days after FET between the pregnant and non-pregnant women. In the multivariate logistic regression, the number of embryos transferred was the only significant factor predictive of the ongoing pregnancy rate after natural cycle FET. This study only included FET with cleavage stage embryos and only hCG, not vaginal progesterone, was used as luteal phase support. The findings in this study do not support the use of hCG for luteal phase support in natural cycle FET. No external funding was used and there were no competing interests. clinicaltrial.gov identifier: NCT01931384. 23/8/2013. 30/8/2013. © The Author 2017. Published by Oxford University Press on behalf of the European Society of Human Reproduction and Embryology. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Molecular control of pentacene/ZnO photoinduced charge transfer

NASA Astrophysics Data System (ADS)

Spalenka, Josef W.; Paoprasert, Peerasak; Franking, Ryan; Hamers, Robert J.; Gopalan, Padma; Evans, Paul G.

2011-03-01

Photoinduced charge transfer modifies the device properties of illuminated pentacene field effect transistors (FETs) incorporating ZnO quantum dots at the gate insulator/pentacene interface. The transferred charge is trapped on electronic states associated with the ZnO quantum dots, with a steady state population approximately proportional to the rate of organic-inorganic charge transfer. Trapped charge shifts the threshold voltage of the FETs, providing the means to evaluate the rate of organic/inorganic charge transfer and the effects of interface modification. Monolayers of the wide-gap alkane stearic acid and the conjugated oligomer terthiophene attached to the ZnO suppress or permit charge transfer, respectively.

Human dopamine receptor nanovesicles for gate-potential modulators in high-performance field-effect transistor biosensors

NASA Astrophysics Data System (ADS)

Park, Seon Joo; Song, Hyun Seok; Kwon, Oh Seok; Chung, Ji Hyun; Lee, Seung Hwan; An, Ji Hyun; Ahn, Sae Ryun; Lee, Ji Eun; Yoon, Hyeonseok; Park, Tai Hyun; Jang, Jyongsik

2014-03-01

The development of molecular detection that allows rapid responses with high sensitivity and selectivity remains challenging. Herein, we demonstrate the strategy of novel bio-nanotechnology to successfully fabricate high-performance dopamine (DA) biosensor using DA Receptor-containing uniform-particle-shaped Nanovesicles-immobilized Carboxylated poly(3,4-ethylenedioxythiophene) (CPEDOT) NTs (DRNCNs). DA molecules are commonly associated with serious diseases, such as Parkinson's and Alzheimer's diseases. For the first time, nanovesicles containing a human DA receptor D1 (hDRD1) were successfully constructed from HEK-293 cells, stably expressing hDRD1. The nanovesicles containing hDRD1 as gate-potential modulator on the conducting polymer (CP) nanomaterial transistors provided high-performance responses to DA molecule owing to their uniform, monodispersive morphologies and outstanding discrimination ability. Specifically, the DRNCNs were integrated into a liquid-ion gated field-effect transistor (FET) system via immobilization and attachment processes, leading to high sensitivity and excellent selectivity toward DA in liquid state. Unprecedentedly, the minimum detectable level (MDL) from the field-induced DA responses was as low as 10 pM in real- time, which is 10 times more sensitive than that of previously reported CP based-DA biosensors. Moreover, the FET-type DRNCN biosensor had a rapid response time (<1 s) and showed excellent selectivity in human serum.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Silicon, germanium, and III-V-based tunneling devices for low-power applications

NASA Astrophysics Data System (ADS)

Smith, Joshua T.

While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit---the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the most promising low-power device candidate, owing to its potential to operate within small supply and gate voltage windows. In a critical analysis of the TFET, the advantages of 1-D systems, such as NWs, that can potentially access the so-called quantum capacitance limit (QCL) are discussed, and the remaining challenges for TFETs, such as source/channel doping abruptness, and material tradeoffs are considered. To this end, substantial performance improvements, as measured by Savg and ION, are experimentally realized in top-down fabricated Si NW-TFET arrays by systematically varying the annealing process used to enhance doping abruptness at the source/channel junction---a critical feature for maximizing tunneling efficiency. A combination of excimer laser annealing (ELA) and a low-temperature rapid thermal anneal (LT-RTA) are identified as an optimum choice, resulting in a 36% decrease in Savg as well as ˜500% improvement in ION over the conventional RTA approach. Extrapolation of these results with simulation shows that sub-60-mV/decade operation is possible on a Si-based platform for aggressively scaled, yet realistic, NW-TFET devices. Back-gated NW-FET measurements are also presented to assess the material quality of Ge/Si core/shell NW heterostructures with an n+-doped shell, and these NWs are found to be suitable building blocks for the fabrication of more efficient TFET systems, owing to the very abrupt doping profile at the shell/core (source/channel) interface and smaller bandgap/effective mass of the Ge channel. Finally, low current levels in conventional TFETs have recently led researchers to re-examine III-V heterostructures, particularly those with a broken-gap band alignment to allow a tunneling probability near unity. Along these lines, a novel tunnel-based alternative is presented---the broken-gap tunnel MOS---that enables a constant S < 60 mV/decade. The proposed device permits the use of 2-D device architectures without degradation of S given the source-controlled operation mechanism, while simultaneously avoiding undesirable nonlinearities in the output characteristics.

Electrical control of flying spin precession in chiral 1D edge states

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakajima, Takashi; Komiyama, Susumu; Lin, Kuan-Ting

2013-12-04

Electrical control and detection of spin precession are experimentally demonstrated by using spin-resolved edge states in the integer quantum Hall regime. Spin precession is triggered at a corner of a biased metal gate, where electron orbital motion makes a sharp turn leading to a nonadiabatic change in the effective magnetic field via spin-orbit interaction. The phase of precession is controlled by the group velocity of edge-state electrons tuned by gate bias voltage: Spin-FET-like coherent control of spin precession is thus realized by all-electrical means.

GaAs circuits for monolithic optical controller

NASA Technical Reports Server (NTRS)

Gustafson, G.; Bendett, M.; Carney, J.; Mactaggart, R.; Palmquist, S.

1988-01-01

GaAs circuits for use in a fully monolithic 1 Gb/s optical controller have been developed and tested. The circuits include photodetectors, transimpedance amplifiers and 1:16 demultiplexers that can directly control the phase of MMIC phase shifters. The entire chip contains approximately 300 self-aligned gate E/D-mode MESFETs. The MESFETs have one micron-wide gate and the E-mode FETs typically have transconductance of 200 ms/mm. Results of simulations and tests are reported. Also, the design and layout of the fully monolithic chip is discussed.

pH and Protein Sensing with Functionalized Semiconducting Oxide Nanobelt FETs

NASA Astrophysics Data System (ADS)

Cheng, Yi; Yun, C. S.; Strouse, G. F.; Xiong, P.; Yang, R. S.; Wang, Z. L.

2008-03-01

We report solution pH sensing and selective protein detection with high-performance channel-limited field-effect transistors (FETs) based on single semiconducting oxide (ZnO and SnO2) nanobelts^1. The devices were integrated with PDMS microfluidic channels for analyte delivery and the source/drain contacts were passivated for in-solution sensing. pH sensing experiments were performed on FETs with functionalized and unmodified nanobelts. Functionalization of the nanobelts by APTES was found to greatly improve the pH sensitivity. The change in nanobelt conductance as functions of pH values at different gate voltages and ionic strengths showed high sensitivity and consistency. For the protein detection, we achieved highly selective biotinylation of the nanobelt channel with through APTES linkage. The specific binding of fluorescently-tagged streptavidin to the biotinylated nanobelt was verified by fluorescence microscopy; non-specific binding to the substrate was largely eliminated using PEG-silane passivation. The electrical responses of the biotinylated FETs to the streptavidin binding in PBS buffers of different pH values were systematically measured. The results will be presented and discussed. ^1Y. Cheng et al., Appl. Phys. Lett. 89, 093114 (2006). *Supported by NSF NIRT Grant ECS-0210332.

Molybdenum disulfide nanoflake-zinc oxide nanowire hybrid photoinverter.

PubMed

Hosseini Shokouh, Seyed Hossein; Pezeshki, Atiye; Ali Raza, Syed Raza; Choi, Kyunghee; Min, Sung-Wook; Jeon, Pyo Jin; Lee, Hee Sung; Im, Seongil

2014-05-27

We demonstrate a hybrid inverter-type nanodevice composed of a MoS2 nanoflake field-effect transistor (FET) and ZnO nanowire Schottky diode on one substrate, aiming at a one-dimensional (1D)-two-dimensional (2D) hybrid integrated electronic circuit with multifunctional capacities of low power consumption, high gain, and photodetection. In the present work, we used a nanotransfer printing method using polydimethylsiloxane for the fabrication of patterned bottom-gate MoS2 nanoflake FETs, so that they could be placed near the ZnO nanowire Schottky diodes that were initially fabricated. The ZnO nanowire Schottky diode and MoS2 FET worked respectively as load and driver for a logic inverter, which exhibits a high voltage gain of ∼50 at a supply voltage of 5 V and also shows a low power consumption of less than 50 nW. Moreover, our inverter effectively operates as a photoinverter, detecting visible photons, since MoS2 FETs appear very photosensitive, while the serially connected ZnO nanowire Schottky diode was blind to visible light. Our 1D-2D hybrid nanoinverter would be quite promising for both logic and photosensing applications due to its performance and simple device configuration as well.

Highly sensitive protein detection using a plasmonic field effect transistor (Conference Presentation)

NASA Astrophysics Data System (ADS)

Shokri-Kojori, Hossein; Ji, Yiwen; Han, Xu; Paik, Younghun; Braunschweig, Adam; Kim, Sung Jin

2016-03-01

Localized surface Plasmon Resonance (LSPR) is a nanoscale phenomenon which presents strong resonance associated with noble metal nanostructures. This plasmon resonance based technology enables highly sensitive detection for chemical and biological applications. Recently, we have developed a plasmon field effect transistor (FET) that enables direct plasmonic-to-electric signal conversion with signal amplification. The plasmon FET consists of back-gated field effect transistor incorporated with gold nanoparticles on top of the FET channel. The gold nanostructures are physically separated from transistor electrodes and can be functionalized for a specific biological application. In this presentation, we report a successful demonstration of a model system to detect Con A proteins using Carbohydrate linkers as a capture molecule. The plasmon FET detected a very low concentration of Con A (0.006 mg/L) while it offers a wide dynamic range of 0.006-50 mg/L. In this demonstration, we used two-color light sources instead of a bulky spectrometer to achieve high sensitivity and wide dynamic range. The details of two-color based differential measurement method will be discussed. This novel protein-based sensor has several advantages such as extremely small size for point-of-care system, multiplexing capability, no need of complex optical geometry.

Improving the Performance of Semiconductor Sensor Devices Using Surface Functionalization

NASA Astrophysics Data System (ADS)

Rohrbaugh, Nathaniel W.

As production and understanding of III-nitride growth has progressed, this class of material has been used for its semiconducting properties in the fields of computer processing, microelectronics, and LEDs. As understanding of materials properties has advanced, devices were fabricated to be sensitive to environmental surroundings such as pH, gas, or ionic concentration. Simultaneously the world of pharmaceuticals and environmental science has come to the age where the use of wearable devices and active environmental sensing can not only help us learn more about our surroundings, but help save lives. At the crossroads of these two fields work has been done in marrying the high stability and electrical properties of the III-nitrides with the needs of a growing sensor field for various environments and stimuli. Device architecture can only get one so far, and thus the need for well understood surface functionalization techniques has arisen in the field of III-nitride environmental sensing. Many existing schemes for functionalization involve chemistries that may be unfriendly to a biological environment, unstable in solution, or expensive to produce. One possible solution to these issues is the work presented here, which highlights a surface modification scheme utilizing phosphonic acid based chemistry and biomolecular attachment. This dissertation presents a set of studies and experiments quantifying and analyzing the response behaviors of AlGaN/GaN field effect transistor (FET) devices via their interfacial electronic properties. Additional investigation was done on the modification of these surfaces, effects of stressful environmental conditions, and the utility of the phosphonic acid surface treatments. Signals of AlGaN/GaN FETs were measured as IDrain values and in the earliest study an average signal increase of 96.43% was observed when surfaces were incubated in a solution of a known recognition peptide sequence (SVSVGMKPSPRP). This work showed that even without a form of surface modification the devices were capable of generating a response in the presence of a charged biomolecule. Solution exposure tests done devices showed that incubating peptides on the device surfaces produced a weak interaction and following 24 hrs of soaking no signs of peptide remained via XPS analysis. Subsequent testing was done to incorporate the phosphonic acid functionalization techniques shown previously by other members of this lab to the AlGaN/GaN surfaces as a remedy to this solution instability. In this second study FETs were modified using a heated phosphoric acid:ethephon etch followed by an incubation in TAT-C peptide. Resulting IV measurements done on the samples showed a shift in threshold voltage of the FETs following the etching procedure followed by a recovery of this shift from prolonged solution exposure. In total samples were given 168 hours of soaking and showed persistent peptide presence through the N 1s peak from XPS scans. FETs modified with this phosphonic acid derivative were examined in a third study under a simulated pollutant sensing scenario by measuring varied concentrations of Hg via a phytochelatin peptide bound to FET surfaces. HNO3 used in the Hg stock solution led to degradation of the FET signal but did not remove the phytochelatin layer. This led to a compensation effect in sensing the highest levels of Hg, lower concentrations however were successfully tested and showed varied responses from the FETs relative to the Hg content. In a concluding study on devices work was done to understand broader effects on the AlGaN/GaN FETs relative to a simulated biological sensing environment. Here an effect was noted from the addition of a biological fouling solution to the FETs and an increase in this effect when the biofouling was done to a phosphonic modified FET surface. Additionally devices were modified and soaked for 5 weeks and showed no shift or degradation in signal. Lastly in controlling for gate width of the FET it was found that the shorter 50 im gates were more susceptible to environmental interference than the 100 and 150 im gated devices. Thus this work has shown that modifying AlGaN/GaN devices with phosphonic acid derivatives is a viable functionalization method that is both adaptable and stable in solution over time. In moving forward, opportunities are available for testing a larger variety of analytes in both the medical and environmental fields. The final goal for this technology would be the fabrication and design of a multi-device sensing unit leading to eventual production of these sensors on an industrial scale for the use in future personal medical devices or environmental monitoring systems.

Operation of a New Half-Bridge Gate Driver for Enhancement - Mode GaN FETs, Type LM5113, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2011-01-01

A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.

A 4H Silicon Carbide Gate Buffer for Integrated Power Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, N; Frank, S; Britton, C

2014-02-01

A gate buffer fabricated in a 2-mu m 4H silicon carbide (SiC) process is presented. The circuit is composed of an input buffer stage with a push-pull output stage, and is fabricated using enhancement mode N-channel FETs in a process optimized for SiC power switching devices. Simulation and measurement results of the fabricated gate buffer are presented and compared for operation at various voltage supply levels, with a capacitive load of 2 nF. Details of the design including layout specifics, simulation results, and directions for future improvement of this buffer are presented. In addition, plans for its incorporation into anmore » isolated high-side/low-side gate-driver architecture, fully integrated with power switching devices in a SiC process, are briefly discussed. This letter represents the first reported MOSFET-based gate buffer fabricated in 4H SiC.« less

Circuit model for single-energy-level trap centers in FETs

NASA Astrophysics Data System (ADS)

Albahrani, Sayed Ali; Parker, Anthony; Heimlich, Michael

2016-12-01

A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.

Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Johnson, A. T.; MacDiarmid, A. G.; Mueller, C. H.; Theofylaktos, N.; Robinson, D. C.; Miranda, F. A.

2003-01-01

We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.

Effect of buffer layer on photoresponse of MoS2 phototransistor

NASA Astrophysics Data System (ADS)

Miyamoto, Yuga; Yoshikawa, Daiki; Takei, Kuniharu; Arie, Takayuki; Akita, Seiji

2018-06-01

An atomically thin MoS2 field-effect transistor (FET) is expected as an ultrathin photosensor with high sensitivity. However, a persistent photoconductivity phenomenon prevents high-speed photoresponse. Here, we investigate the photoresponse of a MoS2 FET with a thin Al2O3 buffer layer on a SiO2 gate insulator. The application of a 2-nm-thick Al2O3 buffer layer greatly improves not only the steady state properties but also the response speed from 1700 to 0.2 s. These experimental results are well explained by the random localized potential fluctuation model combined with the model based on the recombination of the bounded electrons around the trapped hole.

The NASA satellite communication 20 x 20 matrix switches

NASA Technical Reports Server (NTRS)

Saunders, A. L.

1983-01-01

The characteristics of two matrix switches designed for high capacity satellite communications systems are described. The switches provide routing between 20 input and 20 output ports at an IF frequency during TDMA operations. Switching speeds of 10 nsec are projected for dual gate GaAs FETs. The two designs differed in the coupling configurations, bandwidth (2.69-1.2 GHz), off-state isolation (-54 to -40 dB), switching speeds (16-37 nsec), and gain ripple (5.3-2.2 dB). Both designs achieved a 2 nsec reconfiguration rate. Further development is required to reduce the ripple effects and attain the potential 2 nsec switching speed offered by the GaAs FETs.

Experimental and theoretical studies of Sub-THz detection using strained-Si FETs

NASA Astrophysics Data System (ADS)

Delgado Notario, J. A.; Javadi, E.; Clericò, V.; Fobelets, K.; Otsuji, T.; Diez, E.; Velázquez-Pérez, J. E.; Meziani, Y. M.

2017-10-01

We report on experimental and theoretical studies of nanoscale gate-lengths strained Silicon MODFETs as room temperature non resonant detectors. Devices were excited at room temperature by an electronic source at 150 and 300 GHz to characterize their sub-THz response. The maximum of the photovoltaic response was obtained when the FET gate was biased at a value close to the threshold voltage. Simulations based on a bi-dimensional hydrodynamic model for the charge transport coupled to a Poisson equation solver were performed by using Synopsys TCAD. A charge boundary condition for the floating drain contact was implemented to obtain the photovoltaic response. Results from numerical simulations are in agreement with experimental ones. To understand the coupling between terahertz radiation and devices, the devices were rotated at different angles under excitation at both sub-terahertz frequencies and their response measured. Both NEP (Noise Equivalent Power) and Responsivity were calculated from measurements. To demonstrate their utility, devices were used as sensors in a terahertz imaging system for inspection of hidden objects at both frequencies.

Predictive of the quantum capacitance effect on the excitation of plasma waves in graphene transistors with scaling limit

NASA Astrophysics Data System (ADS)

Wang, Lin; Chen, Xiaoshuang; Hu, Yibin; Wang, Shao-Wei; Lu, Wei

2015-04-01

Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions.Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr07689c

Metal–insulator transition in a transition metal dichalcogenide: Dependence on metal contacts

NASA Astrophysics Data System (ADS)

Shimazu, Y.; Arai, K.; Iwabuchi, T.

2018-03-01

Transition metal dichalcogenides are promising layered materials for realizing novel nanoelectronic and nano-optoelectronic devices. Molybdenum disulfide (MoS2), a typical transition metal dichalcogenide, has been extensively investigated due to the presence of a sizable band gap, which enables the use of MoS2 as a channel material in field-effect transistors (FET). The gate-voltage-tunable metal–insulator transition and superconductivity using MoS2 have been demonstrated in previous studies. These interesting phenomena can be considered as quantum phase transitions in two-dimensional systems. In this study, we observed that the transport properties of thin MoS2 flakes in FET geometry significantly depend on metal contacts. On comparing Ti/Au with Al contacts, it was found that the threshold voltages for FET switching and metal–insulator transition were considerably lower for the device with Al contacts. This result indicated the significant influence of the Al contacts on the properties of MoS2 devices.

High quality crystalline pentacene and rubrene FETs

NASA Astrophysics Data System (ADS)

Butko, Vladimir

2005-03-01

Molecular organic materials offer the promise of novel electronic devices but also present challenges for understanding charge transport in narrow band systems. We find that one of the most important intermolecular transport FET parameters, the effective channel mobility, is parameterized by two factors: (1) the degree of carrier trapping in localized DOS band-tail states, which are higher in concentration for FET structures than for bulk crystal, and (2) the free-carrier mobility, μ0. Our analysis shows crystalline devices possess μ0˜70 cm^2/Vs, significantly greater than polycrystalline thin film devices where free-carrier mobility μ0˜1 cm^2/Vs. Low temperature studies elucidate fundamental transport processes. We report the lowest temperature field effect transport results on a crystalline oligomeric organic material, rubrene. Gated transport shows a factor of ˜10 suppression of the thermal activation energy in 10-50 K range and nearly temperature independent resistivity below 10 K. Other examples of 2 dimensional charge carrier transport will also be discussed.

Negative Photoconductance in Heavily Doped Si Nanowire Field-Effect Transistors.

PubMed

Baek, Eunhye; Rim, Taiuk; Schütt, Julian; Baek, Chang-Ki; Kim, Kihyun; Baraban, Larysa; Cuniberti, Gianaurelio

2017-11-08

We report the first observation of negative photoconductance (NPC) in n- and p-doped Si nanowire field-effect transistors (FETs) and demonstrate the strong influence of doping concentrations on the nonconventional optical switching of the devices. Furthermore, we show that the NPC of Si nanowire FETs is dependent on the wavelength of visible light due to the phonon-assisted excitation to multiple conduction bands with different band gap energies that would be a distinct optoelectronic property of indirect band gap semiconductor. We attribute the main driving force of NPC in Si nanowire FETs to the photogenerated hot electrons trapping by dopants ions and interfacial states. Finally, comparing back- and top-gate modulation, we derive the mechanisms of the transition between negative and positive photoconductance regimes in nanowire devices. The transition is decided by the competition between the light-induced interfacial trapping and the recombination of mobile carriers, which is dependent on the light intensity and the doping concentration.

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Kim, Hyeongnam; Nath, Digbijoy; Rajan, Siddharth; Lu, Wu

2013-01-01

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/ p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al0.2Ga0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al0.3Ga0.7N/GaN channel/Al0.2Ga0.8N/ p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80- μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al0.3GaN0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.

Inhomogeneous screening of gate electric field by interface states in graphene FETs

NASA Astrophysics Data System (ADS)

Singh, Anil Kumar; Gupta, Anjan Kumar

2017-09-01

The electronic states at graphene-SiO2 interface and their inhomogeneity is investigated using the back-gate-voltage dependence of local tunnel spectra acquired with a scanning tunneling microscope. The conductance spectra show two, or occasionally three, minima that evolve along the bias-voltage axis with the back gate voltage. This evolution is modeled using tip-gating and interface states. The energy dependent interface states’ density, Dit(E) , required to model the back-gate evolution of the minima, is found to have significant inhomogeneity in its energy-width. A broad Dit(E) leads to an effect similar to a reduction in the Fermi velocity while the narrow Dit(E) leads to the pinning of the Fermi energy close to the Dirac point, as observed in some places, due to enhanced screening of the gate electric field by the narrow Dit(E) . Finally, this also demonstrates STM as a tool to probe the density of interface states in various 2D Dirac materials.

Device Physics of Contact Issues for the Overestimation and Underestimation of Carrier Mobility in Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Liu, Chuan; Li, Gongtan; Di Pietro, Riccardo; Huang, Jie; Noh, Yong-Young; Liu, Xuying; Minari, Takeo

2017-09-01

Very high values of carrier mobility have been recently reported in newly developed materials for field-effect transistors (FETs) or thin-film transistors (TFTs). However, there is an increasing concern of whether the values are overestimated. In this paper, we investigate how much contact resistance a FET or TFT can tolerate to allow the conventional current-voltage equations, which is derived for no contact resistance. We contend that mobility in transistors with resistive contact can be underestimated with the presence of the injection barrier, whereas mobility in transistors with gated Schottky contact can be overestimated by more than 10 times. The latter phenomenon occurs even in long-channel devices, and it becomes more severe when using low-k dielectrics. This is because the band bending and injection barrier experience a complicated evolution on account of electrostatic doping in the semiconducting layer; thus, they do not follow a capacitance approximation. When the band bending is weak, the accumulation is as weak as that in the subthreshold regime. Accordingly, the carrier concentration nonlinearly increases with the gate field. This mechanism can occur with or without exhibiting the "kink" feature in the transfer curves, which has been suggested as the signature of overestimation. For precision, carrier mobility should be presented against gate voltage and should be examined by other recommended extraction methods.

Precision absolute-value amplifier for a precision voltmeter

DOEpatents

Hearn, W.E.; Rondeau, D.J.

1982-10-19

Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resistor is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resistor. The output current through the load resistor is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resistor. A second gain determining resistor is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier. The source and drain circuit of the third transistor is connected between the minus input of the third amplifier and a voltage-frequency converter, constituting an output device. A polarity detector is also provided, comprising a pair of transistors having their inputs connected to the outputs of the first and second differential amplifiers. The outputs of the polarity detector are connected to gates which switch the output of the voltage-frequency converter between up and down counting outputs.

Precision absolute value amplifier for a precision voltmeter

DOEpatents

Hearn, William E.; Rondeau, Donald J.

1985-01-01

Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resister is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resister. The output current through the load resister is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resister. A second gain determining resister is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier. The source and drain circuit of the third transistor is connected between the minus input of the third amplifier and a voltage-frequency converter, constituting an output device. A polarity detector is also provided, comprising a pair of transistors having their inputs connected to the outputs of the first and second differential amplifiers. The outputs of the polarity detector are connected to gates which switch the output of the voltage-frequency converter between up and down counting outputs.

Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

NASA Astrophysics Data System (ADS)

He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

2017-04-01

In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

Spearhead Nanometric Field-Effect Transistor Sensors for Single-Cell Analysis.

PubMed

Zhang, Yanjun; Clausmeyer, Jan; Babakinejad, Babak; Córdoba, Ainara López; Ali, Tayyibah; Shevchuk, Andrew; Takahashi, Yasufumi; Novak, Pavel; Edwards, Christopher; Lab, Max; Gopal, Sahana; Chiappini, Ciro; Anand, Uma; Magnani, Luca; Coombes, R Charles; Gorelik, Julia; Matsue, Tomokazu; Schuhmann, Wolfgang; Klenerman, David; Sviderskaya, Elena V; Korchev, Yuri

2016-03-22

Nanometric field-effect-transistor (FET) sensors are made on the tip of spear-shaped dual carbon nanoelectrodes derived from carbon deposition inside double-barrel nanopipettes. The easy fabrication route allows deposition of semiconductors or conducting polymers to comprise the transistor channel. A channel from electrodeposited poly pyrrole (PPy) exhibits high sensitivity toward pH changes. This property is exploited by immobilizing hexokinase on PPy nano-FETs to give rise to a selective ATP biosensor. Extracellular pH and ATP gradients are key biochemical constituents in the microenvironment of living cells; we monitor their real-time changes in relation to cancer cells and cardiomyocytes. The highly localized detection is possible because of the high aspect ratio and the spear-like design of the nano-FET probes. The accurately positioned nano-FET sensors can detect concentration gradients in three-dimensional space, identify biochemical properties of a single living cell, and after cell membrane penetration perform intracellular measurements.

Spearhead Nanometric Field-Effect Transistor Sensors for Single-Cell Analysis

PubMed Central

Córdoba, Ainara López; Ali, Tayyibah; Shevchuk, Andrew; Takahashi, Yasufumi; Novak, Pavel; Edwards, Christopher; Lab, Max; Gopal, Sahana; Chiappini, Ciro; Anand, Uma; Magnani, Luca; Coombes, R. Charles; Gorelik, Julia; Matsue, Tomokazu; Schuhmann, Wolfgang; Klenerman, David; Sviderskaya, Elena V.; Korchev, Yuri

2016-01-01

Nanometric field-effect-transistor (FET) sensors are made on the tip of spear-shaped dual carbon nanoelectrodes derived from carbon deposition inside double-barrel nanopipettes. The easy fabrication route allows deposition of semiconductors or conducting polymers to comprise the transistor channel. A channel from electrodeposited poly pyrrole (PPy) exhibits high sensitivity toward pH changes. This property is exploited by immobilizing hexokinase on PPy nano-FETs to give rise to a selective ATP biosensor. Extracellular pH and ATP gradients are key biochemical constituents in the microenvironment of living cells; we monitor their real-time changes in relation to cancer cells and cardiomyocytes. The highly localized detection is possible because of the high aspect ratio and the spear-like design of the nano-FET probes. The accurately positioned nano-FET sensors can detect concentration gradients in three-dimensional space, identify biochemical properties of a single living cell, and after cell membrane penetration perform intracellular measurements. PMID:26816294

A highly manufacturable 0.2 {mu}m AlGaAs/InGaAs PHEMT fabricated using the single-layer integrated-metal FET (SLIMFET) process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Havasy, C.K.; Quach, T.K.; Bozada, C.A.

1995-12-31

This work is the development of a single-layer integrated-metal field effect transistor (SLIMFET) process for a high performance 0.2 {mu}m AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT). This process is compatible with MMIC fabrication and minimizes process variations, cycle time, and cost. This process uses non-alloyed ohmic contacts, a selective gate-recess etching process, and a single gate/source/drain metal deposition step to form both Schottky and ohmic contacts at the same time.

Glucose Sensing Using Functionalized Amorphous In-Ga-Zn-O Field-Effect Transistors.

PubMed

Du, Xiaosong; Li, Yajuan; Motley, Joshua R; Stickle, William F; Herman, Gregory S

2016-03-01

Recent advances in glucose sensing have focused on the integration of sensors into contact lenses to allow noninvasive continuous glucose monitoring. Current technologies focus primarily on enzyme-based electrochemical sensing which requires multiple nontransparent electrodes to be integrated. Herein, we leverage amorphous indium gallium zinc oxide (IGZO) field-effect transistors (FETs), which have found use in a wide range of display applications and can be made fully transparent. Bottom-gated IGZO-FETs can have significant changes in electrical characteristics when the back-channel is exposed to different environments. We have functionalized the back-channel of IGZO-FETs with aminosilane groups that are cross-linked to glucose oxidase and have demonstrated that these devices have high sensitivity to changes in glucose concentrations. Glucose sensing occurs through the decrease in pH during glucose oxidation, which modulates the positive charge of the aminosilane groups attached to the IGZO surface. The change in charge affects the number of acceptor-like surface states which can deplete electron density in the n-type IGZO semiconductor. Increasing glucose concentrations leads to an increase in acceptor states and a decrease in drain-source conductance due to a positive shift in the turn-on voltage. The functionalized IGZO-FET devices are effective in minimizing detection of interfering compounds including acetaminophen and ascorbic acid. These studies suggest that IGZO FETs can be effective for monitoring glucose concentrations in a variety of environments, including those where fully transparent sensing elements may be of interest.

A small signal amplifier based on ionic liquid gated black phosphorous field effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Saptarshi; Zhang, Wei; Thoutam, Laxman Raju

2015-04-10

In this article we report an analog small signal amplifier based on semiconducting black phosphorus (BP), the most recent addition to the family of two dimensional crystals. The amplifier, consisting of a BP load resistor and a BP field effect transistor (FET) was integrated on a single flake. The gain of the amplifier was found to be ~9 and it remained undistorted for input signal frequencies up to 15 kHz. In addition, we also report record high ON current of 200 µA/µm at V DD = -0.5V in BP FETs. Our results demonstrates the possibility for the implementation of BPmore » in the future generations of analog devices.« less

Sulfur as a surface passivation for InP

NASA Technical Reports Server (NTRS)

Iyer, R.; Chang, R. R.; Lile, D. L.

1988-01-01

The use of liquid and gas phase sulfur pretreatment of the surface of InP as a way to form a near-ideal passivated surface prior to chemical vapor deposition of SiO2 was investigated. Results of high-frequency and quasi-static capacitance-voltage measurements, as well as enhancement mode insulated gate field-effect transistor (FET) transductance and drain current stability studies, all support the efficacy of this approach for metal-insulator-semiconductor application of this semiconductor. In particular, surface state values in the range of 10 to the 10th to a few 10 to the 11th/sq cm per eV and enhancement mode FET drain current drifts of less than 5 percent over a 12 h test period were measured.

Design and synthesis of diverse functional kinked nanowire structures for nanoelectronic bioprobes.

PubMed

Xu, Lin; Jiang, Zhe; Qing, Quan; Mai, Liqiang; Zhang, Qingjie; Lieber, Charles M

2013-02-13

Functional kinked nanowires (KNWs) represent a new class of nanowire building blocks, in which functional devices, for example, nanoscale field-effect transistors (nanoFETs), are encoded in geometrically controlled nanowire superstructures during synthesis. The bottom-up control of both structure and function of KNWs enables construction of spatially isolated point-like nanoelectronic probes that are especially useful for monitoring biological systems where finely tuned feature size and structure are highly desired. Here we present three new types of functional KNWs including (1) the zero-degree KNW structures with two parallel heavily doped arms of U-shaped structures with a nanoFET at the tip of the "U", (2) series multiplexed functional KNW integrating multi-nanoFETs along the arm and at the tips of V-shaped structures, and (3) parallel multiplexed KNWs integrating nanoFETs at the two tips of W-shaped structures. First, U-shaped KNWs were synthesized with separations as small as 650 nm between the parallel arms and used to fabricate three-dimensional nanoFET probes at least 3 times smaller than previous V-shaped designs. In addition, multiple nanoFETs were encoded during synthesis in one of the arms/tip of V-shaped and distinct arms/tips of W-shaped KNWs. These new multiplexed KNW structures were structurally verified by optical and electron microscopy of dopant-selective etched samples and electrically characterized using scanning gate microscopy and transport measurements. The facile design and bottom-up synthesis of these diverse functional KNWs provides a growing toolbox of building blocks for fabricating highly compact and multiplexed three-dimensional nanoprobes for applications in life sciences, including intracellular and deep tissue/cell recordings.

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

PubMed Central

Brady, Gerald J.; Way, Austin J.; Safron, Nathaniel S.; Evensen, Harold T.; Gopalan, Padma; Arnold, Michael S.

2016-01-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies. PMID:27617293

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs.

PubMed

Brady, Gerald J; Way, Austin J; Safron, Nathaniel S; Evensen, Harold T; Gopalan, Padma; Arnold, Michael S

2016-09-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

Bandlike Transport in Ferroelectric-Based Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Laudari, A.; Guha, S.

2016-10-01

The dielectric constant of polymer-ferroelectric dielectrics may be tuned by changing the temperature, offering a platform for monitoring changes in interfacial transport with the polarization strength in organic field-effect transistors (FETs). Temperature-dependent transport studies of FETs are carried out from a solution-processed organic semiconductor, 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene), using both ferroelectric- and nonferroelectric-gate insulators. Nonferroelectric dielectric-based TIPS-pentacene FETs show a clear activated transport, in contrast to the ferroelectric dielectric polymer, poly(vinylidene fluoride-trifluoroethylene), where a negative temperature coefficient of the mobility is observed in the ferroelectric temperature range. The current-voltage (I -V ) characteristics from TIPS-pentacene diodes signal a space-charge-limited conduction (SCLC) for a discrete set of trap levels, suggesting that charge injection and transport occurs through regions of ordering in the semiconductor. The carrier mobility extracted from temperature-dependent I -V characteristics from the trap-free SCLC region shows a negative coefficient beyond 200 K, similar to the trend observed in FETs with the ferroelectric dielectric. At moderate temperatures, the polarization-fluctuation-dominant transport inherent in a ferroelectric dielectric, in conjunction with the nature of traps, results in an effective detrapping of the shallow-trap states into more mobile states in TIPS-pentacene.

Large-area, continuous and high electrical performances of bilayer to few layers MoS2 fabricated by RF sputtering via post-deposition annealing method

PubMed Central

Hussain, Sajjad; Singh, Jai; Vikraman, Dhanasekaran; Singh, Arun Kumar; Iqbal, Muhammad Zahir; Khan, Muhammad Farooq; Kumar, Pushpendra; Choi, Dong-Chul; Song, Wooseok; An, Ki-Seok; Eom, Jonghwa; Lee, Wan-Gyu; Jung, Jongwan

2016-01-01

We report a simple and mass-scalable approach for thin MoS2 films via RF sputtering combined with the post-deposition annealing process. We have prepared as-sputtered film using a MoS2 target in the sputtering system. The as-sputtered film was subjected to post-deposition annealing to improve crystalline quality at 700 °C in a sulfur and argon environment. The analysis confirmed the growth of continuous bilayer to few-layer MoS2 film. The mobility value of ~29 cm2/Vs and current on/off ratio on the order of ~104 were obtained for bilayer MoS2. The mobility increased up to ~173–181 cm2/Vs, respectively, for few-layer MoS2. The mobility of our bilayer MoS2 FETs is larger than any previously reported values of single to bilayer MoS2 grown on SiO2/Si substrate with a SiO2 gate oxide. Moreover, our few-layer MoS2 FETs exhibited the highest mobility value ever reported for any MoS2 FETs with a SiO2 gate oxide. It is presumed that the high mobility behavior of our film could be attributed to low charged impurities of our film and dielectric screening effect by an interfacial MoOxSiy layer. The combined preparation route of RF sputtering and post-deposition annealing process opens up the novel possibility of mass and batch production of MoS2 film. PMID:27492282

Enzyme-polyelectrolyte multilayer assemblies on reduced graphene oxide field-effect transistors for biosensing applications.

PubMed

Piccinini, Esteban; Bliem, Christina; Reiner-Rozman, Ciril; Battaglini, Fernando; Azzaroni, Omar; Knoll, Wolfgang

2017-06-15

We present the construction of layer-by-layer (LbL) assemblies of polyethylenimine and urease onto reduced-graphene-oxide based field-effect transistors (rGO FETs) for the detection of urea. This versatile biosensor platform simultaneously exploits the pH dependency of liquid-gated graphene-based transistors and the change in the local pH produced by the catalyzed hydrolysis of urea. The use of an interdigitated microchannel resulted in transistors displaying low noise, high pH sensitivity (20.3µA/pH) and transconductance values up to 800 µS. The modification of rGO FETs with a weak polyelectrolyte improved the pH response because of its transducing properties by electrostatic gating effects. In the presence of urea, the urease-modified rGO FETs showed a shift in the Dirac point due to the change in the local pH close to the graphene surface. Markedly, these devices operated at very low voltages (less than 500mV) and were able to monitor urea in the range of 1-1000µm, with a limit of detection (LOD) down to 1µm, fast response and good long-term stability. The urea-response of the transistors was enhanced by increasing the number of bilayers due to the increment of the enzyme surface coverage onto the channel. Moreover, quantification of the heavy metal Cu 2+ (with a LOD down to 10nM) was performed in aqueous solution by taking advantage of the urease specific inhibition. Copyright © 2016 The Authors. Published by Elsevier B.V. All rights reserved.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Superconductivity Series in Transition Metal Dichalcogenides by Ionic Gating

PubMed Central

Shi, Wu; Ye, Jianting; Zhang, Yijin; Suzuki, Ryuji; Yoshida, Masaro; Miyazaki, Jun; Inoue, Naoko; Saito, Yu; Iwasa, Yoshihiro

2015-01-01

Functionalities of two-dimensional (2D) crystals based on semiconducting transition metal dichalcogenides (TMDs) have now stemmed from simple field effect transistors (FETs) to a variety of electronic and opto-valleytronic devices, and even to superconductivity. Among them, superconductivity is the least studied property in TMDs due to methodological difficulty accessing it in different TMD species. Here, we report the systematic study of superconductivity in MoSe2, MoTe2 and WS2 by ionic gating in different regimes. Electrostatic gating using ionic liquid was able to induce superconductivity in MoSe2 but not in MoTe2 because of inefficient electron accumulation limited by electronic band alignment. Alternative gating using KClO4/polyethylene glycol enabled a crossover from surface doping to bulk doping, which induced superconductivities in MoTe2 and WS2 electrochemically. These new varieties greatly enriched the TMD superconductor families and unveiled critical methodology to expand the capability of ionic gating to other materials. PMID:26235962

Superconductivity Series in Transition Metal Dichalcogenides by Ionic Gating.

PubMed

Shi, Wu; Ye, Jianting; Zhang, Yijin; Suzuki, Ryuji; Yoshida, Masaro; Miyazaki, Jun; Inoue, Naoko; Saito, Yu; Iwasa, Yoshihiro

2015-08-03

Functionalities of two-dimensional (2D) crystals based on semiconducting transition metal dichalcogenides (TMDs) have now stemmed from simple field effect transistors (FETs) to a variety of electronic and opto-valleytronic devices, and even to superconductivity. Among them, superconductivity is the least studied property in TMDs due to methodological difficulty accessing it in different TMD species. Here, we report the systematic study of superconductivity in MoSe2, MoTe2 and WS2 by ionic gating in different regimes. Electrostatic gating using ionic liquid was able to induce superconductivity in MoSe2 but not in MoTe2 because of inefficient electron accumulation limited by electronic band alignment. Alternative gating using KClO4/polyethylene glycol enabled a crossover from surface doping to bulk doping, which induced superconductivities in MoTe2 and WS2 electrochemically. These new varieties greatly enriched the TMD superconductor families and unveiled critical methodology to expand the capability of ionic gating to other materials.

AlGaN/GaN-on-Si monolithic power-switching device with integrated gate current booster

NASA Astrophysics Data System (ADS)

Han, Sang-Woo; Jo, Min-Gi; Kim, Hyungtak; Cho, Chun-Hyung; Cha, Ho-Young

2017-08-01

This study investigates the effects of a monolithic gate current booster integrated with an AlGaN/GaN-on-Si power-switching device. The integrated gate current booster was implemented by a single-stage inverter topology consisting of a recessed normally-off AlGaN/GaN MOS-HFET and a mesa resistor. The monolithically integrated gate current booster in a switching FET eliminated the parasitic elements caused by external interconnection and enabled fast switching operation. The gate charging and discharging currents were boosted by the integrated inverter, which significantly reduced both rise and fall times: the rise time was reduced from 626 to 41.26 ns, while the fall time was reduced from 554 to 42.19 ns by the single-stage inverter. When the packaged monolithic power chip was tested under 1 MHz hard-switching operation with VDD = 200 V, the switching loss was found to have been drastically reduced, from 5.27 to 0.55 W.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

GaAs-based optoelectronic neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H. (Inventor); Kim, Jae H. (Inventor); Psaltis, Demetri (Inventor)

1993-01-01

An integrated, optoelectronic, variable thresholding neuron implemented monolithically in GaAs integrated circuit and exhibiting high differential optical gain and low power consumption is presented. Two alternative embodiments each comprise an LED monolithically integrated with a detector and two transistors. One of the transistors is responsive to a bias voltage applied to its gate for varying the threshold of the neuron. One embodiment is implemented as an LED monolithically integrated with a double heterojunction bipolar phototransistor (detector) and two metal semiconductor field effect transistors (MESFET's) on a single GaAs substrate and another embodiment is implemented as an LED monolithically integrated with three MESFET's (one of which is an optical FET detector) on a single GaAs substrate. The first noted embodiment exhibits a differential optical gain of 6 and an optical switching energy of 10 pJ. The second embodiment has a differential optical gain of 80 and an optical switching energy of 38 pJ. Power consumption is 2.4 and 1.8 mW, respectively. Input 'light' power needed to turn on the LED is 2 micro-W and 54 nW, respectively. In both embodiments the detector is in series with a biasing MESFET and saturates the other MESFET upon detecting light above a threshold level. The saturated MESFET turns on the LED. Voltage applied to the biasing MESFET gate controls the threshold.

Synthesis of Mismatched Heterojunction/Substrate Interfaces

DTIC Science & Technology

1991-10-11

and advantages of strained layers. DD IZ JAN7 1473 EDITION OF INOV 65 IS OBSOLETE *’~~s.*. ~ ~.-A ~’ SECURITY CLASSIFICATIO14 Ol THIS PAGE (When Dsea...cross-section is shown ini 1-ig. 1.14(a), is analogous to the polysilicon -gate FET in Si-MOS devices. From the band diagam in Fig 1.14(b), it can be seen

High-field modulated ion-selective field-effect-transistor (FET) sensors with sensitivity higher than the ideal Nernst sensitivity.

PubMed

Chen, Yi-Ting; Sarangadharan, Indu; Sukesan, Revathi; Hseih, Ching-Yen; Lee, Geng-Yen; Chyi, Jen-Inn; Wang, Yu-Lin

2018-05-29

Lead ion selective membrane (Pb-ISM) coated AlGaN/GaN high electron mobility transistors (HEMT) was used to demonstrate a whole new methodology for ion-selective FET sensors, which can create ultra-high sensitivity (-36 mV/log [Pb 2+ ]) surpassing the limit of ideal sensitivity (-29.58 mV/log [Pb 2+ ]) in a typical Nernst equation for lead ion. The largely improved sensitivity has tremendously reduced the detection limit (10 -10  M) for several orders of magnitude of lead ion concentration compared to typical ion-selective electrode (ISE) (10 -7  M). The high sensitivity was obtained by creating a strong filed between the gate electrode and the HEMT channel. Systematical investigation was done by measuring different design of the sensor and gate bias, indicating ultra-high sensitivity and ultra-low detection limit obtained only in sufficiently strong field. Theoretical study in the sensitivity consistently agrees with the experimental finding and predicts the maximum and minimum sensitivity. The detection limit of our sensor is comparable to that of Inductively-Coupled-Plasma Mass Spectrum (ICP-MS), which also has detection limit near 10 -10  M.

Nanopore extended field-effect transistor for selective single-molecule biosensing.

PubMed

Ren, Ren; Zhang, Yanjun; Nadappuram, Binoy Paulose; Akpinar, Bernice; Klenerman, David; Ivanov, Aleksandar P; Edel, Joshua B; Korchev, Yuri

2017-09-19

There has been a significant drive to deliver nanotechnological solutions to biosensing, yet there remains an unmet need in the development of biosensors that are affordable, integrated, fast, capable of multiplexed detection, and offer high selectivity for trace analyte detection in biological fluids. Herein, some of these challenges are addressed by designing a new class of nanoscale sensors dubbed nanopore extended field-effect transistor (nexFET) that combine the advantages of nanopore single-molecule sensing, field-effect transistors, and recognition chemistry. We report on a polypyrrole functionalized nexFET, with controllable gate voltage that can be used to switch on/off, and slow down single-molecule DNA transport through a nanopore. This strategy enables higher molecular throughput, enhanced signal-to-noise, and even heightened selectivity via functionalization with an embedded receptor. This is shown for selective sensing of an anti-insulin antibody in the presence of its IgG isotype.Efficient detection of single molecules is vital to many biosensing technologies, which require analytical platforms with high selectivity and sensitivity. Ren et al. combine a nanopore sensor and a field-effect transistor, whereby gate voltage mediates DNA and protein transport through the nanopore.

Junctionless tri-gate InGaAs MOSFETs

NASA Astrophysics Data System (ADS)

Zota, Cezar B.; Borg, Mattias; Wernersson, Lars-Erik; Lind, Erik

2017-12-01

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 × 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mS/µm and I ON = 160 µA/µm (at I OFF = 100 nA/µm and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Monte Carlo model for the analysis and development of III-V Tunnel-FETs and Impact Ionization-MOSFETs

NASA Astrophysics Data System (ADS)

Talbo, V.; Mateos, J.; González, T.; Lechaux, Y.; Wichmann, N.; Bollaert, S.; Vasallo, B. G.

2015-10-01

Impact-ionization metal-oxide-semiconductor FETs (I-MOSFETs) are in competition with tunnel FETs (TFETs) in order to achieve the best behaviour for low power logic circuits. Concretely, III-V I-MOSFETs are being explored as promising devices due to the proper reliability, since the impact ionization events happen away from the gate oxide, and the high cutoff frequency, due to high electron mobility. To facilitate the design process from the physical point of view, a Monte Carlo (MC) model which includes both impact ionization and band-to-band tunnel is presented. Two ungated InGaAs and InAlAs/InGaAs 100 nm PIN diodes have been simulated. In both devices, the tunnel processes are more frequent than impact ionizations, so that they are found to be appropriate for TFET structures and not for I- MOSFETs. According to our simulations, other narrow bandgap candidates for the III-V heterostructure, such as InAs or GaSb, and/or PININ structures must be considered for a correct I-MOSFET design.

Understanding Charge Transport in Mixed Networks of Semiconducting Carbon Nanotubes

PubMed Central

2016-01-01

The ability to select and enrich semiconducting single-walled carbon nanotubes (SWNT) with high purity has led to a fast rise of solution-processed nanotube network field-effect transistors (FETs) with high carrier mobilities and on/off current ratios. However, it remains an open question whether it is best to use a network of only one nanotube species (monochiral) or whether a mix of purely semiconducting nanotubes but with different bandgaps is sufficient for high performance FETs. For a range of different polymer-sorted semiconducting SWNT networks, we demonstrate that a very small amount of narrow bandgap nanotubes within a dense network of large bandgap nanotubes can dominate the transport and thus severely limit on-currents and effective carrier mobility. Using gate-voltage-dependent electroluminescence, we spatially and spectrally reveal preferential charge transport that does not depend on nominal network density but on the energy level distribution within the network and carrier density. On the basis of these results, we outline rational guidelines for the use of mixed SWNT networks to obtain high performance FETs while reducing the cost for purification. PMID:26867006

Photo-assisted hysteresis of electronic transport for ZnO nanowire transistors

NASA Astrophysics Data System (ADS)

Du, Qianqian; Ye, Jiandong; Xu, Zhonghua; Zhu, Shunming; Tang, Kun; Gu, Shulin; Zheng, Youdou

2018-03-01

Recently, ZnO nanowire field effect transistors (FETs) have received renewed interest due to their extraordinary low dimensionality and high sensitivity to external chemical environments and illumination conditions. These prominent properties have promising potential in nanoscale chemical and photo-sensors. In this article, we have fabricated ZnO nanowire FETs and have found hysteresis behavior in their transfer characteristics. The mechanism and dynamics of the hysteresis phenomena have been investigated in detail by varying the sweeping rate and range of the gate bias with and without light irradiation. Significantly, light irradiation is of great importance on charge trapping by regulating adsorption and desorption of oxygen at the interface of ZnO/SiO2. Carriers excited by light irradiation can dramatically promote trapping/detrapping processes. With the assistance of light illumination, we have demonstrated a photon-assisted nonvolatile memory which employs the ZnO nanowire FET. The device exhibits reliable programming/erasing operations and a large on/off ratio. The proposed proto-type memory has thus provided a possible novel path for creating a memory functionality to other low-dimensional material systems.

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

NASA Astrophysics Data System (ADS)

Saeidi, Ali; Jazaeri, Farzan; Stolichnov, Igor; Luong, Gia V.; Zhao, Qing-Tai; Mantl, Siegfried; Ionescu, Adrian M.

2018-03-01

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a trained-polycrystalline PZT capacitor and the tunnel FET (TFET) gate capacitance fabricated on a strained silicon-nanowire technology. We report a non-hysteretic switch configuration by combining a homojunction TFET and a negative capacitance effect booster, suitable for logic applications, for which the on-current is increased by a factor of 100, the transconductance by 2 orders of magnitude, and the low swing region is extended. The operation of a hysteretic negative capacitance TFET, when the matching condition for the negative capacitance is fulfilled only in a limited region of operation, is also reported and discussed. In this late case, a limited improvement in the device performance is observed. Overall, the paper demonstrates the main beneficial effects of negative capacitance on TFETs are the overdrive and transconductance amplification, which exactly address the most limiting performances of current TFETs.

FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers

NASA Technical Reports Server (NTRS)

Theofylaktos, Noulie; Robinson, Daryl; Miranda, Felix; Pinto, Nicholas; Johnson, Alan, Jr.; MacDiarmid, Alan; Mueller, Carl

2006-01-01

A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

Peak holding circuit for extremely narrow pulses

NASA Technical Reports Server (NTRS)

Oneill, R. W. (Inventor)

1975-01-01

An improved pulse stretching circuit comprising: a high speed wide-band amplifier connected in a fast charge integrator configuration; a holding circuit including a capacitor connected in parallel with a discharging network which employs a resistor and an FET; and an output buffer amplifier. Input pulses of very short duration are applied to the integrator charging the capacitor to a value proportional to the input pulse amplitude. After a predetermined period of time, conventional circuitry generates a dump pulse which is applied to the gate of the FET making a low resistance path to ground which discharges the capacitor. When the dump pulse terminates, the circuit is ready to accept another pulse to be stretched. The very short input pulses are thus stretched in width so that they may be analyzed by conventional pulse height analyzers.

Sensitivity Challenge of Steep Transistors

NASA Astrophysics Data System (ADS)

Ilatikhameneh, Hesameddin; Ameen, Tarek A.; Chen, ChinYi; Klimeck, Gerhard; Rahman, Rajib

2018-04-01

Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of these devices in integrated circuits. From a sensitivity perspective, an ideal switch should have a high sensitivity to the gate voltage and lower sensitivity to the device design parameters like oxide and body thicknesses. In this work, conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer from high sensitivity to device design parameters using full-band atomistic quantum transport simulations and analytical analysis. Although Dielectric Engineered (DE-) TFETs based on 2D materials show smaller sensitivity compared with the conventional TFETs, they have leakage issue. To mitigate this challenge, a novel DE-TFET design has been proposed and studied.

Dual origin of room temperature sub-terahertz photoresponse in graphene field effect transistors

NASA Astrophysics Data System (ADS)

Bandurin, D. A.; Gayduchenko, I.; Cao, Y.; Moskotin, M.; Principi, A.; Grigorieva, I. V.; Goltsman, G.; Fedorov, G.; Svintsov, D.

2018-04-01

Graphene is considered as a promising platform for detectors of high-frequency radiation up to the terahertz (THz) range due to its superior electron mobility. Previously, it has been shown that graphene field effect transistors (FETs) exhibit room temperature broadband photoresponse to incoming THz radiation, thanks to the thermoelectric and/or plasma wave rectification. Both effects exhibit similar functional dependences on the gate voltage, and therefore, it was difficult to disentangle these contributions in previous studies. In this letter, we report on combined experimental and theoretical studies of sub-THz response in graphene field-effect transistors analyzed at different temperatures. This temperature-dependent study allowed us to reveal the role of the photo-thermoelectric effect, p-n junction rectification, and plasmonic rectification in the sub-THz photoresponse of graphene FETs.

Efficient n-Doping and Hole Blocking in Single-Walled Carbon Nanotube Transistors with 1,2,4,5-Tetrakis(tetramethylguanidino)ben-zene.

PubMed

Schneider, Severin; Brohmann, Maximilian; Lorenz, Roxana; Hofstetter, Yvonne J; Rother, Marcel; Sauter, Eric; Zharnikov, Michael; Vaynzof, Yana; Himmel, Hans-Jörg; Zaumseil, Jana

2018-05-31

Efficient, stable, and solution-based n-doping of semiconducting single-walled carbon nanotubes (SWCNTs) is highly desired for complementary circuits but remains a significant challenge. Here, we present 1,2,4,5-tetrakis(tetramethylguanidino)benzene (ttmgb) as a strong two-electron donor that enables the fabrication of purely n-type SWCNT field-effect transistors (FETs). We apply ttmgb to networks of monochiral, semiconducting (6,5) SWCNTs that show intrinsic ambipolar behavior in bottom-contact/top-gate FETs and obtain unipolar n-type transport with 3-5-fold enhancement of electron mobilities (approximately 10 cm 2  V -1  s -1 ), while completely suppressing hole currents, even at high drain voltages. These n-type FETs show excellent on/off current ratios of up to 10 8 , steep subthreshold swings (80-100 mV/dec), and almost no hysteresis. Their excellent device characteristics stem from the reduction of the work function of the gold electrodes via contact doping, blocking of hole injection by ttmgb 2+ on the electrode surface, and removal of residual water from the SWCNT network by ttmgb protonation. The ttmgb-treated SWCNT FETs also display excellent environmental stability under bias stress in ambient conditions. Complementary inverters based on n- and p-doped SWCNT FETs exhibit rail-to-rail operation with high gain and low power dissipation. The simple and stable ttmgb molecule thus serves as an example for the larger class of guanidino-functionalized aromatic compounds as promising electron donors for high-performance thin film electronics.

The effect of endometrial scratch on natural-cycle cryopreserved embryo transfer outcomes: a randomized controlled study.

PubMed

Mak, Jennifer Sze Man; Chung, Cathy Hoi Sze; Chung, Jacqueline Pui Wah; Kong, Grace Wing Shan; Saravelos, Sotirios H; Cheung, Lai Ping; Li, Tin-Chiu

2017-07-01

The benefit of endometrial scratch (ES) prior to embryo transfer is controversial. Systemic analysis has confirmed its potential benefit, especially in women with repeated IVF failures, yet most studies have focused on fresh embryo transfer, and its effect on vitrified-warmed embryo transfer (FET) cycles is yet to be explored. We hereby present our prospective, double-blind, randomized controlled study on the evaluation of the implantation and pregnancy rate after ES prior to natural-cycle FET. A total of 299 patients underwent natural-cycle FET and were randomized to receive ES (n = 115) or endocervical manipulation as control (n = 114) prior to FET cycle, and a total of 196 patients had embryo transfer (93 patients in each group). Our study showed no significant difference in the implantation and pregnancy rate, as well as the clinical and ongoing pregnancy or live birth rates between the two groups. It appears that ES does not have any beneficial effect on an unselected group of women undergoing FET in natural cycles. Further studies on its effect in women with recurrent implantation failure after IVF are warranted. Copyright © 2017 Reproductive Healthcare Ltd. Published by Elsevier Ltd. All rights reserved.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

The 20 GHz GaAs monolithic power amplifier module development

NASA Technical Reports Server (NTRS)

1984-01-01

The development of a 20 GHz GaAs FET monlithic power amplifier module for advanced communication applications is described. Four-way power combing of four 0.6 W amplifier modules is used as the baseline approach. For this purpose, a monolithic four-way traveling-wave power divider/combiner was developed. Over a 20 GHz bandwidth (10 to 30 GHz), an insertion loss of no more than 1.2 dB was measured for a pair of back-to-back connected divider/combiners. Isolation between output ports is better than 20 dB, and VSWRs are better than 21:1. A distributed amplifier with six 300 micron gate width FETs and gate and drain transmission line tapers has been designed, fabricated, and evaluated for use as an 0.6 W module. This amplifier has achieved state-of-the-art results of 0.5 W output power with at least 4 dB gain across the entire 2 to 21 GHz frequency range. An output power of 2 W was achieved at a measurement frequency of 18 GHz when four distributed amplifiers were power-combined using a pair of traveling-wave divider/combiners. Another approach is the direct common-source cascading of three power FET stages. An output power of up to 2W with 12 dB gain and 20% power-added efficiency has been achieved with this approach (at 17 GHz). The linear gain was 14 dB at 1 W output. The first two stages of the three-stage amplifier have achieved an output power of 1.6 W with 9 dB gain and 26% power-added efficiency at 16 GHz.

Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS2 flake based field effect transistors on SiO2 and hBN substrates.

PubMed

Lee, Changhee; Rathi, Servin; Khan, Muhammad Atif; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo-Hyeb; Watanabe, Kenji; Taniguchi, Takashi; Kim, Gil-Ho

2018-08-17

Molybdenum disulfide (MoS 2 ) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS 2 flake are fabricated on hBN and SiO 2 substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS 2 -SiO 2 and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS 2 layer with a single hBN on both the devices. The device to device variations induced by different MoS 2 layer is also eliminated by employing a single MoS 2 layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 10 11 cm -2 on hBN substrate as compared to 1.1 × 10 12 cm -2 on SiO 2 substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO 2 and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS 2 FETs.

Test Bus Evaluation

DTIC Science & Technology

1998-04-01

selected is statistically based on the total number of faults and the failure rate distribution in the system under test. The fault set is also...implemented the BPM and system level emulation consolidation logic as well as statistics counters for cache misses and various bus transactions. These...instruction F22 Advanced Tactical Fighter FET Field Effect Transitor FF Flip-Flop FM Failures/Milhon hours C-3 FPGA Field Programmable Gate Array GET

Polarization induced doped transistor

DOEpatents

Xing, Huili; Jena, Debdeep; Nomoto, Kazuki; Song, Bo; Zhu, Mingda; Hu, Zongyang

2016-06-07

A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

Extrinsic Rashba spin-orbit coupling effect on silicene spin polarized field effect transistors

NASA Astrophysics Data System (ADS)

Pournaghavi, Nezhat; Esmaeilzadeh, Mahdi; Abrishamifar, Adib; Ahmadi, Somaieh

2017-04-01

Regarding the spin field effect transistor (spin FET) challenges such as mismatch effect in spin injection and insufficient spin life time, we propose a silicene based device which can be a promising candidate to overcome some of those problems. Using non-equilibrium Green’s function method, we investigate the spin-dependent conductance in a zigzag silicene nanoribbon connected to two magnetized leads which are supposed to be either in parallel or anti-parallel configurations. For both configurations, a controllable spin current can be obtained when the Rashba effect is present; thus, we can have a spin filter device. In addition, for anti-parallel configuration, in the absence of Rashba effect, there is an intrinsic energy gap in the system (OFF-state); while, in the presence of Rashba effect, electrons with flipped spin can pass through the channel and make the ON-state. The current voltage (I-V) characteristics which can be tuned by changing the gate voltage or Rashba strength, are studied. More importantly, reducing the mismatch conductivity as well as energy consumption make the silicene based spin FET more efficient relative to the spin FET based on two-dimensional electron gas proposed by Datta and Das. Also, we show that, at the same conditions, the current and {{I}\\text{on}}/{{I}\\text{off}} ratio of silicene based spin FET are significantly greater than that of the graphene based one.

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor.

PubMed

Vitale, Wolfgang A; Casu, Emanuele A; Biswas, Arnab; Rosca, Teodor; Alper, Cem; Krammer, Anna; Luong, Gia V; Zhao, Qing-T; Mantl, Siegfried; Schüler, Andreas; Ionescu, A M

2017-03-23

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO 2 ) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

Influence of High-Energy Proton Irradiation on β-Ga2O3 Nanobelt Field-Effect Transistors.

PubMed

Yang, Gwangseok; Jang, Soohwan; Ren, Fan; Pearton, Stephen J; Kim, Jihyun

2017-11-22

The robust radiation resistance of wide-band gap materials is advantageous for space applications, where the high-energy particle irradiation deteriorates the performance of electronic devices. We report on the effects of proton irradiation of β-Ga 2 O 3 nanobelts, whose energy band gap is ∼4.85 eV at room temperature. Back-gated field-effect transistor (FET) based on exfoliated quasi-two-dimensional β-Ga 2 O 3 nanobelts were exposed to a 10 MeV proton beam. The proton-dose- and time-dependent characteristics of the radiation-damaged FETs were systematically analyzed. A 73% decrease in the field-effect mobility and a positive shift of the threshold voltage were observed after proton irradiation at a fluence of 2 × 10 15 cm -2 . Greater radiation-induced degradation occurs in the conductive channel of the β-Ga 2 O 3 nanobelt than at the contact between the metal and β-Ga 2 O 3 . The on/off ratio of the exfoliated β-Ga 2 O 3 FETs was maintained even after proton doses up to 2 × 10 15 cm -2 . The radiation-induced damage in the β-Ga 2 O 3 -based FETs was significantly recovered after rapid thermal annealing at 500 °C. The outstanding radiation durability of β-Ga 2 O 3 renders it a promising building block for space applications.

ADMET biosensors: up-to-date issues and strategies.

PubMed

Fang, Yan; Offenhaeusser, Andrease

2004-12-01

This insight review introduces the new concepts, theories, technology, instruments, frontier issues, and key strategies of ADMET (absorption, distribution, metabolism, elimination, and toxicity) biosensors, from the fermi to the quantum levels. Information about ADMET, originating from one author's invention, a patented pharmacotherapy for rescuing cardio-cerebral vascular stunning and regulating vascular endothelial growth-factor signaling at the post-genomic level, can be detected by a new generation of ADMET biosensor. This is a single-cell/single-molecule field-effect transistor (FET) hybrid system, where single molecules or single cells are assembled at the FET surface in a high density array manner via complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Within a given nanometer distance, ADMET-mediated oxidation-reduction (redox) potentials, electrochemistry responses, and electron transfer processes can be simultaneously and directly probed by the gates of field-effect transistor arrays. The nanometer details of the functional coupling principles and characterization technologies of DNA single-molecule/single-cell FETs, as well as the design of lab-on-a-chip instruments, are indicated. Four frontier issues and key strategies are elucidated in detail. This can lead to innovative technology for high-throughout screening of labs-on-chips to resolve the pharmaceutical industry's current bottleneck via novel, FET-based drug discovery and single-molecule/single-cell screening methods, which can bring about a pharmaceutical industry revolution in the 21st century.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Improved performance of InSe field-effect transistors by channel encapsulation

NASA Astrophysics Data System (ADS)

Liang, Guangda; Wang, Yiming; Han, Lin; Yang, Zai-Xing; Xin, Qian; Kudrynskyi, Zakhar R.; Kovalyuk, Zakhar D.; Patanè, Amalia; Song, Aimin

2018-06-01

Due to the high electron mobility and photo-responsivity, InSe is considered as an excellent candidate for next generation electronics and optoelectronics. In particular, in contrast to many high-mobility two-dimensional (2D) materials, such as phosphorene, InSe is more resilient to oxidation in air. Nevertheless, its implementation in future applications requires encapsulation techniques to prevent the adsorption of gas molecules on its surface. In this work, we use a common lithography resist, poly(methyl methacrylate) (PMMA) to encapsulate InSe-based field-effect transistors (FETs). The encapsulation of InSe by PMMA improves the electrical stability of the FETs under a gate bias stress, and increases both the drain current and electron mobility. These findings indicate the effectiveness of the PMMA encapsulation method, which could be applied to other 2D materials.

Ion sensitivity of large-area epitaxial graphene film on SiC substrate

NASA Astrophysics Data System (ADS)

Mitsuno, Takanori; Taniguchi, Yoshiaki; Ohno, Yasuhide; Nagase, Masao

2017-11-01

We investigated the intrinsic ion sensitivity of graphene field-effect transistors (FETs) fabricated by a resist-free stencil mask lithography process from a large-scale graphene film epitaxially grown on a SiC substrate. A pH-adjusted phosphate-buffered solution was used for the measurement to eliminate the interference of other ions on the graphene FET's ion sensitivity. The charge neutrality point shifted negligibly with changing pH for the pH-adjusted phosphate-buffered solution, whereas for the mixed buffer solution, it shifted toward the negative gate voltage owing to the decrease in the concentration of phthalate ions. This phenomenon is contrary to that observed in previous reports. Overall, our results indicate that the graphene film is intrinsically insensitive to ions except for those with functional groups that interact with the graphene surface.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Field-Effect Transistor-Integration with TiO2 Nanoparticles for Sensing of Cardiac Troponin I Biomarker.

PubMed

Arshad, M K Md; Adzhri, R; Fathil, M F M; Gopinath, Subash C B; N M, Nuzaihan M

2018-08-01

The development of electrical biosensor towards device miniaturization in order to achieve better sensitivity with enhanced electrical signal has certain limitations especially complexity in fabrication process and costs. In this paper, an alternative technique with minor modification in the device structure is presented for signal amplification by implementing ambipolar conduction in the biosensor itself. We demonstrated the field-effect transistor (FET)-based biosensor coupled back-gate for attaining a higher sensitivity with the detection of lower target abundance. To utilize the coupled back-gate as a pre-amplifier, silicon-on-insulator wafer with thicknesses of top-silicon and buried oxide (BOX) layers of 70 nm and 145 nm, respectively were desired. Titanium dioxide (TiO2) nanomaterial was deposited using sol-gel method on the channel which acts as a transducer. Surface functionalization on TiO2 thin film allowed an effective immobilization of anti-cardiac troponin I antibody to interact cardiac troponin I (cTnI). Binding events at each step was validated by X-ray photoelectron spectroscopy (XPS) analysis. Further, electrical characterization (Id-Vd) confirms the potentiality of FET-based biosensor to detect cTnI (represents acute myocardial infarction disease) with the concentration ranges from 10 μg/ml down to 1 fg/ml. The sensitivity of 459.2 nA (g/ml)-1 and lower detection limit of 1 fg/ml were achieved at Vbg = -5 V and Vd = 5 V. The designed device demonstrates its ability to detect lower level of cTnI with pre-amplified electrical signal by back-gate biasing.

Bio-Organic Optoelectronic Devices Using DNA

NASA Astrophysics Data System (ADS)

Singh, Thokchom Birendra; Sariciftci, Niyazi Serdar; Grote, James G.

Biomolecular DNA, as a marine waste product from salmon processing, has been exploited as biodegradable polymeric material for photonics and electronics. For preparing high optical quality thin films of DNA, a method using DNA with cationic surfactants such as DNA-cetyltrimethylammonium, CTMA has been applied. This process enhances solubility and processing for thin film fabrication. These DNA-CTMA complexes resulted in the formation of self-assembled supramolecular films. Additionally, the molecular weight can be tailored to suit the application through sonication. It revealed that DNA-CTMA complexes were thermostable up to 230 ∘ C. UV-VIS absorption shows that these thin films have high transparency from 350 to about 1,700 nm. Due to its nature of large band gap and large dielectric constant, thin films of DNA-CTMA has been successfully used in multiple applications such as organic light emitting diodes (OLED), a cladding and host material in nonlinear optical devices, and organic field-effect transistors (OFET). Using this DNA based biopolymers as a gate dielectric layer, OFET devices were fabricated that exhibits current-voltage characteristics with low voltages as compared with using other polymer-based dielectrics. Using a thin film of DNA-CTMA based biopolymer as the gate insulator and pentacene as the organic semiconductor, we have demonstrated a bio-organic FET or BioFET in which the current was modulated over three orders of magnitude using gate voltages less than 10 V. Given the possibility to functionalise the DNA film customised for specific purposes viz. biosensing, DNA-CTMA with its unique structural, optical and electronic properties results in many applications that are extremely interesting.

Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor to Sensor Variations and Enhanced Sensing Characteristics.

PubMed

Zafar, Sufi; D'Emic, Christopher; Jagtiani, Ashish; Kratschmer, Ernst; Miao, Xin; Zhu, Yu; Mo, Renee; Sosa, Norma; Hamann, Hendrik F; Shahidi, Ghavam; Riel, Heike

2018-06-22

Silicon nanowire field effect transistor (FET) sensors have demonstrated their ability for rapid and label free detection of proteins, nucleotide sequences, and viruses at ultralow concentrations with the potential to be a transformative diagnostic technology. Their nanoscale size gives them their unique ultralow detection ability but also makes their fabrication challenging with large sensor to sensor variations, thus limiting their commercial applications. In this work, a combined approach of nanofabrication, device simulation, materials and electrical characterization is applied towards identifying and improving fabrication steps that induce sensor to sensor variations. An enhanced complementary metal-oxide-semiconductor (CMOS) compatible process for fabricating silicon nanowire FET sensors is demonstrated. Nanowire (30 nm width) FETs with aqueous solution as gates are shown to have the Nernst limit sub-threshold swing SS = 60 mV/decade with ~1.7% variations, whereas literature values for SS are ≥ 80 mV/decade with larger (>10 times) variations. Also, their threshold voltage variations are significantly (~3 times) reduced, compared to literature values. Furthermore, these improved FETs have significantly reduced drain current hysteresis (~0.6 mV) and enhanced on-current to off-current ratios (~10 6 ). These improvements resulted in nanowire FET sensors with lowest (~3%) reported sensor to sensor variations, compared to literature studies. Also, these improved nanowire sensors have the highest reported sensitivity and enhanced signal to noise ratio with the lowest reported defect density of 1x10 18 eV -1 cm -3 in comparison to literature data. In summary, this work brings the nanowire sensor technology a step closer to commercial products for early diagnosis and monitoring of diseases.

Correlating Charge Transport with Structure in Deconstructed Diketopyrrolopyrrole Oligomers: A Case Study of a Monomer in Field-Effect Transistors.

PubMed

Pickett, Alec; Torkkeli, Mika; Mukhopadhyay, Tushita; Puttaraju, Boregowda; Laudari, Amrit; Lauritzen, Andreas E; Bikondoa, Oier; Kjelstrup-Hansen, Jakob; Knaapila, Matti; Patil, Satish; Guha, Suchismita

2018-06-13

Copolymers based on diketopyrrolopyrrole (DPP) cores have attracted a lot of attention because of their high p-type as well as n-type carrier mobilities in organic field-effect transistors (FETs) and high power conversion efficiencies in solar cell structures. We report the structural and charge transport properties of n-dialkyl side-chain-substituted thiophene DPP end-capped with a phenyl group (Ph-TDPP-Ph) monomer in FETs which were fabricated by vacuum deposition and solvent coating. Grazing-incidence X-ray diffraction (GIXRD) from bottom-gate, bottom-contact FET architectures was measured with and without biasing. Ph-TDPP-Ph reveals a polymorphic structure with π-conjugated stacking direction oriented in-plane. The unit cell comprises either one monomer with a = 20.89 Å, b = 13.02 Å, c = 5.85 Å, α = 101.4°, β = 90.6°, and γ = 94.7° for one phase (TR1) or two monomers with a = 24.92 Å, b = 25.59 Å, c = 5.42 Å, α = 80.3°, β = 83.5°, and γ = 111.8° for the second phase (TR2). The TR2 phase thus signals a shift from a coplanar to herringbone orientation of the molecules. The device performance is sensitive to the ratio of the two triclinic phases found in the film. Some of the best FET performances with p-type carrier mobilities of 0.1 cm 2 /V s and an on/off ratio of 10 6 are for films that comprise mainly the TR1 phase. GIXRD from in operando FETs demonstrates the crystalline stability of Ph-TDPP-Ph.

Improving the Stability of High-Performance Multilayer MoS2 Field-Effect Transistors.

PubMed

Liu, Na; Baek, Jongyeol; Kim, Seung Min; Hong, Seongin; Hong, Young Ki; Kim, Yang Soo; Kim, Hyun-Suk; Kim, Sunkook; Park, Jozeph

2017-12-13

In this study, we propose a method for improving the stability of multilayer MoS 2 field-effect transistors (FETs) by O 2 plasma treatment and Al 2 O 3 passivation while sustaining the high performance of bulk MoS 2 FET. The MoS 2 FETs were exposed to O 2 plasma for 30 s before Al 2 O 3 encapsulation to achieve a relatively small hysteresis and high electrical performance. A MoO x layer formed during the plasma treatment was found between MoS 2 and the top passivation layer. The MoO x interlayer prevents the generation of excess electron carriers in the channel, owing to Al 2 O 3 passivation, thereby minimizing the shift in the threshold voltage (V th ) and increase of the off-current leakage. However, prolonged exposure of the MoS 2 surface to O 2 plasma (90 and 120 s) was found to introduce excess oxygen into the MoO x interlayer, leading to more pronounced hysteresis and a high off-current. The stable MoS 2 FETs were also subjected to gate-bias stress tests under different conditions. The MoS 2 transistors exhibited negligible decline in performance under positive bias stress, positive bias illumination stress, and negative bias stress, but large negative shifts in V th were observed under negative bias illumination stress, which is attributed to the presence of sulfur vacancies. This simple approach can be applied to other transition metal dichalcogenide materials to understand their FET properties and reliability, and the resulting high-performance hysteresis-free MoS 2 transistors are expected to open up new opportunities for the development of sophisticated electronic applications.

Effect of channel-width and chirality on graphene field-effect transistor based real-time biomolecule sensing

NASA Astrophysics Data System (ADS)

Lyu, Letian; Jaswal, Perveshwer; Xu, Guangyu

2018-03-01

Graphene field-effect transistors (GFET) hold promise in biomolecule sensing due to the outstanding properties of graphene materials. Charges in biomolecules are transduced into a change in the GFET current, which allows real-time monitoring of the biomolecule concentrations. Here we theoretically evaluate the performance of GFET based real-time biomolecule sensing, aiming to better understand the width-scaling limit in GFET based biosensors. In particular, we study the effect of the channel-width and the chirality on FET sensitivity by taking the percentage change of the FET current per unit charge density as the sensing signal. Firstly, GFETs made of graphene nanoribbons (GNR) and graphene sheets (GS) show comparable sensing signals to each other when gated at 1011 - 1012 cm-2 carrier densities. Sensing signals in GNRs are enhanced when gated near the sub-band thresholds, and increase their values in wider GNRs due to the change in device conductance and quantum capacitance. Secondly, the GNR chirality is found to fine tune the sensing signals. Armchair GNRs with smaller energy bandgaps appear to have an enhanced sensing signal close to 1011 cm-2 carrier densities. These results may help understand the scaling limit in GFET based biosensors along the width direction, and shed light on forming all-electrical bio-arrays.

Photoconductivity of few-layered p-WSe2 phototransistors via multi-terminal measurements

NASA Astrophysics Data System (ADS)

Pradhan, Nihar R.; Garcia, Carlos; Holleman, Joshua; Rhodes, Daniel; Parker, Chason; Talapatra, Saikat; Terrones, Mauricio; Balicas, Luis; McGill, Stephen A.

2016-12-01

Recently, two-dimensional materials and in particular transition metal dichalcogenides (TMDs) have been extensively studied because of their strong light-matter interaction and the remarkable optoelectronic response of their field-effect transistors (FETs). Here, we report a photoconductivity study from FETs built from few-layers of p-WSe2 measured in a multi-terminal configuration under illumination by a 532 nm laser source. The photogenerated current was measured as a function of the incident optical power, of the drain-to-source bias and of the gate voltage. We observe a considerably larger photoconductivity when the phototransistors were measured via a four-terminal configuration when compared to a two-terminal one. For an incident laser power of 248 nW, we extract 18 A W-1 and ˜4000% for the two-terminal responsivity (R) and the concomitant external quantum efficiency (EQE) respectively, when a bias voltage V ds = 1 V and a gate voltage V bg = 10 V are applied to the sample. R and EQE are observed to increase by 370% to ˜85 A W-1 and ˜20 000% respectively, when using a four-terminal configuration. Thus, we conclude that previous reports have severely underestimated the optoelectronic response of transition metal dichalcogenides, which in fact reveals a remarkable potential for photosensing applications.

Electrical transport and low-frequency noise in chemical vapor deposited single-layer MoS2 devices.

PubMed

Sharma, Deepak; Amani, Matin; Motayed, Abhishek; Shah, Pankaj B; Birdwell, A Glen; Najmaei, Sina; Ajayan, Pulickel M; Lou, Jun; Dubey, Madan; Li, Qiliang; Davydov, Albert V

2014-04-18

We have studied temperature-dependent (77-300 K) electrical characteristics and low-frequency noise (LFN) in chemical vapor deposited (CVD) single-layer molybdenum disulfide (MoS2) based back-gated field-effect transistors (FETs). Electrical characterization and LFN measurements were conducted on MoS2 FETs with Al2O3 top-surface passivation. We also studied the effect of top-surface passivation etching on the electrical characteristics of the device. Significant decrease in channel current and transconductance was observed in these devices after the Al2O3 passivation etching. For passivated devices, the two-terminal resistance variation with temperature showed a good fit to the activation energy model, whereas for the etched devices the trend indicated a hopping transport mechanism. A significant increase in the normalized drain current noise power spectral density (PSD) was observed after the etching of the top passivation layer. The observed channel current noise was explained using a standard unified model incorporating carrier number fluctuation and correlated surface mobility fluctuation mechanisms. Detailed analysis of the gate-referred noise voltage PSD indicated the presence of different trapping states in passivated devices when compared to the etched devices. Etched devices showed weak temperature dependence of the channel current noise, whereas passivated devices exhibited near-linear temperature dependence.

Palladium Gate All Around - Hetero Dielectric -Tunnel FET based highly sensitive Hydrogen Gas Sensor

NASA Astrophysics Data System (ADS)

Madan, Jaya; Chaujar, Rishu

2016-12-01

The paper presents a novel highly sensitive Hetero-Dielectric-Gate All Around Tunneling FET (HD-GAA-TFET) based Hydrogen Gas Sensor, incorporating the advantages of band to band tunneling (BTBT) mechanism. Here, the Palladium supported silicon dioxide is used as a sensing media and sensing relies on the interaction of hydrogen with Palladium-SiO2-Si. The high surface to volume ratio in the case of cylindrical GAA structure enhances the fortuities for surface reactions between H2 gas and Pd, and thus improves the sensitivity and stability of the sensor. Behaviour of the sensor in presence of hydrogen and at elevated temperatures is discussed. The conduction path of the sensor which is dependent on sensors radius has also been varied for the optimized sensitivity and static performance analysis of the sensor where the proposed design exhibits a superior performance in terms of threshold voltage, subthreshold swing, and band to band tunneling rate. Stability of the sensor with respect to temperature affectability has also been studied, and it is found that the device is reasonably stable and highly sensitive over the bearable temperature range. The successful utilization of HD-GAA-TFET in gas sensors may open a new door for the development of novel nanostructure gas sensing devices.

XPS-XRF hybrid metrology enabling FDSOI process

NASA Astrophysics Data System (ADS)

Hossain, Mainul; Subramanian, Ganesh; Triyoso, Dina; Wahl, Jeremy; Mcardle, Timothy; Vaid, Alok; Bello, A. F.; Lee, Wei Ti; Klare, Mark; Kwan, Michael; Pois, Heath; Wang, Ying; Larson, Tom

2016-03-01

Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO2) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.

Interaction of Black Phosphorus with Oxygen and Water

DOE PAGES

Huang, Yuan; Qiao, Jingsi; He, Kai; ...

2016-10-24

Black phosphorus (BP) has attracted significant interest as a monolayer or few-layer material with extraordinary electrical and optoelectronic properties. Chemical reactions with different ambient species, notably oxygen and water, are important as they govern key properties such as stability in air, electronic structure and charge transport, wetting by aqueous solutions, etc. Here, we report experiments combined with ab-initio calculations that address the effects of oxygen and water in contact with BP. Our results show that the reaction with oxygen is primarily responsible for changing properties of BP. Oxidation involving the dissociative chemisorption of O 2 causes the decomposition of BPmore » and continuously lowers the conductance of BP field-effect transistors (FETs). In contrast, BP is stable in contact with deaerated (i.e., O 2 depleted) water and the carrier mobility in BP FETs gated by H 2O increases significantly due to efficient dielectric screening of scattering centers by the high-k dielectric. Isotope labeling experiments, contact angle measurements and calculations show that the pristine BP surface is hydrophobic, but is turned progressively hydrophilic by oxidation. Lastly, our results open new avenues for exploring applications that require contact of BP with aqueous solutions including solution gating, electrochemistry, and solution-phase approaches for exfoliation, dispersion, and delivery of BP.« less

Piezoelectric coupling in a field-effect transistor with a nanohybrid channel of ZnO nanorods grown vertically on graphene.

PubMed

Quang Dang, Vinh; Kim, Do-Il; Thai Duy, Le; Kim, Bo-Yeong; Hwang, Byeong-Ung; Jang, Mi; Shin, Kyung-Sik; Kim, Sang-Woo; Lee, Nae-Eung

2014-12-21

Piezoelectric coupling phenomena in a graphene field-effect transistor (GFET) with a nano-hybrid channel of chemical-vapor-deposited Gr (CVD Gr) and vertically aligned ZnO nanorods (NRs) under mechanical pressurization were investigated. Transfer characteristics of the hybrid channel GFET clearly indicated that the piezoelectric effect of ZnO NRs under static or dynamic pressure modulated the channel conductivity (σ) and caused a positive shift of 0.25% per kPa in the Dirac point. However, the GFET without ZnO NRs showed no change in either σ or the Dirac point. Analysis of the Dirac point shifts indicated transfer of electrons from the CVD Gr to ZnO NRs due to modulation of their interfacial barrier height under pressure. High responsiveness of the hybrid channel device with fast response and recovery times was evident in the time-dependent behavior at a small gate bias. In addition, the hybrid channel FET could be gated by mechanical pressurization only. Therefore, a piezoelectric-coupled hybrid channel GFET can be used as a pressure-sensing device with low power consumption and a fast response time. Hybridization of piezoelectric 1D nanomaterials with a 2D semiconducting channel in FETs enables a new design for future nanodevices.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Maximizing the value of gate capacitance in field-effect devices using an organic interface layer

NASA Astrophysics Data System (ADS)

Kwok, H. L.

2015-12-01

Past research has confirmed the existence of negative capacitance in organics such as tris (8-Hydroxyquinoline) Aluminum (Alq3). This work explored using such an organic interface layer to enhance the channel voltage in the field-effect transistor (FET) thereby lowering the sub-threshold swing. In particular, if the values of the positive and negative gate capacitances are approximately equal, the composite negative capacitance will increase by orders of magnitude. One concern is the upper frequency limit (∼100 Hz) over which negative capacitance has been observed. Nonetheless, this frequency limit can be raised to kHz when the organic layer is subjected to a DC bias.

Bias temperature instability in tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Mizubayashi, Wataru; Mori, Takahiro; Fukuda, Koichi; Ishikawa, Yuki; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Matsukawa, Takashi; Masahara, Meishoku; Endo, Kazuhiko

2017-04-01

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal-oxide-semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Phosphorous doped p-type MoS2 polycrystalline thin films via direct sulfurization of Mo film

NASA Astrophysics Data System (ADS)

Momose, Tomohiro; Nakamura, Atsushi; Daniel, Moraru; Shimomura, Masaru

2018-02-01

We report on the successful synthesis of a p-type, substitutional doping at S-site, MoS2 thin film using Phosphorous (P) as the dopant. MoS2 thin films were directly sulfurized for molybdenum films by chemical vapor deposition technique. Undoped MoS2 film showed n-type behavior and P doped samples showed p-type behavior by Hall-effect measurements in a van der Pauw (vdP) configuration of 10×10 mm2 area samples and showed ohmic behavior between the silver paste contacts. The donor and the acceptor concentration were detected to be ˜2.6×1015 cm-3 and ˜1.0×1019 cm-3, respectively. Hall-effect mobility was 61.7 cm2V-1s-1 for undoped and varied in the range of 15.5 ˜ 0.5 cm2V-1s-1 with P supply rate. However, the performance of field-effect transistors (FETs) declined by double Schottky barrier contacts where the region between Ni electrodes on the source/drain contact and the MoS2 back-gate cannot be depleted and behaves as a 3D material when used in transistor geometry, resulting in poor on/off ratio. Nevertheless, the FETs exhibit hole transport and the field-effect mobility showed values as high as the Hall-effect mobility, 76 cm2V-1s-1 in undoped MoS2 with p-type behavior and 43 cm2V-1s-1 for MoS2:P. Our findings provide important insights into the doping constraints for transition metal dichalcogenides.

Isolation and Identification of Post-Transcriptional Gene Silencing-Related Micro-RNAs by Functionalized Silicon Nanowire Field-effect Transistor

NASA Astrophysics Data System (ADS)

Chen, Kuan-I.; Pan, Chien-Yuan; Li, Keng-Hui; Huang, Ying-Chih; Lu, Chia-Wei; Tang, Chuan-Yi; Su, Ya-Wen; Tseng, Ling-Wei; Tseng, Kun-Chang; Lin, Chi-Yun; Chen, Chii-Dong; Lin, Shih-Shun; Chen, Yit-Tsong

2015-11-01

Many transcribed RNAs are non-coding RNAs, including microRNAs (miRNAs), which bind to complementary sequences on messenger RNAs to regulate the translation efficacy. Therefore, identifying the miRNAs expressed in cells/organisms aids in understanding genetic control in cells/organisms. In this report, we determined the binding of oligonucleotides to a receptor-modified silicon nanowire field-effect transistor (SiNW-FET) by monitoring the changes in conductance of the SiNW-FET. We first modified a SiNW-FET with a DNA probe to directly and selectively detect the complementary miRNA in cell lysates. This SiNW-FET device has 7-fold higher sensitivity than reverse transcription-quantitative polymerase chain reaction in detecting the corresponding miRNA. Next, we anchored viral p19 proteins, which bind the double-strand small RNAs (ds-sRNAs), on the SiNW-FET. By perfusing the device with synthesized ds-sRNAs of different pairing statuses, the dissociation constants revealed that the nucleotides at the 3‧-overhangs and pairings at the terminus are important for the interactions. After perfusing the total RNA mixture extracted from Nicotiana benthamiana across the device, this device could enrich the ds-sRNAs for sequence analysis. Finally, this bionanoelectronic SiNW-FET, which is able to isolate and identify the interacting protein-RNA, adds an additional tool in genomic technology for the future study of direct biomolecular interactions.

Vacuum ultraviolet radiation effects on two-dimensional MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

McMorrow, Julian J.; Cress, Cory D.; Arnold, Heather N.; Sangwan, Vinod K.; Jariwala, Deep; Schmucker, Scott W.; Marks, Tobin J.; Hersam, Mark C.

2017-02-01

Atomically thin MoS2 has generated intense interest for emerging electronics applications. Its two-dimensional nature and potential for low-power electronics are particularly appealing for space-bound electronics, motivating the need for a fundamental understanding of MoS2 electronic device response to the space radiation environment. In this letter, we quantify the response of MoS2 field-effect transistors (FETs) to vacuum ultraviolet (VUV) total ionizing dose radiation. Single-layer (SL) and multilayer (ML) MoS2 FETs are compared to identify differences that arise from thickness and band structure variations. The measured evolution of the FET transport properties is leveraged to identify the nature of VUV-induced trapped charge, isolating the effects of the interface and bulk oxide dielectric. In both the SL and ML cases, oxide trapped holes compete with interface trapped electrons, exhibiting an overall shift toward negative gate bias. Raman spectroscopy shows no variation in the MoS2 signatures as a result of VUV exposure, eliminating significant crystalline damage or oxidation as possible radiation degradation mechanisms. Overall, this work presents avenues for achieving radiation-hard MoS2 devices through dielectric engineering that reduces oxide and interface trapped charge.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Electrically controlled wire-channel GaN/AlGaN transistor for terahertz plasma applications

NASA Astrophysics Data System (ADS)

Cywiński, G.; Yahniuk, I.; Kruszewski, P.; Grabowski, M.; Nowakowski-Szkudlarek, K.; Prystawko, P.; Sai, P.; Knap, W.; Simin, G. S.; Rumyantsev, S. L.

2018-03-01

We report on a design of fin-shaped channel GaN/AlGaN field-effect transistors developed for studying resonant terahertz plasma oscillations. Unlike common two dimensional FinFET transistor design, the gates were deposited only to the sides of the two dimensional electron gas channel, i.e., metal layers were not deposited on the top of the AlGaN. This side gate configuration allowed us to electrically control the conductivity of the channel by changing its width while keeping the carrier density and mobility virtually unchanged. Computer simulations and analytical model describe well the general shape of the characteristics. The side gate control of the channel width of these transistors allowed us to eliminate the so-called oblique plasma wave modes and paves the way towards future terahertz detectors and emitters using high quality factor plasma wave resonances.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics

PubMed Central

2017-01-01

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport. PMID:28084725

Extraction method of interfacial injected charges for SiC power MOSFETs

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

2018-01-01

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

High-performance all-printed amorphous oxide FETs and logics with electronically compatible electrode/ channel interface.

PubMed

Sharma, Bhupendra Kumar; Stoesser, Anna; Mondal, Sandeep Kumar; Garlapati, Suresh K; Fawey, Mohammed H; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

2018-06-12

Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially, when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/ printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/ channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/ channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO) based diffused a-IGZO/ ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS based logic circuits have also been demonstrated towards new-generation portable electronics.

Predictive of the quantum capacitance effect on the excitation of plasma waves in graphene transistors with scaling limit.

PubMed

Wang, Lin; Chen, Xiaoshuang; Hu, Yibin; Wang, Shao-Wei; Lu, Wei

2015-04-28

Plasma waves in graphene field-effect transistors (FETs) and nano-patterned graphene sheets have emerged as very promising candidates for potential terahertz and infrared applications in myriad areas including remote sensing, biomedical science, military, and many other fields with their electrical tunability and strong interaction with light. In this work, we study the excitations and propagation properties of plasma waves in nanometric graphene FETs down to the scaling limit. Due to the quantum-capacitance effect, the plasma wave exhibits strong correlation with the distribution of density of states (DOS). It is indicated that the electrically tunable plasma resonance has a power-dependent V0.8 TG relation on the gate voltage, which originates from the linear dependence of density of states (DOS) on the energy in pristine graphene, in striking difference to those dominated by classical capacitance with only V0.5 TG dependence. The results of different transistor sizes indicate the potential application of nanometric graphene FETs in highly-efficient electro-optic modulation or detection of terahertz or infrared radiation. In addition, we highlight the perspectives of plasma resonance excitation in probing the many-body interaction and quantum matter state in strong correlation electron systems. This study reveals the key feature of plasma waves in decorated/nanometric graphene FETs, and paves the way to tailor plasma band-engineering and expand its application in both terahertz and mid-infrared regions.

Graphene nanoribbon field effect transistor for nanometer-size on-chip temperature sensor

NASA Astrophysics Data System (ADS)

Banadaki, Yaser M.; Srivastava, Ashok; Sharifi, Safura

2016-04-01

Graphene has been extensively investigated as a promising material for various types of high performance sensors due to its large surface-to-volume ratio, remarkably high carrier mobility, high carrier density, high thermal conductivity, extremely high mechanical strength and high signal-to-noise ratio. The power density and the corresponding die temperature can be tremendously high in scaled emerging technology designs, urging the on-chip sensing and controlling of the generated heat in nanometer dimensions. In this paper, we have explored the feasibility of a thin oxide graphene nanoribbon (GNR) as nanometer-size temperature sensor for detecting local on-chip temperature at scaled bias voltages of emerging technology. We have introduced an analytical model for GNR FET for 22nm technology node, which incorporates both thermionic emission of high-energy carriers and band-to-band-tunneling (BTBT) of carriers from drain to channel regions together with different scattering mechanisms due to intrinsic acoustic phonons and optical phonons and line-edge roughness in narrow GNRs. The temperature coefficient of resistivity (TCR) of GNR FET-based temperature sensor shows approximately an order of magnitude higher TCR than large-area graphene FET temperature sensor by accurately choosing of GNR width and bias condition for a temperature set point. At gate bias VGS = 0.55 V, TCR maximizes at room temperature to 2.1×10-2 /K, which is also independent of GNR width, allowing the design of width-free GNR FET for room temperature sensing applications.

Dependence of mobility on shallow localized gap states in single-crystal organic field-effect-transistors

NASA Astrophysics Data System (ADS)

Butko, V. Y.; So, W.; Lang, D. V.; Chi, X.; Lashley, J. C.; Ramirez, A. P.

2009-12-01

In order to optimize the performance of molecular organic electronic devices it is important to study the intermolecular density of states and charge transport mechanisms in the environment of crystalline organic material. Using this approach in Field Effect Transistors (FETs) we show that material purification improves carrier mobility and decreases density of the deep localized electronic state. We also report a general exponential energy dependence of the density of localized states in a vicinity of the mobility edge (Fermi energies up to ∼7 times higher than the thermal energy (kT)) in a variety of the extensively purified molecular organic crystal FETs. This observation and the low activation energy of the order of ∼kT suggest that molecular structural misplacements of the sizes that are comparable with thermal molecular modes rather than impurity deep traps play a role in formation of these shallow states. We find that the charge carrier mobility in the FET nanochannels, μeff, is parameterized by two factors, the free-carrier mobility, μ0, and the ratio of the free carrier density to the total carrier density induced by gate bias. Crystalline FETs fabricated from rubrene, pentacene, and tetracene have a high free-carrier mobility, μ0∼50 cm2/Vs, at 300 K with lower device μeff dominated by localized shallow gap states. This relationship suggests that further improvements in electronic performance could be possible with enhanced device quality.

Development of Short Gate FET’s.

DTIC Science & Technology

1983-12-01

Electrical Engineering AREA OK UIT NUMBERS S School of Engineering, Howard University 61102F 2300 Sixth St. N.W. Washington D.C. 20059 2305/Cl CITROLLING... Howard University Washington# D.C. 20059 64 04 24 021 RESEARCH OBJECTIVES The principal objective of this research is to try to under- stand the... Howard University Washington, D.C. 20059 (202)636-6684 James Comas Naval Research Laboratory, Code 6823 Washington, D.C. 20375 (202)767-3097

Double-gated myocardial ASL perfusion imaging is robust to heart rate variation.

PubMed

Do, Hung Phi; Yoon, Andrew J; Fong, Michael W; Saremi, Farhood; Barr, Mark L; Nayak, Krishna S

2017-05-01

Cardiac motion is a dominant source of physiological noise (PN) in myocardial arterial spin labeled (ASL) perfusion imaging. This study investigates the sensitivity to heart rate variation (HRV) of double-gated myocardial ASL compared with the more widely used single-gated method. Double-gating and single-gating were performed on 10 healthy volunteers (n = 10, 3F/7M; age, 23-34 years) and eight heart transplant recipients (n = 8, 1F/7M; age, 26-76 years) at rest in the randomized order. Myocardial blood flow (MBF), PN, temporal signal-to-noise ratio (SNR), and HRV were measured. HRV ranged from 0.2 to 7.8 bpm. Double-gating PN did not depend on HRV, while single-gating PN increased with HRV. Over all subjects, double-gating provided a significant reduction in global PN (from 0.20 ± 0.15 to 0.11 ± 0.03 mL/g/min; P = 0.01) and per-segment PN (from 0.33 ± 0.23 to 0.21 ± 0.12 mL/g/min; P < 0.001), with significant increases in global temporal SNR (from 11 ± 8 to 18 ± 8; P = 0.02) and per-segment temporal SNR (from 7 ± 4 to 11 ± 12; P < 0.001) without significant difference in measured MBF. Single-gated myocardial ASL suffers from reduced temporal SNR, while double-gated myocardial ASL provides consistent temporal SNR independent of HRV. Magn Reson Med 77:1975-1980, 2017. © 2016 International Society for Magnetic Resonance in Medicine. © 2016 International Society for Magnetic Resonance in Medicine.

Atomic defects in monolayer WSe2 tunneling FETs studied by systematic ab initio calculations

NASA Astrophysics Data System (ADS)

Wu, Jixuan; Fan, Zhiqiang; Chen, Jiezhi; Jiang, Xiangwei

2018-05-01

Atomic defects in monolayer WSe2 tunneling FETs (TFETs) are studied through systematic ab initio calculations aiming at performance predictions and enhancements. The effects of various defect positions and different passivation atoms are characterized in WSe2 TFETs by rigorous ab initio quantum transport simulations. It is suggested that the Se vacancy (VSe) defect located in the gate-controlled channel region tends to increase the OFF current (I off), whereas it can be well suppressed by oxygen passivation. It is demonstrated that chlorine (Cl) passivation at the source-side tunneling region can largely suppress I off, leading to an impressively improved on–off ratio (I on/I off) compared with that without any defect. However, it is also observed that randomly positioned atomic defects tend to induce significant fluctuation of the TFET output. Further discussions are made with focus on the performance-variability trade-off for robust circuit design.

Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

NASA Astrophysics Data System (ADS)

Lahgere, Avinash; Panchore, Meena; Singh, Jawar

2016-08-01

In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10× improvement in on-current, 100× reduced leakage current, 3× more transconductance (gm), and on-off current ratio of ∼1011 as compared to DL-TFET.

One-Dimensional Nanostructure Field-Effect Sensors for Gas Detection

PubMed Central

Zhao, Xiaoli; Cai, Bin; Tang, Qingxin; Tong, Yanhong; Liu, Yichun

2014-01-01

Recently; one-dimensional (1D) nanostructure field-effect transistors (FETs) have attracted much attention because of their potential application in gas sensing. Micro/nanoscaled field-effect sensors combine the advantages of 1D nanostructures and the characteristic of field modulation. 1D nanostructures provide a large surface area-volume ratio; which is an outstanding advantage for gas sensors with high sensitivity and fast response. In addition; the nature of the single crystals is favorable for the studies of the response mechanism. On the other hand; one main merit of the field-effect sensors is to provide an extra gate electrode to realize the current modulation; so that the sensitivity can be dramatically enhanced by changing the conductivity when operating the sensors in the subthreshold regime. This article reviews the recent developments in the field of 1D nanostructure FET for gas detection. The sensor configuration; the performance as well as their sensing mechanism are evaluated. PMID:25090418

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

NASA Astrophysics Data System (ADS)

Greene, Andrew M.

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1,500 and sub-threshold swing = 340 mV/dec. Split C-V measurements were used to extract an effective channel mobility of muh* = 300 cm2/Vs at Ns = 2 x 1012 cm -2. "Gate-last" MOSFETs grown with an epitaxial p + contact layer were fabricated using selective gate-recess etching techniques. A parasitic "n-channel" limited ION/I OFF ratio and sub-threshold swing, most likely due to effects from the InAs surface layer.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-01

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

High Speed FETs Fabricated in GaAs/AlGaAs Layered Structures Prepared by Molecular Beam Epitaxy.

DTIC Science & Technology

1984-01-01

but proper measures, such as improved ohmic con - tacts, metal conductors and small geometrics are useful. In digital circuit applications in addition to...heterointerface encounter reduced scattering by ionized donors located in AlGaAs layer, the current con - ducting channel must be parallel to the...ments apply to the velocity saturated MOSFET as well. For the MESFET, in con - trast, the transconductance increases with increasing gate biases, since

The Present State of Amperometric Nanowire Sensors for Chemical and Biological Detection

DTIC Science & Technology

2006-10-01

reported for a multi(nano)wire carbon monoxide 6 sensor (17). A single gallium oxide nanowire ethanol sensor with a 2.5 second response time has also...Covington, J. A.; Gardner, J. W.; Bartlett, P. N.; Toh, C-S. Conductive polymer gate FET devices for vapour sensing. IEE Proceedings - Circuits...detecting organic vapours . Sensors and Actuators B 2001, 77 (1–2), 155–162. 48. Malliaras G.; Friend, R. An organic electronics primer. Physics

A novel micromixer based on the alternating current-flow field effect transistor.

PubMed

Wu, Yupan; Ren, Yukun; Tao, Ye; Hou, Likai; Hu, Qingming; Jiang, Hongyuan

2016-12-20

Induced-charge electroosmosis (ICEO) phenomena have been attracting considerable attention as a means for pumping and mixing in microfluidic systems with the advantage of simple structures and low-energy consumption. We propose the first effort to exploit a fixed-potential ICEO flow around a floating electrode for microfluidic mixing. In analogy with the field effect transistor (FET) in microelectronics, the floating electrode act as a "gate" electrode for generating asymmetric ICEO flow and thus the device is called an AC-flow FET (AC-FFET). We take advantage of a tandem electrode configuration containing two biased center metal strips arranged in sequence at the bottom of the channel to generate asymmetric vortexes. The current device is manufactured on low-cost glass substrates via an easy and reliable process. Mixing experiments were conducted in the proposed device and the comparison between simulation and experimental results was also carried out, which indicates that the micromixer permits an efficient mixing effect. The mixing performance can be further enhanced by the application of a suitable phase difference between the driving electrode and the gate electrode or a square wave signal. Finally, we performed a critical analysis of the proposed micromixer in comparison with different mixer designs using a comparative mixing index (CMI). The novel methods put forward here offer a simple solution to mixing issues in microfluidic systems.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistors

NASA Technical Reports Server (NTRS)

Yamada, Toshishige; Biegel, Bryan (Technical Monitor)

2002-01-01

The threshold voltages of a carbon nanotube (CNT) field-effect transistor (FET) are derived and compared with those of the metal oxide-semiconductor (MOS) FETs. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, which is the CNT diameter direction, and this makes the CNTFET characteristics quite different from those in MOSFETs. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and it is shown that the familiar relations are still valid because of the macroscopic number of states available in the CNTs. This is in sharp contrast to the cases of quantum dots. Using these relations, we derive an inversion threshold voltage V(sub Ti) and an accumulation threshold voltage V(sub Ta) as a function of the Fermi level E(sub F) in the channel, where E(sub F) is a measure of channel doping. V(sub Ti) of the CNTFETs has a much stronger dependence than that of MOSFETs, while V(sub Ta)s of both CNTFETs and MOSFETs depend quite weakly on E(sub F) with the same functional form. This means the transition from normally-off mode to normally-on mode is much sharper in CNTFETs as the doping increases, and this property has to be taken into account in circuit design.

Electroluminescence and other diagnostic techniques for the study of hot-electron effects in compound semiconductor devices

NASA Astrophysics Data System (ADS)

Zanoni, Enrico; Meneghesso, Gaudenzio; Menozzi, Roberto

2000-03-01

Hot electron in III-V FETs can be indirectly monitored by measuring the current coming out from the gate when the device is biased at high electric fields. This negative current is due to the collection of holes generated by impact ionization in the gate-to drain region. Electroluminescence represents a powerful tool in order to characterize not only hot electrons but also material properties. By using spatially resolved emission microscopy it is possible to show that the light due to cold electron/hole recombination is emitted between the gate and the source (low electric field region), while the contribution due to hot electrons is emitted between the gate and the drain (high electric field region). Deep-traps created in the device by hot carriers can be analysed by means of drain current deep level transient spectroscopy and by transconductance frequency dispersion. Cathodoluminescence, optical beam induced current, X-ray spectroscopy, electron energy loss spectroscopy in combination with a transmission electron microscopy are powerful tools in order to identify and localize surface modification following hot-electron stress tests.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

NASA Astrophysics Data System (ADS)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

Hexagonal MoTe2 with Amorphous BN Passivation Layer for Improved Oxidation Resistance and Endurance of 2D Field Effect Transistors.

PubMed

Sirota, Benjamin; Glavin, Nicholas; Krylyuk, Sergiy; Davydov, Albert V; Voevodin, Andrey A

2018-06-06

Environmental and thermal stability of two-dimensional (2D) transition metal dichalcogenides (TMDs) remains a fundamental challenge towards enabling robust electronic devices. Few-layer 2H-MoTe 2 with an amorphous boron nitride (a-BN) covering layer was synthesized as a channel for back-gated field effect transistors (FET) and compared to uncovered MoTe 2 . A systematic approach was taken to understand the effects of heat treatment in air on the performance of FET devices. Atmospheric oxygen was shown to negatively affect uncoated MoTe 2 devices while BN-covered FETs showed considerably enhanced chemical and electronic characteristic stability. Uncapped MoTe 2 FET devices, which were heated in air for one minute, showed a polarity switch from n- to p-type at 150 °C, while BN-MoTe 2 devices switched only after 200 °C of heat treatment. Time-dependent experiments at 100 °C showed that uncapped MoTe 2 samples exhibited the polarity switch after 15 min of heat treatment while the BN-capped device maintained its n-type conductivity for the maximum 60 min duration of the experiment. X-ray photoelectron spectroscopy (XPS) analysis suggests that oxygen incorporation into MoTe 2 was the primary doping mechanism for the polarity switch. This work demonstrates the effectiveness of an a-BN capping layer in preserving few-layer MoTe 2 material quality and controlling its conductivity type at elevated temperatures in an atmospheric environment.

Simple and robust strategy for potentiometric detection of glucose using fluorinated phenylboronic acid self-assembled monolayer.

PubMed

Matsumoto, Akira; Matsumoto, Hiroko; Maeda, Yasuhiro; Miyahara, Yuji

2013-09-01

Field effect transistor (FET) based signal-transduction (Bio-FET) is an emerging technique for label-free and real-time basis biosensors for a wide range of targets. Glucose has constantly been of interest due to its clinical relevance. Use of glucose oxidase (GOD) and a lectin protein Concanavalin A are two common strategies to generate glucose-dependent electrochemical events. However, these protein-based materials are intolerant of long-term usage and storage due to their inevitable denaturing. A phenylboronic acid (PBA) modified self-assembled monolayer (SAM) on a gold electrode with an optimized disassociation constant of PBA, that is, 3-fluoro-4-carbamoyl-PBA possessing its pKa of 7.1, was prepared and utilized as an extended gate electrode for Bio-FET. The prepared electrode showed a glucose-dependent change in the surface potential under physiological conditions, thus providing a remarkably simple rationale for the glyco-sensitive Bio-FET. Importantly, the PBA modified electrode showed tolerance to relatively severe heat and drying treatments; conditions under which protein based materials would surely be denatured. A PBA modified SAM with optimized disassociation constant (pKa) can exhibit a glucose-dependent change in the surface potential under physiological conditions, providing a remarkably simple but robust method for the glyco-sensing. This protein-free, totally synthetic glyco-sensing strategy may offer cheap, robust and easily accessible platform that may be useful in developing countries. This article is part of a Special Issue entitled Organic Bioelectronics-Novel Applications in Biomedicine. Copyright © 2013 Elsevier B.V. All rights reserved.

Characterization of Graphene-based FET Fabricated using a Shadow Mask

PubMed Central

Tien, Dung Hoang; Park, Jun-Young; Kim, Ki Buem; Lee, Naesung; Seo, Yongho

2016-01-01

To pattern electrical metal contacts, electron beam lithography or photolithography are commonly utilized, and these processes require polymer resists with solvents. During the patterning process the graphene surface is exposed to chemicals, and the residue on the graphene surface was unable to be completely removed by any method, causing the graphene layer to be contaminated. A lithography free method can overcome these residue problems. In this study, we use a micro-grid as a shadow mask to fabricate a graphene based field-effect-transistor (FET). Electrical measurements of the graphene based FET samples are carried out in air and vacuum. It is found that the Dirac peaks of the graphene devices on SiO2 or on hexagonal boron nitride (hBN) shift from a positive gate voltage region to a negative region as air pressure decreases. In particular, the Dirac peaks shift very rapidly when the pressure decreases from ~2 × 10−3 Torr to ~5 × 10−5 Torr within 5 minutes. These Dirac peak shifts are known as adsorption and desorption of environmental gases, but the shift amounts are considerably different depending on the fabrication process. The high gas sensitivity of the device fabricated by shadow mask is attributed to adsorption on the clean graphene surface. PMID:27169620

Radio Frequency Transistors and Circuits Based on CVD MoS2.

PubMed

Sanne, Atresh; Ghosh, Rudresh; Rai, Amritesh; Yogeesh, Maruthi Nagavalli; Shin, Seung Heon; Sharma, Ankit; Jarvis, Karalee; Mathew, Leo; Rao, Rajesh; Akinwande, Deji; Banerjee, Sanjay

2015-08-12

We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm(2)/(V s) was achieved. Radio frequency FETs were fabricated in the ground-signal-ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

NASA Astrophysics Data System (ADS)

Toriumi, Akira; Nishimura, Tomonori

2018-01-01

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO2/Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO2/Ge interface should be intensively studied to make the best of Ge’s advantages. Therefore we first discuss the GeO2/Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge’s intrinsic properties because they are derived from the strong Fermi-level pinning and the narrow energy band gap, respectively. Even if the carrier transport in the channel may be ideally ballistic, these properties should degrade FET properties. The narrower energy band gap of Ge is often addressed, but the higher dielectric constant of Ge is rarely discussed. This is also the case for most of the other high-mobility materials. The dielectric constant is directly and negatively related to short-channel effects, and we have not been able to provide a substantial solution to overcome this hardship. We have to keep this in mind for the short-channel FET operation. Although a number of problems remain to be solved, in this paper, we view the current status of Ge FET technology positively. A number of (but not all) Ge-related challenges have been overcome in the past 10 years, which seems to be a good time to summarize the status of Ge technology, particularly materials engineering aspects rather than device integration issues. Since we cannot cover all of the results published to date, we mainly discuss fundamental aspects based on our experimental results. Remaining challenges are also addressed but not comprehensively. Integration issues are not discussed in this review. Finally, new types of electron devices utilizing Ge’s advantages are briefly introduced on the basis of our experimental results.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

DTIC Science & Technology

2010-03-31

in OFETs have been investigated extensively in the past couple of years. They are mainly attributed to the (i) charge trapping and release in the...This sharp rise in capacitance can be attributed due to trap charges or impurities such as ions which is most likely in the bulk of DNA-CTMA as well...5 Transient response of BiOFETs As mentioned before, charge trapping and release time can be strong function of applied voltage as well as device

Comparisons of single event vulnerability of GaAs SRAMS

NASA Astrophysics Data System (ADS)

Weatherford, T. R.; Hauser, J. R.; Diehl, S. E.

1986-12-01

A GaAs MESFET/JFET model incorporated into SPICE has been used to accurately describe C-EJFET, E/D MESFET and D MESFET/resistor GaAs memory technologies. These cells have been evaluated for critical charges due to gate-to-drain and drain-to-source charge collection. Low gate-to-drain critical charges limit conventional GaAs SRAM soft error rates to approximately 1E-6 errors/bit-day. SEU hardening approaches including decoupling resistors, diodes, and FETs have been investigated. Results predict GaAs RAM cell critical charges can be increased to over 0.1 pC. Soft error rates in such hardened memories may approach 1E-7 errors/bit-day without significantly reducing memory speed. Tradeoffs between hardening level, performance and fabrication complexity are discussed.

An All-Solid-State pH Sensor Employing Fluorine-Terminated Polycrystalline Boron-Doped Diamond as a pH-Insensitive Solution-Gate Field-Effect Transistor.

PubMed

Shintani, Yukihiro; Kobayashi, Mikinori; Kawarada, Hiroshi

2017-05-05

A fluorine-terminated polycrystalline boron-doped diamond surface is successfully employed as a pH-insensitive SGFET (solution-gate field-effect transistor) for an all-solid-state pH sensor. The fluorinated polycrystalline boron-doped diamond (BDD) channel possesses a pH-insensitivity of less than 3mV/pH compared with a pH-sensitive oxygenated channel. With differential FET (field-effect transistor) sensing, a sensitivity of 27 mv/pH was obtained in the pH range of 2-10; therefore, it demonstrated excellent performance for an all-solid-state pH sensor with a pH-sensitive oxygen-terminated polycrystalline BDD SGFET and a platinum quasi-reference electrode, respectively.

The LER/LWR metrology challenge for advance process control through 3D-AFM and CD-SEM

NASA Astrophysics Data System (ADS)

Faurie, P.; Foucher, J.; Foucher, A.-L.

2009-12-01

The continuous shrinkage in dimensions of microelectronic devices has reached such level, with typical gate length in advance R&D of less than 20nm combine with the introduction of new architecture (FinFET, Double gate...) and new materials (porous interconnect material, 193 immersion resist, metal gate material, high k materials...), that new process parameters have to be well understood and well monitored to guarantee sufficient production yield in a near future. Among these parameters, there are the critical dimensions (CD) associated to the sidewall angle (SWA) values, the line edge roughness (LER) and the line width roughness (LWR). Thus, a new metrology challenge has appeared recently and consists in measuring "accurately" the fabricated patterns on wafers in addition to measure the patterns on a repeatable way. Therefore, a great effort has to be done on existing techniques like CD-SEM, Scatterometry and 3D-AFM in order to develop them following the two previous criteria: Repeatability and Accuracy. In this paper, we will compare the 3D-AFM and CD-SEM techniques as a mean to measure LER and LWR on silicon and 193 resist and point out CD-SEM impact on the material during measurement. Indeed, depending on the material type, the interaction between the electron beam and the material or between the AFM tip and the material can vary a lot and subsequently can generate measurements bias. The first results tend to show that depending on CD-SEM conditions (magnification, number of acquisition frames) the final outputs can vary on a large range and therefore show that accuracy in such measurements are really not obvious to obtain. On the basis of results obtained on various materials that present standard sidewall roughness, we will show the limit of each technique and will propose different ways to improve them in order to fulfil advance roadmap requirements for the development of the next IC generation.

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

NASA Astrophysics Data System (ADS)

Kukita, Kentaro; Uechi, Tadayoshi; Shimokawa, Junji; Goto, Masakazu; Yokota, Yoshinori; Kawanaka, Shigeru; Tanamoto, Tetsufumi; Tanimoto, Hiroyoshi; Takagi, Shinichi

2018-04-01

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= V gs = V ds) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current I on (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length L ov.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

NASA Astrophysics Data System (ADS)

Miyoshi, Tomoyuki; Oshima, Takayuki; Noguchi, Junji

2015-05-01

High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

Two-dimensional analytical model for dual-material control-gate tunnel FETs

NASA Astrophysics Data System (ADS)

Xu, Hui Fang; Dai, Yue Hua; Gui Guan, Bang; Zhang, Yong Feng

2016-09-01

An analytical model for a dual-material control-gate (DMCG) tunnel field effect transistor (TFET) is presented for the first time in this paper, and the influence of the mobile charges on the potential profile is taken into account. On the basis of the potential profile, the lateral electric field is derived and the expression for the drain current is obtained by integrating the band-to-band tunneling (BTBT) generation rate applicable to low-bandgap and high-bandgap materials over the tunneling region. The model also predicts the impacts of the control-gate work function on the potential and drain current. The advantage of this work is that it not only offers physical insight into device physics but also provides the basic designing guideline for DMCG TFETs, enabling the designer to optimize the device in terms of the on-state current, the on-off current ratio, and suppressed ambipolar behavior. Very good agreements for both the potential and drain current are observed between the model calculations and the simulated results.

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond

NASA Astrophysics Data System (ADS)

Dunn, Derren; Sporre, John R.; Deshpande, Vaibhav; Oulmane, Mohamed; Gull, Ronald; Ventzek, Peter; Ranjan, Alok

2017-03-01

Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.1 When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.2

Performance analysis of SiGe double-gate N-MOSFET

NASA Astrophysics Data System (ADS)

Singh, A.; Kapoor, D.; Sharma, R.

2017-04-01

The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET. The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool. Moreover, we have designed its structure and studied both {I}{{d}}{-}{V}{{g}} characteristics for different voltages namely 0.05, 0.1, 0.5, 0.8, 1 and 1.5 V and {I}{{d}}{-}{V}{{d}} characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-06

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool-Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (10 7 ) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian

2017-12-01

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N + pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g  = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian

2017-03-01

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Highly Sensitive Flexible Pressure Sensors Based on Printed Organic Transistors with Centro-Apically Self-Organized Organic Semiconductor Microstructures.

PubMed

Yeo, So Young; Park, Sangsik; Yi, Yeon Jin; Kim, Do Hwan; Lim, Jung Ah

2017-12-13

A highly sensitive pressure sensor based on printed organic transistors with three-dimensionally self-organized organic semiconductor microstructures (3D OSCs) was demonstrated. A unique organic transistor with semiconductor channels positioned at the highest summit of printed cylindrical microstructures was achieved simply by printing an organic semiconductor and polymer blend on the plastic substrate without the use of additional etching or replication processes. A combination of the printed organic semiconductor microstructure and an elastomeric top-gate dielectric resulted in a highly sensitive organic field-effect transistor (FET) pressure sensor with a high pressure sensitivity of 1.07 kPa -1 and a rapid response time of <20 ms with a high reliability over 1000 cycles. The flexibility and high performance of the 3D OSC FET pressure sensor were exploited in the successful application of our sensors to real-time monitoring of the radial artery pulse, which is useful for healthcare monitoring, and to touch sensing in the e-skin of a realistic prosthetic hand.

Understanding Charge Collection Mechanisms in InGaAs FinFETs Using High-Speed Pulsed-Laser Transient Testing With Tunable Wavelength

NASA Astrophysics Data System (ADS)

Ni, Kai; Sternberg, Andrew L.; Zhang, En Xia; Kozub, John A.; Jiang, Rong; Schrimpf, Ronald D.; Reed, Robert A.; Fleetwood, Daniel M.; Alles, Michael L.; McMorrow, Dale; Lin, Jianqiang; Vardi, Alon; del Alamo, Jesús

2017-08-01

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current.

Mimicking Neurotransmitter Release in Chemical Synapses via Hysteresis Engineering in MoS2 Transistors.

PubMed

Arnold, Andrew J; Razavieh, Ali; Nasr, Joseph R; Schulman, Daniel S; Eichfeld, Chad M; Das, Saptarshi

2017-03-28

Neurotransmitter release in chemical synapses is fundamental to diverse brain functions such as motor action, learning, cognition, emotion, perception, and consciousness. Moreover, improper functioning or abnormal release of neurotransmitter is associated with numerous neurological disorders such as epilepsy, sclerosis, schizophrenia, Alzheimer's disease, and Parkinson's disease. We have utilized hysteresis engineering in a back-gated MoS 2 field effect transistor (FET) in order to mimic such neurotransmitter release dynamics in chemical synapses. All three essential features, i.e., quantal, stochastic, and excitatory or inhibitory nature of neurotransmitter release, were accurately captured in our experimental demonstration. We also mimicked an important phenomenon called long-term potentiation (LTP), which forms the basis of human memory. Finally, we demonstrated how to engineer the LTP time by operating the MoS 2 FET in different regimes. Our findings could provide a critical component toward the design of next-generation smart and intelligent human-like machines and human-machine interfaces.

Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

NASA Astrophysics Data System (ADS)

Bersch, Brian M.; Eichfeld, Sarah M.; Lin, Yu-Chuan; Zhang, Kehao; Bhimanapati, Ganesh R.; Piasecki, Aleksander F.; Labella, Michael, III; Robinson, Joshua A.

2017-06-01

Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.

Robust Deterministic Controlled Phase-Flip Gate and Controlled-Not Gate Based on Atomic Ensembles Embedded in Double-Sided Optical Cavities

NASA Astrophysics Data System (ADS)

Liu, A.-Peng; Cheng, Liu-Yong; Guo, Qi; Zhang, Shou

2018-02-01

We first propose a scheme for controlled phase-flip gate between a flying photon qubit and the collective spin wave (magnon) of an atomic ensemble assisted by double-sided cavity quantum systems. Then we propose a deterministic controlled-not gate on magnon qubits with parity-check building blocks. Both the gates can be accomplished with 100% success probability in principle. Atomic ensemble is employed so that light-matter coupling is remarkably improved by collective enhancement. We assess the performance of the gates and the results show that they can be faithfully constituted with current experimental techniques.

The interplay between pH sensitivity and label-free protein detection in immunologically modified nano-scaled field-effect transistor.

PubMed

Shalev, Gil; Rosenwaks, Yossi; Levy, Ilan

2012-01-15

We present experimental results in order to establish a correlation between pH sensitivity of immunologically modified nano-scaled field-effect transistor (NS-ImmunoFET) with their sensing capacity for label-free detection. The NS-ImmunoFETs are fabricated from silicon-on-insulator (SOI) wafers and are fully-depleted with thickness of ~20 nm. The data shows that higher sensitivity to pH entails enhanced sensitivity to analyte detection. This suggests that the mechanism of analyte detection as pure electrostatic perturbation induced by antibody-analyte interaction is over simplified. The fundamental assumption, in existing models for field-effect sensing mechanism assumes that the analyte molecules do not directly interact with the surface but rather stand 'deep' in the solution and away from the dielectric surface. Recent studies clearly provide contradicting evidence demonstrating that antibodies lie down flat on the surface. These observations led us to propose that the proteins that cover the gate area intimately interact with active sites on the surface thus forming a network of interacting sites. Since sensitivity to pH is directly correlated with the amount of amphoteric sites, we witness a direct correlation between sensitivity to pH and analyte detection. The highest and lowest threshold voltage shift for a label-free and specific detection of 6.5 nM IgG were 40 mV and 2.3 mV for NS-ImmunoFETs with pH sensitivity of 35 mV/decade and 15 mV/decade, respectively. Finally, physical modeling of the NS-ImmunoFET is presented and charge of a single IgG protein at pH 6 is calculated. The obtained value is consistent with charge of IgG protein cited in literature. Copyright © 2011 Elsevier B.V. All rights reserved.

Enzyme-modified electrolyte-gated organic field-effect transistors

NASA Astrophysics Data System (ADS)

Buth, Felix; Donner, Andreas; Stutzmann, Martin; Garrido, Jose A.

2012-10-01

Organic solution-gated field-effect transistors (SGFETs) can be operated at low voltages in aqueous environments, paving the way to the use of organic semiconductors in bio-sensing applications. However, it has been shown that these devices exhibit only a rather weak sensitivity to standard electrolyte parameters such as pH and ionic strength. In order to increase the sensitivity and to add specificity towards a given analyte, the covalent attachment of functional groups and enzymes to the device surface would be desirable. In this contribution we demonstrate that enzyme modified organic SGFETs can be used for the in-situ detection of penicillin in the low μM regime. In a first step, silane molecules with amine terminal groups are grafted to α-sexithiophene-based thin film transistors. Surface characterization techniques like X-ray photoemission confirm the modification of the surface with these functional groups, which are stable in standard aqueous electrolytes. We show that the presence of surface-bound amphoteric groups (e.g. amino or carboxylic moieties) increases the pH-sensitivity of the organic SGFETs. In addition, these groups serve as anchoring sites for the attachment of the enzyme penicillinase. The resulting enzyme-FETs are used for the detection of penicillin, enabling the study of the influence of the buffer strength and the pH of the electrolyte on the enzyme kinetics. The functionalization of the organic FETs shown here can be extended to a large variety of enzymes, allowing the specific detection of different chemical and biochemical analytes.

Side-gate modulation effects on high-quality BN-Graphene-BN nanoribbon capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yang; Chen, Xiaolong; Ye, Weiguang

High-quality BN-Graphene-BN nanoribbon capacitors with double side-gates of graphene have been experimentally realized. The double side-gates can effectively modulate the electronic properties of graphene nanoribbon capacitors. By applying anti-symmetric side-gate voltages, we observed significant upward shifting and flattening of the V-shaped capacitance curve near the charge neutrality point. Symmetric side-gate voltages, however, only resulted in tilted upward shifting along the opposite direction of applied gate voltages. These modulation effects followed the behavior of graphene nanoribbons predicted theoretically for metallic side-gate modulation. The negative quantum capacitance phenomenon predicted by numerical simulations for graphene nanoribbons modulated by graphene side-gates was not observed,more » possibly due to the weakened interactions between the graphene nanoribbon and side-gate electrodes caused by the Ga{sup +} beam etching process.« less

Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

NASA Astrophysics Data System (ADS)

Madan, Jaya; Chaujar, Rishu

2017-02-01

This work integrates the merits of gate-drain underlapping (GDU) and N+ source pocket on cylindrical gate all around tunnel FET (GAA-TFET) to form GDU-PNIN-GAA-TFET. It is analysed that the source pocket located at the source-channel junction narrows the tunneling barrier width at the tunneling junction and thereby enhances the ON-state current of GAA-TFET. Further, it is obtained that the GDU resists the extension of carrier density (built-up under the gated region) towards the drain side (under the underlapped length), thereby suppressing the ambipolar current and reducing the parasitic capacitances of GAA-TFET. Consequently, the amalgamated merits of both engineering schemes are obtained in GDU-PNIN-GAA-TFET that thus conquers the greatest challenges faced by TFET. Thus, GDU-PNIN-GAA-TFET results in an up-gradation in the overall performance of GAA-TFET. Moreover, it is realised that the RF figure of merits FOMs such as cut-off frequency (fT) and maximum oscillation frequency (fMAX) are also considerably improved with integration of source pocket on GAA-TFET. Thus, the improved analog and RF performance of GDU-PNIN-GAA-TFET makes it ideal for low power and high-speed applications.

Impedance spectroscopy with field-effect transistor arrays for the analysis of anti-cancer drug action on individual cells.

PubMed

Susloparova, A; Koppenhöfer, D; Vu, X T; Weil, M; Ingebrandt, S

2013-02-15

In this study, impedance spectroscopy measurements of silicon-based open-gate field-effect transistor (FET) devices were utilized to study the adhesion status of cancer cells at a single cell level. We developed a trans-impedance amplifier circuit for the FETs with a higher bandwidth compared to a previously described system. The new system was characterized with a fast lock-in amplifier, which enabled measuring of impedance spectra up to 50 MHz. We studied cellular activities, including cell adhesion and anti-cancer drug induced apoptosis of human embryonic kidney (HEK293) and human lung adenocarcinoma epithelial (H441) cells. A well-known chemotherapeutic drug, topotecan hydrochloride, was used to investigate the effect of this drug to tumor cells cultured on the FET devices. The presence of the drug resulted in a 20% change in the amplitude of the impedance spectra at 200 kHz as a result of the induced apoptosis process. Real-time impedance measurements were performed inside an incubator at a constant frequency. The experimental results can be interpreted with an equivalent electronic circuit to resolve the influence of the system parameters. The developed method could be applied for the analysis of the specificity and efficacy of novel anti-cancer drugs in cancer therapy research on a single cell level in parallelized measurements. Copyright © 2012 Elsevier B.V. All rights reserved.

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Valin, R., E-mail: r.valinferreiro@swansea.ac.uk; Martinez, A., E-mail: a.e.Martinez@swansea.ac.uk; Barker, J. R., E-mail: john.barker@glasgow.ac.uk

In this paper, we study the effect of random discrete dopants on the performance of a 6.6 nm channel length silicon FinFET. The discrete dopants have been distributed randomly in the source/drain region of the device. Due to the small dimensions of the FinFET, a quantum transport formalism based on the non-equilibrium Green's functions has been deployed. The transfer characteristics for several devices that differ in location and number of dopants have been calculated. Our results demonstrate that discrete dopants modify the effective channel length and the height of the source/drain barrier, consequently changing the channel control of the charge. Thismore » effect becomes more significant at high drain bias. As a consequence, there is a strong effect on the variability of the on-current, off-current, sub-threshold slope, and threshold voltage. Finally, we have also calculated the mean and standard deviation of these parameters to quantify their variability. The obtained results show that the variability at high drain bias is 1.75 larger than at low drain bias. However, the variability of the on-current, off-current, and sub-threshold slope remains independent of the drain bias. In addition, we have found that a large source to drain current by tunnelling current occurs at low gate bias.« less

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Recent Progress of B-Ga2O3 MOSFETs for Power Electronic Applications

DTIC Science & Technology

2017-03-20

variety of group 4 elements such as Silicon, Tin , and Germanium.[2, 9] Multiple samples will be referenced throughout the text, but it should be noted...Ga2O3 channel. Fabrication steps 2-4 are used in the standard fabrication as seen in Figure 1. Figure 8a below shows a top-down SEM image of the gated...voltage of 567V. Please see reference [11] for more information. 393 Figure 8. (a) Colored SEM image of a β-Ga2O3 finFET. (b) Transfer

Millimeter-Wave Circuit Analysis and Synthesis.

DTIC Science & Technology

1985-05-01

correct within a few percent and the resulting drain-source t.r7njnal current is usually high by approximately 10 percent. -20- Before Eqs. 5 and 9 can...typically used in arialytic FET models and is correct in the limit of long gates.1-3 With this approximation, the voltage drop across the depletion layer...carried out for two ba. c geometrica ss- ft WI sa of arbitrary thickness place-i c;c:.slc,, wi’ta -v .h each sidewall and (2) a thin Yl, s 1 te w~ith

Spin measurement in an undoped Si/SiGe double quantum dot incorporating a micromagnet

NASA Astrophysics Data System (ADS)

Wu, Xian; Ward, Daniel; Prance, Jonathan; Kim, Dohun; Shi, Zhan; Mohr, Robert; Gamble, John; Savage, Donald; Lagally, Max; Friesen, Mark; Coppersmith, Susan; Eriksson, Mark

2014-03-01

We present measurements on a double dot formed in an accumulation-mode undoped Si/SiGe heterostructure. The double dot incorporates a proximal micromagnet to generate a stable magnetic field difference between the quantum dots. The gate design incorporates two layers of gates, and the upper layer of gates is split into five different sections to decrease crosstalk between different gates. A novel pattern of the lower layer gates enhances the tunability of tunnel rates. We will describe our attempts to create a singlet-triplet qubit in this device. This work was supported in part by ARO(W911NF-12-0607), NSF(DMR-1206915), and the United States Department of Defense. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government. Now works at Lancaster University, UK.

Coupling between electrolyte and organic semiconductor in electrolyte-gated organic field effect transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Biscarini, Fabio; Di Lauro, Michele; Berto, Marcello; Bortolotti, Carlo A.; Geerts, Yves H.; Vuillaume, Dominique

2016-11-01

Organic field effect transistors (OFET) operated in aqueous environments are emerging as ultra-sensitive biosensors and transducers of electrical and electrochemical signals from a biological environment. Their applications range from detection of biomarkers in bodily fluids to implants for bidirectional communication with the central nervous system. They can be used in diagnostics, advanced treatments and theranostics. Several OFET layouts have been demonstrated to be effective in aqueous operations, which are distinguished either by their architecture or by the respective mechanism of doping by the ions in the electrolyte solution. In this work we discuss the unification of the seemingly different architectures, such as electrolyte-gated OFET (EGOFET), organic electrochemical transistor (OECT) and dual-gate ion-sensing FET. We first demonstrate that these architectures give rise to the frequency-dependent response of a synapstor (synapse-like transistor), with enhanced or depressed modulation of the output current depending on the frequency of the time-dependent gate voltage. This behavior that was reported for OFETs with embedded metal nanoparticles shows the existence of a capacitive coupling through an equivalent network of RC elements. Upon the systematic change of ions in the electrolyte and the morphology of the charge transport layer, we show how the time scale of the synapstor is changed. We finally show how the substrate plays effectively the role of a second bottom gate, whose potential is actually fixed by the pH/composition of the electrolyte and the gate voltage applied.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Field-effect sensors - from pH sensing to biosensing: sensitivity enhancement using streptavidin-biotin as a model system.

PubMed

Lowe, Benjamin M; Sun, Kai; Zeimpekis, Ioannis; Skylaris, Chris-Kriton; Green, Nicolas G

2017-11-06

Field-Effect Transistor sensors (FET-sensors) have been receiving increasing attention for biomolecular sensing over the last two decades due to their potential for ultra-high sensitivity sensing, label-free operation, cost reduction and miniaturisation. Whilst the commercial application of FET-sensors in pH sensing has been realised, their commercial application in biomolecular sensing (termed BioFETs) is hindered by poor understanding of how to optimise device design for highly reproducible operation and high sensitivity. In part, these problems stem from the highly interdisciplinary nature of the problems encountered in this field, in which knowledge of biomolecular-binding kinetics, surface chemistry, electrical double layer physics and electrical engineering is required. In this work, a quantitative analysis and critical review has been performed comparing literature FET-sensor data for pH-sensing with data for sensing of biomolecular streptavidin binding to surface-bound biotin systems. The aim is to provide the first systematic, quantitative comparison of BioFET results for a single biomolecular analyte, specifically streptavidin, which is the most commonly used model protein in biosensing experiments, and often used as an initial proof-of-concept for new biosensor designs. This novel quantitative and comparative analysis of the surface potential behaviour of a range of devices demonstrated a strong contrast between the trends observed in pH-sensing and those in biomolecule-sensing. Potential explanations are discussed in detail and surface-chemistry optimisation is shown to be a vital component in sensitivity-enhancement. Factors which can influence the response, yet which have not always been fully appreciated, are explored and practical suggestions are provided on how to improve experimental design.

Phase transition transistors based on strongly-correlated materials

NASA Astrophysics Data System (ADS)

Nakano, Masaki

2013-03-01

The field-effect transistor (FET) provides electrical switching functions through linear control of the number of charges at a channel surface by external voltage. Controlling electronic phases of condensed matters in a FET geometry has long been a central issue of physical science. In particular, FET based on a strongly correlated material, namely ``Mott transistor,'' has attracted considerable interest, because it potentially provides gigantic and diverse electronic responses due to a strong interplay between charge, spin, orbital and lattice. We have investigated electric-field effects on such materials aiming at novel physical phenomena and electronic functions originating from strong correlation effects. Here we demonstrate electrical switching of bulk state of matter over the first-order metal-insulator transition. We fabricated FETs based on VO2 with use of a recently developed electric-double-layer transistor technique, and found that the electrostatically induced carriers at a channel surface drive all preexisting localized carriers of 1022 cm-3 even inside a bulk to motion, leading to bulk carrier delocalization beyond the electrostatic screening length. This non-local switching of bulk phases is achieved with just around 1 V, and moreover, a novel non-volatile memory like character emerges in a voltage-sweep measurement. These observations are apparently distinct from those of conventional FETs based on band insulators, capturing the essential feature of collective interactions in strongly correlated materials. This work was done in collaboration with K. Shibuya, D. Okuyama, T. Hatano, S. Ono, M. Kawasaki, Y. Iwasa, and Y. Tokura. This work was supported by the Japan Society for the Promotion of Science (JSAP) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Current switching ratio optimization using dual pocket doping engineering

NASA Astrophysics Data System (ADS)

Dash, Sidhartha; Sahoo, Girija Shankar; Mishra, Guru Prasad

2018-01-01

This paper presents a smart idea to maximize current switching ratio of cylindrical gate tunnel FET (CGT) by growing pocket layers in both source and channel region. The pocket layers positioned in the source and channel of the device provides significant improvement in ON-state and OFF-state current respectively. The dual pocket doped cylindrical gate TFET (DP-CGT) exhibits much superior performance in term of drain current, transconductance and current ratio as compared to conventional CGT, channel pocket doped CGT (CP-CGT) and source pocket doped CGT (SP-CGT). Further, the current ratio has been optimized w.r.t. width and instantaneous position both the pocket layers. The much improved current ratio and low power consumption makes the proposed device suitable for low-power and high speed application. The simulation work of DP-CGT is done using 3D Sentaurus TCAD device simulator from Synopsys.

Gate tunable parallel double quantum dots in InAs double-nanowire devices

NASA Astrophysics Data System (ADS)

Baba, S.; Matsuo, S.; Kamata, H.; Deacon, R. S.; Oiwa, A.; Li, K.; Jeppesen, S.; Samuelson, L.; Xu, H. Q.; Tarucha, S.

2017-12-01

We report fabrication and characterization of InAs nanowire devices with two closely placed parallel nanowires. The fabrication process we develop includes selective deposition of the nanowires with micron scale alignment onto predefined finger bottom gates using a polymer transfer technique. By tuning the double nanowire with the finger bottom gates, we observed the formation of parallel double quantum dots with one quantum dot in each nanowire bound by the normal metal contact edges. We report the gate tunability of the charge states in individual dots as well as the inter-dot electrostatic coupling. In addition, we fabricate a device with separate normal metal contacts and a common superconducting contact to the two parallel wires and confirm the dot formation in each wire from comparison of the transport properties and a superconducting proximity gap feature for the respective wires. With the fabrication techniques established in this study, devices can be realized for more advanced experiments on Cooper-pair splitting, generation of Parafermions, and so on.

Human T cells monitored by impedance spectrometry using field-effect transistor arrays: a novel tool for single-cell adhesion and migration studies.

PubMed

Law, Jessica Ka Yan; Susloparova, Anna; Vu, Xuan Thang; Zhou, Xiao; Hempel, Felix; Qu, Bin; Hoth, Markus; Ingebrandt, Sven

2015-05-15

Cytotoxic T lymphocytes (CTLs) play an important role in the immune system by recognizing and eliminating pathogen-infected and tumorigenic cells. In order to achieve their function, T cells have to migrate throughout the whole body and identify the respective targets. In conventional immunology studies, interactions between CTLs and targets are usually investigated using tedious and time-consuming immunofluorescence imaging. However, there is currently no straightforward measurement tool available to examine the interaction strengths. In the present study, adhesion strengths and migration of single human CD8(+) T cells on pre-coated field-effect transistor (FET) devices (i.e. fibronectin, anti-CD3 antibody, and anti-LFA-1 antibody) were measured using impedance spectroscopy. Adhesion strengths to different protein and antibody coatings were compared. By fitting the data to an electronically equivalent circuit model, cell-related parameters (cell membrane capacitance referring to cell morphology and seal resistance referring to adhesion strength) were obtained. This electronically-assessed adhesion strength provides a novel, fast, and important index describing the interaction efficiency. Furthermore, the size of our detection transistor gates as well as their sensitivity reaches down to single cell resolution. Real-time motions of individually migrating T cells can be traced using our FET devices. The in-house fabricated FETs used in the present study are providing a novel and very efficient insight to individual cell interactions. Copyright © 2014 Elsevier B.V. All rights reserved.

Single-event Effect Report for EPC Series eGaN FETs: Proton Testing for SEE and TNID Effects

NASA Technical Reports Server (NTRS)

Scheick, Leif

2014-01-01

Previous testing of the Enhanced Power Conversion (EPC) eGaN FETs showed sensitivity to destructive single-event effects (SEE) effects to heavy ions. The presence of tungsten plugs in the gate area raises concerns that the device may be vulnerable to SEE from protons. Irradiation of biased and unbiased devices with heavy ion has results in some damage suspected of being due to total non-ionizing dose (TNID). Proton irradiation is a better radiation type to study this effect. This study presents the results of testing device with protons for SEE and TNID. No SEE in the EPC2012 device, the most sensitive device to SEE, were seen with 53 MeV protons at several angles. The devices continued to function after 1.5 Mrad (Si) of proton dose with only a slight shift in parameters. These results suggest that gross TNID will not be a factor in using these devices nor suffer from SEE due to protons. However, the device should be tested at with 500 MeV protons to guarantee to immunity proton SEE.

Radiation Failures in Intel 14nm Microprocessors

NASA Technical Reports Server (NTRS)

Bossev, Dobrin P.; Duncan, Adam R.; Gadlage, Matthew J.; Roach, Austin H.; Kay, Matthew J.; Szabo, Carl; Berger, Tammy J.; York, Darin A.; Williams, Aaron; LaBel, K.;

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Electronic Biosensing with Functionalized rGO FETs

PubMed Central

Reiner-Rozman, Ciril; Kotlowski, Caroline; Knoll, Wolfgang

2016-01-01

In the following we give a short summary of examples for biosensor concepts in areas in which reduced graphene oxide-based electronic devices can be developed into new classes of biosensors, which are highly sensitive, label-free, disposable and cheap, with electronic signals that are easy to analyze and interpret, suitable for multiplexed operation and for remote control, compatible with NFC technology, etc., and in many cases a clear and promising alternative to optical sensors. The presented areas concern sensing challenges in medical diagnostics with an example for detecting general antibody-antigen interactions, for the monitoring of toxins and pathogens in food and feed stuff, exemplified by the detection of aflatoxins, and the area of smell sensors, which are certainly the most exciting development as there are very few existing examples in which the typically small and hydrophobic odorant molecules can be detected by other means. The example given here concerns the recording of a honey flavor (and a cancer marker for neuroblastoma), homovanillic acid, by the odorant binding protein OBP 14 from the honey bee, immobilized on the reduced graphene oxide gate of an FET sensor. PMID:27110828

Interplay of Nanoscale, Hybrid P3HT/ZTO Interface on Optoelectronics and Photovoltaic Cells.

PubMed

Lai, Jian-Jhong; Li, Yu-Hsun; Feng, Bo-Rui; Tang, Shiow-Jing; Jian, Wen-Bin; Fu, Chuan-Min; Chen, Jiun-Tai; Wang, Xu; Lee, Pooi See

2017-09-27

Photovoltaic effects in poly(3-hexylthiophene-2,5-diyl) (P3HT) have attracted much attention recently. Here, natively p-type doped P3HT nanofibers and n-type doped zinc tin oxide (ZTO) nanowires are used for making not only field-effect transistors (FETs) but also p-n nanoscale diodes. The hybrid P3HT/ZTO p-n heterojunction shows applications in many directions, and it also facilitates the investigation of photoelectrons and photovoltaic effects on the nanoscale. As for applications, the heterojunction device shows a simultaneously high on/off ratio of n- and p-type FETs, gatable p-n junction diodes, tristate buffer devices, gatable photodetectors, and gatable solar cells. On the other hand, P3HT nanofibers are taken as a photoactive layer and the role played by the p-n heterojunction in the photoelectric and photovoltaic effects is investigated. It is found that the hybrid P3HT/ZTO p-n heterojunction assists in increasing photocurrents and enhancing photovoltaic effects. Through the controllable gating of the heterojunction, we can discuss the background mechanisms of photocurrent generation and photovoltaic energy harvesting.

Electronic Biosensing with Functionalized rGO FETs.

PubMed

Reiner-Rozman, Ciril; Kotlowski, Caroline; Knoll, Wolfgang

2016-04-22

In the following we give a short summary of examples for biosensor concepts in areas in which reduced graphene oxide-based electronic devices can be developed into new classes of biosensors, which are highly sensitive, label-free, disposable and cheap, with electronic signals that are easy to analyze and interpret, suitable for multiplexed operation and for remote control, compatible with NFC technology, etc., and in many cases a clear and promising alternative to optical sensors. The presented areas concern sensing challenges in medical diagnostics with an example for detecting general antibody-antigen interactions, for the monitoring of toxins and pathogens in food and feed stuff, exemplified by the detection of aflatoxins, and the area of smell sensors, which are certainly the most exciting development as there are very few existing examples in which the typically small and hydrophobic odorant molecules can be detected by other means. The example given here concerns the recording of a honey flavor (and a cancer marker for neuroblastoma), homovanillic acid, by the odorant binding protein OBP 14 from the honey bee, immobilized on the reduced graphene oxide gate of an FET sensor.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Multiple and configurable optical logic systems based on layered double hydroxides and chromophore assemblies.

PubMed

Shi, Wenying; Fu, Yi; Li, Zhixiong; Wei, Min

2015-01-14

Multiple and configurable fluorescence logic gates were fabricated via self-assembly of layered double hydroxides and various chromophores. These logic gates were operated by observation of different emissions with the same excitation wavelength, which achieve YES, NOT, AND, INH and INHIBIT logic operations, respectively.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

AlGaN Channel Transistors for Power Management and Distribution

NASA Technical Reports Server (NTRS)

VanHove, James M.

1996-01-01

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

Electrical characterization of organic thin film transistors and alternative device architectures

NASA Astrophysics Data System (ADS)

Newman, Christopher R.

In the last 10--15 years, organic semiconductors have evolved from experimental curiosities into viable alternatives for practical applications involving large-area and low-cost electronics such as display backplanes, electronic paper, radio frequency identification (RFID) tags, and solar cells. Many of the initially-stated goals in this field have been achieved; organic semconductors have demonstrated performance comparable to or greater than amorphous silicon (a-Si), the entrenched technology for most of the applications listed above. At present, the major obstacles remaining to commercialization of devices based on organic semiconductors involve material stability, processing considerations and optimization of the other device components (e.g. metal contacts and dielectric materials). Despite these technical achievements, significant gaps remain in our understanding of the underlying transport physics in these devices. This thesis summarizes experiments performed on organic field-effect transistors (OFETs) in an attempt to address some of these knowledge gaps. The FET, in addition to being a very useful device for practical applications (such as the driving elements in pixel backplanes), is also a very flexible architecture from an experimental standpoint. The presence of a capacitively-coupled gate electrode allows the investigation of transport physics as a function of carrier concentration. For devices in which non-idealities (i.e. carrier traps) largely dictate the observed characteristics, this is a very useful feature. Although practical OFETs are fabricated as conventional single-gate structures on an organic thin film (OTFTs), more exotic structures can often provide insights that standard OTFTs cannot. Specifically, single-crystal OFETs allow the investigation of carrier transport in the absence of grain boundaries, and double-gated OTFTs facilitate the investigation and comparison of properties across two discrete interfaces. One of the remaining challenges in terms of achieving stability inorganic semiconductors involves understanding, and hopefully minimizing, the bias stress effect of operating OTFTs. Largely ignored during the years in which research groups sought to optimize the standard device metrics of field-effect mobility, current on/off ratio, and threshold voltage, operational stability is emerging as a dominant consideration in these materials. Experiments performed with the goal of quantifying and understanding the bias-stress effect in organic semiconductors are described at the end of this thesis.

Pulse-Driven Capacitive Lead Ion Detection with Reduced Graphene Oxide Field-Effect Transistor Integrated with an Analyzing Device for Rapid Water Quality Monitoring.

PubMed

Maity, Arnab; Sui, Xiaoyu; Tarman, Chad R; Pu, Haihui; Chang, Jingbo; Zhou, Guihua; Ren, Ren; Mao, Shun; Chen, Junhong

2017-11-22

Rapid and real-time detection of heavy metals in water with a portable microsystem is a growing demand in the field of environmental monitoring, food safety, and future cyber-physical infrastructure. Here, we report a novel ultrasensitive pulse-driven capacitance-based lead ion sensor using self-assembled graphene oxide (GO) monolayer deposition strategy to recognize the heavy metal ions in water. The overall field-effect transistor (FET) structure consists of a thermally reduced graphene oxide (rGO) channel with a thin layer of Al 2 O 3 passivation as a top gate combined with sputtered gold nanoparticles that link with the glutathione (GSH) probe to attract Pb 2+ ions in water. Using a preprogrammed microcontroller, chemo-capacitance based detection of lead ions has been demonstrated with this FET sensor. With a rapid response (∼1-2 s) and negligible signal drift, a limit of detection (LOD) < 1 ppb and excellent selectivity (with a sensitivity to lead ions 1 order of magnitude higher than that of interfering ions) can be achieved for Pb 2+ measurements. The overall assay time (∼10 s) for background water stabilization followed by lead ion testing and calculation is much shorter than common FET resistance/current measurements (∼minutes) and other conventional methods, such as optical and inductively coupled plasma methods (∼hours). An approximate linear operational range (5-20 ppb) around 15 ppb (the maximum contaminant limit by US Environmental Protection Agency (EPA) for lead in drinking water) makes it especially suitable for drinking water quality monitoring. The validity of the pulse method is confirmed by quantifying Pb 2+ in various real water samples such as tap, lake, and river water with an accuracy ∼75%. This capacitance measurement strategy is promising and can be readily extended to various FET-based sensor devices for other targets.

The low threshold voltage n-type silicon transistors based on a polymer/silica nanocomposite gate dielectric: The effect of annealing temperatures on their operation

NASA Astrophysics Data System (ADS)

Hashemi, Adeleh; Bahari, Ali; Ghasemi, Shahram

2017-09-01

In this work, povidone/silica nanocomposite dielectric layers were deposited on the n-type Si (100) substrates for application in n-type silicon field-effect transistors (FET). Thermogravimetric analysis (TGA) indicated that strong chemical interactions between polymer and silica nanoparticles were created. In order to examine the effect of annealing temperatures on chemical interactions and nanostructure properties, annealing process was done at 423-513 K. Atomic force microscopy (AFM) images show the very smooth surfaces with very low surface roughness (0.038-0.088 nm). The Si2p and C1s core level photoemission spectra were deconvoluted to the chemical environments of Si and C atoms respectively. The obtained results of deconvoluted X-ray photoelectron spectroscopy (XPS) spectra revealed a high percentage of silanol hydrogen bonds in the sample which was not annealed. These bonds were inversed to stronger covalence bonds (siloxan bonds) at annealing temperature of 423 K. By further addition of temperature, siloxan bonds were shifted to lower binding energy of about 1 eV and their intensity were abated at annealing temperature of 513 K. The electrical characteristics were extracted from current-Voltage (I-V) and capacitance-voltage (C-V) measurements in metal-insulator-semiconductor (MIS) structure. The all n-type Si transistors showed very low threshold voltages (-0.24 to 1 V). The formation of the strongest cross-linking at nanostructure of dielectric film annealed at 423 K caused resulted in an un-trapped path for the transport of charge carriers yielding the lowest threshold voltage (0.08 V) and the highest electron mobility (45.01 cm2/V s) for its FET. By increasing the annealing temperature (473 and 513 K) on the nanocomposite dielectric films, the values of the average surface roughness, the capacitance and the FET threshold voltage increased and the value of FET electron field-effect mobility decreased.

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Razavi, S. M.; Ebrahim Hosseini, Seyed; Amini Moghadam, Hamid

2011-11-01

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

The Yfe and Feo transporters are involved in microaerobic growth and virulence of Yersinia pestis in bubonic plague.

PubMed

Fetherston, Jacqueline D; Mier, Ildefonso; Truszczynska, Helena; Perry, Robert D

2012-11-01

The Yfe/Sit and Feo transport systems are important for the growth of a variety of bacteria. In Yersinia pestis, single mutations in either yfe or feo result in reduced growth under static (limited aeration), iron-chelated conditions, while a yfe feo double mutant has a more severe growth defect. These growth defects were not observed when bacteria were grown under aerobic conditions or in strains capable of producing the siderophore yersiniabactin (Ybt) and the putative ferrous transporter FetMP. Both fetP and a downstream locus (flp for fet linked phenotype) were required for growth of a yfe feo ybt mutant under static, iron-limiting conditions. An feoB mutation alone had no effect on the virulence of Y. pestis in either bubonic or pneumonic plague models. An feo yfe double mutant was still fully virulent in a pneumonic plague model but had an ∼90-fold increase in the 50% lethal dose (LD(50)) relative to the Yfe(+) Feo(+) parent strain in a bubonic plague model. Thus, Yfe and Feo, in addition to Ybt, play an important role in the progression of bubonic plague. Finally, we examined the factors affecting the expression of the feo operon in Y. pestis. Under static growth conditions, the Y. pestis feo::lacZ fusion was repressed by iron in a Fur-dependent manner but not in cells grown aerobically. Mutations in feoC, fnr, arcA, oxyR, or rstAB had no significant effect on transcription of the Y. pestis feo promoter. Thus, the factor(s) that prevents repression by Fur under aerobic growth conditions remains to be identified.

The Yfe and Feo Transporters Are Involved in Microaerobic Growth and Virulence of Yersinia pestis in Bubonic Plague

PubMed Central

Fetherston, Jacqueline D.; Mier, Ildefonso; Truszczynska, Helena

2012-01-01

The Yfe/Sit and Feo transport systems are important for the growth of a variety of bacteria. In Yersinia pestis, single mutations in either yfe or feo result in reduced growth under static (limited aeration), iron-chelated conditions, while a yfe feo double mutant has a more severe growth defect. These growth defects were not observed when bacteria were grown under aerobic conditions or in strains capable of producing the siderophore yersiniabactin (Ybt) and the putative ferrous transporter FetMP. Both fetP and a downstream locus (flp for fet linked phenotype) were required for growth of a yfe feo ybt mutant under static, iron-limiting conditions. An feoB mutation alone had no effect on the virulence of Y. pestis in either bubonic or pneumonic plague models. An feo yfe double mutant was still fully virulent in a pneumonic plague model but had an ∼90-fold increase in the 50% lethal dose (LD50) relative to the Yfe+ Feo+ parent strain in a bubonic plague model. Thus, Yfe and Feo, in addition to Ybt, play an important role in the progression of bubonic plague. Finally, we examined the factors affecting the expression of the feo operon in Y. pestis. Under static growth conditions, the Y. pestis feo::lacZ fusion was repressed by iron in a Fur-dependent manner but not in cells grown aerobically. Mutations in feoC, fnr, arcA, oxyR, or rstAB had no significant effect on transcription of the Y. pestis feo promoter. Thus, the factor(s) that prevents repression by Fur under aerobic growth conditions remains to be identified. PMID:22927049

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

Role of Hole Trap Sites in MoS2 for Inconsistency in Optical and Electrical Phenomena.

PubMed

Tran, Minh Dao; Kim, Ji-Hee; Kim, Hyun; Doan, Manh Ha; Duong, Dinh Loc; Lee, Young Hee

2018-03-28

Because of strong Coulomb interaction in two-dimensional van der Waals-layered materials, the trap charges at the interface strongly influence the scattering of the majority carriers and thus often degrade their electrical properties. However, the photogenerated minority carriers can be trapped at the interface, modulate the electron-hole recombination, and eventually influence the optical properties. In this study, we report the role of the hole trap sites on the inconsistency in the electrical and optical phenomena between two systems with different interfacial trap densities, which are monolayer MoS 2 -based field-effect transistors (FETs) on hexagonal boron nitride (h-BN) and SiO 2 substrates. Electronic transport measurements indicate that the use of h-BN as a gate insulator can induce a higher n-doping concentration of the monolayer MoS 2 by suppressing the free-electron transfer from the intrinsically n-doped MoS 2 to the SiO 2 gate insulator. Nevertheless, optical measurements show that the electron concentration in MoS 2 /SiO 2 is heavier than that in MoS 2 /h-BN, manifested by the relative red shift of the A 1g Raman peak. The inconsistency in the evaluation of the electron concentration in MoS 2 by electrical and optical measurements is explained by the trapping of the photogenerated holes in the spatially modulated valence band edge of the monolayer MoS 2 caused by the local strain from the SiO 2 /Si substrate. This photoinduced electron doping in MoS 2 /SiO 2 is further confirmed by the development of the trion component in the power-dependent photoluminescence spectra and negative shift of the threshold voltage of the FET after illumination.

Characteristics of camel-gate structures with active doping channel profiles

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Lour, Wen-Shiung; Laih, Lih-Wen; Liu, Rong-Chau; Liu, Wen-Chau

1996-03-01

In this paper, we demonstrate the influence of channel doping profile on the performances of camel-gate field effect transistors (CAMFETs). For comparison, single and tri-step doping channel structures with identical doping thickness products are employed, while other parameters are kept unchanged. The results of a theoretical analysis show that the single doping channel FET with lightly doping active layer has higher barrier height and drain-source saturation current. However, the transconductance is decreased. For a tri-step doping channel structure, it is found that the output drain-source saturation current and the barrier height are enhanced. Furthermore, the relatively voltage independent performances are improved. Two CAMFETs with single and tri-step doping channel structures have been fabricated and discussed. The devices exhibit nearly voltage independent transconductances of 144 mS mm -1 and 222 mS mm -1 for single and tri-step doping channel CAMFETs, respectively. The operation gate voltage may extend to ± 1.5 V for a tri-step doping channel CAMFET. In addition, the drain current densities of > 750 and 405 mA mm -1 are obtained for the tri-step and single doping CAMFETs. These experimental results are inconsistent with theoretical analysis.

In2O3 nanowire based field effect transistor for biological sensors.

NASA Astrophysics Data System (ADS)

Zeng, Zhongming; Wang, Kai; Zhou, Weilie

2008-03-01

Semiconductor nanowires (NWs) are attracting considerable attention due to their nanoscale dimensions and enormous surface-to-volume ratios. Many applications have been demonstrated in toxic gas, protein, small molecule and viruses sensing because of their superior sensing performances. Indium oxide (In2O3) NWs have been successfully applied for toxic gas and small organic molecule sensing. In our experiment, In2O3 NWs based field effect transistors (FET) are fabricated for virus (Ricin) detections. Single-crystalline In2O3 NWs with diameters around 100 nm were synthesized by the thermal evaporation. The nanodevice based on In2O3 NWs bridges the source/drain electrodes with a channel length of ˜5 μm. Basic transport properties of devices were measured before biological detection. The I-V curves with the gate voltage Vg=0 shows good ohmic contact and the resistance is about 10 Mφ. The back-gate effect on the conductivity showed that In2O3 NW is working as n-type channel with obvious back-gate effect, which is much stronger than the reported results. The nanodevices used as virus detection will be also discussed.

Si1-yGey or Ge1-zSnz Source/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

NASA Astrophysics Data System (ADS)

Eneman, Geert; De Keersgieter, An; Witters, Liesbeth; Mitard, Jerome; Vincent, Benjamin; Hikavyy, Andriy; Loo, Roger; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron

2013-04-01

The interaction between two stress techniques, strain-relaxed buffers (SRBs) and epitaxial source/drain stressors, is studied on short, Si1-xGex- and Ge-channel planar transistors. This work focuses on the longitudinal channel stress generated by these two techniques. Unlike for unstrained silicon-channel transistors, for strained channels on top of a strain-relaxed buffer a source/drain stressor without recess generates similar longitudinal channel stress than source/drain stressors with a deep recess. The least efficient stress transfer is obtained for source/drain stressors with a small recess that removes only the strained channel, not the substrate underneath. These trends are explained by a trade-off between elastic relaxation of the strained-channel during source/drain recess and the increased stress generation of thicker source/drain stressors. For Ge-channel pFETs, GeSn source/drains and Si1-xGex strain-relaxed buffers are efficient stressors for mobility enhancement. The former is more efficient for gate-last schemes than for gate-first, while the stress generated by the SRB is found to be independent of the gate-scheme.

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Simultaneous control of thermoelectric properties in p- and n-type materials by electric double-layer gating: New design for thermoelectric device

NASA Astrophysics Data System (ADS)

Takayanagi, Ryohei; Fujii, Takenori; Asamitsu, Atsushi

2015-05-01

We report a novel design of a thermoelectric device that can control the thermoelectric properties of p- and n-type materials simultaneously by electric double-layer gating. Here, p-type Cu2O and n-type ZnO were used as the positive and negative electrodes of the electric double-layer capacitor structure. When a gate voltage was applied between the two electrodes, holes and electrons accumulated on the surfaces of Cu2O and ZnO, respectively. The thermopower was measured by applying a thermal gradient along the accumulated layer on the electrodes. We demonstrate here that the accumulated layers worked as a p-n pair of the thermoelectric device.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

The Use of Ferroelectrics and Dipeptides as Insulators in Organic Field-Effect Transistor Devices

NASA Astrophysics Data System (ADS)

Knotts, Grant

While the electrical transport characteristics of organic electronic devices are generally inferior to their inorganic counterparts, organic materials offer many advantages over inorganics. The materials used in organic devices can often be deposited using cheap and simple processing techniques such as spincoating, inkjet printing, or roll-to-roll processing; allow for large-scale, flexible devices; and can have the added benefits of being transparent or biodegradable. In this manuscript, we examine the role of solvents in the performance of pentacene-based devices using the ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (PVDF-TrFe) as a gate insulating layer. High dipole moment solvents, such as dimethyl sulfoxide, used to dissolve the copolymer for spincoating increase the charge carrier mobility in field-effect transistors (FETs) by nearly an order of magnitude as compared to lower dipole moment solvents. The polarization in Al/PVDF-TrFe/Au metal-ferroelectric-metal devices also shows an increase in remnant polarization of 20% in the sample using dimethyl sulfoxide as the solvent for the ferroelectric. Interestingly, at low applied electric fields of 100 MV/m a remnant polarization is seen in the high dipole moment device that is nearly 3.5 times larger than the value observed in the lower dipole moment samples, suggesting that the degree of dipolar order is higher at low operating voltages for the high dipole moment device. We will also discuss the use of peptide-based nanostructures derived from natural amino acids as building blocks for biocompatible devices. These peptides can be used in a bottom-up process without the need for expensive lithography. Thin films of L,L-diphenylalanine micro/nanostructures (FF-MNSs) were used as the dielectric layer in pentacene-based FETs and metal-insulator-semiconductor diodes both in bottom-gate and top-gate structures. It is demonstrated that the FFMNSs can be functionalized for detection of enzyme-analyte interactions. This work opens up a novel and facile route towards scalable organic electronics using peptide nanostructures as scaffolding and as a platform for biosensing.

Simultaneous protection of organic p- and n-channels in complementary inverter from aging and bias-stress by DNA-base guanine/Al2O3 double layer.

PubMed

Lee, Junyeong; Hwang, Hyuncheol; Min, Sung-Wook; Shin, Jae Min; Kim, Jin Sung; Jeon, Pyo Jin; Lee, Hee Sung; Im, Seongil

2015-01-28

Although organic field-effect transistors (OFETs) have various advantages of lightweight, low-cost, mechanical flexibility, and nowadays even higher mobility than amorphous Si-based FET, stability issue under bias and ambient condition critically hinder its practical application. One of the most detrimental effects on organic layer comes from penetrated atmospheric species such as oxygen and water. To solve such degradation problems, several molecular engineering tactics are introduced: forming a kinetic barrier, lowering the level of molecule orbitals, and increasing the band gap. However, direct passivation of organic channels, the most promising strategy, has not been reported as often as other methods. Here, we resolved the ambient stability issues of p-type (heptazole)/or n-type (PTCDI-C13) OFETs and their bias-stability issues at once, using DNA-base small molecule guanine (C5H5N5O)/Al2O3 bilayer. The guanine protects the organic channels as buffer/and H getter layer between the channels and capping Al2O3, whereas the oxide capping resists ambient molecules. As a result, both p-type and n-type OFETs are simultaneously protected from gate-bias stress and 30 days-long ambient aging, finally demonstrating a highly stable, high-gain complementary-type logic inverter.

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

NASA Astrophysics Data System (ADS)

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.; Lagally, Max G.; Foote, Ryan H.; Friesen, Mark; Coppersmith, Susan N.; Eriksson, Mark A.

2016-10-01

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of double quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. We further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau-Zener-Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

NASA Astrophysics Data System (ADS)

Shao, Jinhai; Deng, Jianan; Lu, W.; Chen, Yifang

2017-07-01

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin

PubMed Central

Taube Navaraj, William; García Núñez, Carlos; Shakthivel, Dhayalan; Vinciguerra, Vincenzo; Labeau, Fabrice; Gregory, Duncan H.; Dahiya, Ravinder

2017-01-01

This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological skin) in the backplane. The modeling and simulation of υ-NWFET based devices show that the overlapping areas between individual gates and the floating gate determines the initial synaptic weights of the neural network - thus validating the working of υ-NWFETs as the building block for HNN. The simulation has been further extended to υ-NWFET based circuits and neuronal computation system and this has been validated by interfacing it with a transparent tactile skin prototype (comprising of 6 × 6 ITO based capacitive tactile sensors array) integrated on the palm of a 3D printed robotic hand. In this regard, a tactile data coding system is presented to detect touch gesture and the direction of touch. Following these simulation studies, a four-gated υ-NWFET is fabricated with Pt/Ti metal stack for gates, source and drain, Ni floating gate, and Al2O3 high-k dielectric layer. The current-voltage characteristics of fabricated υ-NWFET devices confirm the dependence of turn-off voltages on the (synaptic) weight of each gate. The presented υ-NWFET approach is promising for a neuro-robotic tactile sensory system with distributed computing as well as numerous futuristic applications such as prosthetics, and electroceuticals. PMID:28979183

Analysis and optimization of RC delay in vertical nanoplate FET

NASA Astrophysics Data System (ADS)

Woo, Changbeom; Ko, Kyul; Kim, Jongsu; Kim, Minsoo; Kang, Myounggon; Shin, Hyungcheol

2017-10-01

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2 nm, channel thickness (Tch) of 4 nm, and spacer length (LSD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG = 12.2 nm, Tch = 6 nm, LSD = 11.9 nm). It has each characteristic in this dimension (Ion/Ioff = 1.64 × 105, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Pseudomorphic InGaAs/AlGaAs modulation-doped FET's with reduced low-frequency noise and thermally stable performance

NASA Technical Reports Server (NTRS)

Liu, Shih-Ming; Das, M. B.; Peng, C. K.; Klem, J.; Henderson, T.

1987-01-01

A high-performance MODFET structure grown by MBE with the incorporation of a single quantum well In(0.15)Ga(0.85)As layer for the transport of two-dimensional electron gas has been critically examined for its thermal stability at 80 K and low-frequency noise form 0.01 to 10 to the 8th Hz. Experimental results indicate that the behavior of this device in both these respects is much superior when compared with the same behavior of conventional MODFETs. A maximum low-field carrier mobility of 29,000 sq cm/s at 80 K and an average carrier saturation velocity of 2 x 10 to the 7th cm/s at 300 K in a 1-micron gate device clearly indicate that the quality of the pseudomorphic quantum well (InGaAs) layer is either comparable or better than that of the usual GaAs buffer layer. The deep level spectra, obtained through photo-FET measurements, and the low-frequency noise spectra at different temperatures obtained for the new pseudomorphic and conventional MODFET's have clearly indicated that contributions from various deep levels present in the new structure are significantly reduced.

All-Electrical Spin Field Effect Transistor in van der Waals Heterostructures at Room Temperature

NASA Astrophysics Data System (ADS)

Dankert, André; Dash, Saroj

Spintronics aims to exploit the spin degree of freedom in solid state devices for data storage and information processing. Its fundamental concepts (creation, manipulation and detection of spin polarization) have been demonstrated in semiconductors and spin transistor structures using electrical and optical methods. However, an unsolved challenge is the realization of all-electrical methods to control the spin polarization in a transistor manner at ambient temperatures. Here we combine graphene and molybdenum disulfide (MoS2) in a van der Waals heterostructure to realize a spin field-effect transistor (spin-FET) at room temperature. These two-dimensional crystals offer a unique platform due to their contrasting properties, such as weak spin-orbit coupling (SOC) in graphene and strong SOC in MoS2. The gate-tuning of the Schottky barrier at the MoS2/graphene interface and MoS2 channel yields spins to interact with high SOC material and allows us to control the spin polarization and lifetime. This all-electrical spin-FET at room temperature is a substantial step in the field of spintronics and opens a new platform for testing a plethora of exotic physical phenomena, which can be key building blocks in future device architectures.

In-situ SiN{sub x}/InN structures for InN field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zervos, Ch., E-mail: hzervos@physics.uoc.gr; Georgakilas, A.; Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete

Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performancemore » was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.« less

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmid, H., E-mail: sih@zurich.ibm.com; Borg, M.; Moselund, K.

2015-06-08

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm{sup 2}/V s, while the alongsidemore » fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at V{sub DS} = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.« less

Field-effect transistors as electrically controllable nonlinear rectifiers for the characterization of terahertz pulses

NASA Astrophysics Data System (ADS)

Lisauskas, Alvydas; Ikamas, Kestutis; Massabeau, Sylvain; Bauer, Maris; ČibiraitÄ--, DovilÄ--; Matukas, Jonas; Mangeney, Juliette; Mittendorff, Martin; Winnerl, Stephan; Krozer, Viktor; Roskos, Hartmut G.

2018-05-01

We propose to exploit rectification in field-effect transistors as an electrically controllable higher-order nonlinear phenomenon for the convenient monitoring of the temporal characteristics of THz pulses, for example, by autocorrelation measurements. This option arises because of the existence of a gate-bias-controlled super-linear response at sub-threshold operation conditions when the devices are subjected to THz radiation. We present measurements for different antenna-coupled transistor-based THz detectors (TeraFETs) employing (i) AlGaN/GaN high-electron-mobility and (ii) silicon CMOS field-effect transistors and show that the super-linear behavior in the sub-threshold bias regime is a universal phenomenon to be expected if the amplitude of the high-frequency voltage oscillations exceeds the thermal voltage. The effect is also employed as a tool for the direct determination of the speed of the intrinsic TeraFET response which allows us to avoid limitations set by the read-out circuitry. In particular, we show that the build-up time of the intrinsic rectification signal of a patch-antenna-coupled CMOS detector changes from 20 ps in the deep sub-threshold voltage regime to below 12 ps in the vicinity of the threshold voltage.

Probing the intrinsic charge transport in indacenodithiophene-co-benzothiadiazole thin films

NASA Astrophysics Data System (ADS)

Wang, Wenhe; Tang, Wei; Zhao, Jiaqing; Bao, Bei; Xing, Hui; Guo, Xiaojun; Wang, Shun; Liu, Ying

2017-12-01

Indacenodithiophene-co-benzothiadiazole (IDTBT) belongs to a class of donor-acceptor polymers, exhibiting high electronic mobility and low energetic disorder. Applying vacuum as dielectric enables us to investigate the intrinsic charge transport properties in IDTBT. Vacuum-gap IDTBT field-effect transistors (FET) show high mobilites approaching 1 cm2V-1s-1. In addition, with increasing dielectric constant of the gate insulators, the mobilites of IDTBT transistors first increase and then decrease. The reason could be attributed to effect of both charge carrier accumulation and the presence of dipolar disorder at the semiconductor/insulator interface induced by polar insulator layer.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2018-03-05

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10 -14 A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (10 7 ) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Lim, Cheol-Min

2018-02-01

In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Technical Reports Server (NTRS)

Jones, C. W. (Editor)

1985-01-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2018-03-01

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10-14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (107) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Astrophysics Data System (ADS)

Jones, C. W.

1985-12-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.