Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

NASA Astrophysics Data System (ADS)

Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

2011-03-01

The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

Gate-Induced Metal–Insulator Transition in MoS 2 by Solid Superionic Conductor LaF 3

DOE PAGES

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin; ...

2018-03-23

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Electrofluidic gating of a chemically reactive surface.

PubMed

Jiang, Zhijun; Stein, Derek

2010-06-01

We consider the influence of an electric field applied normal to the electric double layer at a chemically reactive surface. Our goal is to elucidate how surface chemistry affects the potential for field-effect control over micro- and nanofluidic systems, which we call electrofluidic gating. The charging of a metal-oxide-electrolyte (MOE) capacitor is first modeled analytically. We apply the Poisson-Boltzmann description of the double layer and impose chemical equilibrium between the ionizable surface groups and the solution at the solid-liquid interface. The chemically reactive surface is predicted to behave as a buffer, regulating the charge in the double layer by either protonating or deprotonating in response to the applied field. We present the dependence of the charge density and the electrochemical potential of the double layer on the applied field, the density, and the dissociation constants of ionizable surface groups and the ionic strength and the pH of the electrolyte. We simulate the responses of SiO(2) and Al(2)O(3), two widely used oxide insulators with different surface chemistries. We also consider the limits to electrofluidic gating imposed by the nonlinear behavior of the double layer and the dielectric strength of oxide materials, which were measured for SiO(2) and Al(2)O(3) films in MOE configurations. Our results clarify the response of chemically reactive surfaces to applied fields, which is crucial to understanding electrofluidic effects in real devices.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Printable Top-Gate-Type Polymer Light-Emitting Transistors with Surfaces of Amorphous Fluoropolymer Insulators Modified by Vacuum Ultraviolet Light Treatment

NASA Astrophysics Data System (ADS)

Kajii, Hirotake; Terashima, Daiki; Kusumoto, Yusuke; Ikezoe, Ikuya; Ohmori, Yutaka

2013-04-01

We investigated the fabrication and electrical and optical properties of top-gate-type polymer light-emitting transistors with the surfaces of amorphous fluoropolymer insulators, CYTOP (Asahi Glass) modified by vacuum ultraviolet light (VUV) treatment. The surface energy of CYTOP, which has a good solution barrier property was increased by VUV irradiation, and the gate electrode was fabricated by solution processing on the CYTOP film using the Ag nano-ink. The influence of VUV irradiation on the optical properties of poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT) films with various gate insulators was investigated to clarify the passivation effect of gate insulators. It was found that the poly(methyl methacrylate) (PMMA) film prevented the degradation of the F8BT layer under VUV irradiation because the PMMA film can absorb VUV. The solution-processed F8BT device with multilayer PMMA/CYTOP insulators utilizing a gate electrode fabricated using the Ag nano-ink exhibited both the ambipolar characteristics and yellow-green emission.

A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

NASA Astrophysics Data System (ADS)

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

2015-09-01

A carrier-based analytical drain current model for negative capacitance symmetric double-gate field effect transistors (NC-SDG FETs) is proposed by solving the differential equation of the carrier, the Pao-Sah current formulation, and the Landau-Khalatnikov equation. The carrier equation is derived from Poisson’s equation and the Boltzmann distribution law. According to the model, an amplified semiconductor surface potential and a steeper subthreshold slope could be obtained with suitable thicknesses of the ferroelectric film and insulator layer at room temperature. Results predicted by the analytical model agree well with those of the numerical simulation from a 2D simulator without any fitting parameters. The analytical model is valid for all operation regions and captures the transitions between them without any auxiliary variables or functions. This model can be used to explore the operating mechanisms of NC-SDG FETs and to optimize device performance.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Lithographically defined few-electron silicon quantum dots based on a silicon-on-insulator substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horibe, Kosuke; Oda, Shunri; Kodera, Tetsuo, E-mail: kodera.t.ac@m.titech.ac.jp

2015-02-23

Silicon quantum dot (QD) devices with a proximal single-electron transistor (SET) charge sensor have been fabricated in a metal-oxide-semiconductor structure based on a silicon-on-insulator substrate. The charge state of the QDs was clearly read out using the charge sensor via the SET current. The lithographically defined small QDs enabled clear observation of the few-electron regime of a single QD and a double QD by charge sensing. Tunnel coupling on tunnel barriers of the QDs can be controlled by tuning the top-gate voltages, which can be used for manipulation of the spin quantum bit via exchange interaction between tunnel-coupled QDs. Themore » lithographically defined silicon QD device reported here is technologically simple and does not require electrical gates to create QD confinement potentials, which is advantageous for the integration of complicated constructs such as multiple QD structures with SET charge sensors for the purpose of spin-based quantum computing.« less

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

PubMed

Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

2013-06-11

We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Gate-tunable gigantic changes in lattice parameters and optical properties in VO2

NASA Astrophysics Data System (ADS)

Nakano, Masaki; Okuyama, Daisuke; Shibuya, Keisuke; Ogawa, Naoki; Hatano, Takafumi; Kawasaki, Masashi; Arima, Taka-Hisa; Iwasa, Yoshihiro; Tokura, Yoshinori

2014-03-01

The field-effect transistor provides an electrical switching function of current flowing through a channel surface by external gate voltage (VG). We recently reported that an electric-double-layer transistor (EDLT) based on vanadium dioxide (VO2) enables electrical switching of the metal-insulator phase transition, where the low-temperature insulating state can be completely switched to the metallic state by application of VG. Here we demonstrate that VO2-EDLT enables electrical switching of lattice parameters and optical properties as well as electrical current. We performed in-situ x-ray diffraction and optical transmission spectroscopy measurements, and found that the c-axis length and the infrared transmittance of VO2 can be significantly modulated by more than 1% and 40%, respectively, by application of VG. We emphasize that these distinguished features originate from the electric-field induced bulk phase transition available with VO2-EDLT. This work was supported by the Japan Society for the Promotion of Science (JSPS) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

Gate-Variable Mid-Infrared Optical Transitions in a (Bi1-xSbx)2Te3 Topological Insulator.

PubMed

Whitney, William S; Brar, Victor W; Ou, Yunbo; Shao, Yinming; Davoyan, Artur R; Basov, D N; He, Ke; Xue, Qi-Kun; Atwater, Harry A

2017-01-11

We report mid-infrared spectroscopy measurements of ultrathin, electrostatically gated (Bi 1-x Sb x ) 2 Te 3 topological insulator films in which we observe several percent modulation of transmittance and reflectance as gating shifts the Fermi level. Infrared transmittance measurements of gated films were enabled by use of an epitaxial lift-off method for large-area transfer of topological insulator films from infrared-absorbing SrTiO 3 growth substrates to thermal oxidized silicon substrates. We combine these optical experiments with transport measurements and angle-resolved photoemission spectroscopy to identify the observed spectral modulation as a gate-driven transfer of spectral weight between both bulk and 2D topological surface channels and interband and intraband channels. We develop a model for the complex permittivity of gated (Bi 1-x Sb x ) 2 Te 3 and find a good match to our experimental data. These results open the path for layered topological insulator materials as a new candidate for tunable, ultrathin infrared optics and highlight the possibility of switching topological optoelectronic phenomena between bulk and spin-polarized surface regimes.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

NASA Astrophysics Data System (ADS)

Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-11-01

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to silicon for potentiometric biosensing.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Ui, Toshimasa; Nguyen, Tuan Quy

Using aluminum titanium oxide (AlTiO, an alloy of Al{sub 2}O{sub 3} and TiO{sub 2}) as a high-k gate insulator, we fabricated and investigated AlTiO/AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors. From current low-frequency noise (LFN) characterization, we find Lorentzian spectra near the threshold voltage, in addition to 1/f spectra for the well-above-threshold regime. The Lorentzian spectra are attributed to electron trapping/detrapping with two specific time constants, ∼25 ms and ∼3 ms, which are independent of the gate length and the gate voltage, corresponding to two trap level depths of 0.5–0.7 eV with a 0.06 eV difference in the AlTiO insulator. In addition, gate leakage currents aremore » analyzed and attributed to the Poole-Frenkel mechanism due to traps in the AlTiO insulator, where the extracted trap level depth is consistent with the Lorentzian LFN.« less

Nature of superconductor-insulator transition at LaAlO{sub 3}/SrTiO{sub 3} interface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohanta, N., E-mail: nmohanta@phy.iitkgp.ernet.in; Taraphder, A.; Centre for Theoretical Studies, Indian Institute of Technology Kharagpur, W. B. 721302

2015-05-15

The two-dimensional electron liquid, at the interface between two band insulators LaAlO{sub 3} and SrTiO{sub 3}, exhibits novel, unconventional superconductivity below 200 mK. One of the remarkable properties of the two-dimensional superconductor is its fantastic tunability by external parameters such as gate-voltage or magnetic field. We study the superconductor to insulator transition induced by gate-voltage by employing a self-consistent, mean-field Bogoliubov-de Gennes treatment based on an effective model. We show that the non-monotonic behaviour of the superconductivity with respect to gate-voltage is intrinsically due to the Rashba spin-orbit coupling. With increasing gate-voltage both the electron concentration and Rashba spin-orbit splittingmore » increases. Elevated electron filling boosts superconductivity whereas enhanced spin-orbit splitting annihilates electron-pairing. The non-monotonicity is a result of this competition. The device application of the superconductor-insulator transition in this interface is discussed.« less

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Priyanka; Sahu, P. K.

2016-01-01

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

Electric-field driven insulator-metal transition and tunable magnetoresistance in ZnO thin film

NASA Astrophysics Data System (ADS)

Zhang, Le; Chen, Shanshan; Chen, Xiangyang; Ye, Zhizhen; Zhu, Liping

2018-04-01

Electrical control of the multistate phase in semiconductors offers the promise of nonvolatile functionality in the future semiconductor spintronics. Here, by applying an external electric field, we have observed a gate-induced insulator-metal transition (MIT) with the temperature dependence of resistivity in ZnO thin films. Due to a high-density carrier accumulation, we have shown the ability to inverse change magnetoresistance in ZnO by ionic liquid gating from 10% to -2.5%. The evolution of photoluminescence under gate voltage was also consistent with the MIT, which is due to the reduction of dislocation. Our in-situ gate-controlled photoluminescence, insulator-metal transition, and the conversion of magnetoresistance open up opportunities in searching for quantum materials and ZnO based photoelectric devices.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

PubMed

Dimitrakopoulos; Purushothaman; Kymissis; Callegari; Shaw

1999-02-05

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

NASA Astrophysics Data System (ADS)

Karmakar, Supriya; Suarez, Ernesto; Jain, Faquir C.

2011-08-01

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high- κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO x -Ge quantum dots.

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Properties of the correlated metal phase induced by electrolyte gating of insulating vanadium dioxide nanobeams

NASA Astrophysics Data System (ADS)

Singh, Sujay; Horrocks, Gregory; Marley, Peter; Banerjee, Sarbajit; Sambandamurthy, G.

2014-03-01

Vanadium oxide (VO2) undergoes a first order metal to insulator transition (MIT) and a structural phase transition (monoclinic insulator to rutile metal) near 340 K. Over the past few years, several attempts are made to trigger the MIT in VO2 using ionic liquids (IL). Parkin's group has recently showed that IL gating leads to the creation of oxygen vacancies in VO2 and stabilizes the metallic phase. Our goal is to study the electronic properties, changes in the stoichiometry and structure of this metallic phase created by oxygen vacancies. Electrical transport measurements on single crystal nanobeams show that the metallic phase has a higher resistance while IL gating is applied and results from Raman spectroscopy studies on any structural change during IL gating will be presented. The role of substitutional dopants (such as W, Mo) on the creation of oxygen vacancies and subsequent stabilization of metallic phase in IL gated experiments will also be discussed. The work is supported by NSF DMR 0847324 and 0847169.

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Magnetic gating of a 2D topological insulator

NASA Astrophysics Data System (ADS)

Dang, Xiaoqian; Burton, J. D.; Tsymbal, Evgeny Y.

2016-09-01

Deterministic control of transport properties through manipulation of spin states is one of the paradigms of spintronics. Topological insulators offer a new playground for exploring interesting spin-dependent phenomena. Here, we consider a ferromagnetic ‘gate’ representing a magnetic adatom coupled to the topologically protected edge state of a two-dimensional (2D) topological insulator to modulate the electron transmission of the edge state. Due to the locked spin and wave vector of the transport electrons the transmission across the magnetic gate depends on the mutual orientation of the adatom magnetic moment and the current. If the Fermi energy matches an exchange-split bound state of the adatom, the electron transmission can be blocked due to the full back scattering of the incident wave. This antiresonance behavior is controlled by the adatom magnetic moment orientation so that the transmission of the edge state can be changed from 1 to 0. Expanding this consideration to a ferromagnetic gate representing a 1D chain of atoms shows a possibility to control the spin-dependent current of a strip of a 2D topological insulator by magnetization orientation of the ferromagnetic gate.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Ambipolar insulator-to-metal transition in black phosphorus by ionic-liquid gating.

PubMed

Saito, Yu; Iwasa, Yoshihiro

2015-03-24

We report ambipolar transport properties in black phosphorus using an electric-double-layer transistor configuration. The transfer curve clearly exhibits ambipolar transistor behavior with an ON-OFF ratio of ∼5 × 10(3). The band gap was determined as ≅0.35 eV from the transfer curve, and Hall-effect measurements revealed that the hole mobility was ∼190 cm(2)/(V s) at 170 K, which is 1 order of magnitude larger than the electron mobility. By inducing an ultrahigh carrier density of ∼10(14) cm(-2), an electric-field-induced transition from the insulating state to the metallic state was realized, due to both electron and hole doping. Our results suggest that black phosphorus will be a good candidate for the fabrication of functional devices, such as lateral p-n junctions and tunnel diodes, due to the intrinsic narrow band gap.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Surface modification of polyimide gate insulators for solution-processed 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiophene (C10-BTBT) thin-film transistors.

PubMed

Jang, Kwang-Suk; Kim, Won Soo; Won, Jong-Myung; Kim, Yun-Ho; Myung, Sung; Ka, Jae-Won; Kim, Jinsoo; Ahn, Taek; Yi, Mi Hye

2013-01-21

The surface property of a polyimide gate insulator was successfully modified with an n-octadecyl side-chain. Alkyl chain-grafted poly(amic acid), the polyimide precursor, was synthesized using the diamine comonomer with an alkyl side-chain. By adding a base catalyst to the poly(amic acid) coating solution, the imidization temperature of the spin-coated film could be reduced to 200 °C. The 350 nm-thick polyimide film had a dielectric constant of 3.3 at 10 kHz and a leakage current density of less than 8.7 × 10(-10) A cm(-2), while biased from 0 to 100 V. To investigate the potential of the alkyl chain-grafted polyimide film as a gate insulator for solution-processed organic thin-film transistors (TFTs), we fabricated C(10)-BTBT TFTs. C(10)-BTBT was deposited on the alkyl chain-grafted polyimide gate insulator by spin-coating, forming a well-ordered crystal structure. The field-effect mobility and the on/off current ratio of the TFT device were measured to be 0.20-0.56 cm(2) V(-1) s(-1) and >10(5), respectively.

Enhanced stability of thin film transistors with double-stacked amorphous IWO/IWO:N channel layer

NASA Astrophysics Data System (ADS)

Lin, Dong; Pi, Shubin; Yang, Jianwen; Tiwari, Nidhi; Ren, Jinhua; Zhang, Qun; Liu, Po-Tsun; Shieh, Han-Ping

2018-06-01

In this work, bottom-gate top-contact thin film transistors with double-stacked amorphous IWO/IWO:N channel layer were fabricated. Herein, amorphous IWO and N-doped IWO were deposited as front and back channel layers, respectively, by radio-frequency magnetron sputtering. The electrical characteristics of the bi-layer-channel thin film transistors (TFTs) were examined and compared with those of single-layer-channel (i.e., amorphous IWO or IWO:N) TFTs. It was demonstrated to exhibit a high mobility of 27.2 cm2 V‑1 s‑1 and an on/off current ratio of 107. Compared to the single peers, bi-layer a-IWO/IWO:N TFTs showed smaller hysteresis and higher stability under negative bias stress and negative bias temperature stress. The enhanced performance could be attributed to its unique double-stacked channel configuration, which successfully combined the merits of the TFTs with IWO and IWO:N channels. The underlying IWO thin film provided percolation paths for electron transport, meanwhile, the top IWO:N layer reduced the bulk trap densities. In addition, the IWO channel/gate insulator interface had reduced defects, and IWO:N back channel surface was insensitive to the ambient atmosphere. Overall, the proposed bi-layer a-IWO/IWO:N TFTs show potential for practical applications due to its possibly long-term serviceability.

Gate-tunable supercurrent and multiple Andreev reflections in a superconductor-topological insulator nanoribbon-superconductor hybrid device

NASA Astrophysics Data System (ADS)

Jauregui, Luis A.; Kayyalha, Morteza; Kazakov, Aleksandr; Miotkowski, Ireneusz; Rokhinson, Leonid P.; Chen, Yong P.

2018-02-01

We report on the observation of gate-tunable proximity-induced superconductivity and multiple Andreev reflections (MARs) in a bulk-insulating BiSbTeSe2 topological insulator nanoribbon (TINR) Josephson junction with superconducting Nb contacts. We observe a gate-tunable critical current (IC) for gate voltages (Vg) above the charge neutrality point (VCNP), with IC as large as 430 nA. We also observe MAR peaks in the differential conductance (dI/dV) versus DC voltage (Vdc) across the junction corresponding to sub-harmonic peaks (at Vdc = Vn = 2ΔNb/en, where ΔNb is the superconducting gap of the Nb contacts and n is the sub-harmonic order). The sub-harmonic order, n, exhibits a Vg-dependence and reaches n = 13 for Vg = 40 V, indicating the high transparency of the Nb contacts to TINR. Our observations pave the way toward exploring the possibilities of using TINR in topologically protected devices that may host exotic physics such as Majorana fermions.

Extracting current induced spins from topological insulator wires: gate control of extracted spin polarization

NASA Astrophysics Data System (ADS)

Adagideli, Inanc

Spin-momentum locking featured by the surface states of 3D topological insulators (TIs) allows electrical generation of spin accumulations and provides a new avenue for spintronics applications. In this work, we explore how to extract electrically induced spins from topological insulator surfaces, where they are generated into topologically trivial metallic leads that are commonly used in conventional electronic devices. We first focus on an effective surface theory of current induced spin accumulation in topological insulators. Then we focus on a particular geometry: a metallic pocket attached to top and side faces of a 3D topological insulator quantum wire with a rectangular cross section, and explore spin extraction into topologically non-trivial materials. We find surprisingly that the doping in and/or a gate voltage applied to the metallic side pocket can control the direction of the extracted spin polarization opening the possibility for a spin transistor operation of these device geometries. We also perform numerical simulations of nonequilibrium spin accumulations generated by an applied bias in the same geometry and demonstrate the spin polarization control via applied gate voltages. Work funded by TUBITAK Grant No 114F163.

Chiral tunneling modulated by a time-periodic potential on the surface states of a topological insulator

PubMed Central

Li, Yuan; Jalil, Mansoor B. A.; Tan, S. G.; Zhao, W.; Bai, R.; Zhou, G. H.

2014-01-01

Time-periodic perturbation can be used to modify the transport properties of the surface states of topological insulators, specifically their chiral tunneling property. Using the scattering matrix method, we study the tunneling transmission of the surface states of a topological insulator under the influence of a time-dependent potential and finite gate bias voltage. It is found that perfect transmission is obtained for electrons which are injected normally into the time-periodic potential region in the absence of any bias voltage. However, this signature of Klein tunneling is destroyed when a bias voltage is applied, with the transmission probability of normally incident electrons decreasing with increasing gate bias voltage. Likewise, the overall conductance of the system decreases significantly when a gate bias voltage is applied. The characteristic left-handed helicity of the transmitted spin polarization is also broken by the finite gate bias voltage. In addition, the time-dependent potential modifies the large-angle transmission profile, which exhibits an oscillatory or resonance-like behavior. Finally, time-dependent transport modes (with oscillating potential in the THz frequency) can result in enhanced overall conductance, irrespective of the presence or absence of the gate bias voltage. PMID:24713634

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

Improved Mobility and Bias Stability of Thin Film Transistors Using the Double-Layer a-InGaZnO/a-InGaZnO:N Channel.

PubMed

Yu, H; Zhang, L; Li, X H; Xu, H Y; Liu, Y C

2016-04-01

The amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) were demonstrated based on a double-layer channel structure, where the channel is composed of an ultrathin nitro-genated a-IGZO (a-IGZO:N) layer and an undoped a-IGZO layer. The double-layer channel device showed higher saturation mobility and lower threshold-voltage shift (5.74 cm2/Vs, 2.6 V) compared to its single-layer counterpart (0.17 cm2/Vs, 7.23 V). The improvement can be attributed to three aspects: (1) improved carrier transport properties of the channel by the a-IGZO:N layer with high carrier mobility and the a-IGZO layer with high carrier concentration, (2) reduced interfacial trap density between the active channel and the gate insulator, and (3) higher surface flatness of the double-layer channel. Our study reveals key insights into double-layer channel, involving selecting more suitable electrical property for back-channel layer and more suitable interface modification for active layer. Meanwhile, room temperature fabrication amorphous TFTs offer certain advantages on better flexibility and higher uniformity over a large area.

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Low voltage-driven oxide phototransistors with fast recovery, high signal-to-noise ratio, and high responsivity fabricated via a simple defect-generating process

PubMed Central

Yun, Myeong Gu; Kim, Ye Kyun; Ahn, Cheol Hyoun; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun; Kim, Yong-Hoon

2016-01-01

We have demonstrated that photo-thin film transistors (photo-TFTs) fabricated via a simple defect-generating process could achieve fast recovery, a high signal to noise (S/N) ratio, and high sensitivity. The photo-TFTs are inverted-staggered bottom-gate type indium-gallium-zinc-oxide (IGZO) TFTs fabricated using atomic layer deposition (ALD)-derived Al2O3 gate insulators. The surfaces of the Al2O3 gate insulators are damaged by ion bombardment during the deposition of the IGZO channel layers by sputtering and the damage results in the hysteresis behavior of the photo-TFTs. The hysteresis loops broaden as the deposition power density increases. This implies that we can easily control the amount of the interface trap sites and/or trap sites in the gate insulator near the interface. The photo-TFTs with large hysteresis-related defects have high S/N ratio and fast recovery in spite of the low operation voltages including a drain voltage of 1 V, positive gate bias pulse voltage of 3 V, and gate voltage pulse width of 3 V (0 to 3 V). In addition, through the hysteresis-related defect-generating process, we have achieved a high responsivity since the bulk defects that can be photo-excited and eject electrons also increase with increasing deposition power density. PMID:27553518

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Tunneling Plasmonics in Bilayer Graphene.

PubMed

Fei, Z; Iwinski, E G; Ni, G X; Zhang, L M; Bao, W; Rodin, A S; Lee, Y; Wagner, M; Liu, M K; Dai, S; Goldflam, M D; Thiemens, M; Keilmann, F; Lau, C N; Castro-Neto, A H; Fogler, M M; Basov, D N

2015-08-12

We report experimental signatures of plasmonic effects due to electron tunneling between adjacent graphene layers. At subnanometer separation, such layers can form either a strongly coupled bilayer graphene with a Bernal stacking or a weakly coupled double-layer graphene with a random stacking order. Effects due to interlayer tunneling dominate in the former case but are negligible in the latter. We found through infrared nanoimaging that bilayer graphene supports plasmons with a higher degree of confinement compared to single- and double-layer graphene, a direct consequence of interlayer tunneling. Moreover, we were able to shut off plasmons in bilayer graphene through gating within a wide voltage range. Theoretical modeling indicates that such a plasmon-off region is directly linked to a gapped insulating state of bilayer graphene, yet another implication of interlayer tunneling. Our work uncovers essential plasmonic properties in bilayer graphene and suggests a possibility to achieve novel plasmonic functionalities in graphene few-layers.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Floquet high Chern insulators in periodically driven chirally stacked multilayer graphene

NASA Astrophysics Data System (ADS)

Li, Si; Liu, Cheng-Cheng; Yao, Yugui

2018-03-01

Chirally stacked N-layer graphene is a semimetal with ±p N band-touching at two nonequivalent corners in its Brillioun zone. We predict that an off-resonant circularly polarized light (CPL) drives chirally stacked N-layer graphene into a Floquet Chern insulators (FCIs), aka quantum anomalous Hall insulators, with tunable high Chern number C F = ±N and large gaps. A topological phase transition between such a FCI and a valley Hall (VH) insulator with high valley Chern number C v = ±N induced by a voltage gate can be engineered by the parameters of the CPL and voltage gate. We propose a topological domain wall between the FCI and VH phases, along which perfectly valley-polarized N-channel edge states propagate unidirectionally without backscattering.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

Phase coherence and Andreev reflection in topological insulator devices

DOE PAGES

Finck, A. D. K.; Kurter, C.; Hor, Y. S.; ...

2014-11-04

Topological insulators (TIs) have attracted immense interest because they host helical surface states. Protected by time-reversal symmetry, they are robust to nonmagnetic disorder. When superconductivity is induced in these helical states, they are predicted to emulate p-wave pairing symmetry, with Majorana states bound to vortices. Majorana bound states possess non-Abelian exchange statistics that can be probed through interferometry. Here, we take a significant step towards Majorana interferometry by observing pronounced Fabry-Pérot oscillations in a TI sandwiched between a superconducting and a normal lead. For energies below the superconducting gap, we observe a doubling in the frequency of the oscillations, arisingmore » from an additional phase from Andreev reflection. When a magnetic field is applied perpendicular to the TI surface, a number of very sharp and gate-tunable conductance peaks appear at or near zero energy, which has consequences for interpreting spectroscopic probes of Majorana fermions. Our results show that TIs are a promising platform for exploring phase-coherent transport in a solid-state system.« less

A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

2016-05-01

Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

DTIC Science & Technology

2015-02-01

executed with SolidWorks Flow Simulation , a computational fluid-dynamics code. The graph in Fig. 2 shows the timing and amplitudes of power pulses...defined a convective flow of air perpendicular to the bottom surface of the mounting plate, with a velocity of 10 ft/s. The thermal simulations were...Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210

An AlGaN/GaN high-electron-mobility transistor with an AlN sub-buffer layer

NASA Astrophysics Data System (ADS)

Shealy, J. R.; Kaper, V.; Tilak, V.; Prunty, T.; Smart, J. A.; Green, B.; Eastman, L. F.

2002-04-01

The AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible microwave performance. The semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure. The addition of an insulating AlN sub-buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AlGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the AlN sub-buffer layer. These structures operate up to 50 V drain bias under drive, corresponding to a peak voltage of 80 V, for a 0.30 µm gate length device. The devices have achieved high-efficiency operation at 10 GHz (>70% power-added efficiency in class AB mode at 15 V drain bias) and the highest output power density observed thus far (11.2 W mm-1). Large-periphery devices (1.5 mm gate width) deliver 10 W (continuous wave) of maximum saturated output power at 10 GHz. The growth, processing, and performance of these devices are briefly reviewed.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Gate-tunable gigantic lattice deformation in VO{sub 2}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Okuyama, D., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp; Hatano, T.; Nakano, M., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp

2014-01-13

We examined the impact of electric field on crystal lattice of vanadium dioxide (VO{sub 2}) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO{sub 2} decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature.

Investigation of the fabrication processes of AlGaN/AlN/GaN HEMTs with in situ Si{sub 3}N{sub 4} passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tomosh, K. N., E-mail: sky77781@mail.ru; Pavlov, A. Yu.; Pavlov, V. Yu.

2016-10-15

The optimum mode of the in situ plasma-chemical etching of a Si{sub 3}N{sub 4} passivating layer in C{sub 3}F{sub 8}/O{sub 2} medium is chosen for the case of fabricating AlGaN/AlN/GaN HEMTs. It is found that a bias of 40–50 V at a high-frequency electrode provides anisotropic etching of the insulator through a resist mask and introduces no appreciable radiation-induced defects upon overetching of the insulator films in the region of gate-metallization formation. To estimate the effect of in situ Si{sub 3}N{sub 4} growth together with the heterostructure in one process on the AlGaN/AlN/GaN HEMT characteristics, transistors with gates without themore » insulator and with gates through Si{sub 3}N{sub 4} slits are fabricated. The highest drain current of the AlGaN/AlN/GaN HEMT at 0 V at the gate is shown to be 1.5 times higher in the presence of Si{sub 3}N{sub 4} than without it.« less

Improving subthreshold swing to thermionic emission limit in carbon nanotube network film-based field-effect

NASA Astrophysics Data System (ADS)

Zhao, Chenyi; Zhong, Donglai; Qiu, Chenguang; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2018-01-01

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3 nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2 μm) that exhibit an SS of approximately 60 mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7 nm and 10 nm, simultaneously yielding an excellent SS (<80 mV/decade) and low gate leakage. However, because of the statistical fluctuations of the network CNT channel, the lateral scaling of CNT network film-based FETs is more difficult than that of conventional FETs. Experiments suggest that excellent SS is difficult to achieve statistically in CNT network film FETs with a small channel length (smaller than the mean length of the CNTs), which eventually limits the further scaling down of this kind of CNT FET to the sub-micrometer regime.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

Advanced insulated gate bipolar transistor gate drive

DOEpatents

Short, James Evans [Monongahela, PA; West, Shawn Michael [West Mifflin, PA; Fabean, Robert J [Donora, PA

2009-08-04

A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Nonvolatile Solid-State Charged-Polymer Gating of Topological Insulators into the Topological Insulating Regime

NASA Astrophysics Data System (ADS)

Ireland, R. M.; Wu, Liang; Salehi, M.; Oh, S.; Armitage, N. P.; Katz, H. E.

2018-04-01

We demonstrate the ability to reduce the carrier concentration of thin films of the topological insulator (TI) Bi2 Se3 by utilizing a nonvolatile electrostatic gating via corona charging of electret polymers. Sufficient electric field can be imparted to a polymer-TI bilayer to result in significant electron density depletion, even without the continuous connection of a gate electrode or the chemical modification of the TI. We show that the Fermi level of Bi2 Se3 is shifted toward the Dirac point with this method. Using terahertz spectroscopy, we find that the surface chemical potential is lowered into the bulk band gap (approximately 50 meV above the Dirac point and 170 meV below the conduction-band minimum), and it is stabilized in the intrinsic regime while enhancing electron mobility. The mobility of surface state electrons is enhanced to a value as high as approximately 1600 cm2/V s at 5 K.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2017-12-01

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

Specific features of the current–voltage characteristics of SiO{sub 2}/4H-SiC MIS structures with phosphorus implanted into silicon carbide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mikhaylova, A. I., E-mail: m.aleksey.spb@gmail.com; Afanasyev, A. V.; Ilyin, V. A.

The effect of phosphorus implantation into a 4H-SiC epitaxial layer immediately before the thermal growth of a gate insulator in an atmosphere of dry oxygen on the reliability of the gate insulator is studied. It is found that, together with passivating surface states, the introduction of phosphorus ions leads to insignificant weakening of the dielectric breakdown field and to a decrease in the height of the energy barrier between silicon carbide and the insulator, which is due to the presence of phosphorus atoms at the 4H-SiC/SiO{sub 2} interface and in the bulk of silicon dioxide.

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Chromium-induced ferromagnetism with perpendicular anisotropy in topological crystalline insulator SnTe (111) thin films

NASA Astrophysics Data System (ADS)

Wang, Fei; Zhang, Hongrui; Jiang, Jue; Zhao, Yi-Fan; Yu, Jia; Liu, Wei; Li, Da; Chan, Moses H. W.; Sun, Jirong; Zhang, Zhidong; Chang, Cui-Zu

2018-03-01

Topological crystalline insulator is a recently discovered topological phase of matter. It possesses multiple Dirac surface states, which are protected by the crystal symmetry. This is in contrast to the time-reversal symmetry that is operative in the well-known topological insulators. In the presence of a Zeeman field and/or strain, the multiple Dirac surface states are gapped. The high-Chern-number quantum anomalous Hall (QAH) state is predicted to emerge if the chemical potential resides in all the Zeeman gaps. Here, we use molecular-beam epitaxy to grow 12 double-layer (DL) pure and Cr-doped SnTe (111) thin film on heat-treated SrTi O3 (111) substrate using a quintuple layer of insulating (Bi0.2Sb0.8 ) 2T e3 topological insulator as a buffer film. The Hall traces of Cr-doped SnTe film at low temperatures display square hysteresis loops indicating long-range ferromagnetic order with perpendicular anisotropy. The Curie temperature of the 12 DL S n0.9C r0.1Te film is ˜110 K. Due to the chemical potential crossing the bulk valence bands, the anomalous Hall resistance of 12 DL S n0.9C r0.1Te film is substantially lower than the predicted quantized value (˜1 /4 h /e2 ). It is possible that with systematic tuning the chemical potential via chemical doping and electrical gating, the high-Chern-number QAH state can be realized in the Cr-doped SnTe (111) thin film.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

NASA Astrophysics Data System (ADS)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Gate-tuned Josephson effect on the surface of a topological insulator

PubMed Central

2014-01-01

In the study, we investigate the Josephson supercurrent of a superconductor/normal metal/superconductor junction on the surface of a topological insulator, where a gate electrode is attached to the normal metal. It is shown that the Josephson supercurrent not only can be tuned largely by the temperature but also is related to the potential and the length of the weak-link region. Especially, the asymmetry excess critical supercurrent, oscillatory character, and plateau-like structure have been revealed. We except those phenomena that can be observed in the recent experiment. PMID:25249827

Double-gated myocardial ASL perfusion imaging is robust to heart rate variation.

PubMed

Do, Hung Phi; Yoon, Andrew J; Fong, Michael W; Saremi, Farhood; Barr, Mark L; Nayak, Krishna S

2017-05-01

Cardiac motion is a dominant source of physiological noise (PN) in myocardial arterial spin labeled (ASL) perfusion imaging. This study investigates the sensitivity to heart rate variation (HRV) of double-gated myocardial ASL compared with the more widely used single-gated method. Double-gating and single-gating were performed on 10 healthy volunteers (n = 10, 3F/7M; age, 23-34 years) and eight heart transplant recipients (n = 8, 1F/7M; age, 26-76 years) at rest in the randomized order. Myocardial blood flow (MBF), PN, temporal signal-to-noise ratio (SNR), and HRV were measured. HRV ranged from 0.2 to 7.8 bpm. Double-gating PN did not depend on HRV, while single-gating PN increased with HRV. Over all subjects, double-gating provided a significant reduction in global PN (from 0.20 ± 0.15 to 0.11 ± 0.03 mL/g/min; P = 0.01) and per-segment PN (from 0.33 ± 0.23 to 0.21 ± 0.12 mL/g/min; P < 0.001), with significant increases in global temporal SNR (from 11 ± 8 to 18 ± 8; P = 0.02) and per-segment temporal SNR (from 7 ± 4 to 11 ± 12; P < 0.001) without significant difference in measured MBF. Single-gated myocardial ASL suffers from reduced temporal SNR, while double-gated myocardial ASL provides consistent temporal SNR independent of HRV. Magn Reson Med 77:1975-1980, 2017. © 2016 International Society for Magnetic Resonance in Medicine. © 2016 International Society for Magnetic Resonance in Medicine.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Technology Solutions Case Study: Monitoring of Double Stud Wall Moisture Conditions in the Northeast, Devens, Massachusetts

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2015-03-01

Double stud walls have a higher risk of interior-sourced condensation moisture damage when compared with high-R approaches using exterior insulating sheathing. In this project, Building Science Corporation monitored moisture conditions in double-stud walls from 2011 through 2014 at a new production house located in Devens, Massachusetts. The builder, Transformations, Inc., has been using double-stud walls insulated with 12 in. of open cell polyurethane spray foam (ocSPF); however, the company has been considering a change to netted and blown cellulose insulation for cost reasons. Cellulose is a common choice for double-stud walls because of its lower cost (in most markets). However,more » cellulose is an air-permeable insulation, unlike spray foams, which increases interior moisture risks. The team compared three double-stud assemblies: 12 in. of ocSPF, 12 in. of cellulose, and 5-½ in. of ocSPF at the exterior of a double-stud wall (to approximate conventional 2 × 6 wall construction and insulation levels, acting as a control wall). These assemblies were repeated on the north and south orientations, for a total of six assemblies.« less

MCTs and IGBTs - A comparison of performance in power electronic circuits

NASA Technical Reports Server (NTRS)

Sul, S. K.; Profumo, F.; Cho, G. H.; Lipo, T. A.

1989-01-01

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported.

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Low-frequency noise in AlN/AlGaN/GaN metal-insulator-semiconductor devices: A comparison with Schottky devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Nguyen, Tuan Quy; Shih, Hong-An

2014-08-07

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, where the AlN gate insulator layer was sputtering-deposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in the MIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated regionmore » as a function of the sheet electron concentration n{sub s} under the gate. In a regime of small n{sub s}, both the MIS- and Schottky-HFETs exhibit α∝n{sub s}{sup −1}. On the other hand, in a middle n{sub s} regime of the MIS-HFETs, α decreases rapidly like n{sub s}{sup −ξ} with ξ ∼ 2-3, which is not observed for the Schottky-HFETs. In addition, we observe strong increase in α∝n{sub s}{sup 3} in a large n{sub s} regime for both the MIS- and Schottky-HFETs.« less

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

NASA Astrophysics Data System (ADS)

Kitano, Naomu; Horie, Shinya; Arimura, Hiroaki; Kawahara, Takaaki; Sakashita, Shinsuke; Nishida, Yukio; Yugami, Jiro; Minami, Takashi; Kosuda, Motomu; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2007-12-01

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal-insulator-semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 μA/μm at Ioff = 200 pA/μm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Temperature-Dependent Characterization, Modeling, and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET

DOE PAGES

Ji, Shiqi; Zheng, Sheng; Wang, Fei; ...

2017-07-06

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simplemore » behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.« less

Temperature-Dependent Characterization, Modeling, and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ji, Shiqi; Zheng, Sheng; Wang, Fei

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simplemore » behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.« less

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

Self-Aligned ALD AlOx T-gate Insulator for Gate Leakage Current Suppression in SiNx-Passivated AlGaN/GaN HEMTs

DTIC Science & Technology

2010-01-01

Heterostructure epitaxial material growth was performed by RF plasma-assisted molecular - beam epitaxy (MBE) on a 2-in. semi- insulating 4H SiC wafer. From... beam epitaxy of beryllium-doped GaN buffer layers for AlGaN/GaN HEMTs . J Cryst Growth 2003;251:481–6. [25] Storm DF, Katzer DS, Binari SC, Glaser ER...Shanabrook BV, Roussos JA. Reduction of buffer layer conduction near plasma-assisted molecular - beam epitaxy grown GaN/AlN interfaces by beryllium

Fabrication of (NH4)2S passivated GaAs metal-insulator-semiconductor devices using low-frequency plasma-enhanced chemical vapor deposition

NASA Astrophysics Data System (ADS)

Jaouad, A.; Aimez, V.; Aktik, Ç.; Bellatreche, K.; Souifi, A.

2004-05-01

Metal-insulator-semiconductor (MIS) capacitors were fabricated on n-GaAs(100) substrate using (NH4)2S surface passivation and low-frequency plasma-enhanced chemical vapor deposited silicon nitride as gate insulators. The electrical properties of the fabricated MIS capacitors were analyzed using high-frequency capacitance-voltage and conductance-voltage measurements. The high concentration of hydrogen present during low-frequency plasma deposition of silicon nitride enhances the passivation of GaAs surface, leading to the unpinning of the Fermi level and to a good modulation of the surface potential by gate voltage. The electrical properties of the insulator-semiconductor interface are improved after annealing at 450 °C for 60 s, as a significant reduction of the interface fixed charges and of the interface states density is put into evidence. The minimum interface states density was found to be about 3×1011 cm-2 eV-1, as estimated by the Terman method. .

Monitoring of Double Stud Wall Moisture Conditions in the Northeast

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ueno, K.

2015-03-01

Double-stud walls insulated with cellulose or low-density spray foam can have R-values of 40 or higher. However, double stud walls have a higher risk of interior-sourced condensation moisture damage, when compared with high-R approaches using exterior insulating sheathing.; Moisture conditions in double stud walls were monitored in Zone 5A (Massachusetts); three double stud assemblies were compared.

Monitoring of Double-Stud Wall Moisture Conditions in the Northeast

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ueno, K.

2015-03-01

Double-stud walls insulated with cellulose or low-density spray foam can have R-values of 40 or higher. However, double-stud walls have a higher risk of interior-sourced condensation moisture damage when compared with high-R approaches using exterior insulating sheathing. Moisture conditions in double-stud walls were monitored in Zone 5A (Massachusetts); three double-stud assemblies were compared.

FET charge sensor and voltage probe

NASA Technical Reports Server (NTRS)

Robinson, P. A., Jr. (Inventor)

1986-01-01

A MOSFET structure having a biased gate covered with an insulator is described. The insulator is of such a thickness as to render the structure capable of giving a measure of accumulated charge. The structure is also capable of being used in a stacked structure as a particle spectrometer.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Insulator to metal transition in WO 3 induced by electrolyte gating

DOE PAGES

Leng, X.; Pereiro, J.; Strle, J.; ...

2017-07-03

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Atomic layer deposited Ta2O5 gate insulation for enhancing breakdown voltage of AlN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Deen, D. A.; Storm, D. F.; Bass, R.; Meyer, D. J.; Katzer, D. S.; Binari, S. C.; Lacis, J. W.; Gougousi, T.

2011-01-01

AlN/GaN heterostructures with a 3.5 nm AlN cap have been grown by molecular beam epitaxy followed by a 6 nm thick atomic layer deposited Ta2O5 film. Transistors fabricated with 150 nm length gates showed drain current density of 1.37 A/mm, transconductance of 315 mS/mm, and sustained drain-source biases up to 96 V while in the off-state before destructive breakdown as a result of the Ta2O5 gate insulator. Terman's method has been modified for the multijunction capacitor and allowed the measurement of interface state density (˜1013 cm-2 eV-1). Small-signal frequency performance of 75 and 115 GHz was obtained for ft and fmax, respectively.

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Performance analysis of SiGe double-gate N-MOSFET

NASA Astrophysics Data System (ADS)

Singh, A.; Kapoor, D.; Sharma, R.

2017-04-01

The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET. The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool. Moreover, we have designed its structure and studied both {I}{{d}}{-}{V}{{g}} characteristics for different voltages namely 0.05, 0.1, 0.5, 0.8, 1 and 1.5 V and {I}{{d}}{-}{V}{{d}} characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.

Building America Case Study: Monitoring of Double Stud Wall Moisture Conditions in the Northeast, Devens, Massachusetts (Fact Sheet)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

2015-03-01

Double-stud walls insulated with cellulose or low-density spray foam can have R-values of 40 or higher. However, double stud walls have a higher risk of interior-sourced condensation moisture damage, when compared with high-R approaches using exterior insulating sheathing. Moisture conditions in double stud walls were monitored in Zone 5A (Massachusetts); three double stud assemblies were compared.

An X-Band SOS Resistive Gate-Insulator-Semiconductor /RIS/ switch

NASA Astrophysics Data System (ADS)

Kwok, S. P.

1980-02-01

The new X-Band Resistive Gate-Insulator-Semiconductor (RIS) switch has been fabricated on silicon-on-sapphire, and its equivalent circuit model characterized. An RIS SPST switch with 20-dB on/off isolation, 1.2-dB insertion loss, and power handling capacity in excess of 20-W peak has been achieved at X band. The device switching time is on the order of 600 ns, and it requires negligible control holding current in both on and off states. The device is compatible with monolithic integrated-circuit technology and thus is suitable for integration into low-cost monolithic phase shifters or other microwave integrated circuits.

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Kawamura, Yumi; Tani, Mai; Hattori, Nozomu; Miyatake, Naomasa; Horita, Masahiro; Ishikawa, Yasuaki; Uraoka, Yukiharu

2012-02-01

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

Enhancement of electrical transport modulation in epitaxial VO2 nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Tanaka, Hidekazu; Chikanari, Masashi; Kanki, Teruo

Strongly correlated system vanadium dioxide VO2 has attracted widespread concerns from researchers as an exciting electronic material, due to the many intriguing features, especially metal-insulator transition (MIT) in vicinity of room temperature. In this work, we report a diverse geometry for high sensitivity in the transport modulation. By taking advantage of nanometer scale channel, instead of thin film channels, we demonstrated the enhancement of resistance modulation by applying gate voltage. Also we designed the insulating gate, consisting of high-k material Ta2O5/organic polymer parylene-C hybrid insulator. Such as this hybrid gate dielectric would effectively reduce interface deterioration of active channel oxide and provide sufficient carrier density. Moreover, benefited from the nanometer scale channel, the VO2 nanowire-based transistor could deliver a resistance modulation ratio over 8.5%, which are about 10 folds higher than that of the film case. Furthermore, this result is explained that in spite of the stronger field distribution in the edge parts of VO2 nanowire channel yielded little carrier density, the generated mobility modulation would biquadratic increase according to Brinkman-Rice picture as new finding.

Full superconducting dome of strong Ising protection in gated monolayer WS2.

PubMed

Lu, Jianming; Zheliuk, Oleksandr; Chen, Qihong; Leermakers, Inge; Hussey, Nigel E; Zeitler, Uli; Ye, Jianting

2018-04-03

Many recent studies show that superconductivity not only exists in atomically thin monolayers but can exhibit enhanced properties such as a higher transition temperature and a stronger critical field. Nevertheless, besides being unstable in air, the weak tunability in these intrinsically metallic monolayers has limited the exploration of monolayer superconductivity, hindering their potential in electronic applications (e.g., superconductor-semiconductor hybrid devices). Here we show that using field effect gating, we can induce superconductivity in monolayer WS 2 grown by chemical vapor deposition, a typical ambient-stable semiconducting transition metal dichalcogenide (TMD), and we are able to access a complete set of competing electronic phases over an unprecedented doping range from band insulator, superconductor, to a reentrant insulator at high doping. Throughout the superconducting dome, the Cooper pair spin is pinned by a strong internal spin-orbit interaction, making this material arguably the most resilient superconductor in the external magnetic field. The reentrant insulating state at positive high gating voltages is attributed to localization induced by the characteristically weak screening of the monolayer, providing insight into many dome-like superconducting phases observed in field-induced quasi-2D superconductors.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Dirac-electron-mediated magnetic proximity effect in topological insulator/magnetic insulator heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Mingda; Song, Qichen; Zhao, Weiwei

The possible realization of dissipationless chiral edge current in a topological insulator/magnetic insulator heterostructure is based on the condition that the magnetic proximity exchange coupling at the interface is dominated by the Dirac surface states of the topological insulator. We report a polarized neutron reflectometry observation of Dirac-electron-mediated magnetic proximity effect in a bulk-insulating topological insulator (Bi 0.2Sb 0.8) 2Te 3/magnetic insulator EuS heterostructure. We are able to maximize the proximity-induced magnetism by applying an electrical back gate to tune the Fermi level of topological insulator to be close to the Dirac point. A phenomenological model based on diamagnetic screeningmore » is developed to explain the suppressed proximity-induced magnetism at high carrier density. Our work paves the way to utilize the magnetic proximity effect at the topological insulator/magnetic insulator heterointerface for low-power spintronic applications.« less

Dirac-electron-mediated magnetic proximity effect in topological insulator/magnetic insulator heterostructures

DOE PAGES

Li, Mingda; Song, Qichen; Zhao, Weiwei; ...

2017-11-01

The possible realization of dissipationless chiral edge current in a topological insulator/magnetic insulator heterostructure is based on the condition that the magnetic proximity exchange coupling at the interface is dominated by the Dirac surface states of the topological insulator. We report a polarized neutron reflectometry observation of Dirac-electron-mediated magnetic proximity effect in a bulk-insulating topological insulator (Bi 0.2Sb 0.8) 2Te 3/magnetic insulator EuS heterostructure. We are able to maximize the proximity-induced magnetism by applying an electrical back gate to tune the Fermi level of topological insulator to be close to the Dirac point. A phenomenological model based on diamagnetic screeningmore » is developed to explain the suppressed proximity-induced magnetism at high carrier density. Our work paves the way to utilize the magnetic proximity effect at the topological insulator/magnetic insulator heterointerface for low-power spintronic applications.« less

49 CFR Appendix A to Part 234 - Schedule of Civil Penalties 1

Code of Federal Regulations, 2010 CFR

2010-10-01

....219Gate arm lights and light cable 1,000 2,000 234.221Lamp voltage 1,000 2,000 234.223Gate arm 1,000 2,000... 234.251Standby power 5,000 7,500 234.253Flashing light units and lamp voltage 1,000 2,000 234.255Gate....265Timing relays and timing devices 1,000 2,000 234.267Insulation resistance tests, wires in trunking and...

Resistance noise in epitaxial thin films of ferromagnetic topological insulators

NASA Astrophysics Data System (ADS)

Bhattacharyya, Semonti; Kandala, Abhinav; Richardella, Anthony; Islam, Saurav; Samarth, Nitin; Ghosh, Arindam

2016-02-01

We report detailed temperature and gate-voltage dependence of 1/f resistance noise in magnetically doped topological insulators (TI) Crx(Bi,Sb)2-xTe3. The noise is remarkably sensitive to the gate voltage, increasing rapidly as the chemical potential is moved towards the charge neutrality point. Unlike in identically prepared (Bi,Sb)2Te3 films, where mobility-fluctuations in the surface states is the dominant mechanism, the noise in the magnetic Crx(Bi,Sb)2-xTe3 originates from transport in the localized band tail of the bulk valence band. A strong increase in noise with decreasing temperature supports this scenario. At higher temperature (≥10 K), we observed large noise peaks at gate voltage-dependent characteristic temperature scales. In line with similar observations in other non-magnetic TI systems, we attribute these peaks to generation-recombination in the Cr-impurity band.

Memory operation mechanism of fullerene-containing polymer memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakajima, Anri, E-mail: anakajima@hiroshima-u.ac.jp; Fujii, Daiki

2015-03-09

The memory operation mechanism in fullerene-containing nanocomposite gate insulators was investigated while varying the kind of fullerene in a polymer gate insulator. It was cleared what kind of traps and which positions in the nanocomposite the injected electrons or holes are stored in. The reason for the difference in the easiness of programming was clarified taking the role of the charging energy of an injected electron into account. The dependence of the carrier dynamics on the kind of fullerene molecule was investigated. A nonuniform distribution of injected carriers occurred after application of a large magnitude programming voltage due to themore » width distribution of the polystyrene barrier between adjacent fullerene molecules. Through the investigations, we demonstrated a nanocomposite gate with fullerene molecules having excellent retention characteristics and a programming capability. This will lead to the realization of practical organic memories with fullerene-containing polymer nanocomposites.« less

Gate-Tunable Spin Transport and Giant Electroresistance in Ferromagnetic Graphene Vertical Heterostructures

PubMed Central

Myoung, Nojoon; Park, Hee Chul; Lee, Seung Joo

2016-01-01

Controlling tunneling properties through graphene vertical heterostructures provides advantages in achieving large conductance modulation which has been known as limitation in lateral graphene device structures. Despite of intensive research on graphene vertical heterosturctures for recent years, the potential of spintronics based on graphene vertical heterostructures remains relatively unexplored. Here, we present an analytical device model for graphene-based spintronics by using ferromagnetic graphene in vertical heterostructures. We consider a normal or ferroelectric insulator as a tunneling layer. The device concept yields a way of controlling spin transport through the vertical heterostructures, resulting in gate-tunable spin-switching phenomena. Also, we revealed that a ‘giant’ resistance emerges through a ferroelectric insulating layer owing to the anti-parallel configuration of ferromagnetic graphene layers by means of electric fields via gate and bias voltages. Our findings discover the prospect of manipulating the spin transport properties in vertical heterostructures without use of magnetic fields. PMID:27126101

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Double layered tailorable advanced blanket insulation

NASA Technical Reports Server (NTRS)

Falstrup, D.

1983-01-01

An advanced flexible reusable surface insulation material for future space shuttle flights was investigated. A conventional fly shuttle loom with special modifications to weave an integral double layer triangular core fabric from quartz yarn was used. Two types of insulating material were inserted into the cells of the fabric, and a procedure to accomplish this was developed. The program is follow up of a program in which single layer rectangular cell core fabrics are woven and a single type of insulating material was inserted into the cells.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Robust Deterministic Controlled Phase-Flip Gate and Controlled-Not Gate Based on Atomic Ensembles Embedded in Double-Sided Optical Cavities

NASA Astrophysics Data System (ADS)

Liu, A.-Peng; Cheng, Liu-Yong; Guo, Qi; Zhang, Shou

2018-02-01

We first propose a scheme for controlled phase-flip gate between a flying photon qubit and the collective spin wave (magnon) of an atomic ensemble assisted by double-sided cavity quantum systems. Then we propose a deterministic controlled-not gate on magnon qubits with parity-check building blocks. Both the gates can be accomplished with 100% success probability in principle. Atomic ensemble is employed so that light-matter coupling is remarkably improved by collective enhancement. We assess the performance of the gates and the results show that they can be faithfully constituted with current experimental techniques.

Electric Field Distribution in High Voltage Power Modules Using Finite Element Simulations

NASA Astrophysics Data System (ADS)

Wang, Zhao; Liu, Yaoning

2018-03-01

With the development of the high voltage insulated gate bipolar transistor (IGBT) power module, it leads to serious problems concerning the electric field insulation. The electric field capabilities of the silicone gels used in the power module encapsulation directly affect the module insulation. Some solutions have been developed to optimize the electric field and reliability. In this letter, the finite element simulation was used to analyze and localize the maximum electric field position; solutions were proposed to improve the module insulation. It’s demonstrated that BaTiO3 silicone composite is a promising insulation material for high voltage power device.

Solid-state non-volatile electronically programmable reversible variable resistance device

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

1989-01-01

A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

A High Temperature Silicon Carbide mosfet Power Module With Integrated Silicon-On-Insulator-Based Gate Drive

DOE PAGES

Wang, Zhiqiang; Shi, Xiaojie; Tolbert, Leon M.; ...

2014-04-30

Here we present a board-level integrated silicon carbide (SiC) MOSFET power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200°C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate drivermore » and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225°C.« less

Ferroelectric control of a Mott insulator

PubMed Central

Yamada, Hiroyuki; Marinova, Maya; Altuntas, Philippe; Crassous, Arnaud; Bégon-Lours, Laura; Fusil, Stéphane; Jacquet, Eric; Garcia, Vincent; Bouzehouane, Karim; Gloter, Alexandre; Villegas, Javier E.; Barthélémy, Agnès; Bibes, Manuel

2013-01-01

The electric field control of functional properties is an important goal in oxide-based electronics. To endow devices with memory, ferroelectric gating is interesting, but usually weak compared to volatile electrolyte gating. Here, we report a very large ferroelectric field-effect in perovskite heterostructures combining the Mott insulator CaMnO3 and the ferroelectric BiFeO3 in its “supertetragonal” phase. Upon polarization reversal of the BiFeO3 gate, the CaMnO3 channel resistance shows a fourfold variation around room temperature, and a tenfold change at ~200 K. This is accompanied by a carrier density modulation exceeding one order of magnitude. We have analyzed the results for various CaMnO3 thicknesses and explain them by the electrostatic doping of the CaMnO3 layer and the presence of a fixed dipole at the CaMnO3/BiFeO3 interface. Our results suggest the relevance of ferroelectric gates to control orbital- or spin-ordered phases, ubiquitous in Mott systems, and pave the way toward efficient Mott-tronics devices. PMID:24089020

Side-gate modulation effects on high-quality BN-Graphene-BN nanoribbon capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yang; Chen, Xiaolong; Ye, Weiguang

High-quality BN-Graphene-BN nanoribbon capacitors with double side-gates of graphene have been experimentally realized. The double side-gates can effectively modulate the electronic properties of graphene nanoribbon capacitors. By applying anti-symmetric side-gate voltages, we observed significant upward shifting and flattening of the V-shaped capacitance curve near the charge neutrality point. Symmetric side-gate voltages, however, only resulted in tilted upward shifting along the opposite direction of applied gate voltages. These modulation effects followed the behavior of graphene nanoribbons predicted theoretically for metallic side-gate modulation. The negative quantum capacitance phenomenon predicted by numerical simulations for graphene nanoribbons modulated by graphene side-gates was not observed,more » possibly due to the weakened interactions between the graphene nanoribbon and side-gate electrodes caused by the Ga{sup +} beam etching process.« less

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Method for disclosing invisible physical properties in metal-ferroelectric-insulator-semiconductor gate stacks

NASA Astrophysics Data System (ADS)

Sakai, Shigeki; Zhang, Wei; Takahashi, Mitsue

2017-04-01

In metal-ferroelectric-insulator-semiconductor gate stacks of ferroelectric-gate field effect transistors (FeFETs), it is impossible to directly obtain curves of polarization versus electric field (P f-E f) in the ferroelectric layer. The P f-E f behavior is not simple, i.e. the P f-E f curves are hysteretic and nonlinear, and the hysteresis curve width depends on the electric field scan amplitude. Unless the P f-E f relation is known, the field E f strength cannot be solved when the voltage is applied between the gate meal and the semiconductor substrate, and thus P f-E f cannot be obtained after all. In this paper, the method for disclosing the relationships among the polarization peak-to-peak amplitude (2P mm_av), the electric field peak-to-peak amplitude (2E mm_av), and the memory window (E w) in units of the electric field is presented. To get P mm_av versus E mm_av, FeFETs with different ferroelectric-layer thicknesses should be prepared. Knowing such essential physical parameters is helpful and in many cases enough to quantitatively understand the behavior of FeFETs. The method is applied to three groups. The first one consists of SrBi2Ta2O9-based FeFETs. The second and third ones consist of Ca x Sr1-x Bi2Ta2O9-based FeFETs made by two kinds of annealing. The method can clearly differentiate the characters of the three groups. By applying the method, ferroelectric relationships among P mm_av, E mm_av, and E w are well classified in the three groups according to the difference of the material kinds and the annealing conditions. The method also evaluates equivalent oxide thickness (EOT) of a dual layer of a deposited high-k insulator and a thermally-grown SiO2-like interfacial layer (IL). The IL thickness calculated by the method is consistent with cross-sectional image of the FeFETs observed by a transmission electron microscope. The method successfully discloses individual characteristics of the ferroelectric and the insulator layers hidden in the gate stack of a FeFET.

Gas-controlled dynamic vacuum insulation with gas gate

DOEpatents

Benson, David K.; Potter, Thomas F.

1994-06-07

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber.

Gas-controlled dynamic vacuum insulation with gas gate

DOEpatents

Benson, D.K.; Potter, T.F.

1994-06-07

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber. 25 figs.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kwon, Dae Woong; Kim, Jang Hyun; Chang, Ji Soo; Kim, Sang Wan; Sun, Min-Chul; Kim, Garam; Kim, Hyun Woo; Park, Jae Chul; Song, Ihun; Kim, Chang Jung; Jung, U. In; Park, Byung-Gook

2010-11-01

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET

DTIC Science & Technology

2016-02-04

Metal insulator semiconductor AlGaN /GaN high electron mobility transistors (MISHEMTs) are promising for power device applications due to a lower leakage...current than the conventional Schottky AlGaN/GaN HEMTs.1–3 Among a large number of insulator materials, an Al2O3 dielectric layer, deposited by...atomic layer deposition (ALD), is often employed as the gate insulator because of a large band gap (and the resultant high conduction band offset on

Spin measurement in an undoped Si/SiGe double quantum dot incorporating a micromagnet

NASA Astrophysics Data System (ADS)

Wu, Xian; Ward, Daniel; Prance, Jonathan; Kim, Dohun; Shi, Zhan; Mohr, Robert; Gamble, John; Savage, Donald; Lagally, Max; Friesen, Mark; Coppersmith, Susan; Eriksson, Mark

2014-03-01

We present measurements on a double dot formed in an accumulation-mode undoped Si/SiGe heterostructure. The double dot incorporates a proximal micromagnet to generate a stable magnetic field difference between the quantum dots. The gate design incorporates two layers of gates, and the upper layer of gates is split into five different sections to decrease crosstalk between different gates. A novel pattern of the lower layer gates enhances the tunability of tunnel rates. We will describe our attempts to create a singlet-triplet qubit in this device. This work was supported in part by ARO(W911NF-12-0607), NSF(DMR-1206915), and the United States Department of Defense. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government. Now works at Lancaster University, UK.

Vortices and gate-tunable bound states in a topological insulator coupled to superconducting leads

NASA Astrophysics Data System (ADS)

Finck, Aaron; Kurter, C.; Hor, Y. S.; van Harlingen, D. J.

2014-03-01

It has been predicted that zero energy Majorana bound states can be found in the core of vortices within topological superconductors. Here, we report on Andreev spectroscopy measurements of the topological insulator Bi2Se3 with a normal metal lead and one or more niobium leads. The niobium induces superconductivity in the Bi2Se3 through the proximity effect, leading to both signatures of Andreev reflection and a prominent re-entrant resistance effect. When a large magnetic field is applied perpendicular to the surface of the Bi2Se3, we observe multiple abrupt changes in the subgap conductance that are accompanied by sharp peaks in the dynamical resistance. These peaks are very sensitive to changes in magnetic field and disappear at temperatures associated with the critical temperature of the induced superconductivity. The appearance of the transitions and peaks can be tuned by a top gate. At high magnetic fields, we also find evidence of gate-tunable states, which can lead to stable zero-bias conductance peaks. We interpret our results in terms of a transition occurring within the proximity effect region of the topological insulator, likely due to the formation of vortices. We acknowledge support from Microsoft Project Q.

Investigation of pentacene growth on SiO2 gate insulator after photolithography for nitrogen-doped LaB6 bottom-contact electrode formation

NASA Astrophysics Data System (ADS)

Maeda, Yasutaka; Hiroki, Mizuha; Ohmi, Shun-ichiro

2018-04-01

Nitrogen-doped (N-doped) LaB6 is a candidate material for the bottom-contact electrode of n-type organic field-effect transistors (OFETs). However, the formation of a N-doped LaB6 electrode affects the surface morphology of a pentacene film. In this study, the effects of surface treatments and a N-doped LaB6 interfacial layer (IL) were investigated to improve the pentacene film quality after N-doped LaB6 electrode patterning with diluted HNO3, followed by resist stripping with acetone and methanol. It was found that the sputtering damage during N-doped LaB6 deposition on a SiO2 gate insulator degraded the crystallinity of pentacene. The H2SO4 and H2O2 (SPM) and diluted HF treatments removed the damaged layer on the SiO2 gate insulator surface. Furthermore, the N-doped LaB6 IL improved the crystallinity of pentacene and realized dendritic grain growth. Owing to these surface treatments, the hole mobility improved from 2.8 × 10-3 to 0.11 cm2/(V·s), and a steep subthreshold swing of 78 mV/dec for the OFET with top-contact configuration was realized in air even after bottom-contact electrode patterning.

Solution-derived SiO2 gate insulator formed by CO2 laser annealing for polycrystalline silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Hishitani, Daisuke; Horita, Masahiro; Ishikawa, Yasuaki; Ikenoue, Hiroshi; Uraoka, Yukiharu

2017-05-01

The formation of perhydropolysilazane (PHPS)-based SiO2 films by CO2 laser annealing is proposed. Irradiation with a CO2 laser with optimum fluence transformed a prebaked PHPS film into a SiO2 film with uniform composition in the thickness direction. Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a SiO2 film as the gate insulator were fabricated. When the SiO2 film was formed by CO2 laser annealing (CO2LA) at the optimum fluence of 20 mJ/cm2, the film had fewer OH groups which was one-twentieth that of the furnace annealed PHPS film and one-hundredth that of the SiO2 film deposited by plasma-enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS). The resulting TFTs using PHPS showed a clear transistor operation with a field-effect mobility of 37.9 ± 1.2 cm2 V-1 s-1, a threshold voltage of 9.8 ± 0.2 V, and a subthreshold swing of 0.76 ± 0.02 V/decade. The characteristics of such TFTs were as good as those of a poly-Si TFT with a SiO2 gate insulator prepared by PECVD using TEOS.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

NASA Astrophysics Data System (ADS)

Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

2016-02-01

A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

NASA Astrophysics Data System (ADS)

Xue, Peng; Fu, Guicui

2017-03-01

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT's dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT's clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT's dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT's experimental results implies that the CSTBT's abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT's abnormal dynamic avalanche mechanism. Moreover, the CSTBT's negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT's dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Rapid construction of insulated genetic circuits via synthetic sequence-guided isothermal assembly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Torella, JP; Boehm, CR; Lienert, F

2013-12-28

In vitro recombination methods have enabled one-step construction of large DNA sequences from multiple parts. Although synthetic biological circuits can in principle be assembled in the same fashion, they typically contain repeated sequence elements such as standard promoters and terminators that interfere with homologous recombination. Here we use a computational approach to design synthetic, biologically inactive unique nucleotide sequences (UNSes) that facilitate accurate ordered assembly. Importantly, our designed UNSes make it possible to assemble parts with repeated terminator and insulator sequences, and thereby create insulated functional genetic circuits in bacteria and mammalian cells. Using UNS-guided assembly to construct repeating promoter-gene-terminatormore » parts, we systematically varied gene expression to optimize production of a deoxychromoviridans biosynthetic pathway in Escherichia coli. We then used this system to construct complex eukaryotic AND-logic gates for genomic integration into embryonic stem cells. Construction was performed by using a standardized series of UNS-bearing BioBrick-compatible vectors, which enable modular assembly and facilitate reuse of individual parts. UNS-guided isothermal assembly is broadly applicable to the construction and optimization of genetic circuits and particularly those requiring tight insulation, such as complex biosynthetic pathways, sensors, counters and logic gates.« less

Ambipolar surface state thermoelectric power of topological insulator Bi2Se3.

PubMed

Kim, Dohun; Syers, Paul; Butch, Nicholas P; Paglione, Johnpierre; Fuhrer, Michael S

2014-01-01

We measure gate-tuned thermoelectric power of mechanically exfoliated Bi2Se3 thin films in the topological insulator regime. The sign of the thermoelectric power changes across the charge neutrality point as the majority carrier type switches from electron to hole, consistent with the ambipolar electric field effect observed in conductivity and Hall effect measurements. Near the charge neutrality point and at low temperatures, the gate-dependent thermoelectric power follows the semiclassical Mott relation using the expected surface state density of states but is larger than expected at high electron doping, possibly reflecting a large density of states in the bulk gap. The thermoelectric power factor shows significant enhancement near the electron-hole puddle carrier density ∼0.5 × 10(12) cm(-2) per surface at all temperatures. Together with the expected reduction of lattice thermal conductivity in low-dimensional structures, the results demonstrate that nanostructuring and Fermi level tuning of three-dimensional topological insulators can be promising routes to realize efficient thermoelectric devices.

Selective area deposited n-Al0.5Ga0.5N channel field effect transistors with high solar-blind ultraviolet photo-responsivity

NASA Astrophysics Data System (ADS)

Muhtadi, S.; Hwang, S.; Coleman, A.; Asif, F.; Lunev, A.; Chandrashekhar, M. V. S.; Khan, A.

2017-04-01

We report on AlGaN field effect transistors over AlN/sapphire templates with selective area grown n-Al0.5Ga0.5N channel layers for which a field-effect mobility of 55 cm2/V-sec was measured. Using a pulsed plasma enhanced chemical vapor deposition deposited 100 A thick SiO2 layer as the gate-insulator, the gate-leakage currents were reduced by three orders of magnitude. These devices with or without gate insulators are excellent solar-blind ultraviolet detectors, and they can be operated either in the photoconductive or the photo-voltaic modes. In the photo-conductive mode, gain arising from hole-trapping in the depletion region leads to steady-state photoresponsivity as high as 1.2 × 106A/W at 254 nm, which drops sharply below 290 nm. A hole-trapping limited detector response time of 34 ms, fast enough for real-time flame-detection and imaging applications, was estimated.

Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

NASA Astrophysics Data System (ADS)

Chatterjee, Sulagna; Chattopadhyay, Sanatan

2016-10-01

An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

Effects of trap density on drain current LFN and its model development for E-mode GaN MOS-HEMT

NASA Astrophysics Data System (ADS)

Panda, D. K.; Lenka, T. R.

2017-12-01

In this paper the drain current low-frequency noise (LFN) of E-mode GaN MOS-HEMT is investigated for different gate insulators such as SiO2, Al2O3/Ga2O3/GdO3, HfO2/SiO2, La2O3/SiO2 and HfO2 with different trap densities by IFM based TCAD simulation. In order to analyze this an analytical model of drain current low frequency noise is developed. The model is developed by considering 2DEG carrier fluctuations, mobility fluctuations and the effects of 2DEG charge carrier fluctuations on the mobility. In the study of different gate insulators it is observed that carrier fluctuation is the dominant low frequency noise source and the non-uniform exponential distribution is critical to explain LFN behavior, so the analytical model is developed by considering uniform distribution of trap density. The model is validated with available experimental data from literature. The effect of total number of traps and gate length scaling on this low frequency noise due to different gate dielectrics is also investigated.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

All-electric spin modulator based on a two-dimensional topological insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiao, Xianbo; Ai, Guoping; Liu, Ying

2016-01-18

We propose and investigate a spin modulator device consisting of two ferromagnetic leads connected by a two-dimensional topological insulator as the channel material. It exploits the unique features of the topological spin-helical edge states, such that the injected carriers with a non-collinear spin-polarization direction would travel through both edges and show interference effect. The conductance of the device can be controlled in a simple and all-electric manner by a side-gate voltage, which effectively rotates the spin-polarization of the carrier. At low voltages, the rotation angle is linear in the gate voltage, and the device can function as a good spin-polarizationmore » rotator by replacing the drain electrode with a non-magnetic material.« less

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Gate tunable parallel double quantum dots in InAs double-nanowire devices

NASA Astrophysics Data System (ADS)

Baba, S.; Matsuo, S.; Kamata, H.; Deacon, R. S.; Oiwa, A.; Li, K.; Jeppesen, S.; Samuelson, L.; Xu, H. Q.; Tarucha, S.

2017-12-01

We report fabrication and characterization of InAs nanowire devices with two closely placed parallel nanowires. The fabrication process we develop includes selective deposition of the nanowires with micron scale alignment onto predefined finger bottom gates using a polymer transfer technique. By tuning the double nanowire with the finger bottom gates, we observed the formation of parallel double quantum dots with one quantum dot in each nanowire bound by the normal metal contact edges. We report the gate tunability of the charge states in individual dots as well as the inter-dot electrostatic coupling. In addition, we fabricate a device with separate normal metal contacts and a common superconducting contact to the two parallel wires and confirm the dot formation in each wire from comparison of the transport properties and a superconducting proximity gap feature for the respective wires. With the fabrication techniques established in this study, devices can be realized for more advanced experiments on Cooper-pair splitting, generation of Parafermions, and so on.

Electrophoretic-like gating used to control metal-insulator transitions in electronically phase separated manganite wires.

PubMed

Guo, Hangwen; Noh, Joo H; Dong, Shuai; Rack, Philip D; Gai, Zheng; Xu, Xiaoshan; Dagotto, Elbio; Shen, Jian; Ward, T Zac

2013-08-14

Electronically phase separated manganite wires are found to exhibit controllable metal-insulator transitions under local electric fields. The switching characteristics are shown to be fully reversible, polarity independent, and highly resistant to thermal breakdown caused by repeated cycling. It is further demonstrated that multiple discrete resistive states can be accessed in a single wire. The results conform to a phenomenological model in which the inherent nanoscale insulating and metallic domains are rearranged through electrophoretic-like processes to open and close percolation channels.

Dual-gate GaAs FET switches

NASA Astrophysics Data System (ADS)

Vorhaus, J. L.; Fabian, W.; Ng, P. B.; Tajima, Y.

1981-02-01

A set of multi-pole, multi-throw switch devices consisting of dual-gate GaAs FET's is described. Included are single-pole, single-throw (SPST), double-pole, double-throw (DPDT), and single-pole four-throw (SP4T) switches. Device fabrication and measurement techniques are discussed. The device models for these switches were based on an equivalent circuit of a dual-gate FET. The devices were found to have substantial gain in X-band and low Ku-band.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

NASA Astrophysics Data System (ADS)

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of -37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays.

Quantum and Classical Magnetoresistance in Ambipolar Topological Insulator Transistors with Gate-tunable Bulk and Surface Conduction

PubMed Central

Tian, Jifa; Chang, Cuizu; Cao, Helin; He, Ke; Ma, Xucun; Xue, Qikun; Chen, Yong P.

2014-01-01

Weak antilocalization (WAL) and linear magnetoresistance (LMR) are two most commonly observed magnetoresistance (MR) phenomena in topological insulators (TIs) and often attributed to the Dirac topological surface states (TSS). However, ambiguities exist because these phenomena could also come from bulk states (often carrying significant conduction in many TIs) and are observable even in non-TI materials. Here, we demonstrate back-gated ambipolar TI field-effect transistors in (Bi0.04Sb0.96)2Te3 thin films grown by molecular beam epitaxy on SrTiO3(111), exhibiting a large carrier density tunability (by nearly 2 orders of magnitude) and a metal-insulator transition in the bulk (allowing switching off the bulk conduction). Tuning the Fermi level from bulk band to TSS strongly enhances both the WAL (increasing the number of quantum coherent channels from one to peak around two) and LMR (increasing its slope by up to 10 times). The SS-enhanced LMR is accompanied by a strongly nonlinear Hall effect, suggesting important roles of charge inhomogeneity (and a related classical LMR), although existing models of LMR cannot capture all aspects of our data. Our systematic gate and temperature dependent magnetotransport studies provide deeper insights into the nature of both MR phenomena and reveal differences between bulk and TSS transport in TI related materials. PMID:24810663

Surface Engineering of Polycrystalline Silicon for Long-Term Mechanical Stress Endurance Enhancement in Flexible Low-Temperature Poly-Si Thin-Film Transistors.

PubMed

Chen, Bo-Wei; Chang, Ting-Chang; Chang, Kuan-Chang; Hung, Yu-Ju; Huang, Shin-Ping; Chen, Hua-Mao; Liao, Po-Yung; Lin, Yu-Ho; Huang, Hui-Chun; Chiang, Hsiao-Cheng; Yang, Chung-I; Zheng, Yu-Zhe; Chu, Ann-Kuo; Li, Hung-Wei; Tsai, Chih-Hung; Lu, Hsueh-Hsing; Wang, Terry Tai-Jui; Chang, Tsu-Chiang

2017-04-05

The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

PubMed Central

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

Abstract The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of −37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays. PMID:27877886

Multiple and configurable optical logic systems based on layered double hydroxides and chromophore assemblies.

PubMed

Shi, Wenying; Fu, Yi; Li, Zhixiong; Wei, Min

2015-01-14

Multiple and configurable fluorescence logic gates were fabricated via self-assembly of layered double hydroxides and various chromophores. These logic gates were operated by observation of different emissions with the same excitation wavelength, which achieve YES, NOT, AND, INH and INHIBIT logic operations, respectively.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Effects of structure and oxygen flow rate on the photo-response of amorphous IGZO-based photodetector devices

NASA Astrophysics Data System (ADS)

Jang, Jun Tae; Ko, Daehyun; Choi, Sungju; Kang, Hara; Kim, Jae-Young; Yu, Hye Ri; Ahn, Geumho; Jung, Haesun; Rhee, Jihyun; Lee, Heesung; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan

2018-02-01

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Reducing DNA context dependence in bacterial promoters

PubMed Central

Carr, Swati B.; Densmore, Douglas M.

2017-01-01

Variation in the DNA sequence upstream of bacterial promoters is known to affect the expression levels of the products they regulate, sometimes dramatically. While neutral synthetic insulator sequences have been found to buffer promoters from upstream DNA context, there are no established methods for designing effective insulator sequences with predictable effects on expression levels. We address this problem with Degenerate Insulation Screening (DIS), a novel method based on a randomized 36-nucleotide insulator library and a simple, high-throughput, flow-cytometry-based screen that randomly samples from a library of 436 potential insulated promoters. The results of this screen can then be compared against a reference uninsulated device to select a set of insulated promoters providing a precise level of expression. We verify this method by insulating the constitutive, inducible, and repressible promotors of a four transcriptional-unit inverter (NOT-gate) circuit, finding both that order dependence is largely eliminated by insulation and that circuit performance is also significantly improved, with a 5.8-fold mean improvement in on/off ratio. PMID:28422998

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Tian-Li, E-mail: Tian-Li.Wu@imec.be; Groeseneken, Guido; Department of Electrical Engineering, KU Leuven, Leuven

2015-08-31

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g{sub m}), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si{sub 3}N{sub 4}, Rapid Thermal Chemical Vapor Deposition Si{sub 3}N{sub 4}, and Atomic Layer Deposition (ALD) Al{sub 2}O{sub 3}) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D{sub it}), the amount of border traps, and the threshold voltage (V{sub TH}) shift during a positive gate bias stress can be obtained. The results show that the V{sub TH} shift during a positive gate bias stress ismore » highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V{sub TH} shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D{sub it} needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g{sub m} dispersion commonly attributed to border traps might be influenced by interface states.« less

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Razavi, S. M.; Ebrahim Hosseini, Seyed; Amini Moghadam, Hamid

2011-11-01

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

Origin of positive fixed charge at insulator/AlGaN interfaces and its control by AlGaN composition

NASA Astrophysics Data System (ADS)

Matys, M.; Stoklas, R.; Blaho, M.; Adamowicz, B.

2017-06-01

The key feature for the precise tuning of Vth in GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors is the control of the positive fixed charge (Qf) at the insulator/III-N interfaces, whose amount is often comparable to the negative surface polarization charge ( Qp o l -). In order to clarify the origin of Qf, we carried out a comprehensive capacitance-voltage (C-V) characterization of SiO2/AlxGa1-xN/GaN and SiN/AlxGa1-xN/GaN structures with Al composition (x) varying from 0.15 to 0.4. For both types of structures, we observed a significant Vth shift in C-V curves towards the positive gate voltage with increasing x. On the contrary, the Schottky gate structures exhibited Vth shift towards the more negative biases. From the numerical simulations of C-V curves using the Poisson's equation supported by the analytical calculations of Vth, we showed that the Vth shift in the examined MIS structures is due to a significant decrease in the positive Qf with rising x. Finally, we examined this result with respect to various hypotheses developed in the literature to explain the origin of the positive Qf at insulator/III-N interfaces.

Quantum Hall effect in dual gated BiSbTeSe2 topological insulator

NASA Astrophysics Data System (ADS)

Chong, Su Kong; Han, Kyu Bum; Nagaoka, Akira; Harmer, Jared; Tsuchikawa, Ryuichi; Sparks, Taylor D.; Deshpande, Vikram V.

The discovery of topological insulators (TIs) has expanded the family of Dirac materials and enables the probing of exotic matter such as Majorana fermions and magnetic monopoles. Different from conventional 2D electron gas, 3D TIs exhibit a gapped insulating bulk and gapless topological surface states as a result of the strong spin-orbit coupling. BiSbTeSe2 is also known to be a 3D TI with a large intrinsic bulk gap of about 0.3 eV and a single Dirac cone surface state. The highly bulk insulating BiSbTeSe2 permits surface dominated conduction, which is an ideal system for the study of quantum Hall effect (QHE). Due to the spin-momentum locking, the Dirac fermions at the topological surface states have a degeneracy of one. In the QH regime, the Hall conductance is quantized to (n + 1 / 2) e2 / h , where n is an integer and the factor of half is related to Berry curvature. In this work, we study the QHE 3D TI using a dual gated BiSbTeSe2 device. By tuning the chemical potentials on top and bottom surfaces, integer QHE with Landau filling factors, ν = 0, +/-1, and +/-2 are observed.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

NASA Astrophysics Data System (ADS)

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito; Fujii, Eiji; Tsujimura, Ayumu

2013-04-01

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Determination of Thermal Transmittance of Insulated Double Low-E Glazing Panel Using Portable Uglass Measuring Technique

NASA Astrophysics Data System (ADS)

Kim, Inkoo; Frenzl, Alexander; Kim, Taehan; Min, Steven; Blumm, Jürgen

2018-01-01

Windows are regarded as the primary object of energy efficiency in buildings because window is one of the major energy loss areas in building construction. Existing methods were not field measurements and were not enough to get the correct thermal transmittance. We used portable Ug measuring device on field and measured the thermal transmittance with low-E coated and uncoated double glazing panels in existing houses, apartments and buildings. In addition, we prepared four test benches and compared the insulation performance according to the construction conditions. In results, the insulation performance of double glazing panel with low-E coating is up to about 41 % higher than uncoated panel due to low-E coating inside and the glazing panel filled with about 90 % of argon gas decrease about 0.15 W \\cdot m^{-2} \\cdot K^{-1} than glazing panel filled with air gas. The measured results were compared with the theoretically calculated results according to DIN EN 673 to confirm the reliability of the analytical results. In this study, portable NETZSCH Uglass is used to increase the accuracy of calculation of thermal transmittance with various double and triple glazing panels. The paper analyzes the insulation performance of the double glazing panels in accordance with the construction conditions.

Experimental studies on hybrid superconductor-topological insulator nanoribbon Josephson devices

NASA Astrophysics Data System (ADS)

Kayyalha, Morteza; Jauregui, Luis; Kazakov, Aleksander; Miotkowski, Ireneusz; Rokhinson, Leonid; Chen, Yong

The spin-helical topological surface states (TSS) of topological insulators in proximity with an s-wave superconductor are predicted to demonstrate signatures of topological superconductivity and host Majorana fermions. Here, we report on the observation of gate-tunable proximity-induced superconductivity in an intrinsic BiSbTeSe2 topological insulator nanoribbon (TINR) based Josephson junction (JJ) with Nb contacts. We observe a gate-tunable critical current (IC) with an anomalous behavior in the temperature (T) dependence of IC. We discuss various possible scenarios that could be relevant to this anomalous behavior, such as (i) the different temperature dependence of supercurrent generated by in-gap, where phase slip plays an important role, and out-of-gap Andreev bound states or (ii) the different critical temperatures associated with the top and bottom topological surface states. Our modeling of IC vs. T suggests the possible existence of one pair of in-gap Andreev bound states in our TINR. We have also studied the effects of magnetic fields on the critical current in our TINR Josephson junctions.

Effects of trench profile and self-aligned ion implantation on electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs using bottom protection p-well

NASA Astrophysics Data System (ADS)

Seok, Ogyun; Ha, Min-Woo; Kang, In Ho; Kim, Hyoung Woo; Kim, Dong Young; Bahng, Wook

2018-06-01

The effects of a trench profile and self-aligned ion implantation on the electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs employing a bottom protection p-well (BPW) were investigated to improve blocking capability by simulation studies. The trench profile and thickness of a SiO2 spacer during self-aligned ion implantation for BPW affect electrons flow through a trench gate as well as E-field concentration at the gate insulator on a trench bottom. At trench angle higher than 84° and a SiO2 spacer thicker than 0.2 µm showed that the Al concentration penetrated into the trench sidewall during ion implantation is less than 0.3% in comparison with the background doping concentration in a drift region. Under the optimum conditions with a trench angle of 90° and 0.2-µm-thick SiO2 spacer, a high breakdown voltage of 1.45 kV with a low E-field peak in the gate insulator was achieved.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Comparison of conductor and dielectric inks in printed organic complementary transistors

NASA Astrophysics Data System (ADS)

Ng, Tse Nga; Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Abraham, Biby; Wu, Yiliang; Veres, Janos

2014-10-01

Two types of printable conductor and a bilayer gate dielectric are evaluated for use in all-additive, inkjetprinted complementary OTFTs. The Ag nanoparticle ink based on nonpolar alkyl amine surfactant or stabilizer enables good charge injection into p-channel devices, but this ink also leaves residual stabilizer that modifies the transistor backchannel and shifts the turn-on voltage to negative values. The Ag ink based on polar solvent requires dopant modification to improve charge injection to p-channel devices, but this ink allows the OTFT turn-on voltage to be close to 0 V. The reverse trend is observed for n-channel OTFTs. For gate insulator, a bilayer dielectric is demonstrated that combines the advantages of two types of insulator materials, in which a fluoropolymer reduces dipolar disorder at the semiconductor-dielectric interface, while a high-k PVDF terpolymer dielectric facilitates high gate capacitance. The dielectric is incorporated into an inverter and a three-stage ring oscillator, and the resulting circuits were demonstrated to operate at a supply voltage as low as 2 V, with bias stress levels comparable to circuits with other types of dielectrics.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

2 p -insulator heterointerfaces: Creation of half-metallicity and anionogenic ferromagnetism via double exchange

NASA Astrophysics Data System (ADS)

Zhang, Baomin; Cao, Chonglong; Li, Guowei; Li, Feng; Ji, Weixiao; Zhang, Shufeng; Ren, Miaojuan; Zhang, Haikun; Zhang, Rui-Qin; Zhong, Zhicheng; Yuan, Zhe; Yuan, Shengjun; Blake, Graeme R.

2018-04-01

We use first-principles calculations to predict the occurrence of half-metallicity and anionogenic ferromagnetism at the heterointerface between two 2p insulators, taking the KO2/BaO2 (001) interface as an example. Whereas a sharp heterointerface is semiconducting, a heterointerface with a moderate concentration of swapped K and Ba atoms is half-metallic and ferromagnetic at ambient pressure due to the double exchange mechanism. The K-Ba swap renders the interfacial K-O and Ba-O atomic layers electron-doped and hole-doped, respectively. Our findings pave the way to realize metallicity and ferromagnetism at the interface between two 2 p insulators, and such systems can constitute a new family of heterostructures with novel properties, expanding studies on heterointerfaces from 3 d insulators to 2 p insulators.

Improvement of sound insulation performance of double-glazed windows by using viscoelastic connectors

NASA Astrophysics Data System (ADS)

Takahashi, D.; Sawaki, S.; Mu, R.-L.

2016-06-01

A new method for improving the sound insulation performance of double-glazed windows is proposed. This technique uses viscoelastic materials as connectors between the two glass panels to ensure that the appropriate spacing is maintained. An analytical model that makes it possible to discuss the effects of spacing, contact area, and viscoelastic properties of the connectors on the performance in terms of sound insulation is developed. The validity of the model is verified by comparing its results with measured data. The numerical experiments using this analytical model showed the importance of the ability of the connectors to achieve the appropriate spacing and their viscoelastic properties, both of which are necessary for improving the sound insulation performance. In addition, it was shown that the most effective factor is damping: the stronger the damping, the more the insulation performance increases.

Demonstration of large field effect in topological insulator films via a high-κ back gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, C. Y.; Lin, H. Y.; Yang, S. R.

2016-05-16

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi{sub 2}Se{sub 3} films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al{sub 2}O{sub 3} and Y{sub 2}O{sub 3}. Large gating effect of tuning the Fermi level E{sub F} to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO{sub 2} back gate, and the modulation of filmmore » resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN{sub 2D}/ΔV{sub g} varies with TI film thickness as ∼t{sup −0.75}. To enhance the gating effect, a Y{sub 2}O{sub 3} layer thickness 4 nm was inserted into Al{sub 2}O{sub 3} gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi{sub 2}Se{sub 3} to form Bi{sub 2}Te{sub x}Se{sub 1−x}. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the E{sub F} very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable E{sub F} for dissipationless spintronics based on well-established semiconductor technology.« less

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Top and Split Gating Control of the Electrical Characteristics of a Two-dimensional Electron Gas in a LaAlO3/SrTiO3 Perovskite

NASA Astrophysics Data System (ADS)

Kwak, Yongsu; Song, Jonghyun; Kim, Jihwan; Kim, Jinhee

2018-04-01

A top gate field effect transistor was fabricated using polymethyl methacrylate (PMMA) as a gate insulator on a LaAlO3 (LAO)/SrTiO3 (STO) hetero-interface. It showed n-type behavior, and a depletion mode was observed at low temperature. The electronic properties of the 2-dimensional electron gas at the LAO/STO hetero-interface were not changed by covering LAO with PMMA following the Au top gate electrode. A split gate device was also fabricated to construct depletion mode by using a narrow constriction between the LAO/STO conduction interface. The depletion mode, as well as superconducting critical current, could be controlled by applying a split gate voltage. Noticeably, the superconducting critical current tended to decrease with decreasing the split gate voltage and finally became zero. These results indicate that a weak-linked Josephson junction can be constructed and destroyed by split gating. This observation opens the possibility of gate-voltage-adjustable quantum devices.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Simultaneous control of thermoelectric properties in p- and n-type materials by electric double-layer gating: New design for thermoelectric device

NASA Astrophysics Data System (ADS)

Takayanagi, Ryohei; Fujii, Takenori; Asamitsu, Atsushi

2015-05-01

We report a novel design of a thermoelectric device that can control the thermoelectric properties of p- and n-type materials simultaneously by electric double-layer gating. Here, p-type Cu2O and n-type ZnO were used as the positive and negative electrodes of the electric double-layer capacitor structure. When a gate voltage was applied between the two electrodes, holes and electrons accumulated on the surfaces of Cu2O and ZnO, respectively. The thermopower was measured by applying a thermal gradient along the accumulated layer on the electrodes. We demonstrate here that the accumulated layers worked as a p-n pair of the thermoelectric device.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

Silicon Carbide Transistor For Detecting Hydrocarbon Gases

NASA Technical Reports Server (NTRS)

Shields, Virgil B.; Ryan, Margaret A.; Williams, Roger M.

1996-01-01

Proposed silicon carbide variable-potential insulated-gate field-effect transistor specially designed for use in measuring concentrations of hydrocarbon gases. Devices like this prove useful numerous automotive, industrial, aeronautical, and environmental monitoring applications.

A flexible amorphous Bi(5)Nb(3)O(15) film for the gate insulator of the low-voltage operating pentacene thin-film transistor fabricated at room temperature.

PubMed

Cho, Kyung-Hoon; Seong, Tae-Geun; Choi, Joo-Young; Kim, Jin-Seong; Kwon, Jae-Hong; Shin, Sang-Il; Chung, Myung-Ho; Ju, Byeong-Kwon; Nahm, Sahn

2009-10-20

The amorphous Bi(5)Nb(3)O(15) film grown at room temperature under an oxygen-plasma sputtering ambient (BNRT-O(2) film) has a hydrophobic surface with a surface energy of 35.6 mJ m(-2), which is close to that of the orthorhombic pentacene (38 mJ m(-2)), resulting in the formation of a good pentacene layer without the introduction of an additional polymer layer. This film was very flexible, maintaining a high capacitance of 145 nF cm(-2) during and after 10(5) bending cycles with a small curvature radius of 7.5 mm. This film was optically transparent. Furthermore, the flexible, pentacene-based, organic thin-film transistors (OTFTs) fabricated on the poly(ether sulfone) substrate at room temperature using a BNRT-O(2) film as a gate insulator exhibited a promising device performance with a high field effect mobility of 0.5 cm(2) V(-1) s(-1), an on/off current modulation of 10(5), and a small subthreshold slope of 0.2 V decade(-1) under a low operating voltage of -5 V. This device also maintained a high carrier mobility of 0.45 cm(2) V(-1 )s(-1) during the bending with a small curvature radius of 9 mm. Therefore, the BNRT-O(2) film is considered a promising material for the gate insulator of the flexible, pentacene-based OTFT.

Graphene-insulator-semiconductor capacitors as superior test structures for photoelectric determination of semiconductor devices band diagrams

NASA Astrophysics Data System (ADS)

Piskorski, K.; Passi, V.; Ruhkopf, J.; Lemme, M. C.; Przewlocki, H. M.

2018-05-01

We report on the advantages of using Graphene-Insulator-Semiconductor (GIS) instead of Metal-Insulator-Semiconductor (MIS) structures in reliable and precise photoelectric determination of the band alignment at the semiconductor-insulator interface and of the insulator band gap determination. Due to the high transparency to light of the graphene gate in GIS structures large photocurrents due to emission of both electrons and holes from the substrate and negligible photocurrents due to emission of carriers from the gate can be obtained, which allows reliable determination of barrier heights for both electrons, Ee and holes, Eh from the semiconductor substrate. Knowing the values of both Ee and Eh allows direct determination of the insulator band gap EG(I). Photoelectric measurements were made of a series of Graphene-SiO2-Si structures and an example is shown of the results obtained in sequential measurements of the same structure giving the following barrier height values: Ee = 4.34 ± 0.01 eV and Eh = 4.70 ± 0.03 eV. Based on this result and results obtained for other structures in the series we conservatively estimate the maximum uncertainty of both barrier heights estimations at ± 0.05 eV. This sets the SiO2 band gap estimation at EG(I) = 7.92 ± 0.1 eV. It is shown that widely different SiO2 band gap values were found by research groups using various determination methods. We hypothesize that these differences are due to different sensitivities of measurement methods used to the existence of the SiO2 valence band tail.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Technology of Double Thermal Insulation for the Repair and Energy Optimization of Existing Thermal Insulation Composite Systems

NASA Astrophysics Data System (ADS)

Belániová, Barbora; Antošová, Naďa

2017-06-01

The theme of improvement thermal proprieties of external cladding according to the New EU Directive is still a hot topic, which needs to be answered necessarily till December 2020. Maintenance and repair of existing ETICS became to also an actual open theme in search solutions for existing constructions. The aim of the research in this review is to analyze influence of layers the alternative thermal materials in technology "double thermal insulation". Humidity and temperature conditions will be further examined in connection with the development and colonization of microorganisms on surface construction.

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

NASA Astrophysics Data System (ADS)

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.; Lagally, Max G.; Foote, Ryan H.; Friesen, Mark; Coppersmith, Susan N.; Eriksson, Mark A.

2016-10-01

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of double quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. We further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau-Zener-Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

NASA Astrophysics Data System (ADS)

Shao, Jinhai; Deng, Jianan; Lu, W.; Chen, Yifang

2017-07-01

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

Comparative influence study of gate-formation structuring on Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors

NASA Astrophysics Data System (ADS)

Hsu, M. K.; Chiu, S. Y.; Wu, C. H.; Guo, D. F.; Lour, W. S.

2008-12-01

Pseudomorphic Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) fabricated with different gate-formation structures of a single-recess gate (SRG), a double-recess gate (DRG) and a field-plate gate (FPG) were comparatively investigated. FPG devices show the best breakdown characteristics among these devices due to great reduction in the peak electric field between the drain and gate electrodes. The measured gate-drain breakdown voltages defined at a 1 mA mm-1 reverse gate-drain current density were -15.3, -19.1 and -26.0 V for SRG, DRG and FPG devices, respectively. No significant differences in their room-temperature common-source current-voltage characteristics were observed. However, FPG devices exhibit threshold voltages being the least sensitive to temperature. Threshold voltages as a function of temperature indicate a threshold-voltage variation as low as -0.97 mV K-1 for FPG devices. According to the 2.4 GHz load-pull power measurement at VDS = 3.0 V and VGS = -0.5 V, the saturated output power (POUT), power gain (GP) and maximum power-added efficiency (PAE) were 10.3 dBm/13.2 dB/36.6%, 11.2 dBm/13.1 dB/39.7% and 13.06 dBm/12.8 dB/47.3%, respectively, for SRG, DRG and FPG devices with a pi-gate in class AB operation. When the FPG device is biased at a VDS of 10 V, the saturated power density is more than 600 mW mm-1.

Probing the intrinsic charge transport in indacenodithiophene-co-benzothiadiazole thin films

NASA Astrophysics Data System (ADS)

Wang, Wenhe; Tang, Wei; Zhao, Jiaqing; Bao, Bei; Xing, Hui; Guo, Xiaojun; Wang, Shun; Liu, Ying

2017-12-01

Indacenodithiophene-co-benzothiadiazole (IDTBT) belongs to a class of donor-acceptor polymers, exhibiting high electronic mobility and low energetic disorder. Applying vacuum as dielectric enables us to investigate the intrinsic charge transport properties in IDTBT. Vacuum-gap IDTBT field-effect transistors (FET) show high mobilites approaching 1 cm2V-1s-1. In addition, with increasing dielectric constant of the gate insulators, the mobilites of IDTBT transistors first increase and then decrease. The reason could be attributed to effect of both charge carrier accumulation and the presence of dipolar disorder at the semiconductor/insulator interface induced by polar insulator layer.

Homogeneous double-layer amorphous Si-doped indium oxide thin-film transistors for control of turn-on voltage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kizu, Takio, E-mail: KIZU.Takio@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Tsukagoshi, Kazuhito, E-mail: KIZU.Takio@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Aikawa, Shinya

We fabricated homogeneous double-layer amorphous Si-doped indium oxide (ISO) thin-film transistors (TFTs) with an insulating ISO cap layer on top of a semiconducting ISO bottom channel layer. The homogeneously stacked ISO TFT exhibited high mobility (19.6 cm{sup 2}/V s) and normally-off characteristics after annealing in air. It exhibited normally-off characteristics because the ISO insulator suppressed oxygen desorption, which suppressed the formation of oxygen vacancies (V{sub O}) in the semiconducting ISO. Furthermore, we investigated the recovery of the double-layer ISO TFT, after a large negative shift in turn-on voltage caused by hydrogen annealing, by treating it with annealing in ozone. The recoverymore » in turn-on voltage indicates that the dense V{sub O} in the semiconducting ISO can be partially filled through the insulator ISO. Controlling molecule penetration in the homogeneous double layer is useful for adjusting the properties of TFTs in advanced oxide electronics.« less

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Wan, Xiang; Shi, Yi; Wan, Qing

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

A pH sensor based on electric properties of nanotubes on a glass substrate

PubMed Central

Nakamura, Motonori; Ishii, Atsushi; Subagyo, Agus; Hosoi, Hirotaka; Sueoka, Kazuhisa; Mukasa, Koichi

2007-01-01

We fabricated a pH-sensitive device on a glass substrate based on properties of carbon nanotubes. Nanotubes were immobilized specifically on chemically modified areas on a substrate followed by deposition of metallic source and drain electrodes on the area. Some nanotubes connected the source and drain electrodes. A top gate electrode was fabricated on an insulating layer of silane coupling agent on the nanotube. The device showed properties of ann-type field effect transistor when a potential was applied to the nanotube from the top gate electrode. Before fabrication of the insulating layer, the device showed that thep-type field effect transistor and the current through the source and drain electrodes depend on the buffer pH. The current increases with decreasing pH of the CNT solution. This device, which can detect pH, is applicable for use as a biosensor through modification of the CNT surface. PMID:21806848

Oxide Semiconductor-Based Flexible Organic/Inorganic Hybrid Thin-Film Transistors Fabricated on Polydimethylsiloxane Elastomer.

PubMed

Jung, Soon-Won; Choi, Jeong-Seon; Park, Jung Ho; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lim, Sang Chul; Lee, Sang Seok; Chu, Hye Yong

2016-03-01

We demonstrate flexible organic/inorganic hybrid thin-film transistors (TFTs) on a polydimethysilox- ane (PDMS) elastomer substrate. The active channel and gate insulator of the hybrid TFT are composed of In-Ga-Zn-O (IGZO) and blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF- TrFE)] with poly(methyl methacrylate) (PMMA), respectively. It has been confirmed that the fabri- cated TFT display excellent characteristics: the recorded field-effect mobility, sub-threshold voltage swing, and I(on)/I(off) ratio were approximately 0.35 cm2 V(-1) s(-1), 1.5 V/decade, and 10(4), respectively. These characteristics did not experience any degradation at a bending radius of 15 mm. These results correspond to the first demonstration of a hybrid-type TFT using an organic gate insulator/oxide semiconducting active channel structure fabricated on PDMS elastomer, and demonstrate the feasibility of a promising device in a flexible electronic system.

Chemical Gating of a Weak Topological Insulator: Bi14Rh3I9.

PubMed

Ghimire, Madhav Prasad; Richter, Manuel

2017-10-11

The compound Bi 14 Rh 3 I 9 has recently been suggested as a weak three-dimensional topological insulator on the basis of angle-resolved photoemission and scanning-tunneling experiments in combination with density functional (DF) electronic structure calculations. These methods unanimously support the topological character of the headline compound, but a compelling confirmation could only be obtained by dedicated transport experiments. The latter, however, are biased by an intrinsic n-doping of the material's surface due to its polarity. Electronic reconstruction of the polar surface shifts the topological gap below the Fermi energy, which would also prevent any future device application. Here, we report the results of DF slab calculations for chemically gated and counter-doped surfaces of Bi 14 Rh 3 I 9 . We demonstrate that both methods can be used to compensate the surface polarity without closing the electronic gap.

Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET

NASA Astrophysics Data System (ADS)

Ueda, Daiki; Takeuchi, Kiyoshi; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

A new circuit model that provides a clear guide on designing a MOS-gated thyristor (MGT) is reported. MGT plays a significant role in achieving a steep subthreshold slope of a PN-body tied silicon-on-insulator (SOI) FET (PNBTFET), which is an SOI MOSFET merged with an MGT. The effects of design parameters on MGT and the proposed equivalent circuit model are examined to determine how to regulate the voltage response of MGT and how to suppress power dissipation. It is demonstrated that MGT with low threshold voltages, small hysteresis widths, and small power dissipation can be designed by tuning design parameters. The temperature dependence of MGT is also examined, and it is confirmed that hysteresis width decreases with the average threshold voltage kept nearly constant as temperature rises. The equivalent circuit model can be conveniently used to design low-power PNBTFET.

Understanding Metal-Insulator transitions in ultra-thin films of LaNiO3

NASA Astrophysics Data System (ADS)

Ravichandran, Jayakanth; King, Philip D. C.; Schlom, Darrell G.; Shen, Kyle M.; Kim, Philip

2014-03-01

LaNiO3 (LNO) is a bulk paramagnetic metal and a member of the family of RENiO3 Nickelates (RE = Rare Earth Metals), which is on the verge of the metal-insulator transition. Ultra-thin films of LNO has been studied extensively in the past and due to its sensitivity to disorder, the true nature of the metal-insulator transition in these films have been hard to decipher. We grow high quality ultra-thin films of LNO using reactive molecular beam epitaxy (MBE) and use a combination of ionic liquid gating and magneto-transport measurements to understand the nature and tunability of metal-insulator transition as a function of thickness for LNO. The underlying mechanisms for the transition are discussed in the framework of standard transport models. These results are discussed in the light of other Mott insulators such as Sr2IrO4, where we have performed similar measurements around the insulating state.

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

NASA Astrophysics Data System (ADS)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

Low-Temperature Carrier Transport in Ionic-Liquid-Gated Hydrogen-Terminated Silicon

NASA Astrophysics Data System (ADS)

Sasama, Yosuke; Yamaguchi, Takahide; Tanaka, Masashi; Takeya, Hiroyuki; Takano, Yoshihiko

2017-11-01

We fabricated ionic-liquid-gated field-effect transistors on the hydrogen-terminated (111)-oriented surface of undoped silicon. Ion implantation underneath electrodes leads to good ohmic contacts, which persist at low temperatures down to 1.4 K. The sheet resistance of the channel decreases by more than five orders of magnitude as the gate voltage is changed from 0 to -1.6 V at 220 K. This is caused by the accumulation of hole carriers. The sheet resistance shows thermally activated behavior at temperatures below 10 K, which is attributed to hopping transport of the carriers. The activation energy decreases towards zero with increasing carrier density, suggesting the approach to an insulator-metal transition. We also report the variation of device characteristics induced by repeated sweeps of the gate voltage.

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

Simple and double emulsions via electrospray

NASA Astrophysics Data System (ADS)

Barrero, Antonio; Loscertales, Ignacio G.

2005-11-01

Generation of nanoemulsions is of great interest in medical and pharmaceutical applications; drug delivery or antiviral emulsions are typical examples. The use of electrosprays for dispersing liquids inside liquid insulator baths have been recently reported, (Barrero et al. J. Colloid Interf. Sci. 272, 104, 2004). Capsules, nanotubes and coaxial nanofibers have been obtained from electrified coaxial jets (Loscertales et al. Science 295, n. 5560, 1695, 2002; J. American Chem. Soc. 126, 5376, 2004). Here we present a method for making double emulsions (both water-oil-water and o/w/o) based on the generation of compound electrosprays inside insulator liquid baths. Basically, a conducting liquid injected throughout a capillary needle is electroatomized in cone-jet mode inside a dielectric liquid bath. A third insulating liquid is injected inside the Taylor cone to form a second meniscus. Then, a steady coaxial jet, in which the insulating liquid is coated by the conducting one, develops. A double emulsion forms as a result of the jet breaking up into compound droplets electrically charged. Experimental results carried out with glycerine and different oils in a bath of heptane are reported.

Tuning carrier density across Dirac point in epitaxial graphene on SiC by corona discharge

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lartsev, Arseniy; Yager, Tom; Lara-Avila, Samuel, E-mail: samuel.lara@chalmers.se

We demonstrate reversible carrier density control across the Dirac point (Δn ∼ 10{sup 13 }cm{sup −2}) in epitaxial graphene on SiC (SiC/G) via high electrostatic potential gating with ions produced by corona discharge. The method is attractive for applications where graphene with a fixed carrier density is needed, such as quantum metrology, and more generally as a simple method of gating 2DEGs formed at semiconductor interfaces and in topological insulators.

Dopant-controlled single-electron pumping through a metallic island

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wenz, Tobias, E-mail: tobias.wenz@ptb.de; Hohls, Frank, E-mail: frank.hohls@ptb.de; Jehl, Xavier

We investigate a hybrid metallic island/single dopant electron pump based on fully depleted silicon-on-insulator technology. Electron transfer between the central metallic island and the leads is controlled by resonant tunneling through single phosphorus dopants in the barriers. Top gates above the barriers are used to control the resonance conditions. Applying radio frequency signals to the gates, non-adiabatic quantized electron pumping is achieved. A simple deterministic model is presented and confirmed by comparing measurements with simulations.

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

The Insulation of Houses against Noise from Aircraft in Flight.

ERIC Educational Resources Information Center

Scholes, W. E.; Parkin, P. H.

Three groups of traditional houses were insulated against aircraft noise by double glazing and installing sound attenuating ventilator units. For upper floor rooms of two story houses, overall insulations of 35-40 dB were obtainable, providing transmission through the roofs and down flues were also reduced. The noise levels caused by ventilator…

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Comparison of reusable insulation systems for cryogenically-tanked earth-based space vehicles

NASA Technical Reports Server (NTRS)

Sumner, I. E.; Barber, J. R.

1978-01-01

Three reusable insulation systems concepts have been developed for use with cryogenic tanks of earth-based space vehicles. Two concepts utilized double-goldized Kapton (DGK) or double-aluminized Mylar (DAM) multilayer insulation (MLI), while the third utilized a hollow-glass-microsphere, load-bearing insulation (LBI). All three insulation systems have recently undergone experimental testing and evaluation under NASA-sponsored programs. Thermal performance measurements were made under space-hold (vacuum) conditions for insulation warm boundary temperatures of approximately 291 K. The resulting effective thermal conductivity was approximately .00008 W/m-K for the MLI systems (liquid hydrogen test results) and .00054 W/m-K for the LBI system (liquid nitrogen test results corrected to liquid hydrogen temperature). The DGK MLI system experienced a maximum thermal degradation of 38 percent, the DAM MLI system 14 percent, and the LBI system 6.7 percent due to repeated thermal cycling representing typical space flight conditions. Repeated exposure of the DAM MLI system to a high humidity environment for periods as long as 8 weeks provided a maximum degradation of only 24 percent.

Control of magnetism in Co by an electric field

NASA Astrophysics Data System (ADS)

Chiba, D.; Ono, T.

2013-05-01

In this paper, we review the recent experimental developments on electric-field switching of ferromagnetism in ultra-thin Co films. The application of an electric field changes the electron density at the surface of the Co film, which results in modulation of its Curie temperature. A capacitor structure consisting of a gate electrode, a solid-state dielectric insulator and a Co bottom electrode is used to observe the effect. To obtain a larger change in the electron density, we also fabricated an electric double-layer capacitor structure using an ionic liquid. A large change in the Curie temperature of ∼100 K across room temperature is achieved with this structure. The application of the electric field influences not only the Curie temperature but also the domain-wall motion. A change in the velocity of a domain wall prepared in a Co micro-wire of more than one order of magnitude is observed. Possible mechanisms to explain the above-mentioned electric-field effects in Co ultra-thin films are discussed.

Optimal control of universal quantum gates in a double quantum dot

NASA Astrophysics Data System (ADS)

Castelano, Leonardo K.; de Lima, Emanuel F.; Madureira, Justino R.; Degani, Marcos H.; Maialle, Marcelo Z.

2018-06-01

We theoretically investigate electron spin operations driven by applied electric fields in a semiconductor double quantum dot (DQD) formed in a nanowire with longitudinal potential modulated by local gating. We develop a model that describes the process of loading and unloading the DQD taking into account the overlap between the electron wave function and the leads. Such a model considers the spatial occupation and the spin Pauli blockade in a time-dependent fashion due to the highly mixed states driven by the external electric field. Moreover, we present a road map based on the quantum optimal control theory (QOCT) to find a specific electric field that performs two-qubit quantum gates on a faster timescale and with higher possible fidelity. By employing the QOCT, we demonstrate the possibility of performing within high efficiency a universal set of quantum gates {cnot, H, and T } , where cnot is the controlled-not gate, H is the Hadamard gate, and T is the π /8 gate, even in the presence of the loading/unloading process and charge noise effects. Furthermore, by varying the intensity of the applied magnetic field B , the optimized fidelity of the gates oscillates with a period inversely proportional to the gate operation time tf. This behavior can be useful to attain higher fidelity for fast gate operations (>1 GHz) by appropriately choosing B and tf to produce a maximum of the oscillation.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Local Gate Control of a Carbon Nanotube Double Quantum Dot

DTIC Science & Technology

2016-04-04

Nanotube Double Quantum Dot N. Mason,*† M. J. Biercuk,* C. M. Marcus† We have measured carbon nanotube quantum dots with multiple electro- static gates and...computation. Carbon nanotubes have been considered lead- ing candidates for nanoscale electronic applica- tions (1, 2). Previous measurements of nano- tube...electronics have shown electron confine- ment (quantum dot) effects such as single- electron charging and energy-level quantization (3–5). Nanotube

Composite flexible blanket insulation

NASA Technical Reports Server (NTRS)

Kourtides, Demetrius A. (Inventor); Lowe, David M. (Inventor)

1994-01-01

An improved composite flexible blanket insulation is presented comprising top silicon carbide having an interlock design, wherein the reflective shield is composed of single or double aluminized polyimide and wherein the polyimide film has a honeycomb pattern.

Characterizing the structure of topological insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Richardella, Anthony; Kandala, Abhinav; Lee, Joon Sue

2015-08-01

We describe the characterization of structural defects that occur during molecular beam epitaxy of topological insulator thin films on commonly used substrates. Twinned domains are ubiquitous but can be reduced by growth on smooth InP (111)A substrates, depending on details of the oxide desorption. Even with a low density of twins, the lattice mismatch between (Bi, Sb){sub 2}Te{sub 3} and InP can cause tilts in the film with respect to the substrate. We also briefly discuss transport in simultaneously top and back electrically gated devices using SrTiO{sub 3} and the use of capping layers to protect topological insulator films frommore » oxidation and exposure.« less

Specular Andreev reflection in thin films of topological insulators

NASA Astrophysics Data System (ADS)

Majidi, Leyla; Asgari, Reza

2016-05-01

We theoretically reveal the possibility of specular Andreev reflection in a thin film topological insulator normal-superconductor (N/S) junction in the presence of a gate electric field. The probability of specular Andreev reflection increases with the electric field, and electron-hole conversion with unit efficiency happens in a wide experimentally accessible range of the electric field. We show that perfect specular Andreev reflection can occur for all angles of incidence with a particular excitation energy value. In addition, we find that the thermal conductance of the structure displays exponential dependence on the temperature. Our results reveal the potential of the proposed topological insulator thin-film-based N/S structure for the realization of intraband specular Andreev reflection.

Lightweight Thermal Insulation for a Liquid-Oxygen Tank

NASA Technical Reports Server (NTRS)

Willen, G. Scott; Lock, Jennifer; Nieczkoski, Steve

2005-01-01

A proposed lightweight, reusable thermal-insulation blanket has been designed for application to a tank containing liquid oxygen, in place of a non-reusable spray-on insulating foam. The blanket would be of the multilayer-insulation (MLI) type and equipped with a pressure-regulated nitrogen purge system. The blanket would contain 16 layers in two 8-layer sub-blankets. Double-aluminized polyimide 0.3 mil (.0.008 mm) thick was selected as a reflective shield material because of its compatibility with oxygen and its ability to withstand ionizing radiation and high temperature. The inner and outer sub-blanket layers, 1 mil (approximately equals 0.025 mm) and 3 mils (approximately equals 0.076 mm) thick, respectively, would be made of the double-aluminized polyimide reinforced with aramid. The inner and outer layers would provide structural support for the more fragile layers between them and would bear the insulation-to-tank attachment loads. The layers would be spaced apart by lightweight, low-thermal-conductance netting made from polyethylene terephthalate.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Materials considerations for forming the topological insulator phase in InAs/GaSb heterostructures

NASA Astrophysics Data System (ADS)

Shojaei, B.; McFadden, A. P.; Pendharkar, M.; Lee, J. S.; Flatté, M. E.; Palmstrøm, C. J.

2018-06-01

In an ideal InAs/GaSb bilayer of appropriate dimension, in-plane electron and hole bands overlap and hybridize, and a topologically nontrivial, or quantum spin Hall (QSH) insulator, phase is predicted to exist. The in-plane dispersion's potential landscape, however, is subject to microscopic perturbations originating from material imperfections. In this work, the effect of disorder on the electronic structure of InAs/GaSb (001) bilayers was studied by observing the temperature and magnetic-field dependence of the resistance of a dual-gated heterostructure gate-tuned through the inverted to normal gap regimes. Conduction with the electronic structure tuned to the inverted (predicted topological) regime and the Fermi level in the hybridization gap was qualitatively similar to behavior in a disordered two-dimensional system. The impact of charged impurities and interface roughness on the formation of topologically protected edge states and an insulating bulk was estimated. The experimental evidence and estimates of disorder in the potential landscape indicated that the potential fluctuations in state-of-the-art films are sufficiently strong such that conduction with the electronic structure tuned to the predicted topological insulator (TI) regime and the Fermi level in the hybridization gap was dominated by a symplectic metal phase rather than a TI phase. The implications are that future efforts must address disorder in this system, and focus must be placed on the reduction of defects and disorder in these heterostructures if a TI regime is to be achieved.

A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2017-08-01

This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson's equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for amore » strong depletion of the 2-DEG.« less

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Undoped Si/SiGe Depletion-Mode Few-Electron Double Quantum Dots

NASA Astrophysics Data System (ADS)

Borselli, Matthew; Huang, Biqin; Ross, Richard; Croke, Edward; Holabird, Kevin; Hazard, Thomas; Watson, Christopher; Kiselev, Andrey; Deelman, Peter; Alvarado-Rodriguez, Ivan; Schmitz, Adele; Sokolich, Marko; Gyure, Mark; Hunter, Andrew

2011-03-01

We have successfully formed a double quantum dot in the sSi/SiGe material system without need for intentional dopants. In our design, a two-dimensional electron gas is formed in a strained silicon well by forward biasing a global gate. Lateral definition of quantum dots is established with reverse-biased gates with ~ 40 nm critical dimensions. Low-temperature capacitance and Hall measurements confirm electrons are confined in the Si-well with mobilities > 10 4 cm 2 / V - s . Further characterization identifies practical gate bias limits for this design and will be compared to simulation. Several double dot devices have been brought into the few-electron Coulomb blockade regime as measured by through-dot transport. Honeycomb diagrams and nonlinear through-dot transport measurements are used to quantify dot capacitances and addition energies of several meV. Sponsored by United States Department of Defense. Approved for Public Release, Distribution Unlimited.

Metal-insulator and charge ordering transitions in oxide nanostructures

NASA Astrophysics Data System (ADS)

Singh, Sujay Kumar

Strongly correlated oxides are a class of materials wherein interplay of various degrees of freedom results in novel electronic and magnetic phenomena. Vanadium oxides are widely studied correlated materials that exhibit metal-insulator transitions (MIT) in a wide temperature range from 70 K to 380 K. In this Thesis, results from electrical transport measurements on vanadium dioxide (VO2) and vanadium oxide bronze (MxV 2O5) (where M: alkali, alkaline earth, and transition metal cations) are presented and discussed. Although the MIT in VO2 has been studied for more than 50 years, the microscopic origin of the transition is still debated since a slew of external parameters such as light, voltage, and strain are found to significantly alter the transition. Furthermore, recent works on electrically driven switching in VO2 have shown that the role of Joule heating to be a major cause as opposed to electric field. We explore the mechanisms behind the electrically driven switching in single crystalline nanobeams of VO2 through DC and AC transport measurements. The harmonic analysis of the AC measurement data shows that non-uniform Joule heating causes electronic inhomogeneities to develop within the nanobeam and is responsible for driving the transition in VO2. Surprisingly, field assisted emission mechanisms such as Poole-Frenkel effect is found to be absent and the role of percolation is also identified in the electrically driven transition. This Thesis also provides a new insight into the mechanisms behind the electrolyte gating induced resistance modulation and the suppression of MIT in VO2. We show that the metallic phase of VO2 induced by electrolyte gating is due to an electrochemical process and can be both reversible and irreversible under different conditions. The kinetics of the redox processes increase with temperature; a complete suppression of the transition and the stabilization of the metallic phase are achievable by gating in the rutile metallic phase. First principles calculations show that the destabilization of the insulating phase during the gating arises due to the formation of oxygen vacancies in VO2; the rutile phase is far more amenable to electrochemical reduction as compared to the monoclinic phase, likely due to its higher electrical conductivity. The generation of oxygen vacancies appears thermodynamically favorable if the removed oxygen atoms from VO2 oxidize the anions in the ionic liquid. Finally, electronic properties of single crystalline, individual nanowires of vanadium oxide bronzes (MxVO 2O5) are presented. The intercalation effects of metal cation and the stoichiometry (x) are explored and discussed. These nanowires exhibit thermally and electrically driven charge ordering and metal to insulator transitions. The electrolyte gating measurements show resistance modulations across the phase transition but the effect is not as dramatic as in VO2.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Maintenance Resources by Building Use for Installations in Germany

DTIC Science & Technology

1991-11-01

125125. .01 0531140 STEEL ( INSULATED ) PAINTED INTERIOR DOOR 124956. .01 0432710 DOUBLE PANE STEEL FIXED WNDW. 1ST FLOOR 124922. .01 1131200 QUARTZ...FINISH 8507. .00 0535400 ALUMINUM DOUBLE ROLL-UP INTERIOR DOOR 8490. .00 0424310 ALUMINUM LOUVERED EXT DOORS 7973. .00 0421340 STEEL ( INSUL CORE) UNPUT...H.P. 0831130 20 1.09 Clay Block (Painted) Interior 0612200 21 1.08 Wall Sink. Stainless Steel 0811F00 22 1.03 Steel (Painted) Exterior Door 0421210 23

Functional Dependence for Calculation of Additional Real-Power Losses in a Double-Wound Supply Transformer Caused by Unbalanced Active Inductive Load in a Star Connection with an Insulated Neutral

ERIC Educational Resources Information Center

Kostinskiy, Sergey S.; Troitskiy, Anatoly I.

2016-01-01

This article deals with the problem of calculating the additional real-power losses in double-wound supply transformers with voltage class 6 (10)/0,4 kV, caused by unbalanced active inductive load connected in a star connection with an insulated neutral. When solving the problem, authors used the theory of electric circuits, method of balanced…

Toward Efficient Design of Reversible Logic Gates in Quantum-Dot Cellular Automata with Power Dissipation Analysis

NASA Astrophysics Data System (ADS)

Sasamal, Trailokya Nath; Singh, Ashutosh Kumar; Ghanekar, Umesh

2018-04-01

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for designing area and power efficient reversible logic gates. The proposed designs achieve superior performance by incorporating a compact 2-input XOR gate. The proposed design for Feynman, Toffoli, and Fredkin gates demonstrates 28.12, 24.4, and 7% reduction in cell count and utilizes 46, 24.4, and 7.6% less area, respectively over previous best designs. Regarding the cell count (area cover) that of the proposed Peres gate and Double Feynman gate are 44.32% (21.5%) and 12% (25%), respectively less than the most compact previous designs. Further, the delay of Fredkin and Toffoli gates is 0.75 clock cycles, which is equal to the delay of the previous best designs. While the Feynman and Double Feynman gates achieve a delay of 0.5 clock cycles, equal to the least delay previous one. Energy analysis confirms that the average energy dissipation of the developed Feynman, Toffoli, and Fredkin gates is 30.80, 18.08, and 4.3% (for 1.0 E k energy level), respectively less compared to best reported designs. This emphasizes the beneficial role of using proposed reversible gates to design complex and power efficient QCA circuits. The QCADesigner tool is used to validate the layout of the proposed designs, and the QCAPro tool is used to evaluate the energy dissipation.

Fluid insulation to prevent ice formation in heat exchangers

NASA Technical Reports Server (NTRS)

Coffinberry, G. A.

1973-01-01

Heat transfer surfaces were insulated to maintain air side surface temperature above freezing. Double wall tubes, with annular space between tubes, were filled with static liquid hydrogen. Low thermal conductivity of this hydrogen provided thermal resistance.

Thermal performance of gaseous-helium-purged tank-mounted multilayer insulation system during ground-hold and space-hold thermal cycling and exposure to water vapor

NASA Technical Reports Server (NTRS)

Sumner, I. E.

1978-01-01

An experimental investigation was conducted to determine (1) the ground-hold and space-hold thermal performance of a multilayer insulation (MLI) system mounted on a spherical, liquid-hydrogen propellant tank and (2) the degradation to the space-hold thermal performance of the insulation system that resulted from both thermal cycling and exposure to moisture. The propellant tank had a diameter of 1.39 meters (4.57ft). The MLI consisted of two blankets of insulation; each blanket contained 15 double-aluminized Mylar radiation shields separated by double silk net spacers. Nineteen tests simulating basic cryogenic spacecraft thermal (environmental) conditions were conducted. These tests typically included initial helium purge, liquid-hydrogen fill and ground-hold, ascent, space-hold, and repressurization. No significant degradation of the space-hold thermal performance due to thermal cycling was noted.

Structural Modification of Organic Thin-Film Transistors for Photosensor Application

NASA Astrophysics Data System (ADS)

Jeong, Hyeon Seok; Bae, Jin-Hyuk; Lee, Hyeonju; Ndikumana, Joel; Park, Jaehoon

2018-05-01

We investigated the light response characteristics of bottom-gate/top-contact organic TFTs fabricated using pentacene and polystyrene as an organic semiconductor and a polymeric insulator, respectively. The pentacene TFT with overlaps (50 μm) between the source and gate electrodes as well as between the drain and gate electrodes exhibited negligible hysteresis in its transfer characteristics upon reversal of the gate voltage sweep direction. When the TFTs were structurally modified to produce an underlap structure between the source and gate electrodes, clockwise hysteresis and a drain-current decrease were observed, which were further augmented by increasing the gate underlap (from 30 μm to 50 μm and 70 μm). Herein, these results are explained in terms of space charge formation and accumulation capacitance reduction. Importantly, we found that space charges formed under the source electrode contributed to the drain currents via light irradiation through the underlap region. Under constant bias conditions, the TFTs with gate underlap structures thus exhibited on-state drain current changes in response to light signals. In our study, an optimal photosensitivity exceeding 11 was achieved by the TFT with a 30 μm gate underlap. Consequently, we suggest that gate underlap structure modification is a viable means of implementing light responsiveness in organic TFTs.

Electrochemically Induced Insulator-Metal-Insulator Transformations of Vanadium Dioxide Nanocrystal Films

NASA Astrophysics Data System (ADS)

Milliron, Delia; Dahlman, Clayton; Leblanc, Gabriel; Bergerud, Amy

Vanadium dioxide (VO2) undergoes significant optical, electronic, and structural changes as it transforms between the low-temperature monoclinic and high-temperature rutile phases. The low-temperature state is insulating and transparent, while the high-temperature state is metallic and IR blocking. Alternative stimuli have been utilized to trigger insulator-to-metal transformations in VO2, including electrochemical gating. Here, VO2 nanocrystal films have been prepared by solution deposition of V2O3 nanocrystals followed by oxidative annealing. Nanocrystalline VO2 films are electrochemically reduced, inducing changes in their electronic and optical properties. We observe a reversible transition between infrared transparent insulating phases and a darkened metallic phase by in situ visible-near-infrared spectroelectrochemistry and correlate these observations with structural and electronic changes monitored by X-ray absorption spectroscopy, X-ray diffraction, Raman spectroscopy, and conductivity measurements. Reduction causes an initial transformation to a metallic, IR-colored distorted monoclinic phase. However, an unexpected reversible transition from conductive, reduced monoclinic VO2 to an infrared-transparent insulating phase is observed upon further reduction.

Phase coherent transport in hybrid superconductor-topological insulator devices

NASA Astrophysics Data System (ADS)

Finck, Aaron

2015-03-01

Heterostructures of superconductors and topological insulators are predicted to host unusual zero energy bound states known as Majorana fermions, which can robustly store and process quantum information. Here, I will discuss our studies of such heterostructures through phase-coherent transport, which can act as a unique probe of Majorana fermions. We have extensively explored topological insulator Josephson junctions through SQUID and single-junction diffraction patterns, whose unusual behavior give evidence for low-energy Andreev bound states. In topological insulator devices with closely spaced normal and superconducting leads, we observe prominent Fabry-Perot oscillations, signifying gate-tunable, quasi-ballistic transport that can elegantly interact with Andreev reflection. Superconducting disks deposited on the surface of a topological insulator generate Aharonov-Bohm-like oscillations, giving evidence for unusual states lying near the interface between the superconductor and topological insulator surface. Our results point the way towards sophisticated interferometers that can detect and read out the state of Majorana fermions in topological systems. This work was done in collaboration with Cihan Kurter, Yew San Hor, and Dale Van Harlingen. We acknowledge funding from Microsoft Project Q.

Development of a Si/ SiO 2-based double quantum dot charge qubit with dispersive microwave readout

NASA Astrophysics Data System (ADS)

House, M. G.; Henry, E.; Schmidt, A.; Naaman, O.; Siddiqi, I.; Pan, H.; Xiao, M.; Jiang, H. W.

2011-03-01

Coupling of a high-Q microwave resonator to superconducting qubits has been successfully used to prepare, manipulate, and read out the state of a single qubit, and to mediate interactions between qubits. Our work is geared toward implementing this architecture in a semiconductor qubit. We present the design and development of a lateral quantum dot in which a superconducting microwave resonator is capacitively coupled to a double dot charge qubit. The device is a silicon MOSFET structure with a global gate which is used to accumulate electrons at a Si/ Si O2 interface. A set of smaller gates are used to deplete these electrons to define a double quantum dot and adjacent conduction channels. Two of these depletion gates connect directly to the conductors of a 6 GHz co-planar stripline resonator. We present measurements of transport and conventional charge sensing used to characterize the double quantum dot, and demonstrate that it is possible to reach the few-electron regime in this system. This work is supported by the DARPA-QuEST program.

Wavelength-dependence of double optical gating for attosecond pulse generation

NASA Astrophysics Data System (ADS)

Tian, Jia; Li, Min; Yu, Ji-Zhou; Deng, Yong-Kai; Liu, Yun-Quan

2014-10-01

Both polarization gating (PG) and double optical gating (DOG) are productive methods to generate single attosecond (as) pulses. In this paper, considering the ground-state depletion effect, we investigate the wavelength-dependence of the DOG method in order to optimize the generation of single attosecond pulses for the future application. By calculating the ionization probabilities of the leading edge of the pulse at different driving laser wavelengths, we obtain the upper limit of duration for the driving laser pulse for the DOG setup. We find that the upper limit duration increases with the increase of laser wavelength. We further describe the technical method of choosing and calculating the thickness values of optical components for the DOG setup.

Design architecture of double spiral interdigitated electrode with back gate electrode for biosensor application

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

2016-07-01

This paper presents the preparation method of photolithography chrome mask design used in fabrication process of double spiral interdigitated electrode with back gate biasing based biosensor. By learning the fabrication process flow of the biosensor, the chrome masks are designed through drawing using the AutoCAD software. The overall width and length of the device is optimized at 7.0 mm and 10.0 mm, respectively. Fabrication processes of the biosensor required three chrome masks, which included back gate opening, spiral IDE formation, and passivation area formation. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

A reconfigurable gate architecture for Si/SiGe quantum dots

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zajac, D. M.; Hazard, T. M.; Mi, X.

2015-06-01

We demonstrate a reconfigurable quantum dot gate architecture that incorporates two interchangeable transport channels. One channel is used to form quantum dots, and the other is used for charge sensing. The quantum dot transport channel can support either a single or a double quantum dot. We demonstrate few-electron occupation in a single quantum dot and extract charging energies as large as 6.6 meV. Magnetospectroscopy is used to measure valley splittings in the range of 35–70 μeV. By energizing two additional gates, we form a few-electron double quantum dot and demonstrate tunable tunnel coupling at the (1,0) to (0,1) interdot charge transition.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

NASA Astrophysics Data System (ADS)

Lenka, Annada Shankar; Mishra, Sikha; Mishra, Satyaranjan; Bhanja, Urmila; Mishra, Guru Prasad

2017-11-01

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

Improvement in negative bias illumination stress stability of In-Ga-Zn-O thin film transistors using HfO2 gate insulators by controlling atomic-layer-deposition conditions

NASA Astrophysics Data System (ADS)

Na, So-Yeong; Kim, Yeo-Myeong; Yoon, Da-Jeong; Yoon, Sung-Min

2017-12-01

The effects of atomic layer deposition (ALD) conditions for the HfO2 gate insulators (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature and Hf precursor purge time were varied to 200, 225, and 250 °C, and 15 and 30 s, respectively. The HfO2 thin films showed low leakage current density of 10-8 A cm-2, high dielectric constant of over 20, and smooth surface roughness at all ALD conditions. The IGZO TFTs using the HfO2 GIs showed good device characteristics such as a saturation mobility as high as 11 cm2 V-1 s-1, a subthreshold swing as low as 0.10 V/dec, and all the devices could be operated at a gate voltage as low as  ±3 V. While there were no marked differences in transfer characteristics and PBS stabilities among the fabricated devices, the NBIS instabilities could be improved by increasing the ALD temperature for the formation of HfO2 GIs by reducing the oxygen vacancies within the IGZO channel.

Microscopic signature of insulator-to-metal transition in highly doped semicrystalline conducting polymers in ionic-liquid-gated transistors

NASA Astrophysics Data System (ADS)

Tanaka, Hisaaki; Nishio, Satoshi; Ito, Hiroshi; Kuroda, Shin-ichi

2015-12-01

Electronic state of charge carriers, in particular, in highly doped regions, in thin-film transistors of a semicrystalline conducting polymer poly(2,5-bis(3-alkylthiophene-2-yl)thieno[3,2-b]thiophene), has been studied by using field-induced electron spin resonance (ESR) spectroscopy. By adopting an ionic-liquid gate insulator, a gate-controlled reversible electrochemical hole-doping of the polymer backbone is achieved, as confirmed from the change of the optical absorption spectra. The edge-on molecular orientation in the pristine film is maintained even after the electrochemical doping, which is clarified from the angular dependence of the g value. As the doping level increases, spin 1/2 polarons transform into spinless bipolarons, which is demonstrated from the spin-charge relation showing a spin concentration peak around 1%, contrasting to the monotonic increase in the charge concentration. At high doping levels, a drastic change in the linewidth anisotropy due to the generation of conduction electrons is observed, indicating the onset of metallic state, which is also supported by the temperature dependence of the spin susceptibility and the ESR linewidth. Our results suggest that semicrystalline conducting polymers become metallic with retaining their molecular orientational order, when appropriate doping methods are chosen.

A 65-kV insulated gate bipolar transistor switch applied in damped AC voltages partial discharge detection system.

PubMed

Jiang, J; Ma, G M; Luo, D P; Li, C R; Li, Q M; Wang, W

2014-02-01

Damped AC voltages detection system (DAC) is a productive way to detect the faults in power cables. To solve the problems of large volume, complicated structure and electromagnetic interference in existing switches, this paper developed a compact solid state switch based on electromagnetic trigger, which is suitable for DAC test system. Synchronous electromagnetic trigger of 32 Insulated Gate Bipolar Transistors (IGBTs) in series was realized by the topological structure of single line based on pulse width modulation control technology. In this way, external extension was easily achieved. Electromagnetic trigger and resistor-capacitor-diode snubber circuit were optimized to reduce the switch turn-on time and circular layout. Epoxy encapsulating was chosen to enhance the level of partial discharge initial voltage (PDIV). The combination of synchronous trigger and power supply is proposed to reduce the switch volume. Moreover, we have overcome the drawback of the electromagnetic interference and improved the detection sensitivity of DAC by using capacitor storage energy to maintain IGBT gate driving voltage. The experimental results demonstrated that the solid-state switch, with compact size, whose turn-on time was less than 400 ns and PDIV was more than 65 kV, was able to meet the actual demands of 35 kV DAC test system.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

PubMed Central

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-01-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand. PMID:28649986

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

NASA Astrophysics Data System (ADS)

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-06-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

The improvement of a simple theoretical model for the prediction of the sound insulation of double leaf walls.

PubMed

Davy, John L

2010-02-01

This paper presents a revised theory for predicting the sound insulation of double leaf cavity walls that removes an approximation, which is usually made when deriving the sound insulation of a double leaf cavity wall above the critical frequencies of the wall leaves due to the airborne transmission across the wall cavity. This revised theory is also used as a correction below the critical frequencies of the wall leaves instead of a correction due to Sewell [(1970). J. Sound Vib. 12, 21-32]. It is found necessary to include the "stud" borne transmission of the window frames when modeling wide air gap double glazed windows. A minimum value of stud transmission is introduced for use with resilient connections such as steel studs. Empirical equations are derived for predicting the effective sound absorption coefficient of wall cavities without sound absorbing material. The theory is compared with experimental results for double glazed windows and gypsum plasterboard cavity walls with and without sound absorbing material in their cavities. The overall mean, standard deviation, maximum, and minimum of the differences between experiment and theory are -0.6 dB, 3.1 dB, 10.9 dB at 1250 Hz, and -14.9 dB at 160 Hz, respectively.

Spintronic signatures of Klein tunneling in topological insulators

NASA Astrophysics Data System (ADS)

Xie, Yunkun; Tan, Yaohua; Ghosh, Avik W.

2017-11-01

Klein tunneling, the perfect transmission of normally incident Dirac electrons across a potential barrier, has been widely studied in graphene and explored to design switches, albeit indirectly. We show an alternative way to directly measure Klein tunneling for spin-momentum locked electrons crossing a PN junction along a three-dimensional topological insulator surface. In these topological insulator PN junctions (TIPNJs), the spin texture and momentum distribution of transmitted electrons can be measured electrically using a ferromagnetic probe for varying gate voltages and angles of current injection. Based on transport models across a TIPNJ, we show that the asymmetry in the potentiometric signal between PP and PN junctions and its overall angular dependence serve as a direct signature of Klein tunneling.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

NASA Astrophysics Data System (ADS)

Bidzinski, Piotr; Miczek, Marcin; Adamowicz, Boguslawa; Mizue, Chihoko; Hashizume, Tamotsu

2011-04-01

The influence of interface state density and bulk carrier lifetime on the dependencies of photocapacitance versus wide range of gate bias (-0.1 to -3 V) and light intensity (109 to 1020 photon cm-2 s-1) was studied for metal/insulator/n-GaN UV light photodetector by means of numerical simulations. The light detection limit and photocapacitance saturation were analyzed in terms of the interface charge and interface Fermi level for electrons and holes and effective interface recombination velocity. It was proven that the excess carrier recombination through interface states is the main reason of photocapacitance signal quenching. It was found that the photodetector can work in various modes (on-off or quantitative light measurement) adjusted by the gate bias. A comparison between experimental data and theoretical capacitance-light intensity characteristics was made. A new method for the determination of the interface state density distribution from capacitance-voltage-light intensity measurements was also proposed.

Improving yield and performance in ZnO thin-film transistors made using selective area deposition.

PubMed

Nelson, Shelby F; Ellinger, Carolyn R; Levy, David H

2015-02-04

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.

Surface plasmon polaritons in a topological insulator embedded in an optical cavity

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, L. L., E-mail: lllihfcas@foxmail.com; Xu, W., E-mail: wenxu-issp@aliyun.com; Department of Physics, Yunnan University, Kunming 650091

Very recently, the surface plasmons in a topological insulator (TI) have been experimentally observed by exciting these collective modes with polarized light [P. Di Pietro, M. Ortolani, O. Limaj, A. Di Gaspare, V. Giliberti, F. Giorgianni, M. Brahlek, N. Bansal, N. Koirala, S. Oh, P. Calvani, and S. Lupi, Nat. Nanotechnol. 8, 556 (2013)]. Motivated by this experimental work, here we present a theoretical study on the surface plasmon polaritons (SPPs) induced by plasmon-photon interactions in a TI thin film embedded in an optical cavity. It is found that the frequencies of SPP modes are within the terahertz (THz) bandwidthmore » and can be tuned effectively by adjusting the surface electron density and/or the optical cavity length. Since the surface electron density can be well controlled by the gate-voltage applied perpendicular to the TI surface, our theoretical results indicate that gated TI thin films may have potential applications in the electrically tunable THz plasmonic devices.« less

Surface plasmon polaritons in a topological insulator embedded in an optical cavity

NASA Astrophysics Data System (ADS)

Li, L. L.; Xu, W.

2014-03-01

Very recently, the surface plasmons in a topological insulator (TI) have been experimentally observed by exciting these collective modes with polarized light [P. Di Pietro, M. Ortolani, O. Limaj, A. Di Gaspare, V. Giliberti, F. Giorgianni, M. Brahlek, N. Bansal, N. Koirala, S. Oh, P. Calvani, and S. Lupi, Nat. Nanotechnol. 8, 556 (2013)]. Motivated by this experimental work, here we present a theoretical study on the surface plasmon polaritons (SPPs) induced by plasmon-photon interactions in a TI thin film embedded in an optical cavity. It is found that the frequencies of SPP modes are within the terahertz (THz) bandwidth and can be tuned effectively by adjusting the surface electron density and/or the optical cavity length. Since the surface electron density can be well controlled by the gate-voltage applied perpendicular to the TI surface, our theoretical results indicate that gated TI thin films may have potential applications in the electrically tunable THz plasmonic devices.

Approaching quantum anomalous Hall effect in proximity-coupled YIG/graphene/h-BN sandwich structure

NASA Astrophysics Data System (ADS)

Tang, Chi; Cheng, Bin; Aldosary, Mohammed; Wang, Zhiyong; Jiang, Zilong; Watanabe, K.; Taniguchi, T.; Bockrath, Marc; Shi, Jing

2018-02-01

Quantum anomalous Hall state is expected to emerge in Dirac electron systems such as graphene under both sufficiently strong exchange and spin-orbit interactions. In pristine graphene, neither interaction exists; however, both interactions can be acquired by coupling graphene to a magnetic insulator as revealed by the anomalous Hall effect. Here, we show enhanced magnetic proximity coupling by sandwiching graphene between a ferrimagnetic insulator yttrium iron garnet (YIG) and hexagonal-boron nitride (h-BN) which also serves as a top gate dielectric. By sweeping the top-gate voltage, we observe Fermi level-dependent anomalous Hall conductance. As the Dirac point is approached from both electron and hole sides, the anomalous Hall conductance reaches ¼ of the quantum anomalous Hall conductance 2e2/h. The exchange coupling strength is determined to be as high as 27 meV from the transition temperature of the induced magnetic phase. YIG/graphene/h-BN is an excellent heterostructure for demonstrating proximity-induced interactions in two-dimensional electron systems.

Fabrication of high performance thin-film transistors via pressure-induced nucleation.

PubMed

Kang, Myung-Koo; Kim, Si Joon; Kim, Hyun Jae

2014-10-31

We report a method to improve the performance of polycrystalline Si (poly-Si) thin-film transistors (TFTs) via pressure-induced nucleation (PIN). During the PIN process, spatial variation in the local solidification temperature occurs because of a non-uniform pressure distribution during laser irradiation of the amorphous Si layer, which is capped with an SiO2 layer. This leads to a four-fold increase in the grain size of the poly-Si thin-films formed using the PIN process, compared with those formed using conventional excimer laser annealing. We find that thin films with optimal electrical properties can be achieved with a reduction in the number of laser irradiations from 20 to 6, as well as the preservation of the interface between the poly-Si and the SiO2 gate insulator. This interface preservation becomes possible to remove the cleaning process prior to gate insulator deposition, and we report devices with a field-effect mobility greater than 160 cm(2)/Vs.

Enhanced and continuous electrostatic carrier doping on the SrTiO3 surface

PubMed Central

Eyvazov, A. B.; Inoue, I. H.; Stoliar, P.; Rozenberg, M. J.; Panagopoulos, C.

2013-01-01

Paraelectrical tuning of a charge carrier density as high as 1013 cm−2 in the presence of a high electronic carrier mobility on the delicate surfaces of correlated oxides, is a key to the technological breakthrough of a field effect transistor (FET) utilising the metal-nonmetal transition. Here we introduce the Parylene-C/Ta2O5 hybrid gate insulator and fabricate FET devices on single-crystalline SrTiO3, which has been regarded as a bedrock material for oxide electronics. The gate insulator accumulates up to ~1013cm−2 carriers, while the field-effect mobility is kept at 10 cm2/Vs even at room temperature. Further to the exceptional performance of our devices, the enhanced compatibility of high carrier density and high mobility revealed the mechanism for the long standing puzzle of the distribution of electrostatically doped carriers on the surface of SrTiO3. Namely, the formation and continuous evolution of field domains and current filaments.

Low trap states in in situ SiN{sub x}/AlN/GaN metal-insulator-semiconductor structures grown by metal-organic chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Xing; Ma, Jun; Jiang, Huaxing

2014-09-08

We report the use of SiN{sub x} grown in situ by metal-organic chemical vapor deposition as the gate dielectric for AlN/GaN metal-insulator-semiconductor (MIS) structures. Two kinds of trap states with different time constants were identified and characterized. In particular, the SiN{sub x}/AlN interface exhibits remarkably low trap state densities in the range of 10{sup 11}–10{sup 12 }cm{sup −2}eV{sup −1}. Transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the in situ SiN{sub x} layer can provide excellent passivation without causing chemical degradation to the AlN surface. These results imply the great potential of in situ SiN{sub x} as an effectivemore » gate dielectric for AlN/GaN MIS devices.« less

Automatic alternative phase-shift mask CAD layout tool for gate shrinkage of embedded DRAM in logic below 0.18 μm

NASA Astrophysics Data System (ADS)

Ohnuma, Hidetoshi; Kawahira, Hiroichi

1998-09-01

An automatic alternative phase shift mask (PSM) pattern layout tool has been newly developed. This tool is dedicated for embedded DRAM in logic device to shrink gate line width with improving line width controllability in lithography process with a design rule below 0.18 micrometers by the KrF excimer laser exposure. The tool can crete Levenson type PSM used being coupled with a binary mask adopting a double exposure method for positive photo resist. By using graphs, this tool automatically creates alternative PSM patterns. Moreover, it does not give any phase conflicts. By adopting it to actual embedded DRAM in logic cells, we have provided 0.16 micrometers gate resist patterns at both random logic and DRAM areas. The patterns were fabricated using two masks with the double exposure method. Gate line width has been well controlled under a practical exposure-focus window.

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

NASA Astrophysics Data System (ADS)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of doublemore » quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. Finally, we further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau–Zener–Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.« less

State-conditional coherent charge qubit oscillations in a Si/SiGe quadruple quantum dot

DOE PAGES

Ward, Daniel R.; Kim, Dohun; Savage, Donald E.; ...

2016-10-18

Universal quantum computation requires high-fidelity single-qubit rotations and controlled two-qubit gates. Along with high-fidelity single-qubit gates, strong efforts have been made in developing robust two-qubit logic gates in electrically gated quantum dot systems to realise a compact and nanofabrication-compatible architecture. Here we perform measurements of state-conditional coherent oscillations of a charge qubit. Using a quadruple quantum dot formed in a Si/SiGe heterostructure, we show the first demonstration of coherent two-axis control of a double quantum dot charge qubit in undoped Si/SiGe, performing Larmor and Ramsey oscillation measurements. We extract the strength of the capacitive coupling between a pair of doublemore » quantum dots by measuring the detuning energy shift (≈75 μeV) of one double dot depending on the excess charge configuration of the other double dot. Finally, we further demonstrate that the strong capacitive coupling allows fast, state-conditional Landau–Zener–Stückelberg oscillations with a conditional π phase flip time of about 80 ps, showing a promising pathway towards multi-qubit entanglement and control in semiconductor quantum dots.« less

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

NASA Astrophysics Data System (ADS)

Saravana Kumar, R.; Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.

2018-03-01

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As subchannel DG-HEMT with optimised device structure of 2 nm In0.48Al0.52As barrier layer show a peak gm of 3.09 mS/µm, VT of 0.29 V, ION/IOFF ratio of 2.24 × 105, subthreshold slope 73 mV/decade and drain induced barrier lowering 68 mV/V with fT and fmax of 776 and 905 GHz at Vds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Indium gallium arsenide microwave power transistors

NASA Technical Reports Server (NTRS)

Johnson, Gregory A.; Kapoor, Vik J.; Shokrani, Mohsen; Messick, Louis J.; Nguyen, Richard

1991-01-01

Depletion-mode InGaAs microwave power MISFETs with 1-micron gate lengths and up to 1-mm gate widths have been fabricated using an ion-implantation process. The devices employed a plasma-deposited silicon/silicon dioxide gate insulator. The dc I-V characteristics and RF power performance at 9.7 GHz are presented. The output power, power-added efficiency, and power gain as a function of input power are reported. An output power of 1.07 W with a corresponding power gain and power-added efficiency of 4.3 dB and 38 percent, respectively, was obtained. The large-gate-width devices provided over twice the previously reported output power for InGaAs MISFETs at X-band. In addition, output power stability within 1.2 percent over 24 h of continuous operation was achieved. In addition, a drain current drift of 4 percent over 10,000 sec was obtained.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Monolithic integration of a MOSFET with a MEMS device

DOEpatents

Bennett, Reid; Draper, Bruce

2003-01-01

An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

Covalency and the metal-insulator transition in titanate and vanadate perovskites

NASA Astrophysics Data System (ADS)

Dang, Hung T.; Millis, Andrew J.; Marianetti, Chris A.

2014-04-01

A combination of density functional and dynamical mean-field theory is applied to the perovskites SrVO3, LaTiO3, and LaVO3. We show that DFT + DMFT in conjunction with the standard fully localized-limit (FLL) double-counting predicts that LaTiO3 and LaVO3 are metals even though experimentally they are correlation-driven ("Mott") insulators. In addition, the FLL double counting implies a splitting between oxygen p and transition metal d levels, which differs from experiment. Introducing into the theory an ad hoc double counting correction, which reproduces the experimentally measured insulating gap leads also to a p-d splitting consistent with experiment if the on-site interaction U is chosen in a relatively narrow range (˜6±1 eV). The results indicate that these early transition metal oxides will serve as critical test for the formulation of a general ab initio theory of correlated electron metals.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

NASA Astrophysics Data System (ADS)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Double optical gating

NASA Astrophysics Data System (ADS)

Gilbertson, Steve

The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.

Measure Guideline: Deep Energy Enclosure Retrofit for Double-Stud Walls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Loomis, H.; Pettit, B.

2015-06-22

This Measure Guideline describes a deep energy enclosure retrofit solution that provides insulation to the interior of the wall assembly with the use of a double-stud wall. The guide describes two approaches to retrofitting the existing walls—one that involves replacing the existing cladding and the other that leaves the cladding in place. This guideline also covers the design principles related to the use of various insulation types and provides strategies and procedures for implementing the double-stud wall retrofit. It also includes an evaluation of important moisture-related and indoor air quality measures that need to be implemented to achieve a durablemore » high-performance wall.« less

Measure Guideline: Deep Energy Enclosure Retrofit for Double-Stud Walls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Loomis, H.; Pettit, B.

2015-06-01

This Measure Guideline describes a deep energy enclosure retrofit (DEER) solution that provides insulation to the interior of the wall assembly with the use of a double stud wall. The guide describes two approaches to retrofitting the existing the walls: one involving replacement of the existing cladding, and the other that leaves the existing cladding in place. It discusses the design principles related to the use of various insulation types, and provides strategies and procedures for implementing the double stud wall retrofit. It also evaluates important moisture-related and indoor air quality measures that need to be implemented to achieve amore » durable, high performance wall.« less

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Double optical gating of high-order harmonic generation with carrier-envelope phase stabilized lasers.

PubMed

Mashiko, Hiroki; Gilbertson, Steve; Li, Chengquan; Khan, Sabih D; Shakya, Mahendra M; Moon, Eric; Chang, Zenghu

2008-03-14

We demonstrated a novel optical switch to control the high-order harmonic generation process so that single attosecond pulses can be generated with multiple-cycle pulses. The technique combines two powerful optical gating methods: polarization gating and two-color gating. An extreme ultraviolet supercontinuum supporting 130 as was generated with neon gas using 9 fs laser pulses. We discovered a unique dependence of the harmonic spectra on the carrier-envelope phase of the laser fields, which repeats every 2 pi radians.

Double Optical Gating of High-Order Harmonic Generation with Carrier-Envelope Phase Stabilized Lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mashiko, Hiroki; Gilbertson, Steve; Li, Chengquan

2008-03-14

We demonstrated a novel optical switch to control the high-order harmonic generation process so that single attosecond pulses can be generated with multiple-cycle pulses. The technique combines two powerful optical gating methods: polarization gating and two-color gating. An extreme ultraviolet supercontinuum supporting 130 as was generated with neon gas using 9 fs laser pulses. We discovered a unique dependence of the harmonic spectra on the carrier-envelope phase of the laser fields, which repeats every 2{pi} radians.

Thermal performance of a liquid hydrogen tank multilayer insulation system at warm boundary temperatures of 630, 530, and 152 R

NASA Astrophysics Data System (ADS)

Stochl, Robert J.; Knoll, Richard H.

1991-06-01

The results are presented of a study conducted to obtain experimental heat transfer data on a liquid hydrogen tank insulated with 34 layers of MLI (multilayer insulation) for warm side boundary temperatures of 630, 530, and 150 R. The MLI system consisted of two blankets, each blanket made up of alternate layers of double silk net (16 layers) and double aluminized Mylar radiation shields (15 layers) contained between two cover sheets of Dacron scrim reinforced Mylar. The insulation system was designed for and installed on a 87.6 in diameter liquid hydrogen tank. Nominal layer density of the insulation blankets is 45 layers/in. The insulation system contained penetrations for structural support, plumbing, and electrical wiring that would be representative of a cryogenic spacecraft. The total steady state heat transfer rates into the test tank for shroud temperatures of 630, 530, 152 R were 164.4, 95.8, and 15.9 BTU/hr respectively. The noninsulation heat leaks into the tank (12 fiberglass support struts, tank plumbing, and instrumentation lines) represent between 13 to 17 pct. of the total heat input. The heat input values would translate to liquid H2 losses of 2.3, 1.3, and 0.2 pct/day, with the tank held at atmospheric pressure.

Thermal performance of a liquid hydrogen tank multilayer insulation system at warm boundary temperatures of 630, 530, and 152 R

NASA Astrophysics Data System (ADS)

Stochl, Robert J.; Knoll, Richard H.

1991-06-01

The results are presented of a study conducted to obtain experimental heat transfer data on a liquid hydrogen tank insulated with 34 layers of MLI (multilayer insulation) for warm side boundary temperatures of 630, 530, and 150 R. The MLI system consisted of two blankets, each blanket made up of alternate layers of double silk net (16 layers) and double aluminized Mylar radiation shields (15 layers) contained between two cover sheets of Dacron scrim reinforced Mylar. The insulation system was designed for and installed on an 87.6 in. diameter liquid hydrogen tank. Nominal layer density of the insulation blankets is 45 layers/in. The insulation system contained penetrations for structural support, plumbing, and electrical wiring that would be representative of a cryogenic spacecraft. The total steady state heat transfer rates into the test tank for shroud temperatures of 630, 530, 152 R were 164.4, 95.8, and 15.9 BTU/hr, respectively. The noninsulation heat leaks into the tank (12 fiberglass support struts, tank plumbing, and instrumentation lines) represent between 13 to 17 pct. of the total heat input. The heat input values would translate to liquid H2 losses of 2.3, 1.3, and 0.2 pct/day, with the tank held at atmospheric pressure.

Double helix boron-10 powder thermal neutron detector

DOEpatents

Wang, Zhehui; Morris, Christopher L.; Bacon, Jeffrey D.

2015-06-02

A double-helix Boron-10 powder detector having intrinsic thermal neutron detection efficiency comparable to 36'' long, 2-in diameter, 2-bar Helium-3 detectors, and which can be used to replace such detectors for use in portal monitoring, is described. An embodiment of the detector includes a metallic plate coated with Boron-10 powder for generating alpha and Lithium-7 particles responsive to neutrons impinging thereon supported by insulators affixed to at least two opposing edges; a grounded first wire wound in a helical manner around two opposing insulators; and a second wire having a smaller diameter than that of the first wire, wound in a helical manner around the same insulators and spaced apart from the first wire, the second wire being positively biased. A gas, disposed within a gas-tight container enclosing the plate, insulators and wires, and capable of stopping alpha and Lithium-7 particles and generating electrons produces a signal on the second wire which is detected and subsequently related to the number of neutrons impinging on the plate.

Dimensionality-Driven Metal-Insulator Transition in Spin-Orbit-Coupled SrIrO3

NASA Astrophysics Data System (ADS)

Schütz, P.; Di Sante, D.; Dudy, L.; Gabel, J.; Stübinger, M.; Kamp, M.; Huang, Y.; Capone, M.; Husanu, M.-A.; Strocov, V. N.; Sangiovanni, G.; Sing, M.; Claessen, R.

2017-12-01

Upon reduction of the film thickness we observe a metal-insulator transition in epitaxially stabilized, spin-orbit-coupled SrIrO3 ultrathin films. By comparison of the experimental electronic dispersions with density functional theory at various levels of complexity we identify the leading microscopic mechanisms, i.e., a dimensionality-induced readjustment of octahedral rotations, magnetism, and electronic correlations. The astonishing resemblance of the band structure in the two-dimensional limit to that of bulk Sr2 IrO4 opens new avenues to unconventional superconductivity by "clean" electron doping through electric field gating.

Degradation diagnosis of transformer insulating oils with terahertz time-domain spectroscopy

NASA Astrophysics Data System (ADS)

Kang, Seung Beom; Kim, Won-Seok; Chung, Dong Chul; Joung, Jong Man; Kwak, Min Hwan

2017-12-01

We report the frequency-dependent complex optical constants, refractive index and absorption, and complex dielectric properties over the frequency range from 0.2 to 3.0 THz for aged power transformer mineral insulating oils. These results have been obtained using terahertz time-domain spectroscopy (THz-TDS) and demonstrate the double-Debye relaxation behavior of the mineral insulating oil. The measured complex optical and dielectric characteristics can be important benchmarks for liquid molecular dynamics and theoretical studies of insulating oils. Due to clear differences in THz responses of aged mineral insulating oils, THz-TDS can be used as a novel on-site diagnostic technique to monitor the insulation condition in aged power transformers and may be valuable alternative to characterize other developing eco-friendly insulating oils and industrial liquids.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Spin transport in lateral structures with semiconducting channel

NASA Astrophysics Data System (ADS)

Zainuddin, Abu Naser

Spintronics is an emerging field of electronics with the potential to be used in future integrated circuits. Spintronic devices are already making their mark in storage technologies in recent times and there are proposals for using spintronic effects in logic technologies as well. So far, major improvement in spintronic effects, for example, the `spin-valve' effect, is being achieved in metals or insulators as channel materials. But not much progress is made in semiconductors owing to the difficulty in injecting spins into them, which has only very recently been overcome with the combined efforts of many research groups around the world. The key motivations for semiconductor spintronics are their ease in integration with the existing semiconductor technology along with the gate controllability. At present semiconductor based spintronic devices are mostly lateral and are showing a very poor performance compared to their metal or insulator based vertical counterparts. The objective of this thesis is to analyze these devices based on spin-transport models and simulations. At first a lateral spin-valve device is modeled with the spin-diffusion equation based semiclassical approach. Identifying the important issues regarding the device performance, a compact circuit equivalent model is presented which would help to improve the device design. It is found that the regions outside the current path also have a significant influence on the device performance under certain conditions, which is ordinarily neglected when only charge transport is considered. Next, a modified spin-valve structure is studied where the spin signal is controlled with a gate in between the injecting and detecting contacts. The gate is used to modulate the rashba spin-orbit coupling of the channel which, in turn, modulates the spin-valve signal. The idea of gate controlled spin manipulation was originally proposed by Datta and Das back in 1990 and is called 'Datta-Das' effect. In this thesis, we have extended the model described in the original proposal to include the influence of channel dimensions on the nature of electron flow and the contact dimensions on the magnitude and phase of the spin-valve signal. In order to capture the spin-orbit effect a non-equilibrium Green's function (NEGF) based quantum transport model for spin-valve device have been developed which is also explained with simple theoretical treatment based on stationary phase approximation. The model is also compared against a recent experiment that demonstrated such gate modulated spin-valve effect. This thesis also evaluates the possibility of gate controlled magnetization reversal or spin-torque effect as a means to validate this, so called, 'Datta-Das' effect on a more solid footing. Finally, the scope for utilizing topological insulator material in semiconductor spintronics is discussed as a possible future work for this thesis.

Poole Frenkel current and Schottky emission in SiN gate dielectric in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Hanna, Mina J.; Zhao, Han; Lee, Jack C.

2012-10-01

We analyze the anomalous I-V behavior in SiN prepared by plasma enhanced chemical vapor deposition for use as a gate insulator in AlGaN/GaN metal insulator semiconductor heterostructure filed effect transistors (HFETs). We observe leakage current across the dielectric with opposite polarity with respect to the applied electric field once the voltage sweep reaches a level below a determined threshold. This is observed as the absolute minimum of the leakage current does not occur at minimum voltage level (0 V) but occurs earlier in the sweep interval. Curve-fitting analysis suggests that the charge-transport mechanism in this region is Poole-Frenkel current, followed by Schottky emission due to band bending. Despite the current anomaly, the sample devices have shown a notable reduction of leakage current of over 2 to 6 order of magnitudes compared to the standard Schottky HFET. We show that higher pressures and higher silane concentrations produce better films manifesting less trapping. This conforms to our results that we reported in earlier publications. We found that higher chamber pressure achieves higher sheet carrier concentration that was found to be strongly dependent on the trapped space charge at the SiN/GaN interface. This would suggest that a lower chamber pressure induces more trap states into the SiN/GaN interface.

Force Measurements of Single and Double Barrier DBD Plasma Actuators in Quiescent Air

NASA Technical Reports Server (NTRS)

Hoskinson, Alan R.; Hershkowitz, Noah; Ashpis, David E.

2008-01-01

We have performed measurements of the force induced by both single (one electrode insulated) and double (both electrodes insulated) dielectric barrier discharge plasma actuators in quiescent air. We have shown that, for single barrier actuators, as the electrode diameter decreased below those values previously studied the induced Force increases exponentially rather than linearly. This behavior has been experimentally verified using two different measurement techniques: stagnation probe measurements of the induced flow velocity and direct measurement of the force using an electronic balance. In addition, we have shown the the induced force is independent of the material used for the exposed electrode. The same techniques have shown that the induced force of a double barrier actuator increases with decreasing narrow electrode diameter.

Noise characterization of enhancement-mode AlGaN graded barrier MIS-HEMT devices

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Saravana Kumar, R.; Mohankumar, N.

2017-12-01

This paper reports a systematic theoretical study on the microwave noise performance of graded AlGaN/GaN metal-insulator semiconductor high-electron mobility transistors (MIS-HEMTs) built on an Al2O3 substrate. The HfAlOx/AlGaN/GaN MIS-HEMT devices designed for this study show an outstanding small signal analog/RF and noise performance. The results on 1 μm gate length device show an enhancement mode operation with threshold voltage, VT = + 5.3 V, low drain leakage current, Ids,LL in the order of 1 × 10-9 A/mm along with high current gain cut-off frequency, fT of 17 GHz and maximum oscillation frequency fmax of 47 GHz at Vds = 10 V. The device Isbnd V and low-frequency noise estimation of the gate and drain noise spectral density and their correlation are evaluated using a Green's function method under different biasing conditions. The devices show a minimum noise figure (NFmin) of 1.053 dB in combination with equivalent noise resistance (Rn) of 23 Ω at 17 GHz, at Vgs = 6 V and Vds = 5 V which is relatively low and is suitable for broad-band low-noise amplifiers. This study shows that the graded AlGaN MIS-HEMT with HfAlOX gate insulator is appropriate for application requiring high-power and low-noise.

Electric-field-induced extremely large change in resistance in graphene ferromagnets

NASA Astrophysics Data System (ADS)

Song, Yu

2018-01-01

A colossal magnetoresistance (˜100×10^3% ) and an extremely large magnetoresistance (˜1×10^6% ) have been previously explored in manganite perovskites and Dirac materials, respectively. However, the requirement of an extremely strong magnetic field (and an extremely low temperature) makes them not applicable for realistic devices. In this work, we propose a device that can generate even larger changes in resistance in a zero-magnetic field and at a high temperature. The device is composed of graphene under two strips of yttrium iron garnet (YIG), where two gate voltages are applied to cancel the heavy charge doping in the YIG-induced half-metallic ferromagnets. By calculations using the Landauer-Büttiker formalism, we demonstrate that, when a proper gate voltage is applied on the free ferromagnet, changes in resistance up to 305×10^6% (16×10^3% ) can be achieved at the liquid helium (nitrogen) temperature and in a zero magnetic field. We attribute such a remarkable effect to a gate-induced full-polarization reversal in the free ferromagnet, which results in a metal-state to insulator-state transition in the device. We also find that the proposed effect can be realized in devices using other magnetic insulators, such as EuO and EuS. Our work should be helpful for developing a realistic switching device that is energy saving and CMOS-technology compatible.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Solid-gate control of insulator to 2D metal transition at SrTiO3 surface

NASA Astrophysics Data System (ADS)

Schulman, Alejandro; Stoliar, Pablo; Kitoh, Ai; Rozenberg, Marcelo; Inoue, Isao H.

As miniaturization of the semiconductor transistor approaches its limit, semiconductor industries are facing a major challenge to extend information processing beyond what can be attainable by conventional Si-based transistors. Innovative combinations of new materials and new processing platforms are desired. Recent discovery of the 2D electron gas (2DEG) at the surface of SrTiO3 (STO) and its electrostatic control, have carried it to the top of promising materials to be utilized in innovative devices. We report an electrostatic control of the carrier density of the 2DEG formed at the channel of bilayer-gated STO field-effect devices. By applying a gate electric field at room temperature, its highly insulating channel exhibits a transition to metallic one. This transition is accompanied by non-monotonic voltage-gain transfer characteristic with both negative and positive slope regions and unexpected enhancement of the sheet carrier density. We will introduce a numerical model to rationalize the observed features in terms of the established physics of field-effect transistors and the physics of percolation. Furthermore, we have found a clear signature of a Kondo effect that arises due to the interaction between the dilute 2DEG and localized Ti 3d orbitals originated by oxygen vacancies near the channel. On leave from CIC nanoGUNE, Spain.

Gate-tunable resonant tunneling in double bilayer graphene heterostructures.

PubMed

Fallahazad, Babak; Lee, Kayoung; Kang, Sangwoo; Xue, Jiamin; Larentis, Stefano; Corbet, Christopher; Kim, Kyounghwan; Movva, Hema C P; Taniguchi, Takashi; Watanabe, Kenji; Register, Leonard F; Banerjee, Sanjay K; Tutuc, Emanuel

2015-01-14

We demonstrate gate-tunable resonant tunneling and negative differential resistance in the interlayer current-voltage characteristics of rotationally aligned double bilayer graphene heterostructures separated by hexagonal boron nitride (hBN) dielectric. An analysis of the heterostructure band alignment using individual layer densities, along with experimentally determined layer chemical potentials indicates that the resonance occurs when the energy bands of the two bilayer graphene are aligned. We discuss the tunneling resistance dependence on the interlayer hBN thickness, as well as the resonance width dependence on mobility and rotational alignment.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Scalable photonic quantum computing assisted by quantum-dot spin in double-sided optical microcavity.

PubMed

Wei, Hai-Rui; Deng, Fu-Guo

2013-07-29

We investigate the possibility of achieving scalable photonic quantum computing by the giant optical circular birefringence induced by a quantum-dot spin in a double-sided optical microcavity as a result of cavity quantum electrodynamics. We construct a deterministic controlled-not gate on two photonic qubits by two single-photon input-output processes and the readout on an electron-medium spin confined in an optical resonant microcavity. This idea could be applied to multi-qubit gates on photonic qubits and we give the quantum circuit for a three-photon Toffoli gate. High fidelities and high efficiencies could be achieved when the side leakage to the cavity loss rate is low. It is worth pointing out that our devices work in both the strong and the weak coupling regimes.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Using stepped anvils to make even insulation layers in laser-heated diamond-anvil cell samples

DOE Office of Scientific and Technical Information (OSTI.GOV)

Du, Zhixue; Gu, Tingting; Dobrosavljevic, Vasilije

Here, we describe a method to make even insulation layers for high-pressure laser-heated diamond-anvil cell samples using stepped anvils. Moreover, the method works for both single-sided and double-sided laser heating using solid or fluid insulation. The stepped anvils are used as matched pairs or paired with a flat culet anvil to make gasket insulation layers and not actually used at high pressures; thus, their longevity is ensured. We also compare the radial temperature gradients and Soret diffusion of iron between self-insulating samples and samples produced with stepped anvils and find that less pronounced Soret diffusion occurs in samples with evenmore » insulation layers produced by stepped anvils.« less

Using stepped anvils to make even insulation layers in laser-heated diamond-anvil cell samples

DOE PAGES

Du, Zhixue; Gu, Tingting; Dobrosavljevic, Vasilije; ...

2015-09-01

Here, we describe a method to make even insulation layers for high-pressure laser-heated diamond-anvil cell samples using stepped anvils. Moreover, the method works for both single-sided and double-sided laser heating using solid or fluid insulation. The stepped anvils are used as matched pairs or paired with a flat culet anvil to make gasket insulation layers and not actually used at high pressures; thus, their longevity is ensured. We also compare the radial temperature gradients and Soret diffusion of iron between self-insulating samples and samples produced with stepped anvils and find that less pronounced Soret diffusion occurs in samples with evenmore » insulation layers produced by stepped anvils.« less

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Scalable quantum computing based on stationary spin qubits in coupled quantum dots inside double-sided optical microcavities

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Deng, Fu-Guo

2014-12-01

Quantum logic gates are the key elements in quantum computing. Here we investigate the possibility of achieving a scalable and compact quantum computing based on stationary electron-spin qubits, by using the giant optical circular birefringence induced by quantum-dot spins in double-sided optical microcavities as a result of cavity quantum electrodynamics. We design the compact quantum circuits for implementing universal and deterministic quantum gates for electron-spin systems, including the two-qubit CNOT gate and the three-qubit Toffoli gate. They are compact and economic, and they do not require additional electron-spin qubits. Moreover, our devices have good scalability and are attractive as they both are based on solid-state quantum systems and the qubits are stationary. They are feasible with the current experimental technology, and both high fidelity and high efficiency can be achieved when the ratio of the side leakage to the cavity decay is low.

Scalable quantum computing based on stationary spin qubits in coupled quantum dots inside double-sided optical microcavities.

PubMed

Wei, Hai-Rui; Deng, Fu-Guo

2014-12-18

Quantum logic gates are the key elements in quantum computing. Here we investigate the possibility of achieving a scalable and compact quantum computing based on stationary electron-spin qubits, by using the giant optical circular birefringence induced by quantum-dot spins in double-sided optical microcavities as a result of cavity quantum electrodynamics. We design the compact quantum circuits for implementing universal and deterministic quantum gates for electron-spin systems, including the two-qubit CNOT gate and the three-qubit Toffoli gate. They are compact and economic, and they do not require additional electron-spin qubits. Moreover, our devices have good scalability and are attractive as they both are based on solid-state quantum systems and the qubits are stationary. They are feasible with the current experimental technology, and both high fidelity and high efficiency can be achieved when the ratio of the side leakage to the cavity decay is low.

Extended-gate-type IGZO electric-double-layer TFT immunosensor with high sensitivity and low operation voltage

NASA Astrophysics Data System (ADS)

Liang, Lingyan; Zhang, Shengnan; Wu, Weihua; Zhu, Liqiang; Xiao, Hui; Liu, Yanghui; Zhang, Hongliang; Javaid, Kashif; Cao, Hongtao

2016-10-01

An immunosensor is proposed based on the indium-gallium-zinc-oxide (IGZO) electric-double-layer thin-film transistor (EDL TFT) with a separating extended gate. The IGZO EDL TFT has a field-effect mobility of 24.5 cm2 V-1 s-1 and an operation voltage less than 1.5 V. The sensors exhibit the linear current response to label-free target immune molecule in the concentrations ranging from 1.6 to 368 × 10-15 g/ml with a detection limit of 1.6 × 10-15 g/ml (0.01 fM) under an ultralow operation voltage of 0.5 V. The IGZO TFT component demonstrates a consecutive assay stability and recyclability due to the unique structure with the separating extended gate. With the excellent electrical properties and the potential for plug-in-card-type multifunctional sensing, extended-gate-type IGZO EDL TFTs can be promising candidates for the development of a label-free biosensor for public health applications.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Nonstoichiometric Solution-Processed BaTiO₃ Film for Gate Insulator Applications.

PubMed

Lau, Joyce; Kim, Sangsub; Kim, Hyunki; Koo, Kwangjun; Lee, Jaeseob; Kim, Sangsoo; Choi, Byoungdeog

2018-09-01

Solution processed barium titanate (BTO) was used to fabricate an Al/BaTiO3/p-Si metal-insulator-semiconductor (MIS) structure, which was used as a gate insulator. Changes in the electrical characteristics of the film were investigated as a function of the film thickness and post deposition annealing conditions. Our results showed that a thickness of 5 layers and an annealing temperature of 650 °C produced the highest electrical performance. BaxTi1-xO3 was altered at x = 0.10, 0.30, 0.50, 0.70, 0.90, and 1.0 to investigate changes in the electrical properties as a function of composition. The highest dielectric constant of 87 was obtained for x = 0.10, while the leakage current density was suppressed as Ba content increased. The lowest leakage current density was 1.34×10-10 A/cm2, which was observed at x = 0.90. The leakage current was related to the resistivity of the film, the interface states, and grain densification. Space charge limited current (SCLC) was the dominant leakage mechanism in BTO films based on leakage current analysis. Although a Ba content of x = 0.90 had the highest trap density, the traps were mainly composed of Ti-vacancies, which acted as strong electron traps and affected the film resistivity. A secondary phase, Ba2TiO4, which was observed in cases of excess Ba, acted as a grain refiner and provided faster densification of the film during the thermal process. The absence of a secondary phase in BaO (x = 1.0) led to the formation of many interface states and degradation in the electrical properties. Overall, the insulator properties of BTO were improved when the composition ratio was x = 0.90.

Development of a 3D finite element acoustic model to predict the sound reduction index of stud based double-leaf walls

NASA Astrophysics Data System (ADS)

Arjunan, A.; Wang, C. J.; Yahiaoui, K.; Mynors, D. J.; Morgan, T.; Nguyen, V. B.; English, M.

2014-11-01

Building standards incorporating quantitative acoustical criteria to ensure adequate sound insulation are now being implemented. Engineers are making great efforts to design acoustically efficient double-wall structures. Accordingly, efficient simulation models to predict the acoustic insulation of double-leaf wall structures are needed. This paper presents the development of a numerical tool that can predict the frequency dependent sound reduction index R of stud based double-leaf walls at one-third-octave band frequency range. A fully vibro-acoustic 3D model consisting of two rooms partitioned using a double-leaf wall, considering the structure and acoustic fluid coupling incorporating the existing fluid and structural solvers are presented. The validity of the finite element (FE) model is assessed by comparison with experimental test results carried out in a certified laboratory. Accurate representation of the structural damping matrix to effectively predict the R values are studied. The possibilities of minimising the simulation time using a frequency dependent mesh model was also investigated. The FEA model presented in this work is capable of predicting the weighted sound reduction index Rw along with A-weighted pink noise C and A-weighted urban noise Ctr within an error of 1 dB. The model developed can also be used to analyse the acoustically induced frequency dependent geometrical behaviour of the double-leaf wall components to optimise them for best acoustic performance. The FE modelling procedure reported in this paper can be extended to other building components undergoing fluid-structure interaction (FSI) to evaluate their acoustic insulation.

Non-scaling behavior of electroosmotic flow in voltage-gated nanopores

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lian, Cheng; Gallegos, Alejandro; Liu, Honglai

2017-01-01

Ionic size effects and electrostatic correlations result in the non-monotonic dependence of the electrical conductivity on the pore size. For ion transport at a high gating voltage, the conductivity oscillates with the pore size due to a significant overlap of the electric double layers.

A Survey of Solid-State Microwave Power Devices

DTIC Science & Technology

1977-04-29

from the channel by a thin oxide layer (insulated gate FET or IGFET), it may be a diffused junction at the top of the channel (junction FET or JFET...greater than 100 GHz. YIG-tuned units are finding increasing use as extremely stable sources, whereas varactor tuning is used where tuning speed is

Dual ion beam processed diamondlike films for industrial applications

NASA Technical Reports Server (NTRS)

Mirtich, M. J.; Kussmaul, M. T.; Banks, B. A.; Sovey, J. S.

1991-01-01

Single and dual beam ion source systems are used to generate amorphous diamondlike carbon (DLC) films, which were evaluated for a variety of applications including protective coatings on transmitting materials, power electronics as insulated gates and corrosion resistant barriers. A list of the desirable properties of DLC films along with potential applications are presented.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Fabrication of solution-processed InSnZnO/ZrO2 thin film transistors.

PubMed

Hwang, Soo Min; Lee, Seung Muk; Choi, Jun Hyuk; Lim, Jun Hyung; Joo, Jinho

2013-11-01

We fabricated InSnZnO (ITZO) thin-film transistors (TFTs) with a high-permittivity (K) ZrO2 gate insulator using a solution process and explored the microstructure and electrical properties. ZrO2 and ITZO (In:Sn:Zn = 2:1:1) precursor solutions were deposited using consecutive spin-coating and drying steps on highly doped p-type Si substrate, followed by annealing at 700 degrees C in ambient air. The ITZO/ZrO2 TFT device showed n-channel depletion mode characteristics, and it possessed a high saturation mobility of approximately 9.8 cm2/V x s, a small subthreshold voltage swing of approximately 2.3 V/decade, and a negative V(TH) of approximately 1.5 V, but a relatively low on/off current ratio of approximately 10(-3). These results were thought to be due to the use of the high-kappa crystallized ZrO2 dielectric (kappa approximately 21.8) as the gate insulator, which could permit low-voltage operation of the solution-processed ITZO TFT devices for applications to high-throughput, low-cost, flexible and transparent electronics.

Chemical shift and surface characteristics of Al-doped ZnO thin film on SiOC dielectrics.

PubMed

Oh, Teresa; Lee, Sang Yeol

2013-10-01

Aluminum doped zinc oxide (AZO) films were fabricated on SiOC/p-Si wafer and SiOC film was prepared on a p-type Si substrate with the SiC target at oxygen ambient with the gas flow rate of 5-30 sccm by a RF magnetron sputter. C-V curve of SiOC/Si wafer was measured to observe the relationship between the polarity of SiOC dielectrics and the change of capacitance depending on oxygen gas flow rate. The SiOC film could be controlled to be polar or nonpolar, and their surface energy was changed depending on the polarity. Smooth surface is essential to improve the TFT performance. AZO-TFTs used smooth SiOC film with low polarity as a gate insulator was observed to show low leakage current (IL) and low subthreshold voltage swing. It is proposed that SiOC film with high degree amorphous structure as a gate insulator between AZO and Si wafer could solve problems of the mismatched interfaces, which was originated from the electron scattering due to the grain boundary.

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

Monolithically integrated Si gate-controlled light-emitting device: science and properties

NASA Astrophysics Data System (ADS)

Xu, Kaikai

2018-02-01

The motivation of this study is to develop a p-n junction based light emitting device, in which the light emission is conventionally realized using reverse current driving, by voltage driving. By introducing an additional terminal of insulated gate for voltage driving, a novel three-terminal Si light emitting device is described where both the light intensity and spatial light pattern of the device are controlled by the gate voltage. The proposed light emitting device employs injection-enhanced Si in avalanche mode where electric field confinement occurs in the corner of a reverse-biased p+n junction. It is found that, depending on the bias conditions, the light intensity is either a linear or a quadratic function of the applied gate voltage or the reverse-bias. Since the light emission is based on the avalanching mode, the Si light emitting device offers the potential for very large scale integration-compatible light emitters for inter- or intra-chip signal transmission and contactless functional testing of wafers.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-06-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-05-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Self-Organization of Ions at the Interface between Graphene and Ionic Liquid DEME-TFSI.

PubMed

Hu, Guangliang; Pandey, Gaind P; Liu, Qingfeng; Anaredy, Radhika S; Ma, Chunrui; Liu, Ming; Li, Jun; Shaw, Scott K; Wu, Judy

2017-10-11

Electrochemical effects manifest as nonlinear responses to an applied electric field in electrochemical devices, and are linked intimately to the molecular orientation of ions in the electric double layer (EDL). Herein, we probe the origin of the electrochemical effect using a double-gate graphene field effect transistor (GFET) of ionic liquid N,N-diethyl-N-(2-methoxyethyl)-N-methylammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI) top-gate, paired with a ferroelectric Pb 0.92 La 0.08 Zr 0.52 Ti 0.48 O 3 (PLZT) back-gate of compatible gating efficiency. The orientation of the interfacial molecular ions can be extracted by measuring the GFET Dirac point shift, and their dynamic response to ultraviolet-visible light and a gate electric field was quantified. We have observed that the strong electrochemical effect is due to the TFSI anions self-organizing on a treated GFET surface. Moreover, a reversible order-disorder transition of TFSI anions self-organized on the GFET surface can be triggered by illuminating the interface with ultraviolet-visible light, revealing that it is a useful method to control the surface ion configuration and the overall performance of the device.

Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

PubMed

Fratto, Brian E; Katz, Evgeny

2015-05-18

Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

NASA Astrophysics Data System (ADS)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Topological insulators double perovskites: A2TePoO6 (A = Ca, Sr, Ba)

NASA Astrophysics Data System (ADS)

Lee, Po-Han; Zhou, Jian; Pi, Shu-Ting; Wang, Yin-Kuo

2017-12-01

Based on first-principle calculations and direct density functional theory calculations of surface bands, we predict a new class of three-dimensional (3D) Z2 topological insulators (TIs) with larger bulk bandgaps up to 0.4 eV in double perovskite materials A2TePoO6 (A = Ca, Sr, and Ba). The larger nontrivial gaps are induced by the symmetry-protected band contact along with band inversion occurring in the absence of spin-orbit coupling (SOC) making the SOC more effective than conventional TIs. The proposed materials are chemically inert and more robust to surface perturbations due to its intrinsic protection layer. This study provides the double perovskite material as a rich platform to design new TI-based electronic devices.

Ellipticity dependence of high harmonics generated using 400 nm driving lasers

NASA Astrophysics Data System (ADS)

Cheng, Yan; Khan, Sabih; Zhao, Kun; Zhao, Baozhen; Chini, Michael; Chang, Zenghu

2011-05-01

High order harmonics generated from 400 nm driving pulses hold promise of scaling photon flux of single attosecond pulses by one to two orders of magnitude. We report ellipticity dependence and phase matching of high order harmonics generated from such pulses in Neon gas target and compared them with similar measurements using 800 nm driving pulses. Based on measured ellipticity dependence, we predict that double optical gating (DOG) and generalized double optical gating (GDOG) can be employed to extract intense single attosecond pulses from pulse train, while polarization gating (PG) may not work for this purpose. This material is supported by the U.S. Army Research Office under grant number W911NF-07-1-0475, and by the Chemical Sciences, Geosciences and Biosciences Division, Office of Basic Energy Sciences, Office of Science, U.S. Department of Energy.

Variable N-type negative resistance in an injection-gated double-injection diode

NASA Technical Reports Server (NTRS)

Kapoor, A. K.; Henderson, H. T.

1981-01-01

Double-injection (DI) switching devices consist of p+ and n+ contacts (for hole and electron injection, respectively), separated by a near intrinsic semiconductor region containing deep traps. Under proper conditions, these devices exhibit S-type differential negative resistance (DNR) similar to silicon-controlled rectifiers. With the added influence of a p+ gate appropriately placed between the anode (p+) and cathode (n+), the current-voltage characteristic of the device has been manipulated for the first time to exhibit a variable N-type DNR. The anode current and the anode-to-cathode voltage levels at which this N-type DNR is observed can be varied by changing the gate-to-cathode bias. In essence, the classical S-type DI diode can be electronically transformed into an N-type diode. A first-order phenomenological model is proposed for the N-type DNR.

10 CFR 429.53 - Walk-in coolers and walk-in freezers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... insulation, and a declaration that the manufacturer has incorporated the applicable design requirements. In... windows (e.g., double-pane with heat reflective treatment, triple-pane glass with gas fill), and the power...-value of the insulation (except for glazed portions of the doors or structural members) (iii) For WICF...

10 CFR 429.53 - Walk-in coolers and walk-in freezers.

Code of Federal Regulations, 2013 CFR

2013-01-01

... insulation, and a declaration that the manufacturer has incorporated the applicable design requirements. In... windows (e.g., double-pane with heat reflective treatment, triple-pane glass with gas fill), and the power...-value of the insulation (except for glazed portions of the doors or structural members) (iii) For WICF...

77 FR 12584 - Gorell Enterprises, Inc.; Analysis of Proposed Consent Order To Aid Public Comment

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-01

... location, size, insulation package, and existing windows. Consumers who replace single or double-paned wood... a building having a specific level of insulation in a specific region). The performance standard... consumption, energy savings, energy costs, heating and cooling costs, U-factor, solar heat gain coefficient, R...

10 CFR 429.53 - Walk-in coolers and walk-in freezers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... insulation, and a declaration that the manufacturer has incorporated the applicable design requirements. In... windows (e.g., double-pane with heat reflective treatment, triple-pane glass with gas fill), and the power...-value of the insulation (except for glazed portions of the doors or structural members) (iii) For WICF...

Understanding mobility degeneration mechanism in organic thin-film transistors (OTFT)

NASA Astrophysics Data System (ADS)

Wang, Wei; Wang, Long; Xu, Guangwei; Gao, Nan; Wang, Lingfei; Ji, Zhuoyu; Lu, Congyan; Lu, Nianduan; Li, Ling; Liu, Miwng

2017-08-01

Mobility degradation at high gate bias is often observed in organic thin film transistors. We propose a mechanism for this confusing phenomenon, based on the percolation theory with the presence of disordered energy landscape with an exponential density of states. Within a simple model we show how the surface states at insulator/organic interface trap a portion of channel carriers, and result in decrease of mobility as well as source/drain current with gate voltage. Depending on the competition between the carrier accumulation and surface trapping effect, two different carrier density dependences of mobility are obtained, in excellent agreement with experiment data.

Berry phase mechanism of the anomalous Hall effect in a disordered two-dimensional magnetic semiconductor structure

PubMed Central

Oveshnikov, L. N.; Kulbachinskii, V. A.; Davydov, A. B.; Aronzon, B. A.; Rozhansky, I. V.; Averkiev, N. S.; Kugel, K. I.; Tripathi, V.

2015-01-01

The anomalous Hall effect (AHE) arises from the interplay of spin-orbit interactions and ferromagnetic order and is a potentially useful probe of electron spin polarization, especially in nanoscale systems where direct measurement is not feasible. While AHE is rather well-understood in metallic ferromagnets, much less is known about the relevance of different physical mechanisms governing AHE in insulators. As ferromagnetic insulators, but not metals, lend themselves to gate-control of electron spin polarization, understanding AHE in the insulating state is valuable from the point of view of spintronic applications. Among the mechanisms proposed in the literature for AHE in insulators, the one related to a geometric (Berry) phase effect has been elusive in past studies. The recent discovery of quantized AHE in magnetically doped topological insulators - essentially a Berry phase effect - provides strong additional motivation to undertake more careful search for geometric phase effects in AHE in the magnetic semiconductors. Here we report our experiments on the temperature and magnetic field dependences of AHE in insulating, strongly-disordered two-dimensional Mn delta-doped semiconductor heterostructures in the hopping regime. In particular, it is shown that at sufficiently low temperatures, the mechanism of AHE related to the Berry phase is favoured. PMID:26596472

Environmental impact of thermal insulations: How do natural insulation products differ from synthetic ones?

NASA Astrophysics Data System (ADS)

Dovjak, M.; Košir, M.; Pajek, L.; Iglič, N.; Božiček, D.; Kunič, R.

2017-10-01

As the environmental awareness of the public is rising and at the same time contemporary buildings are becoming more and more energy efficient, the focus is shifting towards the usage of environmentally friendly building products. Human decisions are often driven by emotions and perceptions. Consequently, there exists a strong tendency towards preferring “natural” constructional products to the synthetic ones, especially in the case of thermal insulations. Life cycle assessment (LCA) has enabled an opportunity to widen the meaning of the word “environmentally friendly”, giving researchers and building designers an objective decision making tool to determine the environmental impact of building products, building components and buildings as a whole. The purpose of this study was to compare the environmental impact of various thermal insulations for the cradle to gate life cycle stages, based on a unified functional unit. Overall, 15 most commonly used thermal insulation products were analysed and classified into natural and synthetic groups. Based on the differentiation, we compared the impact in the selected environmental categories and identified the most influential environmental drivers. The results show that in some environmental categoriesnatural thermal insulations perform better (i.e. global warming potential), whilein others (i.e. eutrophication potential) they underperform. However, environmental impact trends can be identified, specifically for the natural and the synthetic materials.

Insulation Progress since the Mid-1950s

NASA Astrophysics Data System (ADS)

Timmerhaus, K. D.

Storage vessel and cryostat design for modern cryogenic systems has become rather routine as the result of the wide use of and application of cryogenic fluids. Such vessels for these fluids range in size from 1 L flasks used in the laboratory for liquid nitrogen to the more than 200,000 m3 double-walled tanks used for temporary storage of liquefied natural gas before being transported overseas to their final destination. These storage vessels for cryogenic fluids range in type from low-performance containers insulated with rigid foam or fibrous insulation to high-performance containers insulated with evacuated multilayer insulations. The overriding factors in the type of container selected normally are of economics and safety. This paper will consider various insulation concepts used in such cryogenic storage systems and will review the progress that has been made over the past 50 years in these insulation systems.

Purging of multilayer insulation by gas diffusion

NASA Technical Reports Server (NTRS)

Sumner, I. E.; Spuckler, C. M.

1976-01-01

An experimental investigation was conducted to determine the time required to purge a multilayer insulation (MLI) panel with gaseous helium by means of gas diffusion to obtain a condensable (nitrogen) gas concentration of less than 1 percent within the panel. Two flat, rectangular MLI panel configurations, one incorporating a butt joint, were tested. The insulation panels consisted of 15 double-aluminized Mylar radiation shields separated by double silk net spacers. The test results indicated that the rate which the condensable gas concentration at the edge or at the butt joint of an MLI panel was reduced was a significant factor in the total time required to reduce the condensable gas concentration within the panel to less than 1 percent. The experimental data agreed well with analytical predictions made by using a simple, one-dimensional gas diffusion model in which the boundary conditions at the edge of the MLI panel were time dependent.

Property Changes of Cyanate Ester/epoxy Insulation Systems Caused by AN Iter-Like Double Impregnation and by Reactor Irradiation

NASA Astrophysics Data System (ADS)

Prokopec, R.; Humer, K.; Fillunger, H.; Maix, R. K.; Weber, H. W.

2010-04-01

Because of the double pancake design of the ITER TF coils the insulation will be applied in several steps. As a consequence, the conductor insulation as well as the pancake insulation will undergo multiple heat cycles in addition to the initial curing cycle. In particular the properties of the organic resin may be influenced, since its heat resistance is limited. Two identical types of sample consisting of wrapped R-glass/Kapton layers and vacuum impregnated with a cyanate ester/epoxy blend were prepared. The build-up of the reinforcement was identical for both insulation systems; however, one system was fabricated in two steps. In the first step only one half of the reinforcing layers was impregnated and cured. Afterwards the remaining layers were wrapped onto the already cured system, before the resulting system was impregnated and cured again. The mechanical properties were characterized prior to and after irradiation to fast neutron fluences of 1 and 2×1022 m-2 (E>0.1 MeV) in tension and interlaminar shear at 77 K. In order to simulate the pulsed operation of ITER, tension-tension fatigue measurements were performed in the load controlled mode. The results do not show any evidence for reduced mechanical strength caused by the additional heat cycle.

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

A study on the high temperature-dependence of the electrical properties in a solution-deposited zinc-tin-oxide thin-film transistor operated in the saturation region

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Bae, Byung Seong; Jung, Myunghee; Yun, Eui-Jung

2016-06-01

We investigate the effects of high temperatures in the range of 292 - 393 K on the electrical properties of solution-processed amorphous zinc-tin-oxide (a-ZTO) thin-film transistors (TFTs) operated in the saturation region. The fabricated a-ZTO TFTs have a non-patterned bottom gate and top contact structure, and they use a heavily-doped Si wafer and SiO2 as a gate electrode and a gate insulator layer, respectively. In a-ZTO TFTs, the trap release energy ( E TR ) was deduced by using Maxwell-Boltzmann statistics. The decreasing E TR toward zero with increasing gate voltage (the density of trap states ( n s )) in the a-ZTO active layer can be attributed to a shift of the Fermi level toward the mobility edge with increasing gate voltage. The TFTs with low gate voltage (low n s ) exhibit multiple trap and release characteristics and show thermally-activated behavior. In TFTs with a high gate voltage (high n s ), however, we observe decreasing mobility and conductivity with increasing temperature at temperatures ranging from 303 to 363 K. This confirms that the E TR can drop to zero, indicating a shift of the Fermi level beyond the mobility edge. Hence, the mobility edge is detected at the cusp between thermally-activated transport and band transport.

Spontaneously formed high-performance charge-transport layers of organic single-crystal semiconductors on precisely synthesized insulating polymers

NASA Astrophysics Data System (ADS)

Makita, Tatsuyuki; Sasaki, Masayuki; Annaka, Tatsuro; Sasaki, Mari; Matsui, Hiroyuki; Mitsui, Chikahiko; Kumagai, Shohei; Watanabe, Shun; Hayakawa, Teruaki; Okamoto, Toshihiro; Takeya, Jun

2017-04-01

Charge-transporting semiconductor layers with high carrier mobility and low trap-density, desired for high-performance organic transistors, are spontaneously formed as a result of thermodynamic phase separation from a blend of π-conjugated small molecules and precisely synthesized insulating polymers dissolved in an aromatic solvent. A crystal film grows continuously to the size of centimeters, with the critical conditions of temperature, concentrations, and atmosphere. It turns out that the molecular weight of the insulating polymers plays an essential role in stable film growth and interfacial homogeneity at the phase separation boundary. Fabricating the transistor devices directly at the semiconductor-insulator boundaries, we demonstrate that the mixture of 3,11-didecyldinaphtho[2,3-d:2',3'-d']benzo[1,2-b:4,5-b']dithiophene and poly(methyl methacrylate) with the optimized weight-average molecular weight shows excellent device performances. The spontaneous phase separation with a one-step fabrication process leads to a high mobility up to 10 cm2 V-1 s-1 and a low subthreshold swing of 0.25 V dec-1 even without any surface treatment such as self-assembled monolayer modifications on oxide gate insulators.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

NASA Astrophysics Data System (ADS)

Chen, Ya-Yi; Liu, Yuan; Wu, Zhao-Hui; Wang, Li; Li, Bin; En, Yun-Fei; Chen, Yi-Qiang

2018-04-01

Not Available Supported by the National Natural Science Foundation of China under Grant No 61574048, the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2015B090901048, and the Pearl River S&T Nova Program of Guangzhou under Grant No 201710010172.

Quantum anomalous Hall Majorana platform

NASA Astrophysics Data System (ADS)

Zeng, Yongxin; Lei, Chao; Chaudhary, Gaurav; MacDonald, Allan H.

2018-02-01

We show that quasi-one-dimensional quantum wires can be written onto the surface of magnetic topological insulator (MTI) thin films by gate arrays. When the MTI is in a quantum anomalous Hall state, MTI/superconductor quantum wires have especially broad stability regions for both topological and nontopological states, facilitating creation and manipulation of Majorana particles on the MTI surface.

Magnetic quantum phase transition in Cr-doped Bi2(SexTe1-x)3 driven by the Stark effect

NASA Astrophysics Data System (ADS)

Zhang, Zuocheng; Feng, Xiao; Wang, Jing; Lian, Biao; Zhang, Jinsong; Chang, Cuizu; Guo, Minghua; Ou, Yunbo; Feng, Yang; Zhang, Shou-Cheng; He, Ke; Ma, Xucun; Xue, Qi-Kun; Wang, Yayu

2017-10-01

The recent experimental observation of the quantum anomalous Hall effect has cast significant attention on magnetic topological insulators. In these magnetic counterparts of conventional topological insulators such as Bi2Te3, a long-range ferromagnetic state can be established by chemical doping with transition-metal elements. However, a much richer electronic phase diagram can emerge and, in the specific case of Cr-doped Bi2(SexTe1-x)3, a magnetic quantum phase transition tuned by the actual chemical composition has been reported. From an application-oriented perspective, the relevance of these results hinges on the possibility to manipulate magnetism and electronic band topology by external perturbations such as an electric field generated by gate electrodes—similar to what has been achieved in conventional diluted magnetic semiconductors. Here, we investigate the magneto-transport properties of Cr-doped Bi2(SexTe1-x)3 with different compositions under the effect of a gate voltage. The electric field has a negligible effect on magnetic order for all investigated compositions, with the remarkable exception of the sample close to the topological quantum critical point, where the gate voltage reversibly drives a ferromagnetic-to-paramagnetic phase transition. Theoretical calculations show that a perpendicular electric field causes a shift in the electronic energy levels due to the Stark effect, which induces a topological quantum phase transition and, in turn, a magnetic phase transition.

Metal-to-insulator transition induced by UV illumination in a single SnO2 nanobelt

NASA Astrophysics Data System (ADS)

Viana, E. R.; Ribeiro, G. M.; de Oliveira, A. G.; González, J. C.

2017-11-01

An individual tin oxide (SnO2) nanobelt was connected in a back-gate field-effect transistor configuration and the conductivity of the nanobelt was measured at different temperatures from 400 K to 4 K, in darkness and under UV illumination. In darkness, the SnO2 nanobelts showed semiconductor behavior for the whole temperature range measured. However, when subjected to UV illumination the photoinduced carriers were high enough to lead to a metal-to-insulator transition (MIT), near room temperature, at T MIT = 240 K. By measuring the current versus gate voltage curves, and considering the electrostatic properties of a non-ideal conductor, for the SnO2 nanobelt on top of a gate-oxide substrate, we estimated the capacitance per unit length, the mobility and the density of carriers. In darkness, the density was estimated to be 5-10 × 1018 cm-3, in agreement with our previously reported result (Phys. Status Solid. RRL 6, 262-4 (2012)). However, under UV illumination the density of carriers was estimated to be 0.2-3.8 × 1019 cm-3 near T MIT, which exceeded the critical Mott density estimated to be 2.8 × 1019 cm-3 above 240 K. These results showed that the electrical properties of the SnO2 nanobelts can be drastically modified and easily tuned from semiconducting to metallic states as a function of temperature and light.

CNOT sequences for heterogeneous spin qubit architectures in a noisy environment

NASA Astrophysics Data System (ADS)

Ferraro, Elena; Fanciulli, Marco; de Michielis, Marco

Explicit CNOT gate sequences for two-qubits mixed architectures are presented in view of applications for large-scale quantum computation. Different kinds of coded spin qubits are combined allowing indeed the favorable physical properties of each to be employed. The building blocks for such composite systems are qubit architectures based on the electronic spin in electrostatically defined semiconductor quantum dots. They are the single quantum dot spin qubit, the double quantum dot singlet-triplet qubit and the double quantum dot hybrid qubit. The effective Hamiltonian models expressed by only exchange interactions between pair of electrons are exploited in different geometrical configurations. A numerical genetic algorithm that takes into account the realistic physical parameters involved is adopted. Gate operations are addressed by modulating the tunneling barriers and the energy offsets between different couple of quantum dots. Gate infidelities are calculated considering limitations due to unideal control of gate sequence pulses, hyperfine interaction and unwanted charge coupling. Second affiliation: Dipartimento di Scienza dei Materiali, University of Milano Bicocca, Via R. Cozzi, 55, 20126 Milano, Italy.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Flat-lying semiconductor-insulator interfacial layer in DNTT thin films.

PubMed

Jung, Min-Cherl; Leyden, Matthew R; Nikiforov, Gueorgui O; Lee, Michael V; Lee, Han-Koo; Shin, Tae Joo; Takimiya, Kazuo; Qi, Yabing

2015-01-28

The molecular order of organic semiconductors at the gate dielectric is the most critical factor determining carrier mobility in thin film transistors since the conducting channel forms at the dielectric interface. Despite its fundamental importance, this semiconductor-insulator interface is not well understood, primarily because it is buried within the device. We fabricated dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) thin film transistors by thermal evaporation in vacuum onto substrates held at different temperatures and systematically correlated the extracted charge mobility to the crystal grain size and crystal orientation. As a result, we identify a molecular layer of flat-lying DNTT molecules at the semiconductor-insulator interface. It is likely that such a layer might form in other material systems as well, and could be one of the factors reducing charge transport. Controlling this interfacial flat-lying layer may raise the ultimate possible device performance for thin film devices.

Interface engineering of quantum Hall effects in digital transition metal oxide heterostructures.

PubMed

Xiao, Di; Zhu, Wenguang; Ran, Ying; Nagaosa, Naoto; Okamoto, Satoshi

2011-12-20

Topological insulators are characterized by a non-trivial band topology driven by the spin-orbit coupling. To fully explore the fundamental science and application of topological insulators, material realization is indispensable. Here we predict, based on tight-binding modelling and first-principles calculations, that bilayers of perovskite-type transition-metal oxides grown along the [111] crystallographic axis are potential candidates for two-dimensional topological insulators. The topological band structure of these materials can be fine-tuned by changing dopant ions, substrates and external gate voltages. We predict that LaAuO(3) bilayers have a topologically non-trivial energy gap of about 0.15 eV, which is sufficiently large to realize the quantum spin Hall effect at room temperature. Intriguing phenomena, such as fractional quantum Hall effect, associated with the nearly flat topologically non-trivial bands found in e(g) systems are also discussed.

Double-wall tubing for oil recovery

NASA Technical Reports Server (NTRS)

Back, L. H.; Carroll, W. F.; Jaffee, L. D.; Stimpson, L. D.

1980-01-01

Insulated double-wall tubing designed for steam injection oil recovery makes process more economical and allows deeper extension of wells. Higher quality wet steam is delivered through tubing to oil deposits with significant reductions in heat loss to surrounding rock allowing greater exploitation of previously unworkable reservoirs.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Study of noise reduction characteristics of double-wall panels

NASA Technical Reports Server (NTRS)

Navaneethan, R.; Quayle, B.; Stevenson, S.; Graham, M.

1983-01-01

The noise reduction characteristics of general aviation type, flat, double-wall structures were investigated. The experimental study was carried out on 20-by-20 inch panels with an exposed area of 18 by 18 inches. A frequency range from 20 to 5000 Hz was covered. The experimental results, in general, follow the expected trends. At low frequencies the double-wall structures are no better than the single-wall structures. However, for depths normally used in the general aviation industry, the double-wall panels are very attractive. The graphite-spoxy skin panels have higher noise reduction at very low frequencies ( 100 Hz) than the Kevlar skin panels. But the aluminum panels have higher noise reduction in the high frequency region, due to their greater mass. Use of fiberglass insulation is not effective in the low frequency region, and at times it is even negative. But the insulation is effective in the high-frequency region. The theoretical model for predicting the transmission loss of these multilayered panels is also discussed.

Study of noise reduction characteristics of double-wall panels

NASA Astrophysics Data System (ADS)

Navaneethan, R.; Quayle, B.; Stevenson, S.; Graham, M.

1983-05-01

The noise reduction characteristics of general aviation type, flat, double-wall structures were investigated. The experimental study was carried out on 20-by-20 inch panels with an exposed area of 18 by 18 inches. A frequency range from 20 to 5000 Hz was covered. The experimental results, in general, follow the expected trends. At low frequencies the double-wall structures are no better than the single-wall structures. However, for depths normally used in the general aviation industry, the double-wall panels are very attractive. The graphite-spoxy skin panels have higher noise reduction at very low frequencies ( 100 Hz) than the Kevlar skin panels. But the aluminum panels have higher noise reduction in the high frequency region, due to their greater mass. Use of fiberglass insulation is not effective in the low frequency region, and at times it is even negative. But the insulation is effective in the high-frequency region. The theoretical model for predicting the transmission loss of these multilayered panels is also discussed.

Rodney Hunt supplies gates to Idaho Power's Swan Falls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

1993-02-01

Rodney Hunt Co. shipped two 30-foot by 28-foot fabricated steel roller gates to Idaho Power Co.'s Swan Falls Dam Project, where they will be installed as draft tube gates. Rodney Hunt said the gates, each weighing approximately 55 tons, are the largest roller gates the company has manufactured. The company supplied the gates under the terms of a contract worth more than $500,000. The gates were ordered as part of Idaho Power's rehabilitation of Swan Falls Dam, which will double the power plant's capacity to 25 MW. New units will begin producing power in 1993, and the project will bemore » completed in 1994. Elsewhere on the Snake River, Idaho Power intends to increase the capacity of its Twin Falls project to 52 MW from 10 MW. Construction is scheduled to start in June 1993.« less

Plasmid-derived DNA Strand Displacement Gates for Implementing Chemical Reaction Networks.

PubMed

Chen, Yuan-Jyue; Rao, Sundipta D; Seelig, Georg

2015-11-25

DNA nanotechnology requires large amounts of highly pure DNA as an engineering material. Plasmid DNA could meet this need since it is replicated with high fidelity, is readily amplified through bacterial culture and can be stored indefinitely in the form of bacterial glycerol stocks. However, the double-stranded nature of plasmid DNA has so far hindered its efficient use for construction of DNA nanostructures or devices that typically contain single-stranded or branched domains. In recent work, it was found that nicked double stranded DNA (ndsDNA) strand displacement gates could be sourced from plasmid DNA. The following is a protocol that details how these ndsDNA gates can be efficiently encoded in plasmids and can be derived from the plasmids through a small number of enzymatic processing steps. Also given is a protocol for testing ndsDNA gates using fluorescence kinetics measurements. NdsDNA gates can be used to implement arbitrary chemical reaction networks (CRNs) and thus provide a pathway towards the use of the CRN formalism as a prescriptive molecular programming language. To demonstrate this technology, a multi-step reaction cascade with catalytic kinetics is constructed. Further it is shown that plasmid-derived components perform better than identical components assembled from synthetic DNA.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Edge states in gated bilayer-monolayer graphene ribbons and bilayer domain walls

NASA Astrophysics Data System (ADS)

Mirzakhani, M.; Zarenia, M.; Peeters, F. M.

2018-05-01

Using the effective continuum model, the electron energy spectrum of gated bilayer graphene with a step-like region of decoupled graphene layers at the edge of the sample is studied. Different types of coupled-decoupled interfaces are considered, i.e., zigzag (ZZ) and armchair junctions, which result in significant different propagating states. Two non-valley-polarized conducting edge states are observed for ZZ type, which are mainly located around the ZZ-ended graphene layers. Additionally, we investigated both BA-BA and BA-AB domain walls in the gated bilayer graphene within the continuum approximation. Unlike the BA-BA domain wall, which exhibits gapped insulating behaviour, the domain walls surrounded by different stackings of bilayer regions feature valley-polarized edge states. Our findings are consistent with other theoretical calculations, such as from the tight-binding model and first-principles calculations, and agree with experimental observations.

Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage

NASA Astrophysics Data System (ADS)

Namai, Masaki; An, Junjie; Yano, Hiroshi; Iwamuro, Noriyuki

2018-07-01

In this study, the experimental evaluation and numerical analysis of short-circuit mechanisms of 1200 V SiC planar and trench MOSFETs were conducted at various DC bus voltages from 400 to 800 V. Investigation of the impact of DC bus voltage on short-circuit capability yielded results that are extremely useful for many existing power electronics applications. Three failure mechanisms were identified in this study: thermal runaway, MOS channel current following device turn-off, and rupture of the gate oxide layer (gate oxide layer damage). The SiC MOSFETs experienced lattice temperatures exceeding 1000 K during the short-circuit transient; as Si insulated gate bipolar transistors (IGBTs) are not typically subject to such temperatures, the MOSFETs experienced distinct failure modes, and the mode experienced was significantly influenced by the DC bus voltage. In conclusion, suggestions regarding the SiC MOSFET design and operation methods that would enhance device robustness are proposed.

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics

PubMed Central

2017-01-01

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport. PMID:28084725

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

PubMed

Egard, M; Johansson, S; Johansson, A-C; Persson, K-M; Dey, A W; Borg, B M; Thelander, C; Wernersson, L-E; Lind, E

2010-03-10

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

A double tyrosine motif in the cardiac sodium channel domain III-IV linker couples calcium-dependent calmodulin binding to inactivation gating.

PubMed

Sarhan, Maen F; Van Petegem, Filip; Ahern, Christopher A

2009-11-27

Voltage-gated sodium channels maintain the electrical cadence and stability of neurons and muscle cells by selectively controlling the transmembrane passage of their namesake ion. The degree to which these channels contribute to cellular excitability can be managed therapeutically or fine-tuned by endogenous ligands. Intracellular calcium, for instance, modulates sodium channel inactivation, the process by which sodium conductance is negatively regulated. We explored the molecular basis for this effect by investigating the interaction between the ubiquitous calcium binding protein calmodulin (CaM) and the putative sodium channel inactivation gate composed of the cytosolic linker between homologous channel domains III and IV (DIII-IV). Experiments using isothermal titration calorimetry show that CaM binds to a novel double tyrosine motif in the center of the DIII-IV linker in a calcium-dependent manner, N-terminal to a region previously reported to be a CaM binding site. An alanine scan of aromatic residues in recombinant DIII-DIV linker peptides shows that whereas multiple side chains contribute to CaM binding, two tyrosines (Tyr(1494) and Tyr(1495)) play a crucial role in binding the CaM C-lobe. The functional relevance of these observations was then ascertained through electrophysiological measurement of sodium channel inactivation gating in the presence and absence of calcium. Experiments on patch-clamped transfected tsA201 cells show that only the Y1494A mutation of the five sites tested renders sodium channel steady-state inactivation insensitive to cytosolic calcium. The results demonstrate that calcium-dependent calmodulin binding to the sodium channel inactivation gate double tyrosine motif is required for calcium regulation of the cardiac sodium channel.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Abstract probabilistic CNOT gate model based on double encoding: study of the errors and physical realizability

NASA Astrophysics Data System (ADS)

Gueddana, Amor; Attia, Moez; Chatta, Rihab

2015-03-01

In this work, we study the error sources standing behind the non-perfect linear optical quantum components composing a non-deterministic quantum CNOT gate model, which performs the CNOT function with a success probability of 4/27 and uses a double encoding technique to represent photonic qubits at the control and the target. We generalize this model to an abstract probabilistic CNOT version and determine the realizability limits depending on a realistic range of the errors. Finally, we discuss physical constraints allowing the implementation of the Asymmetric Partially Polarizing Beam Splitter (APPBS), which is at the heart of correctly realizing the CNOT function.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Gates Fund Creates Plan for College Completion

ERIC Educational Resources Information Center

Gose, Ben

2008-01-01

The Bill & Melinda Gates Foundation plans to spend several hundred million dollars over the next five years to double the number of low-income young people who complete a college degree or certificate program by age 26. Foundation officials described the ambitious plan to an exclusive group of education leaders, citing 2025 as a target goal. If…

All-optical switching in silicon-on-insulator photonic wire nano-cavities.

PubMed

Belotti, Michele; Galli, Matteo; Gerace, Dario; Andreani, Lucio Claudio; Guizzetti, Giorgio; Md Zain, Ahmad R; Johnson, Nigel P; Sorel, Marc; De La Rue, Richard M

2010-01-18

We report on experimental demonstration of all-optical switching in a silicon-on-insulator photonic wire nanocavity operating at telecom wavelengths. The switching is performed with a control pulse energy as low as approximately 0.1 pJ on a cavity device that presents very high signal transmission, an ultra-high quality-factor, almost diffraction-limited modal volume and a footprint of only 5 microm(2). High-speed modulation of the cavity mode is achieved by means of optical injection of free carriers using a nanosecond pulsed laser. Experimental results are interpreted by means of finite-difference time-domain simulations. The possibility of using this device as a logic gate is also demonstrated.

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

NASA Astrophysics Data System (ADS)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Temperature dependence of DC transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure

NASA Astrophysics Data System (ADS)

Chou, Kuan-Yu; Hsu, Nai-Wen; Su, Yi-Hsin; Chou, Chung-Tao; Chiu, Po-Yuan; Chuang, Yen; Li, Jiun-Yun

2018-02-01

We investigate DC characteristics of a two-dimensional electron gas (2DEG) in an undoped Si/SiGe heterostructure and its temperature dependence. An insulated-gate field-effect transistor was fabricated, and transfer characteristics were measured at 4 K-300 K. At low temperatures (T < 45 K), source electrons are injected into the buried 2DEG channel first and drain current increases with the gate voltage. By increasing the gate voltage further, the current saturates followed by a negative transconductance observed, which can be attributed to electron tunneling from the buried channel to the surface channel. Finally, the drain current is saturated again at large gate biases due to parallel conduction of buried and surface channels. By increasing the temperature, an abrupt increase in threshold voltage is observed at T ˜ 45 K and it is speculated that negatively charged impurities at the Al2O3/Si interface are responsible for the threshold voltage shift. At T > 45 K, the current saturation and negative transconductance disappear and the device acts as a normal transistor.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

NASA Astrophysics Data System (ADS)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Electron mobility in the inversion layers of fully depleted SOI films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I.

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished.more » The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.« less

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

Nuclear Plant Siting Study. Volume 2

DTIC Science & Technology

1976-06-01

210 feet apart with sliding type supports every 35 feet. See Figure 3-6 for support details. A double wrapping of mineral wool insulation with...3,000 Mhr 11.80 35,400 (M 3,500 12", XS, .375 Wall - Conduit 20" (M 1,000 LF 105 105,000 (L 3,700 Mhr 11.80 43,700 (M 4,300 Insulation Mineral Wool 3

First results from GaAs double-sided detectors

NASA Astrophysics Data System (ADS)

Beaumont, S. P.; Bertin, R.; Booth, C. N.; Buttar, C.; Carraresi, L.; Cindolo, F.; Colocci, M.; Combley, F. H.; D'Auria, S.; del Papa, C.; Dogru, M.; Edwards, M.; Foster, F.; Francescato, A.; Gowdy, S.; Gray, R.; Hill, G.; Hou, Y.; Houston, P.; Hughes, G.; Jones, B. K.; Lynch, J. G.; Lisowski, B.; Matheson, J.; Nava, F.; Nuti, M.; O'Shea, V.; Pelfer, P. G.; Raine, C.; Santana, J.; Saunders, I. J.; Seller, P. H.; Shankar, K.; Sharp, P. H.; Skillicorn, I. O.; Sloan, T.; Smith, K. M.; ten Have, I.; Turnbull, R. M.; Vanni, U.; Zichichi, A.

1994-09-01

Preliminary results are presented on the performance of double-sided microstrip detectors using Schottky contacts on both sides of a semi-insulating (SI) GaAs substrate wafer, after exposure to 10 14 neutrons cm -2 at the ISIS facility. A qualitative explanation of the device behaviour is given.

Enhanced photovoltage on the surface of topological insulator via optical aging

NASA Astrophysics Data System (ADS)

Yoshikawa, Tomoki; Ishida, Yukiaki; Sumida, Kazuki; Chen, Jiahua; Kokh, Konstantin A.; Tereshchenko, Oleg E.; Shin, Shik; Kimura, Akio

2018-05-01

The efficient generation of spin-polarized current is one of the keys to realizing spintronic devices with a low power consumption. Topological insulators are strong candidates for this purpose. A surface photovoltaic effect can be utilized on the surface of a topological insulator, where a surface spin-polarized current can flow upon illumination. Here, we used time- and angle-resolved photoelectron spectroscopy on the surface of Bi2Te3 to demonstrate that the magnitude of the surface photovoltage is almost doubled in optically aged samples, i.e., samples whose surface has been exposed to intense infrared light illumination. Our findings pave the way for optical control of the spin-polarized current by utilizing topological insulators.

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

NASA Astrophysics Data System (ADS)

Tang, Zhaohuan; Fu, Xinghua; Yang, Fashun; Tan, Kaizhou; Ma, Kui; Wu, Xue; Lin, Jiexing

2017-12-01

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture (SEGR) and single event burnout (SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers. Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs. Project supported by the National Natural Science Foundation of China (No. 61464002), the Grand Science and Technology Special Project in Guizhou Province of China (No. [2015]6006), and the Ministry of Education Open Foundation for Semiconductor Power Device Reliability (No. 010201).

Interface engineering and solid-state organization for triindole-based p-type organic thin-film transistors.

PubMed

Reig, Marta; Bagdziunas, Gintautas; Ramanavicius, Arunas; Puigdollers, Joaquim; Velasco, Dolores

2018-06-21

Inspired by the excellent device performance of triindole-based semiconductors in electronic and optoelectronic devices, the relationship between the solid-state organization and the charge-transporting properties of an easily accessible series of triindole derivatives is reported herein. The vacuum-evaporated organic thin-film transistors (OTFTs) exhibited a non ideal behaviour with a double slope in the saturation curves. Moreover, the treatment of the gate insulator of the OTFT device with either a self-assembled monolayer (SAM) or a polymer controls the molecular growth and the film morphology of the semiconducting layer, as shown by X-ray diffraction (XRD) analyses, atomic force microscopy (AFM) and theoretical calculations. N-Trihexyltriindole exhibited the best device performance with hole mobilities up to 0.1 cm2 V-1 s-1 at the low VG range and up to 0.01 cm2 V-1 s-1 at high VG, as well as enhanced Ion/Ioff ratios of around 106. The results suggest that the non-ideal behaviour of the here studied OTFT devices could be related to the higher interfacial disorder in comparison to that in the bulk.

Transparent conducting oxide induced by liquid electrolyte gating

NASA Astrophysics Data System (ADS)

ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

2016-10-01

Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ˜1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Disorder from the Bulk Ionic Liquid in Electric Double Layer Transistors

DOE PAGES

Petach, Trevor A.; Reich, Konstantin V.; Zhang, Xiao; ...

2017-07-28

Ionic liquid gating has a number of advantages over solid-state gating, especially for flexible or transparent devices and for applications requiring high carrier densities. But, the large number of charged ions near the channel inevitably results in Coulomb scattering, which limits the carrier mobility in otherwise clean systems. We develop a model for this Coulomb scattering. We then validate our model experimentally using ionic liquid gating of graphene across varying thicknesses of hexagonal boron nitride, demonstrating that disorder in the bulk ionic liquid often dominates the scattering.

Enhanced ferromagnetism, metal-insulator transition, and large magnetoresistance in La1-xCaxMn1-xRuxO3 free of eg-orbital double-exchange

NASA Astrophysics Data System (ADS)

Liu, M. F.; Du, Z. Z.; Liu, H. M.; Li, X.; Yan, Z. B.; Dong, S.; Liu, J.-M.

2014-03-01

The structure, ionic valences, magnetism, and magneto-transport behaviors of mixed valence oxides La1-xCaxMn1-xRuxO3 are systematically investigated. The simultaneous substitutions of La3+ and Mn3+ ions by Ca2+ and Ru4+, respectively, are confirmed by the structural and ionic valence characterizations, excluding the presence of Mn4+ and Ru3+ ions. The enhanced ferromagnetism, induced metal-insulator transition, and remarkable magnetoresistance effect are demonstrated when the substitution level x is lower than ˜0.6, in spite of the absence of the Mn3+-Ru4+ eg-orbital double-exchange. These anomalous magnetotransport effects are discussed based on the competing multifold interactions associated with the Mn3+-Ru4+ super-exchange and strong Ru4+-Ru4+ hopping, while the origins for the metal-insulator transition and magnetoresistance effect remain to be clarified.

Nanoscale control of an interfacial metal-insulator transition at room temperature.

PubMed

Cen, C; Thiel, S; Hammerl, G; Schneider, C W; Andersen, K E; Hellberg, C S; Mannhart, J; Levy, J

2008-04-01

Experimental and theoretical investigations have demonstrated that a quasi-two-dimensional electron gas (q-2DEG) can form at the interface between two insulators: non-polar SrTiO3 and polar LaTiO3 (ref. 2), LaAlO3 (refs 3-5), KTaO3 (ref. 7) or LaVO3 (ref. 6). Electronically, the situation is analogous to the q-2DEGs formed in semiconductor heterostructures by modulation doping. LaAlO3/SrTiO3 heterostructures have recently been shown to exhibit a hysteretic electric-field-induced metal-insulator quantum phase transition for LaAlO3 thicknesses of 3 unit cells. Here, we report the creation and erasure of nanoscale conducting regions at the interface between two insulating oxides, LaAlO3 and SrTiO3. Using voltages applied by a conducting atomic force microscope (AFM) probe, the buried LaAlO3/SrTiO3 interface is locally and reversibly switched between insulating and conducting states. Persistent field effects are observed using the AFM probe as a gate. Patterning of conducting lines with widths of approximately 3 nm, as well as arrays of conducting islands with densities >10(14) inch(-2), is demonstrated. The patterned structures are stable for >24 h at room temperature.

Tailoring Materials for Mottronics: Excess Oxygen Doping of a Prototypical Mott Insulator.

PubMed

Scheiderer, Philipp; Schmitt, Matthias; Gabel, Judith; Zapf, Michael; Stübinger, Martin; Schütz, Philipp; Dudy, Lenart; Schlueter, Christoph; Lee, Tien-Lin; Sing, Michael; Claessen, Ralph

2018-05-07

The Mott transistor is a paradigm for a new class of electronic devices-often referred to by the term Mottronics-which are based on charge correlations between the electrons. Since correlation-induced insulating phases of most oxide compounds are usually very robust, new methods have to be developed to push such materials right to the boundary to the metallic phase in order to enable the metal-insulator transition to be switched by electric gating. Here, it is demonstrated that thin films of the prototypical Mott insulator LaTiO 3 grown by pulsed laser deposition under oxygen atmosphere are readily tuned by excess oxygen doping across the line of the band-filling controlled Mott transition in the electronic phase diagram. The detected insulator to metal transition is characterized by a strong change in resistivity of several orders of magnitude. The use of suitable substrates and capping layers to inhibit oxygen diffusion facilitates full control of the oxygen content and renders the films stable against exposure to ambient conditions. These achievements represent a significant advancement in control and tuning of the electronic properties of LaTiO 3+ x thin films making it a promising channel material in future Mottronic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Super-resolution depth information from a short-wave infrared laser gated-viewing system by using correlated double sampling

NASA Astrophysics Data System (ADS)

Göhler, Benjamin; Lutzmann, Peter

2017-10-01

Primarily, a laser gated-viewing (GV) system provides range-gated 2D images without any range resolution within the range gate. By combining two GV images with slightly different gate positions, 3D information within a part of the range gate can be obtained. The depth resolution is higher (super-resolution) than the minimal gate shift step size in a tomographic sequence of the scene. For a state-of-the-art system with a typical frame rate of 20 Hz, the time difference between the two required GV images is 50 ms which may be too long in a dynamic scenario with moving objects. Therefore, we have applied this approach to the reset and signal level images of a new short-wave infrared (SWIR) GV camera whose read-out integrated circuit supports correlated double sampling (CDS) actually intended for the reduction of kTC noise (reset noise). These images are extracted from only one single laser pulse with a marginal time difference in between. The SWIR GV camera consists of 640 x 512 avalanche photodiodes based on mercury cadmium telluride with a pixel pitch of 15 μm. A Q-switched, flash lamp pumped solid-state laser with 1.57 μm wavelength (OPO), 52 mJ pulse energy after beam shaping, 7 ns pulse length and 20 Hz pulse repetition frequency is used for flash illumination. In this paper, the experimental set-up is described and the operating principle of CDS is explained. The method of deriving super-resolution depth information from a GV system by using CDS is introduced and optimized. Further, the range accuracy is estimated from measured image data.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

NASA Astrophysics Data System (ADS)

Shin, Yong Hyeon; Bae, Min Soo; Park, Chuntaek; Park, Joung Won; Park, Hyunwoo; Lee, Yong Ju; Yun, Ilgu

2018-06-01

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Q inv ) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Highly flexible SRAM cells based on novel tri-independent-gate FinFET

NASA Astrophysics Data System (ADS)

Liu, Chengsheng; Zheng, Fanglin; Sun, Yabin; Li, Xiaojin; Shi, Yanling

2017-10-01

In this paper, a novel tri-independent-gate (TIG) FinFET is proposed for highly flexible SRAM cells design. To mitigate the read-write conflict, two kinds of SRAM cells based on TIG FinFETs are designed, and high tradeoff are obtained between read stability and speed. Both cells can offer multi read operations for frequency requirement with single voltage supply. In the first TIG FinFET SRAM cell, the strength of single-fin access transistor (TIG FinFET) can be flexibly adjusted by selecting five different modes to meet the needs of dynamic frequency design. Compared to the previous double-independent-gate (DIG) FinFET SRAM cell, 12.16% shorter read delay can be achieved with only 1.62% read stability decrement. As for the second TIG FinFET SRAM cell, pass-gate feedback technology is applied and double-fin TIG FinFETs are used as access transistors to solve the severe write-ability degradation. Three modes exist to flexibly adjust read speed and stability, and 68.2% larger write margin and 51.7% shorter write delay are achieved at only the expense of 26.2% increase in leakage power, with the same layout area as conventional FinFET SRAM cell.

Single attosecond pulse generation by using plasmon-driven double optical gating technology in crossed metal nanostructures

NASA Astrophysics Data System (ADS)

Feng, Liqiang; Liu, Katheryn

2018-05-01

An effective method to obtain the single attosecond pulses (SAPs) by using the multi-cycle plasmon-driven double optical gating (DOG) technology in the specifically designed metal nanostructures has been proposed and investigated. It is found that with the introduction of the crossed metal nanostructures along the driven and the gating polarization directions, not only the harmonic cutoff can be extended, but also the efficient high-order harmonic generation (HHG) at the very highest orders occurs only at one side of the region inside the nanostructure. As a result, a 93 eV supercontinuum with the near stable phase can be found. Further, by properly introducing an ultraviolet (UV) pulse into the driven laser polarization direction (which is defined as the DOG), the harmonic yield can be enhanced by two orders of magnitude in comparison with the singe polarization gating (PG) technology. However, as the polarized angle or the ellipticity of the UV pulse increase, the enhancement of the harmonic yield is slightly reduced. Finally, by superposing the selected harmonics from the DOG scheme, a 30 as SAP with intensity enhancement of two orders of magnitude can be obtained.

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Low-temperature electron cyclotron resonance plasma-enhanced chemical-vapor deposition silicon dioxide as gate insulator for polycrystalline silicon thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maiolo, L.; Pecora, A.; Fortunato, G.

2006-03-15

Silicon dioxide films have been deposited at temperatures below 270 deg. C in an electron cyclotron resonance (ECR) plasma reactor from O{sub 2}, SiH{sub 4}, and He gas mixture. Pinhole density analysis as a function of substrate temperature for different microwave powers was carried out. Films deposited at higher microwave power and at room temperature show defect densities (<7 pinhole/mm{sup 2}), ensuring low-temperature process integration on large area. From Fourier transform infrared analysis and thermal desorption spectrometry we also evaluated very low hydrogen content if compared to conventional rf-plasma-enhanced chemical-vapor-deposited (PECVD) SiO{sub 2} deposited at 350 deg. C. Electrical propertiesmore » have been measured in metal-oxide-semiconductor (MOS) capacitors, depositing SiO{sub 2} at RT as gate dielectric; breakdown electric fields >10 MV/cm and charge trapping at fields >6 MV/cm have been evaluated. From the study of interface quality in MOS capacitors, we found that even for low annealing temperature (200 deg. C), it is possible to considerably reduce the interface state density down to 5x10{sup 11} cm{sup -2} eV{sup -1}. To fully validate the ECR-PECVD silicon dioxide we fabricated polycrystalline silicon thin-film transistors using RT-deposited SiO{sub 2} as gate insulator. Different postdeposition thermal treatments have been studied and good device characteristics were obtained even for annealing temperature as low as 200 deg. C.« less

A Test Fixture for Simulating Human Limb Physiology and Soft Tissue Biomechanics

DTIC Science & Technology

1989-04-14

Food and Drug Administration (FDA) has not promu!gated performance standards for vital signs monitors that determine blood pressure and heart rate...static char answer[] = "" double f~ttnun~pts, single, doubleit, triple; int single_ -leftover, doubleit I eftover , triple-Leftover; double sin

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

Electron-Phonon and Electron-Electron Interactions in Individual Suspended Carbon Nanotubes

NASA Astrophysics Data System (ADS)

Cronin, Stephen

2010-03-01

The fabrication of pristine, nearly defect-free, suspended carbon nanotubes (CNTs) enables the observation of several phenomena not seen before in carbon nanotubes, including breakdown of the Born-Oppenheimer approximation^1, mode selective electron-phonon coupling^2, and a Mott insulator transition^3. Raman spectroscopy of these nanotubes under applied gate and bias potentials reveals exceptionally strong electron-phonon coupling, arising from Kohn anomalies, which result in mode selective electron-phonon coupling, negative differential conductance (NDC), and non-equilibrium phonon populations^2,4. Due to the extremely long electron lifetimes, we observe a breakdown of the Born-Oppenheimer approximation, as deduced from the gate voltage-induced changes in the vibrational energies of suspended carbon nanotubes^1. We also report strikingly large variations in the Raman intensity of pristine metallic CNTs in response to gate voltages, which are attributed to a Mott insulating state of the strongly correlated electrons^3. As will be shown, preparing clean, defect-free devices is an essential prerequisite for studying the rich low-dimensional physics of CNTs. (1.) Bushmaker, A.W., Deshpande, V.V., Hsieh, S., Bockrath, M.W., and Cronin, S.B., ``Direct Observation of Born-Oppenheimer Approximation Breakdown in Carbon Nanotubes.'' Nano Letters, 9, 607 (2009). (2.) Bushmaker, A.W., Deshpande, V.V., Bockrath, M.W., and Cronin, S.B., ``Direct Observation of Mode Selective Electron-Phonon Coupling in Suspended Carbon Nanotubes.'' Nano Letters, 7, 3618 (2007) (3.) Bushmaker, A.W., Deshpande, V.V., Hsieh, S., Bockrath, M.W., and Cronin, S.B., ``Large Modulations in the Intensity of Raman-Scattered Light from Pristine Carbon Nanotubes.'' Physical Review Letters, 103, 067401 (2009). (4.) Bushmaker, A.W., Deshpande, V.V., Hsieh, S., Bockrath, M.W., and Cronin, S.B., ``Gate Voltage Controlled Non-Equilibrium and Non-Ohmic Behavior in Suspended Carbon Nanotubes.'' Nano Letters, 9, 2862 (2009)

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Enhanced two dimensional electron gas transport characteristics in Al2O3/AlInN/GaN metal-oxide-semiconductor high-electron-mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Freedsman, J. J.; Watanabe, A.; Urayama, Y.; Egawa, T.

2015-09-01

The authors report on Al2O3/Al0.85In0.15N/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor (MOS-HEMT) on Si fabricated by using atomic layer deposited Al2O3 as gate insulator and passivation layer. The MOS-HEMT with the gate length of 2 μm exhibits excellent direct-current (dc) characteristics with a drain current maximum of 1270 mA/mm at a gate bias of 3 V and an off-state breakdown voltage of 180 V for a gate-drain spacing of 4 μm. Also, the 1 μm-gate MOS-HEMT shows good radio-frequency (rf) response such as current gain and maximum oscillation cut-off frequencies of 10 and 34 GHz, respectively. The capacitance-voltage characteristics at 1 MHz revealed significant increase in two-dimensional electron gas (2DEG) density for the MOS-HEMT compared to conventional Schottky barrier HEMTs. Analyses using drain-source conductivity measurements showed improvements in 2DEG transport characteristics for the MOS-HEMT. The enhancements in dc and rf performances of the Al2O3/Al0.85In0.15N/GaN MOS-HEMT are attributed to the improvements in 2DEG characteristics.

Probing spin helical surface states in topological HgTe nanowires

NASA Astrophysics Data System (ADS)

Ziegler, J.; Kozlovsky, R.; Gorini, C.; Liu, M.-H.; Weishäupl, S.; Maier, H.; Fischer, R.; Kozlov, D. A.; Kvon, Z. D.; Mikhailov, N.; Dvoretsky, S. A.; Richter, K.; Weiss, D.

2018-01-01

Nanowires with helical surface states represent key prerequisites for observing and exploiting phase-coherent topological conductance phenomena, such as spin-momentum locked quantum transport or topological superconductivity. We demonstrate in a joint experimental and theoretical study that gated nanowires fabricated from high-mobility strained HgTe, known as a bulk topological insulator, indeed preserve the topological nature of the surface states, that moreover extend phase-coherently across the entire wire geometry. The phase-coherence lengths are enhanced up to 5 μ m when tuning the wires into the bulk gap, so as to single out topological transport. The nanowires exhibit distinct conductance oscillations, both as a function of the flux due to an axial magnetic field and of a gate voltage. The observed h /e -periodic Aharonov-Bohm-type modulations indicate surface-mediated quasiballistic transport. Furthermore, an in-depth analysis of the scaling of the observed gate-dependent conductance oscillations reveals the topological nature of these surface states. To this end we combined numerical tight-binding calculations of the quantum magnetoconductance with simulations of the electrostatics, accounting for the gate-induced inhomogeneous charge carrier densities around the wires. We find that helical transport prevails even for strongly inhomogeneous gating and is governed by flux-sensitive high-angular momentum surface states that extend around the entire wire circumference.

Multi-bit dark state memory: Double quantum dot as an electronic quantum memory

NASA Astrophysics Data System (ADS)

Aharon, Eran; Pozner, Roni; Lifshitz, Efrat; Peskin, Uri

2016-12-01

Quantum dot clusters enable the creation of dark states which preserve electrons or holes in a coherent superposition of dot states for a long time. Various quantum logic devices can be envisioned to arise from the possibility of storing such trapped particles for future release on demand. In this work, we consider a double quantum dot memory device, which enables the preservation of a coherent state to be released as multiple classical bits. Our unique device architecture uses an external gating for storing (writing) the coherent state and for retrieving (reading) the classical bits, in addition to exploiting an internal gating effect for the preservation of the coherent state.

Development of the Field-Induced Electron Injection and Impact Ionization (F4I) Technique for Radiation Hardness Testing of MOS (Metal-Oxide-Semiconductor) Gate Insulators.

DTIC Science & Technology

1988-03-01

Applesoft language, a variant of floating-point BASIC that is supplied with the computer. As an intepreted language, Apple- soft BASIC executes fairly...fit with (VI , II ) array. I 8400 Sound bell and display warning when current limit exceeded. 8500-8510 Output HV pulse, read and display amplitude

A 10 kW dc-dc converter using IGBTs with active snubbers. [Insulated Gate Bipolar Transistor

NASA Technical Reports Server (NTRS)

Masserant, Brian J.; Shriver, Jeffrey L.; Stuart, Thomas A.

1993-01-01

This full bridge dc-dc converter employs zero voltage switching (ZVS) on one leg and zero current switching (ZCS) on the other. This technique produces exceptionally low IGBT switching losses through the use of an active snubber that recycles energy back to the source. Experimental results are presented for a 10 kW, 20 kHz converter.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

The Use of Ferroelectrics and Dipeptides as Insulators in Organic Field-Effect Transistor Devices

NASA Astrophysics Data System (ADS)

Knotts, Grant

While the electrical transport characteristics of organic electronic devices are generally inferior to their inorganic counterparts, organic materials offer many advantages over inorganics. The materials used in organic devices can often be deposited using cheap and simple processing techniques such as spincoating, inkjet printing, or roll-to-roll processing; allow for large-scale, flexible devices; and can have the added benefits of being transparent or biodegradable. In this manuscript, we examine the role of solvents in the performance of pentacene-based devices using the ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (PVDF-TrFe) as a gate insulating layer. High dipole moment solvents, such as dimethyl sulfoxide, used to dissolve the copolymer for spincoating increase the charge carrier mobility in field-effect transistors (FETs) by nearly an order of magnitude as compared to lower dipole moment solvents. The polarization in Al/PVDF-TrFe/Au metal-ferroelectric-metal devices also shows an increase in remnant polarization of 20% in the sample using dimethyl sulfoxide as the solvent for the ferroelectric. Interestingly, at low applied electric fields of 100 MV/m a remnant polarization is seen in the high dipole moment device that is nearly 3.5 times larger than the value observed in the lower dipole moment samples, suggesting that the degree of dipolar order is higher at low operating voltages for the high dipole moment device. We will also discuss the use of peptide-based nanostructures derived from natural amino acids as building blocks for biocompatible devices. These peptides can be used in a bottom-up process without the need for expensive lithography. Thin films of L,L-diphenylalanine micro/nanostructures (FF-MNSs) were used as the dielectric layer in pentacene-based FETs and metal-insulator-semiconductor diodes both in bottom-gate and top-gate structures. It is demonstrated that the FFMNSs can be functionalized for detection of enzyme-analyte interactions. This work opens up a novel and facile route towards scalable organic electronics using peptide nanostructures as scaffolding and as a platform for biosensing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kurishima, Kazunori, E-mail: ce41034@meiji.ac.jp; Nabatame, Toshihide, E-mail: NABATAME.Toshihide@nims.go.jp; Shimizu, Maki

To investigate the influence of ionic/covalent interface of Al{sub 2}O{sub 3}/SiO{sub 2} gate insulator on the electrical properties of thin-film transistors (TFTs) with ionic Ga-In-Zn-O (GIZO) semiconducting channel layers, Al{sub 2}O{sub 3} layers of different thickness were introduced between SiO{sub 2} and GIZO using plasma-enhanced atomic layer deposition. The GIZO layers were obtained by DC magnetron sputtering using a GIZO target (Ga:In:Zn = 1:1:1 mol. %). The GIZO TFTs with an Al{sub 2}O{sub 3}/SiO{sub 2} gate insulator exhibited positive threshold voltage (V{sub th}) shift (about 1.1 V), V{sub th} hysteresis suppression (0.23 V), and electron mobility degradation (about 13%) compared with thosemore » of a GIZO TFT with SiO{sub 2} gate insulator by the influence of ionic/ionic and ionic/covalent interface at Al{sub 2}O{sub 3}/GIZO and Al{sub 2}O{sub 3}/SiO{sub 2}, respectively. To clarify the origin of the positive V{sub th} shift, the authors estimated the shifts of flatband voltage (0.4 V) due to the dipole and the fixed charge (−1.1 × 10{sup 11}/cm{sup 2}) at Al{sub 2}O{sub 3}/SiO{sub 2} interface, from capacitance–voltage data for Pt/Al{sub 2}O{sub 3}/SiO{sub 2}/p-Si capacitors. Based on these experimental data, the authors found that the positive V{sub th} shift (1.1 V) could be divided into three components: the dipole (−0.4 V) and fixed charge (0.15 V) at the SiO{sub 2}/Al{sub 2}O{sub 3} interface, and the fixed charge (1.35 V) at the Al{sub 2}O{sub 3}/GIZO interface. Finally, it is noted that heterointerface of SiO{sub 2}/Al{sub 2}O{sub 3}/GIZO stacks is important not only to recognize mechanism of V{sub th} shift but also to design future TFTs with high-k dielectrics and low operating voltage.« less

CALUTRON

DOEpatents

Brobeck, W.M.; Lofgren, E.J.; Thornton, R.L.

1959-06-01

A calutron improved in liner and capacity is offered. The liner is a hollow insulated structure at high negative potential with respect to the vessel. The liner has delimiting vanes to prevent ions from one beam scattering into the receiver from another beam. The double beam-double receiver feature is thus made possible, increasing the capacity of the calutron. (T.R.H.)

Organic electrical double layer transistors gated with ionic liquids

NASA Astrophysics Data System (ADS)

Xie, Wei; Frisbie, C. Daniel

2011-03-01

Transport in organic semiconductors gated with several types of ionic liquids has been systematically studied at charge densities larger than 1013 cm-2 . We observe a pronounced maximum in channel conductance for both p-type and n-type organic single crystals which is attributed to carrier localization at the semiconductor-electrolyte interface. Carrier mobility, as well as charge density and dielectric capacitance are determined through displacement current measurement and capacitance-voltage measurement. By using a larger-sized and spherical anion, tris(pentafluoroethyl)trifluorophosphate (FAP), effective carrier mobility in rubrene can be enhanced substantially up to 3.2 cm2 V-1 s -1 . Efforts have been made to maximize the charge density in rubrene single crystals, and at low temperature when higher gate bias can be applied, charge density can more than double the amount of that at room temperature, reaching 8*1013 cm-2 holes (0.4 holes per rubrene molecule). NSF MRSEC program at the University of Minnesota.

Sub-50-as isolated extreme ultraviolet continua generated by 1.6-cycle near-infrared pulse combined with double optical gating scheme

NASA Astrophysics Data System (ADS)

Oguri, Katsuya; Mashiko, Hiroki; Ogawa, Tatsuya; Hanada, Yasutaka; Nakano, Hidetoshi; Gotoh, Hideki

2018-04-01

We demonstrate the generation of ultrabroad bandwidth attosecond continua extending to sub-50-as duration in the extreme ultraviolet (EUV) region based on a 1.6-cycle Ti:sapphire laser pulse. The combination of the amplitude gating scheme with a sub-two-cycle driver pulse and the double optical gating scheme achieves the continuum generation with a bandwidth of 70 eV at the full width at half maximum near the peak photon energy of 140 eV, which supports a Fourier-transform-limited pulse duration as short as 32 as. The carrier-envelope-phase (CEP) dependence of the attosecond continua shows a single-peak structure originating from the half-cycle cut-off at appropriate CEP values, which strongly indicates the generation of a single burst of an isolated attosecond pulse. Our approach suggests a possibility for isolated sub-50-as pulse generation in the EUV region by compensating for the intrinsic attosecond chirp with a Zr filter.

Thermal insulated glazing unit

DOEpatents

Selkowitz, Stephen E.; Arasteh, Dariush K.; Hartmann, John L.

1991-01-01

An improved insulated glazing unit is provided which can attain about R5 to about R10 thermal performance at the center of the glass while having dimensions about the same as those of a conventional double glazed insulated glazing unit. An outer glazing and inner glazing are sealed to a spacer to form a gas impermeable space. One or more rigid, non-structural glazings are attached to the inside of the spacer to divide the space between the inner and outer glazings to provide insulating gaps between glazings of from about 0.20 inches to about 0.40 inches. One or more glazing surfaces facing each thermal gap are coated with a low emissivity coating. Finally, the thermal gaps are filled with a low conductance gas such as krypton gas.

Hysteresis free negative total gate capacitance in junctionless transistors

NASA Astrophysics Data System (ADS)

Gupta, Manish; Kranti, Abhinav

2017-09-01

In this work, we report on the hysteresis free impact ionization induced off-to-on transition while preserving sub-60 mV/decade Subthreshold swing (S-swing) using asymmetric mode operation in double gate silicon (Si) and germanium (Ge) junctionless (JL) transistor. It is shown that sub-60 mV/decade steep switching due to impact ionization implies a negative value of the total gate capacitance. The performance of asymmetric gate JL transistor is compared with symmetric gate operation of JL device, and the condition for hysteresis free current transition with a sub-60 mV/decade switching is analyzed through the product of current density (J) and electric field (E). It is shown that asymmetric gate operation limits the degree of impact ionization inherent in the semiconductor film to levels sufficient for negative total gate capacitance but lower than that required for the occurrence of hysteresis. The work highlights new viewpoints related to the suppression of hysteresis associated with steep switching JL transistors while maintaining S-swing within the range 6-15 mV/decade leading to the negative value of total gate capacitance.

Automatic identification and location technology of glass insulator self-shattering

NASA Astrophysics Data System (ADS)

Huang, Xinbo; Zhang, Huiying; Zhang, Ye

2017-11-01

The insulator of transmission lines is one of the most important infrastructures, which is vital to ensure the safe operation of transmission lines under complex and harsh operating conditions. The glass insulator often self-shatters but the available identification methods are inefficient and unreliable. Then, an automatic identification and localization technology of self-shattered glass insulators is proposed, which consists of the cameras installed on the tower video monitoring devices or the unmanned aerial vehicles, the 4G/OPGW network, and the monitoring center, where the identification and localization algorithm is embedded into the expert software. First, the images of insulators are captured by cameras, which are processed to identify the region of insulator string by the presented identification algorithm of insulator string. Second, according to the characteristics of the insulator string image, a mathematical model of the insulator string is established to estimate the direction and the length of the sliding blocks. Third, local binary pattern histograms of the template and the sliding block are extracted, by which the self-shattered insulator can be recognized and located. Finally, a series of experiments is fulfilled to verify the effectiveness of the algorithm. For single insulator images, Ac, Pr, and Rc of the algorithm are 94.5%, 92.38%, and 96.78%, respectively. For double insulator images, Ac, Pr, and Rc are 90.00%, 86.36%, and 93.23%, respectively.

Sulfur as a surface passivation for InP

NASA Technical Reports Server (NTRS)

Iyer, R.; Chang, R. R.; Lile, D. L.

1988-01-01

The use of liquid and gas phase sulfur pretreatment of the surface of InP as a way to form a near-ideal passivated surface prior to chemical vapor deposition of SiO2 was investigated. Results of high-frequency and quasi-static capacitance-voltage measurements, as well as enhancement mode insulated gate field-effect transistor (FET) transductance and drain current stability studies, all support the efficacy of this approach for metal-insulator-semiconductor application of this semiconductor. In particular, surface state values in the range of 10 to the 10th to a few 10 to the 11th/sq cm per eV and enhancement mode FET drain current drifts of less than 5 percent over a 12 h test period were measured.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Magnon-based logic in a multi-terminal YIG/Pt nanostructure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ganzhorn, Kathrin, E-mail: kathrin.ganzhorn@wmi.badw.de; Klingler, Stefan; Wimmer, Tobias

2016-07-11

Boolean logic is the foundation of modern digital information processing. Recently, there has been a growing interest in phenomena based on pure spin currents, which allows to move from charge to spin based logic gates. We study a proof-of-principle logic device based on the ferrimagnetic insulator Yttrium Iron Garnet, with Pt strips acting as injectors and detectors for non-equilibrium magnons. We experimentally observe incoherent superposition of magnons generated by different injectors. This allows to implement a fully functional majority gate, enabling multiple logic operations (AND and OR) in one and the same device. Clocking frequencies of the order of severalmore » GHz and straightforward down-scaling make our device promising for applications.« less

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

NASA Astrophysics Data System (ADS)

Yang, Xiaolei; Tao, Yonghong; Yang, Tongtong; Huang, Runhua; Song, Bai

2018-03-01

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

NASA Astrophysics Data System (ADS)

Konwar, K.; Baishya, B.

2010-12-01

Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La2O3, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07×10-3 cm2V-1s-1 for the devices annealed in vacuum at 90° C for 5 hours.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

PubMed

Park, Jae Hyo; Son, Se Wan; Byun, Chang Woo; Kim, Hyung Yoon; Joo, So Na; Lee, Yong Woo; Yun, Seung Jae; Joo, Seung Ki

2013-10-01

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

High-fidelity gates in quantum dot spin qubits

PubMed Central

Koh, Teck Seng; Coppersmith, S. N.; Friesen, Mark

2013-01-01

Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet–triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning ϵ, which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound that is specific to the qubit-gate combination. We show that similar gate fidelities should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins. PMID:24255105

Gates Foundation donates $25 million for AIDS vaccine.

PubMed

1999-05-07

The International AIDS Vaccine Initiative (IAVI) received a $25 million five-year grant from Bill and Melinda Gates through the William H. Gates Foundation. This is the largest gift seen in the AIDS epidemic, and will allow IAVI to more than double vaccine development efforts. IAVI is currently developing two potential vaccines, hopes to study three others, and is working with the business community to insure that a successful vaccine is affordable in developing countries. With 16,000 new infections occurring daily, a vaccine is seen as the most effective way to stop the epidemic. The William H. Gates Foundation had donated $1.5 million to IAVI and $100 million for programs to speed the delivery of vaccines to children in poor countries. Internet addresses are included for both IAVI and the William H. Gates Foundation.

Two-dimensional topological crystalline insulator phase in Sb/Bi planar honeycomb with tunable Dirac gap

DOE PAGES

Hsu, Chia -Hsiu; Huang, Zhi -Quan; Crisostomo, Christian P.; ...

2016-01-14

We predict planar Sb/Bi honeycomb to harbor a two-dimensional (2D) topological crystalline insulator (TCI) phase based on first-principles computations. Although buckled Sb and Bi honeycombs support 2D topological insulator (TI) phases, their structure becomes planar under tensile strain. The planar Sb/Bi honeycomb structure restores the mirror symmetry, and is shown to exhibit non-zero mirror Chern numbers, indicating that the system can host topologically protected edge states. Our computations show that the electronic spectrum of a planar Sb/Bi nanoribbon with armchair or zigzag edges contains two Dirac cones within the band gap and an even number of edge bands crossing themore » Fermi level. Lattice constant of the planar Sb honeycomb is found to nearly match that of hexagonal-BN. As a result, the Sb nanoribbon on hexagonal-BN exhibits gapped edge states, which we show to be tunable by an out-of the-plane electric field, providing controllable gating of edge state important for device applications.« less

Metal–insulator transition in a transition metal dichalcogenide: Dependence on metal contacts

NASA Astrophysics Data System (ADS)

Shimazu, Y.; Arai, K.; Iwabuchi, T.

2018-03-01

Transition metal dichalcogenides are promising layered materials for realizing novel nanoelectronic and nano-optoelectronic devices. Molybdenum disulfide (MoS2), a typical transition metal dichalcogenide, has been extensively investigated due to the presence of a sizable band gap, which enables the use of MoS2 as a channel material in field-effect transistors (FET). The gate-voltage-tunable metal–insulator transition and superconductivity using MoS2 have been demonstrated in previous studies. These interesting phenomena can be considered as quantum phase transitions in two-dimensional systems. In this study, we observed that the transport properties of thin MoS2 flakes in FET geometry significantly depend on metal contacts. On comparing Ti/Au with Al contacts, it was found that the threshold voltages for FET switching and metal–insulator transition were considerably lower for the device with Al contacts. This result indicated the significant influence of the Al contacts on the properties of MoS2 devices.

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

NASA Astrophysics Data System (ADS)

Maulik, Subhodip; Sarkar, Anirban; Basu, Srismrita; Daniels-Race, Theda

2018-05-01

A facile, cost-effective, voltage-controlled, "single-step" method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

Low inductance diode design of the Proto 2 accelerator for imploding plasma loads

NASA Astrophysics Data System (ADS)

Hsing, W. W.; Coats, R.; McDaniel, D. H.; Spielman, R. B.

A new water transmission line convolute, single piece insulator, and double accelerator. The water transmission lines have a 5 cm gap to eliminate any water arcing. A two-dimensional magnetic field code was used to calculate the convolute inductance. An acrylic insulator was used as well as a single piece, laminated polycarbonate insulator. They have been successfully tested at over 90% of the Shipman criteria for classical insulator breakdown, although the laminations in the polycarbonate insulator failed after a few shots. The anode and cathode each have two pieces and are held together mechanically. The vacuum MITL tapers to a 3 mm minimum gap. The total inductance is 8.4 nH for gas puff loads and 7.8 nH for imploding foil loads. Out of a forward-going energy of 290 kJ, 175 kJ has been delivered past the insulator, and 100 kJ has been successfully delivered to the load.

Electrolysis-induced protonation of VO2 thin film transistor for the metal-insulator phase modulation

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Endo, Kenji; Ohta, Hiromichi

2016-02-01

Compared to state-of-the-art modulation techniques, protonation is the most ideal to control the electrical and optical properties of transition metal oxides (TMOs) due to its intrinsic non-volatile operation. However, the protonation of TMOs is not typically utilized for solid-state devices because of imperative high-temperature annealing treatment in hydrogen source. Although one solution for room temperature (RT) protonation of TMOs is liquid-phase electrochemistry, it is unsuited for practical purposes due to liquid-leakage problem. Herein we demonstrate solid-state RT-protonation of vanadium dioxide (VO2), which is a well-known thermochromic TMO. We fabricated the three terminal thin-film-transistor structure on an insulating VO2 film using a water-infiltrated nanoporous glass, which serves as a solid electrolyte. For gate voltage application, water electrolysis and protonation/deprotonation of VO2 film surface occurred, leading to reversible metal-insulator phase conversion of ~11-nm-thick VO2 layer. The protonation was clearly accompanied by the structural change from an insulating monoclinic to a metallic tetragonal phase. Present results offer a new route for the development of electro-optically active solid-state devices with TMO materials by engineering RT protonation.

Investigation of 1/f Noise Mechanisms in Midwave Infrared HgCdTe Gated Photodiodes

NASA Astrophysics Data System (ADS)

Westerhout, R. J.; Musca, C. A.; Antoszewski, J.; Dell, J. M.; Faraone, L.

2007-08-01

In this work, gated midwave infrared (MWIR) Hg1 x Cd x Te photodiodes are used to investigate the physical origin of 1/f noise generation. Gated photodiodes were fabricated on liquid-phase epitaxy p-type HgCdTe MWIR material with a vacancy-doped concentration of 1.6 × 1016 cm-3 and x = 0.31. CdTe was thermally deposited and used as both a passivant and a mask for the plasma-based type conversion, and ZnS was used as an insulator. Fabricated devices show a R 0 A of 1 5 × 104 Ωcm2 with zero gate bias. Application of 2 V to the gate improves the R 0 A by more than two orders of magnitude to 6.0 × 106 Ωcm2, which corresponds to the p-type surface being at transition between depletion and weak inversion. Trap-assisted tunneling (TAT) current was observed at negative gate biases and reverse junction biases. For gate biases greater than 3 V, a field-induced junction breakdown was observed. An I n = α I β f -0.5 trend was observed above 200 pA reverse bias dark current, with α = 3.5 × 10-5 and β = 0.82, which corresponds to the TAT dominated region. Below 200 pA, junction generation-recombination (GR) current starts to dominate and this previously mentioned trend is no longer observed. Junction GR current was not seen to be correlated with 1/f noise in these photodiodes.

The ZnO-FET Biosensor for Cardiac Troponin I

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md; Nuzaihan, M. N. M.; Gopinath, Subash C. B.; Ruslinda, A. R.; Hashim, U.

2018-03-01

This paper investigates the influence of substrate-gate coupling on the ZnO-FET biosensor’s sensitivity for detection of cardiac troponin I (cTnI), a ‘gold standard’ biomarker for acute myocardial infarction (AMI). The FET-based device with introduction of substrate-gate coupling on p-type silicon-on-insulator (SOI) substrate is fabricated using conventional lithography processes. An n-type zinc oxide (ZnO) thin film deposited via electron-beam evaporator is used as transducer for bridging the source and drain regions. Surface modifications via functionalization with 3-aminopropyltriethoxysilane (APTES) and glutaraldehyde (GA) as chemical linkers, followed by immobilization of cTnI monoclonal antibody (MAb-cTnI) as bio-receptor on the ZnO thin film allow different concentration of cTnI detection with high selectivity. The device’s sensitivity increases up to 9 %·(g/ml)-1 with the increase of the substrate-gate voltage (VSG) up to -10 V at very low limit of detection (LOD) down to 1.6 fg/ml.

Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

NASA Astrophysics Data System (ADS)

Miyoshi, Tomoyuki; Oshima, Takayuki; Noguchi, Junji

2015-05-01

High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Isolated Attosecond Pulse Generation without the Need to Stabilize the Carrier-Envelope Phase of Driving Lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gilbertson, Steve; Khan, Sabih D.; Wu Yi

2010-08-27

Single isolated attosecond pulses can be extracted from a pulse train with an ultrafast gate in the generation target. By setting the gate width sufficiently narrow with the generalized double optical gating, we demonstrate that single isolated attosecond pulses can be generated with any arbitrary carrier-envelope phase value of the driving laser. The carrier-envelope phase only affects the photon flux, not the pulse duration or contrast. Our results show that isolated attosecond pulses can be generated using carrier-envelope phase unstabilized 23 fs pulses directly from chirped pulse amplifiers.