Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer.

PubMed

Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

2017-04-20

Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO₂ have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm² at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 10⁵. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices.

Organic Field Effect Transistor Using Amorphous Fluoropolymer as Gate Insulating Film

NASA Astrophysics Data System (ADS)

Kitajima, Yosuke; Kojima, Kenzo; Mizutani, Teruyoshi; Ochiai, Shizuyasu

Organic field effect transistors are fabricated by the active layer of Regioregular poly (3-hexylthiophene-2,5-diy)(P3HT) thin film. CYTOP thin film made from Amorphous Fluoropolymer and fabricated by spin-coating is adopted to a gate dielectric layer on Polyethylenenaphthalate (PEN) thin film that is the substrate of an organic field effect transistor. The surface morphology and molecular orientation of P3HT thin films is observed by atomic force microscope (AFM) and X-Ray diffractometer (XRD). Grains are observed on the CYTOP thin film via an AFM image and the P3HT molecule is oriented perpendicularly on the CYTOP thin film. Based on the performance of the organic field effect transistor, the carrier mobility is 0.092 cm2/Vs, the ON/OFF ratio is 7, and the threshold voltage is -12 V. The ON/OFF ratio is relatively low and to improve On/Off ratio, the CYTOP/Polyimide double gate insulating layer is adopted to OFET.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

PubMed

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

NASA Astrophysics Data System (ADS)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Electrical responses of artificial DNA nanostructures on solution-processed In-Ga-Zn-O thin-film transistors with multistacked active layers.

PubMed

Jung, Joohye; Kim, Si Joon; Yoon, Doo Hyun; Kim, Byeonghoon; Park, Sung Ha; Kim, Hyun Jae

2013-01-01

We propose solution-processed In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) with multistacked active layers for detecting artificial deoxyribonucleic acid (DNA). Enhanced sensing ability and stable electrical performance of TFTs were achieved through use of multistacked active layers. Our IGZO TFT had a turn-on voltage (V(on)) of -0.8 V and a subthreshold swing (SS) value of 0.48 V/decade. A dry-wet method was adopted to immobilize double-crossover DNA on the IGZO surface, after which an anomalous hump effect accompanying a significant decrease in V(on) (-13.6 V) and degradation of SS (1.29 V/decade) was observed. This sensing behavior was attributed to the middle interfaces of the multistacked active layers and the negatively charged phosphate groups on the DNA backbone, which generated a parasitic path in the TFT device. These results compared favorably with those reported for conventional field-effect transistor-based DNA sensors with remarkable sensitivity and stability.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Strategy for improved frequency response of electric double-layer capacitors

NASA Astrophysics Data System (ADS)

Wada, Yoshifumi; Pu, Jiang; Takenobu, Taishi

2015-10-01

We propose a strategy for improving the response speed of electric double-layer capacitors (EDLCs) and electric double-layer transistors (EDLTs), based on an asymmetric structure with differently sized active materials and gate electrodes. We validate the strategy analytically by a classical calculation and experimentally by fabricating EDLCs with asymmetric Au electrodes (1:50 area ratio and 7.5 μm gap distance). The performance of the EDLCs is compared with that of conventional symmetric EDLCs. Our strategy dramatically improved the cut-off frequency from 14 to 93 kHz and this improvement is explained by fast charging of smaller electrodes. Therefore, this approach is particularly suitable to EDLTs, potentially expanding the applicability to medium speed (kHz-MHz) devices.

Carrier mobility and scattering lifetime in electric double-layer gated few-layer graphene

NASA Astrophysics Data System (ADS)

Piatti, E.; Galasso, S.; Tortello, M.; Nair, J. R.; Gerbaldi, C.; Bruna, M.; Borini, S.; Daghero, D.; Gonnelli, R. S.

2017-02-01

We fabricate electric double-layer field-effect transistor (EDL-FET) devices on mechanically exfoliated few-layer graphene. We exploit the large capacitance of a polymeric electrolyte to study the transport properties of three, four and five-layer samples under a large induced surface charge density both above and below the glass transition temperature of the polymer. We find that the carrier mobility shows a strong asymmetry between the hole and electron doping regime. We then employ ab initio density functional theory (DFT) calculations to determine the average scattering lifetime from the experimental data. We explain its peculiar dependence on the carrier density in terms of the specific properties of the electrolyte we used in our experiments.

AlGaAs/InGaAs/AlGaAs double pulse doped pseudomorphic high electron mobility transistor structures on InGaAs substrates

NASA Astrophysics Data System (ADS)

Hoke, W. E.; Lyman, P. S.; Mosca, J. J.; McTaggart, R. A.; Lemonias, P. J.; Beaudoin, R. M.; Torabi, A.; Bonner, W. A.; Lent, B.; Chou, L.-J.; Hsieh, K. C.

1997-10-01

Double pulse doped AlGaAs/InGaAs/AlGaAs pseudomorphic high electron mobility transistor (PHEMT) structures have been grown on InxGa1-xAs (x=0.025-0.07) substrates using molecular beam epitaxy. A strain compensated, AlGaInAs/GaAs superlattice was used for improved resistivity and breakdown. Excellent electrical and optical properties were obtained for 110-Å-thick InGaAs channel layers with indium concentrations up to 31%. A room temperature mobility of 6860 cm2/V s with 77 K sheet density of 4.0×1012cm-2 was achieved. The InGaAs channel photoluminescence intensity was equivalent to an analogous structure on a GaAs substrate. To reduce strain PHEMT structures with a composite InGaP/AlGaAs Schottky layer were also grown. The structures also exhibited excellent electrical and optical properties. Transmission electron micrographs showed planar channel interfaces for highly strained In0.30Ga0.70As channel layers.

Enhanced electrical properties of oxide semiconductor thin-film transistors with high conductivity thin layer insertion for the channel region

NASA Astrophysics Data System (ADS)

Nguyen, Cam Phu Thi; Raja, Jayapal; Kim, Sunbo; Jang, Kyungsoo; Le, Anh Huy Tuan; Lee, Youn-Jung; Yi, Junsin

2017-02-01

This study examined the performance and the stability of indium tin zinc oxide (ITZO) thin film transistors (TFTs) by inserting an ultra-thin indium tin oxide (ITO) layer at the active/insulator interface. The electrical properties of the double channel device (ITO thickness of 5 nm) were improved in comparison with the single channel ITZO or ITO devices. The TFT characteristics of the device with an ITO thickness of less than 5 nm were degraded due to the formation of an island-like morphology and the carriers scattering at the active/insulator interface. The 5 nm-thick ITO inserted ITZO TFTs (optimal condition) exhibited a superior field effect mobility (∼95 cm2/V·s) compared with the ITZO-only TFTs (∼34 cm2/V·s). The best characteristics of the TFT devices with double channel layer are due to the lowest surface roughness (0.14 nm) and contact angle (50.1°) that result in the highest hydrophicility, and the most effective adhesion at the surface. Furthermore, the threshold voltage shifts for the ITO/ITZO double layer device decreased to 0.80 and -2.39 V compared with 6.10 and -6.79 V (for the ITZO only device) under positive and negative bias stress, respectively. The falling rates of EA were 0.38 eV/V and 0.54 eV/V for the ITZO and ITO/ITZO bi-layer devices, respectively. The faster falling rate of the double channel devices suggests that the trap density, including interface trap and semiconductor bulk trap, can be decreased by the ion insertion of a very thin ITO film into the ITZO/SiO2 reference device. These results demonstrate that the double active layer TFT can potentially be applied to the flat panel display.

A NANO enhancement to Moore's law

NASA Astrophysics Data System (ADS)

Wu, Jerry; Shen, Yin-Lin; Reinhardt, Kitt; Szu, Harold

2012-06-01

In the past 46 years, Intel Moore observed an exponential doubling in the number of transistors in every 18 months through the size reduction of individual transistor components since 1965. In this paper, we are exploring the nanotechnology impact upon the Law. Since we cannot break down the atomic size barrier, the fact implies a fundamental size limit at the atomic or Nanotechnology scale. This means, no more simple 18 month doubling as in Moore's Law, but other forms of transistor doubling may happen at a different slope in new directions. We are particularly interested in the Nano enhancement area. (i) 3-D: If the progress in shrinking the in-plane dimensions (2D) is to slow down, vertical integration (3D) can help increasing the areal device transistor density and keep us on the modified Moore's Law curve including the 3rd dimension. As the devices continue to shrink further into the 20 to 30 nm range, the consideration of thermal properties and transport in such nanoscale devices becomes increasingly important. (ii) Carbon Computing: Instead of traditional Transistors, the other types of transistors material are rapidly developed in Laboratories Worldwide, e.g. IBM Spintronics bandgap material and Samsung Nano-storage material, HD display Nanotechnology, which are modifying the classical Moore's Law. We shall consider the overall limitation of phonon engineering, fundamental information unit 'Qubyte' in quantum computing, Nano/Micro Electrical Mechanical System (NEMS), Carbon NanoTubes (CNTs), single layer Graphemes, single strip Nano-Ribbons, etc., and their variable degree of fabrication maturities for the computing and information processing applications.

Calculation of the electron wave function in a graded-channel double-heterojunction modulation-doped field-effect transistor

NASA Technical Reports Server (NTRS)

Mui, D. S. L.; Patil, M. B.; Morkoc, H.

1989-01-01

Three double-heterojunction modulation-doped field-effect transistor structures with different channel composition are investigated theoretically. All of these transistors have an In(x)Ga(1-x)As channel sandwiched between two doped Al(0.3)Ga(0.7)As barriers with undoped spacer layers. In one of the structures, x varies from 0 from either heterojunction to 0.15 at the center of the channel quadratically; in the other two, constant values of x of 0 and 0.15 are used. The Poisson and Schroedinger equations are solved self-consistently for the electron wave function in all three cases. The results showed that the two-dimensional electron gas (2DEG) concentration in the channel of the quadratically graded structure is higher than the x = 0 one and slightly lower than the x = 0.15 one, and the mean distance of the 2DEG is closer to the center of the channel for this transistor than the other two. These two effects have important implications on the electron mobility in the channel.

Determination of the electronic energy levels of colloidal nanocrystals using field-effect transistors and Ab-initio calculations.

PubMed

Bisri, Satria Zulkarnaen; Degoli, Elena; Spallanzani, Nicola; Krishnan, Gopi; Kooi, Bart Jan; Ghica, Corneliu; Yarema, Maksym; Heiss, Wolfgang; Pulci, Olivia; Ossicini, Stefano; Loi, Maria Antonietta

2014-08-27

Colloidal nanocrystals electronic energy levels are determined by strong size-dependent quantum confinement. Understanding the configuration of the energy levels of nanocrystal superlattices is vital in order to use them in heterostructures with other materials. A powerful method is reported to determine the energy levels of PbS nanocrystal assemblies by combining the utilization of electric-double-layer-gated transistors and advanced ab-initio theory. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Doping Nitrogen in InGaZnO Thin Film Transistor with Double Layer Channel Structure.

PubMed

Chang, Sheng-Po; Shan, Deng

2018-04-01

This paper presents the electrical characteristics of doping nitrogen in an amorphous InGaZnO thin film transistor. The IGZO:N film, which acted as a channel layer, was deposited using RF sputtering with a nitrogen and argon gas mixture at room temperature. The optimized parameters of the IGZO:N/IGZO TFT are as follows: threshold voltage is 0.5 V, field effect mobility is 14.34 cm2V-1S-1. The on/off current ratio is 106 and subthreshold swing is 1.48 V/decade. The positive gate bias stress stability of InGaZnO doping with nitrogen shows improvement compared to doping with oxygen.

Enhancement of superconducting transition temperature in FeSe electric-double-layer transistor with multivalent ionic liquids

NASA Astrophysics Data System (ADS)

Miyakawa, Tomoki; Shiogai, Junichi; Shimizu, Sunao; Matsumoto, Michio; Ito, Yukihiro; Harada, Takayuki; Fujiwara, Kohei; Nojima, Tsutomu; Itoh, Yoshimitsu; Aida, Takuzo; Iwasa, Yoshihiro; Tsukazaki, Atsushi

2018-03-01

We report on an enhancement of the superconducting transition temperature (Tc) of the FeSe-based electric-double-layer transistor (FeSe-EDLT) by applying the multivalent oligomeric ionic liquids (ILs). The IL composed of dimeric cation (divalent IL) enables a large amount of charge accumulation on the surface of the FeSe ultrathin film, resulting in inducing electron-rich conduction even in a rather thick 10 nm FeSe channel. The onset Tc in FeSe-EDLT with the divalent IL is enhanced to be approaching about 50 K at the thin limit, which is about 7 K higher than that in EDLT with conventional monovalent ILs. The enhancement of Tc is a pronounced effect of the application of the divalent IL, in addition to the large capacitance, supposing preferable interface formation of ILs driven by geometric and/or Coulombic effect. The present finding strongly indicates that multivalent ILs are powerful tools for controlling and improving physical properties of materials.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Electric double-layer transistor using layered iron selenide Mott insulator TlFe1.6Se2

PubMed Central

Katase, Takayoshi; Hiramatsu, Hidenori; Kamiya, Toshio; Hosono, Hideo

2014-01-01

A1–xFe2–ySe2 (A = K, Cs, Rb, Tl) are recently discovered iron-based superconductors with critical temperatures (Tc) ranging up to 32 K. Their parent phases have unique properties compared with other iron-based superconductors; e.g., their crystal structures include ordered Fe vacancies, their normal states are antiferromagnetic (AFM) insulating phases, and they have extremely high Néel transition temperatures. However, control of carrier doping into the parent AFM insulators has been difficult due to their intrinsic phase separation. Here, we fabricated an Fe-vacancy-ordered TlFe1.6Se2 insulating epitaxial film with an atomically flat surface and examined its electrostatic carrier doping using an electric double-layer transistor (EDLT) structure with an ionic liquid gate. The positive gate voltage gave a conductance modulation of three orders of magnitude at 25 K, and further induced and manipulated a phase transition; i.e., delocalized carrier generation by electrostatic doping is the origin of the phase transition. This is the first demonstration, to the authors' knowledge, of an EDLT using a Mott insulator iron selenide channel and opens a way to explore high Tc superconductivity in iron-based layered materials, where carrier doping by conventional chemical means is difficult. PMID:24591598

Optimizing pentacene thin-film transistor performance: Temperature and surface condition induced layer growth modification.

PubMed

Lassnig, R; Hollerer, M; Striedinger, B; Fian, A; Stadlober, B; Winkler, A

2015-11-01

In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p ++ -silicon/silicon dioxide bottom-gate, gold bottom-contact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered + carbon and unsputtered + carbon) at sample temperatures during deposition of 200 K, 300 K and 350 K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3-4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact-channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8 ML) pentacene transistors of comparably high mobility.

Optimizing pentacene thin-film transistor performance: Temperature and surface condition induced layer growth modification

PubMed Central

Lassnig, R.; Hollerer, M.; Striedinger, B.; Fian, A.; Stadlober, B.; Winkler, A.

2015-01-01

In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p++-silicon/silicon dioxide bottom-gate, gold bottom-contact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered + carbon and unsputtered + carbon) at sample temperatures during deposition of 200 K, 300 K and 350 K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3–4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact–channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8 ML) pentacene transistors of comparably high mobility. PMID:26543442

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

PubMed Central

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts

NASA Astrophysics Data System (ADS)

Cho, Sang-Hyeok; Cho, Kwanghee; Park, No-Won; Park, Soonyong; Koh, Jung-Hyuk; Lee, Sang-Kwon

2017-05-01

We report p-type tin monoselenide (SnSe) single crystals, grown in double-sealed quartz ampoules using a modified Bridgman technique at 920 °C. X-ray powder diffraction (XRD) and energy dispersive X-ray spectroscopy (EDX) measurements clearly confirm that the grown SnSe consists of single-crystal SnSe. Electrical transport of multi-layer SnSe nanoflakes, which were prepared by exfoliation from bulk single crystals, was conducted using back-gated field-effect transistor (FET) structures with Au and Ti contacts on SiO2/Si substrates, revealing that multi-layer SnSe nanoflakes exhibit p-type semiconductor characteristics owing to the Sn vacancies on the surfaces of SnSe nanoflakes. In addition, a strong carrier screening effect was observed in 70-90-nm-thick SnSe nanoflake FETs. Furthermore, the effect of the metal contacts to multi-layer SnSe nanoflake-based FETs is also discussed with two different metals, such as Ti/Au and Au contacts.

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Study of vertical type organic light emitting transistor using ZnO

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2006-04-01

We propose a new type organic light emitting transistor (OLET) combining static induction transistor (SIT) with double hetero junction type organic light emitting diodes (OLED) using n-type zinc oxide (ZnO) films which works as a transparent and electron injection layer. The device characteristics of newly developed OLED and ZnO-SIT showed relatively high luminance of about 500 cd/m2 at 7.6 mA/cm2 and is able to control by gate voltage as low as a few volts, respectively. The crystal structures of the ZnO films as a function of Ar/O II flow ratio and the basic characteristics of the thin film transistor (TFT) and SIT depending on the ZnO sputtering conditions are investigated. The results obtained here show that the OLET using ZnO film is a suitable element for flexible sheet displays.

A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistor

NASA Technical Reports Server (NTRS)

Halsor, J. L.; Lin, H. C.

1974-01-01

Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Direct detection of fibrinogen in human plasma using electric-double-layer gated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Regmi, Abiral; Sarangadharan, Indu; Chen, Yen-Wen; Hsu, Chen-Pin; Lee, Geng-Yen; Chyi, Jen-Inn; Shiesh, Shu-Chu; Lee, Gwo-Bin; Wang, Yu-Lin

2017-08-01

Fibrinogen found in blood plasma is an important protein biomarker for potentially fatal diseases such as cardiovascular diseases. This study focuses on the development of an assay to detect plasmatic fibrinogen using electrical double layer gated AlGaN/GaN high electron mobility transistor biosensors without complex sample pre-treatment methods used in the traditional assays. The test results in buffer solution and clinical plasma samples show high sensitivity, specificity, and dynamic range. The sensor exhibits an ultra-low detection limit of 0.5 g/l and a detection range of 0.5-4.5 g/l in 1× PBS with 1% BSA. The concentration dependent sensor signal in human serum samples demonstrates the specificity to fibrinogen in a highly dense matrix of background proteins. The sensor does not require complicated automation, and quantitative results are obtained in 5 min with <5 μl sample volume. This sensing technique is ideal for speedy blood based diagnostics such as POC (point of care) tests, homecare tests, or personalized healthcare.

MMIC DHBT Common-Base Amplifier for 172 GHz

NASA Technical Reports Server (NTRS)

Paidi, Vamsi; Griffith, Zack; Wei, Yun; Dahlstrom, Mttias; Urteaga, Miguel; Rodwell, Mark; Samoska, Lorene; Fung, King Man; Schlecht, Erich

2006-01-01

Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

Optimization of the Solution-Based Indium-Zinc Oxide/Zinc-Tin Oxide Channel Layer for Thin-Film Transistors.

PubMed

Lim, Kiwon; Choi, Pyungho; Kim, Sangsub; Kim, Hyunki; Kim, Minsoo; Lee, Jeonghyun; Hyeon, Younghwan; Koo, Kwangjun; Choi, Byoungdeog

2018-09-01

Double stacked indium-zinc oxide (IZO)/zinc-tin oxide (ZTO) active layers were employed in amorphous-oxide-semiconductor thin-film transistors (AOS TFTs). Channel layers of the TFTs were optimized by varying the molarity of ZTO back channel layers (0.05, 0.1, 0.2, 0.3 M) and the electrical properties of IZO/ZTO double stacked TFTs were compared to single IZO and ZTO TFTs with varying the molarity and molar ratio. On the basis of the results, IZO/ZTO (0.1 M) TFTs showed the excellent electrical properties of saturation mobility (13.6 cm2/V·s), on-off ratio (7×106), and subthreshold swing (0.223 V/decade) compared to ZTO (0.1 M) of 0.73 cm2/V · s, 1 × 107, 0.416 V/decade and IZO (0.04 M) of 0.10 cm2/V · s, 5 × 106, 0.60 V/decade, respectively. This may be attributed to diffusing Sn into front layer during annealing process. In addition, with varying molarity of ZTO back channel layer, from 0.1 M to 0.3 M ZTO back channel TFTs, electrical properties and positive bias stability deteriorated with increasing molarity of back channel layer because of increasing total trap states. On the other hand, 0.05 M ZTO back channel TFT had inferior electrical properties than that of 0.1 M ZTO back channel TFT. It was related to back channel effect because of having thin thickness of channel layer. Among these devices, 0.1 M ZTO back channel TFT had a lowest total trap density, outstanding electrical properties and stability. Therefore, we recommended IZO/ZTO (0.1 M) TFT as a promising channel structure for advanced display applications.

Demonstration of β-(AlxGa1-x)2O3/Ga2O3 double heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Zhang, Yuewei; Joishi, Chandan; Xia, Zhanbo; Brenner, Mark; Lodha, Saurabh; Rajan, Siddharth

2018-06-01

In this work, we demonstrate modulation-doped β-(AlxGa1-x)2O3/Ga2O3 double heterostructure field effect transistors. The maximum sheet carrier density for a two-dimensional electron gas (2DEG) in a β-(AlxGa1-x)2O3/Ga2O3 heterostructure is limited by the conduction band offset and parasitic channel formation in the barrier layer. We demonstrate a double heterostructure to realize a β-(AlxGa1-x)2O3/Ga2O3/(AlxGa1-x)2O3 quantum well, where electrons can be transferred from below and above the β-Ga2O3 quantum well. The confined 2DEG charge density of 3.85 × 1012 cm-2 was estimated from the low-temperature Hall measurement, which is higher than that achievable in a single heterostructure. Hall mobilities of 1775 cm2/V.s at 40 K and 123 cm2/V.s at room temperature were measured. Modulation-doped double heterostructure field effect transistors showed a maximum drain current of IDS = 257 mA/mm, a peak transconductance (gm) of 39 mS/mm, and a pinch-off voltage of -7.0 V at room temperature. The three-terminal off-state breakdown measurement on the device with a gate-drain spacing (LGD) of 1.55 μm showed a breakdown voltage of 428 V, corresponding to an average breakdown field of 2.8 MV/cm. The breakdown measurement on the device with a scaled gate-drain spacing of 196 nm indicated an average breakdown field of 3.2 MV/cm. The demonstrated modulation-doped β-(AlxGa1-x)2O3/Ga2O3 double heterostructure field effect transistor could act as a promising candidate for high power and high frequency device applications.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

A carrier-based analytical theory for negative capacitance symmetric double-gate field effect transistors and its simulation verification

NASA Astrophysics Data System (ADS)

Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

2015-09-01

A carrier-based analytical drain current model for negative capacitance symmetric double-gate field effect transistors (NC-SDG FETs) is proposed by solving the differential equation of the carrier, the Pao-Sah current formulation, and the Landau-Khalatnikov equation. The carrier equation is derived from Poisson’s equation and the Boltzmann distribution law. According to the model, an amplified semiconductor surface potential and a steeper subthreshold slope could be obtained with suitable thicknesses of the ferroelectric film and insulator layer at room temperature. Results predicted by the analytical model agree well with those of the numerical simulation from a 2D simulator without any fitting parameters. The analytical model is valid for all operation regions and captures the transitions between them without any auxiliary variables or functions. This model can be used to explore the operating mechanisms of NC-SDG FETs and to optimize device performance.

Large-current-controllable carbon nanotube field-effect transistor in electrolyte solution

NASA Astrophysics Data System (ADS)

Myodo, Miho; Inaba, Masafumi; Ohara, Kazuyoshi; Kato, Ryogo; Kobayashi, Mikinori; Hirano, Yu; Suzuki, Kazuma; Kawarada, Hiroshi

2015-05-01

Large-current-controllable carbon nanotube field-effect transistors (CNT-FETs) were fabricated with mm-long CNT sheets. The sheets, synthesized by remote-plasma-enhanced CVD, contained both single- and double-walled CNTs. Titanium was deposited on the sheet as source and drain electrodes, and an electrolyte solution was used as a gate electrode (solution gate) to apply a gate voltage to the CNTs through electric double layers formed around the CNTs. The drain current came to be well modulated as electrolyte solution penetrated into the sheets, and one of the solution gate CNT-FETs was able to control a large current of over 2.5 A. In addition, we determined the transconductance parameter per tube and compared it with values for other CNT-FETs. The potential of CNT sheets for applications requiring the control of large current is exhibited in this study.

Characterization of the Electric Double Layer Formation Dynamics of a Metal/Ionic Liquid/Metal Structure.

PubMed

Schmidt, Elliot; Shi, Sha; Ruden, P Paul; Frisbie, C Daniel

2016-06-15

Although ionic liquids (ILs) have been used extensively in recent years as a high-capacitance "dielectric" in electric double layer transistors, the dynamics of the double layer formation have remained relatively unexplored. Better understanding of the dynamics and relaxation processes involved in electric double layer formation will guide device optimization, particularly with regard to switching speed. In this paper, we explore the dynamical characteristics of an IL in a metal/ionic liquid/metal (M/IL/M) capacitor. In particular, we examine a Au/IL/Au structure where the IL is 1-butyl-1-methylpyrrolidinium tris(pentafluoroethyl)trifluorophosphate. The experiments consist of frequency-dependent impedance measurements and time-dependent current vs voltage measurements for applied linear voltage ramps and abrupt voltage steps. The parameters of an equivalent circuit model are determined by fits to the impedance vs frequency data and subsequently verified by calculating the current vs voltage characteristics for the applied potential profiles. The data analysis indicates that the dynamics of the structure are characterized by a wide distribution of relaxation times spanning the range of less than microseconds to longer than seconds. Possible causes for these time scales are discussed.

Type-II GaAsSb/InP heterojunction bipolar light-emitting transistor

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Chu-Kung, B.; Walter, G.; Chan, R.

2004-06-01

We report radiative recombination in the base layer of Type-II InP/GaAsSb/InP double heterojunction bipolar light-emitting transistors (HBLET) operating in the common-emitter configuration. The typical current gain, β, for a 120×120 μm2 emitter area of the HBLET is 38. The optical emission wavelength from a 30 nm GaAs0.51Sb0.49 base is centered at λpeak=1600 nm. Three-port operation of the Type-II HBLET with simultaneously an amplified electrical output and an optical output with signal modulation is demonstrated at 10 kHz.

Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer

NASA Astrophysics Data System (ADS)

Kim, Hyoung Woo; Seok, Ogyun; Moon, Jeong Hyun; Bahng, Wook; Jo, Jungyol

2017-12-01

4H-SiC lateral double implanted metal-oxide-semiconductor field effect transistors (LDIMOSFET) were fabricated on on-axis semi-insulating SiC substrates without using an epi-layer. The LDIMOSFET adopted a current path layer (CPL), which was formed by ion-implantation. The CPL works as a drift region between gate and drain. By using on-axis semi-insulating substrate and optimized CPL parameters, breakdown voltage (BV) of 1093 V and specific on-resistance (R on,sp) of 89.8 mΩ·cm2 were obtained in devices with 20 µm long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm2·V-1·s-1 and the figure-of-merit (BV2/R on,sp) was 13.3 MW/cm2.

Enhanced electron mobility at the two-dimensional metallic surface of BaSnO3 electric-double-layer transistor at low temperatures

NASA Astrophysics Data System (ADS)

Fujiwara, Kohei; Nishihara, Kazuki; Shiogai, Junichi; Tsukazaki, Atsushi

2017-05-01

Wide-bandgap oxides exhibiting high electron mobility hold promise for the development of useful electronic and optoelectronic devices as well as for basic research on two-dimensional electron transport phenomena. A perovskite-type tin oxide, BaSnO3, is currently one of such targets owing to distinctly high mobility at room temperature. The challenge to overcome towards the use of BaSnO3 thin films in applications is suppression of dislocation scattering, which is one of the dominant scattering origins for electron transport. Here, we show that the mobility of the BaSnO3 electric-double-layer transistor reaches 300 cm2 V-1 s-1 at 50 K. The improved mobility indicates that charged dislocation scattering is effectively screened by electrostatically doped high-density charge carriers. We also observed metallic conduction persisting down to 2 K, which is attributed to the transition to the degenerate semiconductor. The experimental verification of bulk-level mobility at the densely accumulated surface sheds more light on the importance of suppression of dislocation scattering by interface engineering in doped BaSnO3 thin films for transparent electrode applications.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Polarity control in WSe2 double-gate transistors

NASA Astrophysics Data System (ADS)

Resta, Giovanni V.; Sutar, Surajit; Balaji, Yashwanth; Lin, Dennis; Raghavan, Praveen; Radu, Iuliana; Catthoor, Francky; Thean, Aaron; Gaillardon, Pierre-Emmanuel; de Micheli, Giovanni

2016-07-01

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical properties. Here, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer WSe2. We show how modulation of the Schottky barriers at drain and source by a separate gate, named program gate, can enable the selection of the carriers injected in the channel, and achieved controllable polarity behaviour with ON/OFF current ratios >106 for both electrons and holes conduction. Polarity-controlled WSe2 transistors enable the design of compact logic gates, leading to higher computational densities in 2D-flatronics.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

AlGaSb Buffer Layers for Sb-Based Transistors

DTIC Science & Technology

2010-01-01

transistor ( HEMT ), molecular beam epitaxy (MBE), field-effect transistor (FET), buffer layer INTRODUCTION High-electron-mobility transistors ( HEMTs ) with InAs...monolayers/s. The use of thinner buffer layers reduces molecular beam epitaxial growth time and source consumption. The buffer layers also exhibit...source. In addition, some of the flux from an Sb cell in a molecular beam epitaxy (MBE) system will deposit near the mouth of the cell, eventually

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Light/negative bias stress instabilities in indium gallium zinc oxide thin film transistors explained by creation of a double donor

NASA Astrophysics Data System (ADS)

Migliorato, Piero; Delwar Hossain Chowdhury, Md; Gwang Um, Jae; Seok, Manju; Jang, Jin

2012-09-01

The analysis of current-voltage (I-V) and capacitance-voltage (C-V) characteristics for amorphous indium gallium zinc oxide Thin film transistors as a function of active layer thickness shows that negative bias under illumination stress (NBIS) is quantitatively explained by creation of a bulk double donor, with a shallow singly ionized state ɛ(0/+) > EC-0.073 eV and a deep doubly ionized state ɛ(++/+) < EC-0.3 eV. The gap density of states, extracted from the capacitance-voltage curves, shows a broad peak between EC-E = 0.3 eV and 1.0 eV, which increases in height with NBIS stress time and corresponds to the broadened transition energy between singly and doubly ionized states. We propose that the center responsible is an oxygen vacancy and that the presence of a stable singly ionized state, necessary to explain our experimental results, could be due to the defect environment provided by the amorphous network.

High Performance 0.1 μm GaAs Pseudomorphic High Electron Mobility Transistors with Si Pulse-Doped Cap Layer for 77 GHz Car Radar Applications

NASA Astrophysics Data System (ADS)

Kim, Sungwon; Noh, Hunhee; Jang, Kyoungchul; Lee, JaeHak; Seo, Kwangseok

2005-04-01

In this study, 0.1 μm double-recessed T-gate GaAs pseudomorphic high electron mobility transistors (PHEMT’s), in which an InGaAs layer and a Si pulse-doped layer in the cap structure are inserted, have been successfully fabricated. This cap structure improves ohmic contact. The ohmic contact resistance is as small as 0.07 Ωmm, consequently the source resistance is reduced by about 20% compared to that of a conventional cap structure. This device shows good DC and microwave performance such as an extrinsic transconductance of 620 mS/mm, a maximum saturated drain current of 780 mA/mm, a cut-off frequency fT of 140 GHz and a maximum oscillation frequency of 260 GHz. The reverse breakdown is 5.7 V at a gate current density of 1 mA/mm. The maximum available gain is about 7 dB at 77 GHz. It is well suited for car radar monolithic microwave integrated circuits (MMICs).

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

Time-dependent density functional theory for the charging kinetics of electric double layer containing room-temperature ionic liquids

DOE PAGES

Lian, Cheng; Univ. of California, Riverside, CA; Zhao, Shuangliang; ...

2016-11-29

Understanding the charging kinetics of electric double layers is of fundamental importance for the design and development of novel electrochemical devices such as supercapacitors and field-effect transistors. In this paper, we study the dynamic behavior of room-temperature ionic liquids using a classical time-dependent density functional theory that accounts for the molecular excluded volume effects, the electrostatic correlations, and the dispersion forces. While the conventional models predict a monotonic increase of the surface charge with time upon application of an electrode voltage, our results show that dispersion between ions results in a non-monotonic increase of the surface charge with the durationmore » of charging. Finally and furthermore, we investigate the effects of van der Waals attraction between electrode/ionic-liquid interactions on the charging processes.« less

Recent progress in photoactive organic field-effect transistors.

PubMed

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

NASA Astrophysics Data System (ADS)

Xue, Peng; Fu, Guicui

2017-03-01

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT's dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT's clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT's dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT's experimental results implies that the CSTBT's abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT's abnormal dynamic avalanche mechanism. Moreover, the CSTBT's negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT's dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Organic and inorganic passivation of p-type SnO thin-film transistors with different active layer thicknesses

NASA Astrophysics Data System (ADS)

Qu, Yunxiu; Yang, Jia; Li, Yunpeng; Zhang, Jiawei; Wang, Qingpu; Song, Aimin; Xin, Qian

2018-07-01

Bottom gated thin-film transistors (TFTs) with various sputtered SnO active layer thicknesses ranging from 10 to 30 nm and different passivation layers have been investigated. The device with 20 nm SnO showed the highest on/off ratio of 1.7 × 104 and the smallest subthreshold swing of 8.43 V dec‑1, and the mobility (0.76 cm2 V‑1 s‑1) was only slightly lower than in TFTs with a thicker SnO layer. However, both the mobility and the on/off ratio of the 15 nm SnO TFT dropped significantly by one order of magnitude. This indicated a strong influence of the top surface on the carrier transport, and we thus applied an organic or an inorganic encapsulation material to passivate the top surface. In the 20 nm TFT, the on/off ratio was doubled after passivation. The performance of the 15 nm TFT was improved even more dramatically with the on/off ratio increased by one order of magnitude and the mobility increased also significantly. Our experiment shows that polymethyl methacrylate passivation is more effective to reduce the shallow trap states, and Al2O3 is more effective in reducing the deep traps in the SnO channel.

The active modulation of drug release by an ionic field effect transistor for an ultra-low power implantable nanofluidic system.

PubMed

Bruno, Giacomo; Canavese, Giancarlo; Liu, Xuewu; Filgueira, Carly S; Sacco, Adriano; Demarchi, Danilo; Ferrari, Mauro; Grattoni, Alessandro

2016-11-10

We report an electro-nanofluidic membrane for tunable, ultra-low power drug delivery employing an ionic field effect transistor. Therapeutic release from a drug reservoir was successfully modulated, with high energy efficiency, by actively adjusting the surface charge of slit-nanochannels 50, 110, and 160 nm in size, by the polarization of a buried gate electrode and the consequent variation of the electrical double layer in the nanochannel. We demonstrated control over the transport of ionic species, including two relevant hypertension drugs, atenolol and perindopril, that could benefit from such modulation. By leveraging concentration-driven diffusion, we achieve a 2 to 3 order of magnitude reduction in power consumption as compared to other electrokinetic phenomena. The application of a small gate potential (±5 V) in close proximity (150 nm) of 50 nm nanochannels generated a sufficiently strong electric field, which doubled or blocked the ionic flux depending on the polarity of the voltage applied. These compelling findings can lead to next generation, more reliable, smaller, and longer lasting drug delivery implants with ultra-low power consumption.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, J.A.; Sherwin, M.E.; Drummond, T.J.; Weckwerth, M.V.

1998-10-20

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation. 43 figs.

Resonant tunneling device with two-dimensional quantum well emitter and base layers

DOEpatents

Simmons, Jerry A.; Sherwin, Marc E.; Drummond, Timothy J.; Weckwerth, Mark V.

1998-01-01

A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Low-frequency switching in a transistor amplifier.

PubMed

Carroll, T L

2003-04-01

It is known from extensive work with the diode resonator that the nonlinear properties of a P-N junction can lead to period doubling, chaos, and other complicated behaviors in a driven circuit. There has been very little work on what happens when more than one P-N junction is present. In this work, the first step towards multiple P-N junction circuits is taken by doing both experiments and simulations with a single-transistor amplifier using a bipolar transistor. Period doubling and chaos are seen when the amplifier is driven with signals between 100 kHz and 1 MHz, and they coincide with a very low frequency switching between different period doubled (or chaotic) wave forms. The switching frequencies are between 5 and 10 Hz. The switching behavior was confirmed in a simplified model of the transistor amplifier.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Layer-dependent electrical and optoelectronic responses of ReSe2 nanosheet transistors.

PubMed

Yang, Shengxue; Tongay, Sefaattin; Li, Yan; Yue, Qu; Xia, Jian-Bai; Li, Shun-Shen; Li, Jingbo; Wei, Su-Huai

2014-07-07

The ability to control the appropriate layer thickness of transition metal dichalcogenides (TMDs) affords the opportunity to engineer many properties for a variety of applications in possible technological fields. Here we demonstrate that band-gap and mobility of ReSe2 nanosheet, a new member of the TMDs, increase when the layer number decreases, thus influencing the performances of ReSe2 transistors with different layers. A single-layer ReSe2 transistor shows much higher device mobility of 9.78 cm(2) V(-1) s(-1) than few-layer transistors (0.10 cm(2) V(-1) s(-1)). Moreover, a single-layer device shows high sensitivity to red light (633 nm) and has a light-improved mobility of 14.1 cm(2) V(-1) s(-1). Molecular physisorption is used as "gating" to modulate the carrier density of our single-layer transistors, resulting in a high photoresponsivity (Rλ) of 95 A W(-1) and external quantum efficiency (EQE) of 18 645% in O2 environment. This work highlights the fact that the properties of ReSe2 can be tuned in terms of the number of layers and gas molecule gating, and single-layer ReSe2 with appropriate band-gap is a promising material for future functional device applications.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vexler, M. I., E-mail: shulekin@mail.ioffe.ru; Grekhov, I. V.

The features of electron tunneling from or into the silicon valence band in a metal–insulator–semiconductor system with the HfO{sub 2}(ZrO{sub 2})/SiO{sub 2} double-layer insulator are theoretically analyzed for different modes. It is demonstrated that the valence-band current plays a less important role in structures with HfO{sub 2}(ZrO{sub 2})/SiO{sub 2} than in structures containing only silicon dioxide. In the case of a very wide-gap high-K oxide ZrO{sub 2}, nonmonotonic behavior related to tunneling through the upper barrier is predicted for the valence-band–metal current component. The use of an insulator stack can offer certain advantages for some devices, including diodes, bipolar tunnel-emittermore » transistors, and resonant-tunneling diodes, along with the traditional use of high-K insulators in a field-effect transistor.« less

Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion.

PubMed

Martí, A; Luque, A

2015-04-22

Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base-emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions.

Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion

PubMed Central

Martí, A.; Luque, A.

2015-01-01

Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base–emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions. PMID:25902374

Thickness-dependent electron mobility of single and few-layer MoS{sub 2} thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Ji Heon; Kim, Tae Ho; Lee, Hyunjea

We investigated the dependence of electron mobility on the thickness of MoS{sub 2} nanosheets by fabricating bottom-gate single and few-layer MoS{sub 2} thin-film transistors with SiO{sub 2} gate dielectrics and Au electrodes. All the fabricated MoS{sub 2} transistors showed on/off-current ratio of ∼10{sup 7} and saturated output characteristics without high-k capping layers. As the MoS{sub 2} thickness increased from 1 to 6 layers, the field-effect mobility of the fabricated MoS{sub 2} transistors increased from ∼10 to ∼18 cm{sup 2}V{sup −1}s{sup −1}. The increased subthreshold swing of the fabricated transistors with MoS{sub 2} thickness suggests that the increase of MoS{sub 2}more » mobility with thickness may be related to the dependence of the contact resistance and the dielectric constant of MoS{sub 2} layer on its thickness.« less

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer

PubMed Central

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-01-01

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm2/Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 105. Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles. PMID:27876893

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer.

PubMed

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; Kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-11-23

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O 2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm 2 /Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 10 5 . Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Channel length dependence of negative-bias-illumination-stress in amorphous-indium-gallium-zinc-oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2015-06-21

We have investigated the dependence of Negative-Bias-illumination-Stress (NBIS) upon channel length, in amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The negative shift of the transfer characteristic associated with NBIS decreases for increasing channel length and is practically suppressed in devices with L = 100-μm. The effect is consistent with creation of donor defects, mainly in the channel regions adjacent to source and drain contacts. Excellent agreement with experiment has been obtained by an analytical treatment, approximating the distribution of donors in the active layer by a double exponential with characteristic length L{sub D} ∼ L{sub n} ∼ 10-μm, the latter being the electron diffusion length. The model alsomore » shows that a device with a non-uniform doping distribution along the active layer is in all equivalent, at low drain voltages, to a device with the same doping averaged over the active layer length. These results highlight a new aspect of the NBIS mechanism, that is, the dependence of the effect upon the relative magnitude of photogenerated holes and electrons, which is controlled by the device potential/band profile. They may also provide the basis for device design solutions to minimize NBIS.« less

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Ambipolar insulator-to-metal transition in black phosphorus by ionic-liquid gating.

PubMed

Saito, Yu; Iwasa, Yoshihiro

2015-03-24

We report ambipolar transport properties in black phosphorus using an electric-double-layer transistor configuration. The transfer curve clearly exhibits ambipolar transistor behavior with an ON-OFF ratio of ∼5 × 10(3). The band gap was determined as ≅0.35 eV from the transfer curve, and Hall-effect measurements revealed that the hole mobility was ∼190 cm(2)/(V s) at 170 K, which is 1 order of magnitude larger than the electron mobility. By inducing an ultrahigh carrier density of ∼10(14) cm(-2), an electric-field-induced transition from the insulating state to the metallic state was realized, due to both electron and hole doping. Our results suggest that black phosphorus will be a good candidate for the fabrication of functional devices, such as lateral p-n junctions and tunnel diodes, due to the intrinsic narrow band gap.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Exceptionally High Electric Double Layer Capacitances of Oligomeric Ionic Liquids.

PubMed

Matsumoto, Michio; Shimizu, Sunao; Sotoike, Rina; Watanabe, Masayoshi; Iwasa, Yoshihiro; Itoh, Yoshimitsu; Aida, Takuzo

2017-11-15

Electric double layer (EDL) capacitors are promising as next-generation energy accumulators if their capacitances and operation voltages are both high. However, only few electrolytes can simultaneously fulfill these two requisites. Here we report that an oligomeric ionic liquid such as IL4 TFSI with four imidazolium ion units in its structure provides a wide electrochemical window of ∼5.0 V, similar to monomeric ionic liquids. Furthermore, electrochemical impedance measurements using Au working electrodes demonstrated that IL4 TFSI exhibits an exceptionally high EDL capacitance of ∼66 μF/cm 2 , which is ∼6 times as high as those of monomeric ionic liquids so far reported. We also found that an EDL-based field effect transistor (FET) using IL4 TFSI as a gate dielectric material and SrTiO 3 as a channel material displays a very sharp transfer curve with an enhanced carrier accumulation capability of ∼64 μF/cm 2 , as determined by Hall-effect measurements.

Extended-gate-type IGZO electric-double-layer TFT immunosensor with high sensitivity and low operation voltage

NASA Astrophysics Data System (ADS)

Liang, Lingyan; Zhang, Shengnan; Wu, Weihua; Zhu, Liqiang; Xiao, Hui; Liu, Yanghui; Zhang, Hongliang; Javaid, Kashif; Cao, Hongtao

2016-10-01

An immunosensor is proposed based on the indium-gallium-zinc-oxide (IGZO) electric-double-layer thin-film transistor (EDL TFT) with a separating extended gate. The IGZO EDL TFT has a field-effect mobility of 24.5 cm2 V-1 s-1 and an operation voltage less than 1.5 V. The sensors exhibit the linear current response to label-free target immune molecule in the concentrations ranging from 1.6 to 368 × 10-15 g/ml with a detection limit of 1.6 × 10-15 g/ml (0.01 fM) under an ultralow operation voltage of 0.5 V. The IGZO TFT component demonstrates a consecutive assay stability and recyclability due to the unique structure with the separating extended gate. With the excellent electrical properties and the potential for plug-in-card-type multifunctional sensing, extended-gate-type IGZO EDL TFTs can be promising candidates for the development of a label-free biosensor for public health applications.

Resonant and nondissipative tunneling in independently contacted graphene structures

NASA Astrophysics Data System (ADS)

Vasko, F. T.

2013-02-01

The tunneling processes between independently contacted graphene sheets separated by thin insulator are restricted by the momentum and energy conservation laws. Because of this, both dissipative tunneling transitions, with momentum transfer due to disorder scattering, and nondissipative regime of tunneling, which appears due to intersection of electron and hole branches of energy spectrum, must be taken into account. The tunneling current density is calculated for the graphene-boron nitride-graphene layers, which is described by the tight-binding approach, and for the predominant momentum scattering by static disorder. Dependencies of current on concentrations in top and bottom graphene layers, which are governed by the voltages applied through independent contacts and gates, are considered for the back- and double-gated structures. The current-voltage characteristics of the back-gated structure are in agreement with the recent experiment [ScienceSCIEAS0036-807510.1126/science.1218461 335, 947 (2012)]. For the double-gated structures, the resonant dissipative tunneling causes a 10-fold enhancement of response which is important for transistor applications.

Disorder from the Bulk Ionic Liquid in Electric Double Layer Transistors

DOE PAGES

Petach, Trevor A.; Reich, Konstantin V.; Zhang, Xiao; ...

2017-07-28

Ionic liquid gating has a number of advantages over solid-state gating, especially for flexible or transparent devices and for applications requiring high carrier densities. But, the large number of charged ions near the channel inevitably results in Coulomb scattering, which limits the carrier mobility in otherwise clean systems. We develop a model for this Coulomb scattering. We then validate our model experimentally using ionic liquid gating of graphene across varying thicknesses of hexagonal boron nitride, demonstrating that disorder in the bulk ionic liquid often dominates the scattering.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

High gain, low noise, fully complementary logic inverter based on bi-layer WSe{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Saptarshi; Roelofs, Andreas; Dubey, Madan

2014-08-25

In this article, first, we show that by contact work function engineering, electrostatic doping and proper scaling of both the oxide thickness and the flake thickness, high performance p- and n-type WSe{sub 2} field effect transistors (FETs) can be realized. We report record high drive current of 98 μA/μm for the electron conduction and 110 μA/μm for the hole conduction in Schottky barrier WSe{sub 2} FETs. Then, we combine high performance WSe{sub 2} PFET with WSe{sub 2} NFET in double gated transistor geometry to demonstrate a fully complementary logic inverter. We also show that by adjusting the threshold voltages for themore » NFET and the PFET, the gain and the noise margin of the inverter can be significantly enhanced. The maximum gain of our chemical doping free WSe{sub 2} inverter was found to be ∼25 and the noise margin was close to its ideal value of ∼2.5 V for a supply voltage of V{sub DD} = 5.0 V.« less

Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors

NASA Astrophysics Data System (ADS)

Vaziri, S.; Belete, M.; Dentoni Litta, E.; Smith, A. D.; Lupina, G.; Lemme, M. C.; Östling, M.

2015-07-01

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm-2 (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.

Improving yield and performance in ZnO thin-film transistors made using selective area deposition.

PubMed

Nelson, Shelby F; Ellinger, Carolyn R; Levy, David H

2015-02-04

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.

Integration of Indium Phosphide Based Devices with Flexible Substrates

NASA Astrophysics Data System (ADS)

Chen, Wayne Huai

2011-12-01

Flexible substrates have many advantages in applications where bendability, space, or weight play important roles or where rigid circuits are undesirable. However, conventional flexible thin film transistors are typically characterized as having low carrier mobility as compared to devices used in the electronics industry. This is in part due to the limited temperature tolerance of plastic flexible substrates, which commonly reduces the highest processing temperature to below 200°C. Common approaches of implementation include low temperature deposition of organic, amorphous, or polycrystalline semiconductors, all of which result in carrier mobility well below 100 cm2V -1s-1. High quality, single crystalline III-V semiconductors such as indium phosphide (InP), on the other hand, have carrier mobility well over 1000 cm 2V-1s-1 at room temperature, depending on carrier concentration. Recently, the ion-cut process has been used in conjunction with wafer bonding to integrate thin layers of III-V material onto silicon for optoelectronic applications. This approach has the advantage of high scalability, reusability of the initial III-V substrate, and the ability to tailor the location (depth) of the layer splitting. However, the transferred substrate usually suffers from hydrogen implantation damage. This dissertation demonstrates a new approach to enable integration of InP with various substrates, called the double-flip transfer process. The process combines ion-cutting with adhesive bonding. The problem of hydrogen implantation was overcome by patterned ion-cut transfer. In this type of transfer, areas of interest are shielded from implantation but still transferred by surrounding implanted regions. We found that patterned ion-cut transfer is strongly dependent upon crystal orientation and that using cleavage-plane oriented donors can be beneficial in transferring large areas of high quality semiconductor material. InP-based devices were fabricated to demonstrate the transfer process and test functionality following transfer. Passive devices (photodetectors) as well as active transistors were transferred and fabricated on various substrates. The transferred device layers were either implanted through with a blanket implant or protected with an ion-mask during implantation. Results demonstrate the viability of the double-flip ion-cut process in achieving very high electron mobility (˜2800 cm2V-1s-1) transistors on plastic flexible substrates.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Chemically assembled double-dot single-electron transistor analyzed by the orthodox model considering offset charge

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kano, Shinya; Maeda, Kosuke; Majima, Yutaka, E-mail: majima@msl.titech.ac.jp

2015-10-07

We present the analysis of chemically assembled double-dot single-electron transistors using orthodox model considering offset charges. First, we fabricate chemically assembled single-electron transistors (SETs) consisting of two Au nanoparticles between electroless Au-plated nanogap electrodes. Then, extraordinary stable Coulomb diamonds in the double-dot SETs are analyzed using the orthodox model, by considering offset charges on the respective quantum dots. We determine the equivalent circuit parameters from Coulomb diamonds and drain current vs. drain voltage curves of the SETs. The accuracies of the capacitances and offset charges on the quantum dots are within ±10%, and ±0.04e (where e is the elementary charge),more » respectively. The parameters can be explained by the geometrical structures of the SETs observed using scanning electron microscopy images. Using this approach, we are able to understand the spatial characteristics of the double quantum dots, such as the relative distance from the gate electrode and the conditions for adsorption between the nanogap electrodes.« less

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

pH-sensitive ion-selective field-effect transistor with zirconium dioxide film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vlasov, Yu.G.; Bratov, A.V.; Tarantov, Yu.A.

1988-09-20

Miniature semiconductor pH sensors for liquid media, i.e., ion-selective field-effect transistors (ISFETs), are silicon field-effect transistors with a two-layer dielectric consisting of a passivating SiO/sub 2/ layer adjoining the silicon and a layer of pH-sensitive material in contact with the electrolyte solution to be tested. This study was devoted to the characteristics of pH-sensitive ISFETs with ZrO/sub 2/ films. The base was p-type silicon (KDB-10) with a (100) surface orientation. A ZrO/sub 2/ layer 10-50 nm thick was applied over the SiO/sub 2/ layer by electron-beam deposition. The measurements were made in aqueous KNO/sub 3/ or KCl solutions.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Stacking fault induced tunnel barrier in platelet graphite nanofiber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lan, Yann-Wen, E-mail: chiidong@phys.sinica.edu.tw, E-mail: ywlan@phys.sinica.edu.tw; Chang, Yuan-Chih; Chang, Chia-Seng

A correlation study using image inspection and electrical characterization of platelet graphite nanofiber devices is conducted. Close transmission electron microscopy and diffraction pattern inspection reveal layers with inflection angles appearing in otherwise perfectly stacked graphene platelets, separating nanofibers into two domains. Electrical measurement gives a stability diagram consisting of alternating small-large Coulomb blockade diamonds, suggesting that there are two charging islands coupled together through a tunnel junction. Based on these two findings, we propose that a stacking fault can behave as a tunnel barrier for conducting electrons and is responsible for the observed double-island single electron transistor characteristics.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS₂ Transistors.

PubMed

Ma, Jiyeon; Yoo, Geonwook

2018-09-01

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

PubMed

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Investigation of Electronic and Opto-Electronic Properties of Two-Dimensional (2D) Layers of Copper Indium Selenide Field Effect Transistors

NASA Astrophysics Data System (ADS)

Patil, Prasanna Dnyaneshwar

Investigations performed in order to understand the electronic and optoelectronic properties of field effect transistors based on few layers of 2D Copper Indium Selenide (CuIn7Se11) are reported. In general, field effect transistors (FETs), electric double layer field effect transistors (EDL-FETs), and photodetectors are crucial part of several electronics based applications such as tele-communication, bio-sensing, and opto-electronic industry. After the discovery of graphene, several 2D semiconductor materials like TMDs (MoS2, WS2, and MoSe2 etc.), group III-VI materials (InSe, GaSe, and SnS2 etc.) are being studied rigorously in order to develop them as components in next generation FETs. Traditionally, thin films of ternary system of Copper Indium Selenide have been extensively studied and used in optoelectronics industry as photoactive component in solar cells. Thus, it is expected that atomically thin 2D layered structure of Copper Indium Selenide can have optical properties that could potentially be more advantageous than its thin film counterpart and could find use for developing next generation nano devices with utility in opto/nano electronics. Field effect transistors were fabricated using few-layers of CuIn7Se11 flakes, which were mechanically exfoliated from bulk crystals grown using chemical vapor transport technique. Our FET transport characterization measurements indicate n-type behavior with electron field effect mobility microFE ≈ 36 cm2 V-1 s-1 at room temperature when Silicon dioxide (SiO2) is used as a back gate. We found that in such back gated field effect transistor an on/off ratio of 104 and a subthreshold swing ≈ 1 V/dec can be obtained. Our investigations further indicate that Electronic performance of these materials can be increased significantly when gated from top using an ionic liquid electrolyte [1-Butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF6)]. We found that electron field effect mobility microFE can be increased from 3 cm2 V-1 s-11 in SiO2 back gated device to 18 cm2 V-1 s-11 in top gated electrolyte devices. Similarly, subthreshold swing can be improved from 30 V/dec to 0.2 V/dec and on/off ratio can be increased from 102 to 103 by using an electrolyte as a top gate. These FETs were also tested as phototransistors. Our photo-response characterization indicate photo-responsivity 32 A/W with external quantum efficiency exceeding 103 % when excited with a 658 nm wavelength laser at room temperature. Our phototransistor also exhibit response times tens of micros with specific detectivity (D*) values reaching 1012 Jones. The CuIn7Se11 phototransistor properties can be further tuned & enhanced by applying a back gate voltage along with increased source drain bias. For example, photo-responsivity can gain substantial improvement up to 320 A/W upon application of a gate voltage (Vg = 30 V) and/or increased source-drain bias. The photo-responsivity exhibited by these photo detectors are at least an order of magnitude better than commercially available conventional Si based photo detectors coupled with response times that are orders of magnitude better than several other family of layered materials investigated so far. Further photocurrent generation mechanisms, effect of traps is discussed in detail.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Erofeev, E. V., E-mail: erofeev@micran.ru; Fedin, I. V.; Kutkov, I. V.

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping levelmore » makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.« less

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Fabrication of Organic Thin Film Transistors Using Layer-By-Layer Assembly (Preprint)

DTIC Science & Technology

2007-03-01

thin-film transistors ( TFTs ) have received considerable attention as a low- cost, light-weight, flexible alternative to traditional amorphous silicon...Previous studies have investigated the use of a number of materials for both the active layer and the gate dielectric in various TFT architectures. These...performance. Conjugated small molecules, such as pentacene, or polymers, such as poly(3- hexylthiophene), are commonly used as the active layer in organic TFT

Solving the integration problem of one transistor one memristor architecture with a Bi-layer IGZO film through synchronous process

NASA Astrophysics Data System (ADS)

Chang, Che-Chia; Liu, Po-Tsun; Chien, Chen-Yu; Fan, Yang-Shun

2018-04-01

This study demonstrates the integration of a thin film transistor (TFT) and resistive random-access memory (RRAM) to form a one-transistor-one-resistor (1T1R) configuration. With the concept of the current conducting direction in RRAM and TFT, a triple-layer stack design of Pt/InGaZnO/Al2O3 is proposed for both the switching layer of RRAM and the channel layer of TFT. This proposal decreases the complexity of fabrication and the numbers of photomasks required. Also, the robust endurance and stable retention characteristics are exhibited by the 1T1R architecture for promising applications in memory-embedded flat panel displays.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

NASA Astrophysics Data System (ADS)

Shao, Jinhai; Deng, Jianan; Lu, W.; Chen, Yifang

2017-07-01

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

A gallium phosphide high-temperature bipolar junction transistor

NASA Technical Reports Server (NTRS)

Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

1981-01-01

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Applications of Nanostructured Graphene in Optoelectronics as Transparent Conductors and Photodetectors

NASA Astrophysics Data System (ADS)

Xu, Guowei

Graphene, a single layer of carbon atoms arranged in a hexagonal lattice, has unique properties of high carrier mobility, high optical transmittance, chemical inertness and flexibility, making it attractive for electronic and optoelectronic applications, such as graphene transistors, ultrahigh capacitors, transparent conductors (TCs), photodetectors. This work explores novel schemes of nanostructured graphene for optoelectronic applications including advanced TCs and photodetectors. In nanophotonic graphene nanohole arrays patterned using nanoimprinting lithography (NIL), highly efficient chemical doping was achieved on the hole edges. This provides a unique scheme for improving both optical transmittance and electrical conductivity of graphene-based TCs. In plasmonic graphene, Ag nanoparticles were decorated on graphene using thermally assisted self-assembly and NIL. Much enhanced conductivity by a factor of 2-4 was achieved through electron doping in graphene from Ag nanoparticles. More importantly, surface plasmonic effect has been incorporated into plasmonic graphene as advanced TCs with light trapping, which is critical to ultrathin-film optoelectronics such as photovoltaics and photodetectors. Based on plasmonic graphene electric double-layer (EDL) transistor, a novel scheme of photodetection has been demonstrated using plasmonic enhanced local field gating. The resulting tuning of interfacial capacitance as well as the quantum capacitance of graphene manifested as extraordinary photoconductivity and hence photoresponse.

Polarization induced doped transistor

DOEpatents

Xing, Huili; Jena, Debdeep; Nomoto, Kazuki; Song, Bo; Zhu, Mingda; Hu, Zongyang

2016-06-07

A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

PubMed

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

PubMed Central

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

In-depth analysis and modelling of self-heating effects in nanometric DGMOSFETs

NASA Astrophysics Data System (ADS)

Roldán, J. B.; González, B.; Iñiguez, B.; Roldán, A. M.; Lázaro, A.; Cerdeira, A.

2013-01-01

Self-heating effects (SHEs) in nanometric symmetrical double-gate MOSFETs (DGMOSFETs) have been analysed. An equivalent thermal circuit for the transistors has been developed to characterise thermal effects, where the temperature and thickness dependency of the thermal conductivity of the silicon and oxide layers within the devices has been included. The equivalent thermal circuit is consistent with simulations using a commercial technology computer-aided design (TCAD) tool (Sentaurus by Synopsys). In addition, a model for DGMOSFETs has been developed where SHEs have been considered in detail, taking into account the temperature dependence of the low-field mobility, saturation velocity, and inversion charge. The model correctly reproduces Sentaurus simulation data for the typical bias range used in integrated circuits. Lattice temperatures predicted by simulation are coherently reproduced by the model for varying silicon layer geometry.

Correlation between active layer thickness and ambient gas stability in IGZO thin-film transistors

NASA Astrophysics Data System (ADS)

Gao, Xu; Lin, Meng-Fang; Mao, Bao-Hua; Shimizu, Maki; Mitoma, Nobuhiko; Kizu, Takio; Ou-Yang, Wei; Nabatame, Toshihide; Liu, Zhi; Tsukagoshi, Kazuhito; Wang, Sui-Dong

2017-01-01

Decreasing the active layer thickness has been recently reported as an alternative way to achieve fully depleted oxide thin-film transistors for the realization of low-voltage operations. However, the correlation between the active layer thickness and device resistivity to environmental changes is still unclear, which is important for the optimized design of oxide thin-film transistors. In this work, the ambient gas stability of IGZO thin-film transistors is found to be strongly correlated to the IGZO thickness. The TFT with the thinnest IGZO layer shows the highest intrinsic electron mobility in a vacuum, which is greatly reduced after exposure to O2/air. The device with a thick IGZO layer shows similar electron mobility in O2/air, whereas the mobility variation measured in the vacuum is absent. The thickness dependent ambient gas stability is attributed to a high-mobility region in the IGZO surface vicinity with less sputtering-induced damage, which will become electron depleted in O2/air due to the electron transfer to adsorbed gas molecules. The O2 adsorption and deduced IGZO surface band bending is demonstrated by the ambient-pressure x-ray photoemission spectroscopy results.

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Vertical field-effect transistor based on wave-function extension

NASA Astrophysics Data System (ADS)

Sciambi, A.; Pelliccione, M.; Lilly, M. P.; Bank, S. R.; Gossard, A. C.; Pfeiffer, L. N.; West, K. W.; Goldhaber-Gordon, D.

2011-08-01

We demonstrate a mechanism for a dual layer, vertical field-effect transistor, in which nearly depleting one layer will extend its wave function to overlap the other layer and increase tunnel current. We characterize this effect in a specially designed GaAs/AlGaAs device, observing a tunnel current increase of two orders of magnitude at cryogenic temperatures, and we suggest extrapolations of the design to other material systems such as graphene.

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

NASA Technical Reports Server (NTRS)

Kim, Jae-Hoon; Lin, Steven H.

1991-01-01

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

Modeling of high composition AlGaN channel high electron mobility transistors with large threshold voltage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bajaj, Sanyam, E-mail: bajaj.10@osu.edu; Hung, Ting-Hsiang; Akyol, Fatih

2014-12-29

We report on the potential of high electron mobility transistors (HEMTs) consisting of high composition AlGaN channel and barrier layers for power switching applications. Detailed two-dimensional (2D) simulations show that threshold voltages in excess of 3 V can be achieved through the use of AlGaN channel layers. We also calculate the 2D electron gas mobility in AlGaN channel HEMTs and evaluate their power figures of merit as a function of device operating temperature and Al mole fraction in the channel. Our models show that power switching transistors with AlGaN channels would have comparable on-resistance to GaN-channel based transistors for the samemore » operation voltage. The modeling in this paper shows the potential of high composition AlGaN as a channel material for future high threshold enhancement mode transistors.« less

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

PubMed

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques

NASA Technical Reports Server (NTRS)

Policastro, Steven G. (Inventor); Woo, Dae-Shik (Inventor)

1983-01-01

A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeluri, Ramya, E-mail: ramyay@ece.ucsb.edu; Lu, Jing; Keller, Stacia

2015-05-04

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm{sup 2}) and low ON-resistance (0.4 mΩ cm{sup 2}) are demonstrated. Non-planar selective area regrowth is identified as the limiting factormore » to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities.« less

Electrical in-situ characterisation of interface stabilised organic thin-film transistors

PubMed Central

Striedinger, Bernd; Fian, Alexander; Petritz, Andreas; Lassnig, Roman; Winkler, Adolf; Stadlober, Barbara

2015-01-01

We report on the electrical in-situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom-gate/bottom-contact (coplanar) configuration are electrically characterised in-situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO2 with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor parameters is studied on a bi-layer dielectric of a 150 nm of SiO2 and 20 nm of poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO2 dielectric. The thin layer of PNDPE, which is an intrinsically photo-patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. PMID:26457122

Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

NASA Astrophysics Data System (ADS)

Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

2016-05-01

The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

High-Performance All 2D-Layered Tin Disulfide: Graphene Photodetecting Transistors with Thickness-Controlled Interface Dynamics.

PubMed

Chang, Ren-Jie; Tan, Haijie; Wang, Xiaochen; Porter, Benjamin; Chen, Tongxin; Sheng, Yuewen; Zhou, Yingqiu; Huang, Hefu; Bhaskaran, Harish; Warner, Jamie H

2018-04-18

Tin disulfide crystals with layered two-dimensional (2D) sheets are grown by chemical vapor deposition using a novel precursor approach and integrated into all 2D transistors with graphene (Gr) electrodes. The Gr:SnS 2 :Gr transistors exhibit excellent photodetector response with high detectivity and photoresponsivity. We show that the response of the all 2D photodetectors depends upon charge trapping at the interface and the Schottky barrier modulation. The thickness-dependent SnS 2 measurements in devices reveal a transition from the interface-dominated response for thin crystals to bulklike response for the thicker SnS 2 crystals, showing the sensitivity of devices fabricated using layered materials on the number of layers. These results show that SnS 2 has photosensing performance when combined with Gr electrodes that is comparable to other 2D transition metal dichalcogenides of MoS 2 and WS 2 .

Biosensor properties of SOI nanowire transistors with a PEALD Al{sub 2}O{sub 3} dielectric protective layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Popov, V. P., E-mail: popov@isp.nsc.ru; Ilnitskii, M. A.; Zhanaev, E. D.

2016-05-15

The properties of protective dielectric layers of aluminum oxide Al{sub 2}O{sub 3} applied to prefabricated silicon-nanowire transistor biochips by the plasma enhanced atomic layer deposition (PEALD) method before being housed are studied depending on the deposition and annealing modes. Coating the natural silicon oxide with a nanometer Al{sub 2}O{sub 3} layer insignificantly decreases the femtomole sensitivity of biosensors, but provides their stability in bioliquids. In deionized water, transistors with annealed aluminum oxide are closed due to the trapping of negative charges of <(1–10) × 10{sup 11} cm{sup −2} at surface states. The application of a positive potential to the substratemore » (V{sub sub} > 25 V) makes it possible to eliminate the negative charge and to perform multiple measurements in liquid at least for half a year.« less

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Microscopic properties of ionic liquid/organic semiconductor interfaces revealed by molecular dynamics simulations.

PubMed

Yokota, Yasuyuki; Miyamoto, Hiroo; Imanishi, Akihito; Takeya, Jun; Inagaki, Kouji; Morikawa, Yoshitada; Fukui, Ken-Ichi

2018-05-09

Electric double-layer transistors based on ionic liquid/organic semiconductor interfaces have been extensively studied during the past decade because of their high carrier densities at low operation voltages. Microscopic structures and the dynamics of ionic liquids likely determine the device performance; however, knowledge of these is limited by a lack of appropriate experimental tools. In this study, we investigated ionic liquid/organic semiconductor interfaces using molecular dynamics to reveal the microscopic properties of ionic liquids. The organic semiconductors include pentacene, rubrene, fullerene, and 7,7,8,8-tetracyanoquinodimethane (TCNQ). While ionic liquids close to the substrate always form the specific layered structures, the surface properties of organic semiconductors drastically alter the ionic dynamics. Ionic liquids at the fullerene interface behave as a two-dimensional ionic crystal because of the energy gain derived from the favorable electrostatic interaction on the corrugated periodic substrate.

Solution-processed zinc oxide nanoparticles/single-walled carbon nanotubes hybrid thin-film transistors

NASA Astrophysics Data System (ADS)

Liu, Fangmei; Sun, Jia; Qian, Chuan; Hu, Xiaotao; Wu, Han; Huang, Yulan; Yang, Junliang

2016-09-01

Solution-processed thin-film transistors (TFTs) are the essential building blocks for manufacturing the low-cost and large-area consumptive electronics. Herein, solution-processed TFTs based on the composites of zinc oxide (ZnO) nanoparticles and single-walled carbon nanotubes (SWCNTs) were fabricated by the methods of spin-coating and doctor-blading. Through controlling the weight of SWCNTs, the ZnO/SWCNTs TFTs fabricated by spin-coating demonstrated a field-effect mobility of 4.7 cm2/Vs and a low threshold voltage of 0.8 V, while the TFTs devices fabricated by doctor-blading technique showed reasonable electrical performance with a mobility of 0.22 cm2/Vs. Furthermore, the ion-gel was used as an efficient electrochemical gate dielectric because of its large electric double-layer capacitance. The operating voltage of all the TFTs devices is as low as 4.0 V. The research suggests that ZnO/SWCNTs TFTs have the potential applications in low-cost, large-area and flexible consumptive electronics, such as chemical-biological sensors and smart label.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Rapid detection of cardiac troponin I using antibody-immobilized gate-pulsed AlGaN/GaN high electron mobility transistor structures

NASA Astrophysics Data System (ADS)

Yang, Jiancheng; Carey, Patrick; Ren, Fan; Wang, Yu-Lin; Good, Michael L.; Jang, Soohwan; Mastro, Michael A.; Pearton, S. J.

2017-11-01

We report a comparison of two different approaches to detecting cardiac troponin I (cTnI) using antibody-functionalized AlGaN/GaN High Electron Mobility Transistors (HEMTs). If the solution containing the biomarker has high ionic strength, there can be difficulty in detection due to charge-screening effects. To overcome this, in the first approach, we used a recently developed method involving pulsed biases applied between a separate functionalized electrode and the gate of the HEMT. The resulting electrical double layer produces charge changes which are correlated with the concentration of the cTnI biomarker. The second approach fabricates the sensing area on a glass slide, and the pulsed gate signal is externally connected to the nitride HEMT. This produces a larger integrated change in charge and can be used over a broader range of concentrations without suffering from charge-screening effects. Both approaches can detect cTnI at levels down to 0.01 ng/ml. The glass slide approach is attractive for inexpensive cartridge-type sensors.

Efficient Defect Engineering for Solution Combustion Processed In-Zn-O thin films for high performance transistors

NASA Astrophysics Data System (ADS)

Liang, Xiaoci; Wang, Chengcai; Liang, Jun; Liu, Chuan; Pei, Yanli

2017-09-01

The oxygen related defects in the solution combustion-processed InZnO vitally affect the field-effect mobility and on-off characteristics in thin film transistors (TFTs). We use photoelectron spectroscopy to reveal that these defects can be well controlled by adjusting the atmosphere and flow rate during the combustion reaction, but are hardly affected by further post-annealing after the reaction. In device performance, the threshold voltage of the InZnO-TFTs was regulated in a wide range from 3.5 V to 11.0 V. To compromise the high field-effect mobility and good subthreshold properties, we fabricate the TFTs with double active layers of InZnO to achieve vertical gradience in defect distribution. The resulting TFT exhibits much higher field-effect mobility as 17.5 cm2 · V-1 · s-1, a low reversed sub-threshold slope as 0.35 V/decade, and a high on-off ratio as 107. The presented understandings and methods on defect engineering are efficient in improving the device performance of TFTs made from the combustion reaction process.

Gate-tunable gigantic changes in lattice parameters and optical properties in VO2

NASA Astrophysics Data System (ADS)

Nakano, Masaki; Okuyama, Daisuke; Shibuya, Keisuke; Ogawa, Naoki; Hatano, Takafumi; Kawasaki, Masashi; Arima, Taka-Hisa; Iwasa, Yoshihiro; Tokura, Yoshinori

2014-03-01

The field-effect transistor provides an electrical switching function of current flowing through a channel surface by external gate voltage (VG). We recently reported that an electric-double-layer transistor (EDLT) based on vanadium dioxide (VO2) enables electrical switching of the metal-insulator phase transition, where the low-temperature insulating state can be completely switched to the metallic state by application of VG. Here we demonstrate that VO2-EDLT enables electrical switching of lattice parameters and optical properties as well as electrical current. We performed in-situ x-ray diffraction and optical transmission spectroscopy measurements, and found that the c-axis length and the infrared transmittance of VO2 can be significantly modulated by more than 1% and 40%, respectively, by application of VG. We emphasize that these distinguished features originate from the electric-field induced bulk phase transition available with VO2-EDLT. This work was supported by the Japan Society for the Promotion of Science (JSPS) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

High performance photolithographically-patterned polymer thin-film transistors gated with an ionic liquid/poly(ionic liquid) blend ion gel

NASA Astrophysics Data System (ADS)

Thiburce, Q.; Porcarelli, L.; Mecerreyes, D.; Campbell, A. J.

2017-06-01

We demonstrate the fabrication of polymer thin-film transistors gated with an ion gel electrolyte made of the blend of an ionic liquid and a polymerised ionic liquid. The ion gel exhibits a high stability and ionic conductivity, combined with facile processing by simple drop-casting from solution. In order to avoid parasitic effects such as high hysteresis, high off-currents, and slow switching, a fluorinated photoresist is employed in order to enable high-resolution orthogonal patterning of the polymer semiconductor over an area that precisely defines the transistor channel. The resulting devices exhibit excellent characteristics, with an on/off ratio of 106, low hysteresis, and a very large transconductance of 3 mS. We show that this high transconductance value is mostly the result of ions penetrating the polymer film and doping the entire volume of the semiconductor, yielding an effective capacitance per unit area of about 200 μF cm-2, one order of magnitude higher than the double layer capacitance of the ion gel. This results in channel currents larger than 1 mA at an applied gate bias of only -1 V. We also investigate the dynamic performance of the devices and obtain a switching time of 20 ms, which is mostly limited by the overlap capacitance between the ion gel and the source and drain contacts.

High Performance and Highly Reliable ZnO Thin Film Transistor Fabricated by Atomic Layer Deposition for Next Generation Displays

DTIC Science & Technology

2011-08-19

zinc oxide ( ZnO ) thin film as an active channel layer in TFT has become of great interest owing to their specific...630-0192 Japan Phone: +81-743-72-6060 Fax: +81-743-72-6069 E-mail: uraoka@ms.naist.jp Keywords: zinc oxide , thin film transistors , atomic layer...deposition Symposium topic: Transparent Semiconductors Oxides [Abstract] In this study, we fabricated TFTs using ZnO thin film as the

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A. (Inventor)

1991-01-01

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Electronics Devices and Materials

DTIC Science & Technology

2008-03-17

Molecular -bea epitaxy MCNPX ............... Software code Misse6 ................. Satellite expected to carry ORMatE-I Misse7...patterning using electron beam lithography), spaces (class 1000 clean benches), and skills (appropriate mix of skilled technicians and professionals...34 Process samples for various projects such as Antimode Base High Electron Mobility Transistors ( HEMT ) and Double Heterojuction Bipolar Transistors

Modeling of short channel MOS transistors

NASA Technical Reports Server (NTRS)

Lin, H. C.; Kokalis, D. P.; Bandy, W. R.

1976-01-01

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer

NASA Astrophysics Data System (ADS)

Jiménez Tejada, Juan A.; Lopez-Varo, Pilar; Chaure, Nandu B.; Chambrier, Isabelle; Cammidge, Andrew N.; Cook, Michael J.; Jafari-Fini, Ali; Ray, Asim K.

2018-03-01

70 nm thick solution-processed films of a palladium phthalocyanine (PdPc6) derivative bearing eight hexyl (-C6H13) chains at non-peripheral positions have been employed as active layers in the fabrication of bottom-gate bottom-contact organic thin film transistors (OTFTs) deposited on highly doped p-type Si (110) substrates with SiO2 gate dielectric. The dependence of the transistor electrical performance upon the mesophase behavior of the PdPc6 films has been investigated by measuring the output and transfer characteristics of the OTFT having its active layer ex situ vacuum annealed at temperatures between 500 °C and 200 °C. A clear correlation between the annealing temperature and the threshold voltage and carrier mobility of the transistors, and the transition temperatures extracted from the differential scanning calorimetric curves for bulk materials has been established. This direct relation has been obtained by means of a compact electrical model in which the contact effects are taken into account. The precise determination of the contact-voltage drain-current curves allows for obtaining such a relation.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change inmore » drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.« less

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

NASA Astrophysics Data System (ADS)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Phase transition transistors based on strongly-correlated materials

NASA Astrophysics Data System (ADS)

Nakano, Masaki

2013-03-01

The field-effect transistor (FET) provides electrical switching functions through linear control of the number of charges at a channel surface by external voltage. Controlling electronic phases of condensed matters in a FET geometry has long been a central issue of physical science. In particular, FET based on a strongly correlated material, namely ``Mott transistor,'' has attracted considerable interest, because it potentially provides gigantic and diverse electronic responses due to a strong interplay between charge, spin, orbital and lattice. We have investigated electric-field effects on such materials aiming at novel physical phenomena and electronic functions originating from strong correlation effects. Here we demonstrate electrical switching of bulk state of matter over the first-order metal-insulator transition. We fabricated FETs based on VO2 with use of a recently developed electric-double-layer transistor technique, and found that the electrostatically induced carriers at a channel surface drive all preexisting localized carriers of 1022 cm-3 even inside a bulk to motion, leading to bulk carrier delocalization beyond the electrostatic screening length. This non-local switching of bulk phases is achieved with just around 1 V, and moreover, a novel non-volatile memory like character emerges in a voltage-sweep measurement. These observations are apparently distinct from those of conventional FETs based on band insulators, capturing the essential feature of collective interactions in strongly correlated materials. This work was done in collaboration with K. Shibuya, D. Okuyama, T. Hatano, S. Ono, M. Kawasaki, Y. Iwasa, and Y. Tokura. This work was supported by the Japan Society for the Promotion of Science (JSAP) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

Highly stable thin film transistors using multilayer channel structure

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, D. H.; Hedhili, M. N.; Alshareef, H. N.

2015-03-01

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO2) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured at room temperature and at 60 °C. A tremendous improvement in gate-bias stress stability was obtained in case of the TFT with multiple layers of ZnO embedded between HfO2 layers compared to the TFT with a single layer of ZnO as the semiconductor. The ultra-thin HfO2 layers act as passivation layers, which prevent the adsorption of oxygen and water molecules in the ZnO layer and hence significantly improve the gate-bias stress stability of ZnO TFTs.

Bi-layer Channel AZO/ZnO Thin Film Transistors Fabricated by Atomic Layer Deposition Technique

NASA Astrophysics Data System (ADS)

Li, Huijin; Han, Dedong; Liu, Liqiao; Dong, Junchen; Cui, Guodong; Zhang, Shengdong; Zhang, Xing; Wang, Yi

2017-03-01

This letter demonstrates bi-layer channel Al-doped ZnO/ZnO thin film transistors (AZO/ZnO TFTs) via atomic layer deposition process at a relatively low temperature. The effects of annealing in oxygen atmosphere at different temperatures have also been investigated. The ALD bi-layer channel AZO/ZnO TFTs annealed in dry O2 at 300 °C exhibit a low leakage current of 2.5 × 10-13A, I on/ I off ratio of 1.4 × 107, subthreshold swing (SS) of 0.23 V/decade, and high transmittance. The enhanced performance obtained from the bi-layer channel AZO/ZnO TFT devices is explained by the inserted AZO front channel layer playing the role of the mobility booster.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Artificial semiconductor/insulator superlattice channel structure for high-performance oxide thin-film transistors

PubMed Central

Ahn, Cheol Hyoun; Senthil, Karuppanan; Cho, Hyung Koun; Lee, Sang Yeol

2013-01-01

High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers. PMID:24061388

Unstable Resonator Mid-Infrared Laser Sources

DTIC Science & Technology

2016-02-26

of individual materials depending on metal species and growth temperatures . Fig. 8 (a) Average power consumption and (b) delay of C2MOS and double...feedback lasers, chirped gratings, interferometric lithography, nanowire transistors, tunnel field- effect transistors, nanoscale epitaxial growth, nanowire...technical approaches. Approaches to wavelength tuning include thermal/operation temperature tuning [1], variable cavity length with cantilever/piezo

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

DOEpatents

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

PubMed

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

Anisotropy of the upper critical field and its thickness dependence in superconducting FeSe electric-double-layer transistors

NASA Astrophysics Data System (ADS)

Shiogai, Junichi; Kimura, Shojiro; Awaji, Satoshi; Nojima, Tsutomu; Tsukazaki, Atsushi

2018-05-01

Anisotropy of superconductivity is one of the fundamental physical parameters for understanding layered iron-based superconductors (IBSs). Here we investigated the anisotropic response of resistive transition as a function of thickness (d ) in iron selenide (FeSe) based electric-double-layer transistors (EDLTs) on SrTi O3 , which exhibit superconducting transition temperatures Tc as high as 40 K below d =10 nm . According to the analyses of the in-plane (Hc2 //) and out-of-plane (Hc2 ⊥) upper critical fields (Hc 2) and the magnetic field angle dependence of the resistance (Rs-θ ) in ultrathin condition, we found that the anisotropy factor ɛ0=Hc2 ///Hc2 ⊥ is 7.4 in the thin limit of d ˜1 nm , which is larger than that of bulk IBSs. In addition, we observed the shorter out-of-plane coherence length ξc of 0.19 nm compared to the c -axis lattice constant, which implies the confinement of the order parameter in the one unit cell FeSe. These findings suggest that high-Tc superconductivity in the ultrathin FeSe-EDLT exhibits an anisotropic three-dimensional (3D) or quasi-two-dimensional (2D) nature rather than the pure 2D one, leading to the robust superconductivity. Moreover, we carried out the systematic evaluation of the anisotropic Hc 2 against thickness reduction in the FeSe channel. The in-plane Hc 2 as a function of normalized temperature T /Tc is almost independent of d until the thin limit condition. On the other hand, the out-of-plane Hc 2 near T /Tc˜1 decreases with increasing d , resulting in the increase of ɛ0 at around Tc to 32.0 at the thick condition of d =9.3 nm , which is also confirmed by Rs-θ measurements. The counterintuitive behavior can be attributed to the degree of coupling strength between two electron-rich layers possessing a high superconducting order parameter induced by electrostatic gating at the top interface and charge transfer from SrTi O3 substrates at the bottom interface. Besides a large Hc2 ⊥ for d =9.3 nm exceeding 20 T even at T =0.8 Tc , we observe the decoupling crossover of the two superconducting layers at low temperature, which is a unique feature for the high-Tc FeSe-EDLT on SrTi O3 .

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1987-06-08

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

Ester-free cross-linker molecules for ultraviolet-light-cured polysilsesquioxane gate dielectric layers of organic thin-film transistors

NASA Astrophysics Data System (ADS)

Okada, Shuichi; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2018-04-01

Pentacene thin-film transistors (TFTs) were fabricated with ultraviolet-light (UV)-cured polysilsesquioxane (PSQ) gate dielectric layers using cross-linker molecules with or without ester groups. To polymerize PSQ without ester groups, thiol-ene reaction was adopted. The TFTs fabricated with PSQ layers comprising ester-free cross-linkers showed a higher carrier mobility than the TFTs with PSQ layers cross-linked with ester groups, which had large electric dipole moments that limited the carrier mobility. It was demonstrated that the thiol-ene reaction is more suitable than the conventional radical reaction for UV-cured PSQ with small dielectric constant.

Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

PubMed Central

Yu, Woo Jong; Li, Zheng; Zhou, Hailong; Chen, Yu; Wang, Yang; Huang, Yu; Duan, Xiangfeng

2014-01-01

The layered materials such as graphene have attracted considerable interest for future electronics. Here we report the vertical integration of multi-heterostructures of layered materials to enable high current density vertical field-effect transistors (VFETs). An n-channel VFET is created by sandwiching few-layer molybdenum disulfide (MoS2) as the semiconducting channel between a monolayer graphene and a metal thin film. The VFETs exhibit a room temperature on-off ratio >103, while at same time deliver a high current density up to 5,000 A/cm2, sufficient for high performance logic applications. This study offers a general strategy for the vertical integration of various layered materials to obtain both p- and n-channel transistors for complementary logic functions. A complementary inverter with larger than unit voltage gain is demonstrated by vertically stacking the layered materials of graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel), and metal thin film in sequence. The ability to simultaneously achieve high on-off ratio, high current density, and logic integration in the vertically stacked multi-heterostructures can open up a new dimension for future electronics to enable three-dimensional integration. PMID:23241535

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Increased mobility and on/off ratio in organic field-effect transistors using low-cost guanine-pentacene multilayers

NASA Astrophysics Data System (ADS)

Shi, Wei; Zheng, Yifan; Taylor, André D.; Yu, Junsheng; Katz, Howard E.

2017-07-01

Layer-by-layer deposited guanine and pentacene in organic field-effect transistors (OFETs) is introduced. Through adjusting the layer thickness ratio of guanine and pentacene, the tradeoff of two electronic parameters in OFETs, charge carrier mobility and current on/off ratio, was controlled. The charge mobility was enhanced by depositing pentacene over and between guanine layers and by increasing the proportion of pentacene in the layer-by-layer system, while the current on/off ratio was increased via the decreased off current induced by the guanine layers. The tunable device performance was mainly ascribed to the trap and dopant neutralizing properties of the guanine layers, which would decrease the density of free hydroxyl groups in the OFETs. Furthermore, the cost of the devices could be reduced remarkably via the adoption of low-cost guanine.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

Organic electrical double layer transistors gated with ionic liquids

NASA Astrophysics Data System (ADS)

Xie, Wei; Frisbie, C. Daniel

2011-03-01

Transport in organic semiconductors gated with several types of ionic liquids has been systematically studied at charge densities larger than 1013 cm-2 . We observe a pronounced maximum in channel conductance for both p-type and n-type organic single crystals which is attributed to carrier localization at the semiconductor-electrolyte interface. Carrier mobility, as well as charge density and dielectric capacitance are determined through displacement current measurement and capacitance-voltage measurement. By using a larger-sized and spherical anion, tris(pentafluoroethyl)trifluorophosphate (FAP), effective carrier mobility in rubrene can be enhanced substantially up to 3.2 cm2 V-1 s -1 . Efforts have been made to maximize the charge density in rubrene single crystals, and at low temperature when higher gate bias can be applied, charge density can more than double the amount of that at room temperature, reaching 8*1013 cm-2 holes (0.4 holes per rubrene molecule). NSF MRSEC program at the University of Minnesota.

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

PubMed

Kunc, Jan; Hu, Yike; Palmer, James; Guo, Zelei; Hankinson, John; Gamal, Salah H; Berger, Claire; de Heer, Walt A

2014-09-10

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

Highly Crystalline C8-BTBT Thin-Film Transistors by Lateral Homo-Epitaxial Growth on Printed Templates.

PubMed

Janneck, Robby; Pilet, Nicolas; Bommanaboyena, Satya Prakash; Watts, Benjamin; Heremans, Paul; Genoe, Jan; Rolin, Cedric

2017-11-01

Highly crystalline thin films of organic semiconductors offer great potential for fundamental material studies as well as for realizing high-performance, low-cost flexible electronics. The fabrication of these films directly on inert substrates is typically done by meniscus-guided coating techniques. The resulting layers show morphological defects that hinder charge transport and induce large device-to-device variability. Here, a double-step method for organic semiconductor layers combining a solution-processed templating layer and a lateral homo-epitaxial growth by a thermal evaporation step is reported. The epitaxial regrowth repairs most of the morphological defects inherent to meniscus-guided coatings. The resulting film is highly crystalline and features a mobility increased by a factor of three and a relative spread in device characteristics improved by almost half an order of magnitude. This method is easily adaptable to other coating techniques and offers a route toward the fabrication of high-performance, large-area electronics based on highly crystalline thin films of organic semiconductors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Schottky barrier contrasts in single and bi-layer graphene contacts for MoS{sub 2} field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Du, Hyewon; Kim, Taekwang; Shin, Somyeong

We have investigated single- and bi-layer graphene as source-drain electrodes for n-type MoS{sub 2} transistors. Ti-MoS{sub 2}-graphene heterojunction transistors using both single-layer MoS{sub 2} (1M) and 4-layer MoS{sub 2} (4M) were fabricated in order to compare graphene electrodes with commonly used Ti electrodes. MoS{sub 2}-graphene Schottky barrier provided electron injection efficiency up to 130 times higher in the subthreshold regime when compared with MoS{sub 2}-Ti, which resulted in V{sub DS} polarity dependence of device parameters such as threshold voltage (V{sub TH}) and subthreshold swing (SS). Comparing single-layer graphene (SG) with bi-layer graphene (BG) in 4M devices, SG electrodes exhibited enhancedmore » device performance with higher on/off ratio and increased field-effect mobility (μ{sub FE}) due to more sensitive Fermi level shift by gate voltage. Meanwhile, in the strongly accumulated regime, we observed opposing behavior depending on MoS{sub 2} thickness for both SG and BG contacts. Differential conductance (σ{sub d}) of 1M increases with V{sub DS} irrespective of V{sub DS} polarity, while σ{sub d} of 4M ceases monotonic growth at positive V{sub DS} values transitioning to ohmic-like contact formation. Nevertheless, the low absolute value of σ{sub d} saturation of the 4M-graphene junction demonstrates that graphene electrode could be unfavorable for high current carrying transistors.« less

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

AlN metal-semiconductor field-effect transistors using Si-ion implantation

NASA Astrophysics Data System (ADS)

Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

2018-04-01

We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

2016-09-01

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

Effects of V2O5/Au bi-layer electrodes on the top contact Pentacene-based organic thin film transistors

NASA Astrophysics Data System (ADS)

Borthakur, Tribeni; Sarma, Ranjit

2017-05-01

Top-contact Pentacene-based organic thin film transistors (OTFTs) with a thin layer of Vanadium Pent-oxide between Pentacene and Au layer are fabricated. Here we have found that the devices with V2O5/Au bi-layer source-drain electrode exhibit better field-effect mobility, high on-off ratio, low threshold voltage and low sub-threshold slope than the devices with Au only. The field-effect mobility, current on-off ratio, threshold voltage and sub-threshold slope of V2O5/Au bi-layer OTFT estimated from the device with 15 nm thick V2O5 layer is .77 cm2 v-1 s-1, 7.5×105, -2.9 V and .36 V/decade respectively.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

PubMed

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer

NASA Astrophysics Data System (ADS)

Chong, Eugene; Kim, Bosul; Lee, Sang Yeol

2012-04-01

A silicon-indium-zinc-oxide (SIZO) thin film transistor (TFT) with low channel-resistance (RCH) indium-zinc-oxide (In2O3:ZnO = 9:1) buried layer annealed at low temperature of 200°C exhibited high field-effect mobility (μFE) over 55.8 cm2/V·s which is 5 times higher than that of the conventional TFTs due to small threshold voltage (Vth) change of 1.8 V under bias-temperature stress (BTS) condition for 420 minutes. The low-RCH buried-layer allows more strong current-path formed in channel layer well within relatively high-RCH channel-layer since it is less affected by the channel bulk and/or back interface trap with high carrier concentration.

Performance improvement of organic thin film transistors by using active layer with sandwich structure

NASA Astrophysics Data System (ADS)

Ni, Yao; Zhou, Jianlin; Kuang, Peng; Lin, Hui; Gan, Ping; Hu, Shengdong; Lin, Zhi

2017-08-01

We report organic thin film transistors (OTFTs) with pentacene/fluorinated copper phthalo-cyanine (F16CuPc)/pentacene (PFP) sandwich configuration as active layers. The sandwich devices not only show hole mobility enhancement but also present a well control about threshold voltage and off-state current. By investigating various characteristics, including current-voltage hysteresis, organic film morphology, capacitance-voltage curve and resistance variation of active layers carefully, it has been found the performance improvement is mainly attributed to the low carrier traps and the higher conductivity of the sandwich active layer due to the additional induced carriers in F16CuPc/pentacene. Therefore, using proper multiple active layer is an effective way to gain high performance OTFTs.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Bi-layer Channel AZO/ZnO Thin Film Transistors Fabricated by Atomic Layer Deposition Technique.

PubMed

Li, Huijin; Han, Dedong; Liu, Liqiao; Dong, Junchen; Cui, Guodong; Zhang, Shengdong; Zhang, Xing; Wang, Yi

2017-12-01

This letter demonstrates bi-layer channel Al-doped ZnO/ZnO thin film transistors (AZO/ZnO TFTs) via atomic layer deposition process at a relatively low temperature. The effects of annealing in oxygen atmosphere at different temperatures have also been investigated. The ALD bi-layer channel AZO/ZnO TFTs annealed in dry O 2 at 300 °C exhibit a low leakage current of 2.5 × 10 -13 A, I on /I off ratio of 1.4 × 10 7 , subthreshold swing (SS) of 0.23 V/decade, and high transmittance. The enhanced performance obtained from the bi-layer channel AZO/ZnO TFT devices is explained by the inserted AZO front channel layer playing the role of the mobility booster.

Light emission from organic single crystals operated by electrolyte doping

NASA Astrophysics Data System (ADS)

Matsuki, Keiichiro; Sakanoue, Tomo; Yomogida, Yohei; Hotta, Shu; Takenobu, Taishi

2018-03-01

Light-emitting devices based on electrolytes, such as light-emitting electrochemical cells (LECs) and electric double-layer transistors (EDLTs), are solution-processable devices with a very simple structure. Therefore, it is necessary to apply this device structure into highly fluorescent organic materials for future printed applications. However, owing to compatibility problems between electrolytes and organic crystals, electrolyte-based single-crystal light-emitting devices have not yet been demonstrated. Here, we report on light-emitting devices based on organic single crystals and electrolytes. As the fluorescent materials, α,ω-bis(biphenylyl)terthiophene (BP3T) and 5,6,11,12-tetraphenylnaphthacene (rubrene) single crystals were selected. Using ionic liquids as electrolytes, we observed clear light emission from BP3T LECs and rubrene EDLTs.

Induced-charge electroosmotic trapping of particles.

PubMed

Ren, Yukun; Liu, Weiyu; Jia, Yankai; Tao, Ye; Shao, Jinyou; Ding, Yucheng; Jiang, Hongyuan

2015-05-21

Position-controllable trapping of particles on the surface of a bipolar metal strip by induced-charge electroosmotic (ICEO) flow is presented herein. We demonstrate a nonlinear ICEO slip profile on the electrode surface accounting for stable particle trapping behaviors above the double-layer relaxation frequency, while no trapping occurs in the DC limit as a result of a strong upward fluidic drag induced by a linear ICEO slip profile. By extending an AC-flow field effect transistor from the DC limit to the AC field, we reveal that fixed-potential ICEO exceeding RC charging frequency can adjust the particle trapping position flexibly by generating controllable symmetry breaking in a vortex flow pattern. Our results open up new opportunities to manipulate microscopic objects in modern microfluidic systems by using ICEO.

A solid dielectric gated graphene nanosensor in electrolyte solutions.

PubMed

Zhu, Yibo; Wang, Cheng; Petrone, Nicholas; Yu, Jaeeun; Nuckolls, Colin; Hone, James; Lin, Qiao

2015-03-23

This letter presents a graphene field effect transistor (GFET) nanosensor that, with a solid gate provided by a high- κ dielectric, allows analyte detection in liquid media at low gate voltages. The gate is embedded within the sensor and thus is isolated from a sample solution, offering a high level of integration and miniaturization and eliminating errors caused by the liquid disturbance, desirable for both in vitro and in vivo applications. We demonstrate that the GFET nanosensor can be used to measure pH changes in a range of 5.3-9.3. Based on the experimental observations and quantitative analysis, the charging of an electrical double layer capacitor is found to be the major mechanism of pH sensing.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

Enhanced electrical properties of dual-layer channel ZnO thin film transistors prepared by atomic layer deposition

NASA Astrophysics Data System (ADS)

Li, Huijin; Han, Dedong; Dong, Junchen; Yu, Wen; Liang, Yi; Luo, Zhen; Zhang, Shengdong; Zhang, Xing; Wang, Yi

2018-05-01

The thin film transistors (TFTs) with a dual-layer channel structure combing ZnO thin layer grown at 200 °C and ZnO film grown at 120 °C by atomic layer deposition are fabricated. The dual-layer channel TFT exhibits a low leakage current of 2.8 × 10-13 A, Ion/Ioff ratio of 3.4 × 109, saturation mobility μsat of 12 cm2 V-1 s-1, subthreshold swing (SS) of 0.25 V/decade. The SS value decreases to 0.18 V/decade after the annealing treatment in O2 due to the reduction of the trap states at the channel/dielectric interface and in the bulk channel layer. The enhanced performance obtained from the dual-layer channel TFTs is due to the ability of maintaining high mobility and suppressing the increase in the off-current at the same time.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene-carbon nanotube transistors

NASA Astrophysics Data System (ADS)

Chae, Sang Hoon; Yu, Woo Jong; Bae, Jung Jun; Duong, Dinh Loc; Perello, David; Jeong, Hye Yun; Ta, Quang Huy; Ly, Thuc Hue; Vu, Quoc An; Yun, Minhee; Duan, Xiangfeng; Lee, Young Hee

2013-05-01

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10-13 A. The resulting devices exhibited an excellent on/off ratio of ~105, a high mobility of ~40 cm2 V-1 s-1 and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

PubMed

Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

2016-07-20

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Lin, Wei-Chun; Chen, Hao-Wei

2018-06-01

This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Interface engineering and solid-state organization for triindole-based p-type organic thin-film transistors.

PubMed

Reig, Marta; Bagdziunas, Gintautas; Ramanavicius, Arunas; Puigdollers, Joaquim; Velasco, Dolores

2018-06-21

Inspired by the excellent device performance of triindole-based semiconductors in electronic and optoelectronic devices, the relationship between the solid-state organization and the charge-transporting properties of an easily accessible series of triindole derivatives is reported herein. The vacuum-evaporated organic thin-film transistors (OTFTs) exhibited a non ideal behaviour with a double slope in the saturation curves. Moreover, the treatment of the gate insulator of the OTFT device with either a self-assembled monolayer (SAM) or a polymer controls the molecular growth and the film morphology of the semiconducting layer, as shown by X-ray diffraction (XRD) analyses, atomic force microscopy (AFM) and theoretical calculations. N-Trihexyltriindole exhibited the best device performance with hole mobilities up to 0.1 cm2 V-1 s-1 at the low VG range and up to 0.01 cm2 V-1 s-1 at high VG, as well as enhanced Ion/Ioff ratios of around 106. The results suggest that the non-ideal behaviour of the here studied OTFT devices could be related to the higher interfacial disorder in comparison to that in the bulk.

Interface-Dependent Effective Mobility in Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Ahlberg, Patrik; Hinnemo, Malkolm; Zhang, Shi-Li; Olsson, Jörgen

2018-03-01

By pretreating the substrate of a graphene field-effect transistor (G-FET), a stable unipolar transfer characteristic, instead of the typical V-shape ambipolar behavior, has been demonstrated. This behavior is achieved through functionalization of the SiO2/Si substrate that changes the SiO2 surface from hydrophilic to hydrophobic, in combination with postdeposition of an Al2O3 film by atomic layer deposition (ALD). Consequently, the back-gated G-FET is found to have increased apparent hole mobility and suppressed apparent electron mobility. Furthermore, with addition of a top-gate electrode, the G-FET is in a double-gate configuration with independent top- or back-gate control. The observed difference in mobility is shown to also be dependent on the top-gate bias, with more pronounced effect at higher electric field. Thus, the combination of top and bottom gates allows control of the G-FET's electron and hole mobilities, i.e., of the transfer behavior. Based on these observations, it is proposed that polar ligands are introduced during the ALD step and, depending on their polarization, result in an apparent increase of the effective hole mobility and an apparent suppressed effective electron mobility.

Monolithic 20W 2GHz Transistor and Monolithic 5W 4GHz Transistor.

DTIC Science & Technology

1979-02-01

epitaxial material of better quality than has been obtained from outside vendors . Ini tial tests indicate that the intrinsic material grown in our...system exceeds 800~ —cm , which is at least twice the value required . Also , the correct substrate material will be used and the N buried layer will...be the correct resistivity and thickness. The N layer will also be deposited somewhat thinner than the exist- ing material to reduce the collector

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

PubMed Central

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Heterostructured semiconductor single-walled carbon nanotube films for solution-processed high-performance field-effect transistors

NASA Astrophysics Data System (ADS)

Park, Noh-Hwal; Lee, Seung-Hoon; Jeong, Seung-Hyeon; Khim, Dongyoon; Kim, Yun Ho; Yoo, Sungmi; Noh, Yong-Young; Kim, Jang-Joo

2018-03-01

In this paper, we report a simple and effective method to simultaneously achieve a high charge-carrier mobility and low off current in conjugated polymer-wrapped semiconducting single-walled carbon nanotube (s-SWNT) transistors by applying a SWNT bilayer. To achieve the high mobility and low off current, highly purified and less purified s-SWNTs are successively coated to form the semiconducting layer consisting of poly (3-dodecylthiophene-2,5-diyl) (P3DDT)-wrapped high-pressure carbon mono oxide (HiPCO) SWNT (P3DDT-HiPCO) and poly (9, 9-di-n-dodecylfluorene) (PFDD)-wrapped plasma discharge (PD) SWNT (PFDD-PD). The SWNT transistors with bilayer SWNT networked film showed highly improved hole field-effect mobility (6.18 ± 0.85 cm2V-1s-1 average), on/off current ratio (107), and off current (˜1 pA). Thus, the combination of less purified PFDD-PD (98%-99%) charge-injection layer and highly purified s-P3DDT-HiPCO (>99%) charge-transport layer as the bi-layered semiconducting film achieved high mobility and low off current simultaneously.

Selective UV–O3 treatment for indium zinc oxide thin film transistors with solution-based multiple active layer

NASA Astrophysics Data System (ADS)

Kim, Yu-Jung; Jeong, Jun-Kyo; Park, Jung-Hyun; Jeong, Byung-Jun; Lee, Hi-Deok; Lee, Ga-Won

2018-06-01

In this study, a method to control the electrical performance of solution-based indium zinc oxide (IZO) thin film transistors (TFTs) is proposed by ultraviolet–ozone (UV–O3) treatment on the selective layer during multiple IZO active layer depositions. The IZO film is composed of triple layers formed by spin coating and UV–O3 treatment only on the first layer or last layer. The IZO films are compared by X-ray photoelectron spectroscopy, and the results show that the atomic ratio of oxygen vacancy (VO) increases in the UV–O3 treatment on the first layer, while it decreases on last layer. The device characteristics of the bottom gated structure are also improved in the UV–O3 treatment on the first layer. This indicates that the selective UV–O3 treatment in a multi-stacking active layer is an effective method to optimize TFT properties by controlling the amount of VO in the IZO interface and surface independently.

Lateral carrier diffusion and current gain in terahertz InGaAs/InP double-heterojunction bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Han-Wei; Rode, Johann C.; Choudhary, Prateek

2014-01-21

The DC current gain in In{sub 0.53}Ga{sub 0.47}As/InP double-heterojunction bipolar transistors is computed based on a drift-diffusion model, and is compared with experimental data. Even in the absence of other scaling effects, lateral diffusion of electrons to the base Ohmic contacts causes a rapid reduction in DC current gain as the emitter junction width and emitter-base contact spacing are reduced. The simulation and experimental data are compared in order to examine the effect of carrier lateral diffusion on current gain. The impact on current gain due to device scaling and approaches to increase current gain are discussed.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

Lateral electrochemical etching of III-nitride materials for microfabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Han, Jung

Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

NASA Astrophysics Data System (ADS)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Electronic transport properties of inner and outer shells in near ohmic-contacted double-walled carbon nanotube transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Yuchun; Zhou, Liyan; Zhao, Shangqian

2014-06-14

We investigate electronic transport properties of field-effect transistors based on double-walled carbon nanotubes, of which inner shells are metallic and outer shells are semiconducting. When both shells are turned on, electron-phonon scattering is found to be the dominant phenomenon. On the other hand, when outer semiconducting shells are turned off, a zero-bias anomaly emerges in the dependence of differential conductance on the bias voltage, which is characterized according to the Tomonaga-Luttinger liquid model describing tunneling into one-dimensional materials. We attribute these behaviors to different contact conditions for outer and inner shells of the double-walled carbon nanotubes. A simple model combiningmore » Luttinger liquid model for inner metallic shells and electron-phonon scattering in outer semiconducting shells is given here to explain our transport data at different temperatures.« less

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

NASA Astrophysics Data System (ADS)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Tang, Fengzai; Lee, Kean B.; Guiney, Ivor; Frentrup, Martin; Barnard, Jonathan S.; Divitini, Giorgio; Zaidi, Zaffar H.; Martin, Tomas L.; Bagot, Paul A.; Moody, Michael P.; Humphreys, Colin J.; Houston, Peter A.; Oliver, Rachel A.; Wallis, David J.

2018-01-01

We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

NASA Astrophysics Data System (ADS)

Bhuvaneshwari, Y. V.; Kranti, Abhinav

2017-12-01

In this work, we use the modified McLarty function to understand and extract accumulation (μ acc) and bulk (μ bulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (N d) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ 1 and θ 2) by a single method. The extracted results indicate that μ acc can reach higher values than μ bulk due to the screening effect. Results also show that θ 2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ 1) in JL devices designed with higher N d (≥1019 cm-3) is mainly affected by series resistance (R sd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ 1 factor is governed by both the intrinsic mobility reduction factor (θ 10) and R sd. Additionally, the impact of variation in oxide thickness (T ox), gate length (L g), N d and temperature on θ 1 and θ 2 has been investigated for JL transistor. The weak dependence of μ bulk and μ acc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Solution-processable alumina: PVP nanocomposite dielectric layer for high-performance organic thin-film transistors

NASA Astrophysics Data System (ADS)

Lin, Hui; Kong, Xiao; Li, Yiran; Kuang, Peng; Tao, Silu

2018-03-01

In this article, we have investigated the effect of nanocomposite gate dielectric layer built by alumina (Al2O3) and poly(4-vinyphenol) (PVP) with solution method which could enhance the dielectric capability and decrease the surface polarity. Then, we used modify layer to optimize the surface morphology of dielectric layer to further improve the insulation capability, and finally we fabricated the high-performance and low-voltage organic thin-film transistors by using this nanocomposite dielectric layer. The result shows that the devices with Al2O3:10%PVP dielectric layer with a modified layer exhibited a mobility of 0.49 cm2/Vs, I on/Ioff ratio of 7.8 × 104, threshold voltage of - 1.2 V, sub-threshold swing of 0.3 V/dec, and operating voltage as low as - 4 V. The improvement of devices performance was owing to the good insulation capability, appropriate capacitance of dielectric layer, and preferable interface contact, smaller crystalline size of active layer.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

A delta-doped amorphous silicon thin-film transistor with high mobility and stability

NASA Astrophysics Data System (ADS)

Kim, Pyunghun; Lee, Kyung Min; Lee, Eui-Wan; Jo, Younjung; Kim, Do-Hyung; Kim, Hong-jae; Yang, Key Young; Son, Hyunji; Choi, Hyun Chul

2012-12-01

Ultrathin doped layers, known as delta-doped layers, were introduced within the intrinsic amorphous silicon (a-Si) active layer to fabricate hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with enhanced field-effect mobility. The performance of the delta-doped a-Si:H TFTs depended on the phosphine (PH3) flow rate and the distance from the n+ a-Si to the deltadoping layer. The delta-doped a-Si:H TFTs fabricated using a commercial manufacturing process exhibited an enhanced field-effect mobility of approximately ˜0.23 cm2/Vs (compared to a conventional a-Si:H TFT with 0.15 cm2/Vs) and a desirable stability under a bias-temperature stress test.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

More Efficient Power Conversion for EVs: Gallium-Nitride Advanced Power Semiconductor and Packaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-02-01

Broad Funding Opportunity Announcement Project: Delphi is developing power converters that are smaller and more energy efficient, reliable, and cost-effective than current power converters. Power converters rely on power transistors which act like a very precisely controlled on-off switch, controlling the electrical energy flowing through an electrical circuit. Most power transistors today use silicon (Si) semiconductors. However, Delphi is using semiconductors made with a thin layer of gallium-nitride (GaN) applied on top of the more conventional Si material. The GaN layer increases the energy efficiency of the power transistor and also enables the transistor to operate at much higher temperatures,more » voltages, and power-density levels compared to its Si counterpart. Delphi is packaging these high-performance GaN semiconductors with advanced electrical connections and a cooling system that extracts waste heat from both sides of the device to further increase the device’s efficiency and allow more electrical current to flow through it. When combined with other electronic components on a circuit board, Delphi’s GaN power transistor package will help improve the overall performance and cost-effectiveness of HEVs and EVs.« less

Compositional tuning of atomic layer deposited MgZnO for thin film transistors

NASA Astrophysics Data System (ADS)

Wrench, J. S.; Brunell, I. F.; Chalker, P. R.; Jin, J. D.; Shaw, A.; Mitrovic, I. Z.; Hall, S.

2014-11-01

Thin film transistors (TFTs) have been fabricated using magnesium zinc oxide (MgZnO) layers deposited by atomic layer deposition at 200 °C. The composition of the MgZnO is systematically modified by varying the ratio of MgO and ZnO deposition cycles. A blue-shift of the near band-edge photoluminescence after post-deposition annealing at 300 °C indicates significant activation of the Mg dopant. A 7:1 ratio of ZnO:MgO deposition cycles was used to fabricate a device with a TFT channel width of 2000 μm and a channel length of 60 μm. This transistor yielded an effective saturation mobility of 4 cm2/V s and a threshold voltage of 7.1 V, respectively. The on/off ratio was 1.6 × 10 6 and the maximum interface state density at the ZnO/SiO2 interface is ˜ 6.5 × 10 12 cm-2.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition.

PubMed

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-12-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al 2 O 3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a , which can explain the experimental observation. A high-field effect mobility of 9.4 cm 2 /Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 10 7 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-01-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al2O3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a, which can explain the experimental observation. A high-field effect mobility of 9.4 cm2/Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 107 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

Remarkable reduction in the threshold voltage of pentacene-based thin film transistors with pentacene/CuPc sandwich configuration

NASA Astrophysics Data System (ADS)

Li, Yi; Liu, Qi; Cai, Jing; Li, Yun; Shi, Yi; Wang, Xizhang; Hu, Zheng

2014-06-01

This study investigates the remarkable reduction in the threshold voltage (VT) of pentacene-based thin film transistors with pentacene/copper phthalocyanine (CuPc) sandwich configuration. This reduction is accompanied by increased mobility and lowered sub-threshold slope (S). Sandwich devices coated with a 5 nm layer of CuPc layer are compared with conventional top-contact devices, and results indicate that VT decreased significantly from -20.4 V to -0.2 V, that mobility increased from 0.18 cm2/Vs to 0.51 cm2/Vs, and that S was reduced from 4.1 V/dec to 2.9 V/dec. However, the on/off current ratio remains at 105. This enhanced performance could be attributed to the reduction in charge trap density by the incorporated CuPc layer. Results suggest that this method is simple and effectively generates pentacene-based organic thin film transistors with high mobility and low VT.

Heteroepitaxial growth of In{sub 0.30}Ga{sub 0.70}As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kohen, David, E-mail: david.kohen@asm.com; Nguyen, Xuan Sang; Made, Riko I

We report on the growth of an In{sub 0.30}Ga{sub 0.70}As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 10{sup 7} cm{sup −2} with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with I{sub DS} of 70more » μA/μm and g{sub m} of above 60 μS/μm, demonstrating the high quality of the grown materials.« less

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, K.H.

1998-06-30

A method is disclosed for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates. 1 fig.

Method for producing silicon thin-film transistors with enhanced forward current drive

DOEpatents

Weiner, Kurt H.

1998-01-01

A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon. A device made by this method can be used, for example, as a pixel switch in an active-matrix liquid crystal display to improve display refresh rates.

P-type field effect transistor based on Na-doped BaSnO3

NASA Astrophysics Data System (ADS)

Jang, Yeaju; Hong, Sungyun; Park, Jisung; Char, Kookrin

We fabricated field effect transistors (FET) based on the p-type Na-doped BaSnO3 (BNSO) channel layer. The properties of epitaxial BNSO channel layer were controlled by the doping rate. In order to modulate the p-type FET, we used amorphous HfOx and epitaxial BaHfO3 (BHO) gate oxides, both of which have high dielectric constants. HfOx was deposited by atomic-layer-deposition and BHO was epitaxially grown by pulsed laser deposition. The pulsed laser deposited SrRuO3 (SRO) was used as the source and the drain contacts. Indium-tin oxide and La-doped BaSnO3 were used as the gate electrodes on top of the HfOx and the BHO gate oxides, respectively. We will analyze and present the performances of the BNSO field effect transistor such as the IDS-VDS, the IDS-VGS, the Ion/Ioff ratio, and the field effect mobility. Samsung Science and Technology Foundation.

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

NASA Astrophysics Data System (ADS)

Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-11-01

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to silicon for potentiometric biosensing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Won Lee, Sang; Suh, Dongseok, E-mail: energy.suh@skku.edu; Department of Energy Science and Department of Physics, Sungkyunkwan University, Suwon 440-746

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO{sub 2}/Si. Gate bias stress stability was investigated with various passivation layers of HfO{sub 2} and Al{sub 2}O{sub 3}. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO{sub 2} under positive gate bias stress (PGBS). Al{sub 2}O{sub 3} capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO{submore » 2} layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.« less

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Enhancement of ambipolar characteristics in single-walled carbon nanotubes using C{sub 60} and fabrication of logic gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, Steve; Nam, Ji Hyun; Koo, Ja Hoon

2015-03-09

We demonstrate a technique to convert p-type single-walled carbon nanotube (SWNT) network transistor into ambipolar transistor by thermally evaporating C{sub 60} on top. The addition of C{sub 60} was observed to have two effects in enhancing ambipolar characteristics. First, C{sub 60} served as an encapsulating layer that enhanced the ambipolar characteristics of SWNTs. Second, C{sub 60} itself served as an electron transporting layer that contributed to the n-type conduction. Such a dual effect enables effective conversion of p-type into ambipolar characteristics. We have fabricated inverters using our SWNT/C{sub 60} ambipolar transistors with gain as high as 24, along with adaptivemore » NAND and NOR logic gates.« less

On Practical Charge Injection at the Metal/Organic Semiconductor Interface

PubMed Central

Kumatani, Akichika; Li, Yun; Darmawan, Peter; Minari, Takeo; Tsukagoshi, Kazuhito

2013-01-01

We have revealed practical charge injection at metal and organic semiconductor interface in organic field effect transistor configurations. We have developed a facile interface structure that consisted of double-layer electrodes in order to investigate the efficiency through contact metal dependence. The metal interlayer with few nanometers thickness between electrode and organic semiconductor drastically reduces the contact resistance at the interface. The improvement has clearly obtained when the interlayer is a metal with lower standard electrode potential of contact metals than large work function of the contact metals. The electrode potential also implies that the most dominant effect on the mechanism at the contact interface is induced by charge transfer. This mechanism represents a step forward towards understanding the fundamental physics of intrinsic charge injection in all organic devices. PMID:23293741

Effect of organic buffer layer in the electrical properties of amorphous-indium gallium zinc oxide thin film transistor.

PubMed

Wang, Jian-Xun; Hyung, Gun Woo; Li, Zhao-Hui; Son, Sung-Yong; Kwon, Sang Jik; Kim, Young Kwan; Cho, Eou Sik

2012-07-01

In this research, we reported on the fabrication of top-contact amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with an organic buffer layer between inorganic gate dielectric and active layer in order to improve the electrical properties of devices. By inserting an organic buffer layer, it was possible to make an affirmation of the improvements in the electrical characteristics of a-IGZO TFTs such as subthreshold slope (SS), on/off current ratio (I(ON/OFF)), off-state current, and saturation field-effect mobility (muFE). The a-IGZO TFTs with the cross-linked polyvinyl alcohol (c-PVA) buffer layer exhibited the pronounced improvements of the muFE (17.4 cm2/Vs), SS (0.9 V/decade), and I(ON/OFF) (8.9 x 10(6)).

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, deceased, Roger J.; Dawson, Ralph; Fritz, Ian J.; Osbourn, Gordon C.; Zipperian, Thomas E.

1989-01-01

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

pn-Heterojunction effects of perylene tetracarboxylic diimide derivatives on pentacene field-effect transistor.

PubMed

Yu, Seong Hun; Kang, Boseok; An, Gukil; Kim, BongSoo; Lee, Moo Hyung; Kang, Moon Sung; Kim, Hyunjung; Lee, Jung Heon; Lee, Shichoon; Cho, Kilwon; Lee, Jun Young; Cho, Jeong Ho

2015-01-28

We investigated the heterojunction effects of perylene tetracarboxylic diimide (PTCDI) derivatives on the pentacene-based field-effect transistors (FETs). Three PTCDI derivatives with different substituents were deposited onto pentacene layers and served as charge transfer dopants. The deposited PTCDI layer, which had a nominal thickness of a few layers, formed discontinuous patches on the pentacene layers and dramatically enhanced the hole mobility in the pentacene FET. Among the three PTCDI molecules tested, the octyl-substituted PTCDI, PTCDI-C8, provided the most efficient hole-doping characteristics (p-type) relative to the fluorophenyl-substituted PTCDIs, 4-FPEPTC and 2,4-FPEPTC. The organic heterojunction and doping characteristics were systematically investigated using atomic force microscopy, 2D grazing incidence X-ray diffraction studies, and ultraviolet photoelectron spectroscopy. PTCDI-C8, bearing octyl substituents, grew laterally on the pentacene layer (2D growth), whereas 2,4-FPEPTC, with fluorophenyl substituents, underwent 3D growth. The different growth modes resulted in different contact areas and relative orientations between the pentacene and PTCDI molecules, which significantly affected the doping efficiency of the deposited adlayer. The differences between the growth modes and the thin-film microstructures in the different PTCDI patches were attributed to a mismatch between the surface energies of the patches and the underlying pentacene layer. The film-morphology-dependent doping effects observed here offer practical guidelines for achieving more effective charge transfer doping in thin-film transistors.

Electronic nanobiosensors based on two-dimensional materials

NASA Astrophysics Data System (ADS)

Ping, Jinglei

Atomically-thick two-dimensional (2D) nanomaterials have tremendous potential to be applied as transduction elements in biosensors and bioelectronics. We developed scalable methods for synthesis and large-area transfer of two-dimensional nanomaterials, particularly graphene and metal dichalcogenides (so called ``MX2'' materials). We also developed versatile fabrication methods for large arrays of field-effect transistors (FETs) and micro-electrodes with these nanomaterials based on either conventional photolithography or innovative approaches that minimize contamination of the 2D layer. By functionalizing the FETs with a computationally redesigned water-soluble mu-opioid receptor, we created selective and sensitive biosensors suitable for detection of the drug target naltrexone and the neuropeptide enkephalin at pg/mL concentrations. We also constructed DNA-functionalized biosensors and nano-particle decorated biosensors by applying related bio-nano integration techniques. Our methodology paves the way for multiplexed nanosensor arrays with all-electronic readout suitable for inexpensive point-of-care diagnostics, drug-development and biomedical research. With graphene field-effect transistors, we investigated the graphene/solution interface and developed a quantitative model for the effect of ionic screening on the graphene carrier density based on theories of the electric double layer. Finally, we have developed a technique for measuring low-level Faradaic charge-transfer current (fA) across the graphene/solution interface via real-time charge monitoring of graphene microelectrodes in ionic solution. This technique enables the development of flexible and transparent pH sensors that are promising for in vivo applications. The author acknowledges the support from the Defense Advanced Research Projects Agency (DARPA) and the U. S. Army Research Office under Grant Number W911NF1010093.

Long-Term Reliability of High Speed SiGe/Si Heterojunction Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ponchak, George E. (Technical Monitor); Bhattacharya, Pallab

2003-01-01

Accelerated lifetime tests were performed on double-mesa structure Si/Si0.7Ge0.3/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175C-275C. Both single- and multiple finger transistors were tested. The single-finger transistors (with 5x20 micron sq m emitter area) have DC current gains approximately 40-50 and f(sub T) and f(sub MAX) of up to 22 GHz and 25 GHz, respectively. The multiple finger transistors (1.4 micron finger width, 9 emitter fingers with total emitter area of 403 micron sq m) have similar DC current gain but f(sub T) of 50 GHz. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REID has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of the devices at room temperature is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation. SiGe/Si based amplifier circuits were also subjected to lifetime testing and we extrapolate MTTF is approximately 1.1_10(exp 6) hours at 125iC junction temperature from the circuit lifetime data.

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2016-12-01

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

Double Layers in Astrophysics

NASA Technical Reports Server (NTRS)

Williams, Alton C. (Editor); Moorehead, Tauna W. (Editor)

1987-01-01

Topics addressed include: laboratory double layers; ion-acoustic double layers; pumping potential wells; ion phase-space vortices; weak double layers; electric fields and double layers in plasmas; auroral double layers; double layer formation in a plasma; beamed emission from gamma-ray burst source; double layers and extragalactic jets; and electric potential between plasma sheet clouds.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps

PubMed Central

Mei, Yaochuan; Diemer, Peter J.; Niazi, Muhammad R.; Hallani, Rawad K.; Jarolimek, Karol; Day, Cynthia S.; Risko, Chad; Anthony, John E.; Amassian, Aram

2017-01-01

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms. PMID:28739934

Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators

NASA Astrophysics Data System (ADS)

Kishida, Ryo; Furuta, Jun; Kobayashi, Kazutoshi

2018-04-01

Plasma-induced damage (PID) and bias temperature instability (BTI) are inevitable reliability issues that degrade the performance of transistors. In this study, PID and BTI, depending on the type of antenna layer, are evaluated in current-starved ring oscillators (ROs) to separate degradations in PMOS and NMOS transistors in a 65 nm silicon-on-insulator (SOI) process. Oscillation frequencies of ROs fluctuate with the performance of MOSFET switches between power/ground rails and virtual power/ground nodes. The initial frequencies of ROs with PMOS switches having antennas on upper layers decrease. However, those with NMOS switches become higher than those without PID because high-k dielectrics are damaged by positive charges. The degradation induced by negative BTI (NBTI) in PMOS is 1.5 times larger than that induced by positive BTI (PBTI) in NMOS. However, both NBTI- and PBTI-induced degradations are the same among different antenna layers. The frequency fluctuation caused by PID is converted to threshold voltage shifts by circuit simulations. Threshold voltages shift by 8.4 and 11% owing to PID in PMOS and NMOS transistors, respectively.

Inkjet printed graphene-based field-effect transistors on flexible substrate

NASA Astrophysics Data System (ADS)

Monne, Mahmuda Akter; Enuka, Evarestus; Wang, Zhuo; Chen, Maggie Yihong

2017-08-01

This paper presents the design and fabrication of inkjet printed graphene field-effect transistors (GFETs). The inkjet printed GFET is fabricated on a DuPont Kapton FPC Polyimide film with a thickness of 5 mill and dielectric constant of 3.9 by using a Fujifilm Dimatix DMP-2831 materials deposition system. A layer by layer 3D printing technique is deployed with an initial printing of source and drain by silver nanoparticle ink. Then graphene active layer doped with molybdenum disulfide (MoS2) monolayer/multilayer dispersion, is printed onto the surface of substrate covering the source and drain electrodes. High capacitance ion gel is adopted as the dielectric material due to the high dielectric constant. Then the dielectric layer is then covered with silver nanoparticle gate electrode. Characterization of GFET has been done at room temperature (25°C) using HP-4145B semiconductor parameter analyzer (Hewlett-Packard). The characterization result shows for a voltage sweep from -2 volts to 2 volts, the drain current changes from 949 nA to 32.3 μA and the GFET achieved an on/off ratio of 38:1, which is a milestone for inkjet printed flexible graphene transistor.

Crossover from band-like to thermally activated charge transport in organic transistors due to strain-induced traps.

PubMed

Mei, Yaochuan; Diemer, Peter J; Niazi, Muhammad R; Hallani, Rawad K; Jarolimek, Karol; Day, Cynthia S; Risko, Chad; Anthony, John E; Amassian, Aram; Jurchescu, Oana D

2017-08-15

The temperature dependence of the charge-carrier mobility provides essential insight into the charge transport mechanisms in organic semiconductors. Such knowledge imparts critical understanding of the electrical properties of these materials, leading to better design of high-performance materials for consumer applications. Here, we present experimental results that suggest that the inhomogeneous strain induced in organic semiconductor layers by the mismatch between the coefficients of thermal expansion (CTE) of the consecutive device layers of field-effect transistors generates trapping states that localize charge carriers. We observe a universal scaling between the activation energy of the transistors and the interfacial thermal expansion mismatch, in which band-like transport is observed for similar CTEs, and activated transport otherwise. Our results provide evidence that a high-quality semiconductor layer is necessary, but not sufficient, to obtain efficient charge-carrier transport in devices, and underline the importance of holistic device design to achieve the intrinsic performance limits of a given organic semiconductor. We go on to show that insertion of an ultrathin CTE buffer layer mitigates this problem and can help achieve band-like transport on a wide range of substrate platforms.

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

PubMed

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Three-terminal graphene single-electron transistor fabricated using feedback-controlled electroburning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Puczkarski, Paweł; Gehring, Pascal, E-mail: pascal.gehring@materials.ox.ac.uk; Lau, Chit S.

2015-09-28

We report room-temperature Coulomb blockade in a single layer graphene three-terminal single-electron transistor fabricated using feedback-controlled electroburning. The small separation between the side gate electrode and the graphene quantum dot results in a gate coupling up to 3 times larger compared to the value found for the back gate electrode. This allows for an effective tuning between the conductive and Coulomb blocked state using a small side gate voltage of about 1 V. The technique can potentially be used in the future to fabricate all-graphene based room temperature single-electron transistors or three terminal single molecule transistors with enhanced gate coupling.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Hui Fang; Sun, Wen; Han, Xin Feng

2018-06-01

An analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors (HS-TFETs) is presented for the first time, where hetero stacked materials are composed of two different bandgaps. The bandgap of the underlying layer is smaller than that of the upper layer. Under different device parameters (upper layer thickness, underlying layer thickness, and hetero stacked materials) and temperature, the validity of the model is demonstrated by the agreement of its results with the simulation results. Moreover, the results show that the HS-TFETs can obtain predominant performance with relatively slow changes of subthreshold swing (SS) over a wide drain current range, steep average subthreshold swing, high on-state current, and large on–off state current ratio.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Dry etching method for compound semiconductors

DOEpatents

Shul, Randy J.; Constantine, Christopher

1997-01-01

A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.

Dry etching method for compound semiconductors

DOEpatents

Shul, R.J.; Constantine, C.

1997-04-29

A dry etching method is disclosed. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators. 1 fig.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

NASA Astrophysics Data System (ADS)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Organic field effect transistors - Study of performance parameters for different dielectric layer thickness

NASA Astrophysics Data System (ADS)

Assis, Anu; Shahul Hameed T., A.; Predeep, P.

2017-06-01

Mobility and current handling capabilities of Organic Field Effect Transistor (OFET) are vitally important parameters in the electrical performance where the material parameters and thickness of different layers play significant role. In this paper, we report the simulation of an OFET using multi physics tool, where the active layer is pentacene and Poly Methyl Methacrylate (PMMA) forms the dielectric. Electrical characterizations of the OFET on varying the thickness of the dielectric layer from 600nm to 400nm are simulated and drain current, transconductance and mobility are analyzed. In the study it is found that even though capacitance increases with reduction in dielectric layer thickness, the transconductance effect is reflected many more times in the mobility which in turn could be attributed to the variations in transverse electric field. The layer thickness below 300nm may result in gate leakage current points to the requirement of optimizing the thickness of different layers for better performance.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Polarization of gold in nanopores leads to ion current rectification

DOE PAGES

Yang, Crystal; Hinkle, Preston; Menestrina, Justin; ...

2016-10-03

Biomimetic nanopores with rectifying properties are relevant components of ionic switches, ionic circuits, and biological sensors. Rectification indicates that currents for voltages of one polarity are higher than currents for voltages of the opposite polarity. Ion current rectification requires the presence of surface charges on the pore walls, achieved either by the attachment of charged groups or in multielectrode systems by applying voltage to integrated gate electrodes. Here we present a simpler concept for introducing surface charges via polarization of a thin layer of Au present at one entrance of a silicon nitride nanopore. In an electric field applied bymore » two electrodes placed in bulk solution on both sides of the membrane, the Au layer polarizes such that excess positive charge locally concentrates at one end and negative charge concentrates at the other end. Consequently, a junction is formed between zones with enhanced anion and cation concentrations in the solution adjacent to the Au layer. This bipolar double layer together with enhanced cation concentration in a negatively charged silicon nitride nanopore leads to voltage-controlled surface-charge patterns and ion current rectification. The experimental findings are supported by numerical modeling that confirm modulation of ionic concentrations by the Au layer and ion current rectification even in low-aspect ratio nanopores. Lastly, our findings enable a new strategy for creating ionic circuits with diodes and transistors.« less

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

PubMed Central

Dehzangi, Arash; Abedini, Alam; Abdullah, Ahmad Makarimi; Saion, Elias; Hutagalung, Sabar D; Hamidon, Mohd N; Hassan, Jumiah

2012-01-01

Summary A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current. PMID:23365794

A theoretical modeling of photocurrent generation and decay in layered MoS2 thin-film transistor photosensors

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Park, Junghak; Jeon, Sanghun

2017-02-01

A model that universally describes the characteristics of photocurrent in molybdenum disulphide (MoS2) thin-film transistor (TFT) photosensors in both ‘light on’ and ‘light off’ conditions is presented for the first time. We considered possible material-property dependent carrier generation and recombination mechanisms in layered MoS2 channels with different numbers of layers. We propose that the recombination rates that are mainly composed of direct band-to-band recombination and interface trap-involved recombination change on changing the light condition and the number of layers. By comparing the experimental results, it is shown that the model performs well in describing the photocurrent behaviors of MoS2 TFT photosensors, including the photocurrent generation under illumination and a hugely long time persistent trend of the photocurrent decay in the dark condition, for a range of MoS2 layer numbers.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Enhanced carrier mobility of multilayer MoS2 thin-film transistors by Al2O3 encapsulation

NASA Astrophysics Data System (ADS)

Kim, Seong Yeoul; Park, Seonyoung; Choi, Woong

2016-10-01

We report the effect of Al2O3 encapsulation on the carrier mobility and contact resistance of multilayer MoS2 thin-film transistors by statistically investigating 70 devices with SiO2 bottom-gate dielectric. After Al2O3 encapsulation by atomic layer deposition, calculation based on Y-function method indicates that the enhancement of carrier mobility from 24.3 cm2 V-1 s-1 to 41.2 cm2 V-1 s-1 occurs independently from the reduction of contact resistance from 276 kΩ.μm to 118 kΩ.μm. Furthermore, contrary to the previous literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method of improving the carrier mobility of multilayer MoS2 transistors, providing important implications on the application of MoS2 and other two-dimensional materials into high-performance transistors.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.

PubMed

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A; Anthopoulos, Thomas D

2017-03-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In 2 O 3 /ZnO heterojunction. We find that In 2 O 3 /ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In 2 O 3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In 2 O 3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution

PubMed Central

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A.; Anthopoulos, Thomas D.

2017-01-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In2O3/ZnO heterojunction. We find that In2O3/ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In2O3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In2O3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications. PMID:28435867

Monolithically integrated two-dimensional arrays of optoelectronic threshold devices for neural network applications

NASA Technical Reports Server (NTRS)

Kim, J. H.; Katz, J.; Lin, S. H.; Psaltis, D.

1989-01-01

A monolithic 10 x 10 two-dimensional array of 'optical neuron' optoelectronic threshold elements for neural network applications has been designed, fabricated, and tested. Overall array dimensions are 5 x 5 mm, while the individual neurons, composed of an LED that is driven by a double-heterojunction bipolar transistor, are 250 x 250 microns. The overall integrated structure exhibited semiconductor-controlled rectifier characteristics, with a breakover voltage of 75 V and a reverse-breakdown voltage of 60 V; this is attributable to the parasitic p-n-p transistor which exists as a result of the sharing of the same n-AlGaAs collector between the transistors and the LED.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Achievement of normally-off AlGaN/GaN high-electron mobility transistor with p-NiOx capping layer by sputtering and post-annealing

NASA Astrophysics Data System (ADS)

Huang, Shyh-Jer; Chou, Cheng-Wei; Su, Yan-Kuin; Lin, Jyun-Hao; Yu, Hsin-Chieh; Chen, De-Long; Ruan, Jian-Long

2017-04-01

In this paper, we present a technique to fabricate normally off GaN-based high-electron mobility transistor (HEMT) by sputtering and post-annealing p-NiOx capping layer. The p-NiOx layer is produced by sputtering at room temperature and post-annealing at 500 °C for 30 min in pure O2 environment to achieve high hole concentration. The Vth shifts from -3 V in the conventional transistor to 0.33 V, and on/off current ratio became 107. The forward and reverse gate breakdown increase from 3.5 V and -78 V to 10 V and -198 V, respectively. The reverse gate leakage current is 10-9 A/mm, and the off-state drain-leakage current is 10-8 A/mm. The Vth hysteresis is extremely small at about 33 mV. We also investigate the mechanism that increases hole concentration of p-NiOx after annealing in oxygen environment resulted from the change of Ni2+ to Ni3+ and the surge of (111)-orientation.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

NASA Astrophysics Data System (ADS)

Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

2018-03-01

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

NASA Astrophysics Data System (ADS)

Yeon, Seongjin; Seo, Kwangseok

2008-04-01

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate-channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

Characterization of multilayer GaAs/AlGaAs transistor structures by variable angle spectroscopic ellipsometry

NASA Technical Reports Server (NTRS)

Merkel, Kenneth G.; Snyder, Paul G.; Woollam, John A.; Alterovitz, Samuel; Rai, A. K.

1989-01-01

Variable angle of incidence spectroscopic ellipsometry (VASE) has been implemented as a means of determining layer thickness, alloy composition, and growth quality of GaAs/AlGaAs samples composed of relatively thick layers as well as superlattices. The structures studied in this work contained GaAs/AlGaAs multilayers with a superlattice 'barrier' and were grown for later formation of modulation-doped field effect transistors (MODFETs). Sample modeling was performed by treating the superlattice as a bulk AlGaAs layer of unknown composition. Extremely good data fits were realized when five layer thicknesses and two alloy ratios were allowed to vary in a regression analysis. Room temperature excitonic effects associated with the e-hh(1), e-lh(1) and e-hh(2) transitions were observed in the VASE data.

Method of doping organic semiconductors

DOEpatents

Kloc,; Christian Leo; Ramirez; Arthur Penn; So, Woo-Young

2010-10-26

An apparatus has a crystalline organic semiconducting region that includes polyaromatic molecules. A source electrode and a drain electrode of a field-effect transistor are both in contact with the crystalline organic semiconducting region. A gate electrode of the field-effect transistor is located to affect the conductivity of the crystalline organic semiconducting region between the source and drain electrodes. A dielectric layer of a first dielectric that is substantially impermeable to oxygen is in contact with the crystalline organic semiconducting region. The crystalline organic semiconducting region is located between the dielectric layer and a substrate. The gate electrode is located on the dielectric layer. A portion of the crystalline organic semiconducting region is in contact with a second dielectric via an opening in the dielectric layer. A physical interface is located between the second dielectric and the first dielectric.

Improved photoswitching response times of MoS2 field-effect transistors by stacking p-type copper phthalocyanine layer

NASA Astrophysics Data System (ADS)

Pak, Jinsu; Min, Misook; Cho, Kyungjune; Lien, Der-Hsien; Ahn, Geun Ho; Jang, Jingon; Yoo, Daekyoung; Chung, Seungjun; Javey, Ali; Lee, Takhee

2016-10-01

Photoswitching response times (rise and decay times) of a vertical organic and inorganic heterostructure with p-type copper phthalocyanine (CuPc) and n-type molybdenum disulfide (MoS2) semiconductors are investigated. By stacking a CuPc layer on MoS2 field effect transistors, better photodetection capability and fast photoswitching rise and decay phenomena are observed. Specifically, with a 2 nm-thick CuPc layer on the MoS2 channel, the photoswitching decay time decreases from 3.57 s to 0.18 s. The p-type CuPc layer, as a passivation layer, prevents the absorption of oxygen on the surface of the MoS2 channel layer, which results in a shortened photoswitching decay time because adsorbed oxygen destroys the balanced ratio of electrons and holes, leading to the interruption of recombination processes. The suggested heterostructure may deliver enhanced photodetection abilities and photoswitching characteristics for realizing ultra-thin and sensitive photodetectors.

Doped bottom-contact organic field-effect transistors

NASA Astrophysics Data System (ADS)

Liu, Shiyi; Billig, Paul; Al-Shadeedi, Akram; Kaphle, Vikash; Lüssem, Björn

2018-07-01

The influence of doping on doped bottom-gate bottom-contact organic field-effect transistors (OFETs) is discussed. It is shown that the inclusion of a doped layer at the dielectric/organic semiconductor layer leads to a significant reduction in the contact resistances and a fine control of the threshold voltage. Through varying the thickness of the doped layer, a linear shift of threshold voltage V T from ‑3.1 to ‑0.22 V is observed for increasing thickness of doped layer. Meanwhile, the contact resistance at the source and drain electrode is reduced from 138.8 MΩ at V GS = ‑10 V for 3 nm to 0.3 MΩ for 7 nm thick doped layers. Furthermore, an increase of charge mobility is observed for increasing thickness of doped layer. Overall, it is shown that doping can minimize injection barriers in bottom-contact OFETs with channel lengths in the micro-meter regime, which has the potential to increase the performance of this technology further.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Effect of hydrogen on the device performance and stability characteristics of amorphous InGaZnO thin-film transistors with a SiO2/SiNx/SiO2 buffer

NASA Astrophysics Data System (ADS)

Han, Ki-Lim; Ok, Kyung-Chul; Cho, Hyeon-Su; Oh, Saeroonter; Park, Jin-Seong

2017-08-01

We investigate the influence of the multi-layered buffer consisting of SiO2/SiNx/SiO2 on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The multi-layered buffer inhibits permeation of water from flexible plastic substrates and prevents degradation of overlying organic layers. The a-IGZO TFTs with a multi-layered buffer suffer less positive bias temperature stress instability compared to the device with a single SiO2 buffer layer after annealing at 250 °C. Hydrogen from the SiNx layer diffuses into the active layer and reduces electron trapping at loosely bound oxygen defects near the SiO2/a-IGZO interface. Quantitative analysis shows that a hydrogen density of 1.85 × 1021 cm-3 is beneficial to reliability. However, the multi-layered buffer device annealed at 350 °C resulted in conductive characteristics due to the excess carrier concentration from the higher hydrogen density of 2.12 × 1021 cm-3.

Fabrication and Characteristics of Pentacene/Vanadium Pentoxide Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minagawa, M.; Nakai, K.; Baba, A.

2011-12-23

Organic field-effect transistors (OFETs) were fabricated using pentacene thin layer, and the effects of inserted Lewis-acid thin layers on electrical properties were investigated. The OFETs have active layers of pentacene and vanadium pentoxide (V{sub 2}O{sub 5}) as a Lewis-acid layer. Typical source-drain current (I{sub DS}) vs. source-drain voltage (V{sub DS}) curves were observed under negative gate voltages (V{sub G}S) application, and the shift of the threshold voltage for FET driving (V{sub t}) to positive side was also observed by V{sub 2}O{sub 5} layer insertion, that is, -2.5 V for device with V{sub 2}O{sub 5} layer and -5.7 V for devicemore » without V{sub 2}O{sub 5} layer. It was thought that charge transfer (CT) complexes which were formed at the interface between pentacene and V{sub 2}O{sub 5} layer were dissociated by the applied gate voltage, and the generated holes seem to contribute to drain current and the apparent V{sub t} improvement.« less

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Charge Transport in Low-Temperature Processed Thin-Film Transistors Based on Indium Oxide/Zinc Oxide Heterostructures.

PubMed

Krausmann, Jan; Sanctis, Shawn; Engstler, Jörg; Luysberg, Martina; Bruns, Michael; Schneider, Jörg J

2018-06-20

The influence of the composition within multilayered heterostructure oxide semiconductors has a critical impact on the performance of thin-film transistor (TFT) devices. The heterostructures, comprising alternating polycrystalline indium oxide and zinc oxide layers, are fabricated by a facile atomic layer deposition (ALD) process, enabling the tuning of its electrical properties by precisely controlling the thickness of the individual layers. This subsequently results in enhanced TFT performance for the optimized stacked architecture after mild thermal annealing at temperatures as low as 200 °C. Superior transistor characteristics, resulting in an average field-effect mobility (μ sat. ) of 9.3 cm 2 V -1 s -1 ( W/ L = 500), an on/off ratio ( I on / I off ) of 5.3 × 10 9 , and a subthreshold swing of 162 mV dec -1 , combined with excellent long-term and bias stress stability are thus demonstrated. Moreover, the inherent semiconducting mechanism in such multilayered heterostructures can be conveniently tuned by controlling the thickness of the individual layers. Herein, devices comprising a higher In 2 O 3 /ZnO ratio, based on individual layer thicknesses, are predominantly governed by percolation conduction with temperature-independent charge carrier mobility. Careful adjustment of the individual oxide layer thicknesses in devices composed of stacked layers plays a vital role in the reduction of trap states, both interfacial and bulk, which consequently deteriorates the overall device performance. The findings enable an improved understanding of the correlation between TFT performance and the respective thin-film composition in ALD-based heterostructure oxides.

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer

NASA Astrophysics Data System (ADS)

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-01

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd)4Ti3O12 films as insulator, and HfO2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO2 defect control layer shows a low leakage current density of 3.1 × 10-9 A/cm2 at a gate voltage of - 3 V.

Moving towards the magnetoelectric graphene transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Shi; Xiao, Zhiyong; Kwan, Chun -Pui

Here, the interfacial charge transfer between mechanically exfoliated few-layer graphene and Cr 2O 3 (0001) surfaces has been investigated. Electrostatic force microscopy and Kelvin probe force microscopy studies point to hole doping of few-layer graphene, with up to a 150 meV shift in the Fermi level, an aspect that is confirmed by Raman spectroscopy. Density functional theory calculations furthermore confirm the p-type nature of the graphene/chromia interface and suggest that the chromia is able to induce a significant carrier spin polarization in the graphene layer. A large magnetoelectrically controlled magneto-resistance can therefore be anticipated in transistor structures based on thismore » system, a finding important for developing graphene-based spintronic applications.« less

Single-Walled Carbon Nanotube Dominated Micron-Wide Stripe Patterned-Based Ferroelectric Field-Effect Transistors with HfO2 Defect Control Layer.

PubMed

Tan, Qiuhong; Wang, Qianjin; Liu, Yingkai; Yan, Hailong; Cai, Wude; Yang, Zhikun

2018-04-27

Ferroelectric field-effect transistors (FeFETs) with single-walled carbon nanotube (SWCNT) dominated micron-wide stripe patterned as channel, (Bi,Nd) 4 Ti 3 O 12 films as insulator, and HfO 2 films as defect control layer were developed and fabricated. The prepared SWCNT-FeFETs possess excellent properties such as large channel conductance, high on/off current ratio, high channel carrier mobility, great fatigue endurance performance, and data retention. Despite its thin capacitance equivalent thickness, the gate insulator with HfO 2 defect control layer shows a low leakage current density of 3.1 × 10 -9  A/cm 2 at a gate voltage of - 3 V.

Effect of Al2O3 insulator thickness on the structural integrity of amorphous indium-gallium-zinc-oxide based thin film transistors.

PubMed

Kim, Hak-Jun; Hwang, In-Ju; Kim, Youn-Jea

2014-12-01

The current transparent oxide semiconductors (TOSs) technology provides flexibility and high performance. In this study, multi-stack nano-layers of TOSs were designed for three-dimensional analysis of amorphous indium-gallium-zinc-oxide (a-IGZO) based thin film transistors (TFTs). In particular, the effects of torsional and compressive stresses on the nano-sized active layers such as the a-IGZO layer were investigated. Numerical simulations were carried out to investigate the structural integrity of a-IGZO based TFTs with three different thicknesses of the aluminum oxide (Al2O3) insulator (δ = 10, 20, and 30 nm), respectively, using a commercial code, COMSOL Multiphysics. The results are graphically depicted for operating conditions.

Moving towards the magnetoelectric graphene transistor

DOE PAGES

Cao, Shi; Xiao, Zhiyong; Kwan, Chun -Pui; ...

2017-10-30

Here, the interfacial charge transfer between mechanically exfoliated few-layer graphene and Cr 2O 3 (0001) surfaces has been investigated. Electrostatic force microscopy and Kelvin probe force microscopy studies point to hole doping of few-layer graphene, with up to a 150 meV shift in the Fermi level, an aspect that is confirmed by Raman spectroscopy. Density functional theory calculations furthermore confirm the p-type nature of the graphene/chromia interface and suggest that the chromia is able to induce a significant carrier spin polarization in the graphene layer. A large magnetoelectrically controlled magneto-resistance can therefore be anticipated in transistor structures based on thismore » system, a finding important for developing graphene-based spintronic applications.« less

Artificial Synaptic Devices Based on Natural Chicken Albumen Coupled Electric-Double-Layer Transistors

NASA Astrophysics Data System (ADS)

Wu, Guodong; Feng, Ping; Wan, Xiang; Zhu, Liqiang; Shi, Yi; Wan, Qing

2016-03-01

Recent progress in using biomaterials to fabricate functional electronics has got growing attention for the new generation of environmentally friendly and biocompatible electronic devices. As a kind of biological material with rich source, proteins are essential natural component of all organisms. At the same time, artificial synaptic devices are of great significance for neuromorphic systems because they can emulate the signal process and memory behaviors of biological synapses. In this report, natural chicken albumen with high proton conductivity was used as the coupling electrolyte film for organic/inorganic hybrid synaptic devices fabrication. Some important synaptic functions including paired-pulse facilitation, dynamic filtering, short-term to long-term memory transition and spatial summation and shunting inhibition were successfully mimicked. Our results are very interesting for biological friendly artificial neuron networks and neuromorphic systems.

Behavior of pentacene initial nucleation on various dielectrics and its effect on carrier transport in organic field-effect transistor.

PubMed

Qi, Qiong; Yu, Aifang; Wang, Liangmin; Jiang, Chao

2010-11-01

The influence of dielectric surface energy on the initial nucleation and the growth of pentacene films as well as the electrical properties of the pentacene-based field-effect transistors are investigated. We have examined a range of organic and inorganic dielectrics with different surface energies, such as polycarbonate/SiO2, polystyrene/SiO2, and PMMA/SiO2 bi-layered dielectrics and also the bare SiO2 dielectric. Atomic force microscopy measurements of sub-monolayer and thick pentacene films indicated that the growth of pentacene film was in Stranski-Kranstanow growth mode on all the dielectrics. However, the initial nucleation density and the size of the first-layered pentacene islands deposited on different dielectrics are drastically influenced by the dielectric surface energy. With the increasing of the surface energy, the nucleation density increased and thus the average size of pentacene islands for the first mono-layer deposition decreased. The performance of fabricated pentacene-based thin film transistors was found to be highly related to nucleation density and the island size of deposited Pentacene film, and it had no relationship to the final particle size of the thick pentacene film. The field effect mobility of the thin film transistor could be achieved as high as 1.38 cm2Ns with on/off ratio over 3 x 10(7) on the PS/SiO2 where the lowest surface energy existed among all the dielectrics. For comparison, the values of mobility and on/off ratio were 0.42 cm2Ns and 1 x 10(6) for thin film transistor deposited directly on bare SiO2 having the highest surface energy.

Fully transparent thin film transistors based on zinc oxide channel layer and molybdenum doped indium oxide electrodes

NASA Astrophysics Data System (ADS)

MÄ dzik, Mateusz; Elamurugu, Elangovan; Viegas, Jaime

2016-03-01

In this work we report the fabrication of thin film transistors (TFT) with zinc oxide channel and molybdenum doped indium oxide (IMO) electrodes, achieved by room temperature sputtering. A set of devices was fabricated, with varying channel width and length from 5μm to 300μm. Output and transfer characteristics were then extracted to study the performance of thin film transistors, namely threshold voltage and saturation current, enabling to determine optimal fabrication process parameters. Optical transmission in the UV-VIS-IR are also reported.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

A highly manufacturable 0.2 {mu}m AlGaAs/InGaAs PHEMT fabricated using the single-layer integrated-metal FET (SLIMFET) process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Havasy, C.K.; Quach, T.K.; Bozada, C.A.

1995-12-31

This work is the development of a single-layer integrated-metal field effect transistor (SLIMFET) process for a high performance 0.2 {mu}m AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT). This process is compatible with MMIC fabrication and minimizes process variations, cycle time, and cost. This process uses non-alloyed ohmic contacts, a selective gate-recess etching process, and a single gate/source/drain metal deposition step to form both Schottky and ohmic contacts at the same time.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Back-channel-etch amorphous indium-gallium-zinc oxide thin-film transistors: The impact of source/drain metal etch and final passivation

NASA Astrophysics Data System (ADS)

Nag, Manoj; Bhoolokam, Ajay; Steudel, Soeren; Chasin, Adrian; Myny, Kris; Maas, Joris; Groeseneken, Guido; Heremans, Paul

2014-11-01

We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation.

Effects of Energy Relaxation via Quantum Coupling Among Three-Dimensional Motion on the Tunneling Current of Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Li, Xijun

2015-12-01

We report theoretical study of the effects of energy relaxation on the tunneling current through the oxide layer of a two-dimensional graphene field-effect transistor. In the channel, when three-dimensional electron thermal motion is considered in the Schrödinger equation, the gate leakage current at a given oxide field largely increases with the channel electric field, electron mobility, and energy relaxation time of electrons. Such an increase can be especially significant when the channel electric field is larger than 1 kV/cm. Numerical calculations show that the relative increment of the tunneling current through the gate oxide will decrease with increasing the thickness of oxide layer when the oxide is a few nanometers thick. This highlights that energy relaxation effect needs to be considered in modeling graphene transistors.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Large-area synthesis of high-quality and uniform monolayer WS2 on reusable Au foils

PubMed Central

Gao, Yang; Liu, Zhibo; Sun, Dong-Ming; Huang, Le; Ma, Lai-Peng; Yin, Li-Chang; Ma, Teng; Zhang, Zhiyong; Ma, Xiu-Liang; Peng, Lian-Mao; Cheng, Hui-Ming; Ren, Wencai

2015-01-01

Large-area monolayer WS2 is a desirable material for applications in next-generation electronics and optoelectronics. However, the chemical vapour deposition (CVD) with rigid and inert substrates for large-area sample growth suffers from a non-uniform number of layers, small domain size and many defects, and is not compatible with the fabrication process of flexible devices. Here we report the self-limited catalytic surface growth of uniform monolayer WS2 single crystals of millimetre size and large-area films by ambient-pressure CVD on Au. The weak interaction between the WS2 and Au enables the intact transfer of the monolayers to arbitrary substrates using the electrochemical bubbling method without sacrificing Au. The WS2 shows high crystal quality and optical and electrical properties comparable or superior to mechanically exfoliated samples. We also demonstrate the roll-to-roll/bubbling production of large-area flexible films of uniform monolayer, double-layer WS2 and WS2/graphene heterostructures, and batch fabrication of large-area flexible monolayer WS2 film transistor arrays. PMID:26450174

Enhanced sheet carrier densities in polarization controlled AlInN/AlN/GaN/InGaN field-effect transistor on Si (111)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hennig, J., E-mail: jonas.hennig@ovgu.de; Dadgar, A.; Witte, H.

2015-07-15

We report on GaN based field-effect transistor (FET) structures exhibiting sheet carrier densities of n = 2.9 10{sup 13} cm{sup −2} for high-power transistor applications. By grading the indium-content of InGaN layers grown prior to a conventional GaN/AlN/AlInN FET structure control of the channel width at the GaN/AlN interface is obtained. The composition of the InGaN layer was graded from nominally x{sub In} = 30 % to pure GaN just below the AlN/AlInN interface. Simulations reveal the impact of the additional InGaN layer on the potential well width which controls the sheet carrier density within the channel region of the devices.more » Benchmarking the In{sub x}Ga{sub 1−x}N/GaN/AlN/Al{sub 0.87}In{sub 0.13}N based FETs against GaN/AlN/AlInN FET reference structures we found increased maximum current densities of I{sub SD} = 1300 mA/mm (560 mA/mm). In addition, the InGaN layer helps to achieve broader transconductance profiles as well as reduced leakage currents.« less

Interlayer tunnel field-effect transistor (ITFET): physics, fabrication and applications

NASA Astrophysics Data System (ADS)

Kang, Sangwoo; Mou, Xuehao; Fallahazad, Babak; Prasad, Nitin; Wu, Xian; Valsaraj, Amithraj; Movva, Hema C. P.; Kim, Kyounghwan; Tutuc, Emanuel; Register, Leonard F.; Banerjee, Sanjay K.

2017-09-01

The scaling challenges of complementary metal oxide semiconductors (CMOS) are increasing with the pace of scaling showing marked signs of slowing down. This slowing has brought about a widespread search for an alternative beyond-CMOS device concept. While the charge tunneling phenomenon has been known for almost a century, and tunneling based transistors have been studied in the past few decades, its possibilities are being re-examined with the emergence of a new class of two-dimensional (2D) materials. By stacking varying 2D materials together, with two electrode layers sandwiching a tunnel dielectric layer, it could be possible to make vertical tunnel transistors without the limitations that have plagued such devices implemented within other material systems. When the two electrode layers are of the same material, under certain conditions, one can achieve resonant tunneling between the two layers, manifesting as negative differential resistance (NDR) in the interlayer current-voltage characteristics. We call this type of device an interlayer tunnel FET (ITFET). We review the basic operation principles of this device, experimental and theoretical studies, and benchmark simulation results for several digital logic gates based on a compact model that we developed. The results are placed in the context of work going on in other groups.

Layered CU-based electrode for high-dielectric constant oxide thin film-based devices

DOEpatents

Auciello, Orlando

2010-05-11

A layered device including a substrate; an adhering layer thereon. An electrical conducting layer such as copper is deposited on the adhering layer and then a barrier layer of an amorphous oxide of TiAl followed by a high dielectric layer are deposited to form one or more of an electrical device such as a capacitor or a transistor or MEMS and/or a magnetic device.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

The Mobility Enhancement of Indium Gallium Zinc Oxide Transistors via Low-temperature Crystallization using a Tantalum Catalytic Layer.

PubMed

Shin, Yeonwoo; Kim, Sang Tae; Kim, Kuntae; Kim, Mi Young; Oh, Saeroonter; Jeong, Jae Kyeong

2017-09-07

High-mobility indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are achieved through low-temperature crystallization enabled via a reaction with a transition metal catalytic layer. For conventional amorphous IGZO TFTs, the active layer crystallizes at thermal annealing temperatures of 600 °C or higher, which is not suitable for displays using a glass substrate. The crystallization temperature is reduced when in contact with a Ta layer, where partial crystallization at the IGZO back-channel occurs with annealing at 300 °C, while complete crystallization of the active layer occurs at 400 °C. The field-effect mobility is significantly boosted to 54.0 cm 2 /V·s for the IGZO device with a metal-induced polycrystalline channel formed at 300 °C compared to 18.1 cm 2 /V·s for an amorphous IGZO TFT without a catalytic layer. This work proposes a facile and effective route to enhance device performance by crystallizing the IGZO layer with standard annealing temperatures, without the introduction of expensive laser irradiation processes.

Trilayer TMDC Heterostructures for MOSFETs and Nanobiosensors

NASA Astrophysics Data System (ADS)

Datta, Kanak; Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-02-01

Two dimensional materials such as transition metal dichalcogenides (TMDC) and their bi-layer/tri-layer heterostructures have become the focus of intense research and investigation in recent years due to their promising applications in electronics and optoelectronics. In this work, we have explored device level performance of trilayer TMDC heterostructure (MoS2/MX2/MoS2; M = Mo or, W and X = S or, Se) metal oxide semiconductor field effect transistors (MOSFETs) in the quantum ballistic regime. Our simulation shows that device `on' current can be improved by inserting a WS2 monolayer between two MoS2 monolayers. Application of biaxial tensile strain reveals a reduction in drain current which can be attributed to the lowering of carrier effective mass with increased tensile strain. In addition, it is found that gate underlap geometry improves electrostatic device performance by improving sub-threshold swing. However, increase in channel resistance reduces drain current. Besides exploring the prospect of these materials in device performance, novel trilayer TMDC heterostructure double gate field effect transistors (FETs) are proposed for sensing Nano biomolecules as well as for pH sensing. Bottom gate operation ensures these FETs operating beyond Nernst limit of 59 mV/pH. Simulation results found in this work reveal that scaling of bottom gate oxide results in better sensitivity while top oxide scaling exhibits an opposite trend. It is also found that, for identical operating conditions, proposed TMDC FET pH sensors show super-Nernst sensitivity indicating these materials as potential candidates in implementing such sensor. Besides pH sensing, all these materials show high sensitivity in the sub-threshold region as a channel material in nanobiosensor while MoS2/WS2/MoS2 FET shows the least sensitivity among them.

Fabrication of air-stable n-type carbon nanotube thin-film transistors on flexible substrates using bilayer dielectrics.

PubMed

Li, Guanhong; Li, Qunqing; Jin, Yuanhao; Zhao, Yudan; Xiao, Xiaoyang; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2015-11-14

Single-walled carbon nanotube (SWNT) thin-film transistors hold great potential for flexible electronics. However, fabrication of air-stable n-type devices by methods compatible with standard photolithography on flexible substrates is challenging. Here, we demonstrated that by using a bilayer dielectric structure of MgO and atomic layer deposited (ALD) Al2O3 or HfO2, air-stable n-type devices can be obtained. The mechanism for conduction type conversion was elucidated and attributed to the hole depletion in SWNT, the decrease of the trap state density by MgO assimilating adsorbed water molecules in the vicinity of SWNT, and the energy band bending because of the positive fixed charges in the ALD layer. The key advantage of the method is the relatively low temperature (120 or 90 °C) required here for the ALD process because we need not employ this step to totally remove the absorbates on the SWNTs. This advantage facilitates the integration of both p-type and n-type transistors through a simple lift off process and compact CMOS inverters were demonstrated. We also demonstrated that the doping of SWNTs in the channel plays a more important role than the Schottky barriers at the metal contacts in carbon nanotube thin-film transistors, unlike the situation in individual SWNT-based transistors.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates

NASA Astrophysics Data System (ADS)

Sheraw, Christopher Duncan

2003-10-01

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

The lithographer's dilemma: shrinking without breaking the bank

NASA Astrophysics Data System (ADS)

Levinson, Harry J.

2013-10-01

It can no longer be assumed that the lithographic scaling which has previously driven Moore's Law will lead in the future to reduced cost per transistor. Until recently, higher prices for lithography tools were offset by improvements in scanner productivity. The necessity of using double patterning to extend scaling beyond the single exposure resolution limit of optical lithography has resulted in a sharp increase in the cost of patterning a critical construction layer that has not been offset by improvements in exposure tool productivity. Double patterning has also substantially increased the cost of mask sets. EUV lithography represents a single patterning option, but the combination of very high exposure tools prices, moderate throughput, high maintenance costs, and expensive mask blanks makes this a solution more expensive than optical double patterning but less expensive than triple patterning. Directed self-assembly (DSA) could potentially improve wafer costs, but this technology currently is immature. There are also design layout and process integration issues associated with DSA that need to be solved in order to obtain full benefit from tighter pitches. There are many approaches for improving the cost effectiveness of lithography. Innovative double patterning schemes lead to smaller die. EUV lithography productivity can be improved with higher power light sources and improved reliability. There are many technical and business challenges for extending EUV lithography to higher numerical apertures. Efficient contact hole and cut mask solutions are needed, as well as very tight overlay control, regardless of lithographic solution.

Fabrication of amorphous IGZO thin film transistor using self-aligned imprint lithography with a sacrificial layer

NASA Astrophysics Data System (ADS)

Kim, Sung Jin; Kim, Hyung Tae; Choi, Jong Hoon; Chung, Ho Kyoon; Cho, Sung Min

2018-04-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin film transistor (TFT) was fabricated by a self-aligned imprint lithography (SAIL) method with a sacrificial photoresist layer. The SAIL is a top-down method to fabricate a TFT using a three-dimensional multilayer etch mask having all pattern information for the TFT. The sacrificial layer was applied in the SAIL process for the purpose of removing the resin residues that were inevitably left when the etch mask was thinned by plasma etching. This work demonstrated that the a-IGZO TFT could be fabricated by the SAIL process with the sacrificial layer. Specifically, the simple fabrication process utilized in this study can be utilized for the TFT with a plasma-sensitive semiconductor such as the a-IGZO and further extended for the roll-to-roll TFT fabrication.

Flat-lying semiconductor-insulator interfacial layer in DNTT thin films.

PubMed

Jung, Min-Cherl; Leyden, Matthew R; Nikiforov, Gueorgui O; Lee, Michael V; Lee, Han-Koo; Shin, Tae Joo; Takimiya, Kazuo; Qi, Yabing

2015-01-28

The molecular order of organic semiconductors at the gate dielectric is the most critical factor determining carrier mobility in thin film transistors since the conducting channel forms at the dielectric interface. Despite its fundamental importance, this semiconductor-insulator interface is not well understood, primarily because it is buried within the device. We fabricated dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) thin film transistors by thermal evaporation in vacuum onto substrates held at different temperatures and systematically correlated the extracted charge mobility to the crystal grain size and crystal orientation. As a result, we identify a molecular layer of flat-lying DNTT molecules at the semiconductor-insulator interface. It is likely that such a layer might form in other material systems as well, and could be one of the factors reducing charge transport. Controlling this interfacial flat-lying layer may raise the ultimate possible device performance for thin film devices.

Directionally Aligned Amorphous Polymer Chains via Electrohydrodynamic-Jet Printing: Analysis of Morphology and Polymer Field-Effect Transistor Characteristics.

PubMed

Kim, Yebyeol; Bae, Jaehyun; Song, Hyun Woo; An, Tae Kyu; Kim, Se Hyun; Kim, Yun-Hi; Park, Chan Eon

2017-11-15

Electrohydrodynamic-jet (EHD-jet) printing provides an opportunity to directly assembled amorphous polymer chains in the printed pattern. Herein, an EHD-jet printed amorphous polymer was employed as the active layer for fabrication of organic field-effect transistors (OFETs). Under optimized conditions, the field-effect mobility (μ FET ) of the EHD-jet printed OFETs was 5 times higher than the highest μ FET observed in the spin-coated OFETs, and this improvement was achieved without the use of complex surface templating or additional pre- or post-deposition processing. As the chain alignment can be affected by the surface energy of the dielectric layer in EHD-jet printed OFETs, dielectric layers with varying wettability were examined. Near-edge X-ray absorption fine structure measurements were performed to compare the amorphous chain alignment in OFET active layers prepared by EHD-jet printing and spin coating.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo

2013-12-02

A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobilitymore » of 609 cm{sup 2} V{sup −1} s{sup −1}.« less

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Rhee, K. W.; Teufel, J.; Schoelkopf, R. J.

2002-01-01

This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

All-optical transistor based on Rydberg atom-assisted optomechanical system.

PubMed

Liu, Yi-Mou; Tian, Xue-Dong; Wang, Jing; Fan, Chu-Hui; Gao, Feng; Bao, Qian-Qian

2018-04-30

We study the optical response of a double optomechanical cavity system assisted by two Rydberg atoms. The target atom is only coupled with one side cavity by a single cavity mode, and gate one is outside the cavities. It has been realized that a long-range manipulation of optical properties of a hybrid system, by controlling the Rydberg atom decoupled with the optomechanical cavity. Switching on the coupling between atoms and cavity mode, the original spatial inversion symmetry of the double cavity structure has been broken. Combining the controllable optical non-reciprocity with the coherent perfect absorption/transmission/synthesis effect (CPA/CPT/CPS reported by [ X.-B.Yan Opt. Express 22, 4886 (2014)], we put forward the theoretical schemes of an all-optical transistor which contains functions such as a controllable diode, rectifier, and amplifier by controlling a single gate photon.

Réalisation de circuits intégrés I^2L à base de transistors bipolaires a double hétérojonction GaAlAs/GaAs

NASA Astrophysics Data System (ADS)

Vannel, J. P.; Camps, T.; Ferreira, A. S.; Tasselh, J.; Cazarré, A.; Marty, A.; Bailbé, J. P.

1991-04-01

GaAlAs/GaAs double heterojunction bipolar transistors (DHBT's) have a number of advantages for I^2L (integrated injection logic) high speed integrated circuits concerning the interchangeability between the emitter and the collector and a high design flexibility due to the use of two heterojunctions. We present the fabrication process of an I^2L integrated circuit including a frequency divider-by-two and a ring oscillator which presents a propagation delay time of 1.2 ns for a power consumption of 8 mW. Les transistors bipolaires à double hétérojonction GaAlAs/GaAs (TBDH) présentent de nombreux avantages pour leur application dans des circuits intégrés de logique I^2L (logique à injection intégrée), dont en particulier l'interchangeabilité entre émetteur et collecteur, et la liberté de conception résultant de l'utilisation de deux hétérojonctions. Dans ce cadre nous décrivons les principales étapes technologiques de fabrication d'un circuit intégré I^2L comportant un diviseur de fréquence par 2 et un oscillateur en anneau. Ce demier présente un temps de propagation de 1,2 ns pour une puissance dissipée de 8 mW.

New Lithium- and Diamine-Intercalated Superconductors Lix(CnH2n+4N2)yMoSe2 (n = 2,6)

NASA Astrophysics Data System (ADS)

Sato, Kazuki; Noji, Takashi; Hatakeda, Takehiro; Kawamata, Takayuki; Kato, Masatsune; Koike, Yoji

2018-05-01

We have succeeded in synthesizing new intercalation superconductors Lix(C2H8N2)yMoSe2 and Lix(C6H16N2)yMoSe2 with Tc = 4.2 and 3.8-6.0 K, respectively, via the co-intercalation of lithium and ethylenediamine or hexamethylenediamine into semiconducting 2H-MoSe2. It has been found that the Tc values are related not to the interlayer spacing between MoSe2 layers so much but to the electronic density of states (EDOS) at the Fermi level. Moreover, only Li-intercalated LixMoSe2 with a small interlayer spacing has been found to be non-superconducting. Accordingly, it has been concluded that not only a sufficient amount of EDOS at the Fermi level due to the charge transfer from intercalated Li to MoSe2 layers but also the enhancement of the two-dimensionality of the crystal structure and/or electronic structure due to the expansion of the interlayer spacing between MoSe2 layers is necessary for the appearance of superconductivity in MoSe2-based intercalation superconductors. The pairing mechanism and the analogy to the superconductivity in the electric double-layer transistors of 2H-MoX2 (X = S, Se, Te) are discussed.

Low-temperature fabrication of an HfO2 passivation layer for amorphous indium-gallium-zinc oxide thin film transistors using a solution process.

PubMed

Hong, Seonghwan; Park, Sung Pyo; Kim, Yeong-Gyu; Kang, Byung Ha; Na, Jae Won; Kim, Hyun Jae

2017-11-24

We report low-temperature solution processing of hafnium oxide (HfO 2 ) passivation layers for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). At 150 °C, the hafnium chloride (HfCl 4 ) precursor readily hydrolyzed in deionized (DI) water and transformed into an HfO 2 film. The fabricated HfO 2 passivation layer prevented any interaction between the back surface of an a-IGZO TFT and ambient gas. Moreover, diffused Hf 4+ in the back-channel layer of the a-IGZO TFT reduced the oxygen vacancy, which is the origin of the electrical instability in a-IGZO TFTs. Consequently, the a-IGZO TFT with the HfO 2 passivation layer exhibited improved stability, showing a decrease in the threshold voltage shift from 4.83 to 1.68 V under a positive bias stress test conducted over 10,000 s.

Apparatus for sensing patterns of electrical field variations across a surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, William L.; Devine, Roderick A. B.

An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials createdmore » by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.« less

Passivation of InP heterojunction bipolar transistors by strain controlled plasma assisted electron beam evaporated hafnium oxide

NASA Astrophysics Data System (ADS)

Driad, R.; Sah, R. E.; Schmidt, R.; Kirste, L.

2012-01-01

We present structural, stress, and electrical properties of plasma assisted e-beam evaporated hafnium dioxide (HfO2) layers on n-type InP substrates. These layers have subsequently been used for surface passivation of InGaAs/InP heterostructure bipolar transistors either alone or in combination with plasma enhanced chemical vapor deposited SiO2 layers. The use of stacked HfO2/SiO2 results in better interface quality with InGaAs/InP heterostructures, as illustrated by smaller leakage current and improved breakdown voltage. These improvements can be attributed to the reduced defect density and charge trapping at the dielectric-semiconductor interface. The deposition at room temperature makes these films suitable for sensitive devices.

Analysis of improved dc and ac performances of an InGaP/GaAs heterojunction bipolar transistor with a graded Al xGa 1- xAs layer at emitter/base heterojunction

NASA Astrophysics Data System (ADS)

Cheng, Shiou-Ying

2004-07-01

An InGaP/GaAs heterojunction bipolar transistor (HBT) with a continuous conduction-band structure is demonstrated and theoretically investigated. This device exhibited good performance including lower turn-on voltage, lower offset voltage and smaller collector current saturation voltage. The novel aspect of device structure design is the adoption of the compositionally linear-graded AlGaAs layer between the InGaP-emitter and GaAs-base layers. Therefore, the device studied shows better dc and ac performances than a conventional device. Consequently, this causes the substantial benefit for practical analog and digital applications especially for lower operation voltage, lower power consumption commercial and military products.

Preferential growth of short aligned, metallic-rich single-walled carbon nanotubes from perpendicular layered double hydroxide film.

PubMed

Zhao, Meng-Qiang; Tian, Gui-Li; Zhang, Qiang; Huang, Jia-Qi; Nie, Jing-Qi; Wei, Fei

2012-04-07

Direct bulk growth of single-walled carbon nanotubes (SWCNTs) with required properties, such as diameter, length, and chirality, is the first step to realize their advanced applications in electrical and optical devices, transparent conductive films, and high-performance field-effect transistors. Preferential growth of short aligned, metallic-rich SWCNTs is a great challenge to the carbon nanotube community. We report the bulk preferential growth of short aligned SWCNTs from perpendicular Mo-containing FeMgAl layered double hydroxide (LDH) film by a facile thermal chemical vapor deposition with CH(4) as carbon source. The growth of the short aligned SWCNTs showed a decreased growth velocity with an initial value of 1.9 nm s(-1). Such a low growth velocity made it possible to get aligned SWCNTs shorter than 1 μm with a growth duration less than 15 min. Raman spectra with different excitation wavelengths indicated that the as-grown short aligned SWCNTs showed high selectivity of metallic SWCNTs. Various kinds of materials, such as mica, quartz, Cu foil, and carbon fiber, can serve as the substrates for the growth of perpendicular FeMoMgAl LDH films and also the growth of the short aligned SWCNTs subsequently. These findings highlight the easy route for bulk preferential growth of aligned metallic-rich SWCNTs with well defined length for further bulk characterization and applications. This journal is © The Royal Society of Chemistry 2012

Quantitative analysis of immobilized penicillinase using enzyme-modified AlGaN/GaN field-effect transistors.

PubMed

Müntze, Gesche Mareike; Baur, Barbara; Schäfer, Wladimir; Sasse, Alexander; Howgate, John; Röth, Kai; Eickhoff, Martin

2015-02-15

Penicillinase-modified AlGaN/GaN field-effect transistors (PenFETs) are utilized to systematically investigate the covalently immobilized enzyme penicillinase under different experimental conditions. We demonstrate quantitative evaluation of covalently immobilized penicillinase layers on pH-sensitive field-effect transistors (FETs) using an analytical kinetic PenFET model. This kinetic model is explicitly suited for devices with thin enzyme layers that are not diffusion-limited, as it is the case for the PenFETs discussed here. By means of the kinetic model it was possible to extract the Michaelis constant of covalently immobilized penicillinase as well as relative transport coefficients of the different species associated with the enzymatic reaction which, exempli gratia, give information about the permeability of the enzymatic layer. Based on this analysis we quantify the reproducibility and the stability of the analyzed PenFETs over the course of 33 days as well as the influence of pH and buffer concentration on the properties of the enzymatic layer. Thereby the stability measurements reveal a Michalis constant KM of (67 ± 13)μM while the chronological development of the relative transport coefficients suggests a detachment of physisorbed penicillinase during the first two weeks since production. Our results show that AlGaN/GaN PenFETs prepared by covalent immobilization of a penicillinase enzyme layer present a powerful tool for quantitative analysis of enzyme functionality. Copyright © 2014 Elsevier B.V. All rights reserved.

Decoding the Vertical Phase Separation and Its Impact on C8-BTBT/PS Transistor Properties.

PubMed

Pérez-Rodríguez, Ana; Temiño, Inés; Ocal, Carmen; Mas-Torrent, Marta; Barrena, Esther

2018-02-28

Disentangling the details of the vertical distribution of small semiconductor molecules blended with polystyrene (PS) and the contact properties are issues of fundamental value for designing strategies to optimize small-molecule:polymer blend organic transistors. These questions are addressed here for ultrathin blends of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) and PS processed by a solution-shearing technique using three different blend composition ratios. We show that friction force microscopy (FFM) allows the determination of the lateral and vertical distribution of the two materials at the nanoscale. Our results demonstrate a three-layer stratification of the blend: a film of C8-BTBT of few molecular layers with crystalline order sandwiched between a PS-rich layer at the bottom (a few nm thick) acting as a passivating dielectric layer and a PS-rich skin layer on the top (∼1 nm) conferring stability to the devices. Kelvin probe force microscopy (KPFM) measurements performed in operating organic field-effect transistors (OFETs) reveal that the devices are strongly contact-limited and suggest contact doping as a route for device optimization. By excluding the effect of the contacts, field-effect mobility values in the channel as high as 10 cm 2 V -1 s -1 are obtained. Our findings, obtained via a combination of FFM and KPFM, provide a satisfactory explanation of the different electrical performances of the OFETs as a function of the blend composition ratio and by doping the contacts.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldman, Allen M.

The goal of this program was to study new physical phenomena that might be relevant to the performance of conductive devices and circuits of the smallest realizable feature sizes possible using physical rather than biological techniques. Although the initial scientific work supported involved the use of scanning tunneling microscopy and spectroscopy to ascertain the statistics of the energy level distribution of randomly sized and randomly shaped quantum dots, or nano-crystals, the main focus was on the investigation of selected properties, including superconductivity, of conducting and superconducting nanowires prepared using electron-beam-lithography. We discovered a magnetic-field-restoration of superconductivity in out-of-equilibrium nanowires drivenmore » resistive by current. This phenomenon was explained by the existence of a state in which dissipation coexisted with nonvanishing superconducting order. We also produced ultra-small superconducting loops to study a predicted anomalous fluxoid quantization, but instead, found a magnetic-field-dependent, high-resistance state, rather than superconductivity. Finally, we developed a simple and controllable nanowire in an induced charged layer near the surface of a masked single-crystal insulator, SrTiO 3. The layer was induced using an electric double layer transistor employing an ionic liquid (IL). The transport properties of the induced nanowire resembled those of collective electronic transport through an array of quantum dots.« less

Multiscale modeling and computation of nano-electronic transistors and transmembrane proton channels

NASA Astrophysics Data System (ADS)

Chen, Duan

The miniaturization of nano-scale electronic transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. In biology, proton dynamics and transport across membrane proteins are of paramount importance to the normal function of living cells. Similar physical characteristics are behind the two subjects, and model simulations share common mathematical interests/challenges. In this thesis work, multiscale and multiphysical models are proposed to study the mechanisms of nanotransistors and proton transport in transmembrane at the atomic level. For nano-electronic transistors, we introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential. This framework enables us to put microscopic and macroscopic descriptions on an equal footing at nano-scale. Additionally, this model includes layered structures and random doping effect of nano-transistors. For transmembrane proton channels, we describe proton dynamics quantum mechanically via a density functional approach while implicitly treat numerous solvent molecules as a dielectric continuum. The densities of all other ions in the solvent are assumed to obey the Boltzmann distribution. The impact of protein molecular structure and its charge polarization on the proton transport is considered in atomic details. We formulate a total free energy functional to include kinetic and potential energies of protons, as well as electrostatic energy of all other ions on an equal footing. For both nano-transistors and proton channels systems, the variational principle is employed to derive nonlinear governing equations. The Poisson-Kohn-Sham equations are derived for nano-transistors while the generalized Poisson-Boltzmann equation and Kohn-Sham equation are obtained for proton channels. Related numerical challenges in simulations are addressed: the matched interface and boundary (MIB) method, the Dirichlet-to-Neumann mapping (DNM) technique, and the Krylov subspace and preconditioner theory are introduced to improve the computational efficiency of the Poisson-type equation. The quantum transport theory is employed to solve the Kohn-Sham equation. The Gummel iteration and relaxation technique are utilized for overall self-consistent iterations. Finally, applications are considered and model validations are verified by realistic nano-transistors and transmembrane proteins. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our threedimensional numerical simulations. For these devices, the current uctuation and voltage threshold lowering effect induced by discrete dopants are explored. For proton transport, a realistic channel protein, the Gramicidin A (GA) is used to demonstrate the performance of the proposed proton channel model and validate the efficiency of the proposed mathematical algorithms. The electrostatic characteristics of the GA channel is analyzed with a wide range of model parameters. Proton channel conductances are studied over a number of applied voltages and reference concentrations. Comparisons with experimental data are utilized to verify our model predictions.

Low-voltage organic field effect transistors with a 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene semiconductor layer.

PubMed

Amin, Atefeh Y; Khassanov, Artoem; Reuter, Knud; Meyer-Friedrichsen, Timo; Halik, Marcus

2012-10-10

An asymmetric n-alkyl substitution pattern was realized in 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene (C(13)-BTBT) in order to improve the charge transport properties in organic thin-film transistors. We obtained large hole mobilities up to 17.2 cm(2)/(V·s) in low-voltage operating devices. The large mobility is related to densely packed layers of the BTBT π-systems at the channel interface dedicated to the substitution motif and confirmed by X-ray reflectivity measurements. The devices exhibit promising stability in continuous operation for several hours in ambient air.

Impact of materials engineering on edge placement error (Conference Presentation)

NASA Astrophysics Data System (ADS)

Freed, Regina; Mitra, Uday; Zhang, Ying

2017-04-01

Transistor scaling has transitioned from wavelength scaling to multi-patterning techniques, due to the resolution limits of immersion of immersion lithography. Deposition and etch have enabled scaling in the by means of SADP and SAQP. Spacer based patterning enables extremely small linewidths, sufficient for several future generations of transistors. However, aligning layers in Z-direction, as well as aligning cut and via patterning layers, is becoming a road-block due to global and local feature variation and fidelity. This presentation will highlight the impact of deposition and etch on this feature alignment (EPE) and illustrate potential paths toward lowering EPE using material engineering.

A study of electrically active traps in AlGaN/GaN high electron mobility transistor

NASA Astrophysics Data System (ADS)

Yang, Jie; Cui, Sharon; Ma, T. P.; Hung, Ting-Hsiang; Nath, Digbijoy; Krishnamoorthy, Sriram; Rajan, Siddharth

2013-10-01

We have studied electron conduction mechanisms and the associated roles of the electrically active traps in the AlGaN layer of an AlGaN/GaN high electron mobility transistor structure. By fitting the temperature dependent I-V (Current-Voltage) curves to the Frenkel-Poole theory, we have identified two discrete trap energy levels. Multiple traces of I-V measurements and constant-current injection experiment all confirm that the main role of the traps in the AlGaN layer is to enhance the current flowing through the AlGaN barrier by trap-assisted electron conduction without causing electron trapping.

Quantum-well-base heterojunction bipolar light-emitting transistor

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Chan, R.

2004-03-01

This letter reports the enhanced radiative recombination realized by incorporating InGaAs quantum wells in the base layer of light-emitting InGaP/GaAs heterojunction bipolar transistors (LETs) operating in the common-emitter configuration. Two 50 Å In1-xGaxAs (x=85%) quantum wells (QWs) acting, in effect, as electron capture centers ("traps") are imbedded in the 300 Å GaAs base layer, thus improving (as a "collector" and recombination center) the light emission intensity compared to a similar LET structure without QWs in the base. Gigahertz operation of the QW LET with simultaneously amplified electrical output and an optical output with signal modulation is demonstrated.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Impact of humidity on functionality of on-paper printed electronics.

PubMed

Bollström, Roger; Pettersson, Fredrik; Dolietis, Peter; Preston, Janet; Osterbacka, Ronald; Toivakka, Martti

2014-03-07

A multilayer coated paper substrate, combining barrier and printability properties was manufactured utilizing a pilot-scale slide curtain coating technique. The coating structure consists of a thin mineral pigment layer coated on top of a barrier layer. The surface properties, i.e. smoothness and surface porosity, were adjusted by the choice of calendering parameters. The influence of surface properties on the fine line printability and conductivity of inkjet-printed silver lines was studied. Surface roughness played a significant role when printing narrow lines, increasing the risk of defects and discontinuities, whereas for wider lines the influence of surface roughness was less critical. A smooth, calendered surface resulted in finer line definition, i.e. less edge raggedness. Dimensional stability and its influence on substrate surface properties as well as on the functionality of conductive tracks and transistors were studied by exposure to high/low humidity cycles. The barrier layer of the multilayer coated paper reduced the dimensional changes and surface roughness increase caused by humidity and helped maintain the conductivity of the printed tracks. Functionality of a printed transistor during a short, one hour humidity cycle was maintained, but a longer exposure to humidity destroyed the non-encapsulated transistor.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

In-situ SiN{sub x}/InN structures for InN field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zervos, Ch., E-mail: hzervos@physics.uoc.gr; Georgakilas, A.; Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete

Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performancemore » was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.« less

Near-Infrared to Visible Organic Upconversion Devices Based on Organic Light-Emitting Field Effect Transistors.

PubMed

Li, Dongwei; Hu, Yongsheng; Zhang, Nan; Lv, Ying; Lin, Jie; Guo, Xiaoyang; Fan, Yi; Luo, Jinsong; Liu, Xingyuan

2017-10-18

The near-infrared (NIR) to visible upconversion devices have attracted great attention because of their potential applications in the fields of night vision, medical imaging, and military security. Herein, a novel all-organic upconversion device architecture has been first proposed and developed by incorporating a NIR absorption layer between the carrier transport layer and the emission layer in heterostructured organic light-emitting field effect transistors (OLEFETs). The as-prepared devices show a typical photon-to-photon upconversion efficiency as high as 7% (maximum of 28.7% under low incident NIR power intensity) and millisecond-scale response time, which are the highest upconversion efficiency and one of the fastest response time among organic upconversion devices as referred to the previous reports up to now. The high upconversion performance mainly originates from the gain mechanism of field-effect transistor structures and the unique advantage of OLEFETs to balance between the photodetection and light emission. Meanwhile, the strategy of OLEFETs also offers the advantage of high integration so that no extra OLED is needed in the organic upconversion devices. The results would pave way for low-cost, flexible and portable organic upconversion devices with high efficiency and simplified processing.

The double layers in the plasma sheet boundary layer during magnetic reconnection

NASA Astrophysics Data System (ADS)

Guo, J.; Yu, B.

2014-11-01

We studied the evolutions of double layers which appear after the magnetic reconnection through two-dimensional electromagnetic particle-in-cell simulation. The simulation results show that the double layers are formed in the plasma sheet boundary layer after magnetic reconnection. At first, the double layers which have unipolar structures are formed. And then the double layers turn into bipolar structures, which will couple with another new weak bipolar structure. Thus a new double layer or tripolar structure comes into being. The double layers found in our work are about several ten Debye lengths, which accords with the observation results. It is suggested that the electron beam formed during the magnetic reconnection is responsible for the production of the double layers.

Tunneling and Origin of Large Access Resistance in Layered-Crystal Organic Transistors

NASA Astrophysics Data System (ADS)

Hamai, Takamasa; Arai, Shunto; Minemawari, Hiromi; Inoue, Satoru; Kumai, Reiji; Hasegawa, Tatsuo

2017-11-01

Layered crystallinity of organic semiconductors is crucial to obtaining high-performance organic thin-film transistors (OTFTs), as it allows both smooth-channel-gate-insulator interface formation and efficient two-dimensional carrier transport along the interface. However, the role of vertical transport across the crystalline molecular layers in device operations has not been a crucial subject so far. Here, we show that the interlayer carrier transport causes unusual nonlinear current-voltage characteristics and enormous access resistance in extremely high-quality single-crystal OTFTs based on 2-decyl-7-phenyl[1]-benzothieno[3 ,2 -b ][1]benzothiophene (Ph -BTBT -C10 ) that involve inherent multiple semiconducting π -conjugated layers interposed, respectively, by electrically inert alkyl-chain layers. The output characteristics present layer-number (n )-dependent nonlinearity that becomes more evident at larger n (1 ≤n ≤15 ), demonstrating tunneling across multiple alkyl-chain layers. The n -dependent device mobility and four-probe measurements reveal that the alkyl-chain layers generate a large access resistance that suppresses the device mobility from the intrinsic value of about 20 cm2 V-1 s-1 . Our findings clarify the reason why device characteristics are distributed in single-crystal OTFTs.

Self-Organization of Ions at the Interface between Graphene and Ionic Liquid DEME-TFSI.

PubMed

Hu, Guangliang; Pandey, Gaind P; Liu, Qingfeng; Anaredy, Radhika S; Ma, Chunrui; Liu, Ming; Li, Jun; Shaw, Scott K; Wu, Judy

2017-10-11

Electrochemical effects manifest as nonlinear responses to an applied electric field in electrochemical devices, and are linked intimately to the molecular orientation of ions in the electric double layer (EDL). Herein, we probe the origin of the electrochemical effect using a double-gate graphene field effect transistor (GFET) of ionic liquid N,N-diethyl-N-(2-methoxyethyl)-N-methylammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI) top-gate, paired with a ferroelectric Pb 0.92 La 0.08 Zr 0.52 Ti 0.48 O 3 (PLZT) back-gate of compatible gating efficiency. The orientation of the interfacial molecular ions can be extracted by measuring the GFET Dirac point shift, and their dynamic response to ultraviolet-visible light and a gate electric field was quantified. We have observed that the strong electrochemical effect is due to the TFSI anions self-organizing on a treated GFET surface. Moreover, a reversible order-disorder transition of TFSI anions self-organized on the GFET surface can be triggered by illuminating the interface with ultraviolet-visible light, revealing that it is a useful method to control the surface ion configuration and the overall performance of the device.

Rectifying behavior in the GaN/graded-AlxGa1‑xN/GaN double heterojunction structure

NASA Astrophysics Data System (ADS)

Wang, Caiwei; Jiang, Yang; Ma, Ziguang; Zuo, Peng; Yan, Shen; Die, Junhui; Wang, Lu; Jia, Haiqiang; Wang, Wenxin; Chen, Hong

2018-05-01

Rectifying characteristics induced by the polarization fields are achieved in the GaN/graded-AlxGa1‑xN/GaN double heterojunction structure (DHS). By grading AlxGa1‑xN from x  =  0.4(0.3) to 0.1, the DHS displays a better conductivity for smaller reverse bias than for forward bias voltages (reverse rectifying behavior) which is opposite to p–n junction rectifying characteristics. The mechanism of reverse rectifying behavior is illustrated via calculating the energy band structures of the samples. The band gap narrowing caused by decreasing Al composition could compensate the for the band tilt due to the polarization effect in AlxGa1‑xN barriers, thus lowering the barrier height for electron transport from top to bottom. The reverse rectifying behavior could be enhanced by increasing the Al content and the thickness of the multi-layer graded AlxGa1‑xN barriers. This work gives a better understanding of the mechanism of carrier transport in a DHS and makes it possible to realize novel GaN-based heterojunction transistors.

Field-Induced Disorder and Carrier Localization in Molecular Organic Transistors

NASA Astrophysics Data System (ADS)

Ando, M.; Minakata, T.; Duffy, C.; Sirringhaus, H.

2009-06-01

We propose a "field-induced polymorphous disorder" model to explain bias-stress instability in molecular organic thin-film transistors, based on the experimental results showing the strong correlation between the micro-structural change in semiconductor layer composed of penrtacene molecules and the threshold voltage (Vth) shift due to electron trapping in a reversible manner under the successive bias-stress, thermal annealing, and light irradiation.

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

PubMed

Moon, Kyeong-Ju; Lee, Tae-Il; Lee, Sang-Hoon; Han, Young-Uk; Ham, Moon-Ho; Myoung, Jae-Min

2012-07-25

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

NASA Astrophysics Data System (ADS)

Xu, Jing; Jiang, Shu-Ye; Zhang, Min; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2018-03-01

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Chemical free device fabrication of two dimensional van der Waals materials based transistors by using one-off stamping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Young Tack, E-mail: 023273@kist.re.kr, E-mail: stunalren@gmail.com; Choi, Won Kook; Materials and Life Science Research Division, Korea Institute of Science and Technology

We report on a chemical free one-off imprinting method to fabricate two dimensional (2D) van der Waals (vdWs) materials based transistors. Such one-off imprinting technique is the simplest and effective way to prevent unintentional chemical reaction or damage of 2D vdWs active channel during device fabrication process. 2D MoS{sub 2} nanosheets based transistors with a hexagonal-boron-nitride (h-BN) passivation layer, prepared by one-off imprinting, show negligible variations of transfer characteristics after chemical vapor deposition process. In addition, this method enables the fabrication of all 2D MoS{sub 2} transistors consisting of h-BN gate insulator, and graphene source/drain and gate electrodes without anymore » chemical damage.« less

Negative differential resistance in GaN tunneling hot electron transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Zhichao; Nath, Digbijoy; Rajan, Siddharth

Room temperature negative differential resistance is demonstrated in a unipolar GaN-based tunneling hot electron transistor. Such a device employs tunnel-injected electrons to vary the electron energy and change the fraction of reflected electrons, and shows repeatable negative differential resistance with a peak to valley current ratio of 7.2. The device was stable when biased in the negative resistance regime and tunable by changing collector bias. Good repeatability and double-sweep characteristics at room temperature show the potential of such device for high frequency oscillators based on quasi-ballistic transport.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V. A. L.

2013-02-01

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics.The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics. Electronic supplementary information (ESI) available: UV-vis spectrum of Au nanoparticle aqueous solution, transfer characteristics of the transistors without inserting an Au nanoparticle monolayer, AFM image of the pentacene layer, transfer characteristics at different program voltages and memory windows with respect to the P/E voltage. See DOI: 10.1039/c2nr32579a

On utilizing alternating current-flow field effect transistor for flexibly manipulating particles in microfluidics and nanofluidics

PubMed Central

Liu, Weiyu; Shao, Jinyou; Ren, Yukun; Liu, Jiangwei; Tao, Ye; Jiang, Hongyuan; Ding, Yucheng

2016-01-01

By imposing a biased gate voltage to a center metal strip, arbitrary symmetry breaking in induced-charge electroosmotic flow occurs on the surface of this planar gate electrode, a phenomenon termed as AC-flow field effect transistor (AC-FFET). In this work, the potential of AC-FFET with a shiftable flow stagnation line to flexibly manipulate micro-nano particle samples in both a static and continuous flow condition is demonstrated via theoretical analysis and experimental validation. The effect of finite Debye length of induced double-layer and applied field frequency on the manipulating flexibility factor for static condition is investigated, which indicates AC-FFET turns out to be more effective for achieving a position-controllable concentrating of target nanoparticle samples in nanofluidics compared to the previous trial in microfluidics. Besides, a continuous microfluidics-based particle concentrator/director is developed to deal with incoming analytes in dynamic condition, which exploits a design of tandem electrode configuration to consecutively flow focus and divert incoming particle samples to a desired downstream branch channel, as prerequisite for a following biochemical analysis. Our physical demonstrations with AC-FFET prove valuable for innovative designs of flexible electrokinetic frameworks, which can be conveniently integrated with other microfluidic or nanofluidic components into a complete lab-on-chip diagnostic platform due to a simple electrode structure. PMID:27190570

On utilizing alternating current-flow field effect transistor for flexibly manipulating particles in microfluidics and nanofluidics.

PubMed

Liu, Weiyu; Shao, Jinyou; Ren, Yukun; Liu, Jiangwei; Tao, Ye; Jiang, Hongyuan; Ding, Yucheng

2016-05-01

By imposing a biased gate voltage to a center metal strip, arbitrary symmetry breaking in induced-charge electroosmotic flow occurs on the surface of this planar gate electrode, a phenomenon termed as AC-flow field effect transistor (AC-FFET). In this work, the potential of AC-FFET with a shiftable flow stagnation line to flexibly manipulate micro-nano particle samples in both a static and continuous flow condition is demonstrated via theoretical analysis and experimental validation. The effect of finite Debye length of induced double-layer and applied field frequency on the manipulating flexibility factor for static condition is investigated, which indicates AC-FFET turns out to be more effective for achieving a position-controllable concentrating of target nanoparticle samples in nanofluidics compared to the previous trial in microfluidics. Besides, a continuous microfluidics-based particle concentrator/director is developed to deal with incoming analytes in dynamic condition, which exploits a design of tandem electrode configuration to consecutively flow focus and divert incoming particle samples to a desired downstream branch channel, as prerequisite for a following biochemical analysis. Our physical demonstrations with AC-FFET prove valuable for innovative designs of flexible electrokinetic frameworks, which can be conveniently integrated with other microfluidic or nanofluidic components into a complete lab-on-chip diagnostic platform due to a simple electrode structure.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chun-Lan; Yuan, Hongtao; Li, Yanbin

Electric-double-layer (EDL) gating with liquid electrolyte has been a powerful tool widely used to explore emerging interfacial electronic phenomena. Due to the large EDL capacitance, a high carrier density up to 10 14 cm –2 can be induced, directly leading to the realization of field-induced insulator to metal (or superconductor) transition. However, the liquid nature of the electrolyte has created technical issues including possible side electrochemical reactions or intercalation, and the potential for huge strain at the interface during cooling. In addition, the liquid coverage of active devices also makes many surface characterizations and in situ measurements challenging. Here, wemore » demonstrate an all solid-state EDL device based on a solid superionic conductor LaF 3, which can be used as both a substrate and a fluorine ionic gate dielectric to achieve a wide tunability of carrier density without the issues of strain or electrochemical reactions and can expose the active device surface for external access. Based on LaF 3 EDL transistors (EDLTs), we observe the metal–insulator transition in MoS 2. Interestingly, the well-defined crystal lattice provides a more uniform potential distribution in the substrate, resulting in less interface electron scattering and therefore a higher mobility in MoS 2 transistors. Finally, this result shows the powerful gating capability of LaF 3 solid electrolyte for new possibilities of novel interfacial electronic phenomena.« less

Vibrational and optical properties of MoS2: From monolayer to bulk

NASA Astrophysics Data System (ADS)

Molina-Sánchez, Alejandro; Hummer, Kerstin; Wirtz, Ludger

2015-12-01

Molybdenum disulfide, MoS2, has recently gained considerable attention as a layered material where neighboring layers are only weakly interacting and can easily slide against each other. Therefore, mechanical exfoliation allows the fabrication of single and multi-layers and opens the possibility to generate atomically thin crystals with outstanding properties. In contrast to graphene, it has an optical gap of ~1.9 eV. This makes it a prominent candidate for transistor and opto-electronic applications. Single-layer MoS2 exhibits remarkably different physical properties compared to bulk MoS2 due to the absence of interlayer hybridization. For instance, while the band gap of bulk and multi-layer MoS2 is indirect, it becomes direct with decreasing number of layers. In this review, we analyze from a theoretical point of view the electronic, optical, and vibrational properties of single-layer, few-layer and bulk MoS2. In particular, we focus on the effects of spin-orbit interaction, number of layers, and applied tensile strain on the vibrational and optical properties. We examine the results obtained by different methodologies, mainly ab initio approaches. We also discuss which approximations are suitable for MoS2 and layered materials. The effect of external strain on the band gap of single-layer MoS2 and the crossover from indirect to direct band gap is investigated. We analyze the excitonic effects on the absorption spectra. The main features, such as the double peak at the absorption threshold and the high-energy exciton are presented. Furthermore, we report on the the phonon dispersion relations of single-layer, few-layer and bulk MoS2. Based on the latter, we explain the behavior of the Raman-active A1g and E2g1 modes as a function of the number of layers. Finally, we compare theoretical and experimental results of Raman, photoluminescence, and optical-absorption spectroscopy.

Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer

DOEpatents

Chavarkar, Prashant; Smorchkova, Ioulia P.; Keller, Stacia; Mishra, Umesh; Walukiewicz, Wladyslaw; Wu, Yifeng

2005-02-01

A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an Al.sub.y Ga.sub.1-y N (y=1 or y 1) layer on the GaN buffer layer. An Al.sub.x Ga.sub.1-x N (0.ltoreq.x.ltoreq.0.5) barrier layer on to the Al.sub.y Ga.sub.1-y N layer, opposite the GaN buffer layer, Al.sub.y Ga.sub.1-y N layer having a higher Al concentration than that of the Al.sub.x Ga.sub.1-x N barrier layer. A preferred Al.sub.y Ga.sub.1-y N layer has y=1 or y.about.1 and a preferred Al.sub.x Ga.sub.1-x N barrier layer has 0.ltoreq.x.ltoreq.0.5. A 2DEG forms at the interface between the GaN buffer layer and the Al.sub.y Ga.sub.1-y N layer. Respective source, drain and gate contacts are formed on the Al.sub.x Ga.sub.1-x N barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the Al.sub.y Ga.sub.1-y N layer and a nucleation layer between the Al.sub.x Ga.sub.1-x N buffer layer and the substrate.

General strategy for biodetection in high ionic strength solutions using transistor-based nanoelectronic sensors.

PubMed

Gao, Ning; Zhou, Wei; Jiang, Xiaocheng; Hong, Guosong; Fu, Tian-Ming; Lieber, Charles M

2015-03-11

Transistor-based nanoelectronic sensors are capable of label-free real-time chemical and biological detection with high sensitivity and spatial resolution, although the short Debye screening length in high ionic strength solutions has made difficult applications relevant to physiological conditions. Here, we describe a new and general strategy to overcome this challenge for field-effect transistor (FET) sensors that involves incorporating a porous and biomolecule permeable polymer layer on the FET sensor. This polymer layer increases the effective screening length in the region immediately adjacent to the device surface and thereby enables detection of biomolecules in high ionic strength solutions in real-time. Studies of silicon nanowire field-effect transistors with additional polyethylene glycol (PEG) modification show that prostate specific antigen (PSA) can be readily detected in solutions with phosphate buffer (PB) concentrations as high as 150 mM, while similar devices without PEG modification only exhibit detectable signals for concentrations ≤10 mM. Concentration-dependent measurements exhibited real-time detection of PSA with a sensitivity of at least 10 nM in 100 mM PB with linear response up to the highest (1000 nM) PSA concentrations tested. The current work represents an important step toward general application of transistor-based nanoelectronic detectors for biochemical sensing in physiological environments and is expected to open up exciting opportunities for in vitro and in vivo biological sensing relevant to basic biology research through medicine.

High Electron Mobility Thin‐Film Transistors Based on Solution‐Processed Semiconducting Metal Oxide Heterojunctions and Quasi‐Superlattices

PubMed Central

Lin, Yen‐Hung; Faber, Hendrik; Labram, John G.; Stratakis, Emmanuel; Sygellou, Labrini; Kymakis, Emmanuel; Hastas, Nikolaos A.; Li, Ruipeng; Zhao, Kui; Amassian, Aram; Treat, Neil D.; McLachlan, Martyn

2015-01-01

High mobility thin‐film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin‐film transistors is reported that exploits the enhanced electron transport properties of low‐dimensional polycrystalline heterojunctions and quasi‐superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band‐like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature‐dependent electron transport and capacitance‐voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas‐like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll‐to‐roll, etc.) and can be seen as an extremely promising technology for application in next‐generation large area optoelectronics such as ultrahigh definition optical displays and large‐area microelectronics where high performance is a key requirement. PMID:27660741

Stretchable metal oxide thin film transistors on engineered substrate for electronic skin applications.

PubMed

Romeo, Alessia; Lacour, Stphanie P

2015-08-01

Electronic skins aim at providing distributed sensing and computation in a large-area and elastic membrane. Control and addressing of high-density soft sensors will be achieved when thin film transistor matrices are also integrated in the soft carrier substrate. Here, we report on the design, manufacturing and characterization of metal oxide thin film transistors on these stretchable substrates. The TFTs are integrated onto an engineered silicone substrate with embedded strain relief to protect the devices from catastrophic cracking. The TFT stack is composed of an amorphous In-Ga-Zn-O active layer, a hybrid AlxOy/Parylene dielectric film, gold electrodes and interconnects. All layers are prepared and patterned with planar, low temperature and dry processing. We demonstrate the interconnected IGZO TFTs sustain applied tensile strain up to 20% without electrical degradation and mechanical fracture. Active devices are critical for distributed sensing. The compatibility of IGZO TFTs with soft and biocompatible substrates is an encouraging step towards wearable electronic skins.

Influence of the morphology of the copper(II) phthalocyanine thin film on the performance of organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Jing; Liu, Xueqiang; Wang, Hailong; Hou, Wenlong; Zhao, Lele; Zhang, Haiquan

2017-01-01

Organic thin-film transistors (OTFTs) with high crystallization copper phthalocyanine (CuPc) active layers were fabricated. The performance of CuPc OTFTs was studied without and with treatment by Solvent Vapor Annealing on CuPc film. The values of the threshold voltage without and with solvent-vapor annealing are -17 V and -10.5 V respectively. The field-effect mobility values in saturation region of CuPc thin-film transistors without and with Solvent Vapor Annealing are 0.00027 cm2/V s and 0.0025 cm2/V s respectively. Meanwhile, the high crystallization of the CuPc film with a larger grain size and less grain boundaries can be observed by investigating the morphology of the CuPc active layer through scanning electron microscopy and X-ray diffraction. The experimental results showed the decreased of the resistance of the conducting channel, that led to a performance improvement of the OTFTs.

Fabrication of Organic Transistors Using Nanomaterials for Sensing Applications

NASA Astrophysics Data System (ADS)

Harb, Mohamed E.; Ebrahim, Shaker; Soliman, Moataz; Shabana, Mahmoud

2018-01-01

In this work, an organic field-effect transistor (OFET) was fabricated and characterized based on the bottom contact of a polyaniline (PANI) or PANI/TiO2 nanocomposite as an active layer and SiO2 as an insulating layer to be used for ammonia gas sensing applications. The OFET sensors exhibited a change in the drain current when exposed to NH3. Titanium dioxide (TiO2) nanoparticles with different weight percentages (0-50 wt.%) were added to dope PANI and enhance charge carrier transport, although the response of both the PANI OFET sensor and PANI/TiO2 OFET sensor has reached saturation value at almost the same period. The response of PANI/TiO2 transistor is (2.5), which is much higher than that of PANI (0.17). The results showed that the sensor response of the OFET device fabricated with PANI/TiO2 is 15 times greater than that with an OFET device fabricated using pristine PANI.

Atomic Scale Dynamics of Contact Formation in the Cross-Section of InGaAs Nanowire Channels

DOE PAGES

Chen, Renjie; Jungjohann, Katherine L.; Mook, William M.; ...

2017-03-23

In the alloyed and compound contacts between metal and semiconductor transistor channels we see that they enable self-aligned gate processes which play a significant role in transistor scaling. At nanoscale dimensions and for nanowire channels, prior experiments focused on reactions along the channel length, but the early stage of reaction in their cross sections remains unknown. We report on the dynamics of the solid-state reaction between metal (Ni) and semiconductor (In 0.53Ga 0.47As), along the cross-section of nanowires that are 15 nm in width. Unlike planar structures where crystalline nickelide readily forms at conventional, low alloying temperatures, nanowires exhibit amore » solid-state amorphization step that can undergo a crystal regrowth step at elevated temperatures. Here, we capture the layer-by-layer reaction mechanism and growth rate anisotropy using in situ transmission electron microscopy (TEM). Our kinetic model depicts this new, in-plane contact formation which could pave the way for engineered nanoscale transistors.« less

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

effect of the parameters of AlN/GaN/AlGaN and AlN/GaN/InAlN heterostructures with a two-dimensional electron gas on their electrical properties and the characteristics of transistors on their basis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsatsulnikov, A. F., E-mail: andrew@beam.ioffe.ru; Lundin, V. W.; Zavarin, E. E.

The effect of the layer thickness and composition in AlGaN/AlN/GaN and InAlN/AlN/GaN transistor heterostructures with a two-dimensional electron gas on their electrical and the static parameters of test transistors fabricated from such heterostructures are experimentally and theoretically studied. It is shown that the use of an InAlN barrier layer instead of AlGaN results in a more than twofold increase in the carrier concentration in the channel, which leads to a corresponding increase in the saturation current. In situ dielectric-coating deposition on the InAlN/AlN/GaN heterostructure surface during growth process allows an increase in the maximum saturation current and breakdown voltages whilemore » retaining high transconductance.« less

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Han, Dong-Suk; Moon, Yeon-Keon; Lee, Sih; Kim, Kyung-Taek; Moon, Dae-Yong; Lee, Sang-Ho; Kim, Woong-Sun; Park, Jong-Wan

2012-09-01

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage ( V ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

NASA Astrophysics Data System (ADS)

Han, C. Y.; Qian, L. X.; Leung, C. H.; Che, C. M.; Lai, P. T.

2013-07-01

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

AlGaN/GaN High Electron Mobility Transistor Grown and Fabricated on ZrTi Metallic Alloy Buffer Layers

DOE PAGES

Ren, Fan; Pearton, Stephen J.; Ahn, Shihyun; ...

2017-09-26

AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated for structures grown on ZrTi metallic alloy buffer layers, which provided lattice matching of the in-plane lattice parameter (“a-parameter”) to hexagonal GaN. The quality of the GaN buffer layer and HEMT structure were confirmed with X-ray 2θ and rocking scans as well as cross-section transmission electron microscopy (TEM) images. The X-ray 2θ scans showed full widths at half maximum (FWHM) of 0.06°, 0.05° and 0.08° for ZrTi alloy, GaN buffer layer, and the entire HEMT structure, respectively. TEM of the lower section of the HEMT structure containing the GaN buffer layer andmore » the AlN/ZrTi/AlN stack on the Si substrate showed that it was important to grow AlN on the top of ZrTi prior to growing the GaN buffer layer. Finally, the estimated threading dislocation (TD) density in the GaN channel layer of the HEMT structure was in the 10 8 cm -2 range.« less

Modulation of the operational characteristics of amorphous In-Ga-Zn-O thin-film transistors by In2O3 nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Min-Jung; Lee, Tae Il; Park, Jee Ho; Kim, Jung Han; Chae, Gee Sung; Jun, Myung Chul; Hwang, Yong Kee; Baik, Hong Koo; Lee, Woong; Myoung, Jae-Min

2012-05-01

The structure of thin-film transistors (TFTs) based on amorphous In-Ga-Zn-O (a-IGZO) was modified by spin coating a suspension of In2O3 nanoparticles on a SiO2/p++ Si layered wafer surface prior to the deposition of IGZO layer by room-temperature sputtering. The number of particles per unit area (surface density) of the In2O3 nanoparticles could be controlled by applying multiple spin coatings of the nanoparticle suspension. During the deposition of IGZO, the In2O3 nanoparticles initially located on the substrate surface migrated to the top of the IGZO layer indicating that they were not embedded within the IGZO layer, but they supplied In to the IGZO layer to increase the In concentration in the channel layer. As a result, the channel characteristics of the a-IGZO TFT were modulated so that the device showed an enhanced performance as compared with the reference device prepared without the nanoparticle treatment. Such an improved device performance is attributed to the nano-scale changes in the structure of (InO)n ordering assisted by increased In concentration in the amorphous channel layer.

Organic permeable-base transistors - superb power efficiency at highest frequencies (Conference Presentation)

NASA Astrophysics Data System (ADS)

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Scholz, Reinhard; Lüssem, Björn; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Kasemann, Daniel; Leo, Karl

2016-11-01

Organic field-effect transistors (OFET) are important elements in thin-film electronics, being considered for flat-panel or flexible displays, radio frequency identification systems, and sensor arrays. To optimize the devices for high-frequency operation, the channel length, defined as the horizontal distance between the source and the drain contact, can be scaled down. Here, an architecture with a vertical current flow, in particular the Organic Permeable-Base Transistors (OPBT), opens up new opportunities, because the effective transit length in vertical direction is precisely tunable in the nanometer range by the thickness of the semiconductor layer. We present an advanced OPBT, competing with best OFETs while a low-cost, OLED-like fabrication with low-resolution shadow masks is used (Klinger et al., Adv. Mater. 27, 2015). Its design consists of a stack of three parallel electrodes separated by two semiconductor layers of C60 . The vertical current flow is controlled by the middle base electrode with nano-sized openings passivated by an native oxide. Using insulated layers to structure the active area, devices show an on/off ratio of 10⁶ , drive 11 A/cm² at an operation voltage of 1 V, and have a low subthreshold slope of 102 mV/decade. These OPBTs show a unity current-gain transit frequency of 2.2 MHz and off-state break-down fields above 1 MV/cm. Thus, our optimized setup does not only set a benchmark for vertical organic transistors, but also outperforms best lateral OFETs using similar low-cost structuring techniques in terms of power efficiency at high frequencies.

Organic Field Effect Transistors for Large Format Electronics

DTIC Science & Technology

2003-06-19

calculated output characteristics for a p-channel substrate insulator Organic layer Source Drain Gate 6 pentacene OFET with 2µm source to drain spacing...conventional transistors. Figure 3. Calculated output characteristics of a pentacene OFET with image charge induced contact barrier...Cross section view of a part of an OFET in the vicinity of a source or drain contact. local ordering due to surface energy effects. The development of

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Chemical stability and electrical performance of dual-active-layered zinc-tin-oxide/indium-gallium-zinc-oxide thin-film transistors using a solution process.

PubMed

Kim, Chul Ho; Rim, You Seung; Kim, Hyun Jae

2013-07-10

We investigated the chemical stability and electrical properties of dual-active-layered zinc-tin-oxide (ZTO)/indium-gallium-zinc-oxide (IGZO) structures (DALZI) with the durability of the chemical damage. The IGZO film was easily corroded or removed by an etchant, but the DALZI film was effectively protected by the high chemical stability of ZTO. Furthermore, the electrical performance of the DALZI thin-film transistor (TFT) was improved by densification compared to the IGZO TFT owing to the passivation of the pin holes or pore sites and the increase in the carrier concentration due to the effect of Sn(4+) doping.

Investigation of an anomalous hump phenomenon in via-type amorphous In-Ga-Zn-O thin-film transistors under positive bias temperature stress

NASA Astrophysics Data System (ADS)

Yang, Jianwen; Liao, Po-Yung; Chang, Ting-Chang; Chen, Bo-Wei; Huang, Hui-Chun; Su, Wan-Ching; Chiang, Hsiao-Cheng; Zhang, Qun

2017-04-01

Amorphous InGaZnO thin film transistors (a-IGZO TFTs) with an etching-stop layer (ESL) exhibit an anomalous negative shift of threshold voltage (Vth) under positive bias temperature stress. TFTs with wider and shorter channels show a clear hump phenomenon, resulting from the existence of both main channels and parasitic channels. The electrons trapped in the gate insulator are responsible for the positive shift in the main channel characteristics. The electrons trapped near the IGZO edges and the holes injected into the ESL layer above InGaZnO (IGZO) jointly determine the shift of the parasitic TFT performance.

Study of InGaAs-based modulation doped field effect transistor structures using variable-angle spectroscopic ellipsometry

NASA Technical Reports Server (NTRS)

Alterovitz, S. A.; Sieg, R. M.; Yao, H. D.; Snyder, P. G.; Woollam, J. A.; Pamulapati, J.; Bhattacharya, P. K.; Sekula-Moise, P. A.

1991-01-01

Variable-angle spectroscopic ellipsometry was used to estimate the thicknesses of all layers within the optical penetration depth of InGaAs-based modulation doped field effect transistor structures. Strained and unstrained InGaAs channels were made by molecular beam epitaxy (MBE) on InP substrates and by metal-organic chemical vapor deposition on GaAs substrates. In most cases, ellipsometrically determined thicknesses were within 10% of the growth-calibration results. The MBE-made InGaAs strained layers showed large strain effects, indicating a probable shift in the critical points of their dielectric function toward the InP lattice-matched concentration.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

PubMed

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

Improved electron injection in all-solution-processed n-type organic field-effect transistors with an inkjet-printed ZnO electron injection layer

NASA Astrophysics Data System (ADS)

Roh, Jeongkyun; Kim, Hyeok; Park, Myeongjin; Kwak, Jeonghun; Lee, Changhee

2017-10-01

Interface engineering for the improved injection properties of all-solution-processed n-type organic field-effect transistors (OFETs) arising from the use of an inkjet-printed ZnO electron injection layer were demonstrated. The characteristics of ZnO in terms of electron injection and transport were investigated, and then we employed ZnO as the electron injection layer via inkjet-printing during the fabrication of all-solution-processed, n-type OFETs. With the inkjet-printed ZnO electron injection layer, the devices exhibited approximately five-fold increased mobility (0.0058 cm2/V s to 0.030 cm2/V s), more than two-fold increased charge concentration (2.76 × 1011 cm-2 to 6.86 × 1011 cm-2), and two orders of magnitude reduced device resistance (120 MΩ cm to 3 MΩ cm). Moreover, n-type polymer form smoother film with ZnO implying denser packing of polymer, which results in higher mobility.

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Sangsoo; Son, Yong-Hoon; Semiconductor R and D Center, Samsung Electronics Co., Ltd., Hwasung 445-701

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers weremore » shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.« less

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Effect of Al doping on performance of ZnO thin film transistors

NASA Astrophysics Data System (ADS)

Dong, Junchen; Han, Dedong; Li, Huijin; Yu, Wen; Zhang, Shendong; Zhang, Xing; Wang, Yi

2018-03-01

In this work, we investigate the Aluminum-doped Zinc Oxide (AZO) thin films and their feasibility as the active layer for thin film transistors (TFTs). A comparison on performance is made between the AZO TFTs and ZnO TFTs. The electrical properties such as saturation mobility, subthreshold swing, and on-to-off current ratio are improved when AZO is utilized as the active layer. Oxygen component of the thin film materials indicates that Al is the suppressor for oxygen defect in active layer, which improves the subthreshold swing. Moreover, based on band structure analyzation, we observe that the carrier concentration of AZO is higher than ZnO, leading to the enhancement of saturation mobility. The microstructure of the thin films convey that the AZO films exhibit much smaller grain boundaries than ZnO films, which results in the lower off-state current and higher on-to-off current ratio of AZO TFTs. The AZO thin films show huge potential to be the active layer of TFTs.

Research on liquid impact forming technology of double-layered tubes

NASA Astrophysics Data System (ADS)

Sun, Changying; Liu, Jianwei; Yao, Xinqi; Huang, Beixing; Li, Yuhan

2018-03-01

A double-layered tube is widely used and developed in various fields because of its perfect comprehensive performance and design. With the advent of the era of a double-layered tube, the requirements for double layered tube forming quality, manufacturing cost and forming efficiency are getting higher, so forming methods of a double-layered tube are emerged in an endless stream, the forming methods of a double-layered tube have a great potential in the future. The liquid impact forming technology is a combination of stamping technology and hydroforming technology. Forming a double-layered tube has huge advantages in production cost, quality and efficiency.

Langmuir probe measurements of double-layers in a pulsed discharge

NASA Technical Reports Server (NTRS)

Levine, J. S.; Crawford, F. W.

1980-01-01

Langmuir probe measurements were carried out which confirm the occurrence of double-layers in an argon positive column. Pulsing the discharge current permitted probe measurements to be performed in the presence of the double-layer. Supplementary evidence, obtained from DC and pulsed discharges, indicated that the double-layers formed in the two modes of operation were similar. The double-layers observed were weak and stable; their relation to other classes of double-layers are discussed, and directions for future work are suggested.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Organic electrochemical transistors for cell-based impedance sensing

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Ramuz, Marc; Leleux, Pierre; Hama, Adel; Huerta, Miriam; Owens, Roisin M.

2015-01-01

Electrical impedance sensing of biological systems, especially cultured epithelial cell layers, is now a common technique to monitor cell motion, morphology, and cell layer/tissue integrity for high throughput toxicology screening. Existing methods to measure electrical impedance most often rely on a two electrode configuration, where low frequency signals are challenging to obtain for small devices and for tissues with high resistance, due to low current. Organic electrochemical transistors (OECTs) are conducting polymer-based devices, which have been shown to efficiently transduce and amplify low-level ionic fluxes in biological systems into electronic output signals. In this work, we combine OECT-based drain current measurements with simultaneous measurement of more traditional impedance sensing using the gate current to produce complex impedance traces, which show low error at both low and high frequencies. We apply this technique in vitro to a model epithelial tissue layer and show that the data can be fit to an equivalent circuit model yielding trans-epithelial resistance and cell layer capacitance values in agreement with literature. Importantly, the combined measurement allows for low biases across the cell layer, while still maintaining good broadband signal.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Tailoring the charge carrier in few layers MoS2 field-effect transistors by Au metal adsorbate

NASA Astrophysics Data System (ADS)

Singh, Arun Kumar; Pandey, Rajiv K.; Prakash, Rajiv; Eom, Jonghwa

2018-04-01

It is an essential to tune the charge carrier concentrations in semiconductor in order to approach high-performance of the electronic and optoelectronic devices. Here, we report the effect of thin layer of gold (Au) metal on few layer (FL) molybdenum disulfide (MoS2) by atomic force microscopy (AFM), Raman spectroscopy and electrical charge transport measurements. The Raman spectra and charge transport measurements show that Au thin layer affect the electronic properties of the FL MoS2. After deposition of Au thin layer, the threshold voltages of FL MoS2 field-effect transistors (FETs) shift towards positive gate voltages, this reveal the p-doping in FL MoS2 nanosheets. The shift of peak frequencies of the Raman bands are also analyzed after the deposition of Au metal films of different thickness on FL MoS2 nanosheets. The surface morphology of Au metal on FL MoS2 is characterized by AFM and shows the smoother and denser film in comparison to Au metal on SiO2.

Combinatorial study of zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Field-induced strain degradation of AlGaN/GaN high electron mobility transistors on a nanometer scale

NASA Astrophysics Data System (ADS)

Lin, Chung-Han; Doutt, D. R.; Mishra, U. K.; Merz, T. A.; Brillson, L. J.

2010-11-01

Nanoscale Kelvin probe force microscopy and depth-resolved cathodoluminescence spectroscopy reveal an electronic defect evolution inside operating AlGaN/GaN high electron mobility transistors with degradation under electric-field-induced stress. Off-state electrical stress results in micron-scale areas within the extrinsic drain expanding and decreasing in electric potential, midgap defects increasing by orders-of-magnitude at the AlGaN layer, and local Fermi levels lowering as gate-drain voltages increase above a characteristic stress threshold. The pronounced onset of defect formation, Fermi level movement, and transistor degradation at the threshold gate-drain voltage of J. A. del Alamo and J. Joh [Microelectron. Reliab. 49, 1200 (2009)] is consistent with crystal deformation and supports the inverse piezoelectric model of high electron mobility transistor degradation.

Localized heating on silicon field effect transistors: device fabrication and temperature measurements in fluid.

PubMed

Elibol, Oguz H; Reddy, Bobby; Nair, Pradeep R; Dorvel, Brian; Butler, Felice; Ahsan, Zahab S; Bergstrom, Donald E; Alam, Muhammad A; Bashir, Rashid

2009-10-07

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Effect of spin-orbit coupling on excitonic levels in layered chalcogenide-fluorides

NASA Astrophysics Data System (ADS)

Zakutayev, Andriy; Kykyneshi, Robert; Kinney, Joseph; McIntyre, David H.; Schneider, Guenter; Tate, Janet

2008-03-01

BaCuChF (Ch=S,Se,Te) comprise a family of wide-bandgap p-type semiconductors. Due to their high transparency and conductivity, they have potential applications as components of transparent thin-film transistors, solar cells and light-emitting devices. Thin films of BaCuChF have been deposited on MgO by pulsed laser deposition (PLD). Solid solutions BaCuS1-xSexTeF and BaCuSe1-xTex have been prepared by PLD of alternating thin BaCuChF layers. All films were deposited at elevated substrate temperatures. They are preferentially c-axis oriented, conductive and transparent in the visible part of the spectrum. Double excitonic peaks have been observed in the absorption spectrum of these films in the temperature range from 80 to 300K. The separation between the peaks in the doublet increases with the increase of atomic mass of the chalcogen. It also increases with the increase of the heavy chalcogen component x in the solid solutions. This separation most likely is caused by the effect of spin-orbit coupling in the chalcogen atoms on excitonic levels in BaCuChF.

GaN light-emitting device based on ionic liquid electrolyte

NASA Astrophysics Data System (ADS)

Hirai, Tomoaki; Sakanoue, Tomo; Takenobu, Taishi

2018-06-01

Ionic liquids (ILs) are attractive materials for fabricating unique hybrid devices based on electronics and electrochemistry; thus, IL-gated transistors and organic light-emitting devices of light-emitting electrochemical cells (LECs) are investigated for future low-voltage and high-performance devices. In LECs, voltage application induces the formation of electrochemically doped p–n homojunctions owing to ion rearrangements in composites of semiconductors and electrolytes, and achieves electron–hole recombination for light emission at the homojunctions. In this work, we applied this concept of IL-induced electrochemical doping to the fabrication of GaN-based light-emitting devices. We found that voltage application to the layered IL/GaN structure accumulated electrons on the GaN surface owing to ion rearrangements and improved the conductivity of GaN. The ion rearrangement also enabled holes to be injected by the strong electric field of electric double layers on hole injection contacts. This simultaneous injection of holes and electrons into GaN mediated by ions achieves light emission at a low voltage of around 3.4 V. The light emission from the simple IL/GaN structure indicates the usefulness of an electrochemical technique in generating light emission with great ease of fabrication.

Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

PubMed

Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

2014-02-25

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

Effects of surface passivation dielectrics on carrier transport in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Oh, Sejoon; Jang, Han-Soo; Choi, Chel-Jong; Cho, Jaehee

2018-04-01

Dielectric layers prepared by different deposition methods were used for the surface passivation of AlGaN/GaN heterostructure field-effect transistors (HFETs) and the corresponding electrical characteristics were examined. Increases in the sheet charge density and the maximum drain current by approximately 45% and 28%, respectively, were observed after the deposition of a 100 nm-thick SiO2 layer by plasma-enhanced chemical vapor deposition (PECVD) on the top of the AlGaN/GaN HFETs. However, SiO2 deposited by a radio frequency (rf) sputter system had the opposite effect. As the strain applied to AlGaN was influenced by the deposition methods used for the dielectric layers, the carrier transport in the two-dimensional electron gas formed at the interface between AlGaN and GaN was affected accordingly.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Enhancement of near-infrared detectability from InGaZnO thin film transistor with MoS2 light absorbing layer.

PubMed

Pak, Sang Woo; Chu, Dongil; Song, Da Ye; Lee, Seung Kyo; Kim, Eun Kyu

2017-11-24

We report an enhancement of near-infrared (NIR) detectability from amorphous InGaZnO (α-IGZO) thin film transistor in conjunction with randomly distributed molybdenum disulfide (MoS 2 ) flakes. The electrical characteristics of the α-IGZO grown by radio-frequency magnetron sputtering exhibit high effective mobility exceeding 15 cm 2 V -1 s -1 and current on/off ratio up to 10 7 . By taking advantages of the high quality α-IGZO and MoS 2 light absorbing layer, photodetection spectra are able to extend from ultra-violet to NIR range. The α-IGZO channel detector capped by MoS 2 show a photo-responsivity of approximately 14.9 mA W -1 at 1100 nm wavelength, which is five times higher than of the α-IGZO device without MoS 2 layer.

Enhancement of near-infrared detectability from InGaZnO thin film transistor with MoS2 light absorbing layer

NASA Astrophysics Data System (ADS)

Pak, Sang Woo; Chu, Dongil; Song, Da Ye; Kyo Lee, Seung; Kim, Eun Kyu

2017-11-01

We report an enhancement of near-infrared (NIR) detectability from amorphous InGaZnO (α-IGZO) thin film transistor in conjunction with randomly distributed molybdenum disulfide (MoS2) flakes. The electrical characteristics of the α-IGZO grown by radio-frequency magnetron sputtering exhibit high effective mobility exceeding 15 cm2 V-1 s-1 and current on/off ratio up to 107. By taking advantages of the high quality α-IGZO and MoS2 light absorbing layer, photodetection spectra are able to extend from ultra-violet to NIR range. The α-IGZO channel detector capped by MoS2 show a photo-responsivity of approximately 14.9 mA W-1 at 1100 nm wavelength, which is five times higher than of the α-IGZO device without MoS2 layer.

Electrical instability of InGaZnO thin-film transistors with and without titanium sub-oxide layer under light illumination

NASA Astrophysics Data System (ADS)

Chiu, Y. C.; Zheng, Z. W.; Cheng, C. H.; Chen, P. C.; Yen, S. S.; Fan, C. C.; Hsu, H. H.; Kao, H. L.; Chang, C. Y.

2017-03-01

The electrical instability behaviors of amorphous indium-gallium-zinc oxide thin-film transistors with and without titanium sub-oxide passivation layer were investigated under light illumination in this study. For the unpassivated IGZO TFT device, in contrast with the dark case, a noticeable increase of the sub-threshold swing was observed when under the illumination environment, which can be attributed to the generation of ionized oxygen vacancies within the α-IGZO active layer by high energy photons. For the passivated TFT device, the much smaller SS of 70 mV/dec and high device mobility of >100 cm2/Vs at a drive voltage of 3 V with negligible degradation under light illumination are achieved due to the passivation effect of n-type titanium sub-oxide semiconductor, which may create potential application for high-performance display.

Strain-Modulated Bandgap and Piezo-Resistive Effect in Black Phosphorus Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Zhang, Zuocheng; Li, Likai; Horng, Jason; Wang, Nai Zhou; Yang, Fangyuan; Yu, Yijun; Zhang, Yu; Chen, Guorui; Watanabe, Kenji; Taniguchi, Takashi; Chen, Xian Hui; Wang, Feng; Zhang, Yuanbo

2017-10-01

Energy bandgap largely determines the optical and electronic properties of a semiconductor. Variable bandgap therefore makes versatile functionality possible in a single material. In layered material black phosphorus, the bandgap can be modulated by the number of layers; as a result, few-layer black phosphorus has discrete bandgap values that are relevant for opto-electronic applications in the spectral range from red, in monolayer, to mid-infrared in the bulk limit. Here, we further demonstrate continuous bandgap modulation by mechanical strain applied through flexible substrates. The strain-modulated bandgap significantly alters the charge transport in black phosphorus at room temperature; we for the first time observe a large piezo-resistive effect in black phosphorus field-effect transistors (FETs). The effect opens up opportunities for future development of electro-mechanical transducers based on black phosphorus, and we demonstrate strain gauges constructed from black phosphorus thin crystals.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Bottom-gate poly-Si thin-film transistors by nickel silicide seed-induced lateral crystallization with self-aligned lightly doped layer

NASA Astrophysics Data System (ADS)

Lee, Sol Kyu; Seok, Ki Hwan; Chae, Hee Jae; Lee, Yong Hee; Han, Ji Su; Jo, Hyeon Ah; Joo, Seung Ki

2017-03-01

We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm2/Vs.

Strain-Modulated Bandgap and Piezo-Resistive Effect in Black Phosphorus Field-Effect Transistors.

PubMed

Zhang, Zuocheng; Li, Likai; Horng, Jason; Wang, Nai Zhou; Yang, Fangyuan; Yu, Yijun; Zhang, Yu; Chen, Guorui; Watanabe, Kenji; Taniguchi, Takashi; Chen, Xian Hui; Wang, Feng; Zhang, Yuanbo

2017-10-11

Energy bandgap largely determines the optical and electronic properties of a semiconductor. Variable bandgap therefore makes versatile functionality possible in a single material. In layered material black phosphorus, the bandgap can be modulated by the number of layers; as a result, few-layer black phosphorus has discrete bandgap values that are relevant for optoelectronic applications in the spectral range from red, in monolayer, to mid-infrared in the bulk limit. Here, we further demonstrate continuous bandgap modulation by mechanical strain applied through flexible substrates. The strain-modulated bandgap significantly alters the density of thermally activated carriers; we for the first time observe a large piezo-resistive effect in black phosphorus field-effect transistors (FETs) at room temperature. The effect opens up opportunities for future development of electromechanical transducers based on black phosphorus, and we demonstrate an ultrasensitive strain gauge constructed from black phosphorus thin crystals.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

NASA Astrophysics Data System (ADS)

Li, Yi-Shao; Wu, Chun-Yi; Chou, Chia-Hsin; Liao, Chan-Yu; Chuang, Kai-Chi; Luo, Jun-Dao; Li, Wei-Shuo; Cheng, Huang-Chung

2018-06-01

A tetraethyl-orthosilicate (TEOS) capping oxide was deposited by low-pressure chemical vapor deposition (LPCVD) on a 200-nm-thick amorphous Si (a-Si) film as a heat reservoir to improve the crystallinity and surface roughness of polycrystalline silicon (poly-Si) formed by continuous-wave laser crystallization (CLC). The effects of four thicknesses of the capping oxide layer to satisfy an antireflection condition, namely, 90, 270, 450, and 630 nm, were investigated. The largest poly-Si grain size of 2.5 × 20 µm2 could be achieved using a capping oxide layer with an optimal thickness of 450 nm. Moreover, poly-Si nanorod (NR) thin-film transistors (TFTs) fabricated using the aforementioned technique exhibited a superior electron field-effect mobility of 1093.3 cm2 V‑1 s‑1 and an on/off current ratio of 2.53 × 109.

Formation of low resistivity titanium silicide gates in semiconductor integrated circuits

DOEpatents

Ishida, Emi [Sunnyvale, CA

1999-08-10

A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

A possible high-mobility signal in bulk MoTe2: Temperature independent weak phonon decay

NASA Astrophysics Data System (ADS)

Li, Titao; Zhang, Zhaojun; Zheng, Wei; Lv, Yangyang; Huang, Feng

2016-11-01

Layered transition metal dichalcogenides (TMDs) have attracted great attention due to their non-zero bandgap for potential application in high carrier mobility devices. Recent studies demonstrate that the carrier mobility of MoTe2 would decrease by orders of magnitude when used for few-layer transistors. As phonon scattering has a significant influence on carrier mobility of layered material, here, we first reported temperature-dependent Raman spectra of bulk 2H-MoTe2 from 80 to 300 K and discovered that the phonon lifetime of both E12g and A1g vibration modes are independent with temperature. These results were explained by the weak phonon decay in MoTe2. Our results imply the existence of a carrier mobility higher than the theoretical value in intrinsic bulk 2H-MoTe2 and the feasibility to obtain MoTe2-based transistors with sufficiently high carrier mobility.

AlGaN channel field effect transistors with graded heterostructure ohmic contacts

NASA Astrophysics Data System (ADS)

Bajaj, Sanyam; Akyol, Fatih; Krishnamoorthy, Sriram; Zhang, Yuewei; Rajan, Siddharth

2016-09-01

We report on ultra-wide bandgap (UWBG) Al0.75Ga0.25N channel metal-insulator-semiconductor field-effect transistors (MISFETs) with heterostructure engineered low-resistance ohmic contacts. The low intrinsic electron affinity of AlN (0.6 eV) leads to large Schottky barriers at the metal-AlGaN interface, resulting in highly resistive ohmic contacts. In this work, we use a reverse compositional graded n++ AlGaN contact layer to achieve upward electron affinity grading, leading to a low specific contact resistance (ρsp) of 1.9 × 10-6 Ω cm2 to n-Al0.75Ga0.25N channels (bandgap ˜5.3 eV) with non-alloyed contacts. We also demonstrate UWBG Al0.75Ga0.25N channel MISFET device operation employing the compositional graded n++ ohmic contact layer and 20 nm atomic layer deposited Al2O3 as the gate-dielectric.

AlGaN/GaN field effect transistors for power electronics—Effect of finite GaN layer thickness on thermal characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hodges, C., E-mail: chris.hodges@bristol.ac.uk; Anaya Calvo, J.; Kuball, M.

2013-11-11

AlGaN/GaN heterostructure field effect transistors with a 150 nm thick GaN channel within stacked Al{sub x}Ga{sub 1−x}N layers were investigated using Raman thermography. By fitting a thermal simulation to the measured temperatures, the thermal conductivity of the GaN channel was determined to be 60 W m{sup −1} K{sup −1}, over 50% less than typical GaN epilayers, causing an increased peak channel temperature. This agrees with a nanoscale model. A low thermal conductivity AlGaN buffer means the GaN spreads heat; its properties are important for device thermal characteristics. When designing power devices with thin GaN layers, as well as electrical considerations, the reducedmore » channel thermal conductivity must be considered.« less

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

Potentiometric Detection of Pathogens

DTIC Science & Technology

2012-01-01

nanosize organic electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field...electrode (conducting polymer top-layer) surface. This approach has then been changed to the gate modification in ion sensitive field effect transistors, in...the conducting polymer top-layer, which makes the devices very functional and competitive. Secondly, the device development is discussed and finally

Double layers and circuits in astrophysics

NASA Technical Reports Server (NTRS)

Alfven, Hannes

1986-01-01

As the rate of energy release in a double layer with voltage delta V is P approx I delta V, a double layer must be treated as a part of a circuit which delivers the current I. As neither double layer nor circuit can be derived from magnetofluid models of a plasma, such models are useless for treating energy transfer by means of double layers. They must be replaced by particle models and circuit theory. A simple circuit is suggested which is applied to the energizing of auroral particles, to solar flares, and to intergalactic double radio sources. Application to the heliospheric current systems leads to the prediction of two double layers on the Sun's axis which may give radiations detectable from Earth. Double layers in space should be classified as a new type of celestial object (one example is the double radio sources). It is tentatively suggested in X-ray and Gamma-ray bursts may be due to exploding double layers (although annihilation is an alternative energy source). A study of how a number of the most used textbooks in astrophysics treat important concepts like double layers, critical velocity, pinch effects and circuits is made.

Step buffer layer of Al0.25Ga0.75N/Al0.08Ga0.92N on P-InAlN gate normally-off high electron mobility transistors

NASA Astrophysics Data System (ADS)

Shrestha, Niraj M.; Li, Yiming; Chang, E. Y.

2016-07-01

Normally-off AlGaN/GaN high electron mobility transistors (HEMTs) are indispensable devices for power electronics as they can greatly simplify circuit designs in a cost-effective way. In this work, the electrical characteristics of p-type InAlN gate normally-off AlGaN/GaN HEMTs with a step buffer layer of Al0.25Ga0.75N/Al0.1Ga0.9N is studied numerically. Our device simulation shows that a p-InAlN gate with a step buffer layer allows the transistor to possess normally-off behavior with high drain current and high breakdown voltage simultaneously. The gate modulation by the p-InAlN gate and the induced holes appearing beneath the gate at the GaN/Al0.25Ga0.75N interface is because a hole appearing in the p-InAlN layer can effectively vary the threshold voltage positively. The estimated threshold voltage of the normally-off HEMTs explored is 2.5 V at a drain bias of 25 V, which is 220% higher than the conventional p-AlGaN normally-off AlGaN/GaN gate injection transistor (GIT). Concurrently, the maximum current density of the explored HEMT at a drain bias of 10 V slightly decreases by about 7% (from 240 to 223 mA mm-1). At a drain bias of 15 V, the current density reached 263 mA mm-1. The explored structure is promising owing to tunable positive threshold voltage and the maintenance of similar current density; notably, its breakdown voltage significantly increases by 36% (from 800 V, GIT, to 1086 V). The engineering findings of this study indicate that novel p-InAlN for both the gate and the step buffer layer can feature a high threshold voltage, large current density and high operating voltage for advanced AlGaN/GaN HEMT devices.

Quantum Devices and Structures Using Si-Based Molecular Beam Epitaxy

DTIC Science & Technology

1991-05-15

the MBE growth studies of Sii_..,Ge./Si superlattices and the fabrication of resonant tunneling devices. 1 In the following we highlight the...relaxation was obtained.[7] A new approach in growth of strained layers on a patterned substrate was implemented. Permeable transistors and tunneling ...Fig. 5(b) shows a hot hole transistor using a superlattice base and resonant tunneling injector. In order to facilitate the design of such devices

Models and Measurements for Multi-Layer Displays

DTIC Science & Technology

2006-07-26

measurements. The observed statistical variation in the data results from laser speckle. No systematic uncertainties, which are expected to be less...difference metric. There are also some powerful statistical techniques to deal with this type of experiment, although it would take a lot of time to...hTraceWidth,vTraceWidth] in 10s of micrometers % Transitor sixe is vector : [hTransistorSize,vTransistorSize] in 10s of micrometers %Image is plotted if

Towards colorless transparent organic transistors: potential of benzothieno[3,2-b]benzothiophene-based wide-gap semiconductors.

PubMed

Moon, Hanul; Cho, Hyunsu; Kim, Mincheol; Takimiya, Kazuo; Yoo, Seunghyup

2014-05-21

Colorless, highly transparent organic thin-film transistors (TOTFTs) with high performance are realized based on benzothieno[3,2-b]benzothiophene (BTBT) derivatives that simultaneously exhibit a wide energy gap and high transport properties. Multilayer transparent source/drain electrodes maintain the transparency, and ultrathin fluoropolymer dielectric layers enable stable, low-voltage operation of the proposed TOTFTs. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Princeton VLSI Project.

DTIC Science & Technology

1983-01-01

polysilicon wires in gateleft and laterighi, which will be connected together if both exist. The dimensions of the transistor are determined by the maximum...be implanted. Any wire parameters having layers other than polysilicon or diffusion will be electrically connected to one another over the transistor...Jan 19 ś a’:’> ., , fcr example PLA s and precharged 2-1, (do- : CV O. lHop The implementtional d( :a., of the mod;,ied gates and circuitrv for OL 5

I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Cody; Hunt, Mitchell; Ho, Fat D.; MacLeod, Todd C.

2012-01-01

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

Enzyme-polyelectrolyte multilayer assemblies on reduced graphene oxide field-effect transistors for biosensing applications.

PubMed

Piccinini, Esteban; Bliem, Christina; Reiner-Rozman, Ciril; Battaglini, Fernando; Azzaroni, Omar; Knoll, Wolfgang

2017-06-15

We present the construction of layer-by-layer (LbL) assemblies of polyethylenimine and urease onto reduced-graphene-oxide based field-effect transistors (rGO FETs) for the detection of urea. This versatile biosensor platform simultaneously exploits the pH dependency of liquid-gated graphene-based transistors and the change in the local pH produced by the catalyzed hydrolysis of urea. The use of an interdigitated microchannel resulted in transistors displaying low noise, high pH sensitivity (20.3µA/pH) and transconductance values up to 800 µS. The modification of rGO FETs with a weak polyelectrolyte improved the pH response because of its transducing properties by electrostatic gating effects. In the presence of urea, the urease-modified rGO FETs showed a shift in the Dirac point due to the change in the local pH close to the graphene surface. Markedly, these devices operated at very low voltages (less than 500mV) and were able to monitor urea in the range of 1-1000µm, with a limit of detection (LOD) down to 1µm, fast response and good long-term stability. The urea-response of the transistors was enhanced by increasing the number of bilayers due to the increment of the enzyme surface coverage onto the channel. Moreover, quantification of the heavy metal Cu 2+ (with a LOD down to 10nM) was performed in aqueous solution by taking advantage of the urease specific inhibition. Copyright © 2016 The Authors. Published by Elsevier B.V. All rights reserved.

Simulation of plasma double-layer structures

NASA Technical Reports Server (NTRS)

Borovsky, J. E.; Joyce, G.

1982-01-01

Electrostatic plasma double layers are numerically simulated by means of a magnetized 2 1/2 dimensional particle in cell method. The investigation of planar double layers indicates that these one dimensional potential structures are susceptible to periodic disruption by instabilities in the low potential plasmas. Only a slight increase in the double layer thickness with an increase in its obliqueness to the magnetic field is observed. Weak magnetization results in the double layer electric field alignment of accelerated particles and strong magnetization results in their magnetic field alignment. The numerical simulations of spatially periodic two dimensional double layers also exhibit cyclical instability. A morphological invariance in two dimensional double layers with respect to the degree of magnetization implies that the potential structures scale with Debye lengths rather than with gyroradii. Electron beam excited electrostatic electron cyclotron waves and (ion beam driven) solitary waves are present in the plasmas adjacent to the double layers.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges

NASA Astrophysics Data System (ADS)

Bansal, Monika; Kaur, Harsupreet

2018-05-01

In this work, a comprehensive drain current model has been developed for long channel Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-pFET) by using 1-D Poisson's equation and Landau-Khalatnikov equation. The model takes into account interface trap charges and by using the derived model various parameters such as surface potential, gain, gate capacitance, subthreshold swing, drain current, transconductance, output conductance and Ion/Ioff ratio have been obtained and it is demonstrated that by incorporating ferroelectric material as gate insulator with Ge-channel, subthreshold swing values less than 60 mV/dec can be achieved along with improved gate controllability and current drivability. Further, to critically analyze the advantages offered by NCGe-DG-pFET, a detailed comparison has been done with Germanium Double Gate p-type Field Effect Transistor (Ge-DG-pFET) and it is shown that NCGe-DG-pFET exhibits high gain, enhanced transport efficiency in channel, very less or negligible degradation in device characteristics due to interface trap charges as compared to Ge-DG-pFET. The analytical results so obtained show good agreement with simulated results obtained from Silvaco ATLAS TCAD tool.

Materials and methods for the preparation of nanocomposites

DOEpatents

Nag, Angshuman; Talapin, Dmitri V.

2018-01-30

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

Stable room temperature magnetocurrent in electrodeposited permeable n-type metal base transistor

NASA Astrophysics Data System (ADS)

Silva, G. V. O.; Teixeira, H. A.; Mello, S. L. A.; de Araujo, C. I. L.

2018-02-01

We investigated a permeable metal base transistor consisting of a ZnO/NiFe/Si heterostructure. Both ZnO and NiFe layers were grown by electrodeposition techniques, using only adhesive tape masks to define deposition regions. The base permeability can thus be controlled by varying the NiFe deposition time. We report here our best results obtained for the permeable NiFe base close to the electrical percolation threshold, which gives reasonable sensitivity to the device. Magnetocurrent measurements carried out at room temperature show that this permeable metal base transistor is stable and sensitive under applied magnetic fields of low intensities, ˜100 Oe, required for electronics integration.

Energetic distributions of interface states Dit(phi sub s) of MOS transistors in extension of Kuhn's quasistatic C(V)-method

NASA Astrophysics Data System (ADS)

Krautschneider, W.; Wagemann, H. G.

1983-10-01

Kuhn's quasi-static C(V)-method has been extended to MOS transistors by considering the capacitances of the source and drain p-n junctions additionally to the MOS varactor circuit model. The width of the space charge layers w(phi sub s) is calculated as a function of the surface potential phi sub s and applied to the MOS capacitance as a function of the gate voltage. Capacitance behavior for different channel length is presented as a model and compared to measurement results and evaluations of energetic distributions of interface states Dit(phi sub s) for MOS transistor and MOS varactor on the same chip.

Catalytic activity of enzymes immobilized on AlGaN /GaN solution gate field-effect transistors

NASA Astrophysics Data System (ADS)

Baur, B.; Howgate, J.; von Ribbeck, H.-G.; Gawlina, Y.; Bandalo, V.; Steinhoff, G.; Stutzmann, M.; Eickhoff, M.

2006-10-01

Enzyme-modified field-effect transistors (EnFETs) were prepared by immobilization of penicillinase on AlGaN /GaN solution gate field-effect transistors. The influence of the immobilization process on enzyme functionality was analyzed by comparing covalent immobilization and physisorption. Covalent immobilization by Schiff base formation on GaN surfaces modified with an aminopropyltriethoxysilane monolayer exhibits high reproducibility with respect to the enzyme/substrate affinity. Reductive amination of the Schiff base bonds to secondary amines significantly increases the stability of the enzyme layer. Electronic characterization of the EnFET response to penicillin G indicates that covalent immobilization leads to the formation of an enzyme (sub)monolayer.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.