Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Wafer screening device and methods for wafer screening

DOEpatents

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

High-performance fused indium gallium arsenide/silicon photodiode

NASA Astrophysics Data System (ADS)

Kang, Yimin

Modern long haul, high bit rate fiber-optic communication systems demand photodetectors with high sensitivity. Avalanche photodiodes (APDs) exhibit superior sensitivity performance than other types of photodetectors by virtual of its internal gain mechanism. This dissertation work further advances the APD performance by applying a novel materials integration technique. It is the first successful demonstration of wafer fused InGaAs/Si APDs with low dark current and low noise. APDs generally adopt separate absorption and multiplication (SAM) structure, which allows independent optimization of materials properties in two distinct regions. While the absorption material needs to have high absorption coefficient in the target wavelength range to achieve high quantum efficiency, it is desirable for the multiplication material to have large discrepancy between its electron and hole ionization coefficients to reduce noise. According to these criteria, InGaAs and Si are the ideal materials combination. Wafer fusion is the enabling technique that makes this theoretical ideal an experimental possibility. APDs fabricated on the fused InGaAs/Si wafer with mesa structure exhibit low dark current and low noise. Special device fabrication techniques and high quality wafer fusion reduce dark current to nano ampere level at unity gain, comparable to state-of-the-art commercial III/V APDs. The small excess noise is attributed to the large difference in ionization coefficients between electrons and holes in silicon. Detailed layer structure designs are developed specifically for fused InGaAs/Si APDs based on principles similar to those used in traditional InGaAs/InP APDs. An accurate yet straightforward technique for device structural parameters extraction is also proposed. The extracted results from the fabricated APDs agree with device design parameters. This agreement also confirms that the fusion interface has negligible effect on electric field distributions for devices fabricated from high quality fusion materials. The feasibility of fused InGaAs/Si APD for analog systems is also explored. Preliminary two-tone measurement shows that a moderately high dynamic range of 70 dBc/Hz1/2 for broadband Spur Free Dynamic Range (SFDR) or 82 dBc/Hz2/3 suboctave SFDR, up to 50 muA of optical current, can be achieved. The theoretical analyses of SNR show that fused InGaAs/Si APD receivers can provide larger Signal-to-Noise Ratio (SNR) than their III/V counterparts.

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Production of Optical Quality Free Standing Diamond Wafer

DTIC Science & Technology

2008-05-19

Title : Production of Optical Quality Free Standing Diamond Wafer Prime Contractor : Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568...www.onyxoptics.com Program Manager : Helmuth Meissner Onyx Optics, Inc. 6551 Sierra Lane Dublin, CA 94568 Email: hmeissner@onyxoptics.com Ph: 925...PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING

Surface quality of silicon wafer improved by hydrodynamic effect polishing

NASA Astrophysics Data System (ADS)

Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

2014-08-01

Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Wafer-scale pixelated detector system

DOEpatents

Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

2017-10-17

A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Design Study of Wafer Seals for Future Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

A method to monitor the quality of ultra-thin nitride for trench DRAM with a buried strap structure

NASA Astrophysics Data System (ADS)

Wu, Yung-Hsien; Wang, Chun-Yao; Chang, Ian; Kao, Chien-Kang; Kuo, Chia-Ming; Ku, Alex

2007-02-01

A new approach to monitor the quality of an ultra-thin nitride film has been proposed. The nitride quality is monitored by observing the oxide thickness for the nitride film after wet oxidation since the resistance to oxidation strongly depends on its quality. To obtain a stable oxide thickness without interference from extrinsic factors for process monitoring, monitor wafers without dilute HF solution clean are suggested because the native-oxide containing surface is less sensitive to oxygen and therefore forms the nitride film with stable quality. In addition, the correlation between variable retention time (VRT) performance of a real dynamic random access memory (DRAM) product and oxide thickness from different nitride process temperatures can be successfully explained and this correlation can also be used to establish the appropriate oxide thickness range for process monitoring.

Inverse axial mounting stiffness design for lithographic projection lenses.

PubMed

Wen-quan, Yuan; Hong-bo, Shang; Wei, Zhang

2014-09-01

In order to balance axial mounting stiffness of lithographic projection lenses and the image quality under dynamic working conditions, an easy inverse axial mounting stiffness design method is developed in this article. Imaging quality deterioration at the wafer under different axial vibration levels is analyzed. The desired image quality can be determined according to practical requirements, and axial vibrational tolerance of each lens is solved with the damped least-squares method. Based on adaptive interval adjustment, a binary search algorithm, and the finite element method, the axial mounting stiffness of each lens can be traveled in a large interval, and converges to a moderate numerical solution which makes the axial vibrational amplitude of the lens converge to its axial vibrational tolerance. Model simulation is carried out to validate the effectiveness of the method.

Forming n/p Junctions With An Excimer Laser

NASA Technical Reports Server (NTRS)

Alexander, Paul, Jr.; Campbell, Robert B.; Wong, David C.; Bottenberg, William L.; Byron, Stanley

1988-01-01

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE PAGES

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

2016-07-04

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

NASA Astrophysics Data System (ADS)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

Thin edge-defined film-fed growth (EFG) octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1992-03-01

Mobil Solar Energy Corp. investigated manufacturing crystalline silicon wafers using the edge-defined film-fed growth (EFG) technique. This report identifies the following: (1) current capabilities for manufacturing 200-micron-thick crystalline silicon wafers (10 cm x 10 cm) produced by growing octagons using the EFG technique and laser cutting them into wafers; (2) potential manufacturing improvements from decreasing the thickness of the wafers, improving the quality of the laser cut edge, and increasing cutting speed, all of which lead to reduce manufacturing costs, improved performance, and increased production capacities; (3) problems that impede achieving these potentials; and (4) costs and other requirements involved in overcoming the problems.

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

PubMed

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Investigation of hyper-NA scanner emulation for photomask CDU performance

NASA Astrophysics Data System (ADS)

Poortinga, Eric; Scheruebl, Thomas; Conley, Will; Sundermann, Frank

2007-02-01

As the semiconductor industry moves toward immersion lithography using numerical apertures above 1.0 the quality of the photomask becomes even more crucial. Photomask specifications are driven by the critical dimension (CD) metrology within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately, tolerances of device electrical properties drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process, and photomask quality. Tightening of photomask specifications is one mechanism for meeting the wafer CD targets. The challenge lies in determining how photomask level metrology results influence wafer level imaging performance. Can it be inferred that photomask level CD performance is the direct contributor to wafer level CD performance? With respect to phase shift masks, criteria such as phase and transmission control are generally tightened with each technology node. Are there other photomask relevant influences that effect wafer CD performance? A comprehensive study is presented supporting the use of scanner emulation based photomask CD metrology to predict wafer level within chip CD uniformity (CDU). Using scanner emulation with the photomask can provide more accurate wafer level prediction because it inherently includes all contributors to image formation related to the 3D topography such as the physical CD, phase, transmission, sidewall angle, surface roughness, and other material properties. Emulated images from different photomask types were captured to provide CD values across chip. Emulated scanner image measurements were completed using an AIMS TM45-193i with its hyper-NA, through-pellicle data acquisition capability including the Global CDU Map TM software option for AIMS TM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CDU data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using scanner emulation based photomask CD metrology.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Soft x-ray speckle from rough surfaces

NASA Astrophysics Data System (ADS)

Porter, Matthew Stanton

Dynamic light scattering has been of great use in determining diffusion times for polymer solutions. At the same time, polymer thin films are becoming of increasing importance, especially in the semiconductor industry where they are used as photoresists and interlevel dielectrics. As the dimensions of these devices decrease we will reach a point where lasers will no longer be able to probe the length scales of interest. Current laser wavelengths limit the size of observable diffusion lengths to 180-700 nm. This dissertation will discuss attempts at pushing dynamic fight scattering experiments into the soft x-ray region so that we can examine fluctuations in polymer thin films on the molecular length scale. The dissertation explores the possibility of carrying out a dynamic light scattering experiment in the soft x-ray regime. A detailed account of how to meet the basic requirements for a coherent scattering experiment in the soft x-ray regime win be given. In addition, a complete description of the chamber design will be discussed. We used our custom designed scattering chamber to collect reproducible coherent soft x-ray scattering data from etched silicon wafers and from polystyrene coated silicon wafers. The data from the silicon wafers followed the statistics for a well-developed speckle pattern while the data from the polystyrene films exhibited Poisson statistics. We used the data from both the etched wafers and the polystyrene coated wafers to place a lower limit of ~20 Å on the RMS surface roughness of samples which will produce well defined speckle patterns for the current detector setup. Future experiments which use the criteria set forth in this dissertation have the opportunity to be even more successful than this dissertation project.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

MOCVD process technology for affordable, high-yield, high-performance MESFET structures. Phase 3: MIMIC

NASA Astrophysics Data System (ADS)

1993-01-01

Under the MIMIC Program, Spire has pursued improvements in the manufacturing of low cost, high quality gallium arsenide MOCVD wafers for advanced MIMIC FET applications. As a demonstration of such improvements, Spire was tasked to supply MOCVD wafers for comparison to MBE wafers in the fabrication of millimeter and microwave integrated circuits. In this, the final technical report for Spire's two-year MIMIC contract, we report the results of our work. The main objectives of Spire's MIMIC Phase 3 Program, as outlined in the Statement of Work, were as follows: Optimize the MOCVD growth conditions for the best possible electrical and morphological gallium arsenide. Optimization should include substrate and source qualification as well as determination of the optimum reactor growth conditions; Perform all work on 75 millimeter diameter wafers, using a reactor capable of at least three wafers per run; and Evaluate epitaxial layers using electrical, optical, and morphological tests to obtain thickness, carrier concentration, and mobility data across wafers.

Improving Resonance Characteristics of Gas Sensors by Chemical Etching of Quartz Plates

NASA Astrophysics Data System (ADS)

Raicheva, Z.; Georgieva, V.; Grechnikov, A.; Gadjanova, V.; Angelov, Ts; Vergov, L.; Lazarov, Y.

2012-12-01

The paper presents the results of the influence of the etching process of AT-cut quartz plates on the resonance parameters and the QCM sensors. Quartz wafers (100 μm thick, with a diameter of 8 mm), divided into five groups, have been etched in [NH4]2 F2: H2O = 1:1 solution at temperatures in the range from 70°C to 90°C. The influence of etching temperature on the surface morphology of quartz wafers has been estimated by Atomic Force Microscopy (AFM). A correlation between the etching temperature and the dynamic characteristics is obtained. The optimal etching conditions for removing the surface damages caused by the mechanical treatment of the quartz wafers and for obtaining a clean surface were determined. The typical parameters of fabricated resonators on the quartz plates etched in the temperature range from 70°C to 90°C are as follows: Frequency, Fs 16 MHz ± 100 kHz Motional resistance, Rs less 10 Ω Motional inductance, Lq higher than 3 mH Motional capacitance, Cq less 30 fF Static capacitance, Co around 5 pF Quality factor, Q from 46 000 to 70 000 Sorption properties of QCM - MoO3 are evaluated at NH3 concentrations in the interval from 100 ppm to 500 ppm.

Photolithography and Selective Etching of an Array of Quartz Tuning Fork Resonators with Improved Impact Resistance Characteristics

NASA Astrophysics Data System (ADS)

Lee, Sungkyu

2001-08-01

Quartz tuning fork blanks with improved impact-resistant characteristics for use in Qualcomm mobile station modem (MSM)-3000 central processing unit (CPU) chips for code division multiple access (CDMA), personal communication system (PCS), and global system for mobile communication (GSM) systems were designed using finite element method (FEM) analysis and suitable processing conditions were determined for the reproducible precision etching of a Z-cut quartz wafer into an array of tuning forks. Negative photoresist photolithography for the additive process was used in preference to positive photoresist photolithography for the subtractive process to etch the array of quartz tuning forks. The tuning fork pattern was transferred via a conventional photolithographical chromium/quartz glass template using a standard single-sided aligner and subsequent negative photoresist development. A tightly adhering and pinhole-free 600/2000 Å chromium/gold mask was coated over the developed photoresist pattern which was subsequently stripped in acetone. This procedure was repeated on the back surface of the wafer. With the protective metallization area of the tuning fork geometry thus formed, etching through the quartz wafer was performed at 80°C in a ± 1.5°C controlled bath containing a concentrated solution of ammonium bifluoride to remove the unwanted areas of the quartz wafer. The quality of the quartz wafer surface finish after quartz etching depended primarily on the surface finish of the quartz wafer prior to etching and the quality of quartz crystals used. Selective etching of a 100 μm quartz wafer could be achieved within 90 min at 80°C. A selective etching procedure with reproducible precision has thus been established and enables the photolithographic mass production of miniature tuning fork resonators.

Reduction of image-based ADI-to-AEI overlay inconsistency with improved algorithm

NASA Astrophysics Data System (ADS)

Chen, Yen-Liang; Lin, Shu-Hong; Chen, Kai-Hsiung; Ke, Chih-Ming; Gau, Tsai-Sheng

2013-04-01

In image-based overlay (IBO) measurement, the measurement quality of various measurement spectra can be judged by quality indicators and also the ADI-to-AEI similarity to determine the optimum light spectrum. However we found some IBO measured results showing erroneous indication of wafer expansion from the difference between the ADI and the AEI maps, even after their measurement spectra were optimized. To reduce this inconsistency, an improved image calculation algorithm is proposed in this paper. Different gray levels composed of inner- and outer-box contours are extracted to calculate their ADI overlay errors. The symmetry of intensity distribution at the thresholds dictated by a range of gray levels is used to determine the particular gray level that can minimize the ADI-to-AEI overlay inconsistency. After this improvement, the ADI is more similar to AEI with less expansion difference. The same wafer was also checked by the diffraction-based overlay (DBO) tool to verify that there is no physical wafer expansion. When there is actual wafer expansion induced by large internal stress, both the IBO and the DBO measurements indicate similar expansion results. The scanning white-light interference microscope was used to check the variation of wafer warpage during the ADI and AEI stages. It predicts a similar trend with the overlay difference map, confirming the internal stress.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Through-wafer optical probe characterization for microelectromechanical systems positional state monitoring and feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

2000-12-01

Implementation of closed-loop microelectromechanical system (MEMS) control enables mechanical microsystems to adapt to the demands of the environment that they are actuating, opening a broad range of new opportunities for future MEMS applications. Integrated optical microsystems have the potential to enable continuous in situ optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation that is necessary for realization of feedback control. We present the results of initial research evaluating through-wafer optical microprobes for surface micromachined MEMS integrated optical position monitoring. Results from the through-wafer free-space optical probe of a lateral comb resonator fabricated using the multiuser MEMS process service (MUMPS) indicate significant positional information content with an achievable return probe signal dynamic range of up to 80% arising from film transmission contrast. Static and dynamic deflection analysis and experimental results indicate a through-wafer probe positional signal sensitivity of 40 mV/micrometers for the present setup or 10% signal change per micrometer. A simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure given the availability of positional state information.

Silicon surface passivation by polystyrenesulfonate thin films

NASA Astrophysics Data System (ADS)

Chen, Jianhui; Shen, Yanjiao; Guo, Jianxin; Chen, Bingbing; Fan, Jiandong; Li, Feng; Liu, Haixu; Xu, Ying; Mai, Yaohua

2017-02-01

The use of polystyrenesulfonate (PSS) thin films in a high-quality passivation scheme involving the suppression of minority carrier recombination at the silicon surface is presented. PSS has been used as a dispersant for aqueous poly-3,4-ethylenedioxythiophene. In this work, PSS is coated as a form of thin film on a Si surface. A millisecond level minority carrier lifetime on a high resistivity Si wafer is obtained. The film thickness, oxygen content, and relative humidity are found to be important factors affecting the passivation quality. While applied to low resistivity silicon wafers, which are widely used for photovoltaic cell fabrication, this scheme yields relatively shorter lifetime, for example, 2.40 ms on n-type and 2.05 ms on p-type wafers with a resistivity of 1-5 Ω.cm. However, these lifetimes are still high enough to obtain high implied open circuit voltages (Voc) of 708 mV and 697 mV for n-type and p-type wafers, respectively. The formation of oxides at the PSS/Si interface is suggested to be responsible for the passivation mechanism.

Wafer-scale synthesis of monolayer and few-layer MoS2 via thermal vapor sulfurization

NASA Astrophysics Data System (ADS)

Robertson, John; Liu, Xue; Yue, Chunlei; Escarra, Matthew; Wei, Jiang

2017-12-01

Monolayer molybdenum disulfide (MoS2) is an atomically thin, direct bandgap semiconductor crystal potentially capable of miniaturizing optoelectronic devices to an atomic scale. However, the development of 2D MoS2-based optoelectronic devices depends upon the existence of a high optical quality and large-area monolayer MoS2 synthesis technique. To address this need, we present a thermal vapor sulfurization (TVS) technique that uses powder MoS2 as a sulfur vapor source. The technique reduces and stabilizes the flow of sulfur vapor, enabling monolayer wafer-scale MoS2 growth. MoS2 thickness is also controlled with great precision; we demonstrate the ability to synthesize MoS2 sheets between 1 and 4 layers thick, while also showing the ability to create films with average thickness intermediate between integer layer numbers. The films exhibit wafer-scale coverage and uniformity, with electrical quality varying depending on the final thickness of the grown MoS2. The direct bandgap of grown monolayer MoS2 is analyzed using internal and external photoluminescence quantum efficiency. The photoluminescence quantum efficiency is shown to be competitive with untreated exfoliated MoS2 monolayer crystals. The ability to consistently grow wafer-scale monolayer MoS2 with high optical quality makes this technique a valuable tool for the development of 2D optoelectronic devices such as photovoltaics, detectors, and light emitters.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Control over dark current densities and cutoff wavelengths of GaAs/AlGaAs QWIP grown by multi-wafer MBE reactor

NASA Astrophysics Data System (ADS)

Roodenko, K.; Choi, K. K.; Clark, K. P.; Fraser, E. D.; Vargason, K. W.; Kuo, J.-M.; Kao, Y.-C.; Pinsukanjana, P. R.

2016-09-01

Performance of quantum well infrared photodetector (QWIP) device parameters such as detector cutoff wavelength and the dark current density depend strongly on the quality and the control of the epitaxy material growth. In this work, we report on a methodology to precisely control these critical material parameters for long wavelength infrared (LWIR) GaAs/AlGaAs QWIP epi wafers grown by multi-wafer production Molecular beam epitaxy (MBE). Critical growth parameters such as quantum well (QW) thickness, AlGaAs composition and QW doping level are discussed.

Wafer-size free-standing single-crystalline graphene device arrays

NASA Astrophysics Data System (ADS)

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Throughput increase by adjustment of the BARC drying time with coat track process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Long, Ryan

2005-05-01

Throughput of a coater module within the coater track is related to the solvent evaporation rate from the material that is being coated. Evaporation rate is controlled by the spin dynamics of the wafer and airflow dynamics over the wafer. Balancing these effects is the key to achieving very uniform coatings across a flat unpatterned wafer. As today"s coat tracks are being pushed to higher throughputs to match the scanner, the coat module throughput must be increased as well. For chemical manufacturers the evaporation rate of the material depends on the solvent used. One measure of relative evaporation rates is to compare flash points of a solvent. The lower the flash point, the quicker the solvent will evaporate. It is possible to formulate products with these volatile solvents although at a price. Shipping and manufacturing a more flammable product increase chances of fire, thereby increasing insurance premiums. Also, the end user of these chemicals will have to take extra precautions in the fab and in storage of these more flammable chemicals. An alternative coat process is possible which would allow higher throughput in a distinct coat module without sacrificing safety. A tradeoff is required for this process, that being a more complicated coat process and a higher viscosity chemical. The coat process uses the fact that evaporation rate depends on the spin dynamics of the wafer by utilizing a series of spin speeds that first would set the thickness of the material followed by a high spin speed to remove the residual solvent. This new process can yield a throughput of over 150 wafers per hour (wph) given two coat modules. The thickness uniformity of less than 2 nm (3 sigma) is still excellent, while drying times are shorter than 10 seconds to achieve the 150 wph throughput targets.

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2005-01-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2004-12-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

SiC Seeded Crystal Growth

NASA Astrophysics Data System (ADS)

Glass, R. C.; Henshall, D.; Tsvetkov, V. F.; Carter, C. H., Jr.

1997-07-01

The availability of relatively large (30 mm) SiC wafers has been a primary reason for the renewed high level of interest in SiC semiconductor technology. Projections that 75 mm SiC wafers will be available in 2 to 3 years have further peaked this interest. Now both 4H and 6H polytypes are available, however, the micropipe defects that occur to a varying extent in all wafers produced to date are seen by many as preventing the commercialization of many types of SiC devices, especially high current power devices. Most views on micropipe formation are based around Frank's theory of a micropipe being the hollow core of a screw dislocation with a huge Burgers vector (several times the unit cell) and with the diameter of the core having a direct relationship with the magnitude of the Burgers vector. Our results show that there are several mechanisms or combinations of these mechanisms which cause micropipes in SiC boules grown by the seeded sublimation method. Additional considerations such as polytype variations, dislocations and both impurity and diameter control add to the complexity of producing high quality wafers. Recent results at Cree Research, Inc., including wafers with micropipe densities of less than 1 cm - 2 (with 1 cm2 areas void of micropipes), indicate that micropipes will be reduced to a level that makes high current devices viable and that they may be totally eliminated in the next few years. Additionally, efforts towards larger diameter high quality substrates have led to production of 50 mm diameter 4H and 6H wafers for fabrication of LEDs and the demonstration of 75 mm wafers. Low resistivity and semi-insulating electrical properties have also been attained through improved process and impurity control. Although challenges remain, the industry continues to make significant progress towards large volume SiC-based semiconductor fabrication.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Simplified nonplanar wafer bonding for heterogeneous device integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Bowers, John E.; Riley, Anton

2004-07-01

We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by employing broadband quartz rod-transducer assembles). Experimental results, as predicted by prior rigorous simulations, prove that the temperature measurement accuracy obtained through several dynamic runs using the above specified approach, is better than +/-2°C. Furthermore, these results are highly repeatable and independent of wafer treatment conditions, thereby extolling the versatility and immunity of the new method from environmental conditions.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

High dynamic range CMOS-based mammography detector for FFDM and DBT

NASA Astrophysics Data System (ADS)

Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

2016-03-01

Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

Design and use of multiple blade slurry sawing in a production atmosphere

NASA Technical Reports Server (NTRS)

Lynah, F. P., Jr.; Ross, J. B.

1982-01-01

The technique and uses of the multiple blade slurry (MBS) saw are considered. Multiple bands of steel are arranged in a frame and the frame is reciprocated with the steel bands to a workpiece, while simultaneously applying abrasive at the point of contact. The blades wear slots in the workpiece and progress through the piece resulting in several parts of wafers. The transition to MBA from diamond slicing is justified by savings resulting from minimized kerf losses, minimized subsurface damage, and improved surface quality off the saw. This allows wafering much closer to finished thickness specifications. The current state of the art MBS technology must be significantly improved if the low cost solar array (LSA) goals are to be attained. It is concluded that although MBS will never be the answer to every wafering requirement, the economical production of wafers to LSA project specifications will be achieved.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Evaluating diffraction-based overlay

NASA Astrophysics Data System (ADS)

Li, Jie; Tan, Asher; Jung, JinWoo; Goelzer, Gary; Smith, Nigel; Hu, Jiangtao; Ham, Boo-Hyun; Kwak, Min-Cheol; Kim, Cheol-Hong; Nam, Suk-Woo

2012-03-01

We evaluate diffraction-based overlay (DBO) metrology using two test wafers. The test wafers have different film stacks designed to test the quality of DBO data under a range of film conditions. We present DBO results using traditional empirical approach (eDBO). eDBO relies on linear response of the reflectance with respect to the overlay displacement within a small range. It requires specially designed targets that consist of multiple pads with programmed shifts. It offers convenience of quick recipe setup since there is no need to establish a model. We measure five DBO targets designed with different pitches and programmed shifts. The correlations of five eDBO targets and the correlation of eDBO to image-based overlay are excellent. The targets of 800nm and 600nm pitches have better dynamic precision than targets of 400nm pitch, which agrees with simulated results on signal/noise ratio. 3σ of less than 0.1nm is achieved for both wafers using the best configured targets. We further investigate the linearity assumption of eDBO algorithm. Simulation results indicate that as the pitch of DBO targets gets smaller, the nonlinearity error, i.e., the error in the overlay measurement results caused by deviation from ideal linear response, becomes bigger. We propose a nonlinearity correction (NLC) by including higher order terms in the optical response. The new algorithm with NLC improves measurement consistency for DBO targets of same pitch but different programmed shift, due to improved accuracy. The results from targets with different pitches, however, are improved marginally, indicating the presence of other error sources.

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

NASA Astrophysics Data System (ADS)

Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

2015-03-01

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

1.3 μm wavelength vertical cavity surface emitting laser fabricated by orientation-mismatched wafer bonding: A prospect for polarization control

NASA Astrophysics Data System (ADS)

Okuno, Yae L.; Geske, Jon; Gan, Kian-Giap; Chiu, Yi-Jen; DenBaars, Steven P.; Bowers, John E.

2003-04-01

We propose and demonstrate a long-wavelength vertical cavity surface emitting laser (VCSEL) which consists of a (311)B InP-based active region and (100) GaAs-based distributed Bragg reflectors (DBRs), with an aim to control the in-plane polarization of output power. Crystal growth on (311)B InP substrates was performed under low-migration conditions to achieve good crystalline quality. The VCSEL was fabricated by wafer bonding, which enables us to combine different materials regardless of their lattice and orientation mismatch without degrading their quality. The VCSEL was polarized with a power extinction ratio of 31 dB.

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

NASA Technical Reports Server (NTRS)

Routh, D. E.; Sharma, G. C. (Inventor)

1984-01-01

An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

ArF scanner performance improvement by using track integrated CD optimization

NASA Astrophysics Data System (ADS)

Huang, Jacky; Yu, Shinn-Sheng; Ke, Chih-Ming; Wu, Timothy; Wang, Yu-Hsi; Gau, Tsai-Sheng; Wang, Dennis; Li, Allen; Yang, Wenge; Kaoru, Araki

2006-03-01

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

NASA Astrophysics Data System (ADS)

Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

2018-04-01

A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

Wafer-scale growth of VO2 thin films using a combinatorial approach

PubMed Central

Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

2015-01-01

Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

Advanced overlay: sampling and modeling for optimized run-to-run control

NASA Astrophysics Data System (ADS)

Subramany, Lokesh; Chung, WoongJae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Gutjahr, Karsten; Park, DongSuk; Snow, Patrick; Garcia-Medina, Miguel; Yap, Lipkong; Demirer, Onur Nihat; Pierson, Bill; Robinson, John C.

2016-03-01

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the "sample plan" of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor.

PubMed

Wang, Liying; Du, Xiaohui; Wang, Lingyun; Xu, Zhanhao; Zhang, Chenying; Gu, Dandan

2017-03-16

In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS) stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI) wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB). In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al) on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti) getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm) is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q). The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation.

Si/Ge Junctions Formed by Nanomembrane Bonding

DTIC Science & Technology

2011-01-01

hydrophobic bonding of a 200 nm thick 14. ABSTRACT monocrystalline Si(001) membrane to a bulk Ge(001) wafer. The membrane bond has an extremely high...temperature hydrophobic bonding of a 200 nm thick monocrystalline Si(001) membrane to a bulk Ge(001) wafer. The membrane bond has an extremely high quality...them. A RTIC LE KIEFER ET AL. VOL. 5 ’ NO. 2 ’ 1179–1189 ’ 2011 1182 www.acsnano.org monocrystalline . The interfacial region appears to be amorphous

High fill-factor micromirror array using a self-aligned vertical comb drive actuator with two rotational axes

NASA Astrophysics Data System (ADS)

Kim, Minsoo; Park, Jae-Hyoung; Jeon, Jin-A.; Yoo, Byung-Wook; Park, I. H.; Kim, Yong-Kweon

2009-03-01

We present a two-axis micromirror array with high fill-factor, using a new fabrication procedure on the full wafer scale. The micromirror comprises a self-aligned vertical comb drive actuator with a mirror plate mounted on it and electrical lines on a bottom substrate. A high-aspect-ratio vertical comb drive was built using a bulk micromachining technique on a silicon-on-insulator (SOI) wafer. The thickness of the torsion spring was adjusted using multiple silicon etching steps to enhance the static angular deflection of the mirrors. To address the array, electrical lines were fabricated on a glass substrate and combined with the comb actuators using an anodic bonding process. The silicon mirror plate was fabricated together with the actuator using a wafer bonding process and segmented at the final release step. The actuator and addressing lines were hidden behind the mirror plate, resulting in a high fill-factor of 84% in an 8 × 8 array of micromirrors, each 340 µm × 340 µm. The fabricated mirror plate has a high-quality optical surface with an average surface roughness (Ra) of 4 nm and a curvature radius of 0.9 m. The static and dynamic responses of the micromirror were characterized by comparing the measured results with the calculated values. The maximum static optical deflection for the outer axis is 4.32° at 60 V, and the maximum inner axis tilting angle is 2.82° at 96 V bias. The torsion resonance frequencies along the outer and inner axes were 1.94 kHz and 0.95 kHz, respectively.

Ion Dynamics in a Single and Dual Radio Frequency Sheath Measured by Laser-Induced Fluorescence

NASA Astrophysics Data System (ADS)

Moore, Nathaniel Breckenridge

Ion dynamics are investigated in a single and dual radio frequency sheath as a function of radius above a 30 cm diameter biased silicon wafer for the first time in an industrial inductively coupled (440 kHz, 500 W) plasma etch tool. Ion velocity distribution (IVD) function measurements in the argon plasma are taken using laser induced fluorescence (LIF). Planar sheets of laser light enter the chamber both parallel and perpendicular to the surface of the wafer in order to measure both parallel and perpendicular IVDs at thousands of spatial positions. A fast (30 ns exposure) CCD camera measures the resulting fluorescence with a spatial resolution of 0.4 mm. The dual-frequency bias on the wafer is comprised of a 2 MHz low frequency (LF) bias and a 19 MHz high frequency (HF) bias. The laser is phase locked to the LF bias and IVD measurements are taken at several different LF phases. Ion energy distribution (IED) function measurements and calculated moments are compared for several cases. For the LF case (no HF), the IEDs were found to be highly phase dependent and were varied radially up to 10%. Calculated mean velocity vectors showed large impact angles near the surface of the wafer with the largest angles observed near the wafer edge. The LF experimental results are compared with simulations designed specifically for this particular plasma tool and showed good qualitative agreement. For the dual frequency case, IEDs were measured at two disparate phases of the phase-locked LF bias. IEDs were found to be multi-peaked and were well-approximated by a sum of Maxwellian distributions. The calculated fluxes in the dual frequency case were found to be substantially more radially uniform than the single frequency bias case. For industrial applications, this radially uniform ion flux is evidently a trade off with the undesirable multi-peaked structure in the IEDs.

Carmustine wafer implantation for high-grade gliomas: Evidence-based safety efficacy and practical recommendations from the Neuro-oncology Club of the French Society of Neurosurgery.

PubMed

Roux, A; Caire, F; Guyotat, J; Menei, P; Metellus, P; Pallud, J

2017-12-01

There is a growing body of evidence that carmustine wafer implantation during surgery is an effective therapeutic adjunct to the standard combined radio-chemotherapy regimen using temozolomide in newly diagnosed and recurrent high-grade glioma patient management with a statistically significant survival benefit demonstrated across several randomized clinical trials, as well as prospective and retrospective studies (grade A recommendation). Compelling clinical data also support the safety of carmustine wafer implantation (grade A recommendation) in these patients and suggest that observed adverse events can be avoided in experienced neurosurgeon hands. Furthermore, carmustine wafer implantation does not seem to impact negatively on the quality of life and the completion of adjuvant oncological treatments (grade C recommendation). Moreover, emerging findings support the potential of high-grade gliomas molecular status, especially the O(6)-Methylguanine-DNA Methyltransferase promoter methylation status, in predicting the efficacy of such a surgical strategy, especially at recurrence (grade B recommendation). Finally, carmustine wafer implantation appears to be cost-effective in high-grade glioma patients when performed by an experienced team and when total or subtotal resection can be achieved. Altogether, these data underline the current need for a new randomized clinical trial to assess the impact of a maximal safe resection with carmustine wafer implantation followed by the standard combined chemoradiation protocol stratified by molecular status in high-grade glioma patients. Copyright © 2017 Elsevier Masson SAS. All rights reserved.

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

NASA Astrophysics Data System (ADS)

Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

2018-01-01

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

NASA Astrophysics Data System (ADS)

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

CZT sensors for Computed Tomography: from crystal growth to image quality

NASA Astrophysics Data System (ADS)

Iniewski, K.

2016-12-01

Recent advances in Traveling Heater Method (THM) growth and device fabrication that require additional processing steps have enabled to dramatically improve hole transport properties and reduce polarization effects in Cadmium Zinc Telluride (CZT) material. As a result high flux operation of CZT sensors at rates in excess of 200 Mcps/mm2 is now possible and has enabled multiple medical imaging companies to start building prototype Computed Tomography (CT) scanners. CZT sensors are also finding new commercial applications in non-destructive testing (NDT) and baggage scanning. In order to prepare for high volume commercial production we are moving from individual tile processing to whole wafer processing using silicon methodologies, such as waxless processing, cassette based/touchless wafer handling. We have been developing parametric level screening at the wafer stage to ensure high wafer quality before detector fabrication in order to maximize production yields. These process improvements enable us, and other CZT manufacturers who pursue similar developments, to provide high volume production for photon counting applications in an economically feasible manner. CZT sensors are capable of delivering both high count rates and high-resolution spectroscopic performance, although it is challenging to achieve both of these attributes simultaneously. The paper discusses material challenges, detector design trade-offs and ASIC architectures required to build cost-effective CZT based detection systems. Photon counting ASICs are essential part of the integrated module platforms as charge-sensitive electronics needs to deal with charge-sharing and pile-up effects.

Advances in photonic MOEMS-MEMS device thinning and polishing

NASA Astrophysics Data System (ADS)

McAneny, James J.; Kennedy, Mark; McGroggan, Tom

2010-02-01

As devices continue to increase in density and complexity, ever more stringent specifications are placed on the wafer scale equipment manufacturers to produce higher quality and higher output. This results in greater investment and more resource being diverted into producing tools and processes which can meet the latest demanding criteria. Substrate materials employed in the fabrication process range from Silicon through InP and include GaAs, InSb and other optical networking or waveguide materials. With this diversity of substrate materials presented, controlling the geometries and surfaces grows progressively more challenging. This article highlights the key parameters which require close monitoring and control in order to produce highly precise wafers as part of the fabrication process. Several as cut and commercially available standard polished wafer materials were used in empirical trials to test tooling options in generating high levels of geometric control over the dimensions while producing high quality surface finishes. Specific attention was given to the measurement and control of: flatness; parallelism/TTV; surface roughness and final target thickness as common specifications required by the industry. By combining the process variables of: plate speed, download pressure, slurry flow rate and concentration, pad type and wafer travel path across the polish pad, the effect of altering these variables was recorded and analysed to realize the optimum process conditions for the materials under test. The results being then used to design improved methods and tooling for the thinning and polishing of photonic materials applied to MOEMS-MEMS device fabrication.

Debris-free rear-side picosecond laser ablation of thin germanium wafers in water with ethanol

NASA Astrophysics Data System (ADS)

Zhang, Dongshi; Gökce, Bilal; Sommer, Steffen; Streubel, René; Barcikowski, Stephan

2016-03-01

In this paper, we perform liquid-assisted picosecond laser cutting of 150 μm thin germanium wafers from the rear side. By investigating the cutting efficiency (the ability to allow an one-line cut-through) and quality (characterized by groove morphologies on both sides), the pros and cons of this technique under different conditions are clarified. Specifically, with laser fluence fixed, repetition rate and scanning speed are varied to show quality and efficiency control by means of laser parameter modulation. It is found that low repetition rate ablation in liquid gives rise to a better cut quality on the front side than high repetition rate ablation since it avoids dispersed nanoparticles redeposition resulting from a bubble collapse, unlike the case of 100 kHz which leads to large nanorings near the grooves resulting from a strong interaction of bubbles and the case of 50 kHz which leads to random cutting due to the interaction of the former pulse induced cavitation bubble and the subsequent laser pulse. Furthermore, ethanol is mixed with pure distilled water to assess the liquid's impact on the cutting efficiency and cutting quality. The results show that increasing the ethanol fraction decreases the ablation efficiency but simultaneously, greatly improves the cutting quality. The improvement of cut quality as ethanol ratio increases may be attributed to less laser beam interference by a lower density of bubbles which adhere near the cut kerf during ablation. A higher density of bubbles generated from ethanol vaporization during laser ablation in liquid will cause stronger bubble shielding effect toward the laser beam propagation and therefore result in less laser energy available for the cut, which is the main reason for the decrease of cut efficiency in water-ethanol mixtures. Our findings give an insight into under which condition the rear-side laser cutting of thin solar cells should be performed: high repetition, pure distilled water and high laser power are favorable for high-speed rough cutting but the cut kerf suffers from strong side effects of ripples, nanoredeposition occurrence, while low laser power at low repetition rate (10 kHz), mixed solution (1 wt% ethanol in water) and moderate scanning speed (100 μm/s) are preferable for ultrafine high-quality debris-free cutting. The feasibility of high-quality cut is a good indication of using rear laser ablation in liquid to cut thinner wafers. More importantly, this technique spares any post cleaning steps to reduce the risk to the contamination or crack of the thin wafers.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Method for formation of high quality back contact with screen-printed local back surface field

DOEpatents

Rohatgi, Ajeet; Meemongkolkiat, Vichai

2010-11-30

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Optical processing furnace with quartz muffle and diffuser plate

DOEpatents

Sopori, Bhushan L.

1995-01-01

An optical furnace for annealing a process wafer comprising a source of optical energy, a quartz muffle having a door to hold the wafer for processing, and a quartz diffuser plate to diffuse the light impinging on the quartz muffle; a feedback system with a light sensor located in the door or wall of the muffle is also provided for controlling the source of optical energy. The quartz for the diffuser plate is surface etched (to give the quartz diffusive qualities) in the furnace during a high intensity burn-in process.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Modeling physical vapor deposition of energetic materials

DOE PAGES

Shirvan, Koroush; Forrest, Eric C.

2018-03-28

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Modeling physical vapor deposition of energetic materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shirvan, Koroush; Forrest, Eric C.

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Ultrafast carrier dynamics in a p-type GaN wafer under different carrier distributions

NASA Astrophysics Data System (ADS)

Fang, Yu; Yang, Junyi; Yang, Yong; Wu, Xingzhi; Xiao, Zhengguo; Zhou, Feng; Song, Yinglin

2016-02-01

The dependence of the carrier distribution on photoexcited carrier dynamics in a p-type Mg-doped GaN (GaN:Mg) wafer were systematically measured by femtosecond transient absorption (TA) spectroscopy. The homogeneity of the carrier distribution was modified by tuning the wavelength of the UV pulse excitation around the band gap of GaN:Mg. The TA kinetics appeared to be biexponential for all carrier distributions, and only the slower component decayed faster as the inhomogeneity of the carrier distribution increased. It was concluded that the faster component (50-70 ps) corresponded to the trap process of holes by the Mg acceptors, and the slower component (150-600 ps) corresponded to the combination of non-radiative surface recombination and intrinsic carrier recombination via dislocations. Moreover, the slower component increased gradually with the incident fluence due to the saturation of surface states.

Wafer-level manufacturing technology of glass microlenses

NASA Astrophysics Data System (ADS)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

NASA Astrophysics Data System (ADS)

Bakhshizadeh, N.; Sivoththaman, S.

2017-12-01

Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Shallow Heavily Doped n++ Germanium by Organo-Antimony Monolayer Doping.

PubMed

Alphazan, Thibault; Díaz Álvarez, Adrian; Martin, François; Grampeix, Helen; Enyedi, Virginie; Martinez, Eugénie; Rochat, Névine; Veillerot, Marc; Dewitte, Marc; Nys, Jean-Philippe; Berthe, Maxime; Stiévenard, Didier; Thieuleux, Chloé; Grandidier, Bruno

2017-06-14

Functionalization of Ge surfaces with the aim of incorporating specific dopant atoms to form high-quality junctions is of particular importance for the development of solid-state devices. In this study, we report the shallow doping of Ge wafers with a monolayer doping strategy that is based on the controlled grafting of Sb precursors and the subsequent diffusion of Sb into the wafer upon annealing. We also highlight the key role of citric acid in passivating the surface before its reaction with the Sb precursors and the benefit of a protective SiO 2 overlayer that enables an efficient incorporation of Sb dopants with a concentration higher than 10 20 cm -3 . Microscopic four-point probe measurements and photoconductivity experiments show the full electrical activation of the Sb dopants, giving rise to the formation of an n++ Sb-doped layer and an enhanced local field-effect passivation at the surface of the Ge wafer.

Composite germanium monochromators - Results for the TriCS single-crystal diffractometer at SINQ

NASA Astrophysics Data System (ADS)

Schefer, J.; Fischer, S.; Böhm, M.; Keller, L.; Horisberger, M.; Medarde, M.; Fischer, P.

Composite germanium monochromators are foremost in application in neutron diffraction due to their good scattering properties, low absorption values and the diamond structure which avoids second-order contamination when using hhk reflections (all odd). Our slices for the monochromator are built from 24 wafers, each 0.4 mm thick. The alignment of the wafers within the final composite wafer package has been improved by adding tin for the soldering process with a sputtering method instead of foils. Nine slices, each 12.5 mm high, are mounted on separate miniature goniometer heads to the focusing monochromator. The focusing angle is controlled by only one motor/digitizer by using a sophisticated mechanism. Turning the monochromator by 9° around overlineω allow access of the 311 (primary) and 511 (secondary) reflection. We also show the importance of permanent quality control with neutrons. The monochromator will be used on the single-crystal diffractometer TriCS at SINQ.

Enhancing Scheduling Performance for a Wafer Fabrication Factory: The Biobjective Slack-Diversifying Nonlinear Fluctuation-Smoothing Rule

PubMed Central

Chen, Toly; Wang, Yu Cheng

2012-01-01

A biobjective slack-diversifying nonlinear fluctuation-smoothing rule (biSDNFS) is proposed in the present work to improve the scheduling performance of a wafer fabrication factory. This rule was derived from a one-factor bi-objective nonlinear fluctuation-smoothing rule (1f-biNFS) by dynamically maximizing the standard deviation of the slack, which has been shown to benefit scheduling performance by several previous studies. The efficacy of the biSDNFS was validated with a simulated case; evidence was found to support its effectiveness. We also suggested several directions in which it can be exploited in the future. PMID:23509446

Graphene growth on Ge(100)/Si(100) substrates by CVD method.

PubMed

Pasternak, Iwona; Wesolowski, Marek; Jozwik, Iwona; Lukosius, Mindaugas; Lupina, Grzegorz; Dabrowski, Pawel; Baranowski, Jacek M; Strupinski, Wlodek

2016-02-22

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm(-1).

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

PubMed

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Design of Tactile Sensor Using Dynamic Wafer Technology Based on VLSI Technique

DTIC Science & Technology

2001-10-25

Charles Noback, Rober Carola," Human Anatomy and Physiology" third edition, 1995. [5] M.H. Raibert and John E. Tanner, "Design and Implementation of VLSI Tactile Sensing Computer" Robotics Research vol 1, 1983.

Extending i-line capabilities through variance characterization and tool enhancement

NASA Astrophysics Data System (ADS)

Miller, Dan; Salinas, Adrian; Peterson, Joel; Vickers, David; Williams, Dan

2006-03-01

Continuous economic pressures have moved a large percent of integrated device manufacturing (IDM) operations either overseas or to foundry operations over the last 10 years. These pressures have left the IDM fabs in the U.S. with required COO improvements in order to maintain operations domestically. While the assets of many of these factories are at a very favorable point in the depreciation life cycle, the equipment and processes are constrained to the quality of the equipment in its original state and the degradation over its installed life. With the objective to enhance output and improve process performance, this factory and their primary lithography process tool supplier have been able to extend the usable life of the existing process tools, increase the output of the tool base, and improve the distribution of the CDs on the product produced. Texas Instruments Incorporated lead an investigation with the POLARIS ® Systems & Services business of FSI International to determine the sources of variance in the i-line processing of a wide array of IC device types. Data from the sources of variance were investigated such as PEB temp, PEB delay time, develop recipe, develop time, and develop programming. While PEB processes are a primary driver of acid catalyzed resists, the develop mode is shown in this work to have an overwhelming impact on the wafer to wafer and across wafer CD performance of these i-line processes. These changes have been able to improve the wafer to wafer CD distribution by more than 80 %, and the within wafer CD distribution by more than 50 % while enabling a greater than 50 % increase in lithography cluster throughput. The paper will discuss the contribution from each of the sources of variance and their importance in overall system performance.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies.

PubMed

Yoon, Jongseung; Jo, Sungjin; Chun, Ik Su; Jung, Inhwa; Kim, Hoon-Sik; Meitl, Matthew; Menard, Etienne; Li, Xiuling; Coleman, James J; Paik, Ungyu; Rogers, John A

2010-05-20

Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices to radio-frequency electronics and most forms of optoelectronics. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.

Growth and Implementation of Carbon-Doped AlGaN Layers for Enhancement-Mode HEMTs on 200 mm Si Substrates

NASA Astrophysics Data System (ADS)

Su, Jie; Posthuma, Niels; Wellekens, Dirk; Saripalli, Yoga N.; Decoutere, Stefaan; Arif, Ronald; Papasouliotis, George D.

2016-12-01

We are reporting the growth of AlGaN based enhancement-mode high electron mobility transistors (HEMTs) on 200 mm silicon (111) substrates using a single wafer metalorganic chemical vapor deposition reactor. It is found that TMAl pre-dosing conditions are critical in controlling the structural quality, surface morphology, and wafer bow of the HEMT stack. Optimal structural quality and pit-free surface are demonstrated for AlGaN HEMTs with pre-dosing temperature at 750°C. Intrinsically, carbon-doped AlGaN, is used as the current blocking layer in the HEMT structures. The lateral buffer breakdown and device breakdown characteristics, reach 400 V at a leakage current of 1 μA/mm measured at 150°C. The fabricated HEMT devices, with a Mg doped p-GaN gate layer, are operating in enhancement mode reaching a positive threshold voltage of 2-2.5 V, a low on-resistance of 10.5 Ω mm with a high drain saturation current of 0.35 A/mm, and a low forward bias gate leakage current of 0.5 × 10-6 A/mm ( V gs = 7 V). Tight distribution of device parameters across the 200 mm wafers and over repeat process runs is observed.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

PubMed

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-03-04

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

PubMed Central

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-01-01

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

Graphene-Si heterogeneous nanotechnology

NASA Astrophysics Data System (ADS)

Akinwande, Deji; Tao, Li

2013-05-01

It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

Scatterometry on pelliclized masks: an option for wafer fabs

NASA Astrophysics Data System (ADS)

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Diffusion of oxygen in cork.

PubMed

Lequin, Sonia; Chassagne, David; Karbowiak, Thomas; Simon, Jean-Marc; Paulin, Christian; Bellat, Jean-Pierre

2012-04-04

This work reports measurements of effective oxygen diffusion coefficient in raw cork. Kinetics of oxygen transfer through cork is studied at 298 K thanks to a homemade manometric device composed of two gas compartments separated by a cork wafer sample. The first compartment contains oxygen, whereas the second one is kept under dynamic vacuum. The pressure decrease in the first compartment is recorded as a function of time. The effective diffusion coefficient D(eff) is obtained by applying Fick's law to transient state using a numerical method based on finite differences. An analytical model derived from Fick's law applied to steady state is also proposed. Results given by these two methods are in close agreement with each other. The harmonic average of the effective diffusion coefficients obtained from the distribution of 15 cork wafers of 3 mm thickness is 1.1 × 10(-9) m(2) s(-1) with a large distribution over four decades. The statistical analysis of the Gaussian distribution obtained on a 3 mm cork wafer is extrapolated to a 48 mm cork wafer, which length corresponds to a full cork stopper. In this case, the probability density distribution gives a mean value of D(eff) equal to 1.6 × 10(-9) m(2) s(-1). This result shows that it is possible to obtain the effective diffusion coefficient of oxygen through cork from short time (few days) measurements performed on a thin cork wafer, whereas months are required to obtain the diffusion coefficient for a full cork stopper. Permeability and oxygen transfer rate are also calculated for comparison with data from other studies.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

PubMed Central

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-01-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Less strained and more efficient GaN light-emitting diodes with embedded silica hollow nanospheres

PubMed Central

Kim, Jonghak; Woo, Heeje; Joo, Kisu; Tae, Sungwon; Park, Jinsub; Moon, Daeyoung; Park, Sung Hyun; Jang, Junghwan; Cho, Yigil; Park, Jucheol; Yuh, Hwankuk; Lee, Gun-Do; Choi, In-Suk; Nanishi, Yasushi; Han, Heung Nam; Char, Kookheon; Yoon, Euijoon

2013-01-01

Light-emitting diodes (LEDs) become an attractive alternative to conventional light sources due to high efficiency and long lifetime. However, different material properties between GaN and sapphire cause several problems such as high defect density in GaN, serious wafer bowing, particularly in large-area wafers, and poor light extraction of GaN-based LEDs. Here, we suggest a new growth strategy for high efficiency LEDs by incorporating silica hollow nanospheres (S-HNS). In this strategy, S-HNSs were introduced as a monolayer on a sapphire substrate and the subsequent growth of GaN by metalorganic chemical vapor deposition results in improved crystal quality due to nano-scale lateral epitaxial overgrowth. Moreover, well-defined voids embedded at the GaN/sapphire interface help scatter lights effectively for improved light extraction, and reduce wafer bowing due to partial alleviation of compressive stress in GaN. The incorporation of S-HNS into LEDs is thus quite advantageous in achieving high efficiency LEDs for solid-state lighting. PMID:24220259

Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

NASA Astrophysics Data System (ADS)

Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

2003-09-01

As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

PubMed

Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

2017-07-25

It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

NASA Astrophysics Data System (ADS)

Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

2016-08-01

This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

Investigation of Defects Origin in p-Type Si for Solar Applications

NASA Astrophysics Data System (ADS)

Gwóźdź, Katarzyna; Placzek-Popko, Ewa; Mikosza, Maciej; Zielony, Eunika; Pietruszka, Rafal; Kopalko, Krzysztof; Godlewski, Marek

2017-07-01

In order to improve the efficiency of a solar cell based on silicon, one must find a compromise between its price and crystalline quality. That is precisely why the knowledge of defects present in the material is of primary importance. This paper studies the defects in commercially available cheap Schottky titanium/gold silicon wafers. The electrical properties of the diodes were defined by using current-voltage and capacitance-voltage measurements. Low series resistance and ideality factor are proofs of the good quality of the sample. The concentration of the acceptors is in accordance with the manufacturer's specifications. Deep level transient spectroscopy measurements were used to identify the defects. Three hole traps were found with activation energies equal to 0.093 eV, 0.379 eV, and 0.535 eV. Comparing the values with the available literature, the defects were determined as connected to the presence of iron interstitials in the silicon. The quality of the silicon wafer seems good enough to use it as a substrate for the solar cell heterojunctions.

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Wafer-scale plasmonic and photonic crystal sensors

NASA Astrophysics Data System (ADS)

George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

2015-08-01

200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

Ultrashort pulse laser dicing of thin Si wafers: the influence of laser-induced periodic surface structures on the backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Piredda, Giovanni; Stroj, Sandra; Fasching, Gernot; Bodea, Marius; Schwarz, Elisabeth

2016-11-01

High power electronic chips are usually fabricated on about 50 µm thin Si wafers to improve heat dissipation. At these chip thicknesses mechanical dicing becomes challenging. Chippings may occur at the cutting edges, which reduce the mechanical stability of the die. Thermal load changes could then lead to sudden chip failure. Ultrashort pulsed lasers are a promising tool to improve the cutting quality, because thermal side effects can be reduced to a minimum. However, laser-induced periodic surface structures occur at the sidewalls and at the trench bottom during scribing. The goal of this study was to investigate the influence of these periodic structures on the backside breaking strength of the die. An ultrafast laser with a pulse duration of 380 fs and a wavelength of 1040 nm was used to cut a wafer into single chips. The pulse energy and the number of scans was varied. The cuts in the wafer were investigated using transmitted light microscopy, the sidewalls of the cut chips were investigated using scanning electron and confocal microscopy, and the breaking strength was evaluated using the 3-point bending test. The results indicated that periodic holes with a distance of about 20-30 µm were formed at the bottom of the trench, if the number of scans was set too low to completely cut the wafer; the wafer was only perforated. Mechanical breaking of the bridges caused 5 µm deep kerfs in the sidewall. These kerfs reduced the breaking strength at the backside of the chip to about 300 MPa. As the number of scans was increased, the bridges were ablated and the wafer was cut completely. Periodic structures were observed on the sidewall; the roughness was below 1 µm. The surface roughness remained on a constant level even when the number of scans was doubled. However, the periodic structures on the sidewall seemed to vanish and the probability to remove local flaws increases with the number of scans. As a consequence, the breaking strength was increased to about 700 MPa.

Modifications of Fabrication of Vibratory Microgyroscopes

NASA Technical Reports Server (NTRS)

Bae, Sam Y.; Yee, Karl Y.; Wiberg, Dean

2005-01-01

A micromachining process for the fabrication of vibratory microgyroscopes from silicon wafers, and aspects of the microgyroscope design that are inextricably linked with the fabrication process, have been modified in an effort to increase production yields from perspectives of both quantity and quality. Prior to the modifications, the effective production yield of working microgyroscopes was limited to one or less per wafer. The modifications are part of a continuing effort to improve the design and increase production yields to more than 30 working microgyroscopes per wafer. A discussion of pertinent aspects of the unmodified design and the unmodified fabrication process is prerequisite to a meaningful description of the modifications. The design of the microgyroscope package was not conducive to high yield and rapid testing of many microgyroscopes. One of the major impediments to high yield and testing was found to lie in vibration- isolation beams around the four edges of each microgyroscope, which beams were found to be unnecessary for achieving high resonance quality factors (Q values) characterizing the vibrations of petallike cantilevers. The fabrication process included an 8- m-deep plasma etch. The purpose of the etch was to create 8- m vertical gaps, below which were to be placed large gold evaporated electrodes and sensing pads to drive and sense resonant vibrations of the "petals." The process also included a step in which bridges between dies were cut to separate the dies. The etched areas must be kept clean and smooth (free of debris and spikes), because any object close to 8 m high in those areas would stop the vibrations. However, it was found that after the etch, there remained some spikes with heights that were, variously, almost as high or as high as the etch depth. It also was found that the cutting of bridges created silicon debris, some of which lodged in the 8- m gaps and some of which landed on top of the petals. The masses added to the petals by the debris altered resonance frequencies and/or Q values to unacceptable degrees. Hence, the spikes and the debris have been conjectured to cause most of the observed malfunctions of newly fabricated microgyroscopes. Another pertinent aspect of the unmodified design and process was the fabrication of electrodes and the 8- m capacitance gap on a 500- m-thick wafer, and the fabrication of a 3-mm-thick baseplate from another wafer. It was necessary to bond these wafers to each other in an assembly step that was later found to be superfluous in that it could be eliminated by a suitable modification of the design.

Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

PubMed

Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

2016-03-01

Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

Economics of ingot slicing with an internal diameter saw for low-cost solar cells

NASA Technical Reports Server (NTRS)

Daud, T.; Liu, J. K.; Fiegl, G.

1981-01-01

Slicing of silicon ingots using diamond impregnated internal diameter blade saws has been a standard technology of the semiconductor industry. This paper describes work on improvements to this technology for 10 cm diameter ingot slicing. Ingot rotation, dynamic blade edge control with feedback, mechanized blade dressing and development of thinner blades are the approaches tried. A comparison of the results for wafering with and without ingot rotation is also made. A sensitivity analysis of the major cost elements in wafering is performed for 10 cm diameter ingot and extended to the 15 cm diameter ingot case. Various parameter values such as machine cost, feed rate and consumable materials cost are identified both for single and multiple ingot slicing.

Investigation of the Static and Dynamic Characteristics for a Wafer-Fused C-band VCSEL in the Mode of the Optical-Electric Converter

NASA Astrophysics Data System (ADS)

Belkin, M. E.

2018-01-01

The results of an experimental study for a long wavelength vertical cavity surface-emitting laser of a wafer-fused construction as an effective resonant cavity enhanced photodetector of analog optical signals are described. The device is of interest for a number of promising microwave photonics applications and for creation of a low-cost photoreceiver in a high-speed fiber optics telecommunication system with dense wavelength division multiplexing. The schematic of the testbed, the original technique allowing to calculate the passband of the built-in optical cavity, and the results of measuring dark current, current responsivity, amplitude- and phase-frequency characteristics during the process of photo-detection are demonstrated.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Growth and characterization of high quality ZnS thin films by RF sputtering

NASA Astrophysics Data System (ADS)

Mukherjee, C.; Rajiv, K.; Gupta, P.; Sinha, A. K.; Abhinandan, L.

2012-06-01

High optical quality ZnS films are deposited on glass and Si wafer by RF sputtering from pure ZnS target. Optical transmittance, reflectance, ellipsometry, FTIR and AFM measurements are carried out. Effect of substrate temperature and chamber baking for long duration on film properties have been studied. Roughness of the films as measured by AFM are low (1-2Å).

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Overlay degradation induced by film stress

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Luo, Shing-Ann; Yang, Mars; Yang, Elvis; Hung, Yung-Tai; Luoh, Tuung; Yang, T. H.; Chen, K. C.

2017-03-01

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn't directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

Control of ingot quality and solar cell appearance of cast mono-like silicon by using seed partitions

NASA Astrophysics Data System (ADS)

Lan, C. Y.; Wu, Y. C.; Lan, A.; Yang, C. F.; Hsu, C.; Lu, C. M.; Yang, A.; Lan, C. W.

2017-10-01

The growth of mono-like ingot by directional solidification has suffered serious problems in defect control. We proposed a simple approach by using seed partitions, and the grown crystal had much lower defects and better orientation uniformity. Furthermore, the partitions allowed the much easier seed preparation, which had a significant advantage in production. The concept was demonstrated by a G1 experiment, and the detailed defect analyses were carried out. The wafers after gettering had the best lifetime of more than 1 ms after surface passivation. The color mismatch in the appearance of the solar cells made from the wafer was also significantly mitigated.

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Metal-Free CVD Graphene Synthesis on 200 mm Ge/Si(001) Substrates.

PubMed

Lukosius, M; Dabrowski, J; Kitzmann, J; Fursenko, O; Akhtar, F; Lisker, M; Lippert, G; Schulze, S; Yamamoto, Y; Schubert, M A; Krause, H M; Wolff, A; Mai, A; Schroeder, T; Lupina, G

2016-12-14

Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH 4 as carbon source on epitaxial Ge(100) layers, which were grown on Si(100), prior to the graphene synthesis. Graphene layer with the 2D/G ratio ∼3 and low D mode (i.e., low concentration of defects) was measured over the entire 200 mm wafer by Raman spectroscopy. A typical full-width-at-half-maximum value of 39 cm -1 was extracted for the 2D mode, further indicating that graphene of good structural quality was produced. The study also revealed that the lack of interfacial oxide correlates with superior properties of graphene. In order to evaluate electrical properties of graphene, its 2 × 2 cm 2 pieces were transferred onto SiO 2 /Si substrates from Ge/Si wafers. The extracted sheet resistance and mobility values of transferred graphene layers were ∼1500 ± 100 Ω/sq and μ ≈ 400 ± 20 cm 2 /V s, respectively. The transferred graphene was free of metallic contaminations or mechanical damage. On the basis of results of DFT calculations, we attribute the high structural quality of graphene grown by CVD on Ge to hydrogen-induced reduction of nucleation probability, explain the appearance of graphene-induced facets on Ge(001) as a kinetic effect caused by surface step pinning at linear graphene nuclei, and clarify the orientation of graphene domains on Ge(001) as resulting from good lattice matching between Ge(001) and graphene nucleated on such nuclei.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Integrated otpical monitoring of MEMS for closed-loop control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Wang, Limin; McCormick, W. B.; Rittenhouse, S. A.; Famouri, Parviz F.; Hornak, Lawrence A.

2003-01-01

Robust control and failure assessment of MEMS employed in physically demanding, mission critical applications will allow for higher degrees of quality assurance in MEMS operation. Device fault detection and closed-loop control require detailed knowledge of the operational states of MEMS over the lifetime of the device, obtained by a means decoupled from the system. Preliminary through-wafer optical monitoring research efforts have shown that through-wafer optical probing is suitable for characterizing and monitoring the behavior of MEMS, and can be implemented in an integrated optical monitoring package for continuous in-situ device monitoring. This presentation will discuss research undertaken to establish integrated optical device metrology for closed-loop control of a MUMPS fabricated lateral harmonic oscillator. Successful linear closed-loop control results using a through-wafer optical microprobe position feedback signal will be presented. A theoretical optical output field intensity study of grating structures, fabricated on the shuttle of the resonator, was performed to improve the position resolution of the optical microprobe position signal. Through-wafer microprobe signals providing a positional resolution of 2 μm using grating structures will be shown, along with initial binary Fresnel diffractive optical microelement design layout, process development, and testing results. Progress in the design, fabrication, and test of integrated optical elements for multiple microprobe signal delivery and recovery will be discussed, as well as simulation of device system model parameter changes for failure assessment.

High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.

PubMed

Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

2014-09-05

Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Novel metamaterials and their applications in subwavelength waveguides, imanging and modulation

NASA Astrophysics Data System (ADS)

Zhang, Chaomin

GaAs-based solar cells have attracted much interest because of their high conversion efficiencies of ~28% under one sun illumination. The main carrier recombination mechanisms in the GaAs-based solar cells are surface recombination, radiative recombination and non-radiative recombination. Photon recycling reduces the effect of radiative recombination and is an approach to obtain the device performance described by detailed balance theory. The photon recycling model has been developed and was applied to investigate the loss mechanisms in the state-of-the-art GaAs-based solar cell structures using PC1D software. A standard fabrication process of the GaAs-based solar cells is as follows: wafer preparation, individual cell isolation by mesa, n- and p-type metallization, rapid thermal annealing (RTA), cap layer etching, and anti-reflection coating (ARC). The growth rate for GaAs-based materials is one of critical factors to determine the cost for the growth of GaAs-based solar cells. The cost for fabricating GaAs-based solar cells can be reduced if the growth rate is increased without degrading the crystalline quality. The solar cell wafers grown at different growth rates of 14 mum/hour and 55 mum/hour were discussed in this work. The structural properties of the wafers were characterized by X-ray diffraction (XRD) to identify the crystalline quality, and then the as-grown wafers were fabricated into solar cell devices under the same process conditions. The optical and electrical properties such as surface reflection, external quantum efficiency (EQE), dark I-V, Suns-Voc, and illuminated I-V under one sun using a solar simulator were measured to compare the performances of the solar cells with different growth rates. Some simulations in PC1D have been demonstrated to investigate the reasons of the different device performances between fast growth and slow growth structures. A further analysis of the minority carrier lifetime is needed to investigate into the difference in device performances.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

Growth of blue GaN LED structures on 150-mm Si(1 1 1)

NASA Astrophysics Data System (ADS)

Dadgar, A.; Hums, C.; Diez, A.; Bläsing, J.; Krost, A.

2006-12-01

Up to 5.4-μm thick GaN on Si light emitting diode (LED) structures were grown by metalorganic chemical vapor phase epitaxy (MOVPE) on 150 mm Si(1 1 1) substrates. In-situ curvature measurements enable monitoring of stress development during growth and the influence of interlayers on strain balancing after cooling. In X-ray diffraction (XRD) ω-scans the GaN (0 0 0 2) reflection is about 380 arcsec and in θ-2 θ measurements the InGaN/GaN MQW interference peaks are well resolved indicating the high quality of the grown structure. In comparison to the growth on 2-in sapphire the wafer curvature after growth is low (>50 m) for the growth on Si and also during MQW growth at low temperatures a homogeneous wafer temperature can be achieved. The standard deviation of the wavelength over the whole 150-mm test wafer (5-mm edge exclusion) is <3.5 nm and reflects the three different heater zones of the MOVPE system used.

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

PubMed

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

AlGaAs/Si dual-junction tandem solar cells by epitaxial lift-off and print-transfer-assisted direct bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiong, Kanglin; Mi, Hongyi; Chang, Tzu-Hsuan

A novel method is developed to realize a III-V/Si dual-junction photovoltaic cell by combining epitaxial lift-off (ELO) and print-transfer-assisted bonding methods. The adoption of ELO enables III-V wafers to be recycled and reused, which can further lower the cost of III-V/Si photovoltaic panels. For demonstration, high crystal quality, micrometer-thick, GaAs/AlGaAs/GaAs films are lifted off, transferred, and directly bonded onto Si wafer without the use of any adhesive or bonding agents. The bonding interface is optically transparent and conductive both thermally and electrically. Prototype AlGaAs/Si dual-junction tandem solar cells have been fabricated and exhibit decent performance.

AlGaAs/Si dual-junction tandem solar cells by epitaxial lift-off and print-transfer-assisted direct bonding

DOE PAGES

Xiong, Kanglin; Mi, Hongyi; Chang, Tzu-Hsuan; ...

2018-01-04

A novel method is developed to realize a III-V/Si dual-junction photovoltaic cell by combining epitaxial lift-off (ELO) and print-transfer-assisted bonding methods. The adoption of ELO enables III-V wafers to be recycled and reused, which can further lower the cost of III-V/Si photovoltaic panels. For demonstration, high crystal quality, micrometer-thick, GaAs/AlGaAs/GaAs films are lifted off, transferred, and directly bonded onto Si wafer without the use of any adhesive or bonding agents. The bonding interface is optically transparent and conductive both thermally and electrically. Prototype AlGaAs/Si dual-junction tandem solar cells have been fabricated and exhibit decent performance.

Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires.

PubMed

Persichetti, Luca; Sgarlata, Anna; Mori, Stefano; Notarianni, Marco; Cherubini, Valeria; Fanfoni, Massimo; Motta, Nunzio; Balzarotti, Adalberto

2014-01-01

We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain. 81.07.Gf; 68.35.bg; 68.35.bj; 62.23.Eg.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-05-20

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-11-25

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Electro-Optical Characterization | Photovoltaic Research | NREL

Science.gov Websites

Applications Detection Range Temperature Range Non-Destructive? Image/ Mapping? Photoluminescence spectroscopy Determine bandgap, material quality. Identify defects. 0.4-2.7 µm 4-300 K Yes Yes Minority-carrier lifetime distributions in silicon wafers. 103 to 108 defects/cm2 Room temperature No Yes Reflectance spectroscopy

A quality quantitative method of silicon direct bonding based on wavelet image analysis

NASA Astrophysics Data System (ADS)

Tan, Xiao; Tao, Zhi; Li, Haiwang; Xu, Tiantong; Yu, Mingxing

2018-04-01

The rapid development of MEMS (micro-electro-mechanical systems) has received significant attention from researchers in various fields and subjects. In particular, the MEMS fabrication process is elaborate and, as such, has been the focus of extensive research inquiries. However, in MEMS fabrication, component bonding is difficult to achieve and requires a complex approach. Thus, improvements in bonding quality are relatively important objectives. A higher quality bond can only be achieved with improved measurement and testing capabilities. In particular, the traditional testing methods mainly include infrared testing, tensile testing, and strength testing, despite the fact that using these methods to measure bond quality often results in low efficiency or destructive analysis. Therefore, this paper focuses on the development of a precise, nondestructive visual testing method based on wavelet image analysis that is shown to be highly effective in practice. The process of wavelet image analysis includes wavelet image denoising, wavelet image enhancement, and contrast enhancement, and as an end result, can display an image with low background noise. In addition, because the wavelet analysis software was developed with MATLAB, it can reveal the bonding boundaries and bonding rates to precisely indicate the bond quality at all locations on the wafer. This work also presents a set of orthogonal experiments that consist of three prebonding factors, the prebonding temperature, the positive pressure value and the prebonding time, which are used to analyze the prebonding quality. This method was used to quantify the quality of silicon-to-silicon wafer bonding, yielding standard treatment quantities that could be practical for large-scale use.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Effect of PECVD SiNx/SiOyNx-Si interface property on surface passivation of silicon wafer

NASA Astrophysics Data System (ADS)

Jia, Xiao-Jie; Zhou, Chun-Lan; Zhu, Jun-Jie; Zhou, Su; Wang, Wen-Jing

2016-12-01

It is studied in this paper that the electrical characteristics of the interface between SiOyNx/SiNx stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiOyNx layer on interface parameters, such as interface state density Dit and fixed charge Qf, and the surface passivation quality of silicon are observed. Capacitance-voltage measurements reveal that inserting a thin SiOyNx layer between the SiNx and the silicon wafer can suppress Qf in the film and Dit at the interface. The positive Qf and Dit and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiOyNx film increasing. Prepared by deposition at a low temperature and a low ratio of N2O/SiH4 flow rate, the SiOyNx/SiNx stacks result in a low effective surface recombination velocity (Seff) of 6 cm/s on a p-type 1 Ω·cm-5 Ω·cm FZ silicon wafer. The positive relationship between Seff and Dit suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA050302) and the National Natural Science Foundation of China (Grant No. 61306076).

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Reticle haze: an industrial approach

NASA Astrophysics Data System (ADS)

Gough, Stuart; Gérard, Xavier; Bichebois, Pascal; Roche, Agnès; Sundermann, Frank; Guyader, Véronique; Bièron, Yann; Galvier, Jean; Nicoleau, Serge

2007-02-01

Crystal growth on advanced reticles is currently a world wide industrial problem in high end semiconductor production environment, crystals are mainly found on reticles that use high energy photons at 193nm wavelength. The most common crystals to be found on masks are ammonium sulphate, a combination of sulphate, from maskshop residues after clean, pellicle materials and storage conditions and amines from clean room, tool and storage environments. High energy photons act as a catalyst to form crystals on both the pattern side as well as the backglass surface. After a number of exposures crystals can grow in size and eventually become printable. In order to detect HAZE before critical dimensions have been reached suitable detection methods need to be implemented to ensure image integrity. These detection methods are different and complementary depending on the surface to be inspected. Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented

Prediction of ppm level electrical failure by using physical variation analysis

NASA Astrophysics Data System (ADS)

Hou, Hsin-Ming; Kung, Ji-Fu; Hsu, Y.-B.; Yamazaki, Y.; Maruyama, Kotaro; Toyoshima, Yuya; Chen, Chu-en

2016-03-01

The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology. Each of these factors play an important role in making the process more effective by ensuring that certain design- and process-specific parameters are kept within acceptable variation. Since chip size and pattern density are increasing accordingly, in-line real time catching the in-chip weak patterns/defects per million opportunities (WP-DPMO) plays more and more significant role for product yield with high density memory. However, the current in-line inspection tools focus on single layer defect inspection, not effectively and efficiently to catch multi-layer weak patterns/defects even through voltage contrast and/or special test structure design [1]-[2]. In general, the multi-layer weak patterns/defects are escaped easily by using in-line inspection and cause ignorance of product dysfunction until off-line time-consuming final PFA/EFA will be used. To effectively and efficiently in-line real time monitor the potential multi-layer weak patterns, we quantify the bridge electrical metric between contact and gate electrodes into CD physical metric via big data from the larger field of view (FOV: 8k x 16k with 3 nm pixel equalizes to image main field size 34 um x 34 um @ 3 nm pixel) e-beam quality image contour compared to layout GDS database (D2DB) as shown in Fig. 1. Hadoop-based distributed parallel computing is implemented to improve the performance of big data architectures, Fig. 2. Therefore, the state of art in-line real time catching in-chip potential multi-layer weak patterns can be proven and achieved by following some studying cases [3]. Therefore, manufacturing sources of variations can be partitioned to systematic and random variations by applying statistical techniques based on the big data fundamental infrastructures. After big data handling, the in-chip CD and AA variations are distinguished by their spatial correlation distance. For local variations (LV) there is no correlation, whereas for global variations (GV) the correlation distance is very large [7]-[9]. This is the first time to certificate the validation of spatial distribution from the affordable bias contour big data fundamental infrastructures. And then apply statistical techniques to dig out the variation sources. The GV come from systematic issue, which could be compensated by adaptive LT condition or OPC correction. But LV comes from random issue, which being considered as intrinsic problem such as structure, material, tool capability… etc. In this paper studying, we can find out the advanced technology node SRAM contact CD local variation (LV) dominates in total variation, about 70%. It often plays significant in-line real time catching WP-DPMO role of the product yield loss, especially for wafer edge is the worst loss within wafer distribution and causes serious reliability concern. The major root cause of variations comes from the PR material induced burr defect (LV), the second one comes from GV enhanced wafer edge short opportunity, which being attributed to three factors, first one factor is wafer edge CD deliberated enlargement for yield improvement as shown in Fig. 10. Second factor is overlaps/AA shifts due to tool capability dealing with incoming wafer's war page issue and optical periphery layout dependent working pitch issue as shown in Fig. 9 (1)., the last factor comes from wafer edge burr enhanced by wafer edge larger Photo Resistance (PR) spin centrifugal force. After implementing KPIs such as GV related AA/CD indexes as shown in Fig. 9 (1) and 10, respectively, and LV related burr index as shown in Fig. 11., we can construct the parts per million (PPM) level short probability model via multi-variables regression, canonical correlation analysis and logistic transformation. The model provides prediction of PPM level electrical failure by using in-line real time physical variation analysis. However in order to achieve Total Quality Management (TQM), the adaptive Statistical Process Control (SPC) charts can be implemented to in-line real time catch PPM level product malfunction at manufacturing stage. Applying for early stage monitor likes incoming raw material, Photo Resistance (PR) … etc., the LV related burr KPI SPC charts could be a powerful quality inspection vehicle. To sum up the paper's contributions, the state of art in-line real time catching in-chip potential multi-layer physical weak patterns can be proven and achieved effectively and efficiently to associate with PPM level product dysfunction.

Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers

NASA Astrophysics Data System (ADS)

van de Ven, Jamie S.; Khorasani, Fred

1989-07-01

There is a lot of inspection in the manufacturing of semiconductor devices. Generally, the more important a manufacturing step, the higher is the level of inspection. In some cases 100% of the wafers are inspected after certain steps. Inspection is a non-value added and expensive activity. It requires an army of "inspectors," often times expensive equipment and becomes a "bottle neck" when the level of inspection is high. Although inspection helps identify quality problems, it hurts productivity. The new management, quality and productivity philosophies recommend against over inspection. [Point #3 in Dr. Deming's 14 Points for Management (1)] 100% inspection is quite unnecessary . Often the nature of a process allows us to reduce inspection drastically and still maintain a high level of confidence in quality. In section 2, we discuss such situations and show that some elementary probability theory allows us to determine sample sizes and measure the chances of catching a bad "lot" and accepting a good lot. In section 3, we provide an example and application of the theory, and make a few comments on money and time saved because of this work. Finally, in section 4, we draw some conclusions about the new quality and productivity philosophies and how applied statisticians and engineers should study every situation individually and avoid blindly using methods and tables given in books.

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

Photoluminescence Imaging and LBIC Characterization of Defects in mc-Si Solar Cells

NASA Astrophysics Data System (ADS)

Sánchez, L. A.; Moretón, A.; Guada, M.; Rodríguez-Conde, S.; Martínez, O.; González, M. A.; Jiménez, J.

2018-05-01

Today's photovoltaic market is dominated by multicrystalline silicon (mc-Si) based solar cells with around 70% of worldwide production. In order to improve the quality of the Si material, a proper characterization of the electrical activity in mc-Si solar cells is essential. A full-wafer characterization technique such as photoluminescence imaging (PLi) provides a fast inspection of the wafer defects, though at the expense of the spatial resolution. On the other hand, a study of the defects at a microscopic scale can be achieved through the light-beam induced current technique. The combination of these macroscopic and microscopic resolution techniques allows a detailed study of the electrical activity of defects in mc-Si solar cells. In this work, upgraded metallurgical-grade Si solar cells are studied using these two techniques.

Low temperature InP /Si wafer bonding using boride treated surface

NASA Astrophysics Data System (ADS)

Huang, Hui; Ren, Xiaomin; Wang, Wenjuan; Song, Hailan; Wang, Qi; Cai, Shiwei; Huang, Yongqing

2007-04-01

An approach for InP /Si wafer bonding based on boride-solution treatment was presented. The bonding energy is higher than the InP fracture energy by annealing at 280°C. An In0.53Ga0.47As/InP multiple-quantum-well (MQW) structure grown on InP was transferred onto Si substrate via the bonding process. X-ray diffraction and photoluminescence reveal that crystal quality of the bonded MQW was preserved. A thin B2O3-POx-SiO2 oxide layer of about 28nm thick at the bonding interface was detected. X-ray photoelectron spectroscopy and Raman analyses indicate that the formation of oxygen bridging bonds by boride treatment is responsible for the strong fusion obtained at such low temperature.

Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires

PubMed Central

2014-01-01

We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain. PACS 81.07.Gf; 68.35.bg; 68.35.bj; 62.23.Eg PMID:25114649

NASA Tech Briefs, December 2013

NASA Technical Reports Server (NTRS)

2013-01-01

Topics include: Microwave Kinetic Inductance Detector With; Selective Polarization Coupling; Flexible Microstrip Circuits for; Superconducting Electronics; CFD Extraction Tool for TecPlot From DPLR Solutions; RECOVIR Software for Identifying Viruses; Enhanced Contact Graph Routing (ECGR) MACHETE Simulation Model; Orbital Debris Engineering Model (ORDEM) v.3; Scatter-Reducing Sounding Filtration Using a Genetic Algorithm and Mean Monthly Standard Deviation; Thermo-Mechanical Methodology for Stabilizing Shape Memory Alloy Response; Hermetic Seal Designs for Sample Return Sample Tubes; Silicon Alignment Pins: An Easy Way To Realize a Wafer-to-Wafer Alignment; Positive-Buoyancy Rover for Under Ice Mobility; Electric Machine With Boosted Inductance to Stabilize Current Control; International Space Station-Based Electromagnetic Launcher for Space Science Payloads; Advanced Hybrid Spacesuit Concept Featuring Integrated Open Loop and Closed Loop Ventilation Systems; Data Quality Screening Service.

High-quality AlN grown on a thermally decomposed sapphire surface

NASA Astrophysics Data System (ADS)

Hagedorn, S.; Knauer, A.; Brunner, F.; Mogilatenko, A.; Zeimer, U.; Weyers, M.

2017-12-01

In this study we show how to realize a self-assembled nano-patterned sapphire surface on 2 inch diameter epi-ready wafer and the subsequent AlN overgrowth both in the same metal-organic vapor phase epitaxial process. For this purpose in-situ annealing in H2 environment was applied prior to AlN growth to thermally decompose the c-plane oriented sapphire surface. By proper AlN overgrowth management misoriented grains that start to grow on non c-plane oriented facets of the roughened sapphire surface could be overcome. We achieved crack-free, atomically flat AlN layers of 3.5 μm thickness. The layers show excellent material quality homogeneously over the whole wafer as proved by the full width at half maximum of X-ray measured ω-rocking curves of 120 arcsec to 160 arcsec for the 002 reflection and 440 arcsec to 550 arcsec for the 302 reflection. The threading dislocation density is 2 ∗ 109 cm-2 which shows that the annealing and overgrowth process investigated in this work leads to cost-efficient AlN templates for UV LED devices.

Photomask quality evaluation using lithography simulation and multi-detector MVM-SEM

NASA Astrophysics Data System (ADS)

Ito, Keisuke; Murakawa, Tsutomu; Fukuda, Naoki; Shida, Soichi; Iwai, Toshimichi; Matsumoto, Jun; Nakamura, Takayuki; Matsushita, Shohei; Hagiwara, Kazuyuki; Hara, Daisuke

2013-06-01

The detection and management of mask defects which are transferred onto wafer becomes more important day by day. As the photomask patterns becomes smaller and more complicated, using Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) with Optical Proximity Correction (OPC). To evaluate photomask quality, the current method uses aerial imaging by optical inspection tools. This technique at 1Xnm node has a resolution limit because small defects will be difficult to detect. We already reported the MEEF influence of high-end photomask using wide FOV SEM contour data of "E3630 MVM-SEM®" and lithography simulator "TrueMask® DS" of D2S Inc. in the prior paper [1]. In this paper we evaluate the correlation between our evaluation method and optical inspection tools as ongoing assessment. Also in order to reduce the defect classification work, we can compose the 3 Dimensional (3D) information of defects and can judge whether repairs of defects would be required. Moreover, we confirm the possibility of wafer plane CD measurement based on the combination between E3630 MVM-SEM® and 3D lithography simulation.

Macrodefect-free, large, and thick GaN bulk crystals for high-quality 2–6 in. GaN substrates by hydride vapor phase epitaxy with hardness control

NASA Astrophysics Data System (ADS)

Fujikura, Hajime; Konno, Taichiro; Suzuki, Takayuki; Kitamura, Toshio; Fujimoto, Tetsuji; Yoshida, Takehiro

2018-06-01

On the basis of a novel crystal hardness control, we successfully realized macrodefect-free, large (2–6 in.) and thick +c-oriented GaN bulk crystals by hydride vapor phase epitaxy. Without the hardness control, the introduction of macrodefects including inversion domains and/or basal-plane dislocations seemed to be indispensable to avoid crystal fracture in GaN growth with millimeter thickness. However, the presence of these macrodefects tended to limit the applicability of the GaN substrate to practical devices. The present technology markedly increased the GaN crystal hardness from below 20 to 22 GPa, thus increasing the available growth thickness from below 1 mm to over 6 mm even without macrodefect introduction. The 2 and 4 in. GaN wafers fabricated from these crystals had extremely low dislocation densities in the low- to mid-105 cm‑2 range and low off-angle variations (2 in.: <0.1° 4 in.: ∼0.2°). The realization of such high-quality 6 in. wafers is also expected.

Large-roll growth of 25-inch hexagonal BN monolayer film for self-release buffer layer of free-standing GaN wafer

NASA Astrophysics Data System (ADS)

Wu, Chenping; Soomro, Abdul Majid; Sun, Feipeng; Wang, Huachun; Huang, Youyang; Wu, Jiejun; Liu, Chuan; Yang, Xiaodong; Gao, Na; Chen, Xiaohong; Kang, Junyong; Cai, Duanjun

2016-10-01

Hexagonal boron nitride (h-BN) is known as promising 2D material with a wide band-gap (~6 eV). However, the growth size of h-BN film is strongly limited by the size of reaction chamber. Here, we demonstrate the large-roll synthesis of monolayer and controllable sub-monolayer h-BN film on wound Cu foil by low pressure chemical vapor deposition (LPCVD) method. By winding the Cu foil substrate into mainspring shape supported by a multi-prong quartz fork, the reactor size limit could be overcome by extending the substrate area to a continuous 2D curl of plane inward. An extremely large-size monolayer h-BN film has been achieved over 25 inches in a 1.2” tube. The optical band gap of h-BN monolayer was determined to be 6.0 eV. The h-BN film was uniformly transferred onto 2” GaN or 4” Si wafer surfaces as a release buffer layer. By HVPE method, overgrowth of thick GaN wafer over 200 μm has been achieved free of residual strain, which could provide high quality homo-epitaxial substrate.

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Control of polysilicon on-film particulates with on-product measurements

NASA Astrophysics Data System (ADS)

Barker, Judith B.; Chain, Elizabeth E.; Plachecki, Vincent E.

1997-08-01

Historically, a number of in-line particle measurements have been performed on separate test wafers included with product wafers during polysilicon processes. By performing film thickness and particulate measurements directly on product wafers, instead, a number of benefits accrue: (1) reduced test wafer usage, (2) reduced test wafer storage requirements, (3) reduced need for equipment to reclaim test wafers, (4) reduced need for direct labor to reclaim test wafers, and (5) reduced engineering 'false alarms' due to incorrectly processed test wafers. Implementation of on-product measurements for the polysilicon diffusion process required a number of changes in both philosophy and methodology. We show the necessary steps to implementation of on-product particle measurements with concern for overall manufacturing efficiency and the need to maintain appropriate control. Particle results from the Tencor 7600 Surfscan are presented.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

High quality factor single-crystal diamond mechanical resonators

NASA Astrophysics Data System (ADS)

Ovartchaiyapong, P.; Pascal, L. M. A.; Myers, B. A.; Lauria, P.; Bleszynski Jayich, A. C.

2012-10-01

Single-crystal diamond is a promising material for microelectromechanical systems (MEMs) because of its low mechanical loss, compatibility with extreme environments, and built-in interface to high-quality spin centers. But its use has been limited by challenges in processing and growth. We demonstrate a wafer bonding-based technique to form diamond on insulator, from which we make single-crystal diamond micromechanical resonators with mechanical quality factors as high as 338 000 at room temperature. Variable temperature measurements down to 10 K reveal a nonmonotonic dependence of quality factor on temperature. These resonators enable integration of single-crystal diamond into MEMs technology for classical and quantum applications.

Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

NASA Astrophysics Data System (ADS)

Weatherwax Scott, Caroline; Tsareff, Christopher R.

1990-06-01

One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles played by the process engineering expert and the knowledge engineer are discussed. The features of the systems are shown, particularly the interactive quality of the consultations and the ease of system use.

Development of graphene process control by industrial optical spectroscopy setup

NASA Astrophysics Data System (ADS)

Fursenko, O.; Lukosius, M.; Lupina, G.; Bauer, J.; Villringer, C.; Mai, A.

2017-06-01

The successful integration of graphene into microelectronic devices depends strongly on the availability of fast and nondestructive characterization methods of graphene grown by CVD on large diameter production wafers [1-3] which are in the interest of the semiconductor industry. Here, a high-throughput optical metrology method for measuring the thickness and uniformity of large-area graphene sheets is demonstrated. The method is based on the combination of spectroscopic ellipsometry and normal incidence reflectometry in UV-Vis wavelength range (200-800 nm) with small light spots ( 30 μm2) realized in wafer optical metrology tool. In the first step graphene layers were transferred on a SiO2/Si substrate in order to determine the optical constants of graphene by the combination of multi-angle ellipsometry and reflectometry. Then these data were used for the development of a process control recipe of CVD graphene on 200 mm Ge(100)/Si(100) wafers. The graphene layer quality was additionally monitored by Raman spectroscopy. Atomic force microscopy measurements were performed for micro topography evaluation. In consequence, a robust recipe for unambiguous thickness monitoring of all components of a multilayer film stack, including graphene, surface residuals or interface layer underneath graphene and surface roughness is developed. Optical monitoring of graphene thickness uniformity over a wafer has shown an excellent long term stability (s=0.004 nm) regardless of the growth of interfacial GeO2 and surface roughness. The sensitivity of the optical identification of graphene during microelectronic processing was evaluated. This optical metrology technique with combined data collection exhibit a fast and highly precise method allowing one an unambiguous detection of graphene after transferring as well as after the CVD deposition process on a Ge(100)/Si(100) wafer. This approach is well suited for industrial applications due to its repeatability and flexibility.

Design and performance test of a MEMS vibratory gyroscope with a novel AGC force rebalance control

NASA Astrophysics Data System (ADS)

Sung, Woon-Tahk; Sung, Sangkyung; Lee, Jang Gyu; Kang, Taesam

2007-10-01

In this paper, the development and performance test results of a laterally oscillating MEMS gyroscope using a novel force rebalance control strategy are presented. The micromachined structure and electrodes are fabricated using the deep reactive ion etching (DRIE) and anodic wafer bonding process. The high quality factor required for the resonance-based sensor is achieved using a vacuum-sealed device package. A systematic design approach of the force rebalance control is applied via a modified automatic gain control (AGC) method. The rebalance control design takes advantages of a novel AGC loop modification, which allows the approximation of the system's dynamics into a simple linear form. Using the proposed modification of AGC and the rebalance strategy that maintains a biased oscillation, a number of performance improvements including bandwidth extension and widened operating range were observed to be achieved. Finally, the experimental results of the gyroscope's practical application verify the feasibility and performance of the developed sensor.

Internal gas and liquid distributor for electrodeionization device

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Henry, Michael P.; Datta, Saurav

2016-05-17

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The gas and aqueous fluid are introduced into each basic wafer via a porous gas distributor which disperses the gas as micro-sized bubbles laterally throughout the distributor before entering the wafer. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme or inorganic catalyst to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

Controlling aliased dynamics in motion systems? An identification for sampled-data control approach

NASA Astrophysics Data System (ADS)

Oomen, Tom

2014-07-01

Sampled-data control systems occasionally exhibit aliased resonance phenomena within the control bandwidth. The aim of this paper is to investigate the aspect of these aliased dynamics with application to a high performance industrial nano-positioning machine. This necessitates a full sampled-data control design approach, since these aliased dynamics endanger both the at-sample performance and the intersample behaviour. The proposed framework comprises both system identification and sampled-data control. In particular, the sampled-data control objective necessitates models that encompass the intersample behaviour, i.e., ideally continuous time models. Application of the proposed approach on an industrial wafer stage system provides a thorough insight and new control design guidelines for controlling aliased dynamics.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Research on annealing and properties of TlBr crystals for radiation detector use

NASA Astrophysics Data System (ADS)

Zhiping, Zheng; Yongtao, Yu; Dongxiang, Zhou; Shuping, Gong; Qiuyun, Fu

2014-03-01

In this paper, annealing was carried out in air after cutting, polishing and etching to eliminate defects introduced by crystal and wafer preparation work. The effect of annealing temperature and time on the properties of TlBr crystals was investigated. The crystal quality was characterized by infrared (IR) transmittance spectrum, I-V measurement, XRD and energy response spectrum. In the annealing temperature range (100-320 °C) applied, it was found that higher temperature was more effective for improving quality. Furthermore, it is proved that an appropriate annealing time is vital for better crystal quality.

In collaboration with mask suppliers for change management enhancement

NASA Astrophysics Data System (ADS)

Deng, Erwin; Lee, Chun Der; Lee, Rachel

2013-06-01

For those wafer fabs that have no their own maskshops, the main target of mask quality department is to gain stable mask quality performance through effective supplier management, and therefore achieves competitive business results. After dealing with lots of mask data preparation (MDP) quality problems with suppliers, we have found that incomplete change management procedures are one of major sources that induce incorrect mask data for writing. This article will share our experience in how to enhance change management flows with mask suppliers together and will also show the utility after a series of flow improvement actions.

Materials Development for Auxiliary Components for Large Compact Mo/Au TES Arrays

NASA Technical Reports Server (NTRS)

Finkbeiner, F. m.; Chervenak, J. A.; Bandler, S. R.; Brekosky, R.; Brown, A. D.; Figueroa-Feliciano, E.; Iyomoto, N.; Kelley, R. L.; Kilbourne, C. A.; Porter, F. S.;

Highly-efficient GaN-based light-emitting diode wafers on La0.3Sr1.7AlTaO6 substrates

PubMed Central

Wang, Wenliang; Yang, Weijia; Gao, Fangliang; Lin, Yunhao; Li, Guoqiang

2015-01-01

Highly-efficient GaN-based light-emitting diode (LED) wafers have been grown on La0.3Sr1.7AlTaO6 (LSAT) substrates by radio-frequency molecular beam epitaxy (RF-MBE) with optimized growth conditions. The structural properties, surface morphologies, and optoelectronic properties of as-prepared GaN-based LED wafers on LSAT substrates have been characterized in detail. The characterizations have revealed that the full-width at half-maximums (FWHMs) for X-ray rocking curves of GaN(0002) and GaN(10-12) are 190.1 and 210.2 arcsec, respectively, indicating that high crystalline quality GaN films have been obtained. The scanning electron microscopy and atomic force microscopy measurements have shown the very smooth p-GaN surface with the surface root-mean-square (RMS) roughness of 1.3 nm. The measurements of low-temperature and room-temperature photoluminescence help to calculate the internal quantum efficiency of 79.0%. The as-grown GaN-based LED wafers have been made into LED chips with the size of 300 × 300 μm2 by the standard process. The forward voltage, the light output power and the external quantum efficiency for LED chips are 19.6 W, 2.78 V, and 40.2%, respectively, at a current of 20 mA. These results reveal the high optoelectronic properties of GaN-based LEDs on LSAT substrates. This work brings up a broad future application of GaN-based devices. PMID:25799042

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Fourier ptychographic microscopy at telecommunication wavelengths using a femtosecond laser

NASA Astrophysics Data System (ADS)

Ahmed, Ishtiaque; Alotaibi, Maged; Skinner-Ramos, Sueli; Dominguez, Daniel; Bernussi, Ayrton A.; de Peralta, Luis Grave

2017-12-01

We report the implementation of the Fourier Ptychographic Microscopy (FPM) technique, a phase retrieval technique, at telecommunication wavelengths using a low-coherence ultrafast pulsed laser source. High quality images, near speckle-free, were obtained with the proposed approach. We demonstrate that FPM can also be used to image periodic features through a silicon wafer.

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Development of critical dimension measurement scanning electron microscope for ULSI (S-8000 series)

NASA Astrophysics Data System (ADS)

Ezumi, Makoto; Otaka, Tadashi; Mori, Hiroyoshi; Todokoro, Hideo; Ose, Yoichi

1996-05-01

The semiconductor industry is moving from half-micron to quarter-micron design rules. To support this evolution, Hitachi has developed a new critical dimension measurement scanning electron microscope (CD-SEM), the model S-8800 series, for quality control of quarter- micron process lines. The new CD-SEM provides detailed examination of process conditions with 5 nm resolution and 5 nm repeatability (3 sigma) at accelerating voltage 800 V using secondary electron imaging. In addition, a newly developed load-lock system has a capability of achieving a high sample throughput of 20 wafers/hour (5 point measurements per wafer) under continuous operation. To support user friendliness, the system incorporates a graphical user interface (GUI), an automated pattern recognition system which helps locating measurement points, both manual and semi-automated operation, and user-programmable operating parameters.

The CD control improvement by using CDSEM 2D measurement of complex OPC patterns

NASA Astrophysics Data System (ADS)

Chou, William; Cheng, Jeffrey; Lee, Adder; Cheng, James; Tzeng, Alex C.; Lu, Colbert; Yang, Ray; Lee, Hong Jen; Bandoh, Hideaki; Santo, Izumi; Zhang, Hao; Chen, Chien Kang

2016-10-01

As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

NASA Technical Reports Server (NTRS)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Progress on complementary patterning using plasmon-excited electron beamlets (Conference Presentation)

NASA Astrophysics Data System (ADS)

Du, Zhidong; Chen, Chen; Pan, Liang

2017-04-01

Maskless lithography using parallel electron beamlets is a promising solution for next generation scalable maskless nanolithography. Researchers have focused on this goal but have been unable to find a robust technology to generate and control high-quality electron beamlets with satisfactory brightness and uniformity. In this work, we will aim to address this challenge by developing a revolutionary surface-plasmon-enhanced-photoemission (SPEP) technology to generate massively-parallel electron beamlets for maskless nanolithography. The new technology is built upon our recent breakthroughs in plasmonic lenses, which will be used to excite and focus surface plasmons to generate massively-parallel electron beamlets through photoemission. Specifically, the proposed SPEP device consists of an array of plasmonic lens and electrostatic micro-lens pairs, each pair independently producing an electron beamlet. During lithography, a spatial optical modulator will dynamically project light onto individual plasmonic lenses to control the switching and brightness of electron beamlets. The photons incident onto each plasmonic lens are concentrated into a diffraction-unlimited spot as localized surface plasmons to excite the local electrons to near their vacuum levels. Meanwhile, the electrostatic micro-lens extracts the excited electrons to form a focused beamlet, which can be rastered across a wafer to perform lithography. Studies showed that surface plasmons can enhance the photoemission by orders of magnitudes. This SPEP technology can scale up the maskless lithography process to write at wafers per hour. In this talk, we will report the mechanism of the strong electron-photon couplings and the locally enhanced photoexcitation, design of a SPEP device, overview of our proof-of-concept study, and demonstrated parallel lithography of 20-50 nm features.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

Epitaxial thinning process

NASA Technical Reports Server (NTRS)

Siegel, C. M. (Inventor)

1984-01-01

A method is described for thinning an epitaxial layer of a wafer that is to be used in producing diodes having a specified breakdown voltage and which also facilitates the thinning process. Current is passed through the epitaxial layer, by connecting a current source between the substrate of the wafer and an electrolyte in which the wafer is immersed. When the wafer is initially immersed, the voltage across the wafer initially drops and then rises at a steep rate. When light is applied to the wafer the voltage drops, and when the light is interrupted the voltage rises again. These changes in voltage, each indicate the breakdown voltage of a Schottky diode that could be prepared from the wafer at that time. The epitaxial layer is thinned by continuing to apply current through the wafer while it is immersed and light is applied, to form an oxide film and when the oxide film is thick the wafer can then be cleaned of oxide and the testing and thinning continued. Uninterrupted thinning can be achieved by first forming an oxide film, and then using an electrolyte that dissolves the oxide about as fast as it is being formed, to limit the thickness of the oxide layer.

Role of the blocking capacitor in control of ion energy distributions in pulsed capacitively coupled plasmas sustained in Ar/CF{sub 4}/O{sub 2}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Sang-Heon, E-mail: ssongs@umich.edu; Kushner, Mark J., E-mail: mjkush@umich.edu

2014-03-15

In plasma etching for microelectronics fabrication, the quality of the process is in large part determined by the ability to control the ion energy distribution (IED) onto the wafer. To achieve this control, dual frequency capacitively coupled plasmas (DF-CCPs) have been developed with the goal of separately controlling the magnitude of the fluxes of ions and radicals with the high frequency (HF) and the shape of the IED with the low frequency (LF). In steady state operation, plasma properties are determined by a real time balance between electron sources and losses. As such, for a given geometry, pressure, and frequencymore » of operation, the latitude for controlling the IED may be limited. Pulsed power is one technique being investigated to provide additional degrees of freedom to control the IED. In one configuration of a DF-CCP, the HF power is applied to the upper electrode and LF power is applied to the lower electrode which is serially connected to a blocking capacitor (BC) which generates a self dc-bias. In the steady state, the value of the dc-bias is, in fact, constant. During pulsed operation, however, there may be time modulation of the dc-bias which provides an additional means to control the IED. In this paper, IEDs to the wafer in pulsed DF-CCPs sustained in Ar/CF{sub 4}/O{sub 2} are discussed with results from a two-dimensional plasma hydrodynamics model. The IED can be manipulated depending on whether the LF or HF power is pulsed. The dynamic range of the control can be tuned by the dc-bias generated on the substrate, whose time variation depends on the size of the BC during pulsed operation. It was found that high energy ions can be preferentially produced when pulsing the HF power and low energy ions are preferentially produced when pulsing the LF power. A smaller BC value which allows the bias to follow the change in charged particle fluxes produces a larger dynamic range with which to control IEDs.« less

Thin layer composite unimorph ferroelectric driver and sensor

NASA Technical Reports Server (NTRS)

Hellbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Jr., Antony (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

2004-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

NASA Technical Reports Server (NTRS)

Helbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Antony, Jr. (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

1995-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

High-speed atomic force microscopy and peak force tapping control

NASA Astrophysics Data System (ADS)

Hu, Shuiqing; Mininni, Lars; Hu, Yan; Erina, Natalia; Kindt, Johannes; Su, Chanmin

2012-03-01

ITRS Roadmap requires defect size measurement below 10 nanometers and challenging classifications for both blank and patterned wafers and masks. Atomic force microscope (AFM) is capable of providing metrology measurement in 3D at sub-nanometer accuracy but has long suffered from drawbacks in throughput and limitation of slow topography imaging without chemical information. This presentation focus on two disruptive technology developments, namely high speed AFM and quantitative nanomechanical mapping, which enables high throughput measurement with capability of identifying components through concurrent physical property imaging. The high speed AFM technology has allowed the imaging speed increase by 10-100 times without loss of the data quality. Such improvement enables the speed of defect review on a wafer to increase from a few defects per hour to nearly 100 defects an hour, approaching the requirements of ITRS Roadmap. Another technology development, Peak Force Tapping, substantially simplified the close loop system response, leading to self-optimization of most challenging samples groups to generate expert quality data. More importantly, AFM also simultaneously provides a series of mechanical property maps with a nanometer spatial resolution during defect review. These nanomechanical maps (including elastic modulus, hardness, and surface adhesion) provide complementary information for elemental analysis, differentiate defect materials by their physical properties, and assist defect classification beyond topographic measurements. This paper will explain the key enabling technologies, namely high speed tip-scanning AFM using innovative flexure design and control algorithm. Another critical element is AFM control using Peak Force Tapping, in which the instantaneous tip-sample interaction force is measured and used to derive a full suite of physical properties at each imaging pixel. We will provide examples of defect review data on different wafers and media disks. The similar AFM-based defect review capacity was also applied to EUV masks.

Computer-aided analysis of cutting processes for brittle materials

NASA Astrophysics Data System (ADS)

Ogorodnikov, A. I.; Tikhonov, I. N.

2017-12-01

This paper is focused on 3D computer simulation of cutting processes for brittle materials and silicon wafers. Computer-aided analysis of wafer scribing and dicing is carried out with the use of the ANSYS CAE (computer-aided engineering) software, and a parametric model of the processes is created by means of the internal ANSYS APDL programming language. Different types of tool tip geometry are analyzed to obtain internal stresses, such as a four-sided pyramid with an included angle of 120° and a tool inclination angle to the normal axis of 15°. The quality of the workpieces after cutting is studied by optical microscopy to verify the FE (finite-element) model. The disruption of the material structure during scribing occurs near the scratch and propagates into the wafer or over its surface at a short range. The deformation area along the scratch looks like a ragged band, but the stress width is rather low. The theory of cutting brittle semiconductor and optical materials is developed on the basis of the advanced theory of metal turning. The fall of stress intensity along the normal on the way from the tip point to the scribe line can be predicted using the developed theory and with the verified FE model. The crystal quality and dimensions of defects are determined by the mechanics of scratching, which depends on the shape of the diamond tip, the scratching direction, the velocity of the cutting tool and applied force loads. The disunity is a rate-sensitive process, and it depends on the cutting thickness. The application of numerical techniques, such as FE analysis, to cutting problems enhances understanding and promotes the further development of existing machining technologies.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Optic probe for semiconductor characterization

DOEpatents

Sopori, Bhushan L [Denver, CO; Hambarian, Artak [Yerevan, AM

2008-09-02

Described herein is an optical probe (120) for use in characterizing surface defects in wafers, such as semiconductor wafers. The optical probe (120) detects laser light reflected from the surface (124) of the wafer (106) within various ranges of angles. Characteristics of defects in the surface (124) of the wafer (106) are determined based on the amount of reflected laser light detected in each of the ranges of angles. Additionally, a wafer characterization system (100) is described that includes the described optical probe (120).

An Update on Structural Seal Development at NASA GRC

NASA Technical Reports Server (NTRS)

Dunlap, Pat; Steinetz, Bruce; Finkbeiner, Josh; DeMange, Jeff; Taylor, Shawn; Daniels, Chris; Oswald, Jay

2006-01-01

A viewgraph presentation describing advanced structural seal development for NASA exploration is shown. The topics include: 1) GRC Structural Seals Team Research Areas; 2) Research Areas & Objective; 3) Wafer Seal Geometry/Flow Investigations; 4) Wafer Seal Installation DOE Study; 5) Results of Wafer Seal Installation DOE Study; 6) Wafer Geometry Study: Thickness Variations; 7) Wafer Geometry Study: Full-Size vs. Half-Size Wafers; 8) Spring Tube Seal Development; 9) Resiliency Improvement for Rene 41 Spring Tube; 10) Spring Tube Seals: Go-Forward Plan; 11) High Temperature Seal Preloader Development: TZM Canted Coil Spring; 12) TZM Canted Coil Spring Development; 13) Arc Jet Test Rig Development; and 14) Arc Jet Test Rig Status.

Strong emission of terahertz radiation from nanostructured Ge surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Chul; Maeng, Inhee; Kee, Chul-Sik, E-mail: cskee@gist.ac.kr

2015-06-29

Indirect band gap semiconductors are not efficient emitters of terahertz radiation. Here, we report strong emission of terahertz radiation from germanium wafers with nanostructured surfaces. The amplitude of THz radiation from an array of nano-bullets (nano-cones) is more than five (three) times larger than that from a bare-Ge wafer. The power of the terahertz radiation from a Ge wafer with an array of nano-bullets is comparable to that from n-GaAs wafers, which have been widely used as a terahertz source. We find that the THz radiation from Ge wafers with the nano-bullets is even more powerful than that from n-GaAsmore » for frequencies below 0.6 THz. Our results suggest that introducing properly designed nanostructures on indirect band gap semiconductor wafers is a simple and cheap method to improve the terahertz emission efficiency of the wafers significantly.« less

Method for nanomachining high aspect ratio structures

DOEpatents

Yun, Wenbing; Spence, John; Padmore, Howard A.; MacDowell, Alastair A.; Howells, Malcolm R.

2004-11-09

A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Correlating optical infrared and electronic properties of low tellurium doped GaSb bulk crystals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Roodenko, K., E-mail: kroodenko@intelliepi.com; Liao, P.-K.; Lan, D.

2016-04-07

Control over the Te doping concentration is especially challenging in the mass-production of optically transparent, high-resistivity Te-doped GaSb crystals. Driven by the necessity to perform fast, robust, and non-destructive quality control of the Te doping homogeneity of the optically transparent large-diameter GaSb wafers, we correlated electronic and optical infrared properties of Te-doped GaSb crystals. The study was based on the experimental Hall and Fourier-Transform Infrared (FTIR) data collected from over 50 samples of the low-doped n-type material (carrier concentration of 6 × 10{sup 16} cm{sup −3} to 7 × 10{sup 17} cm{sup −3}) and the Te-doped p-type GaSb (4.6 ×more » 10{sup 15} cm{sup −3} to 1 × 10{sup 16} cm{sup −3}). For the n-type GaSb, the analysis of the FTIR data was performed using free carrier absorption model, while for the p-type material, the absorption was modeled using inter-valence band absorption mechanism. Using the correlation between the Hall and the IR data, FTIR maps across the wafers allow a fast and reliable way to estimate carrier concentration profile within the wafer.« less

Patterned growth of carbon nanotubes obtained by high density plasma chemical vapor deposition

NASA Astrophysics Data System (ADS)

Mousinho, A. P.; Mansano, R. D.

2015-03-01

Patterned growth of carbon nanotubes by chemical vapor deposition represents an assembly approach to place and orient nanotubes at a stage as early as when they are synthesized. In this work, the carbon nanotubes were obtained at room temperature by High Density Plasmas Chemical Vapor Deposition (HDPCVD) system. This CVD system uses a new concept of plasma generation, where a planar coil coupled to an RF system for plasma generation was used with an electrostatic shield for plasma densification. In this mode, high density plasmas are obtained. We also report the patterned growth of carbon nanotubes on full 4-in Si wafers, using pure methane plasmas and iron as precursor material (seed). Photolithography processes were used to pattern the regions on the silicon wafers. The carbon nanotubes were characterized by micro-Raman spectroscopy, the spectra showed very single-walled carbon nanotubes axial vibration modes around 1590 cm-1 and radial breathing modes (RBM) around 120-400 cm-1, confirming that high quality of the carbon nanotubes obtained in this work. The carbon nanotubes were analyzed by atomic force microscopy and scanning electron microscopy too. The results showed that is possible obtain high-aligned carbon nanotubes with patterned growth on a silicon wafer with high reproducibility and control.

Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

1978-01-01

Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Arrangement, Dopant Source, And Method For Making Solar Cells

DOEpatents

Rohatgi, Ajeet; Krygowski, Thomas W.

1999-10-26

Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place. Finally, the cell wafers receive an anti-reflective coating and electrical contacts for the purpose of gathering electrical charge.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Automatic cassette to cassette radiant impulse processor

NASA Astrophysics Data System (ADS)

Sheets, Ronald E.

1985-01-01

Single wafer rapid annealing using high temperature isothermal processing has become increasingly popular in recent years. In addition to annealing, this process is also being investigated for suicide formation, passivation, glass reflow and alloying. Regardless of the application, there is a strong necessity to automate in order to maintain process control, repeatability, cleanliness and throughput. These requirements have been carefully addressed during the design and development of the Model 180 Radiant Impulse Processor which is a totally automatic cassette to cassette wafer processing system. Process control and repeatability are maintained by a closed loop optical pyrometer system which maintains the wafer at the programmed temperature-time conditions. Programmed recipes containing up to 10 steps may be easily entered on the computer keyboard or loaded in from a recipe library stored on a standard 5 {1}/{4″} floppy disk. Cold wall heating chamber construction, controlled environment (N 2, A, forming gas) and quartz wafer carriers prevent contamination of the wafer during high temperature processing. Throughputs of 150-240 wafers per hour are achieved by quickly heating the wafer to temperature (450-1400°C) in 3-6 s with a high intensity, uniform (± 1%) radiant flux of 100 {W}/{cm 2}, parallel wafer handling system and a wafer cool down stage.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Study on the optimization of the deposition rate of planetary GaN-MOCVD films based on CFD simulation and the corresponding surface model

PubMed Central

Fei, Ze-yuan; Xu, Yi-feng; Wang, Jie; Fan, Bing-feng; Ma, Xue-jin; Wang, Gang

2018-01-01

Metal-organic chemical vapour deposition (MOCVD) is a key technique for fabricating GaN thin film structures for light-emitting and semiconductor laser diodes. Film uniformity is an important index to measure equipment performance and chip processes. This paper introduces a method to improve the quality of thin films by optimizing the rotation speed of different substrates of a model consisting of a planetary with seven 6-inch wafers for the planetary GaN-MOCVD. A numerical solution to the transient state at low pressure is obtained using computational fluid dynamics. To evaluate the role of the different zone speeds on the growth uniformity, single factor analysis is introduced. The results show that the growth rate and uniformity are strongly related to the rotational speed. Next, a response surface model was constructed by using the variables and the corresponding simulation results. The optimized combination of the matching of different speeds is also proposed as a useful reference for applications in industry, obtained by a response surface model and genetic algorithm with a balance between the growth rate and the growth uniformity. This method can save time, and the optimization can obtain the most uniform and highest thin film quality. PMID:29515883

Study on the optimization of the deposition rate of planetary GaN-MOCVD films based on CFD simulation and the corresponding surface model.

PubMed

Li, Jian; Fei, Ze-Yuan; Xu, Yi-Feng; Wang, Jie; Fan, Bing-Feng; Ma, Xue-Jin; Wang, Gang

2018-02-01

Metal-organic chemical vapour deposition (MOCVD) is a key technique for fabricating GaN thin film structures for light-emitting and semiconductor laser diodes. Film uniformity is an important index to measure equipment performance and chip processes. This paper introduces a method to improve the quality of thin films by optimizing the rotation speed of different substrates of a model consisting of a planetary with seven 6-inch wafers for the planetary GaN-MOCVD. A numerical solution to the transient state at low pressure is obtained using computational fluid dynamics. To evaluate the role of the different zone speeds on the growth uniformity, single factor analysis is introduced. The results show that the growth rate and uniformity are strongly related to the rotational speed. Next, a response surface model was constructed by using the variables and the corresponding simulation results. The optimized combination of the matching of different speeds is also proposed as a useful reference for applications in industry, obtained by a response surface model and genetic algorithm with a balance between the growth rate and the growth uniformity. This method can save time, and the optimization can obtain the most uniform and highest thin film quality.

Study on the optimization of the deposition rate of planetary GaN-MOCVD films based on CFD simulation and the corresponding surface model

NASA Astrophysics Data System (ADS)

Li, Jian; Fei, Ze-yuan; Xu, Yi-feng; Wang, Jie; Fan, Bing-feng; Ma, Xue-jin; Wang, Gang

2018-02-01

Metal-organic chemical vapour deposition (MOCVD) is a key technique for fabricating GaN thin film structures for light-emitting and semiconductor laser diodes. Film uniformity is an important index to measure equipment performance and chip processes. This paper introduces a method to improve the quality of thin films by optimizing the rotation speed of different substrates of a model consisting of a planetary with seven 6-inch wafers for the planetary GaN-MOCVD. A numerical solution to the transient state at low pressure is obtained using computational fluid dynamics. To evaluate the role of the different zone speeds on the growth uniformity, single factor analysis is introduced. The results show that the growth rate and uniformity are strongly related to the rotational speed. Next, a response surface model was constructed by using the variables and the corresponding simulation results. The optimized combination of the matching of different speeds is also proposed as a useful reference for applications in industry, obtained by a response surface model and genetic algorithm with a balance between the growth rate and the growth uniformity. This method can save time, and the optimization can obtain the most uniform and highest thin film quality.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Design, fabrication and skin-electrode contact analysis of polymer microneedle-based ECG electrodes

NASA Astrophysics Data System (ADS)

O'Mahony, Conor; Grygoryev, Konstantin; Ciarlone, Antonio; Giannoni, Giuseppe; Kenthao, Anan; Galvin, Paul

2016-08-01

Microneedle-based ‘dry’ electrodes have immense potential for use in diagnostic procedures such as electrocardiography (ECG) analysis, as they eliminate several of the drawbacks associated with the conventional ‘wet’ electrodes currently used for physiological signal recording. To be commercially successful in such a competitive market, it is essential that dry electrodes are manufacturable in high volumes and at low cost. In addition, the topographical nature of these emerging devices means that electrode performance is likely to be highly dependent on the quality of the skin-electrode contact. This paper presents a low-cost, wafer-level micromoulding technology for the fabrication of polymeric ECG electrodes that use microneedle structures to make a direct electrical contact to the body. The double-sided moulding process can be used to eliminate post-process via creation and wafer dicing steps. In addition, measurement techniques have been developed to characterize the skin-electrode contact force. We perform the first analysis of signal-to-noise ratio dependency on contact force, and show that although microneedle-based electrodes can outperform conventional gel electrodes, the quality of ECG recordings is significantly dependent on temporal and mechanical aspects of the skin-electrode interface.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Jet printing of convex and concave polymer micro-lenses.

PubMed

Blattmann, M; Ocker, M; Zappe, H; Seifert, A

2015-09-21

We describe a novel approach for fabricating customized convex as well as concave micro-lenses using substrates with sophisticated pinning architecture and utilizing a drop-on-demand jet printer. The polymeric lens material deposited on the wafer is cured by UV light irradiation yielding lenses with high quality surfaces. Surface shape and roughness of the cured polymer lenses are characterized by white light interferometry. Their optical quality is demonstrated by imaging an USAF1951 test chart. The evaluated modulation transfer function is compared to Zemax simulations as a benchmark for the fabricated lenses.

Comprehensive investigation of HgCdTe metalorganic chemical vapor deposition

NASA Technical Reports Server (NTRS)

Raupp, Gregory B.

1993-01-01

The principal objective of this experimental and theoretical research program was to explore the possibility of depositing high quality epitaxial CdTe and HgCdTe at very low pressures through metalorganic chemical vapor deposition (MOCVD). We explored two important aspects of this potential process: (1) the interaction of molecular flow transport and deposition in an MOCVD reactor with a commercial configuration, and (2) the kinetics of metal alkyl source gas adsorption, decomposition and desorption from the growing film surface using ultra high vacuum surface science reaction techniques. To explore the transport-reaction issue, we have developed a reaction engineering analysis of a multiple wafer-in-tube ultrahigh vacuum chemical vapor deposition (UHV/CVD) reactor which allows an estimate of wafer or substrate throughput for a reactor of fixed geometry and a given deposition chemistry with specified film thickness uniformity constraints. The model employs a description of ballistic transport and reaction based on the pseudo-steady approximation to the Boltzmann equation in the limit of pure molecular flow. The model representation takes the form of an integral equation for the flux of each reactant or intermediate species to the wafer surfaces. Expressions for the reactive sticking coefficients (RSC) for each species must be incorporated in the term which represents reemission from a wafer surface. The interactions of MOCVD precursors with Si and CdTe were investigated using temperature programmed desorption (TPD) in ultra high vacuum combined with Auger electron spectroscopy (AES). These studies revealed that diethyltellurium (DETe) and dimethylcadmium (DMCd) adsorb weakly on clean Si(100) and desorb upon heating without decomposing. These precursors adsorb both weakly and strongly on CdTe(111)A, with DMCd exhibiting the stronger interaction with the surface than DETe.

Performance upgrades in the EUV engineering test stand

NASA Astrophysics Data System (ADS)

Tichenor, Daniel A.; Replogle, William C.; Lee, Sang Hun; Ballard, William P.; Leung, Alvin H.; Kubiak, Glenn D.; Klebanoff, Leonard E.; Graham, Samual, Jr.; Goldsmith, John E. M.; Jefferson, Karen L.; Wronosky, John B.; Smith, Tony G.; Johnson, Terry A.; Shields, Harry; Hale, Layton C.; Chapman, Henry N.; Taylor, John S.; Sweeney, Donald W.; Folta, James A.; Sommargren, Gary E.; Goldberg, Kenneth A.; Naulleau, Patrick P.; Attwood, David T., Jr.; Gullikson, Eric M.

2002-07-01

The EUV Engineering Test Stand (ETS) has demonstrated the printing of 100-nm-resolution scanned images. This milestone was first achieved while the ETS operated in an initial configuration using a low power laser and a developmental projection system, PO Box 1. The drive laser has ben upgraded to a single chain of the three-chain Nd:YAG laser developed by TRW. The result in exposure time is approximately 4 seconds for static exposures. One hundred nanometer dense features have been printed in step-and-scan operation with the same image quality obtained in static printing. These experiments are the first steps toward achieving operation using all three laser chains for a total drive laser power of 1500 watts. In a second major upgrade the developmental wafer stage platen, used to demonstrate initial full-field imaging, has been replaced with the final low-expansion platen made of Zerodur. Additional improvements in the hardware and control software have demonstrated combined x and jitter from 2 to 4 nm RMS Over most of the wafer stage travel range, while scanning at the design scan speed of 10 mm/s at the wafer. This value, less than half of the originally specified jitter, provides sufficient stability to support printing of 70 nm features as planned, when the upgraded projection system is installed. The third major upgrade will replace PO Box 1 with an improved projection system, PO Box 2, having lower figure error and lower flare. In addition to these upgrades, dose sensors at the reticle and wafer planes and an EUV- sensitive aerial image monitor have been integrated into the ETS. This paper reports on ETS system upgrades and the impact on system performance.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Methane production using resin-wafer electrodeionization

DOEpatents

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Misfit strain of oxygen precipitates in Czochralski silicon studied with energy-dispersive X-ray diffraction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gröschel, A., E-mail: alexander.groeschel@fau.de; Will, J.; Bergmann, C.

Annealed Czochralski Silicon wafers containing SiO{sub x} precipitates have been studied by high energy X-ray diffraction in a defocused Laue setup using a laboratory tungsten tube. The energy dispersive evaluation of the diffracted Bragg intensity of the 220 reflection within the framework of the statistical dynamical theory yields the static Debye-Waller factor E of the crystal, which gives access to the strain induced by the SiO{sub x} precipitates. The results are correlated with precipitate densities and sizes determined from transmission electron microscopy measurements of equivalent wafers. This allows for the determination of the constrained linear misfit ε between precipitate andmore » crystal lattice. For samples with octahedral precipitates the values ranging from ε = 0.39 (+0.28/−0.12) to ε = 0.48 (+0.34/−0.16) indicate that self-interstitials emitted into the matrix during precipitate growth contribute to the lattice strain. In this case, the expected value calculated from literature values is ε = 0.26 ± 0.05. Further, the precise evaluation of Pendellösung oscillations in the diffracted Bragg intensity of as-grown wafers reveals a thermal Debye-Waller parameter for the 220 reflection B{sup 220}(293 K) of 0.5582 ± 0.0039 Å{sup 2} for a structure factor based on spherically symmetric scattering contributions.« less

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE PAGES

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff; ...

2015-08-20

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

PubMed

Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

2016-05-11

Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials.

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Superconducting micro-resonator arrays with ideal frequency spacing

NASA Astrophysics Data System (ADS)

Liu, X.; Guo, W.; Wang, Y.; Dai, M.; Wei, L. F.; Dober, B.; McKenney, C. M.; Hilton, G. C.; Hubmayr, J.; Austermann, J. E.; Ullom, J. N.; Gao, J.; Vissers, M. R.

2017-12-01

We present a wafer trimming technique for producing superconducting micro-resonator arrays with highly uniform frequency spacing. With the light-emitting diode mapper technique demonstrated previously, we first map the measured resonance frequencies to the physical resonators. Then, we fine-tune each resonator's frequency by lithographically trimming a small length, calculated from the deviation of the measured frequency from its design value, from the interdigitated capacitor. We demonstrate this technique on a 127-resonator array made from titanium-nitride and show that the uniformity of frequency spacing is greatly improved. The array yield in terms of frequency collisions improves from 84% to 97%, while the quality factors and noise properties are unaffected. The wafer trimming technique provides an easy-to-implement tool to improve the yield and multiplexing density of large resonator arrays, which is important for various applications in photon detection and quantum computing.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

PubMed

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-09-21

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

PubMed Central

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-01-01

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

NASA Astrophysics Data System (ADS)

Szabó, Zoltán; Baji, Zsófia; Basa, Péter; Czigány, Zsolt; Bársony, István; Wang, Hsin-Ying; Volk, János

2016-08-01

Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4" wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a "buffer layer" deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

Flip chip bumping technology—Status and update

NASA Astrophysics Data System (ADS)

Juergen Wolf, M.; Engelmann, Gunter; Dietrich, Lothar; Reichl, Herbert

2006-09-01

Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Lead-free solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni-Cu which is especially designed for small-sized lead-free solder bumps will be discussed.

Eddy Current Testing for Detecting Small Defects in Thin Films

NASA Astrophysics Data System (ADS)

Obeid, Simon; Tranjan, Farid M.; Dogaru, Teodor

2007-03-01

Presented here is a technique of using Eddy Current based Giant Magneto-Resistance sensor (GMR) to detect surface and sub-layered minute defects in thin films. For surface crack detection, a measurement was performed on a copper metallization of 5-10 microns thick. It was done by scanning the GMR sensor on the surface of the wafer that had two scratches of 0.2 mm, and 2.5 mm in length respectively. In another experiment, metal coatings were deposited over the layers containing five defects with known lengths such that the defects were invisible from the surface. The limit of detection (resolution), in terms of defect size, of the GMR high-resolution Eddy Current probe was studied using this sample. Applications of Eddy Current testing include detecting defects in thin film metallic layers, and quality control of metallization layers on silicon wafers for integrated circuits manufacturing.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Dynamic Chemically Driven Dewetting, Spreading, and Self-Running of Sessile Droplets on Crystalline Silicon.

PubMed

Arscott, Steve

2016-12-06

A chemically driven dewetting effect is demonstrated using sessile droplets of dilute hydrofluoric acid on chemically oxidized silicon wafers. The dewetting occurs as the thin oxide is slowly etched by the droplet and replaced by a hydrogen-terminated surface; the result of this is a gradual increase in the contact angle of the droplet with time. The time-varying work of adhesion is calculated from the time-varying contact angle; this corresponds to the changing chemical nature of the surface during dewetting and can be modeled by the well-known logistic (sigmoid) function often used for the modeling of restricted growth, in this case, the transition from an oxidized surface to a hydrogen-terminated silicon surface. The observation of the time-varying contact angle allows one to both measure the etch rate of the silicon oxide and estimate the hydrogenation rate as a function of HF concentration and wafer type. In addition to this, at a certain HF concentration, a self-running droplet effect is observed. In contrast, on hydrogen-terminated silicon wafers, a chemically induced spreading effect is observed using sessile droplets of nitric acid. The droplet spreading can also be modeled using a logistical function, where the restricted growth is the transition from hydrogen-terminated to a chemically induced oxidized silicon surface. The chemically driven dewetting and spreading observed here add to the methods available to study dynamic wetting (e.g., the moving three-phase contact line) of sessile droplets on surfaces. By slowing down chemical kinetics of the wetting, one is able to record the changing profile of the sessile droplet with time and gather information concerning the time-varying surface chemistry. The data also indicates a chemical interface hysteresis (CIH) that is compared to contact angle hysteresis (CAH). The approach can also be used to study the chemical etching and deposition behavior of thin films using liquids by monitoring the macroscopic droplet profile and relating this to the time-varying physical and chemical interface phenomena.

A hybrid solution using computational prediction and measured data to accurately determine process corrections with reduced overlay sampling

NASA Astrophysics Data System (ADS)

Noyes, Ben F.; Mokaberi, Babak; Mandoy, Ram; Pate, Alex; Huijgen, Ralph; McBurney, Mike; Chen, Owen

2017-03-01

Reducing overlay error via an accurate APC feedback system is one of the main challenges in high volume production of the current and future nodes in the semiconductor industry. The overlay feedback system directly affects the number of dies meeting overlay specification and the number of layers requiring dedicated exposure tools through the fabrication flow. Increasing the former number and reducing the latter number is beneficial for the overall efficiency and yield of the fabrication process. An overlay feedback system requires accurate determination of the overlay error, or fingerprint, on exposed wafers in order to determine corrections to be automatically and dynamically applied to the exposure of future wafers. Since current and future nodes require correction per exposure (CPE), the resolution of the overlay fingerprint must be high enough to accommodate CPE in the overlay feedback system, or overlay control module (OCM). Determining a high resolution fingerprint from measured data requires extremely dense overlay sampling that takes a significant amount of measurement time. For static corrections this is acceptable, but in an automated dynamic correction system this method creates extreme bottlenecks for the throughput of said system as new lots have to wait until the previous lot is measured. One solution is using a less dense overlay sampling scheme and employing computationally up-sampled data to a dense fingerprint. That method uses a global fingerprint model over the entire wafer; measured localized overlay errors are therefore not always represented in its up-sampled output. This paper will discuss a hybrid system shown in Fig. 1 that combines a computationally up-sampled fingerprint with the measured data to more accurately capture the actual fingerprint, including local overlay errors. Such a hybrid system is shown to result in reduced modelled residuals while determining the fingerprint, and better on-product overlay performance.

Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

PubMed

Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

2008-05-01

An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air exchange rate is 5-10 ACH.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Fabless company mask technology approach: fabless but not fab-careless

NASA Astrophysics Data System (ADS)

Hisamura, Toshiyuki; Wu, Xin

2009-10-01

There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both technology development and benefited from corporations. Our involvement in manufacturing is driven by the following three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity has to be monitored. Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time (TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask manufacturing has contributed significantly to our success in past many nodes and will continue.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Radiation-Hardened Wafer Scale Integration

DTIC Science & Technology

1989-10-25

unlimited. LEXINGTON MASSACHUSETTS EXECUTIVE SUMMARY A focal plane processor (FPP) for a large array of LWIR photodetectors on a space platform must...It seems certain that large. scanning LWIR arrays will once again be of interest in the future, though their specifications will differ from those... nonuniformity and defects in the ZMR material, but films of good quality produced by this technique are now available commercially from Kopin Corporation. Such

INTERNATIONAL CONFERENCE ON SEMICONDUCTOR INJECTION LASERS SELCO-87: Dependence of the photoluminescence density on surface preparation and properties of n-type InP

NASA Astrophysics Data System (ADS)

Knauer, A.; Gramlich, S.; Staske, R.

1988-11-01

Comprehensive studies were made of the relationship between the photoluminescence intensity and the effective carrier lifetime, on the one hand, and the quality of the surface treatment of wafers (damage, oxide layer thickness) and the initial properties of a material (surface and bulk defects, inhomogeneity of the dopant concentration), on the other.

Wafer-scale Thermodynamically Stable GaN Nanorods via Two-Step Self-Limiting Epitaxy for Optoelectronic Applications

NASA Astrophysics Data System (ADS)

Kum, Hyun; Seong, Han-Kyu; Lim, Wantae; Chun, Daemyung; Kim, Young-Il; Park, Youngsoo; Yoo, Geonwook

2017-01-01

We present a method of epitaxially growing thermodynamically stable gallium nitride (GaN) nanorods via metal-organic chemical vapor deposition (MOCVD) by invoking a two-step self-limited growth (TSSLG) mechanism. This allows for growth of nanorods with excellent geometrical uniformity with no visible extended defects over a 100 mm sapphire (Al2O3) wafer. An ex-situ study of the growth morphology as a function of growth time for the two self-limiting steps elucidate the growth dynamics, which show that formation of an Ehrlich-Schwoebel barrier and preferential growth in the c-plane direction governs the growth process. This process allows monolithic formation of dimensionally uniform nanowires on templates with varying filling matrix patterns for a variety of novel electronic and optoelectronic applications. A color tunable phosphor-free white light LED with a coaxial architecture is fabricated as a demonstration of the applicability of these nanorods grown by TSSLG.

Liquid crystal uncooled thermal imager development

NASA Astrophysics Data System (ADS)

Clark, H. R.; Bozler, C. O.; Berry, S. R.; Reich, R. K.; Bos, P. J.; Finnemeyer, V. A.; Bryant, D. R.; McGinty, C.

2016-09-01

An uncooled thermal imager is being developed based on a liquid crystal (LC) transducer. Without any electrical connections, the LC transducer pixels change the long-wavelength infrared (LWIR) scene directly into a visible image as opposed to an electric signal in microbolometers. The objectives are to develop an imager technology scalable to large formats (tens of megapixels) while maintaining or improving the noise equivalent temperature difference (NETD) compared to microbolometers. The present work is demonstrating that the LCs have the required performance (sensitivity, dynamic range, speed, etc.) to enable a more flexible uncooled imager. Utilizing 200-mm wafers, a process has been developed and arrays have been fabricated using aligned LCs confined in 20×20-μm cavities elevated on thermal legs. Detectors have been successfully fabricated on both silicon and fused silica wafers using less than 10 photolithographic mask steps. A breadboard camera system has been assembled to test the imagers. Various sensor configurations are described along with advantages and disadvantages of component arrangements.

Effects of a chirped bias voltage on ion energy distributions in inductively coupled plasma reactors

NASA Astrophysics Data System (ADS)

Lanham, Steven J.; Kushner, Mark J.

2017-08-01

The metrics for controlling reactive fluxes to wafers for microelectronics processing are becoming more stringent as feature sizes continue to shrink. Recent strategies for controlling ion energy distributions to the wafer involve using several different frequencies and/or pulsed powers. Although effective, these strategies are often costly or present challenges in impedance matching. With the advent of matching schemes for wide band amplifiers, other strategies to customize ion energy distributions become available. In this paper, we discuss results from a computational investigation of biasing substrates using chirped frequencies in high density, electronegative inductively coupled plasmas. Depending on the frequency range and chirp duration, the resulting ion energy distributions exhibit components sampled from the entire frequency range. However, the chirping process also produces transient shifts in the self-generated dc bias due to the reapportionment of displacement and conduction with frequency to balance the current in the system. The dynamics of the dc bias can also be leveraged towards customizing ion energy distributions.

Guided growth of horizontal GaN nanowires on quartz and their transfer to other substrates.

PubMed

Goren-Ruck, Lior; Tsivion, David; Schvartzman, Mark; Popovitz-Biro, Ronit; Joselevich, Ernesto

2014-03-25

The guided growth of horizontal nanowires has so far been demonstrated on a limited number of substrates. In most cases, the nanowires are covalently bonded to the substrate where they grow and cannot be transferred to other substrates. Here we demonstrate the guided growth of well-aligned horizontal GaN nanowires on quartz and their subsequent transfer to silicon wafers by selective etching of the quartz while maintaining their alignment. The guided growth was observed on different planes of quartz with varying degrees of alignment. We characterized the crystallographic orientations of the nanowires and proposed a new mechanism of "dynamic graphoepitaxy" for their guided growth on quartz. The transfer of the guided nanowires enabled the fabrication of back-gated field-effect transistors from aligned nanowire arrays on oxidized silicon wafers and the production of crossbar arrays. The guided growth of transferrable nanowires opens up the possibility of massively parallel integration of nanowires into functional systems on virtually any desired substrate.

An Evaluation of High Temperature Airframe Seals for Advanced Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

DeMange, Jeffrey J.; Dunlap, Patrick H.; Steinetz, Bruce M.; Drlik, Gary J.

2007-01-01

High temperature seals are required for advanced hypersonic airframe applications. In this study, both spring tube thermal barriers and innovative wafer seal systems were evaluated under relevant hypersonic test conditions (temperatures, pressures, etc.) via high temperature compression testing and room temperature flow assessments. Thermal barriers composed of a Rene 41 spring tube filled with Saffil insulation and overbraided with a Nextel 312 sheath showed acceptable performance at 1500 F in both short term and longer term compression testing. Nextel 440 thermal barriers with Rene 41 spring tubes and Saffil insulation demonstrated good compression performance up to 1750 F. A silicon nitride wafer seal/compression spring system displayed excellent load performance at temperatures as high as 2200 F and exhibited room temperature leakage values that were only 1/3 those for the spring tube rope seals. For all seal candidates evaluated, no significant degradation in leakage resistance was noted after high temperature compression testing. In addition to these tests, a superalloy seal suitable for dynamic seal applications was optimized through finite element techniques.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

PubMed

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

NASA Astrophysics Data System (ADS)

Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

2018-03-01

We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

PubMed Central

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

A top-down approach to fabrication of high quality vertical heterostructure nanowire arrays.

PubMed

Wang, Hua; Sun, Minghua; Ding, Kang; Hill, Martin T; Ning, Cun-Zheng

2011-04-13

We demonstrate a novel top-down approach for fabricating nanowires with unprecedented complexity and optical quality by taking advantage of a nanoscale self-masking effect. We realized vertical arrays of nanowires of 20-40 nm in diameter with 16 segments of complex longitudinal InGaAsP/InP structures. The unprecedented high quality of etched wires is evidenced by the narrowest photoluminescence linewidth ever produced in similar wavelengths, indistinguishable from that of the corresponding wafer. This top-down, mask-free, large scale approach is compatible with the established device fabrication processes and could serve as an important alternative to the bottom-up approach, significantly expanding ranges and varieties of applications of nanowire technology.

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

PubMed Central

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-01-01

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response.

PubMed

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-09-21

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

Using an extractive Fourier transform infrared spectrometer for improving cleanroom air quality in a semiconductor manufacturing plant.

PubMed

Li, Shou-Nan; Chang, Chin-Ta; Shih, Hui-Ya; Tang, Andy; Li, Alen; Chen, Yin-Yung

2003-01-01

A mobile extractive Fourier transform infrared (FTIR) spectrometer was successfully used to locate, identify, and quantify the "odor" sources inside the cleanroom of a semiconductor manufacturing plant. It was found that ozone (O(3)) gas with a peak concentration of 120 ppm was unexpectedly releasing from a headspace of a drain for transporting used ozonized water and that silicon tetrafluoride (SiF(4)) with a peak concentration of 3 ppm was off-gassed from silicon wafers after dry-etching processing. When the sources of the odors was pinpointed by the FTIR, engineering control measures were applied. For O(3) control, a water-sealed pipeline was added to prevent the O(3) gas (emitting from the ozonized water) from entering the mixing unit. A ventilation system also was applied to the mixing unit in case of O(3) release. For SiF(4) mitigation, before the wafer-out chamber was opened, N(2) gas with a flow rate of 150 L/min was used for 100 sec to purge the wafer-out chamber, and a vacuum system was simultaneously activated to pump away the purging N(2). The effectiveness of the control measures was assured by using the FTIR. In addition, the FTIR was used to monitor the potential hazardous gas emissions during preventative maintenance of the semiconductor manufacturing equipment.

Ileostomy - changing your pouch

MedlinePlus

... it right away. If you have a pouch system made of 2 pieces (a pouch and a wafer) you ... pouch and barrier or wafer (wafers are part of a 2-piece pouch system). Use a stoma guide with different sizes and ...

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, D.C.; Fox, R.J.

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semi-conductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, Dimitrios C.; Fox, Richard J.

1981-01-01

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semiconductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

NASA Astrophysics Data System (ADS)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

The silane depletion fraction as an indicator for the amorphous/crystalline silicon interface passivation quality

NASA Astrophysics Data System (ADS)

Descoeudres, A.; Barraud, L.; Bartlome, R.; Choong, G.; De Wolf, Stefaan; Zicarelli, F.; Ballif, C.

2010-11-01

In silicon heterojunction solar cells, thin amorphous silicon layers passivate the crystalline silicon wafer surfaces. By using in situ diagnostics during plasma-enhanced chemical vapor deposition (PECVD), the authors report how the passivation quality of such layers directly relate to the plasma conditions. Good interface passivation is obtained from highly depleted silane plasmas. Based upon this finding, layers deposited in a large-area very high frequency (40.68 MHz) PECVD reactor were optimized for heterojunction solar cells, yielding aperture efficiencies up to 20.3% on 4 cm2 cells.

ROI on yield data analysis systems through a business process management strategy

NASA Astrophysics Data System (ADS)

Rehani, Manu; Strader, Nathan; Hanson, Jeff

2005-05-01

The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Detection and characterization of microdefects and microprecipitates in Si wafers by Brewster angle illumination using an optical fiber system

NASA Astrophysics Data System (ADS)

Taijing, Lu; Toyoda, Koichi; Nango, Nobuhito; Ogawa, Tomoya

1991-10-01

Microdefects and microprecipitates were non-destructively detected in bulk and near surface of a Si wafer by Brewster angle illumination using an optical fiber system, because the p-component of the illumination enters completely into the wafer and then makes scattering from the defects while the other s-component reflects on the wafer surface so as to deviate from an objective lens for the detection of the scattering. Some results of observations and discussions will be done here about the scatterers in epitaxially grown Si layers, denuded zones of Si wafers, annealed amorphous SiC films, SIMOX specimens and slip bands in Si crystals.

Residual Stress and Fracture of PECVD Thick Oxide Films for Power MEMS Structures and Devices

DTIC Science & Technology

2007-06-01

Residual stress leads to large overall wafer bow, which makes further processing difficult. For example some microfabrication machines , such as chemical...curvature will be measured across the wafer surface in 12 scans, rotating 24 the wafer by 300 between each scan. In situ wafer curvature will be...SiOx. 4.1. Introduction As introduced earlier (Sec.1), in Power MEMS (micro energy- harvesting devices such as micro heat engines and related components

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Precision of a CAD/CAM-engineered surgical template based on a facebow for orthognathic surgery: an experiment with a rapid prototyping maxillary model.

PubMed

Lee, Jae-Won; Lim, Se-Ho; Kim, Moon-Key; Kang, Sang-Hoon

2015-12-01

We examined the precision of a computer-aided design/computer-aided manufacturing-engineered, manufactured, facebow-based surgical guide template (facebow wafer) by comparing it with a bite splint-type orthognathic computer-aided design/computer-aided manufacturing-engineered surgical guide template (bite wafer). We used 24 rapid prototyping (RP) models of the craniofacial skeleton with maxillary deformities. Twelve RP models each were used for the facebow wafer group and the bite wafer group (experimental group). Experimental maxillary orthognathic surgery was performed on the RP models of both groups. Errors were evaluated through comparisons with surgical simulations. We measured the minimum distances from 3 planes of reference to determine the vertical, lateral, and anteroposterior errors at specific measurement points. The measured errors were compared between experimental groups using a t test. There were significant intergroup differences in the lateral error when we compared the absolute values of the 3-D linear distance, as well as vertical, lateral, and anteroposterior errors between experimental groups. The bite wafer method exhibited little lateral error overall and little error in the anterior tooth region. The facebow wafer method exhibited very little vertical error in the posterior molar region. The clinical precision of the facebow wafer method did not significantly exceed that of the bite wafer method. Copyright © 2015 Elsevier Inc. All rights reserved.

Microfluidics for Synthetic Biology: From Design to Execution

PubMed Central

Ferry, M. S.; Razinkov, I. A.; Hasty, J.

2016-01-01

With the expanding interest in cellular responses to dynamic environments, microfluidic devices have become important experimental platforms for biological research. Microfluidic “microchemostat” devices enable precise environmental control while capturing high quality, single-cell gene expression data. For studies of population heterogeneity and gene expression noise, these abilities are crucial. Here, we describe the necessary steps for experimental microfluidics using devices created in our lab as examples. First, we discuss the rational design of microchemostats and the tools available to predict their performance. We carefully analyze the critical parts of an example device, focusing on the most important part of any microchemostat: the cell trap. Next, we present a method for generating on-chip dynamic environments using an integrated fluidic junction coupled to linear actuators. Our system relies on the simple modulation of hydrostatic pressure to alter the mixing ratio between two source reservoirs and we detail the software and hardware behind it. To expand the throughput of microchemostat experiments, we describe how to build larger, parallel versions of simpler devices. To analyze the large amounts of data, we discuss methods for automated cell tracking, focusing on the special problems presented by Saccharomyces cerevisiae cells. The manufacturing of microchemostats is described in complete detail: from the photolithographic processing of the wafer to the final bonding of the PDMS chip to glass coverslip. Finally, the procedures for conducting Escherichia coli and S. cerevisiae microchemostat experiments are addressed. PMID:21601093

Spin coating apparatus

DOEpatents

Torczynski, John R.

2000-01-01

A spin coating apparatus requires less cleanroom air flow than prior spin coating apparatus to minimize cleanroom contamination. A shaped exhaust duct from the spin coater maintains process quality while requiring reduced cleanroom air flow. The exhaust duct can decrease in cross section as it extends from the wafer, minimizing eddy formation. The exhaust duct can conform to entrainment streamlines to minimize eddy formation and reduce interprocess contamination at minimal cleanroom air flow rates.

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

NASA Astrophysics Data System (ADS)

Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

2018-05-01

Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

Dynamic Curvature and Stress Studies for MBE CdTe on Si and GaAs Substrates

NASA Astrophysics Data System (ADS)

Jacobs, R. N.; Jaime Vasquez, M.; Lennon, C. M.; Nozaki, C.; Almeida, L. A.; Pellegrino, J.; Arias, J.; Taylor, C.; Wissman, B.

2015-09-01

Infrared focal plane arrays (IRFPA) based on HgCdTe semiconductor alloys have been shown to be ideal for tactical and strategic applications. High density (>1 M pixel), high operability HgCdTe detectors on large area, low-cost composite substrates, such as CdTe-buffered Si or GaAs, are envisioned for next-generation IRFPAs. Thermal expansion mismatch is among various material parameters that govern the structural properties of the final detector layer. It has previously been shown that thermal expansion mismatch plays the dominant role in the residual stress characteristics of these heteroepitaxial structures (Jacobs et al. in J Electron Mater 37:1480, 2008). The wafer curvature (bowing) resulting from residual stress, is a likely source of problems that may occur during subsequent processing. This includes cracking of the film and substrate during post-growth annealing processes or even certain characterization techniques. In this work, we examine dynamic curvature and stress during molecular beam epitaxy (MBE), of CdTe on Si and GaAs substrates. The effect of temperature changes on wafer curvature throughout the growth sequence is documented using a multi-beam optical sensor developed by K-Space Associates. This monitoring technique makes possible the study of growth sequences which employ annealing schemes and/or interlayers to influence the final residual stress state of the heteroepitaxial structures.

Static/dynamic trade-off performance of PZT thick film micro-actuators

NASA Astrophysics Data System (ADS)

Bienaimé, Alex; Chalvet, Vincent; Clévy, Cédric; Gauthier-Manuel, Ludovic; Baron, Thomas; Rakotondrabe, Micky

2015-07-01

Piezoelectric actuators are widespread in the design of micro/nanorobotic tools and microsystems. Studies toward the integration of such actuators in complex micromechatronic systems require the size reduction of these actuators while retaining a wide range of performance. Two main fabrication processes are currently used for the fabrication of piezoelectric actuators, providing very different behaviors: (i) the use of a bulk lead zirconate titanate (PZT) layer and (ii) the use of thin film growth. In this paper, we propose a trade-off between these two extreme processes and technologies in order to explore the performance of new actuators. This resulted in the design and fabrication of thick film PZT unimorph cantilevers. They allowed a high level of performance, both in the static (displacement) and dynamic (first resonance frequency) regimes, in addition to being small in size. Such cantilever sizes are obtained through the wafer scale bonding and thinning of a PZT plate onto a silicon on insulator wafer. The piezoelectric cantilevers have a 26 μm thick PZT layer with a 5 μm thick silicon layer, over a length of 4 mm and a width of 150 μm. Experimental characterization has shown that the static displacements obtained are in excess of 4.8 μm V-1 and the resonance frequencies are up to 1103 Hz, which are useful for large displacements and low voltage actuators.

In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

NASA Astrophysics Data System (ADS)

Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

2015-09-01

In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Characterization of plasma processing induced charging damage to MOS devices

NASA Astrophysics Data System (ADS)

Ma, Shawming

1997-12-01

Plasma processing has become an integral part of the fabrication of integrated circuits and takes at least 30% of whole process steps since it offers advantages in terms of directionality, low temperature and process convenience. However, wafer charging during plasma processes is a significant concern for both thin oxide damage and profile distortion. In this work, the factors affecting this damage will be explained by plasma issues, device structure and oxide quality. The SPORT (Stanford Plasma On-wafer Real Time) charging probe was developed to investigate the charging mechanism of different plasma processes including poly-Si etching, resist ashing and PECVD. The basic idea of this probe is that it simulates a real device structure in the plasma environment and allows measurement of plasma induced charging voltages and currents directly in real time. This measurement is fully compatible with other charging voltage measurement but it is the only one to do in real-time. Effect of magnetic field induced plasma nonuniformity on spatial dependent charging is well understood by this measurement. In addition, the plasma parameters including ion current density and electron temperature can also be extracted from the probe's plasma I-V characteristics using a dc Langmuir probe like theory. It will be shown that the MOS device tunneling current from charging, the dependence on antenna ratio and the etch uniformity can all be predicted by using this measurement. Moreover, the real-time measurement reveals transient and electrode edge effect during processing. Furthermore, high aspect ratio pattern induced electron shading effects can also be characterized by the probe. On the oxide quality issue, wafer temperature during plasma processing has been experimentally shown to be critical to charging damage. Finally, different MOS capacitor testing methods including breakdown voltage, charge-to-breakdown, gate leakage current and voltage-time at constant current bias were compared to find the optimum method for charging device reliability testing.

The opportunity and challenge of spin coat based nanoimprint lithography

NASA Astrophysics Data System (ADS)

Jung, Wooyung; Cho, Jungbin; Choi, Eunhyuk; Lim, Yonghyun; Bok, Cheolkyu; Tsuji, Masatoshi; Kobayashi, Kei; Kono, Takuya; Nakasugi, Tetsuro

2017-03-01

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Applications of β-limit dextrin as a matrix forming excipient for fast disintegrating buccal dosage formats.

PubMed

Qi, Xin; Tester, Richard; Liu, Yu; Mullin, Margaret

2012-01-01

To compare the properties of buccal delivery matrices (wafers) made with dextrin, β-limit dextrin and pre-gelatinised starch. The constituent α-glucans were tested for their mucoadhesive properties in solution plus their content of crystalline material (differential scanning calorimetry, DSC). Wafers were made by lyophilisation of aqueous solutions/dispersions of the α-glucans. Physical properties of the wafers were evaluated using texture analysis, dissolution coupled to photography and scanning electron microscopy (SEM). The results highlighted how the β-limit dextrins chemical and physical properties were ideally suited for the production of buccal delivery wafers. Dissolution testing confirmed the excellent hydration profile of the β-limit dextrin (within wafers) with time. Using SEM it was evident that the homogeneous "bee-hive" like structure of the β-limit dextrin wafers, unlike the other α-glucans, provided a rapidly hydratable strong porous matrix. The β-limit dextrin α-glucan makes a superb (lyophilised) mucoadhesive delivery structure for the delivery of active agents to the buccal mucosa.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2002-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2000-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

CD and defect improvement challenges for immersion processes

NASA Astrophysics Data System (ADS)

Ehara, Keisuke; Ema, Tatsuhiko; Yamasaki, Toshinari; Nakagawa, Seiji; Ishitani, Seiji; Morita, Akihiko; Kim, Jeonghun; Kanaoka, Masashi; Yasuda, Shuichi; Asai, Masaya

2009-03-01

The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

High-density plasma deposition manufacturing productivity improvement

NASA Astrophysics Data System (ADS)

Olmer, Leonard J.; Hudson, Chris P.

1999-09-01

High Density Plasma (HDP) deposition provides a means to deposit high quality dielectrics meeting submicron gap fill requirements. But, compared to traditional PECVD processing, HDP is relatively expensive due to the higher capital cost of the equipment. In order to keep processing costs low, it became necessary to maximize the wafer throughput of HDP processing without degrading the film properties. The approach taken was to optimize the post deposition microwave in-situ clean efficiency. A regression model, based on actual data, indicated that number of wafers processed before a chamber clean was the dominant factor. Furthermore, a design change in the ceramic hardware, surrounding the electrostatic chuck, provided thermal isolation resulting in an enhanced clean rate of the chamber process kit. An infra-red detector located in the chamber exhaust line provided a means to endpoint the clean and in-film particle data confirmed the infra-red results. The combination of increased chamber clean frequency, optimized clean time and improved process.

Mask automation: need a revolution in mask makers and equipment industry

NASA Astrophysics Data System (ADS)

Moon, Seong-yong; Yu, Sang-yong; Noh, Young-hwa; Son, Ki-jung; Lee, Hyun-Joo; Cho, Han-Ku

2013-09-01

As improving device integration for the next generation, high performance and cost down are also required accordingly in semiconductor business. Recently, significant efforts have been given on putting EUV technology into fabrication in order to improve device integration. At the same time, 450mm wafer manufacturing environment has been considered seriously in many ways in order to boost up the productivity. Accordingly, 9-inch mask has been discussed in mask fabrication business recently to support 450mm wafer manufacturing environment successfully. Although introducing 9-inch mask can be crucial for mask industry, multi-beam technology is also expected as another influential turning point to overcome currently the most critical issue in mask industry, electron beam writing time. No matter whether 9-inch mask or multi-beam technology will be employed or not, mask quality and productivity will be the key factors to survive from the device competition. In this paper, the level of facility automation in mask industry is diagnosed and analyzed and the automation guideline is suggested for the next generation.

Improvement of minority carrier life time in N-type monocrystalline Si by the Czochralski method

NASA Astrophysics Data System (ADS)

Baik, Sungsun; Pang, Ilsun; Kim, Jaemin; Kim, Kwanghun

2016-07-01

The installation amount of solar power plants increases every year. Multi-crystalline Si solar cells comprise a large share of the market of solar power plants. Multi-crystalline and single-crystalline Si solar cells are competing against one another in the market. Many single-crystalline companies are trying to develop and produce n-type solar cells with higher cell efficiency than that of p-type. In n-type wafers with high cell efficiency, wafer quality has become increasingly important. In order to make ingots with higher MCLT, the effects of both poly types related to metal impurities and pull speeds related to vacancy concentration on minority carrier life time were studied. In the final part of ingots, poly types related to the metal impurities are a dominant factor on MCLT. In the initial part of ingots, pull speeds related to vacancy concentration are a dominant factor on MCLT. [Figure not available: see fulltext.

Wafer-scale Fabrication of Non-Polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification.

PubMed

Zhu, Tongtong; Liu, Yingjun; Ding, Tao; Fu, Wai Yuen; Jarman, John; Ren, Christopher Xiang; Kumar, R Vasant; Oliver, Rachel A

2017-03-27

Distributed Bragg reflectors (DBRs) are essential components for the development of optoelectronic devices. For many device applications, it is highly desirable to achieve not only high reflectivity and low absorption, but also good conductivity to allow effective electrical injection of charges. Here, we demonstrate the wafer-scale fabrication of highly reflective and conductive non-polar gallium nitride (GaN) DBRs, consisting of perfectly lattice-matched non-polar (11-20) GaN and mesoporous GaN layers that are obtained by a facile one-step electrochemical etching method without any extra processing steps. The GaN/mesoporous GaN DBRs exhibit high peak reflectivities (>96%) across the entire visible spectrum and wide spectral stop-band widths (full-width at half-maximum >80 nm), while preserving the material quality and showing good electrical conductivity. Such mesoporous GaN DBRs thus provide a promising and scalable platform for high performance GaN-based optoelectronic, photonic, and quantum photonic devices.

Low-Temperature Wafer-Scale Deposition of Continuous 2D SnS2 Films.

PubMed

Mattinen, Miika; King, Peter J; Khriachtchev, Leonid; Meinander, Kristoffer; Gibbon, James T; Dhanak, Vin R; Räisänen, Jyrki; Ritala, Mikko; Leskelä, Markku

2018-04-19

Semiconducting 2D materials, such as SnS 2 , hold immense potential for many applications ranging from electronics to catalysis. However, deposition of few-layer SnS 2 films has remained a great challenge. Herein, continuous wafer-scale 2D SnS 2 films with accurately controlled thickness (2 to 10 monolayers) are realized by combining a new atomic layer deposition process with low-temperature (250 °C) postdeposition annealing. Uniform coating of large-area and 3D substrates is demonstrated owing to the unique self-limiting growth mechanism of atomic layer deposition. Detailed characterization confirms the 1T-type crystal structure and composition, smoothness, and continuity of the SnS 2 films. A two-stage deposition process is also introduced to improve the texture of the films. Successful deposition of continuous, high-quality SnS 2 films at low temperatures constitutes a crucial step toward various applications of 2D semiconductors. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

Heteroepitaxial growth of In{sub 0.30}Ga{sub 0.70}As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kohen, David, E-mail: david.kohen@asm.com; Nguyen, Xuan Sang; Made, Riko I

We report on the growth of an In{sub 0.30}Ga{sub 0.70}As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 10{sup 7} cm{sup −2} with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with I{sub DS} of 70more » μA/μm and g{sub m} of above 60 μS/μm, demonstrating the high quality of the grown materials.« less

Projection x-ray topography system at 1-BM x-ray optics test beamline at the advanced photon source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stoupin, Stanislav, E-mail: sstoupin@aps.anl.gov; Liu, Zunping; Trakhtenberg, Emil

2016-07-27

Projection X-ray topography of single crystals is a classic technique for the evaluation of intrinsic crystal quality of large crystals. In this technique a crystal sample and an area detector (e.g., X-ray film) collecting intensity of a chosen crystallographic reflection are translated simultaneously across an X-ray beam collimated in the diffraction scattering plane (e.g., [1, 2]). A bending magnet beamline of a third-generation synchrotron source delivering x-ray beam with a large horizontal divergence, and therefore, a large horizontal beam size at a crystal sample position offers an opportunity to obtain X-ray topographs of large crystalline samples (e.g., 6-inch wafers) inmore » just a few exposures. Here we report projection X-ray topography system implemented recently at 1-BM beamline of the Advanced Photon Source. A selected X-ray topograph of a 6-inch wafer of 4H-SiC illustrates capabilities and limitations of the technique.« less

Overlay of multiframe SEM images including nonlinear field distortions

NASA Astrophysics Data System (ADS)

Babin, S.; Borisov, S.; Ivonin, I.; Nakazawa, S.; Yamazaki, Y.

2018-03-01

To reduce charging and shrinkage, CD-SEMs utilize low electron energies and multiframe imaging. This results in every next frame being altered due to stage and beam instability, as well as due to charging. Regular averaging of the frames blurs the edges; this directly effects the extracted values of critical dimensions. A technique was developed to overlay multiframe images without the loss of quality. This method takes into account drift, rotation, and magnification corrections, as well as nonlinear distortions due to wafer charging. A significant improvement in the signal to noise ratio and overall image quality without degradation of the feature's edge quality was achieved. The developed software is capable of working with regular and large size images up to 32K pixels in each direction.

Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications.

PubMed

Chen, K N; Tsang, C K; Wu, W W; Lee, S H; Lu, J Q

2011-04-01

A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.

United States Air Force High School Apprenticeship Program. 1990 Program Management Report. Volume 3

DTIC Science & Technology

1991-04-18

User Guide Shelly Knupp 73 Computer-Aided Design (CAD) Area Christopher O’Dell 74 Electron Beam Lithography Suzette Yu 68 Flight Dynamics Laboratory 75...fabrication. I Mr. Ed Davis, for the background knowledge of device processes and I information on electron beam lithography . Captain Mike Cheney, for...researcher may write gates on to the wafer by a process called lithography . This is the most crucial and complex part of the process. Two types of proven

Array automated assembly, phase 2

NASA Technical Reports Server (NTRS)

Taylor, W. E.

1978-01-01

An analysis was made of cost tradeoffs for shaping modified square wafers from cylindrical crystals. Tests were conducted of the effectiveness of texture etching for removal of surface damage on sawed wafers. A single step texturing etch appeared adequate for removal of surface damage on wafers cut with multiple blade reciprocating slurry saws.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Wafer chamber having a gas curtain for extreme-UV lithography

DOEpatents

Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

2001-01-01

An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

Heterogeneously integrated microsystem-on-a-chip

DOEpatents

Chanchani, Rajen [Albuquerque, NM

2008-02-26

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Overlay improvements using a real time machine learning algorithm

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Kubis, Michael; Henke, Wolfgang; Slotboom, Daan; Hoogenboom, Tom; Mulkens, Jan; Coogans, Martyn; ten Berge, Peter; Verkleij, Dick; van de Mast, Frank

2014-04-01

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

PubMed

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization and qualification.

New methodology for dynamic lot dispatching

NASA Astrophysics Data System (ADS)

Tai, Wei-Herng; Wang, Jiann-Kwang; Lin, Kuo-Cheng; Hsu, Yi-Chin

1994-09-01

This paper presents a new dynamic dispatching rule to improve delivery. The dynamic dispatching rule named `SLACK and OTD (on time delivery)' is developed for focusing on due date and target cycle time under the environment of IC manufacturing. This idea uses traditional SLACK policy to control long term due date and new OTD policy to reflect the short term stage queue time. Through the fuzzy theory, these two policies are combined as the dispatching controller to define the lot priority in the entire production line. Besides, the system would automatically update the lot priority according to the current line situation. Since the wafer dispatching used to be controlled by critical ratio that indicates the low customer satisfaction. And the overall slack time in the front end of the process is greater compared to that in the rear end of the process which reveals that the machines in the rear end are overloaded by rush orders. When SLACK and OTD are used the due date control has been gradually improved. The wafer with either a long stage queue time or urgent due date will be pushed through the overall production line instead of jammed in the front end. A demand pull system is also developed to satisfy not only due date but also the quantity of monthly demand. The SLACK and OTD rule has been implemented in Taiwan Semiconductor Manufacturing Company for eight months with beneficial results. In order to clearly monitor the SLACK and OTD policy, a method called box chart is generated to simulate the entire production system. From the box chart, we can not only monitor the result of decision policy but display the production situation on the density figure. The production cycle time and delivery situation can also be investigated.

Enhanced methodology of focus control and monitoring on scanner tool

NASA Astrophysics Data System (ADS)

Chen, Yen-Jen; Kim, Young Ki; Hao, Xueli; Gomez, Juan-Manuel; Tian, Ye; Kamalizadeh, Ferhad; Hanson, Justin K.

2017-03-01

As the demand of the technology node shrinks from 14nm to 7nm, the reliability of tool monitoring techniques in advanced semiconductor fabs to achieve high yield and quality becomes more critical. Tool health monitoring methods involve periodic sampling of moderately processed test wafers to detect for particles, defects, and tool stability in order to ensure proper tool health. For lithography TWINSCAN scanner tools, the requirements for overlay stability and focus control are very strict. Current scanner tool health monitoring methods include running BaseLiner to ensure proper tool stability on a periodic basis. The focus measurement on YIELDSTAR by real-time or library-based reconstruction of critical dimensions (CD) and side wall angle (SWA) has been demonstrated as an accurate metrology input to the control loop. The high accuracy and repeatability of the YIELDSTAR focus measurement provides a common reference of scanner setup and user process. In order to further improve the metrology and matching performance, Diffraction Based Focus (DBF) metrology enabling accurate, fast, and non-destructive focus acquisition, has been successfully utilized for focus monitoring/control of TWINSCAN NXT immersion scanners. The optimal DBF target was determined to have minimized dose crosstalk, dynamic precision, set-get residual, and lens aberration sensitivity. By exploiting this new measurement target design, 80% improvement in tool-to-tool matching, >16% improvement in run-to-run mean focus stability, and >32% improvement in focus uniformity have been demonstrated compared to the previous BaseLiner methodology. Matching <2.4 nm across multiple NXT immersion scanners has been achieved with the new methodology of set baseline reference. This baseline technique, with either conventional BaseLiner low numerical aperture (NA=1.20) mode or advanced illumination high NA mode (NA=1.35), has also been evaluated to have consistent performance. This enhanced methodology of focus control and monitoring on multiple illumination conditions, opens an avenue to significantly reduce Focus-Exposure Matrix (FEM) wafer exposure for new product/layer best focus (BF) setup.

Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2016-03-01

Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low light scattering. Likewise, SEM cannot be used effectively for post-inspection defect review and classification of these very shallow types of defects. To verify and obtain accurate shape and three-dimensional information of those defects, automatic defect review AFM (ADR AFM) is utilized for accurate locating and imaging of DOI. In ADR AFM, non-contact mode imaging is used for non-destructive characterization and preserving tip sharpness for data repeatability and reproducibility. Locating DOI and imaging are performed automatically with a throughput of many defects per hour. Topography images of DOI has been collected and compared with SEM images. The ADR AFM has been shown as a non-destructive metrology tool for defect review and obtaining three-dimensional topography information.

Synthesis of ZnS films on Si(100) wafers by using chemical bath deposition assisted by the complexing agent ethylenediamine

NASA Astrophysics Data System (ADS)

Zhu, He-Jie; Wang, Xue-Mei; Gao, Xiao-Yong

2015-07-01

Low-cost synthesis of high-quality ZnS films on silicon wafers is of much importance to the ZnSbased heterojunction blue light-emitting device integrated with silicon. Thus, a series of ZnS films were chemically synthesized at low cost on Si(100) wafers at 353 K under a mixed acidic solution with a pH of 4 with zinc acetate and thioacetamide as precursors and with ethylenediamine and hydrochloric acid as the complexing agent and the pH value modifier, respectively. The effects of the ethylenediamine concentration on the crystallization, surface morphology, and optical properties of the ZnS films were investigated by using X-ray diffractometry, scanning electron microscopy, spectrophotometry, and fluorescence spectroscopy. A mechanism for the formation of ZnS film under an acidic condition was also proposed. All of the ZnS films were polycrystalline in nature, with a dominant cubic phase and a small amounts of hexagonal phases. The crystallization and the surface pattern of the films were clearly improved with increasing ethylenediamine concentration due to its enhanced complexing role. The absorption edge of the films almost underwent a blue shift with increasing ethylenediamine concentration, which was largely attributed to the quantum confinement effects caused by the small particle size of the polycrystalline ZnS films. Defect species and the corresponding strengths of the ZnS films were strongly affected by the ethylenediamine concentration.

The resonant body transistor.

PubMed

Weinstein, Dana; Bhave, Sunil A

2010-04-14

This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer.

New trends in space x-ray optics

NASA Astrophysics Data System (ADS)

Hudec, R.; Maršíková, V.; Pína, L.; Inneman, A.; Skulinová, M.

2017-11-01

The X-ray optics is a key element of various X-ray telescopes, X-ray microscopes, as well as other X-ray imaging instruments. The grazing incidence X-ray lenses represent the important class of X-ray optics. Most of grazing incidence (reflective) X-ray imaging systems used in astronomy but also in other (laboratory) applications are based on the Wolter 1 (or modified) arrangement. But there are also other designs and configurations proposed, used and considered for future applications both in space and in laboratory. The Kirkpatrick-Baez (K-B) lenses as well as various types of Lobster-Eye optics and MCP/Micropore optics serve as an example. Analogously to Wolter lenses, the X-rays are mostly reflected twice in these systems to create focal images. Various future projects in X-ray astronomy and astrophysics will require large segments with multiple thin shells or foils. The large Kirkpatrick-Baez modules, as well as the large Lobster-Eye X-ray telescope modules in Schmidt arrangement may serve as examples. All these space projects will require high quality and light segmented shells (bent or flat foils) with high X-ray reflectivity and excellent mechanical stability. The Multi Foil Optics (MFO) approach represent a promising alternative for both LE and K-B X-ray optical modules. Several types of reflecting substrates may be considered for these applications, with emphasis on thin float glass sheets and, more recently, high quality silicon wafers. This confirms the importance of non- Wolter X-ray optics designs for the future. Future large space X-ray telescopes (such as IXO) require precise and light-weight X-ray optics based on numerous thin reflecting shells. Novel approaches and advanced technologies are to be exploited and developed. In this contribution, we refer on results of tested X-ray mirror shells produced by glass thermal forming (GTF) and by shaping Si wafers. Both glass foils and Si wafers are commercially available, have excellent surface microroughness of a few 0.1 nm, and low weight (the volume density is 2.5 g cm-3 for glass and 2.3 g cm-3 for Si). Technologies are needed to be exploited; how to shape these substrates to achieve the required precise Xray optics geometries without degradations of the fine surface microroughness. Although glass and recently silicon wafers are considered to represent most promising materials for future advanced large aperture space Xray telescopes, there also exist other alternative materials worth further study such as amorphous metals and glassy carbon [1]. In order to achieve sub-arsec angular resolutions, principles of active optics have to be adopted.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

TaC-coated graphite prepared via a wet ceramic process: Application to CVD susceptors for epitaxial growth of wide-bandgap semiconductors

NASA Astrophysics Data System (ADS)

Nakamura, Daisuke; Kimura, Taishi; Narita, Tetsuo; Suzumura, Akitoshi; Kimoto, Tsunenobu; Nakashima, Kenji

2017-11-01

A novel sintered tantalum carbide coating (SinTaC) prepared via a wet ceramic process is proposed as an approach to reducing the production cost and improving the crystal quality of bulk-grown crystals and epitaxially grown films of wide-bandgap semiconductors. Here, we verify the applicability of the SinTaC components as susceptors for chemical vapor deposition (CVD)-SiC and metal-organic chemical vapor deposition (MOCVD)-GaN epitaxial growth in terms of impurity incorporation from the SinTaC layers and also clarify the surface-roughness controllability of SinTaC layers and its advantage in CVD applications. The residual impurity elements in the SinTaC layers were confirmed to not severely incorporate into the CVD-SiC and MOCVD-GaN epilayers grown using the SinTaC susceptors. The quality of the epilayers was also confirmed to be equivalent to that of epilayers grown using conventional susceptors. Furthermore, the surface roughness of the SinTaC components was controllable over a wide range of average roughness (0.4 ≤ Ra ≤ 5 μm) and maximum height roughness (3 ≤ Rz ≤ 36 μm) through simple additional surface treatment procedures, and the surface-roughened SinTaC susceptor fabricated using these procedures was predicted to effectively reduce thermal stress on epi-wafers. These results confirm that SinTaC susceptors are applicable to epitaxial growth processes and are advantageous over conventional susceptor materials for reducing the epi-cost and improving the quality of epi-wafers.

Method of Fabricating Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

NASA Technical Reports Server (NTRS)

Choi, Sang Hyouk (Inventor); Park, Yeonjoon (Inventor)

2017-01-01

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Wafer characteristics via reflectometry

DOEpatents

Sopori, Bhushan L.

2010-10-19

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

1984-01-01

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

Outcome of patients affected by newly diagnosed glioblastoma undergoing surgery assisted by 5-aminolevulinic acid guided resection followed by BCNU wafers implantation: a 3-year follow-up.

PubMed

Della Puppa, Alessandro; Lombardi, Giuseppe; Rossetto, Marta; Rustemi, Oriela; Berti, Franco; Cecchin, Diego; Gardiman, Marina Paola; Rolma, Giuseppe; Persano, Luca; Zagonel, Vittorina; Scienza, Renato

2017-01-01

The purpose of the study was to evaluate the clinical outcome of the association of BCNU wafers implantation and 5-aminolevulinic acid (5-ALA) fluorescence in the treatment of patients with newly diagnosed glioblastoma (ndGBM). Clinical and surgical data from patients who underwent 5-ALA surgery followed by BCNU wafers implantation were retrospectively evaluated (20 patients, Group I) and compared with data of patients undergoing surgery with BCNU wafers alone (42 patients, Group II) and 5-ALA alone (59 patients, Group III). Patients undergoing 5-ALA assisted resection followed by BCNU wafers implantation (Group I) resulted long survivors (>3 years) in 15 % of cases and showed a median PFS and MS of 11 and 22 months, respectively. Patients treated with BCNU wafers presented a significantly higher survival when tumor was removed with the assistance of 5-ALA (22 months with vs 18 months without 5-ALA, p < 0.0001); these data could be partially explained by the significantly higher CRET achieved in patients operated with 5-ALA assistance (80 % with vs 47 %% without 5-ALA). Moreover, patients of Group I showed a significant increased survival compared with Group III (5-ALA without BCNU) (22 months with vs 21 months without BCNU wafers, p = 0.0025) even with a comparable CRET (80 % vs 76 %, respectively). The occurrence of adverse events related to wafers did not significantly increase with 5-ALA (20 % with and 19 % without 5-ALA) and did not impact in survival outcome. In conclusion, our experience shows that on selected ndGBM patients 5-ALA technology and BCNU wafers implantation show a synergic action on patients' outcome without increasing adverse events occurrence.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Planning for the semiconductor manufacturer of the future

NASA Technical Reports Server (NTRS)

Fargher, Hugh E.; Smith, Richard A.

1992-01-01

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

NASA Astrophysics Data System (ADS)

Zhang, Runchun; Zhao, Beiji; Huang, Kai; You, Tiangui; Jia, Qi; Lin, Jiajie; Zhang, Shibin; Yan, Youquan; Yi, Ailun; Zhou, Min; Ou, Xin

2018-05-01

Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Measurement and thermal modeling of sapphire substrate temperature at III-Nitride MOVPE conditions

DOE PAGES

Creighton, J. Randall; Coltrin, Michael E.; Figiel, Jeffrey J.

2017-04-01

Here, growth rates and alloy composition of AlGaN grown by MOVPE is often very temperature dependent due to the presence of gas-phase parasitic chemical processes. These processes make wafer temperature measurement highly important, but in fact such measurements are very difficult because of substrate transparency in the near- IR (~900 nm) where conventional pyrometers detect radiation. The transparency problem can be solved by using a mid-IR pyrometer operating at a wavelength (~7500 nm) where sapphire is opaque. We employ a mid- IR pyrometer to measure the sapphire wafer temperature and simultaneously a near-IR pyrometer to measure wafer pocket temperature, whilemore » varying reactor pressure in both a N 2 and H 2 ambient. Near 1300 °C, as the reactor pressure is lowered from 300 Torr to 10 Torr the wafer temperature drops dramatically, and the ΔT between the pocket and wafer increases from ~20 °C to ~250 °C. Without the mid-IR pyrometer the large wafer temperature change with pressure would not have been noted. In order to explain this behavior we have developed a quasi-2D thermal model that includes a proper accounting of the pressure-dependent thermal contact resistance, and also accounts for sapphire optical transmission. The model and experimental results demonstrate that at most growth conditions the majority of the heat is transported from the wafer pocket to the wafer via gas conduction, in the free molecular flow limit. In this limit gas conductivity is independent of gap size but first order in pressure, and can quantitatively explain results from 20 to 300 Torr. Further analysis yields a measure of the thermal accommodation coefficients; α(H 2) =0.23, α(N 2) =0.50, which are in the range typically measured.« less

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

MiRNA-181d Expression Significantly Affects Treatment Responses to Carmustine Wafer Implantation.

PubMed

Sippl, Christoph; Ketter, Ralf; Bohr, Lisa; Kim, Yoo Jin; List, Markus; Oertel, Joachim; Urbschat, Steffi

2018-05-26

Standard therapeutic protocols for glioblastoma, the most aggressive type of brain cancer, include surgery followed by chemoradiotherapy. Additionally, carmustine-eluting wafers can be implanted locally into the resection cavity. To evaluate microRNA (miRNA)-181d as a prognostic marker of responses to carmustine wafer implantation. A total of 80 glioblastoma patients (40/group) were included in a matched pair analysis. One group (carmustine wafer group) received concomitant chemoradiotherapy with carmustine wafer implantation (Stupp protocol). The second group (control group) received only concomitant chemoradiotherapy. All tumor specimens were subjected to evaluations of miRNA-181d expression, results were correlated with further individual clinical data. The Cancer Genome Atlas (TCGA) dataset of 149 patients was used as an independent cohort to validate the results. Patients in the carmustine wafer group with low miRNA-181d expression had significantly longer overall (hazard ratio [HR], 35.03, [95% confidence interval (CI): 3.50-350.23], P = .002) and progression-free survival (HR, 20.23, [95% CI: 2.19-186.86], P = .008) than patients of the same group with a high miRNA-181d expression. These correlations were not observed in the control group. The nonsignificance in the control group was confirmed in the independent TCGA dataset. The carmustine wafer group patients with low miRNA-181d expression also had a significantly longer progression-free (P = .049) and overall survival (OS) (P = .034), compared with control group patients. Gross total resection correlated significantly with longer OS (P = .023). MiRNA-181d expression significantly affects treatment responses to carmustine wafer implantation.

Modelling deformation and fracture in confectionery wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

2015-01-22

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

Room-temperature wafer bonding of LiNbO3 and SiO2 using a modified surface activated bonding method

NASA Astrophysics Data System (ADS)

Takigawa, Ryo; Higurashi, Eiji; Asano, Tanemasa

2018-06-01

In this paper, we report room-temperature bonding of LiNbO3 (LN) and SiO2/Si for the realization of a LN on insulator (LNOI)/Si hybrid wafer. We investigate the applicability of a modified surface activated bonding (SAB) method for the direct bonding of LN and a thermally grown SiO2 layer. The modified SAB method using ion beam bombardment demonstrates the room-temperature wafer bonding of LN and SiO2. The bonded wafer was successfully cut into 0.5 × 0.5 mm2 dies without interfacial debonding owing to the applied stress during dicing. In addition, the surface energy of the bonded wafer was estimated to be approximately 1.8 J/m2 using the crack opening method. These results indicate that a strong bond strength can be achieved, which may be sufficient for device applications.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Modelling deformation and fracture in confectionery wafers

NASA Astrophysics Data System (ADS)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Dual-Beam Sample Preparation | Materials Science | NREL

Science.gov Websites

images showing cutting of trenches to remove a wafer section and transferring that section to a grid post section and transferring that section to a grid post. Here the wafer section is lifted out and seen from , extracted from the wafer then transferred and welded to a TEM grid post. Final thinning down to a thickness

BCB Bonding Technology of Back-Side Illuminated COMS Device

NASA Astrophysics Data System (ADS)

Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

2018-03-01

Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Submicron patterned metal hole etching

DOEpatents

McCarthy, Anthony M.; Contolini, Robert J.; Liberman, Vladimir; Morse, Jeffrey

2000-01-01

A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Microfluidics for synthetic biology: from design to execution.

PubMed

Ferry, M S; Razinkov, I A; Hasty, J

2011-01-01

With the expanding interest in cellular responses to dynamic environments, microfluidic devices have become important experimental platforms for biological research. Microfluidic "microchemostat" devices enable precise environmental control while capturing high quality, single-cell gene expression data. For studies of population heterogeneity and gene expression noise, these abilities are crucial. Here, we describe the necessary steps for experimental microfluidics using devices created in our lab as examples. First, we discuss the rational design of microchemostats and the tools available to predict their performance. We carefully analyze the critical parts of an example device, focusing on the most important part of any microchemostat: the cell trap. Next, we present a method for generating on-chip dynamic environments using an integrated fluidic junction coupled to linear actuators. Our system relies on the simple modulation of hydrostatic pressure to alter the mixing ratio between two source reservoirs and we detail the software and hardware behind it. To expand the throughput of microchemostat experiments, we describe how to build larger, parallel versions of simpler devices. To analyze the large amounts of data, we discuss methods for automated cell tracking, focusing on the special problems presented by Saccharomyces cerevisiae cells. The manufacturing of microchemostats is described in complete detail: from the photolithographic processing of the wafer to the final bonding of the PDMS chip to glass coverslip. Finally, the procedures for conducting Escherichia coli and S. cerevisiae microchemostat experiments are addressed. Copyright © 2011 Elsevier Inc. All rights reserved.

[The Detection of Ultra-Broadband Terahertz Spectroscopy of InP Wafer by Using Coherent Heterodyne Time-Domain Spectrometer].

PubMed

Zhang, Liang-liang; Zhang, Rui; Xu, Xiao-yan; Zhang, Cun-lin

2016-02-01

Indium Phosphide (InP) has attracted great physical interest because of its unique characteristics and is indispensable to both optical and electronic devices. However, the optical property of InP in the terahertz range (0. 110 THz) has not yet been fully characterized and systematically studied. The former researches about the properties of InP concentrated on the terahertz frequency between 0.1 and 4 THz. The terahertz optical properties of the InP in the range of 4-10 THz are still missing. It is fairly necessary to fully understand its properties in the entire terahertz range, which results in a better utilization as efficient terahertz devices. In this paper, we study the optical properties of undoped (100) InP wafer in the ultra-broad terahertz frequency range (0.5-18 THz) by using air-biased-coherent-detection (ABCD) system, enabling the coherent detection of terahertz wave in gases, which leads to a significant improvement on the dynamic range and sensitivity of the system. The advantage of this method is broad frequency bandwidth from 0.2 up to 18 THz which is only mainly limited by laser pulse duration since it uses ionized air as terahertz emitter and detector instead of using an electric optical crystal or photoconductive antenna. The terahertz pulse passing through the InP wafer is delayed regarding to the reference pulse and has much lower amplitude. In addition, the frequency spectrum amplitude of the terahertz sample signal drops to the noise floor level from 6.7 to 12.1 THz. At the same time InP wafer is opaque at the frequencies spanning from 6.7 to 12.1 THz. In the frequency regions of 0.8-6.7 and 12.1-18 THz it has relativemy low absorption coefficient. Meanwhile, the refractive index increases monotonously in the 0.8-6.7 THz region and 12.1-18 THz region. These findings will contribute to the design of InP based on nonlinear terahertz devices.

Development of high-efficiency solar cells on thin silicon through design optimization and defect passivation

NASA Astrophysics Data System (ADS)

Sheoran, Manav

The focus of this research is to investigate the potential of lower quality cast multicrystalline Si (mc-Si) as well as thin single and mc-Si cells. The overall goal of this research is to improve fundamental understanding of the hydrogen passivation of defects in low-cost Si and the fabrication of high-efficiency solar cells on thin crystalline silicon through low-cost technology development. This is addressed by a combination of five research tasks. The key results of these tasks are summarized below. A novel method was developed to determine the concentration and flux of H diffusing into the Si. The understanding of defect passivation acquired in task 1 was used to fabricate high-efficiency solar cells on cast mc-Si wafers. An optimized co-firing process was developed, which resulted in ˜17% efficient 4 cm2 screen-printed solar cells with single-layer AR coating, and no surface texturing or selective emitter. The HEM mc-Si wafer gave an average efficiency of 16.5%, with a maximum of 16.9%. The identical process applied to the un-textured Float zone (FZ) wafers gave an efficiency of 17.2%. These cells were fabricated using the same simple, manufacturable process involving POCl3 diffusion for a 45 O/sq emitter, PECVD SiNx:H deposition for single-layer antireflection coating and rapid co-firing of a Ag grid, an Al back contact, and Al-BSF formation in a belt furnace. A high-efficiency of 17.1% was achieved on high sheet-resistance HEM mc-Si with good quality contacts. The effects of changing several device parameters on the efficiency of the solar cells was modeled with PC1D and guidelines were established to improve the efficiency from ˜17% to over 20% cells on low lifetime (100 mus), thin (140 mum) silicon wafers. The understanding of enhanced defect hydrogenation and the optimized fabrication sequence was applied to fabricate high-efficiency solar cells on top, middle, and bottom regions of several mc-Si ingots. Screen-printed solar cells were fabricated on different regions of four boron doped ingots and one gallium doped ingot. High post-diffusion and post-hydrogenation lifetime values were obtained, which resulted in high-screen printed cell efficiencies of . 15.9% for wafers from all the regions and ingots, except for the bottom region of the lower-resistivity boron-doped ingot and the gallium-doped ingot. Using a lower-resistivity boron-doped mc-Si ingot did not improve the efficiency. Solar cells fabricated on the first two ingots grown by a novel process, which produced single-crystal Si wafers by HEM casting method, achieved efficiencies of 16% and 17.2% on planar and textured surfaces, respectively. Lifetime in the middle region of both the ingots exceeded 100 mus after cell processing; however top and bottom regions had lower lifetimes due to the impurities that could not be gettered or passivated. Due to the single-crystal nature of the mono-cast ingots, the wafers were textured easily, which decreased the front surface reflectance from 11.8 to 5.3% and resulted in an enhanced Jsc by ˜3mA/cm2. Large area (100 cm2) solar cells fabricated from the middle regions of this novel mono-cast material achieved an efficiency of 16.5%. The mono-cast grown by the HEM process is still under optimization, however, these results show that the material has a great potential for achieving high-efficiencies at a lower cost. Since the cost of Si material alone is ˜50% in a PV module, attempts were made to fabricate thin Si cells with full area Al-BSF and to identify the key factors responsible for efficiency loss in thin cells with conventional Al-BSF. It was found that the high BSRV (300-400 cm/s) and low back surface reflectance (BSR) (63-70%) associated with the full area Al-BSF were the major reasons for the reduced performance of thin cells. Model calculations showed that a BSRV of . 100 cm/s and BSR of ≤ 95% can virtually eliminate the efficiency gap between 300 mum and 115 mum thick cells for these ≥ 200 mus bulk lifetime wafers. Manufacturing cost modeling showed that reducing the mc-Si wafer thickness from 300 mum to 115-150 mum reduces the module manufacturing cost in spite of ˜1% lower cell efficiency. Full area Al-BSF cells suffered efficiency loss upon thinning due to a relatively higher BSRV and poor BSR of Al-BSF. Therefore, in attempts were made to fabricate, characterize and model, a device structure with local back-surface field. Thin solar cells, without any bowing, were fabricated using the dielectric passivated structure and screen-printed contacts. (Abstract shortened by UMI.)

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Differences between wafer and bake plate temperature uniformity in proximity bake: a theoretical and experimental study

NASA Astrophysics Data System (ADS)

Ramanan, Natarajan; Kozman, Austin; Sims, James B.

2000-06-01

As the lithography industry moves toward finer features, specifications on temperature uniformity of the bake plates are expected to become more stringent. Consequently, aggressive improvements are needed to conventional bake station designs to make them perform significantly better than current market requirements. To this end, we have conducted a rigorous study that combines state-of-the-art simulation tools and experimental methods to predict the impact of the parameters that influence the uniformity of the wafer in proximity bake. The key observation from this detailed study is that the temperature uniformity of the wafer in proximity mode depends on a number of parameters in addition to the uniformity of the bake plate itself. These parameters include the lid design, the air flow distribution around the bake chamber, bake plate design and flatness of the bake plate and wafer. By performing careful experimental studies that were guided by extensive numerical simulations, we were able to understand the relative importance of each of these parameters. In an orderly fashion, we made appropriate design changes to curtail or eliminate the nonuniformity caused by each of these parameters. After implementing all these changes, we have now been able to match or improve the temperature uniformity of the wafer in proximity with that of a contact measurement on the bake plate. The wafer temperature uniformity is also very close to the theoretically predicted uniformity of the wafer.

Wafering economies for industrialization from a wafer manufacturer's viewpoint

NASA Technical Reports Server (NTRS)

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Germanium Plasmon Enhanced Resonators for Label-Free Terahertz Protein Sensing

NASA Astrophysics Data System (ADS)

Bettenhausen, Maximilian; Römer, Friedhard; Witzigmann, Bernd; Flesch, Julia; Kurre, Rainer; Korneev, Sergej; Piehler, Jacob; You, Changjiang; Kazmierczak, Marcin; Guha, Subhajit; Capellini, Giovanni; Schröder, Thomas

2018-03-01

A Terahertz protein sensing concept based on subwavelength Ge resonators is presented. Ge bowtie resonators, compatible with CMOS fabrication technology, have been designed and characterized with a resonance frequency of 0.5 THz and calculated local intensity enhancement of 10.000. Selective biofunctionalization of Ge resonators on Si wafer was achieved in one step using lipoic acid-HaloTag ligand (LA-HTL) for biofunctionalization and passivation. The results lay the foundation for future investigation of protein tertiary structure and the dynamics of protein hydration shell in response to protein conformation changes.

Reflective optical imaging systems with balanced distortion

DOEpatents

Hudyma, Russell M.

2001-01-01

Optical systems compatible with extreme ultraviolet radiation comprising four reflective elements for projecting a mask image onto a substrate are described. The four optical elements comprise, in order from object to image, convex, concave, convex and concave mirrors. The optical systems are particularly suited for step and scan lithography methods. The invention enables the use of larger slit dimensions associated with ring field scanning optics, improves wafer throughput, and allows higher semiconductor device density. The inventive optical systems are characterized by reduced dynamic distortion because the static distortion is balanced across the slit width.

New polymeric materials for designing photoresistors and photodetective assemblies based on CdHgTe

NASA Astrophysics Data System (ADS)

Khitrova, L. M.; Troshkin, Y. S.; Belyaev, V. P.; Popovyan, G. E.; Kiseleva, L. V.

1999-06-01

In order to improve quality of photodetectors and photodetective assemblies two new cryo- and chemically resistant adhesives were developed: epoxy-silico-organic adhesive `(Phi) X-5P' and acrylic `OPHOH-2' adhesive for gluing of CdHgTe wafers to a substrate `XCK-H' vacuum-tight modified adhesive is used for attaching of inlet windows and glass holder elements. `OPUOH-65' vibration damping thixotropic composition was developed for mounting of multi- layer printed circuits.

Process for growing epitaxial gallium nitride and composite wafers

DOEpatents

Weber, Eicke R.; Subramanya, Sudhir G.; Kim, Yihwan; Kruger, Joachim

2003-05-13

A novel growth procedure to grow epitaxial Group III metal nitride thin films on lattice-mismatched substrates is proposed. Demonstrated are the quality improvement of epitaxial GaN layers using a pure metallic Ga buffer layer on c-plane sapphire substrate. X-ray rocking curve results indicate that the layers had excellent structural properties. The electron Hall mobility increases to an outstandingly high value of .mu.>400 cm.sup.2 /Vs for an electron background concentration of 4.times.10.sup.17 cm.sup.-3.

Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

PubMed

Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

2016-02-10

In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications.

Cold-development tool and technique for the ultimate resolution of ZEP520A to fabricate an EB master mold for nano-imprint lithography for 1Tbit/inch2 BPM development

NASA Astrophysics Data System (ADS)

Kobayashi, Hideo; Iyama, Hiromasa; Kagatsume, Takeshi; Watanabe, Tsuyoshi

2012-11-01

Cold-development is well-known for resolution enhancement on ZEP520A. Dipping a wafer in a developer solvent chilled by a freezer, such a typical method had been employed. But, it is obvious that the dip-development method has several inferiorities such as developer temperature instability, temperature inconsistency between developer and a wafer, water-condensation on drying. We then built a single wafer spin-develop tool, and established a process sequence, to solve those difficulties. And, we tried to see their effect down to -10degC over various developers. In specific, we tried to make hole patterns in hexagonal closest packing in 40nm, 35nm, 30nm, 25nm pitch, and examined holes pattern quality and resolution limit by varying setting temperature from room temperature to -10degC in the cold-development, as well as varying developer chemistry from the standard developer ZED N-50 (n-amyl acetate, 100%) to MiBK and IPA mixture which was a rinsing solvent mixture originally. We also examined the other developer (poor solvent mixture) we designed, N-50 and fluorocarbon (FC) mixture, MiBK and FC mixture, and IPA+FC mixture. This paper describes cold-development tool and technique, and its results down to minus (-) 10degC, for ZEP520A resolution enhancement to obtain 1Xnm bits (holes) in 25nm pitch to fabricate an EB master mold for Nano-Imprinting Lithography for 1Tbit/in2 bit patterned media (BPM) in HDD development and production.

An evaluation of multilayer mirrors for the soft x ray and extreme ultraviolet wavelength range that were irradiated with neutrons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Regan, S.P.; May, M.J.; Soukhanovskii, V.

1997-01-01

The Plasma Spectroscopy Group at the Johns Hopkins University develops high photon throughput multilayer mirror (MLM) based soft x ray and extreme ultraviolet (XUV 10 {Angstrom}{lt}{lambda}{lt}304 {Angstrom}) spectroscopic diagnostics for magnetically confined fusion plasmas. The D-T reactions in large fusion reactor type devices such as the International Thermonuclear Experimental Reactor will produce neutrons at a rate as high as 5{times}10{sup 19} ns{sup -1}. The MLMs, which are used as dispersive and focusing optics, will not be shielded from these neutrons. In an effort to assess the potential radiation damage, four MLMs (No. 1: Mo/Si, d=87.8 {Angstrom}, Zerodur substrate with 50more » cm concave spherical curvature; No. 2: W/B{sub 4}C, d=22.75 {Angstrom}, Si wafer substrate; No. 3: W/C, d=25.3 {Angstrom}, Si wafer substrate; and No. 4: Mo/Si, d=186.6 {Angstrom}, Si wafer substrate) were irradiated with fast neutrons at the Los Alamos Spallation Radiation Effects Facility (LASREF). The neutron beam at LASREF has an energy distribution that peaks at 1{endash}2 MeV with a tail that extends out to 100 MeV. The MLMs were irradiated to a fast neutron fluence of 1.1{times}10{sup 19} ncm{sup {minus}2} at 270{endash}300{degree}C. A comparison between the dispersive and reflective characteristics of the irradiated MLMs and the corresponding qualities of control samples will be given. {copyright} {ital 1997 American Institute of Physics.}« less

Heating device for semiconductor wafers

DOEpatents

Vosen, Steven R.

1999-01-01

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Heating device for semiconductor wafers

DOEpatents

Vosen, S.R.

1999-07-27

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

Compact particle accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elizondo-Decanini, Juan M.

2017-08-29

A compact particle accelerator having an input portion configured to receive power to produce particles for acceleration, where the input portion includes a switch, is provided. In a general embodiment, a vacuum tube receives particles produced from the input portion at a first end, and a plurality of wafer stacks are positioned serially along the vacuum tube. Each of the plurality of wafer stacks include a dielectric and metal-oxide pair, wherein each of the plurality of wafer stacks further accelerate the particles in the vacuum tube. A beam shaper coupled to a second end of the vacuum tube shapes themore » particles accelerated by the plurality of wafer stacks into a beam and an output portion outputs the beam.« less

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

Induction soldering of photovoltaic system components

DOEpatents

Kumaria, Shashwat; de Leon, Briccio

2015-11-17

A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology

NASA Astrophysics Data System (ADS)

Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

2014-01-01

The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

NASA Astrophysics Data System (ADS)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Phosphorus Diffusion Gettering Efficacy in Upgraded Metallurgical-Grade Solar Silicon

NASA Astrophysics Data System (ADS)

Jiménez, A.; del Cañizo, C.; Cid, C.; Peral, A.

2018-05-01

In the context of the continuous price reduction in photovoltaics (PV) in recent years, Si feedstock continues to be a relevant component in the cost breakdown of a PV module, highlighting the need for low-cost, low-capital expenditure (CAPEX) silicon technologies to further reduce this cost component. Upgraded metallurgical-grade silicon (UMG Si) has recently received much attention, improving its quality and even attaining, in some cases, solar cell efficiencies similar to those of conventional material. However, some technical challenges still have to be addressed when processing this material to compensate efficiently for the high content of impurities and contaminants. Adaptation of a conventional solar cell process to monocrystalline UMG Si wafers has been studied in this work. In particular, a tailored phosphorus diffusion gettering step followed by a low-temperature anneal at 700°C was implemented, resulting in enhanced bulk lifetime and emitter recombination properties. In spite of the need for further research and material optimization, UMG Si wafers were successfully processed, achieving efficiencies in the range of 15% for a standard laboratory solar cell process with aluminum back surface field.

Upright and Inverted Single-Junction GaAs Solar Cells Grown by Hydride Vapor Phase Epitaxy

DOE PAGES

Simon, John; Schulte, Kevin L.; Jain, Nikhil; ...

2016-10-19

Hydride vapor phase epitaxy (HVPE) is a low-cost alternative to conventional metal-organic vapor phase epitaxy (MOVPE) growth of III-V solar cells. In this work, we show continued improvement of the performance of HVPE-grown single-junction GaAs solar cells. We show over an order of magnitude improvement in the interface recombination velocity between GaAs and GaInP layers through the elimination of growth interrupts, leading to increased short-circuit current density and open-circuit voltage compared with cells with interrupts. One-sun conversion efficiencies as high as 20.6% were achieved with this improved growth process. Solar cells grown in an inverted configuration that were removed frommore » the substrate showed nearly identical performance to on-wafer cells, demonstrating the viability of HVPE to be used together with conventional wafer reuse techniques for further cost reduction. As a result, these devices utilized multiple heterointerfaces, showing the potential of HVPE for the growth of complex and high-quality III-V devices.« less

Thermal analysis of hydroxypropylmethylcellulose and methylcellulose: powders, gels and matrix tablets.

PubMed

Ford, J L

1999-03-15

This review focuses on the thermal analysis of hydroxypropylmethylcellulose (HPMC) and methylcellulose. Differential scanning calorimetry (DSC) of their powders is used to determine temperatures of moisture loss (in conjunction with thermogravimetric analysis) and glass transition temperatures. However, sample preparation and encapsulation affect the values obtained. The interaction of these cellulose ethers with water is evaluated by DSC. Water is added to the powder directly in DSC pans or preformed gels can be evaluated. Data quality depends on previous thermal history but estimates of the quantity of water bound to the polymers may be made. Water uptake by cellulose ethers may be evaluated by the use of polymeric wafers and by following loss of free water, over a series of timed curves, into wafers in contact with water. Cloud points, which assess the reduction of polymer solubility with increase of temperature, may be assessed spectrophotometrically. DSC and rheometric studies are used to follow thermogelation, a process involving hydrophobic interaction between partly hydrated polymeric chains. The advantages and disadvantages of the various methodologies are highlighted. Copyright.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic

NASA Astrophysics Data System (ADS)

Cramer, Hugo; Mc Namara, Elliott; van Laarhoven, Rik; Jaganatharaja, Ram; de la Fuente, Isabel; Hsu, Sharon; Belletti, Filippo; Popadic, Milos; Tu, Ward; Huang, Wade

2017-03-01

The logic manufacturing process requires small in-device metrology targets to exploit the full dose correction potential of the modern scanners and process tools. A high-NA angular resolved scatterometer (YieldStar S-1250D) was modified to demonstrate the possibility of OCD measurements on 5x5µm2 targets. The results obtained on test wafers in a logic manufacturing environment, measured after litho and after core etch, showed a good correlation to larger reference targets and AEI to ADI intra-field CDU correlation, thereby demonstrating the feasibility of OCD on such small targets. The data was used to determine a reduction potential of 55% for the intra-field CD variation, using 145 points per field on a few inner fields, and 33% of the process induced across wafer CD variation using 16 points per field full wafer. In addition, the OCD measurements reveal valuable information on wafer-to-wafer layer height variations within a lot.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

A Statistical Analysis of Laser Ablated Ba(Sub 0.50)Sr(Sub 0.50)TiO(Sub 3)/LaAlO(Sub 3) Films for Microwave Applications

NASA Technical Reports Server (NTRS)

Romanofsky, R. R.; Varaljay, N. C.; Alterovitz, S. A.; Miranda, F. A.; Mueller, C. M.; VanKeuls, F. W.; Kim, J.; Harshavardhan, K. S.

2002-01-01

The NASA Glenn Research Center is constructing a 616 element scanning phased array antenna using thin film Ba(sub x)Sr(sub 1-x)TiO(sub 3) based phase shifters. A critical milestone is the production of 616 identical phase shifters at 19 GHz with [asymptotically equal to]4 dB insertion loss and at least 337.5 deg phase shift with 3 percent bandwidth. It is well known that there is a direct relationship between dielectric tuning and loss due to the Kramers-Kronig relationship and that film crystallinity and strain, affected by the substrate template, play an important role. Ba(sub 0.50)Sr(sub 0.50)TiO (sub 3) films, nominally 400 nm thick, were deposited on 48 0.25 mm thick, 5 cm diameter LaAlO(sub 3) wafers. Although previous results suggested that Mn-doped films on MgO were intrinsically superior in terms of phase shift per unit loss, for this application phase shift per unit length was more important. The composition was selected as a compromise between tuning and loss for room temperature operation (e.g. crystallinity progressively degrades for Ba concentrations in excess of 30 percent). As a prelude to fabricating the array, it was necessary to process, screen, and inventory a large number of samples. Variable angle ellipsometry was used to characterize refractive index and film thickness across each wafer. Microstructural properties of the thin films were characterized using high resolution X-ray diffractometry. Finally, prototype phase shifters and resonators were patterned on each wafer and RE probed to measure tuning as a function of dc bias voltage as well as peak (0 field) permittivity and unloaded Q. The relationship among film quality and uniformity and performance is analyzed. This work presents the first statistically relevant study of film quality and microwave performance and represents a milestone towards commercialization of thin ferroelectric films for microwave applications.

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Composite HPMC and sodium alginate based buccal formulations for nicotine replacement therapy.

PubMed

Okeke, Obinna C; Boateng, Joshua S

2016-10-01

Smoking cessation is of current topical interest due to the significant negative health and economic impact in many countries. This study aimed to develop buccal films and wafers comprising HPMC and sodium alginate (SA) for potential use in nicotine replacement therapy via the buccal mucosa, as a cheap but effective alternative to currently used nicotine patch and chewing gum. The formulations were characterised using texture analyser (tensile and hardness, mucoadhesion), scanning electron microscopy, X-ray diffractometry, attenuated total reflection-Fourier transform infrared (ATR-FTIR), differential scanning calorimetry (DSC) and swelling capacity. Drug loaded films and wafers were characterised for content uniformity (HPLC) whilst the drug loaded wafers only were further characterised for in vitro drug dissolution. SA modified and improved the functional properties of HPMC at optimum ratio of HPMC: SA of 1.25: 0.75. Generally, both films and wafers (blank and drug loaded) were amorphous in nature which impacted on swelling and mucoadhesive performance. HPMC-SA composite wafers showed a porous internal morphology with higher mucoadhesion, swelling index and drug loading capacity compared to the HPMC-SA composite films which were non-porous. The study demonstrates the potential use of composite HPMC-SA wafers in the buccal delivery nicotine. Copyright © 2016 Elsevier B.V. All rights reserved.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

A Lorentz force actuated magnetic field sensor with capacitive read-out

NASA Astrophysics Data System (ADS)

Stifter, M.; Steiner, H.; Kainz, A.; Keplinger, F.; Hortschitz, W.; Sauter, T.

2013-05-01

We present a novel design of a resonant magnetic field sensor with capacitive read-out permitting wafer level production. The device consists of a single-crystal silicon cantilever manufactured from the device layer of an SOI wafer. Cantilevers represent a very simple structure with respect to manufacturing and function. On the top of the structure, a gold lead carries AC currents that generate alternating Lorentz forces in an external magnetic field. The free end oscillation of the actuated cantilever depends on the eigenfrequencies of the structure. Particularly, the specific design of a U-shaped structure provides a larger force-to-stiffness-ratio than standard cantilevers. The electrodes for detecting cantilever deflections are separately fabricated on a Pyrex glass-wafer. They form the counterpart to the lead on the freely vibrating planar structure. Both wafers are mounted on top of each other. A custom SU-8 bonding process on wafer level creates a gap which defines the equilibrium distance between sensing electrodes and the vibrating structure. Additionally to the capacitive read-out, the cantilever oscillation was simultaneously measured with laser Doppler vibrometry through proper windows in the SOI handle wafer. Advantages and disadvantages of the asynchronous capacitive measurement configuration are discussed quantitatively and presented by a comprehensive experimental characterization of the device under test.

Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

Numerical modeling of carrier gas flow in atomic layer deposition vacuum reactor: A comparative study of lattice Boltzmann models

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Dongqing; Chien Jen, Tien; Li, Tao

2014-01-15

This paper characterizes the carrier gas flow in the atomic layer deposition (ALD) vacuum reactor by introducing Lattice Boltzmann Method (LBM) to the ALD simulation through a comparative study of two LBM models. Numerical models of gas flow are constructed and implemented in two-dimensional geometry based on lattice Bhatnagar–Gross–Krook (LBGK)-D2Q9 model and two-relaxation-time (TRT) model. Both incompressible and compressible scenarios are simulated and the two models are compared in the aspects of flow features, stability, and efficiency. Our simulation outcome reveals that, for our specific ALD vacuum reactor, TRT model generates better steady laminar flow features all over the domainmore » with better stability and reliability than LBGK-D2Q9 model especially when considering the compressible effects of the gas flow. The LBM-TRT is verified indirectly by comparing the numerical result with conventional continuum-based computational fluid dynamics solvers, and it shows very good agreement with these conventional methods. The velocity field of carrier gas flow through ALD vacuum reactor was characterized by LBM-TRT model finally. The flow in ALD is in a laminar steady state with velocity concentrated at the corners and around the wafer. The effects of flow fields on precursor distributions, surface absorptions, and surface reactions are discussed in detail. Steady and evenly distributed velocity field contribute to higher precursor concentration near the wafer and relatively lower particle velocities help to achieve better surface adsorption and deposition. The ALD reactor geometry needs to be considered carefully if a steady and laminar flow field around the wafer and better surface deposition are desired.« less

Local delivery of cancer-cell glycolytic inhibitors in high-grade glioma

PubMed Central

Wicks, Robert T.; Azadi, Javad; Mangraviti, Antonella; Zhang, Irma; Hwang, Lee; Joshi, Avadhut; Bow, Hansen; Hutt-Cabezas, Marianne; Martin, Kristin L.; Rudek, Michelle A.; Zhao, Ming; Brem, Henry; Tyler, Betty M.

2015-01-01

Background 3-bromopyruvate (3-BrPA) and dichloroacetate (DCA) are inhibitors of cancer-cell specific aerobic glycolysis. Their application in glioma is limited by 3-BrPA's inability to cross the blood-brain-barrier and DCA's dose-limiting toxicity. The safety and efficacy of intracranial delivery of these compounds were assessed. Methods Cytotoxicity of 3-BrPA and DCA were analyzed in U87, 9L, and F98 glioma cell lines. 3-BrPA and DCA were incorporated into biodegradable pCPP:SA wafers, and the maximally tolerated dose was determined in F344 rats. Efficacies of the intracranial 3-BrPA wafer and DCA wafer were assessed in a rodent allograft model of high-grade glioma, both as a monotherapy and in combination with temozolomide (TMZ) and radiation therapy (XRT). Results 3-BrPA and DCA were found to have similar IC50 values across the 3 glioma cell lines. 5% 3-BrPA wafer-treated animals had significantly increased survival compared with controls (P = .0027). The median survival of rats with the 50% DCA wafer increased significantly compared with both the oral DCA group (P = .050) and the controls (P = .02). Rats implanted on day 0 with a 5% 3-BrPA wafer in combination with TMZ had significantly increased survival over either therapy alone. No statistical difference in survival was noted when the wafers were added to the combination therapy of TMZ and XRT, but the 5% 3-BrPA wafer given on day 0 in combination with TMZ and XRT resulted in long-term survivorship of 30%. Conclusion Intracranial delivery of 3-BrPA and DCA polymer was safe and significantly increased survival in an animal model of glioma, a potential novel therapeutic approach. The combination of intracranial 3-BrPA and TMZ provided a synergistic effect. PMID:25053853

Slopes To Prevent Trapping of Bubbles in Microfluidic Channels

NASA Technical Reports Server (NTRS)

Greer, Harold E.; Lee, Michael C.; Smith, J. Anthony; Willis, Peter A.

2010-01-01

The idea of designing a microfluidic channel to slope upward along the direction of flow of the liquid in the channel has been conceived to help prevent trapping of gas bubbles in the channel. In the original application that gave rise to this idea, the microfluidic channels are parts of micro-capillary electrophoresis (microCE) devices undergoing development for use on Mars in detecting compounds indicative of life. It is necessary to prevent trapping of gas bubbles in these devices because uninterrupted liquid pathways are essential for sustaining the electrical conduction and flows that are essential for CE. The idea is also applicable to microfluidic devices that may be developed for similar terrestrial microCE biotechnological applications or other terrestrial applications in which trapping of bubbles in microfluidic channels cannot be tolerated. A typical microCE device in the original application includes, among other things, multiple layers of borosilicate float glass wafers. Microfluidic channels are formed in the wafers, typically by use of wet chemical etching. The figure presents a simplified cross section of part of such a device in which the CE channel is formed in the lowermost wafer (denoted the channel wafer) and, according to the present innovation, slopes upward into a via hole in another wafer (denoted the manifold wafer) lying immediately above the channel wafer. Another feature of the present innovation is that the via hole in the manifold wafer is made to taper to a wider opening at the top to further reduce the tendency to trap bubbles. At the time of reporting the information for this article, an effort to identify an optimum technique for forming the slope and the taper was in progress. Of the techniques considered thus far, the one considered to be most promising is precision milling by use of femtosecond laser pulses. Other similar techniques that may work equally well are precision milling using a focused ion beam, or a small diamond-tipped drill bit.

Take a byte out of MEEF: VAMPIRE: Vehicle for Advanced Mask Pattern Inspection Readiness Evaluations

NASA Astrophysics Data System (ADS)

Badger, Karen D.; Rankin, Jed; Turley, Christina; Seki, Kazunori; Dechene, Dan J.; Abdelghany, Hesham

2016-09-01

MEEF, or Mask Error Enhancement Factor, is simply defined as the ratio of the change in printed wafer feature width to the change in mask feature width scaled to wafer level. It is important in chip manufacturing that leads to the amplification of mask errors, creating challenges with both achieving dimensional control tolerances and ensuring defect free masks, as measured by on-wafer image quality. As lithographic imaging continues to be stressed, using lower and lower k1 factor resolution enhancement techniques, the high MEEF areas present on advanced optical masks creates an environment where the need for increased mask defect sensitivity in high-MEEF areas becomes more and more critical. There are multiple approaches to mask inspection that may or may not provide enough sensitivity to detect all wafer-printable defects; the challenge in the application of these techniques is simultaneously maintaining an acceptable level of mask inspectability. The higher the MEEF, the harder the challenge will be to achieve and appropriate level of sensitivity while maintaining inspectability…and to do so on the geometries that matter. The predominant photomask fabrication inspection approach in use today compares the features on the reticle directly with the design database using high-NA optics. This approach has the ability to detect small defects, however, when inspecting aggressive OPC, it can lead to the over-detection of inconsequential, or nuisance defects. To minimize these nuisance detections, changing the sensitivity of the inspection can improve the inspectability of a mask inspected in high-NA mode, however, it leads to the inability to detect subtle, yet wafer-printable defects in High-MEEF geometry, due to the fact that this `desense' must be applied globally. There are also `lithography-emulating' approaches to inspection that use various means to provide high defect sensitivity and the ability to tolerate inconsequential, non-printing defects by using scanner-like conditions to determine which defects are wafer printable. This inspection technique is commonly referred to as being `lithography plane' or `litho plane,' since it's assessing the mask quality based on how the mask appears to the imaging optics during use, as proposed to traditional `reticle plane' inspection which is comparing the mask only with its target design. Regardless of how the defects are detected, the real question is when should they be detected? For larger technology nodes, defects are considered `statistical risks'…i.e., first they have to occur, and then they have to fall in high-MEEF areas in order to be of concern, and be below the detection limits of traditional reticle-plane inspection. In short, the `perfect storm' has to happen in order to miss printable defects using well-optimized traditional inspection approaches. The introduction of lithographic inspection techniques has revealed this statistical game is a much higher risk than originally estimated, in that very subtle waferprintable CD errors typically fall into the desense band for traditional reticle plane inspection. Because printability is largely influenced by MEEF, designs with high-MEEF values are at greater risk of traditional inspection missing printable CD errors. The question is… how high is high… and at what MEEF is optical inspection at the reticle plane sufficient? This paper will provide evaluation results for both reticle-plane and litho-plane inspections as they pertain to varying degrees of MEEF. A newly designed high-MEEF programmed defect test mask, named VAMPIRE, will be introduced. This test mask is based on 7 nm node technology and contains intentionally varying degrees of MEEF as well as a variety of programmed defects in high-MEEF environments…all of which have been verified for defect lithographic significance on a Zeiss AIMS system.

Ultra-wideband WDM VCSEL arrays by lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon

Advancements in heterogeneous integration are a driving factor in the development of evermore sophisticated and functional electronic and photonic devices. Such advancements will merge the optical and electronic capabilities of different material systems onto a common integrated device platform. This thesis presents a new lateral heterogeneous integration technology called nonplanar wafer bonding. The technique is capable of integrating multiple dissimilar semiconductor device structures on the surface of a substrate in a single wafer bond step, leaving different integrated device structures adjacent to each other on the wafer surface. Material characterization and numerical simulations confirm that the material quality is not compromised during the process. Nonplanar wafer bonding is used to fabricate ultra-wideband wavelength division multiplexed (WDM) vertical-cavity surface-emitting laser (VCSEL) arrays. The optically-pumped VCSEL arrays span 140 nm from 1470 to 1610 nm, a record wavelength span for devices operating in this wavelength range. The array uses eight wavelength channels to span the 140 nm with all channels separated by precisely 20 nm. All channels in the array operate single mode to at least 65°C with output power uniformity of +/- 1 dB. The ultra-wideband WDM VCSEL arrays are a significant first step toward the development of a single-chip source for optical networks based on coarse WDM (CWDM), a low-cost alternative to traditional dense WDM. The CWDM VCSEL arrays make use of fully-oxidized distributed Bragg reflectors (DBRs) to provide the wideband reflectivity required for optical feedback and lasing across 140 rim. In addition, a novel optically-pumped active region design is presented. It is demonstrated, with an analytical model and experimental results, that the new active-region design significantly improves the carrier uniformity in the quantum wells and results in a 50% lasing threshold reduction and a 20°C improvement in the peak operating temperature of the devices. This thesis investigates the integration and fabrication technologies required to fabricate ultra-wideband WDM VCSEL arrays. The complete device design and fabrication process is presented along with actual device results from completed CWDM VCSEL arrays. Future recommendations for improvements are presented, along with a roadmap toward a final electrically-pumped single-chip source for CWDM applications.

Growth of 1.5 micron gallium indium nitrogen arsenic antimonide vertical cavity surface emitting lasers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Wistey, Mark Allan

Fiber optics has revolutionized long distance communication and long haul networks, allowing unimaginable data speeds and noise-free telephone calls around the world for mere pennies per hour at the trunk level. But the high speeds of optical fiber generally do not extend to individual workstations or to the home, in large part because it has been difficult and expensive to produce lasers which emitted light at wavelengths which could take advantage of optical fiber. One of the most promising solutions to this problem is the development of a new class of semiconductors known as dilute nitrides. Dilute nitrides such as GaInNAs can be grown directly on gallium arsenide, which allows well-established processing techniques. More important, gallium arsenide allows the growth of vertical-cavity surface-emitting lasers (VCSELs), which can be grown in dense, 2D arrays on each wafer, providing tremendous economies of scale for manufacturing, testing, and packaging. Unfortunately, GaInNAs lasers have suffered from what has been dubbed the "nitrogen penalty," with high thresholds and low efficiency as the fraction of nitrogen in the semiconductor was increased. This thesis describes the steps taken to identify and essentially eliminate the nitrogen penalty. Protecting the wafer surface from plasma ignition, using an arsenic cap, greatly improved material quality. Using a Langmuir probe, we further found that the nitrogen plasma source produced a large number of ions which damaged the wafer during growth. The ions were dramatically reduced using deflection plates. Low voltage deflection plates were found to be preferable to high voltages, and simulations showed low voltages to be adequate for ion removal. The long wavelengths from dilute nitrides can be partly explained by wafer damage during growth. As a result of these studies, we demonstrated the first CW, room temperature lasers at wavelengths beyond 1.5mum on gallium arsenide, and the first GaInNAs(Sb) VCSELs beyond 1.31mum: 1.46mum. These techniques offer the promise of inexpensive, high speed fiber networking.

Impact of Beads and Drops on a Repellent Solid Surface: A Unified Description

NASA Astrophysics Data System (ADS)

Arora, S.; Fromental, J.-M.; Mora, S.; Phou, Ty; Ramos, L.; Ligoure, C.

2018-04-01

We investigate freely expanding sheets formed by ultrasoft gel beads, and liquid and viscoelastic drops, produced by the impact of the bead or drop on a silicon wafer covered with a thin layer of liquid nitrogen that suppresses viscous dissipation thanks to an inverse Leidenfrost effect. Our experiments show a unified behavior for the impact dynamics that holds for solids, liquids, and viscoelastic fluids and that we rationalize by properly taking into account elastocapillary effects. In this framework, the classical impact dynamics of solids and liquids, as far as viscous dissipation is negligible, appears as the asymptotic limits of a universal theoretical description. A novel material-dependent characteristic velocity that includes both capillary and bulk elasticity emerges from this unified description of the physics of impact.

Coupled and decoupled on-chip solenoid inductors with nanogranular magnetic cores

NASA Astrophysics Data System (ADS)

He, Yuhan; Wang, Luo; Wang, Yicheng; Zhang, Huaiwu; Peng, Dongliang; Bai, Feiming

2017-12-01

On-chip integrated solenoid inductors with multilayered nanogranular magnetic cores have been designed and fabricated on silicon wafers. Both decoupled and coupled inductors with multilayered magnetic cores were studied. For the decoupled inductor, an inductance of 14.2 nH or an equivalent inductance area density greater than 100 nH/mm2 was obtained, which is about 14 times of that of the air-core inductor, and the quality factor is 7.5 at 130 MHz. For the coupled inductor, an even higher peak quality factor of 17 was achieved at 300 MHz, however, the inductance area density decreased to 34 nH/mm2. The reason of the enhanced peak quality factor was attributed to less spike domains on the edge of the closure-loop shaped magnetic core, and therefore higher permeability and more uniform uniaxial anisotropy.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

PubMed

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Numerical simulation and experimental validation of the dynamics of multiple bubble merger during pool boiling under microgravity conditions.

PubMed

Abarajith, H S; Dhir, V K; Warrier, G; Son, G

2004-11-01

Numerical simulation and experimental validation of the growth and departure of multiple merging bubbles and associated heat transfer on a horizontal heated surface during pool boiling under variable gravity conditions have been performed. A finite difference scheme is used to solve the equations governing mass, momentum, and energy in the vapor liquid phases. The vapor-liquid interface is captured by a level set method that is modified to include the influence of phase change at the liquid-vapor interface. Water is used as test liquid. The effects of reduced gravity condition and orientation of the bubbles on the bubble diameter, interfacial structure, bubble merger time, and departure time, as well as local heat fluxes, are studied. In the experiments, multiple vapor bubbles are produced on artificial cavities in the 2-10 micrometer diameter range, microfabricated on the polished silicon wafer with given spacing. The wafer was heated electrically from the back with miniature strain gage type heating elements in order to control the nucleation superheat. The experiments conducted in normal Earth gravity and in the low gravity environment of KC-135 aircraft are used to validate the numerical simulations.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

2012-08-01

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm 2 and 100 × 100 μm 2 . Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

Effect of Annealing on the Density of Defects in Epitaxial CdTe (211)/GaAs

NASA Astrophysics Data System (ADS)

Bakali, Emine; Selamet, Yusuf; Tarhan, Enver

2018-05-01

CdTe thin films were grown on GaAs (211) wafers by molecular beam epitaxy as the buffer layer for HgCdTe infrared detector applications. We studied the effect of annealing on the density of dislocation of these CdTe thin films under varying annealing parameters such as annealing temperature, annealing duration, and number of cycles. Annealings were carried out using a homemade annealing reactor possessing a special heater element made of a Si wafer for rapid heating. The density of dislocations, which were made observable with a scanning electron microscope after etching with an Everson solution, were calculated by counting the number of dislocations per unit surface area, hence the term etch pit density (EPD). We were able to decrease EPD values by one order of magnitude after annealing. For example, the best EPD value after a 20-min annealing at 400°C was ˜ 2 × 107 cm-2 for a 1.63-μm CdTe thin film which was about 9.5 × 107 cm-2 before annealing. We also employed Raman scattering measurements to see the changes in the structural quality of the samples. From the Raman measurements, we were able to see improvements in the quality of our samples from the annealing by studying the ratio of 2LO/LO phonon mode Raman intensities. We also observed a clear decrease in the intensity of Te precipitations-related modes, indicating a decrease in the size and number of these precipitations.

Spin-on doping of germanium-on-insulator wafers for monolithic light sources on silicon

NASA Astrophysics Data System (ADS)

Al-Attili, Abdelrahman Z.; Kako, Satoshi; Husain, Muhammad K.; Gardes, Frederic Y.; Arimoto, Hideo; Higashitarumizu, Naoki; Iwamoto, Satoshi; Arakawa, Yasuhiko; Ishikawa, Yasuhiko; Saito, Shinichi

2015-05-01

High electron doping of germanium (Ge) is considered to be an important process to convert Ge into an optical gain material and realize a monolithic light source integrated on a silicon chip. Spin-on doping is a method that offers the potential to achieve high doping concentrations without affecting crystalline qualities over other methods such as ion implantation and in-situ doping during material growth. However, a standard spin-on doping recipe satisfying these requirements is not yet available. In this paper we examine spin-on doping of Ge-on-insulator (GOI) wafers. Several issues were identified during the spin-on doping process and specifically the adhesion between Ge and the oxide, surface oxidation during activation, and the stress created in the layers due to annealing. In order to mitigate these problems, Ge disks were first patterned by dry etching followed by spin-on doping. Even by using this method to reduce the stress, local peeling of Ge could still be identified by optical microscope imaging. Nevertheless, most of the Ge disks remained after the removal of the glass. According to the Raman data, we could not identify broadening of the lineshape which shows a good crystalline quality, while the stress is slightly relaxed. We also determined the linear increase of the photoluminescence intensity by increasing the optical pumping power for the doped sample, which implies a direct population and recombination at the gamma valley.

The effects of the NICE Technology Appraisal 121 (gliadel and temozolomide) on survival in high-grade glioma.

PubMed

Barr, James Geoffrey; Grundy, Paul L

2012-12-01

The prognosis of high-grade glioma (HGG) is poor with a median survival of about 1 year for glioblastoma. In 2007, NICE published a technology appraisal (TA121) recommending the use of carmustine wafers (Gliadel) and systemic therapy with temozolomide for selected patients with HGG. Outcomes for HGG surgery in the United Kingdom with these combined treatments have not been published. Retrospective audit of consecutive patients in a single unit with carmustine wafer implantation. Fifty-nine patients had carmustine wafers implanted at primary surgery, between October 2005 and October 2010 at Wessex Neurological Centre, Southampton, UK. Patients were given chemotherapeutic treatments strictly according to NICE TA121. Survival was calculated using Kaplan-Meier method. Fifty-five patients had WHO grade IV tumours and four had grade III. Median age was 61 years. At follow-up, 39 patients had died. Median survival was 15.3 months. Eight patients (13.5%) experienced post-operative complications (including five infections) for which four had the carmustine wafers removed. Forty-seven (80%) patients were treated with radical radiotherapy (55-60 Gy) and six (10%) patients received palliative radiotherapy (30 Gy). Thirty-seven patients (63%) received concomitant temozolomide chemotherapy. In the subset of 37 patients receiving multimodal treatment with radical radiotherapy and concomitant temozolomide, median survival was 15.8 months compared with 7.4 months in those not receiving multimodal treatment. Carmustine wafers for primary HGG surgery in accordance with the NICE TA121 were associated with a median survival of 15.3 months; this is improved compared with previously reported randomised trials. Multimodal treatment with carmustine wafers, radical radiotherapy and concomitant temozolomide was associated with improved survival. Increased incidence of infections was observed in cases receiving carmustine wafers.

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Local interstitial delivery of z-butylidenephthalide by polymer wafers against malignant human gliomas

PubMed Central

Harn, Horng-Jyh; Lin, Shinn-Zong; Lin, Po-Cheng; Liu, Cyong-Yue; Liu, Po-Yen; Chang, Li-Fu; Yen, Ssu-Yin; Hsieh, Dean-Kuo; Liu, Fu-Chen; Tai, Dar-Fu; Chiou, Tzyy-Wen

2011-01-01

We have shown that the natural compound z-butylidenephthalide (Bdph), isolated from the chloroform extract of Angelica sinensis, has antitumor effects. Because of the limitation of the blood-brain barrier, the Bdph dosage required for treatment of glioma is relatively high. To solve this problem, we developed a local-release system with Bdph incorporated into a biodegradable polyanhydride material, p(CPP-SA; Bdph-Wafer), and investigated its antitumor effects. On the basis of in vitro release kinetics, we demonstrated that the Bdph-Wafer released 50% of the available Bdph by the sixth day, and the release reached a plateau phase (90% of Bdph) by the 30th day. To investigate the in situ antitumor effects of the Bdph-Wafer on glioblastoma multiforme (GBM), we used 2 xenograft animal models—F344 rats (for rat GBM) and nude mice (for human GBM)—which were injected with RG2 and DBTRG-05MG cells, respectively, for tumor formation and subsequently treated subcutaneously with Bdph-Wafers. We observed a significant inhibitory effect on tumor growth, with no significant adverse effects on the rodents. Moreover, we demonstrated that the antitumor effect of Bdph on RG2 cells was via the PKC pathway, which upregulated Nurr77 and promoted its translocation from the nucleus to the cytoplasm. Finally, to study the effect of the interstitial administration of Bdph in cranial brain tumor, Bdph-Wafers were surgically placed in FGF-SV40 transgenic mice. Our Bdph-Wafer significantly reduced tumor size in a dose-dependent manner. In summary, our study showed that p(CPP-SA) containing Bdph delivered a sufficient concentration of Bdph to the tumor site and effectively inhibited the tumor growth in the glioma. PMID:21565841

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Capillary liquid chromatography-microchip atmospheric pressure chemical ionization-mass spectrometry.

PubMed

Ostman, Pekka; Jäntti, Sirkku; Grigoras, Kestas; Saarela, Ville; Ketola, Raimo A; Franssila, Sami; Kotiaho, Tapio; Kostiainen, Risto

2006-07-01

A miniaturized nebulizer chip for capillary liquid chromatography-atmospheric pressure chemical ionization-mass spectrometry (capillary LC-microchip APCI-MS) is presented. The APCI chip consists of two wafers, a silicon wafer and a Pyrex glass wafer. The silicon wafer has a DRIE etched through-wafer nebulizer gas inlet, an edge capillary insertion channel, a stopper, a vaporizer channel and a nozzle. The platinum heater electrode and pads for electrical connection were patterned on to the Pyrex glass wafer. The two wafers were joined by anodic bonding, creating a microchip version of an APCI-source. The sample inlet capillary from an LC column is directly connected to the vaporizer channel of the APCI chip. The etched nozzle in the microchip forms a narrow sample plume, which is ionized by an external corona needle, and the formed ions are analyzed by a mass spectrometer. The nebulizer chip enables for the first time the use of low flow rate separation techniques with APCI-MS. The performance of capillary LC-microchip APCI-MS was tested with selected neurosteroids. The capillary LC-microchip APCI-MS provides quantitative repeatability and good linearity. The limits of detection (LOD) with a signal-to-noise ratio (S/N) of 3 in MS/MS mode for the selected neurosteroids were 20-1000 fmol (10-500 nmol l(-1)). LODs (S/N = 3) with commercial macro APCI with the same compounds using the same MS were about 10 times higher. Fast heat transfer allows the use of the optimized temperature for each compound during an LC run. The microchip APCI-source provides a convenient and easy method to combine capillary LC to any API-MS equipped with an APCI source. The advantages and potentials of the microchip APCI also make it a very attractive interface in microfluidic APCI-MS.

Field trials of solid triple lure (trimedlure, methyl eugenol, raspberry ketone, and DDVP) dispensers for detection and male annihilation of Ceratitis capitata, Bactrocera dorsalis, and Bactrocera cucurbitae (Diptera: Tephritidae) in Hawaii.

PubMed

Vargas, Roger I; Souder, Steven K; Mackey, Bruce; Cook, Peter; Morse, Joseph G; Stark, John D

2012-10-01

Solid Mallet TMR (trimedlure [TML], methyl eugenol [ME], raspberry ketone [RK]) wafers and Mallet CMR (ceralure, ME, RK, benzyl acetate) wafers impregnated with DDVP (2,2-dichlorovinyl dimethyl phosphate) insecticide were measured in traps as potential detection and male annihilation technique (MAT) devices. Comparisons were made with 1) liquid lure and insecticide formulations, 2) solid cones and plugs with an insecticidal strip, and 3) solid single and double lure wafers with DDVP for captures of Mediterranean fruit fly, Ceratitis capitata (Wiedemann); oriental fruit fly, Bactrocera dorsalis Hendel; and melon fly, B. cucurbitae Coquillett. Bucket and Jackson traps were tested in a coffee plantation near Eleele, Kauai Island, HI (trials at high populations) and avocado orchards near Kona, HI Island, HI (trials at low populations). Captures of all three species with Mallet TMR were not different from Mallet CMR; therefore, subsequent experiments did not include Mallet CMR because of higher production costs. In MAT trials near Eleele, HI captures in AWPM traps with Mallet TMR wafers were equal to any other solid lure (single or double) except the Mallet ME wafer. In survey trials near Kona, captures of C. capitata, B. cucurbitae, and B. dorsalis with Mallet TMR wafers were equal to those for the standard TML, ME, and C-L traps used in FL and CA. A solid Mallet TMR wafer is safer, more convenient to handle, and may be used in place of several individual lure and trap systems, potentially reducing costs of large survey and detection programs in Florida and California, and MAT programs in Hawaii.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

[Fatty acids in confectionery products].

PubMed

Daniewski, M; Mielniczuk, E; Jacórzyński, B; Pawlicka, M; Balas, J; Filipek, A; Górnicka, M

2000-01-01

The content of fat and fatty acids in 144 different confectionery products purchased on the market in Warsaw region during 1997-1999 have been investigated. In examined confectionery products considerable variability of both fat and fatty acids content have been found. The content of fat varied from 6.6% (coconut cookies) up to 40% (chocolate wafers). Saturated fatty acids were present in both cis and trans form. Especially trans fatty acids reach (above 50%) were fats extracted from nut wafers, coconuts wafers.

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

Active high-power RF switch and pulse compression system

DOEpatents

Tantawi, Sami G.; Ruth, Ronald D.; Zolotorev, Max

1998-01-01

A high-power RF switching device employs a semiconductor wafer positioned in the third port of a three-port RF device. A controllable source of directed energy, such as a suitable laser or electron beam, is aimed at the semiconductor material. When the source is turned on, the energy incident on the wafer induces an electron-hole plasma layer on the wafer, changing the wafer's dielectric constant, turning the third port into a termination for incident RF signals, and. causing all incident RF signals to be reflected from the surface of the wafer. The propagation constant of RF signals through port 3, therefore, can be changed by controlling the beam. By making the RF coupling to the third port as small as necessary, one can reduce the peak electric field on the unexcited silicon surface for any level of input power from port 1, thereby reducing risk of damaging the wafer by RF with high peak power. The switch is useful to the construction of an improved pulse compression system to boost the peak power of microwave tubes driving linear accelerators. In this application, the high-power RF switch is placed at the coupling iris between the charging waveguide and the resonant storage line of a pulse compression system. This optically controlled high power RF pulse compression system can handle hundreds of Megawatts of power at X-band.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less

Fundamental understanding of wave generation and reception using d(36) type piezoelectric transducers.

PubMed

Zhou, Wensong; Li, Hui; Yuan, Fuh-Gwo

2015-03-01

A new piezoelectric wafer made from a PMN-PT single crystal with dominant piezoelectric coefficient d36 is proposed to generate and detect guided waves on isotropic plates. The in-plane shear coupled with electric field arising from the piezoelectric coefficient is not usually present for conventional piezoelectric wafers, such as lead zirconate titanate (PZT). The direct piezoelectric effect of coefficient d36 indicates that under external in-plane shear stress the charge is induced on a face perpendicular to the poled z-direction. On thin plates, this type of piezoelectric wafer will generate shear horizontal (SH) waves in two orthogonal wave propagation directions as well as two Lamb wave modes in other wave propagation directions. Finite element analyses are employed to explore the wave disturbance in terms of time-varying displacements excited by the d36 wafer in different directions of wave propagation to understand all the guided wave modes accurately. Experiments are conducted to examine the voltage responses received by this type of wafer, and also investigate results of tuning frequency and effects of d31 piezoelectric coefficient, which is intentionally ignored in the finite element analysis. All results demonstrate the main features and utility of proposed d36 piezoelectric wafer for guided wave generation and detection in structural health monitoring. Copyright © 2014 Elsevier B.V. All rights reserved.

A novel approach of chemical mechanical polishing using environment-friendly slurry for mercury cadmium telluride semiconductors

PubMed Central

Zhang, Zhenyu; Wang, Bo; Zhou, Ping; Guo, Dongming; Kang, Renke; Zhang, Bi

2016-01-01

A novel approach of chemical mechanical polishing (CMP) is developed for mercury cadmium telluride (HgCdTe or MCT) semiconductors. Firstly, fixed-abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water. Secondly, the MCT wafers are polished using the developed CMP slurry. The CMP slurry consists of mainly SiO2 nanospheres, H2O2, and malic and citric acids, which are different from previous CMP slurries, in which corrosive and toxic chemical reagents are usually employed. Finally, the polished MCT wafers are cleaned and dried by deionized water and compressed air, respectively. The novel approach of CMP is environment-friendly. Surface roughness Ra, and peak-to-valley (PV) values of 0.45, and 4.74 nm are achieved, respectively on MCT wafers after CMP. The first and second passivating processes are observed in electrochemical measurements on MCT wafers. The fundamental mechanisms of CMP are proposed according to the X-ray photoelectron spectroscopy (XPS) and electrochemical measurements. Malic and citric acids dominate the first passivating process, and the CMP slurry governs the second process. Te4+3d peaks are absent after CMP induced by the developed CMP slurry, indicating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2 and malic and citric acids solutions. PMID:26926622