Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

2000-01-01

This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

Flexible Organic Electronics for Use in Neural Sensing

PubMed Central

Bink, Hank; Lai, Yuming; Saudari, Sangameshwar R.; Helfer, Brian; Viventi, Jonathan; Van der Spiegel, Jan; Litt, Brian; Kagan, Cherie

2016-01-01

Recent research in brain-machine interfaces and devices to treat neurological disease indicate that important network activity exists at temporal and spatial scales beyond the resolution of existing implantable devices. High density, active electrode arrays hold great promise in enabling high-resolution interface with the brain to access and influence this network activity. Integrating flexible electronic devices directly at the neural interface can enable thousands of multiplexed electrodes to be connected using many fewer wires. Active electrode arrays have been demonstrated using flexible, inorganic silicon transistors. However, these approaches may be limited in their ability to be cost-effectively scaled to large array sizes (8×8 cm). Here we show amplifiers built using flexible organic transistors with sufficient performance for neural signal recording. We also demonstrate a pathway for a fully integrated, amplified and multiplexed electrode array built from these devices. PMID:22255558

DC switching regulated power supply for driving an inductive load

DOEpatents

Dyer, George R.

1986-01-01

A power supply for driving an inductive load current from a dc power supply hrough a regulator circuit including a bridge arrangement of diodes and switching transistors controlled by a servo controller which regulates switching in response to the load current to maintain a selected load current. First and second opposite legs of the bridge are formed by first and second parallel-connected transistor arrays, respectively, while the third and fourth legs of the bridge are formed by appropriately connected first and second parallel connected diode arrays, respectively. The regulator may be operated in three "stages" or modes: (1) For current runup in the load, both first and second transistor switch arrays are turned "on" and current is supplied to the load through both transistor arrays. (2) When load current reaches the desired level, the first switch is turned "off", and load current "flywheels" through the second switch array and the fourth leg diode array connecting the second switch array in series with the load. Current is maintained by alternating between modes 1 and 2 at a suitable duty cycle and switching rate set by the controller. (3) Rapid current rundown is accomplished by turning both switch arrays "off", allowing load current to be dumped back into the source through the third and fourth diode arrays connecting the source in series opposition with the load to recover energy from the inductive load. The three operating states are controlled automatically by the controller.

PbSe Nanocrystal Solids for n- and p-Channel Thin Film Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Talapin, Dmitri V.; Murray, Christopher B.

2005-10-01

Initially poorly conducting PbSe nanocrystal solids (quantum dot arrays or superlattices) can be chemically ``activated'' to fabricate n- and p-channel field effect transistors with electron and hole mobilities of 0.9 and 0.2 square centimeters per volt-second, respectively; with current modulations of about 103 to 104; and with current density approaching 3 × 104 amperes per square centimeter. Chemical treatments engineer the interparticle spacing, electronic coupling, and doping while passivating electronic traps. These nanocrystal field-effect transistors allow reversible switching between n- and p-transport, providing options for complementary metal oxide semiconductor circuits and enabling a range of low-cost, large-area electronic, optoelectronic, thermoelectric, and sensing applications.

Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

NASA Astrophysics Data System (ADS)

Shauly, Eitan; Rotstein, Israel; Peltinov, Ram; Latinski, Sergei; Adan, Ofer; Levi, Shimon; Menadeva, Ovadya

2009-03-01

The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmaxTM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.

Rapid, sensitive and label-free detection of Shiga-toxin producing Escherichia coli O157 using carbon nanotube biosensors.

PubMed

Subramanian, Sowmya; Aschenbach, Konrad H; Evangelista, Jennifer P; Najjar, Mohamed Badaoui; Song, Wenxia; Gomez, Romel D

2012-02-15

An electronic platform to detect very small amounts of genomic DNA from bacteria without the need for PCR amplification and molecular labeling is described. The system uses carbon nanotube field-effect transistor (FET) arrays whose electrical properties are affected by minute electrical charges localized on their active regions. Two pathogenic strains of E. coli are used to evaluate the detection properties of the transistor arrays. Described herein are the results for detection of synthetic oligomers, unpurified and highly purified genomic DNA at various concentrations and their comparison against non-specific binding. In particular, the capture of genomic DNA of E. coli O157:H7 by a specific oligonucleotide probe coated onto the transistor array results in a significant shift in the threshold (gate-source) voltage (V(th)). By contrast the signal under the same procedure using a different strain, E. coli O45 that is non-complementary to the probe remained nearly constant. This work highlights the detection sensitivity and efficacy of this biosensor without stringent requirement for DNA sample preparation. Copyright © 2011 Elsevier B.V. All rights reserved.

Development of optimized detector/spectrophotometer technology for low background space astronomy missions

NASA Technical Reports Server (NTRS)

Jones, B.

1985-01-01

This program was directed towards a better understanding of some of the important factors in the performance of infrared detector arrays at low background conditions appropriate for space astronomy. The arrays were manufactured by Aerojet Electrosystems Corporation, Azusa. Two arrays, both bismuth doped silicon, were investigated: an AMCID 32x32 Engineering mosiac Si:Bi accumulation mode charge injection device detector array and a metal oxide semiconductor/field effect transistor (MOS-FET) switched array of 16x32 pixels.

Mapping brain activity with flexible graphene micro-transistors

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Tort-Colet, Núria; Guimerà-Brunet, Anton; Weinert, Julia; Rousseau, Lionel; Heimann, Axel; Drieschner, Simon; Kempski, Oliver; Villa, Rosa; Sanchez-Vives, Maria V.; Garrido, Jose A.

2017-06-01

Establishing a reliable communication interface between the brain and electronic devices is of paramount importance for exploiting the full potential of neural prostheses. Current microelectrode technologies for recording electrical activity, however, evidence important shortcomings, e.g. challenging high density integration. Solution-gated field-effect transistors (SGFETs), on the other hand, could overcome these shortcomings if a suitable transistor material were available. Graphene is particularly attractive due to its biocompatibility, chemical stability, flexibility, low intrinsic electronic noise and high charge carrier mobilities. Here, we report on the use of an array of flexible graphene SGFETs for recording spontaneous slow waves, as well as visually evoked and also pre-epileptic activity in vivo in rats. The flexible array of graphene SGFETs allows mapping brain electrical activity with excellent signal-to-noise ratio (SNR), suggesting that this technology could lay the foundation for a future generation of in vivo recording implants.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Monolithically integrated two-dimensional arrays of optoelectronic threshold devices for neural network applications

NASA Technical Reports Server (NTRS)

Kim, J. H.; Katz, J.; Lin, S. H.; Psaltis, D.

1989-01-01

A monolithic 10 x 10 two-dimensional array of 'optical neuron' optoelectronic threshold elements for neural network applications has been designed, fabricated, and tested. Overall array dimensions are 5 x 5 mm, while the individual neurons, composed of an LED that is driven by a double-heterojunction bipolar transistor, are 250 x 250 microns. The overall integrated structure exhibited semiconductor-controlled rectifier characteristics, with a breakover voltage of 75 V and a reverse-breakdown voltage of 60 V; this is attributable to the parasitic p-n-p transistor which exists as a result of the sharing of the same n-AlGaAs collector between the transistors and the LED.

Logarithmic current measurement circuit with improved accuracy and temperature stability and associated method

DOEpatents

Ericson, M. Nance; Rochelle, James M.

1994-01-01

A logarithmic current measurement circuit for operating upon an input electric signal utilizes a quad, dielectrically isolated, well-matched, monolithic bipolar transistor array. One group of circuit components within the circuit cooperate with two transistors of the array to convert the input signal logarithmically to provide a first output signal which is temperature-dependant, and another group of circuit components cooperate with the other two transistors of the array to provide a second output signal which is temperature-dependant. A divider ratios the first and second output signals to provide a resultant output signal which is independent of temperature. The method of the invention includes the operating steps performed by the measurement circuit.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Analysis and Modeling of Fullerene Single Electron Transistor Based on Quantum Dot Arrays at Room Temperature

NASA Astrophysics Data System (ADS)

Khadem Hosseini, Vahideh; Ahmadi, Mohammad Taghi; Ismail, Razali

2018-05-01

The single electron transistor (SET) as a fast electronic device is a candidate for future nanoscale circuits because of its low energy consumption, small size and simplified circuit. It consists of source and drain electrodes with a quantum dot (QD) located between them. Moreover, it operates based on the Coulomb blockade (CB) effect. It occurs when the charging energy is greater than the thermal energy. Consequently, this condition limits SET operation at cryogenic temperatures. Hence, using QD arrays can overcome this temperature limitation in SET which can therefore work at room temperature but QD arrays increase the threshold voltage with is an undesirable effect. In this research, fullerene as a zero-dimensional material with unique properties such as quantum capacitance and high critical temperature has been selected for the material of the QDs. Moreover, the current of a fullerene QD array SET has been modeled and its threshold voltage is also compared with a silicon QD array SET. The results show that the threshold voltage of fullerene SET is lower than the silicon one. Furthermore, the comparison study shows that homogeneous linear QD arrays have a lower CB range and better operation than a ring QD array SET. Moreover, the effect of the number of QDs in a QD array SET is investigated. The result confirms that the number of QDs can directly affect the CB range. Moreover, the desired current can be achieved by controlling the applied gate voltage and island diameters in a QD array SET.

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation using Superconducting Tunnel Junctions with Radio-Frequency Single-Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Wollack, E. J.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2002-01-01

The science drivers for the SPIRIT/SPECS missions demand sensitive, fast, compact, low-power, large-format detector arrays for high resolution imaging and spectroscopy in the far infrared and submillimeter. Detector arrays with 10,000 pixels and sensitivity less than 10(exp 20)-20 W/Hz(exp 20)0.5 are needed. Antenna-coupled superconducting tunnel junction detectors with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique when forming arrays. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Rigid and flexible organic electrochemical transistor arrays for monitoring action potentials from electrogenic cells.

PubMed

Yao, Chunlei; Li, Qianqian; Guo, Jing; Yan, Feng; Hsing, I-Ming

2015-03-11

Rigid and flexible organic electrochemical transistor arrays are successfully implemented for monitoring cardiac action potentials. Excellent signal to noise ratios are achieved with values routinely larger than 4. These devices are promising to be used in both conventional and emerging areas. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Solution-processed single-wall carbon nanotube transistor arrays for wearable display backplanes

NASA Astrophysics Data System (ADS)

Kang, Byeong-Cheol; Ha, Tae-Jun

2018-01-01

In this paper, we demonstrate solution-processed single-wall carbon nanotube thin-film transistor (SWCNT-TFT) arrays with polymeric gate dielectrics on the polymeric substrates for wearable display backplanes, which can be directly attached to the human body. The optimized SWCNT-TFTs without any buffer layer on flexible substrates exhibit a linear field-effect mobility of 1.5cm2/V-s and a threshold voltage of around 0V. The statistical plot of the key device metrics extracted from 35 SWCNT-TFTs which were fabricated in different batches at different times conclusively support that we successfully demonstrated high-performance solution-processed SWCNT-TFT arrays which demand excellent uniformity in the device performance. We also investigate the operational stability of wearable SWCNT-TFT arrays against an applied strain of up to 40%, which is the essential for a harsh degree of strain on human body. We believe that the demonstration of flexible SWCNT-TFT arrays which were fabricated by all solution-process except the deposition of metal electrodes at process temperature below 130oC can open up new routes for wearable display backplanes.

Sparsely-Bonded CMOS Hybrid Imager

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

2015-01-01

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

High performance organic transistor active-matrix driver developed on paper substrate

NASA Astrophysics Data System (ADS)

Peng, Boyu; Ren, Xiaochen; Wang, Zongrong; Wang, Xinyu; Roberts, Robert C.; Chan, Paddy K. L.

2014-09-01

The fabrication of electronic circuits on unconventional substrates largely broadens their application areas. For example, green electronics achieved through utilization of biodegradable or recyclable substrates, can mitigate the solid waste problems that arise at the end of their lifespan. Here, we combine screen-printing, high precision laser drilling and thermal evaporation, to fabricate organic field effect transistor (OFET) active-matrix (AM) arrays onto standard printer paper. The devices show a mobility and on/off ratio as high as 0.56 cm2V-1s-1 and 109 respectively. Small electrode overlap gives rise to a cut-off frequency of 39 kHz, which supports that our AM array is suitable for novel practical applications. We demonstrate an 8 × 8 AM light emitting diode (LED) driver with programmable scanning and information display functions. The AM array structure has excellent potential for scaling up.

High performance organic transistor active-matrix driver developed on paper substrate

PubMed Central

Peng, Boyu; Ren, Xiaochen; Wang, Zongrong; Wang, Xinyu; Roberts, Robert C.; Chan, Paddy K. L.

2014-01-01

The fabrication of electronic circuits on unconventional substrates largely broadens their application areas. For example, green electronics achieved through utilization of biodegradable or recyclable substrates, can mitigate the solid waste problems that arise at the end of their lifespan. Here, we combine screen-printing, high precision laser drilling and thermal evaporation, to fabricate organic field effect transistor (OFET) active-matrix (AM) arrays onto standard printer paper. The devices show a mobility and on/off ratio as high as 0.56 cm2V−1s−1 and 109 respectively. Small electrode overlap gives rise to a cut-off frequency of 39 kHz, which supports that our AM array is suitable for novel practical applications. We demonstrate an 8 × 8 AM light emitting diode (LED) driver with programmable scanning and information display functions. The AM array structure has excellent potential for scaling up. PMID:25234244

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

Analysis of low-offset CTIA amplifier for small-size-pixel infrared focal plane array

NASA Astrophysics Data System (ADS)

Zhang, Xue; Huang, Zhangcheng; Shao, Xiumei

2014-11-01

The design of input stage amplifier becomes more and more difficult as the expansion of format arrays and reduction of pixel size. A design method of low-offset amplifier based on 0.18-μm process used in small-size pixel is analyzed in order to decrease the dark signal of extended wavelength InGaAs infrared focal plane arrays (IRFPA). Based on an example of a cascode operational amplifier (op-amp), the relationship between input offset voltage and size of each transistor is discussed through theoretical analysis and Monte Carlo simulation. The results indicate that input transistors and load transistors have great influence on the input offset voltage while common-gate transistors are negligible. Furthermore, the offset voltage begins to increase slightly when the width and length of transistors decrease along with the diminution of pixel size, and raises rapidly when the size is smaller than a proximate threshold value. The offset voltage of preamplifiers with differential architecture and single-shared architecture in small pitch pixel are studied. After optimization under same conditions, simulation results show that single-shared architecture has smaller offset voltage than differential architecture.

Electrically tunable terahertz metamaterials with embedded large-area transparent thin-film transistor arrays

PubMed Central

Xu, Wei-Zong; Ren, Fang-Fang; Ye, Jiandong; Lu, Hai; Liang, Lanju; Huang, Xiaoming; Liu, Mingkai; Shadrivov, Ilya V.; Powell, David A.; Yu, Guang; Jin, Biaobing; Zhang, Rong; Zheng, Youdou; Tan, Hark Hoe; Jagadish, Chennupati

2016-01-01

Engineering metamaterials with tunable resonances are of great importance for improving the functionality and flexibility of terahertz (THz) systems. An ongoing challenge in THz science and technology is to create large-area active metamaterials as building blocks to enable efficient and precise control of THz signals. Here, an active metamaterial device based on enhancement-mode transparent amorphous oxide thin-film transistor arrays for THz modulation is demonstrated. Analytical modelling based on full-wave techniques and multipole theory exhibits excellent consistent with the experimental observations and reveals that the intrinsic resonance mode at 0.75 THz is dominated by an electric response. The resonant behavior can be effectively tuned by controlling the channel conductivity through an external bias. Such metal/oxide thin-film transistor based controllable metamaterials are energy saving, low cost, large area and ready for mass-production, which are expected to be widely used in future THz imaging, sensing, communications and other applications. PMID:27000419

Application of power transistors to residential and intermediate rating photovoltaic array power conditioners

NASA Astrophysics Data System (ADS)

Steigerwald, R. L.; Ferraro, A.; Turnbull, F. G.

1983-04-01

Power conditioning systems that interface with photovoltaic arrays are presently investigated for the cases of 5-30 kW residential systems interfacing with a 240-V single-phase utility connection, and 30-200 kW intermediate systems interfacing with a 480-V three-phase utility connection. Both systems require an isolation transformer between the array and the utility interface. A tradeoff study is conducted for numerous transistor and thyristor circuits and configurations, with weighting criteria that include full- and part-load efficiency, size, weight, reliability, ease of control, injected harmonics, reactive power requirements, and parts cost. On the basis of study results, a 10-kW high frequency transistor inverter feeding a high frequency isolation transformer with a sinusoidally shaped current wave was selected.

Modified Reference SPS with Solid State Transmitting Antenna

NASA Technical Reports Server (NTRS)

Woodcock, G. R.; Sperber, B. R.

1980-01-01

The development of solid state microwave power amplifiers for a solar power satellite transmitting antenna is discussed. State-of-the-art power-added efficiency, gain, and single device power of various microwave solid state devices are compared. The GaAs field effect transistors and the Si-bipolar transistors appear potentially feasible for solar power satellite use. The integration of solid state devices into antenna array elements is examined and issues concerning antenna integration and consequent satellite configurations are examined.

GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors

NASA Astrophysics Data System (ADS)

Yu, Feng; Yao, Shengbo; Römer, Friedhard; Witzigmann, Bernd; Schimpke, Tilman; Strassburg, Martin; Bakin, Andrey; Schumacher, Hans Werner; Peiner, Erwin; Suryo Wasisto, Hutomo; Waag, Andreas

2017-03-01

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors.

PubMed

Yu, Feng; Yao, Shengbo; Römer, Friedhard; Witzigmann, Bernd; Schimpke, Tilman; Strassburg, Martin; Bakin, Andrey; Schumacher, Hans Werner; Peiner, Erwin; Wasisto, Hutomo Suryo; Waag, Andreas

2017-03-03

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

Energy Guiding and Harvesting through Phonon-Engineered Graphene

DTIC Science & Technology

2016-01-28

improve the performance of carbon nanotube array transistors. Such transistors suffer about two orders of magnitude performance penalty due to high... nanotube - nanotube resistances in the current pathways from source to drain. Thus, under normal operation CNT array 1. REPORT DATE (DD-MM-YYYY) 4. TITLE...Research Office P.O. Box 12211 Research Triangle Park, NC 27709-2211 Carbon Nanotubes , FETs, Nanosoldering REPORT DOCUMENTATION PAGE 11. SPONSOR

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array.

PubMed

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B-H; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable-like human skin-would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array

NASA Astrophysics Data System (ADS)

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R.; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M.; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B.-H.; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable—like human skin—would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Wafer-scale, massively parallel carbon nanotube arrays for realizing field effect transistors with current density exceeding silicon and gallium arsenide

NASA Astrophysics Data System (ADS)

Arnold, Michael

Calculations have indicated that aligned arrays of semiconducting carbon nanotubes (CNTs) promise to outperform conventional semiconducting materials in short-channel, aggressively scaled field effect transistors (FETs) like those used in semiconductor logic and high frequency amplifier technologies. These calculations have been based on extrapolation of measurements of FETs based on one CNT, in which ballistic transport approaching the quantum conductance limit of 2Go = 4e2/h has been achieved. However, constraints in CNT sorting, processing, alignment, and contacts give rise to non-idealities when CNTs are implemented in densely-packed parallel arrays, which has resulted in a conductance per CNT far from 2Go. The consequence has been that it has been very difficult to create high performance CNT array FETs, and CNT array FETs have not outperformed but rather underperformed channel materials such as Si by 6 x or more. Here, we report nearly ballistic CNT array FETs at a density of 50 CNTs um-1, created via CNT sorting, wafer-scale alignment and assembly, and treatment. The on-state conductance in the arrays is as high as 0.46 Go per CNT, and the conductance of the arrays reaches 1.7 mS um-1, which is 7 x higher than previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density reaches 900 uA um-1 and is similar to or exceeds that of Si FETs when compared at equivalent gate oxide thickness, off-state current density, and channel length. The on-state current density exceeds that of GaAs FETs, as well. This leap in CNT FET array performance is a significant advance towards the exploitation of CNTs in high-performance semiconductor electronics technologies.

Method of fabrication of display pixels driven by silicon thin film transistors

DOEpatents

Carey, Paul G.; Smith, Patrick M.

1999-01-01

Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

Toward active-matrix lab-on-a-chip: programmable electrofluidic control enabled by arrayed oxide thin film transistors.

PubMed

Noh, Joo Hyon; Noh, Jiyong; Kreit, Eric; Heikenfeld, Jason; Rack, Philip D

2012-01-21

Agile micro- and nano-fluidic control is critical to numerous life science and chemical science synthesis as well as kinetic and thermodynamic studies. To this end, we have demonstrated the use of thin film transistor arrays as an active matrix addressing method to control an electrofluidic array. Because the active matrix method minimizes the number of control lines necessary (m + n lines for the m×n element array), the active matrix addressing method integrated with an electrofluidic platform can be a significant breakthrough for complex electrofluidic arrays (increased size or resolution) with enhanced function, agility and programmability. An amorphous indium gallium zinc oxide (a-IGZO) semiconductor active layer is used because of its high mobility of 1-15 cm(2) V(-1) s(-1), low-temperature processing and transparency for potential spectroscopy and imaging. Several electrofluidic functionalities are demonstrated using a simple 2 × 5 electrode array connected to a 2 × 5 IGZO thin film transistor array with the semiconductor channel width of 50 μm and mobility of 6.3 cm(2) V(-1) s(-1). Additionally, using the TFT device characteristics, active matrix addressing schemes are discussed as the geometry of the electrode array can be tailored to act as a storage capacitor element. Finally, requisite material and device parameters are discussed in context with a VGA scale active matrix addressed electrofluidic platform.

Strategies for Improving the Performance of Sensors Based on Organic Field-Effect Transistors.

PubMed

Wu, Xiaohan; Mao, Shun; Chen, Junhong; Huang, Jia

2018-04-01

Organic semiconductors (OSCs) have been extensively studied as sensing channel materials in field-effect transistors due to their unique charge transport properties. Stimulation caused by its environmental conditions can readily change the charge-carrier density and mobility of OSCs. Organic field-effect transistors (OFETs) can act as both signal transducers and signal amplifiers, which greatly simplifies the device structure. Over the past decades, various sensors based on OFETs have been developed, including physical sensors, chemical sensors, biosensors, and integrated sensor arrays with advanced functionalities. However, the performance of OFET-based sensors still needs to be improved to meet the requirements from various practical applications, such as high sensitivity, high selectivity, and rapid response speed. Tailoring molecular structures and micro/nanofilm structures of OSCs is a vital strategy for achieving better sensing performance. Modification of the dielectric layer and the semiconductor/dielectric interface is another approach for improving the sensor performance. Moreover, advanced sensory functionalities have been achieved by developing integrated device arrays. Here, a brief review of strategies used for improving the performance of OFET sensors is presented, which is expected to inspire and provide guidance for the design of future OFET sensors for various specific and practical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Focal plane infrared readout circuit

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2002-01-01

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

"Liquid-liquid-solid"-type superoleophobic surfaces to pattern polymeric semiconductors towards high-quality organic field-effect transistors.

PubMed

Wu, Yuchen; Su, Bin; Jiang, Lei; Heeger, Alan J

2013-12-03

Precisely aligned organic-liquid-soluble semiconductor microwire arrays have been fabricated by "liquid-liquid-solid" type superoleophobic surfaces directed fluid drying. Aligned organic 1D micro-architectures can be built as high-quality organic field-effect transistors with high mobilities of >10 cm(2) ·V(-1) ·s(-1) and current on/off ratio of more than 10(6) . All these studies will boost the development of 1D microstructures of organic semiconductor materials for potential application in organic electronics. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nanomechanical silicon resonators with intrinsic tunable gain and sub-nW power consumption.

PubMed

Bartsch, Sebastian T; Lovera, Andrea; Grogg, Daniel; Ionescu, Adrian M

2012-01-24

Nanoelectromechanical systems (NEMS) as integrated components for ultrasensitive sensing, time keeping, or radio frequency applications have driven the search for scalable nanomechanical transduction on-chip. Here, we present a hybrid silicon-on-insulator platform for building NEM oscillators in which fin field effect transistors (FinFETs) are integrated into nanomechanical silicon resonators. We demonstrate transistor amplification and signal mixing, coupled with mechanical motion at very high frequencies (25-80 MHz). By operating the transistor in the subthreshold region, the power consumption of resonators can be reduced to record-low nW levels, opening the way for the parallel operation of hundreds of thousands of NEM oscillators. The electromechanical charge modulation due to the field effect in a resonant transistor body constitutes a scalable nanomechanical motion detection all-on-chip and at room temperature. The new class of tunable NEMS represents a major step toward their integration in resonator arrays for applications in sensing and signal processing. © 2011 American Chemical Society

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation Using Superconducting Tunnel Junctions with Integrated Radio Frequency Single-Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Prober, D. E.; Rhee, K. W.; Schoelkopf, R. J.; Stahle, C. M.; Teufel, J.; Wollack, E. J.

2004-01-01

For high resolution imaging and spectroscopy in the FIR and submillimeter, space observatories will demand sensitive, fast, compact, low-power detector arrays with 104 pixels and sensitivity less than 10(exp -20) W/Hz(sup 0.5). Antenna-coupled superconducting tunnel junctions with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique. The device consists of an antenna to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure current through junctions contacting the absorber. We describe optimization of device parameters, and results on fabrication techniques for producing devices with high yield for detector arrays. We also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

2018-01-01

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

A comprehensive biosensor integrated with a ZnO nanorod FET array for selective detection of glucose, cholesterol and urea.

PubMed

Ahmad, Rafiq; Tripathy, Nirmalya; Park, Jin-Ho; Hahn, Yoon-Bong

2015-08-04

We report a novel straightforward approach for simultaneous and highly-selective detection of multi-analytes (i.e. glucose, cholesterol and urea) using an integrated field-effect transistor (i-FET) array biosensor without any interference in each sensor response. Compared to analytically-measured data, performance of the ZnO nanorod based i-FET array biosensor is found to be highly reliable for rapid detection of multi-analytes in mice blood, and serum and blood samples of diabetic dogs.

High mobility emissive organic semiconductor

PubMed Central

Liu, Jie; Zhang, Hantang; Dong, Huanli; Meng, Lingqiang; Jiang, Longfeng; Jiang, Lang; Wang, Ying; Yu, Junsheng; Sun, Yanming; Hu, Wenping; Heeger, Alan J.

2015-01-01

The integration of high charge carrier mobility and high luminescence in an organic semiconductor is challenging. However, there is need of such materials for organic light-emitting transistors and organic electrically pumped lasers. Here we show a novel organic semiconductor, 2,6-diphenylanthracene (DPA), which exhibits not only high emission with single crystal absolute florescence quantum yield of 41.2% but also high charge carrier mobility with single crystal mobility of 34 cm2 V−1 s−1. Organic light-emitting diodes (OLEDs) based on DPA give pure blue emission with brightness up to 6,627 cd m−2 and turn-on voltage of 2.8 V. 2,6-Diphenylanthracene OLED arrays are successfully driven by DPA field-effect transistor arrays, demonstrating that DPA is a high mobility emissive organic semiconductor with potential in organic optoelectronics. PMID:26620323

1.55 Micrometer Sub-Micron Finger, Interdigitated MSM Photodetector Arrays with Low Dark Current

DTIC Science & Technology

2010-02-02

pf a- IGZO TFTs. IV. RF Characteristics of Room Temperature Deposited Indium Zinc Oxide Thin - Film Transistors Depletion-mode indium zinc...III. High Performance Indium Gallium Zinc Oxide Thin Film Transistors Fabricated On Polyethylene Terephthalate Substrates High-performance...amorphous (a-) InGaZnO-based thin film transistors (TFTs) were fabricated on flexible polyethylene terephthalate (PET) substrates coated with indium

Coulomb blockade based field-effect transistors exploiting stripe-shaped channel geometries of self-assembled metal nanoparticles.

PubMed

Lehmann, Hauke; Willing, Svenja; Möller, Sandra; Volkmann, Mirjam; Klinke, Christian

2016-08-14

Metallic nanoparticles offer possibilities to build basic electric devices with new functionality and improved performance. Due to the small volume and the resulting low self-capacitance, each single nanoparticle exhibits a high charging energy. Thus, a Coulomb-energy gap emerges during transport experiments that can be shifted by electric fields, allowing for charge transport whenever energy levels of neighboring particles match. Hence, the state of the device changes sequentially between conducting and non-conducting instead of just one transition from conducting to pinch-off as in semiconductors. To exploit this behavior for field-effect transistors, it is necessary to use uniform nanoparticles in ordered arrays separated by well-defined tunnel barriers. In this work, CoPt nanoparticles with a narrow size distribution are synthesized by colloidal chemistry. These particles are deposited via the scalable Langmuir-Blodgett technique as ordered, homogeneous monolayers onto Si/SiO2 substrates with pre-patterned gold electrodes. The resulting nanoparticle arrays are limited to stripes of adjustable lengths and widths. In such a defined channel with a limited number of conduction paths the current can be controlled precisely by a gate voltage. Clearly pronounced Coulomb oscillations are observed up to temperatures of 150 K. Using such systems as field-effect transistors yields unprecedented oscillating current modulations with on/off-ratios of around 70%.

Charge Transport in Semiconductor Nanocrystal Solids

NASA Astrophysics Data System (ADS)

Talapin, Dmitri; Shevchenko, Elena; Lee, Jong Soo; Urban, Jeffrey; Mitzi, David; Murray, Christopher

2007-03-01

Self-assembly of chemically-synthesized nanocrystals can yield complex long-range ordered structures which can be used as model systems for studying transport phenomena in low-dimensional materials [1]. Treatment of close-packed PbSe nanocrystal arrays with hydrazine enhanced exchange coupling between the nanocrystals and improved conductance by more than ten orders of magnitude compared to native nanocrystal films [2]. The conductivity of PbSe nanocrystal solids can be switched between n- and p-type transports by controlling the saturation of electronic states at nanocrystal surfaces. Nanocrystal arrays form the n- and p-channels of field-effect transistors with electron and hole mobilities of 2.5 cm^2V-1s-1 and 0.3 cm^2V-1s-1, respectively, and current modulation Ion/Ioff˜10^3-10^4. The field-effect mobility in PbSe nanocrystal arrays is higher than the mobility of organic transistors while the easy switch between n- and p-transport allows realization of complimentary circuits and p-n junctions for nanocrystal-based solar cells and thermoelectric devices. [1] E. V. Shevchenko, D. V. Talapin, N. A. Kotov, S. O'Brien, C. B. Murray. Nature 439, 55 (2006). [2] D. V. Talapin, C. B. Murray. Science 310, 86 (2005).

Fully Solution-Processed Flexible Organic Thin Film Transistor Arrays with High Mobility and Exceptional Uniformity

PubMed Central

Fukuda, Kenjiro; Takeda, Yasunori; Mizukami, Makoto; Kumaki, Daisuke; Tokito, Shizuo

2014-01-01

Printing fully solution-processed organic electronic devices may potentially revolutionize production of flexible electronics for various applications. However, difficulties in forming thin, flat, uniform films through printing techniques have been responsible for poor device performance and low yields. Here, we report on fully solution-processed organic thin-film transistor (TFT) arrays with greatly improved performance and yields, achieved by layering solution-processable materials such as silver nanoparticle inks, organic semiconductors, and insulating polymers on thin plastic films. A treatment layer improves carrier injection between the source/drain electrodes and the semiconducting layer and dramatically reduces contact resistance. Furthermore, an organic semiconductor with large-crystal grains results in TFT devices with shorter channel lengths and higher field-effect mobilities. We obtained mobilities of over 1.2 cm2 V−1 s−1 in TFT devices with channel lengths shorter than 20 μm. By combining these fabrication techniques, we built highly uniform organic TFT arrays with average mobility levels as high as 0.80 cm2 V−1 s−1 and ideal threshold voltages of 0 V. These results represent major progress in the fabrication of fully solution-processed organic TFT device arrays. PMID:24492785

Variability-aware compact modeling and statistical circuit validation on SRAM test array

NASA Astrophysics Data System (ADS)

Qiao, Ying; Spanos, Costas J.

2016-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry's 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Rhee, K. W.; Teufel, J.; Schoelkopf, R. J.

2002-01-01

This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Fabrication of flexible MoS2 thin-film transistor arrays for practical gas-sensing applications.

PubMed

He, Qiyuan; Zeng, Zhiyuan; Yin, Zongyou; Li, Hai; Wu, Shixin; Huang, Xiao; Zhang, Hua

2012-10-08

By combining two kinds of solution-processable two-dimensional materials, a flexible transistor array is fabricated in which MoS(2) thin film is used as the active channel and reduced graphene oxide (rGO) film is used as the drain and source electrodes. The simple device configuration and the 1.5 mm-long MoS(2) channel ensure highly reproducible device fabrication and operation. This flexible transistor array can be used as a highly sensitive gas sensor with excellent reproducibility. Compared to using rGO thin film as the active channel, this new gas sensor exhibits much higher sensitivity. Moreover, functionalization of the MoS(2) thin film with Pt nanoparticles further increases the sensitivity by up to ∼3 times. The successful incorporation of a MoS(2) thin-film into the electronic sensor promises its potential application in various electronic devices. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Impact of the air gap in nanowire array transistors

NASA Astrophysics Data System (ADS)

Mativetsky, Jeffrey; Yang, Tong; Mehta, Jeremy

Organic and inorganic semiconducting nanowires are promising for flexible electronic, energy harvesting, and sensing applications. Nanowire arrays processed from solution are particularly attractive for their ease of processing coupled with their potential for high performance. Random stacking has been observed, however, to hinder the collective electrical performance of such nanowire arrays. Here, we employ solution-processed organic semiconducting nanowires as a model system to assess the impact of the air gap that exists under a large portion of the active material in nanowire array transistors. Confocal Raman spectroscopy is used to non-invasively quantify the average air gap thickness which is found to be unexpectedly large - two to three times the nanowire diameter. This substantial air gap acts as an additional dielectric layer that diminishes the buildup of charge carriers, and can affect the measured charge carrier mobility and current on/off ratio by more than one order of magnitude. These results establish the importance of taking the air gap into account when fabricating and analyzing the performance of transistors based on one-dimensional nanostructures, such as organic and inorganic nanowires, or carbon nanotubes. NSF CAREER award DMR-1555028, NSF CMMI-1537648 , NSF MRI CMMI-1429176.

Design, optimization and evaluation of a "smart" pixel sensor array for low-dose digital radiography

NASA Astrophysics Data System (ADS)

Wang, Kai; Liu, Xinghui; Ou, Hai; Chen, Jun

2016-04-01

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) have been widely used to build flat-panel X-ray detectors for digital radiography (DR). As the demand for low-dose X-ray imaging grows, a detector with high signal-to-noise-ratio (SNR) pixel architecture emerges. "Smart" pixel is intended to use a dual-gate photosensitive TFT for sensing, storage, and switch. It differs from a conventional passive pixel sensor (PPS) and active pixel sensor (APS) in that all these three functions are combined into one device instead of three separate units in a pixel. Thus, it is expected to have high fill factor and high spatial resolution. In addition, it utilizes the amplification effect of the dual-gate photosensitive TFT to form a one-transistor APS that leads to a potentially high SNR. This paper addresses the design, optimization and evaluation of the smart pixel sensor and array for low-dose DR. We will design and optimize the smart pixel from the scintillator to TFT levels and validate it through optical and electrical simulation and experiments of a 4x4 sensor array.

Joint Services Electronics Program.

DTIC Science & Technology

1987-12-31

and annealing, using deep level transient spectroscopy (DLTS), and the effects of co-implantation on 4l the activation of amphoteric dopants and...theriithe study of optical quantum effects with emphasis on nonlinear optical phenomena. For example, a significant accomplishment write-up describes...Millimeter-Wave Array Components Tatsuo Itoh A number of novel solid state devices such as metal semiconductor field effect transistors (MESFET

On the current drive capability of low dimensional semiconductors: 1D versus 2D

DOE PAGES

Zhu, Y.; Appenzeller, J.

2015-10-29

Low-dimensional electronic systems are at the heart of many scaling approaches currently pursuit for electronic applications. Here, we present a comparative study between an array of one-dimensional (1D) channels and its two-dimensional (2D) counterpart in terms of current drive capability. Lastly, our findings from analytical expressions derived in this article reveal that under certain conditions an array of 1D channels can outperform a 2D field-effect transistor because of the added degree of freedom to adjust the threshold voltage in an array of 1D devices.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Wide-bandwidth high-resolution search for extraterrestrial intelligence

NASA Technical Reports Server (NTRS)

Horowitz, Paul

1993-01-01

Research accomplished during the third 6-month period is summarized. Research covered the following: dual-horn antenna performance; high electron mobility transistors (HEMT) low-noise amplifiers; downconverters; fast Fourier transform (FFT) array; and backend 'feature recognizer' array.

Carbon nanotube transistors scaled to a 40-nanometer footprint.

PubMed

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Pentacene-based organic thin film transistors, integrated circuits, and active matrix displays on polymeric substrates

NASA Astrophysics Data System (ADS)

Sheraw, Christopher Duncan

2003-10-01

Organic thin film transistors are attractive candidates for a variety of low cost, large area commercial electronics including smart cards, RF identification tags, and flat panel displays. Of particular interest are high performance organic thin film transistors (TFTs) that can be fabricated on flexible polymeric substrates allowing low-cost, lightweight, rugged electronics such as flexible active matrix displays. This thesis reports pentacene organic thin film transistors fabricated on flexible polymeric substrates with record performance, the fastest photolithographically patterned organic TFT integrated circuits on polymeric substrates reported to date, and the fabrication of the organic TFT backplanes used to build the first organic TFT-driven active matrix liquid crystal display (AMLCD), also the first AMLCD on a flexible substrate, ever reported. In addition, the first investigation of functionalized pentacene derivatives used as the active layer in organic thin film transistors is reported. A low temperature (<110°C) process technology was developed allowing the fabrication of high performance organic TFTs, integrated circuits, and large TFT arrays on flexible polymeric substrates. This process includes the development of a novel water-based photolithographic active layer patterning process using polyvinyl alcohol that allows the patterning of organic semiconductor materials for elimination of active layer leakage current without causing device degradation. The small molecule aromatic hydrocarbon pentacene was used as the active layer material to fabricate organic TFTs on the polymeric material polyethylene naphthalate with field-effect mobility as large as 2.1 cm2/V-s and on/off current ratio of 108. These are the best values reported for organic TFTs on polymeric substrates and comparable to organic TFTs on rigid substrates. Analog and digital integrated circuits were also fabricated on polymeric substrates using pentacene TFTs with propagation delay as low as 38 musec and clocked digital circuits that operated at 1.1 kHz. These are the fastest photolithographically patterned organic TFT circuits on polymeric substrates reported to date. Finally, 16 x 16 pentacene TFT pixel arrays were fabricated on polymeric substrates and integrated with polymer dispersed liquid crystal to build an AMLCD. The pixel arrays showed good optical response to changing data signals when standard quarter-VGA display waveforms were applied. This result marks the first organic TFT-driven active matrix liquid crystal display ever reported as well as the first active matrix liquid crystal display on a flexible polymeric substrate. Lastly, functionalized pentacene derivatives were used as the active layer in organic thin film transistor materials. Functional groups were added to the pentacene molecule to influence the molecular ordering so that the amount of pi-orbital overlap would be increased allowing the potential for improved field-effect mobility. The functionalization of these materials also improves solubility allowing for the possibility of solution-processed devices and increased oxidative stability. Organic thin film transistors were fabricated using five different functionalized pentacene active layers. Devices based on the pentacene derivative triisopropylsilyl pentacene were found to have the best performance with field-effect mobility as large as 0.4 cm 2/V-s.

Growth of nanotubes and chemical sensor applications

NASA Astrophysics Data System (ADS)

Hone, James; Kim, Philip; Huang, X. M. H.; Chandra, B.; Caldwell, R.; Small, J.; Hong, B. H.; Someya, T.; Huang, L.; O'Brien, S.; Nuckolls, Colin P.

2004-12-01

We have used a number of methods to grow long aligned single-walled carbon nanotubes. Geometries include individual long tubes, dense parallel arrays, and long freely suspended nanotubes. We have fabricated a variety of devices for applications such as multiprobe resistance measurement and high-current field effect transistors. In addition, we have measured conductance of single-walled semiconducting carbon nanotubes in field-effect transistor geometry and investigated the device response to water and alcoholic vapors. We observe significant changes in FET drain current when the device is exposed to various kinds of different solvent. These responses are reversible and reproducible over many cycles of vapor exposure. Our experiments demonstrate that carbon nanotube FETs are sensitive to a wide range of solvent vapors at concentrations in the ppm range.

Channel length scaling behavior in transistors based on individual versus dense arrays of carbon nanotubes

NASA Astrophysics Data System (ADS)

Brady, Gerald J.; Jinkins, Katherine R.; Arnold, Michael S.

2017-09-01

Recent advances in the solution-phase sorting and assembly of semiconducting single-walled carbon nanotubes (SWCNTs) have enabled significant gains in the performance of field-effect transistors (FETs) constructed from dense arrays of aligned SWCNTs. However, the channel length (LCH) downscaling behaviors of these arrays, which contain some organizational disorder (i.e., rotational misalignment and non-uniform pitch), have not yet been studied in detail below LCH of 100 nm. This study compares the behaviors of individualized SWCNTs with arrays of aligned, solution-cast SWCNTs in FETs with LCH ranging from 30 to 240 nm. The on-state conductance of both individual and array SWCNTs rises with decreasing LCH. Nearly ballistic transport is observed for LCH < 40 nm in both cases, reaching a conductance of 0.82 Go per SWCNT in arrays, where Go = 2e2/h is the quantum conductance. In the off-state, the off-current and subthreshold swing of the individual SWCNTs remain nearly invariant with decreasing LCH whereas array SWCNT FETs suffer from increasing off-state current and deteriorating subthreshold swing for LCH below 100 nm. We analyze array disorder using atomic force microscopy, which shows that crossing SWCNTs that arise from misoriented alignment raise SWCNTs off of the substrate for large portions of the channel when LCH is small. Electrostatics modeling analysis indicates that these raised SWCNTs are a likely contributor to the deteriorating off-current and subthreshold characteristics of arrays. These results demonstrate that improved inter-SWCNT pitch uniformity and alignment with minimal inter-SWCNT interactions will be necessary in order for solution processed SWCNT arrays to reach subthreshold performance on par with isolated SWCNTs. These results are also promising because they show that arrays of solution-processed SWCNTs can nearly reach ballistic conductance in the on-state despite imperfections in pitch and alignment.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

NASA Astrophysics Data System (ADS)

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min-1), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 105, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm2 V-1 s-1. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing.

PubMed

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-13

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min(-1)), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10(5), a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm(2) V(-1) s(-1). The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

NASA Astrophysics Data System (ADS)

Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Design of hybrid two-dimensional and three-dimensional nanostructured arrays for electronic and sensing applications

NASA Astrophysics Data System (ADS)

Ko, Hyunhyub

This dissertation presents the design of organic/inorganic hybrid 2D and 3D nanostructured arrays via controlled assembly of nanoscale building blocks. Two representative nanoscale building blocks such as carbon nanotubes (one-dimension) and metal nanoparticles (zero-dimension) are the core materials for the study of solution-based assembly of nanostructured arrays. The electrical, mechanical, and optical properties of the assembled nanostructure arrays have been investigated for future device applications. We successfully demonstrated the prospective use of assembled nanostructure arrays for electronic and sensing applications by designing flexible carbon nanotube nanomembranes as mechanical sensors, highly-oriented carbon nanotubes arrays for thin-film transistors, and gold nanoparticle arrays for SERS chemical sensors. In first section, we fabricated highly ordered carbon nanotube (CNT) arrays by tilted drop-casting or dip-coating of CNT solution on silicon substrates functionalized with micropatterned self-assembled monolayers. We further exploited the electronic performance of thin-film transistors based on highly-oriented, densely packed CNT micropatterns and showed that the carrier mobility is largely improved compared to randomly oriented CNTs. The prospective use of Raman-active CNTs for potential mechanical sensors has been investigated by studying the mechano-optical properties of flexible carbon nanotube nanomembranes, which contain freely-suspended carbon nanotube array encapsulated into ultrathin (<50 nm) layer-by-layer (LbL) polymer multilayers. In second section, we fabricated 3D nano-canal arrays of porous alumina membranes decorated with gold nanoparticles for prospective SERS sensors. We showed extraordinary SERS enhancement and suggested that the high performance is associated with the combined effects of Raman-active hot spots of nanoparticle aggregates and the optical waveguide properties of nano-canals. We demonstrated the ability of this SERS substrate for trace level sensing of nitroaromatic explosives by detecting down to 100 zeptogram (˜330 molecules) of DNT.

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fringing-field dielectrophoretic assembly of ultrahigh-density semiconducting nanotube arrays with a self-limited pitch

NASA Astrophysics Data System (ADS)

Cao, Qing; Han, Shu-Jen; Tulevski, George S.

2014-09-01

One key challenge of realizing practical high-performance electronic devices based on single-walled carbon nanotubes is to produce electronically pure nanotube arrays with both a minuscule and uniform inter-tube pitch for sufficient device-packing density and homogeneity. Here we develop a method in which the alternating voltage-fringing electric field formed between surface microelectrodes and the substrate is utilized to assemble semiconducting nanotubes into well-aligned, ultrahigh-density and submonolayered arrays, with a consistent pitch as small as 21±6 nm determined by a self-limiting mechanism, based on the unique field focusing and screening effects of the fringing field. Field-effect transistors based on such nanotube arrays exhibit record high device transconductance (>50 μS μm-1) and decent on current per nanotube (~1 μA per tube) together with high on/off ratios at a drain bias of -1 V.

Initial steps toward the realization of large area arrays of single photon counting pixels based on polycrystalline silicon TFTs

NASA Astrophysics Data System (ADS)

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Jiang, Hao; Street, Robert A.; Lu, Jeng Ping

2014-03-01

The thin-film semiconductor processing methods that enabled creation of inexpensive liquid crystal displays based on amorphous silicon transistors for cell phones and televisions, as well as desktop, laptop and mobile computers, also facilitated the development of devices that have become ubiquitous in medical x-ray imaging environments. These devices, called active matrix flat-panel imagers (AMFPIs), measure the integrated signal generated by incident X rays and offer detection areas as large as ~43×43 cm2. In recent years, there has been growing interest in medical x-ray imagers that record information from X ray photons on an individual basis. However, such photon counting devices have generally been based on crystalline silicon, a material not inherently suited to the cost-effective manufacture of monolithic devices of a size comparable to that of AMFPIs. Motivated by these considerations, we have developed an initial set of small area prototype arrays using thin-film processing methods and polycrystalline silicon transistors. These prototypes were developed in the spirit of exploring the possibility of creating large area arrays offering single photon counting capabilities and, to our knowledge, are the first photon counting arrays fabricated using thin film techniques. In this paper, the architecture of the prototype pixels is presented and considerations that influenced the design of the pixel circuits, including amplifier noise, TFT performance variations, and minimum feature size, are discussed.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms.

PubMed

Pruttivarasin, Thaned; Katori, Hidetoshi

2015-11-01

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Aguirre, Arturo Hernandez; Zebulum, Ricardo S.; Coello, Carlos Coello

2004-01-01

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp; Katori, Hidetoshi; Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Microstructural control over soluble pentacene deposited by capillary pen printing for organic electronics.

PubMed

Lee, Wi Hyoung; Min, Honggi; Park, Namwoo; Lee, Junghwi; Seo, Eunsuk; Kang, Boseok; Cho, Kilwon; Lee, Hwa Sung

2013-08-28

Research into printing techniques has received special attention for the commercialization of cost-efficient organic electronics. Here, we have developed a capillary pen printing technique to realize a large-area pattern array of organic transistors and systematically investigated self-organization behavior of printed soluble organic semiconductor ink. The capillary pen-printed deposits of organic semiconductor, 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS_PEN), was well-optimized in terms of morphological and microstructural properties by using ink with mixed solvents of chlorobenzene (CB) and 1,2-dichlorobenzene (DCB). Especially, a 1:1 solvent ratio results in the best transistor performances. This result is attributed to the unique evaporation characteristics of the TIPS_PEN deposits where fast evaporation of CB induces a morphological evolution at the initial printed position, and the remaining DCB with slow evaporation rate offers a favorable crystal evolution at the pinned position. Finally, a large-area transistor array was facilely fabricated by drawing organic electrodes and active layers with a versatile capillary pen. Our approach provides an efficient printing technique for fabricating large-area arrays of organic electronics and further suggests a methodology to enhance their performances by microstructural control of the printed organic semiconducting deposits.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization.

PubMed

Tran, Duy Phu; Pham, Thuy Thi Thanh; Wolfrum, Bernhard; Offenhäusser, Andreas; Thierry, Benjamin

2018-05-11

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs' promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Anisotropic stress in narrow sGe fin field-effect transistor channels measured using nano-focused Raman spectroscopy

NASA Astrophysics Data System (ADS)

Nuytten, T.; Bogdanowicz, J.; Witters, L.; Eneman, G.; Hantschel, T.; Schulze, A.; Favia, P.; Bender, H.; De Wolf, I.; Vandervorst, W.

2018-05-01

The continued importance of strain engineering in semiconductor technology demands fast and reliable stress metrology that is non-destructive and process line-compatible. Raman spectroscopy meets these requirements but the diffraction limit prevents its application in current and future technology nodes. We show that nano-focused Raman scattering overcomes these limitations and can be combined with oil-immersion to obtain quantitative anisotropic stress measurements. We demonstrate accurate stress characterization in strained Ge fin field-effect transistor channels without sample preparation or advanced microscopy. The detailed analysis of the enhanced Raman response from a periodic array of 20 nm-wide Ge fins provides direct access to the stress levels inside the nanoscale channel, and the results are validated using nano-beam diffraction measurements.

Biofunctionalized Zinc Oxide Field Effect Transistors for Selective Sensing of Riboflavin with Current Modulation

PubMed Central

Hagen, Joshua A.; Kim, Sang N.; Bayraktaroglu, Burhan; Leedy, Kevin; Chávez, Jorge L.; Kelley-Loughnane, Nancy; Naik, Rajesh R.; Stone, Morley O.

2011-01-01

Zinc oxide field effect transistors (ZnO-FET), covalently functionalized with single stranded DNA aptamers, provide a highly selective platform for label-free small molecule sensing. The nanostructured surface morphology of ZnO provides high sensitivity and room temperature deposition allows for a wide array of substrate types. Herein we demonstrate the selective detection of riboflavin down to the pM level in aqueous solution using the negative electrical current response of the ZnO-FET by covalently attaching a riboflavin binding aptamer to the surface. The response of the biofunctionalized ZnO-FET was tuned by attaching a redox tag (ferrocene) to the 3′ terminus of the aptamer, resulting in positive current modulation upon exposure to riboflavin down to pM levels. PMID:22163977

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Nanoscale thermocapillarity enabled purification for horizontally aligned arrays of single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Jin, Sung Hun; Dunham, Simon; Xie, Xu; Rogers, John A.

2015-09-01

Among the remarkable variety of semiconducting nanomaterials that have been discovered over the past two decades, single-walled carbon nanotubes remain uniquely well suited for applications in high-performance electronics, sensors and other technologies. The most advanced opportunities demand the ability to form perfectly aligned, horizontal arrays of purely semiconducting, chemically pristine carbon nanotubes. Here, we present strategies that offer this capability. Nanoscale thermos-capillary flows in thin-film organic coatings followed by reactive ion etching serve as highly efficient means for selectively removing metallic carbon nanotubes from electronically heterogeneous aligned arrays grown on quartz substrates. The low temperatures and unusual physics associated with this process enable robust, scalable operation, with clear potential for practical use. Especially for the purpose of selective joule heating over only metallic nanotubes, two representative platforms are proposed and confirmed. One is achieved by selective joule heating associated with thin film transistors with partial gate structure. The other is based on a simple, scalable, large-area scheme through microwave irradiation by using micro-strip dipole antennas of low work-function metals. In this study, based on purified semiconducting SWNTs, we demonstrated field effect transistors with mobility (> 1,000 cm2/Vsec) and on/off switching ratio (~10,000) with current outputs in the milliamp range. Furthermore, as one demonstration of the effectiveness over large area-scalability and simplicity, implementing the micro-wave based purification, on large arrays consisting of ~20,000 SWNTs completely removes all of the m-SWNTs (~7,000) to yield a purity of s-SWNTs that corresponds, quantitatively, to at least to 99.9925% and likely significantly higher.

Integrated arrays of air-dielectric graphene transistors as transparent active-matrix pressure sensors for wide pressure ranges.

PubMed

Shin, Sung-Ho; Ji, Sangyoon; Choi, Seiho; Pyo, Kyoung-Hee; Wan An, Byeong; Park, Jihun; Kim, Joohee; Kim, Ju-Young; Lee, Ki-Suk; Kwon, Soon-Yong; Heo, Jaeyeong; Park, Byong-Guk; Park, Jang-Ung

2017-03-31

Integrated electronic circuitries with pressure sensors have been extensively researched as a key component for emerging electronics applications such as electronic skins and health-monitoring devices. Although existing pressure sensors display high sensitivities, they can only be used for specific purposes due to the narrow range of detectable pressure (under tens of kPa) and the difficulty of forming highly integrated arrays. However, it is essential to develop tactile pressure sensors with a wide pressure range in order to use them for diverse application areas including medical diagnosis, robotics or automotive electronics. Here we report an unconventional approach for fabricating fully integrated active-matrix arrays of pressure-sensitive graphene transistors with air-dielectric layers simply formed by folding two opposing panels. Furthermore, this realizes a wide tactile pressure sensing range from 250 Pa to ∼3 MPa. Additionally, fabrication of pressure sensor arrays and transparent pressure sensors are demonstrated, suggesting their substantial promise as next-generation electronics.

Integrated arrays of air-dielectric graphene transistors as transparent active-matrix pressure sensors for wide pressure ranges

NASA Astrophysics Data System (ADS)

Shin, Sung-Ho; Ji, Sangyoon; Choi, Seiho; Pyo, Kyoung-Hee; Wan An, Byeong; Park, Jihun; Kim, Joohee; Kim, Ju-Young; Lee, Ki-Suk; Kwon, Soon-Yong; Heo, Jaeyeong; Park, Byong-Guk; Park, Jang-Ung

2017-03-01

Integrated electronic circuitries with pressure sensors have been extensively researched as a key component for emerging electronics applications such as electronic skins and health-monitoring devices. Although existing pressure sensors display high sensitivities, they can only be used for specific purposes due to the narrow range of detectable pressure (under tens of kPa) and the difficulty of forming highly integrated arrays. However, it is essential to develop tactile pressure sensors with a wide pressure range in order to use them for diverse application areas including medical diagnosis, robotics or automotive electronics. Here we report an unconventional approach for fabricating fully integrated active-matrix arrays of pressure-sensitive graphene transistors with air-dielectric layers simply formed by folding two opposing panels. Furthermore, this realizes a wide tactile pressure sensing range from 250 Pa to ~3 MPa. Additionally, fabrication of pressure sensor arrays and transparent pressure sensors are demonstrated, suggesting their substantial promise as next-generation electronics.

Integrated arrays of air-dielectric graphene transistors as transparent active-matrix pressure sensors for wide pressure ranges

PubMed Central

Shin, Sung-Ho; Ji, Sangyoon; Choi, Seiho; Pyo, Kyoung-Hee; Wan An, Byeong; Park, Jihun; Kim, Joohee; Kim, Ju-Young; Lee, Ki-Suk; Kwon, Soon-Yong; Heo, Jaeyeong; Park, Byong-Guk; Park, Jang-Ung

2017-01-01

Integrated electronic circuitries with pressure sensors have been extensively researched as a key component for emerging electronics applications such as electronic skins and health-monitoring devices. Although existing pressure sensors display high sensitivities, they can only be used for specific purposes due to the narrow range of detectable pressure (under tens of kPa) and the difficulty of forming highly integrated arrays. However, it is essential to develop tactile pressure sensors with a wide pressure range in order to use them for diverse application areas including medical diagnosis, robotics or automotive electronics. Here we report an unconventional approach for fabricating fully integrated active-matrix arrays of pressure-sensitive graphene transistors with air-dielectric layers simply formed by folding two opposing panels. Furthermore, this realizes a wide tactile pressure sensing range from 250 Pa to ∼3 MPa. Additionally, fabrication of pressure sensor arrays and transparent pressure sensors are demonstrated, suggesting their substantial promise as next-generation electronics. PMID:28361867

Atomically engineered epitaxial anatase TiO2 metal-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki; Bell, Christopher; Hwang, Harold Y.

2018-03-01

Anatase TiO2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO2 and LaAlO3 (001), which arises for LaO-terminated LaAlO3, while the AlO2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a high field-effect mobility μ FE of 3.14 cm2 (V s)-1 approaching 98% of the corresponding Hall mobility μ Hall . Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ˜4 V.

Solid state image sensing arrays

NASA Technical Reports Server (NTRS)

Sadasiv, G.

1972-01-01

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Silicon junctionless field effect transistors as room temperature terahertz detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marczewski, J., E-mail: jmarcz@ite.waw.pl; Tomaszewski, D.; Zaborowski, M.

2015-09-14

Terahertz (THz) radiation detection by junctionless metal-oxide-semiconductor field-effect transistors (JL MOSFETs) was studied and compared with THz detection using conventional MOSFETs. It has been shown that in contrast to the behavior of standard transistors, the junctionless devices have a significant responsivity also in the open channel (low resistance) state. The responsivity for a photolithographically defined JL FET was 70 V/W and the noise equivalent power 460 pW/√Hz. Working in the open channel state may be advantageous for THz wireless and imaging applications because of its low thermal noise and possible high operating speed or large bandwidth. It has been proven that themore » junctionless MOSFETs can also operate in a zero gate bias mode, which enables simplification of the THz array circuitry. Existing models of THz detection by MOSFETs were considered and it has been demonstrated that the process of detection by these junctionless devices cannot be explained within the framework of the commonly accepted models and therefore requires a new theoretical approach.« less

Particle sensor array

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Lieneweg, Udo (Inventor)

1994-01-01

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

GaAs optoelectronic neuron arrays

NASA Technical Reports Server (NTRS)

Lin, Steven; Grot, Annette; Luo, Jiafu; Psaltis, Demetri

1993-01-01

A simple optoelectronic circuit integrated monolithically in GaAs to implement sigmoidal neuron responses is presented. The circuit integrates a light-emitting diode with one or two transistors and one or two photodetectors. The design considerations for building arrays with densities of up to 10,000/sq cm are discussed.

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

PubMed Central

Brady, Gerald J.; Way, Austin J.; Safron, Nathaniel S.; Evensen, Harold T.; Gopalan, Padma; Arnold, Michael S.

2016-01-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies. PMID:27617293

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs.

PubMed

Brady, Gerald J; Way, Austin J; Safron, Nathaniel S; Evensen, Harold T; Gopalan, Padma; Arnold, Michael S

2016-09-01

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

Gigahertz Electromagnetic Structures via Direct Ink Writing for Radio-Frequency Oscillator and Transmitter Applications.

PubMed

Zhou, Nanjia; Liu, Chengye; Lewis, Jennifer A; Ham, Donhee

2017-04-01

Radio-frequency (RF) electronics, which combine passive electromagnetic devices and active transistors to generate and process gigahertz (GHz) signals, provide a critical basis of ever-pervasive wireless networks. While transistors are best realized by top-down fabrication, relatively larger electromagnetic passives are within the reach of printing techniques. Here, direct writing of viscoelastic silver-nanoparticle inks is used to produce a broad array of RF passives operating up to 45 GHz. These include lumped devices such as inductors and capacitors, and wave-based devices such as transmission lines, their resonant networks, and antennas. Moreover, to demonstrate the utility of these printed RF passive structures in active RF electronic circuits, they are combined with discrete transistors to fabricate GHz self-sustained oscillators and synchronized oscillator arrays that provide RF references, and wireless transmitters clocked by the oscillators. This work demonstrates the synergy of direct ink writing and RF electronics for wireless applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transparent, conformable, active multielectrode array using organic electrochemical transistors.

PubMed

Lee, Wonryung; Kim, Dongmin; Matsuhisa, Naoji; Nagase, Masae; Sekino, Masaki; Malliaras, George G; Yokota, Tomoyuki; Someya, Takao

2017-10-03

Mechanically flexible active multielectrode arrays (MEA) have been developed for local signal amplification and high spatial resolution. However, their opaqueness limited optical observation and light stimulation during use. Here, we show a transparent, ultraflexible, and active MEA, which consists of transparent organic electrochemical transistors (OECTs) and transparent Au grid wirings. The transparent OECT is made of Au grid electrodes and has shown comparable performance with OECTs with nontransparent electrodes/wirings. The transparent active MEA realizes the spatial mapping of electrocorticogram electrical signals from an optogenetic rat with 1-mm spacing and shows lower light artifacts than noise level. Our active MEA would open up the possibility of precise investigation of a neural network system with direct light stimulation.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications.

PubMed

Merced-Grafals, Emmanuelle J; Dávila, Noraica; Ge, Ning; Williams, R Stanley; Strachan, John Paul

2016-09-09

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10(6) cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.

Backside contacted field effect transistor array for extracellular signal recording.

PubMed

Ingebrandt, S; Yeung, C K; Staab, W; Zetterer, T; Offenhäusser, A

2003-04-01

A new approach to the design of field-effect transistor (FET) sensors and the use of these FETs in detecting extracellular electrophysiological recordings is reported. Backside contacts were engineered by deep reactive ion etching and a gas phase boron doping process of the holes using planar diffusion sources. The metal contacts were designed to fit on top of the bonding pads of a standard industrial 22-pin DIL (dual inline) chip carrier. To minimise contact resistance, the metal backside contacts of the chips were electroless plated with gold. The chips were mounted on top of the bonding pads using a standard flip-chip process and a fineplacer unit previously described. Rat embryonic myocytes were cultured on these new devices (effective growth area 6 x 6 mm(2)) in order to confirm their validity in electrophysiological recording. Copyright 2003 Elsevier Science B.V.

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

PubMed Central

Wolfrum, Bernhard; Thierry, Benjamin

2018-01-01

Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs’ promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology. PMID:29751688

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

NASA Astrophysics Data System (ADS)

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J.; Janes, David B.

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including `see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In2O3 and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with ~82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics.

PubMed

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J; Janes, David B

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Synthesis of monolithic graphene – graphite integrated electronics

PubMed Central

Park, Jang-Ung; Nam, SungWoo; Lee, Mi-Sun; Lieber, Charles M.

2013-01-01

Encoding electronic functionality into nanoscale elements during chemical synthesis has been extensively explored over the past decade as the key to developing integrated nanosystems1 with functions defined by synthesis2-6. Graphene7-12 has been recently explored as a two-dimensional nanoscale material, and has demonstrated simple device functions based on conventional top-down fabrication13-20. However, the synthetic approach to encoding electronic functionality and thus enabling an entire integrated graphene electronics in a chemical synthesis had not previously been demonstrated. Here we report an unconventional approach for the synthesis of monolithically-integrated electronic devices based on graphene and graphite. Spatial patterning of heterogeneous catalyst metals permits the selective growth of graphene and graphite, with controlled number of graphene layers. Graphene transistor arrays with graphitic electrodes and interconnects were formed from synthesis. These functional, all-carbon structures were transferrable onto a variety of substrates. The integrated transistor arrays were used to demonstrate real-time, multiplexed chemical sensing, and more significantly, multiple carbon layers of the graphene-graphite device components were vertically assembled to form a three-dimensional flexible structure which served as a top-gate transistor array. These results represent a substantial progress towards encoding electronic functionality via chemical synthesis and suggest future promise for one-step integration of graphene-graphite based electronics. PMID:22101813

Synthesis of monolithic graphene-graphite integrated electronics.

PubMed

Park, Jang-Ung; Nam, SungWoo; Lee, Mi-Sun; Lieber, Charles M

2011-11-20

Encoding electronic functionality into nanoscale elements during chemical synthesis has been extensively explored over the past decade as the key to developing integrated nanosystems with functions defined by synthesis. Graphene has been recently explored as a two-dimensional nanoscale material, and has demonstrated simple device functions based on conventional top-down fabrication. However, the synthetic approach to encoding electronic functionality and thus enabling an entire integrated graphene electronics in a chemical synthesis had not previously been demonstrated. Here we report an unconventional approach for the synthesis of monolithically integrated electronic devices based on graphene and graphite. Spatial patterning of heterogeneous metal catalysts permits the selective growth of graphene and graphite, with a controlled number of graphene layers. Graphene transistor arrays with graphitic electrodes and interconnects were formed from the synthesis. These functional, all-carbon structures were transferable onto a variety of substrates. The integrated transistor arrays were used to demonstrate real-time, multiplexed chemical sensing and more significantly, multiple carbon layers of the graphene-graphite device components were vertically assembled to form a three-dimensional flexible structure which served as a top-gate transistor array. These results represent substantial progress towards encoding electronic functionality through chemical synthesis and suggest the future promise of one-step integration of graphene-graphite based electronics.

Highly flexible electronics from scalable vertical thin film transistors.

PubMed

Liu, Yuan; Zhou, Hailong; Cheng, Rui; Yu, Woojong; Huang, Yu; Duan, Xiangfeng

2014-03-12

Flexible thin-film transistors (TFTs) are of central importance for diverse electronic and particularly macroelectronic applications. The current TFTs using organic or inorganic thin film semiconductors are usually limited by either poor electrical performance or insufficient mechanical flexibility. Here, we report a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 10(5). The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. With large area graphene and IGZO thin film available, our strategy is intrinsically scalable for large scale integration of VTFT arrays and logic circuits, opening up a new pathway to highly flexible macroelectronics.

A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

PubMed Central

Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

2012-01-01

Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography.

PubMed

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-01-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

NASA Astrophysics Data System (ADS)

Knoll, L.; Richter, S.; Nichau, A.; Trellenkamp, S.; Schäfer, A.; Wirths, S.; Blaeser, S.; Buca, D.; Bourdelle, K. K.; Zhao, Q.-T.; Mantl, S.

2014-08-01

Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78 μA/μm at VD = VG = 1.1 V is obtained.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

NASA Astrophysics Data System (ADS)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization

NASA Astrophysics Data System (ADS)

Tsai, Chun-Chien; Lee, Yao-Jen; Chiang, Ko-Yu; Wang, Jyh-Liang; Lee, I.-Che; Chen, Hsu-Hsin; Wei, Kai-Fang; Chang, Ting-Kuo; Chen, Bo-Ting; Cheng, Huang-Chung

2007-11-01

In this paper, location-controlled silicon crystal grains are fabricated by the excimer laser crystallization method which employs amorphous silicon spacer structure and prepatterned thin films. The amorphous silicon spacer in nanometer-sized width formed using spacer technology is served as seed crystal to artificially control superlateral growth phenomenon during excimer laser irradiation. An array of 1.8-μm-sized disklike silicon grains is formed, and the n-channel thin-film transistors whose channels located inside the artificially-controlled crystal grains exhibit higher performance of field-effect-mobility reaching 308cm2/Vs as compared with the conventional ones. This position-manipulated silicon grains are essential to high-performance and good uniformity devices.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Arc-Free High-Power dc Switch

NASA Technical Reports Server (NTRS)

Miller, W. N.; Gray, O. E.

1982-01-01

Hybrid switch allows high-power direct current to be turned on and off without arcing or erosion. Switch consists of bank of transistors in parallel with mechanical contacts. Transistor bank makes and breaks switched circuit; contacts carry current only during steady-state "on" condition. Designed for Space Shuttle orbiter, hybrid switch can be used also in high-power control circuits in aircraft, electric autos, industrial furnaces, and solar-cell arrays.

Direct Fabrication of a-Si:H Thin Film Transistor Arrays on Plastic and Metal Foils for Flexible Displays

DTIC Science & Technology

2008-12-01

TFTs ) arrays for high information content active matrix flexible displays for Army applications. For all flexible substrates a manufacturable...impermeable flexible substrate systems “display-ready” materials and handling protocols, (ii) high performance TFT devices and circuits fabricated...processes for integration with the flexible TFT arrays. Approaches and solution to address each of these major challenges are described in the

Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

NASA Astrophysics Data System (ADS)

Ogasawara, Ryosuke; Endoh, Tetsuo

2018-04-01

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Around Marshall

NASA Image and Video Library

1983-08-10

One of the main components of the Hubble Space Telescope (HST) is the Solar Array Drive Electronics (SADE) system. This system interfaces with the Support System Module (SSM) for exchange of operational commands and telemetry data. SADE operates and controls the Solar Array Drive Mechanisms (SADM) for the orientation of the Solar Array Drive (SAD). It also monitors the position of the arrays and the temperature of the SADM. During the first HST servicing mission, the astronauts replaced the SADE component because of some malfunctions. This turned out to be a very challenging extravehicular activity (EVA). Two transistors and two diodes had been thermally stressed with the conformal coating discolored and charred. Soldered cornections became molten and reflowed between the two diodes. The failed transistors gave no indication of defective construction. All repairs were made and the HST was redeposited into orbit. Prior to undertaking this challenging mission, the orbiter's crew trained at Marshall Space Flight Center's (MSFC) Neutral Buoyancy Simulator (NBS) to prepare themselves for working in a low gravity environment. They also practiced replacing HST parts and exercised maneuverability and equipment handling. Pictured are crew members practicing on a space platform.

Thermal Molding of Organic Thin-Film Transistor Arrays on Curved Surfaces.

PubMed

Sakai, Masatoshi; Watanabe, Kento; Ishimine, Hiroto; Okada, Yugo; Yamauchi, Hiroshi; Sadamitsu, Yuichi; Kudo, Kazuhiro

2017-12-01

In this work, a thermal molding technique is proposed for the fabrication of plastic electronics on curved surfaces, enabling the preparation of plastic films with freely designed shapes. The induced strain distribution observed in poly(ethylene naphthalate) films when planar sheets were deformed into hemispherical surfaces clearly indicated that natural thermal contraction played an important role in the formation of the curved surface. A fingertip-shaped organic thin-film transistor array molded from a real human finger was fabricated, and slight deformation induced by touching an object was detected from the drain current response. This type of device will lead to the development of robot fingers equipped with a sensitive tactile sense for precision work such as palpation or surgery.

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Thermal Molding of Organic Thin-Film Transistor Arrays on Curved Surfaces

NASA Astrophysics Data System (ADS)

Sakai, Masatoshi; Watanabe, Kento; Ishimine, Hiroto; Okada, Yugo; Yamauchi, Hiroshi; Sadamitsu, Yuichi; Kudo, Kazuhiro

2017-05-01

In this work, a thermal molding technique is proposed for the fabrication of plastic electronics on curved surfaces, enabling the preparation of plastic films with freely designed shapes. The induced strain distribution observed in poly(ethylene naphthalate) films when planar sheets were deformed into hemispherical surfaces clearly indicated that natural thermal contraction played an important role in the formation of the curved surface. A fingertip-shaped organic thin-film transistor array molded from a real human finger was fabricated, and slight deformation induced by touching an object was detected from the drain current response. This type of device will lead to the development of robot fingers equipped with a sensitive tactile sense for precision work such as palpation or surgery.

Transparent, conformable, active multielectrode array using organic electrochemical transistors

PubMed Central

Lee, Wonryung; Kim, Dongmin; Matsuhisa, Naoji; Nagase, Masae; Sekino, Masaki; Malliaras, George G.; Yokota, Tomoyuki; Someya, Takao

2017-01-01

Mechanically flexible active multielectrode arrays (MEA) have been developed for local signal amplification and high spatial resolution. However, their opaqueness limited optical observation and light stimulation during use. Here, we show a transparent, ultraflexible, and active MEA, which consists of transparent organic electrochemical transistors (OECTs) and transparent Au grid wirings. The transparent OECT is made of Au grid electrodes and has shown comparable performance with OECTs with nontransparent electrodes/wirings. The transparent active MEA realizes the spatial mapping of electrocorticogram electrical signals from an optogenetic rat with 1-mm spacing and shows lower light artifacts than noise level. Our active MEA would open up the possibility of precise investigation of a neural network system with direct light stimulation. PMID:28923928

Variability aware compact model characterization for statistical circuit design optimization

NASA Astrophysics Data System (ADS)

Qiao, Ying; Qian, Kun; Spanos, Costas J.

2012-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

NASA Astrophysics Data System (ADS)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized acoustic wave detection, high pitch sound diffraction pattern mapping, and directional listening. This system permits the direct visualization of a two dimensional sound field in a format that was previously inaccessible. In addition to the piezoelectric property, pyroelectricity is also exhibited by PVDF and is essential in the world of sensors. An integration of PVDF and OFET for the IR heat sensing is demonstrated to prove the concept of converting pyroelectric charge signal to a electric current signal. The basic pyroelectricity of PVDF sheet is first examined before making a organic transistor integrated IR sensor. Then, two types of architectures are designed and tested. The first one uses the structure similar to the PVDF strain sensor, and the second one uses a PVDF capacitor to gate the integrated OFETs. The conversion from pyroelectric signal to transistor current signal is observed and characterized. This design provides a flexible and gain-tunable version for IR heat sensors.

Dose measurement based on threshold shift in MOSFET arrays in commercial SRAMS

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Swift, G.

2002-01-01

A new method using an array of MOS transistors isdescribed for measuring dose absorbed from ionizingradiation. Using the array of MOSFETs in a SRAM, a direct measurement of the number of MOS cells which change as a function of applied bias on the SRAM. Since the input and output of a SRAM used as a dosimeter is completely digital, the measurement of dose is easily accessible by a remote processing system.

Terahertz Real-Time Imaging Uncooled Arrays Based on Antenna-Coupled Bolometers or FET Developed at CEA-Leti

NASA Astrophysics Data System (ADS)

Simoens, François; Meilhan, Jérôme; Nicolas, Jean-Alain

2015-10-01

Sensitive and large-format terahertz focal plane arrays (FPAs) integrated in compact and hand-held cameras that deliver real-time terahertz (THz) imaging are required for many application fields, such as non-destructive testing (NDT), security, quality control of food, and agricultural products industry. Two technologies of uncooled THz arrays that are being studied at CEA-Leti, i.e., bolometer and complementary metal oxide semiconductor (CMOS) field effect transistors (FET), are able to meet these requirements. This paper reminds the followed technological approaches and focuses on the latest modeling and performance analysis. The capabilities of application of these arrays to NDT and security are then demonstrated with experimental tests. In particular, high technological maturity of the THz bolometer camera is illustrated with fast scanning of large field of view of opaque scenes achieved in a complete body scanner prototype.

Atomically engineered epitaxial anatase TiO 2 metal-semiconductor field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki

Here, anatase TiO 2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO 2 and LaAlO 3 (001), which arises for LaO-terminated LaAlO 3, while the AlO 2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a highmore » field-effect mobility μ FE of 3.14 cm 2 (V s) –1 approaching 98% of the corresponding Hall mobility μ Hall. Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ~4 V.« less

Atomically engineered epitaxial anatase TiO 2 metal-semiconductor field-effect transistors

DOE PAGES

Kim, Brian S. Y.; Minohara, Makoto; Hikita, Yasuyuki; ...

2018-03-26

Here, anatase TiO 2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO 2 and LaAlO 3 (001), which arises for LaO-terminated LaAlO 3, while the AlO 2-terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a highmore » field-effect mobility μ FE of 3.14 cm 2 (V s) –1 approaching 98% of the corresponding Hall mobility μ Hall. Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ~4 V.« less

Standard Transistor Array (STAR). Volume 1: Placement technique

NASA Technical Reports Server (NTRS)

Cox, G. W.; Caroll, B. D.

1979-01-01

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.

Controlled Growth of Large-Area Aligned Single-Crystalline Organic Nanoribbon Arrays for Transistors and Light-Emitting Diodes Driving

NASA Astrophysics Data System (ADS)

Wang, Wei; Wang, Liang; Dai, Gaole; Deng, Wei; Zhang, Xiujuan; Jie, Jiansheng; Zhang, Xiaohong

2017-10-01

Organic field-effect transistors (OFETs) based on organic micro-/nanocrystals have been widely reported with charge carrier mobility exceeding 1.0 cm2 V-1 s-1, demonstrating great potential for high-performance, low-cost organic electronic applications. However, fabrication of large-area organic micro-/nanocrystal arrays with consistent crystal growth direction has posed a significant technical challenge. Here, we describe a solution-processed dip-coating technique to grow large-area, aligned 9,10-bis(phenylethynyl) anthracene (BPEA) and 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) single-crystalline nanoribbon arrays. The method is scalable to a 5 × 10 cm2 wafer substrate, with around 60% of the wafer surface covered by aligned crystals. The quality of crystals can be easily controlled by tuning the dip-coating speed. Furthermore, OFETs based on well-aligned BPEA and TIPS-PEN single-crystalline nanoribbons were constructed. By optimizing channel lengths and using appropriate metallic electrodes, the BPEA and TIPS-PEN-based OFETs showed hole mobility exceeding 2.0 cm2 V-1 s-1 (average mobility 1.2 cm2 V-1 s-1) and 3.0 cm2 V-1 s-1 (average mobility 2.0 cm2 V-1 s-1), respectively. They both have a high on/off ratio ( I on/ I off) > 109. The performance can well satisfy the requirements for light-emitting diodes driving.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Non-classical logic inverter coupling a ZnO nanowire-based Schottky barrier transistor and adjacent Schottky diode.

PubMed

Hosseini Shokouh, Seyed Hossein; Raza, Syed Raza Ali; Lee, Hee Sung; Im, Seongil

2014-08-21

On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Ultrahigh density alignment of carbon nanotube arrays by dielectrophoresis.

PubMed

Shekhar, Shashank; Stokes, Paul; Khondaker, Saiful I

2011-03-22

We report ultrahigh density assembly of aligned single-walled carbon nanotube (SWNT) two-dimensional arrays via AC dielectrophoresis using high-quality surfactant-free and stable SWNT solutions. After optimization of frequency and trapping time, we can reproducibly control the linear density of the SWNT between prefabricated electrodes from 0.5 SWNT/μm to more than 30 SWNT/μm by tuning the concentration of the nanotubes in the solution. Our maximum density of 30 SWNT/μm is the highest for aligned arrays via any solution processing technique reported so far. Further increase of SWNT concentration results in a dense array with multiple layers. We discuss how the orientation and density of the nanotubes vary with concentrations and channel lengths. Electrical measurement data show that the densely packed aligned arrays have low sheet resistances. Selective removal of metallic SWNTs via controlled electrical breakdown produced field-effect transistors with high current on-off ratio. Ultrahigh density alignment reported here will have important implications in fabricating high-quality devices for digital and analog electronics.

Nonvolatile random access memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

1994-01-01

A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Inverter for interfacing advanced energy sources to a utility grid

DOEpatents

Steigerwald, Robert L.

1984-01-01

A transistor is operated in the PWM mode such that a hlaf sine wave of current is delivered first to one-half of a distribution transformer and then the other as determined by steering thyristors operated at the fundamental sinusoidal frequency. Power to the transistor is supplied by a dc source such as a solar array and the power is converted such that a sinusoidal current is injected into a utility at near unity power factor.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

PubMed

Dey, Anil W; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik

2013-01-01

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

A Cryogenic SiGe Low-noise Amplifier Optimized for Phased-array Feeds

NASA Astrophysics Data System (ADS)

Groves, Wavley M., III; Morgan, Matthew A.

2017-08-01

The growing number of phased-array feeds (PAF) being built for radio astronomy demonstrates an increasing need for low-noise amplifiers (LNA), which are designed for repeatability, low noise, and ease of manufacture. Specific design features that help to achieve these goals include the use of unpackaged transistors (for cryogenic operation); single-polarity biasing; straight plug-in radio frequency (RF) interfaces to facilitate installation and re-work; and the use of off-the-shelf components. The focal L-band array for the Green Bank Telescope (FLAG) is a cooperative effort by Brigham Young University and the National Radio Astronomy Observatory using warm dipole antennae and cryogenic Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) LNAs. These LNAs have an in band gain average of 38 dB and 4.85 Kelvin average noise temperature. Although the FLAG instrument was the driving instrument behind this development, most of the key features of the design and the advantages they offer apply broadly to other array feeds, including independent-beam and phased, and for many antenna types such as horn, dipole, Vivaldi, connected-bowtie, etc. This paper focuses on the unique requirements array feeds have for low-noise amplifiers and how amplifier manufacturing can accommodate these needs.

Growth Of Organic Semiconductor Thin Films with Multi-Micron Domain Size and Fabrication of Organic Transistors Using a Stencil Nanosieve.

PubMed

Fesenko, Pavlo; Flauraud, Valentin; Xie, Shenqi; Kang, Enpu; Uemura, Takafumi; Brugger, Jürgen; Genoe, Jan; Heremans, Paul; Rolin, Cédric

2017-07-19

To grow small molecule semiconductor thin films with domain size larger than modern-day device sizes, we evaporate the material through a dense array of small apertures, called a stencil nanosieve. The aperture size of 0.5 μm results in low nucleation density, whereas the aperture-to-aperture distance of 0.5 μm provides sufficient crosstalk between neighboring apertures through the diffusion of adsorbed molecules. By integrating the nanosieve in the channel area of a thin-film transistor mask, we show a route for patterning both the organic semiconductor and the metal contacts of thin-film transistors using one mask only and without mask realignment.

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Flexible graphene transistors for recording cell action potentials

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Lottner, Martin; Drieschner, Simon; Bonaccini Calia, Andrea; Stoiber, Karolina; Rousseau, Lionel; Lissourges, Gaëlle; Garrido, Jose A.

2016-06-01

Graphene solution-gated field-effect transistors (SGFETs) are a promising platform for the recording of cell action potentials due to the intrinsic high signal amplification of graphene transistors. In addition, graphene technology fulfills important key requirements for in-vivo applications, such as biocompability, mechanical flexibility, as well as ease of high density integration. In this paper we demonstrate the fabrication of flexible arrays of graphene SGFETs on polyimide, a biocompatible polymeric substrate. We investigate the transistor’s transconductance and intrinsic electronic noise which are key parameters for the device sensitivity, confirming that the obtained values are comparable to those of rigid graphene SGFETs. Furthermore, we show that the devices do not degrade during repeated bending and the transconductance, governed by the electronic properties of graphene, is unaffected by bending. After cell culture, we demonstrate the recording of cell action potentials from cardiomyocyte-like cells with a high signal-to-noise ratio that is higher or comparable to competing state of the art technologies. Our results highlight the great capabilities of flexible graphene SGFETs in bioelectronics, providing a solid foundation for in-vivo experiments and, eventually, for graphene-based neuroprosthetics.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

Around Marshall

NASA Image and Video Library

1983-08-10

One of the main components of the Hubble Space Telescope (HST) is the Solar Array Drive Electronics (SADE) system. This system interfaces with the Support System Module (SSM) for exchange of operational commands and telemetry data. SADE operates and controls the Solar Array Drive Mechanisms (SADM) for the orientation of the Solar Array Drive (SAD). It also monitors the position of the arrays and the temperature of the SADM. During the first HST servicing mission, the astronauts replaced the SADE component because of some malfunctions. This turned out to be a very challenging extravehicular activity (EVA). Two transistors and two diodes had been thermally stressed with the conformal coating discolored and charred. Soldered cornections became molten and reflowed between the two diodes. The failed transistors gave no indication of defective construction. All repairs were made and the HST was redeposited into orbit. Prior to undertaking this challenging mission, the orbiter's crew trained at Marshall Space Flight Center's (MSFC) Neutral Buoyancy Simulator (NBS) to prepare themselves for working in a low gravity environment. They also practiced replacing HST parts and exercised maneuverability and equipment handling. Pictured is an astronaut practicing climbing a space platform that was necessary in making repairs on the HST.

Neutral Buoyancy Simulator - SADE NBS Test

NASA Technical Reports Server (NTRS)

1983-01-01

One of the main components of the Hubble Space Telescope (HST) is the Solar Array Drive Electronics (SADE) system. This system interfaces with the Support System Module (SSM) for exchange of operational commands and telemetry data. SADE operates and controls the Solar Array Drive Mechanisms (SADM) for the orientation of the Solar Array Drive (SAD). It also monitors the position of the arrays and the temperature of the SADM. During the first HST servicing mission, the astronauts replaced the SADE component because of some malfunctions. This turned out to be a very challenging extravehicular activity (EVA). Two transistors and two diodes had been thermally stressed with the conformal coating discolored and charred. Soldered cornections became molten and reflowed between the two diodes. The failed transistors gave no indication of defective construction. All repairs were made and the HST was redeposited into orbit. Prior to undertaking this challenging mission, the orbiter's crew trained at Marshall Space Flight Center's (MSFC) Neutral Buoyancy Simulator (NBS) to prepare themselves for working in a low gravity environment. They also practiced replacing HST parts and exercised maneuverability and equipment handling. Pictured is an astronaut practicing climbing a space platform that was necessary in making repairs on the HST.

Neutral Buoyancy Simulator-NB50B-SADE Training Exercises

NASA Technical Reports Server (NTRS)

1983-01-01

One of the main components of the Hubble Space Telescope (HST) is the Solar Array Drive Electronics (SADE) system. This system interfaces with the Support System Module (SSM) for exchange of operational commands and telemetry data. SADE operates and controls the Solar Array Drive Mechanisms (SADM) for the orientation of the Solar Array Drive (SAD). It also monitors the position of the arrays and the temperature of the SADM. During the first HST servicing mission, the astronauts replaced the SADE component because of some malfunctions. This turned out to be a very challenging extravehicular activity (EVA). Two transistors and two diodes had been thermally stressed with the conformal coating discolored and charred. Soldered cornections became molten and reflowed between the two diodes. The failed transistors gave no indication of defective construction. All repairs were made and the HST was redeposited into orbit. Prior to undertaking this challenging mission, the orbiter's crew trained at Marshall Space Flight Center's (MSFC) Neutral Buoyancy Simulator (NBS) to prepare themselves for working in a low gravity environment. They also practiced replacing HST parts and exercised maneuverability and equipment handling. Pictured are crew members practicing on a space platform.

Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics.

PubMed

Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2015-10-01

Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems.

Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

PubMed Central

Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2015-01-01

Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

Quick Fabrication of Large-area Organic Semiconductor Single Crystal Arrays with a Rapid Annealing Self-Solution-Shearing Method

PubMed Central

Li, Yunze; Ji, Deyang; Liu, Jie; Yao, Yifan; Fu, Xiaolong; Zhu, Weigang; Xu, Chunhui; Dong, Huanli; Li, Jingze; Hu, Wenping

2015-01-01

In this paper, we developed a new method to produce large-area single crystal arrays by using the organic semiconductor 9, 10-bis (phenylethynyl) anthracene (BPEA). This method involves an easy operation, is efficient, meets the demands of being low-cost and is independent of the substrate for large-area arrays fabrication. Based on these single crystal arrays, the organic field effect transistors exhibit the superior performance with the average mobility extracting from the saturation region of 0.2 cm2 V−1s−1 (the highest 0.47 cm2 V−1s−1) and on/off ratio exceeding 105. In addition, our single crystal arrays also show a very high photoswitch performance with an on/off current ratio up to 4.1 × 105, which is one of the highest values reported for organic materials. It is believed that this method provides a new way to fabricate single crystal arrays and has the potential for application to large area organic electronics. PMID:26282460

Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

DOE PAGES

Wang, Gongming; Li, Dehui; Cheng, Hung -Chieh; ...

2015-10-02

Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that themore » resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. Furthermore, the ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems.« less

Strain effects in Hg/sub 1-//sub x/Cd/sub x/Te (xapprox. 0. 2) photovoltaic arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Weiss, E.; Mainzer, N.

1989-03-01

The effect of stress and strain on the performance of Hg/sub 1-//sub x/Cd/sub x/Te (xapprox.0.2) photovoltaic arrays was studied both in the dark and under illumination. Stress, external as well as internal, affects the current--voltage characteristic of the photodiode. The combined action of illumination and strain yields an anomalous response to light absorption in the device. A model is conceived wherein the photodiode and guard ring are treated as a metal-insulator semiconductor field effect transistor (MISFET). Stress developed in the vicinity of small contact windows causes n-type damage, which brings about a forward bias in the device. The effect ofmore » strain on the reverse current of the photodiode is explained by a change in the n-channel conductivity of the MISFET. This change is caused by charges which are due either to a piezoelectric effect or n-type damage. Using this model observed phenomena in Hg/sub 1-//sub x/Cd/sub x/Te photovoltaic arrays are explained, as due to internal stresses originating from wafer deformation.« less

Graphene nanoribbon field-effect transistors fabricated by etchant-free transfer from Au(788)

NASA Astrophysics Data System (ADS)

Ohtomo, Manabu; Sekine, Yoshiaki; Hibino, Hiroki; Yamamoto, Hideki

2018-01-01

We report etching-free and iodine-free transfer of highly aligned array of armchair-edge graphene nanoribbons (ACGNRs) and their field-effect transistor (FET) characteristics. They were prepared by on-surface polymerization on Au(788) templates. The ACGNRs were mechanically delaminated and transferred onto insulating substrates with the aid of a nano-porous support layer composed of hydrogen silsesquioxane (HSQ). The key process in the mechanical delamination is the intercalation of octanethiol self-assembled monolayers (SAMs), which penetrate the HSQ layer and intercalate between the ACGNRs and Au(788). After the transfer, the octanethiol SAMs were removed with Piranha solution, enabling the reuse of the Au single crystals. The FETs fabricated with the transferred ACGNR array showed ambipolar behavior when the channel length was as long as 60 nm. Quasi-one-dimensional conductivity was observed, which implies a good alignment of GNRs after the transfer. In contrast, short-channel ACGNR FETs (channel length ˜20 nm) suffer from a geometry-dependent short-channel effect. This effect is more severe in the FETs with ACGNRs parallel to the channel, which is an ideal geometry, than in ones perpendicular to the channel. Since the ID-VD curve is well fitted by the power-law model, the short-channel effect likely stems from the space-charge limited current effect, while the wide charge-transfer region in the GNR channel can be another possible cause for the short-channel effect. These results provide us with important insights into the designing short-channel GNR-FETs with improved performance.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Microsensor research

NASA Astrophysics Data System (ADS)

Hughes, R. C.; Drebing, C. G.

1990-04-01

The technology that led to very large scale integrated circuits on silicon chips also provides a basis for new microsensors that are small, inexpensive, low power, rugged, and reliable. Two examples of microsensors Sandia is developing that take advantage of this technology are the microelectronic chemical sensor array and the radiation sensing field effect transistor (RADFET). Increasingly, the technology of chemical sensing needs new microsensor concepts. Applications in this area include environmental monitoring, criminal investigations, and state-of-health monitoring, both for equipment and living things. Chemical microsensors can satisfy sensing needs in the industrial, consumer, aerospace, and defense sectors. The microelectronic chemical-sensor array may address some of these applications. We have fabricated six separate chemical gas sensing areas on the microelectronic chemical sensor array. By using different catalytic metals on the gate areas of the diodes, we can selectively sense several gases.

The Acceleration of Structural Microarchitectural Simulation via Scheduling

DTIC Science & Technology

2006-11-01

193 viii List of Tables 1.1 Size of Intel R ©Processors...Table 1.1 shows the total and estimated non-cache transistor counts in succeeding generations of Intel R ©microprocessors. (Cache array transistors are...Intel486TM 1989 1,200,000 800,000 Intel R ©Pentium R © 1993 3,100,000 2,300,000 Intel R ©Pentium R ©II 1997 7,500,000 5,500,000 Intel R ©Pentium R ©III 1999

Bloch oscillating transistor as the readout element for hot electron bolometers

NASA Astrophysics Data System (ADS)

Hassel, Juha; Seppä, Heikki; Lindell, Rene; Hakonen, Pertti

2004-10-01

In this paper we analyse the properties of the Bloch oscillating transistor as a preamplifier in cryogenic devices. We consider here especially the readout of hot electron bolometers (HEBs) based on Normal-Superconductor-Insulator tunnel junctions, but the results also apply more generally. We show that one can get an equivalent noise voltage below 1 nV/√Hz with a single BOT. By using N BOTs in a parallel array configuration, a further reduction by factor √N may be achieved.

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Evolution of Analog Circuits on Field Programmable Transistor Arrays

NASA Technical Reports Server (NTRS)

Stoica, A.; Keymeulen, D.; Zebulum, R.; Thakoor, A.; Daud, T.; Klimeck, G.; Jin, Y.; Tawel, R.; Duong, V.

2000-01-01

Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications.

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

NASA Technical Reports Server (NTRS)

Kim, Q.; Cunningham, T. J.; Pain, B.; Lange, M. J.; Olsen, G. H.

2000-01-01

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Exploratory Corrugated Infrared Hot-Electron Transistor Arrays

DTIC Science & Technology

2009-02-01

quantum well infrared photodetector ( QWIP ) structure. This improvement is consistent with the hot-electron distributions created by the thermal and...the designed value. This higher barrier height can be attributed to the finite p-type doping density in the material. 15. SUBJECT TERMS QWIP ...infrared photodetector ( QWIP ) sensor in a small exploratory array format, which is capable of suppressing the detector dark current. The new detector

ADMET biosensors: up-to-date issues and strategies.

PubMed

Fang, Yan; Offenhaeusser, Andrease

2004-12-01

This insight review introduces the new concepts, theories, technology, instruments, frontier issues, and key strategies of ADMET (absorption, distribution, metabolism, elimination, and toxicity) biosensors, from the fermi to the quantum levels. Information about ADMET, originating from one author's invention, a patented pharmacotherapy for rescuing cardio-cerebral vascular stunning and regulating vascular endothelial growth-factor signaling at the post-genomic level, can be detected by a new generation of ADMET biosensor. This is a single-cell/single-molecule field-effect transistor (FET) hybrid system, where single molecules or single cells are assembled at the FET surface in a high density array manner via complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Within a given nanometer distance, ADMET-mediated oxidation-reduction (redox) potentials, electrochemistry responses, and electron transfer processes can be simultaneously and directly probed by the gates of field-effect transistor arrays. The nanometer details of the functional coupling principles and characterization technologies of DNA single-molecule/single-cell FETs, as well as the design of lab-on-a-chip instruments, are indicated. Four frontier issues and key strategies are elucidated in detail. This can lead to innovative technology for high-throughout screening of labs-on-chips to resolve the pharmaceutical industry's current bottleneck via novel, FET-based drug discovery and single-molecule/single-cell screening methods, which can bring about a pharmaceutical industry revolution in the 21st century.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors.

PubMed

Yoon, Jun-Sik; Kim, Kihyun; Baek, Chang-Ki

2017-01-23

We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or creating a nanowire array. The off-state current is also manageable for power saving through selective epitaxial growth at the top-side nanowire region. CS TFETs with an EOT of 0.8 nm and an aspect ratio of 20 for the core nanowire region provide the largest drain current ranges with point SS values below 60 mV/dec and superior on/off current ratio under all operation voltages of 0.5, 0.7, and 1.0 V. These devices are promising for low-power applications at low fabrication cost and high device density.

High-performance, low-operating voltage, and solution-processable organic field-effect transistor with silk fibroin as the gate dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Leilei; Xu, Xinjun, E-mail: xuxj@mater.ustb.edu.cn, E-mail: lidong@mater.ustb.edu.cn; Ma, Mingchao

2014-01-13

We report the use of silk fibroin as the gate dielectric material in solution-processed organic field-effect transistors (OFETs) with poly(3-hexylthiophene) (P3HT) as the semiconducting layer. Such OFETs exhibit a low threshold of −0.77 V and a low-operating voltage (0 to −3 V) compatible with the voltage level commonly-used in current electronic industry. The carrier mobility of such OFETs is as high as 0.21 cm{sup 2} V{sup −1} s{sup −1} in the saturation regime, comparable to the best value of P3HT-based OFETs with dielectric layer that is not solution-processed. The high-performance of this kind of OFET is related with the high contentmore » of β strands in fibroin dielectric which leads to an array of fibers in a highly ordered structure, thus reducing the trapping sites at the semiconductor/dielectric interface.« less

High performance inkjet-printed metal oxide thin film transistors via addition of insulating polymer with proper molecular weight

NASA Astrophysics Data System (ADS)

Sun, Dawei; Chen, Cihai; Zhang, Jun; Wu, Xiaomin; Chen, Huipeng; Guo, Tailiang

2018-01-01

Fabrication of metal oxide thin film transistor (MOTFT) arrays using the inkjet printing process has caused tremendous interest for low-cost and large-area flexible electronic devices. However, the inkjet-printed MOTFT arrays usually exhibited a non-uniform geometry due to the coffee ring effect, which restricted their commercial application. Therefore, in this work, a strategy is reported to control the geometry and enhance device performance of inkjet-printed MOTFT arrays by the addition of an insulating polymer to the precursor solution prior to film deposition. Moreover, the impact of the polymer molecular weight (MW) on the geometry, chemical constitution, crystallization, and MOTFT properties of inkjet-printed metal oxide depositions was investigated. The results demonstrated that with an increase of MW of polystyrene (PS) from 2000 to 200 000, the coffee ring was gradually faded and the coffee ring effect was completely eliminated when MW reached 200 000, which is associated with the enhanced viscosity with the insulating polymer, providing a high resistance to the outward capillary flow, which facilitated the depinning of the contact line, leading to the elimination of the coffee ring. More importantly, the carrier mobility increased significantly from 4.2 cm2 V-1 s-1 up to 13.7 cm2 V-1 s-1 as PS MW increased from 2000 to 200 000, which was about 3 times that of the pristine In2O3 TFTs. Grazing incidence X-ray diffraction and X-ray photoelectron spectroscopy results indicated that PS doping of In2O3 films not only frustrated crystallization but also altered chemical constitution by enhancing the formation of the M-O structure, both of which facilitated the carrier transport. These results demonstrated that the simple polymer additive process provides a promising method that can efficiently control the geometry of MO arrays during inkjet printing and maximize the device performance of MOTFT arrays, which showed great potential for the application in next generation printed displays and integrated circuits.

Organic permeable-base transistors - superb power efficiency at highest frequencies (Conference Presentation)

NASA Astrophysics Data System (ADS)

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Scholz, Reinhard; Lüssem, Björn; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Kasemann, Daniel; Leo, Karl

2016-11-01

Organic field-effect transistors (OFET) are important elements in thin-film electronics, being considered for flat-panel or flexible displays, radio frequency identification systems, and sensor arrays. To optimize the devices for high-frequency operation, the channel length, defined as the horizontal distance between the source and the drain contact, can be scaled down. Here, an architecture with a vertical current flow, in particular the Organic Permeable-Base Transistors (OPBT), opens up new opportunities, because the effective transit length in vertical direction is precisely tunable in the nanometer range by the thickness of the semiconductor layer. We present an advanced OPBT, competing with best OFETs while a low-cost, OLED-like fabrication with low-resolution shadow masks is used (Klinger et al., Adv. Mater. 27, 2015). Its design consists of a stack of three parallel electrodes separated by two semiconductor layers of C60 . The vertical current flow is controlled by the middle base electrode with nano-sized openings passivated by an native oxide. Using insulated layers to structure the active area, devices show an on/off ratio of 10⁶ , drive 11 A/cm² at an operation voltage of 1 V, and have a low subthreshold slope of 102 mV/decade. These OPBTs show a unity current-gain transit frequency of 2.2 MHz and off-state break-down fields above 1 MV/cm. Thus, our optimized setup does not only set a benchmark for vertical organic transistors, but also outperforms best lateral OFETs using similar low-cost structuring techniques in terms of power efficiency at high frequencies.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

PubMed

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Solution-processed, Self-organized Organic Single Crystal Arrays with Controlled Crystal Orientation

PubMed Central

Kumatani, Akichika; Liu, Chuan; Li, Yun; Darmawan, Peter; Takimiya, Kazuo; Minari, Takeo; Tsukagoshi, Kazuhito

2012-01-01

A facile solution process for the fabrication of organic single crystal semiconductor devices which meets the demand for low-cost and large-area fabrication of high performance electronic devices is demonstrated. In this paper, we develop a bottom-up method which enables direct formation of organic semiconductor single crystals at selected locations with desired orientations. Here oriented growth of one-dimensional organic crystals is achieved by using self-assembly of organic molecules as the driving force to align these crystals in patterned regions. Based upon the self-organized organic single crystals, we fabricate organic field effect transistor arrays which exhibit an average field-effect mobility of 1.1 cm2V−1s−1. This method can be carried out under ambient atmosphere at room temperature, thus particularly promising for production of future plastic electronics. PMID:22563523

CdSe TFT AMLCDE manufacturing process

NASA Astrophysics Data System (ADS)

Pritchard, Annette M.

1995-06-01

Active Matrix Liquid Crystal Displays, AMLCDs, based on Cadmium Selenide Thin Film Transistors, have been developed by Litton for a number of defence/avionics applications. Fabrication processed for the thin film transistor (TFT) arrays, color filters and liquid crystal cell assembly have been developed which enable the end product to meet the difficult environmental and performance specifications of military applications, while maintaining focus on cost and yield issues. The fabrication of the AMLCD products is now transitioning into a new production facility which has been designed specifically to meet the requirements of the defence/avionics marketplace.

Test pattern generation for ILA sequential circuits

NASA Technical Reports Server (NTRS)

Feng, YU; Frenzel, James F.; Maki, Gary K.

1993-01-01

An efficient method of generating test patterns for sequential machines implemented using one-dimensional, unilateral, iterative logic arrays (ILA's) of BTS pass transistor networks is presented. Based on a transistor level fault model, the method affords a unique opportunity for real-time fault detection with improved fault coverage. The resulting test sets are shown to be equivalent to those obtained using conventional gate level models, thus eliminating the need for additional test patterns. The proposed method advances the simplicity and ease of the test pattern generation for a special class of sequential circuitry.

Fabrication and Characterization of a Long Wavelength InP HBT-Based Optical Receiver

NASA Technical Reports Server (NTRS)

Roenker, Kenneth P.

1997-01-01

Development of a high speed photodetector - the InP-based phototransistor (HPT) for use in optical receivers for microwave signal distribution for satellite phased array antennas is addressed. Currently, p-i-n photodetectors are used because of their compatibility with the heterojunction bipolar transistor (HBT), but their performance limits the bandwidth of these optical receivers. The HPT photodetector was investigated here as an alternative photodetector for monolithic integration with heterojunction bipolar transistor amplifiers in long wavelength (1.3 micron), gigahertz (GHz) frequency optical receivers.

A Water-Based Silver-Nanowire Screen-Print Ink for the Fabrication of Stretchable Conductors and Wearable Thin-Film Transistors.

PubMed

Liang, Jiajie; Tong, Kwing; Pei, Qibing

2016-07-01

A water-based silver-nanowire (AgNW) ink is formulated for screen printing. Screen-printed AgNW patterns have uniform sharp edges, ≈50 μm resolution, and electrical conductivity as high as 4.67 × 10(4) S cm(-1) . The screen-printed AgNW patterns are used to fabricate a stretchable composite conductor, and a fully printed and intrinsically stretchable thin-film transistor array is also realized. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

Neutron Transmutation Doped (NTD) germanium thermistors for sub-mm bolometer applications

NASA Technical Reports Server (NTRS)

Haller, E. E.; Itoh, K. M.; Beeman, J. W.

1996-01-01

Recent advances in the development of neutron transmutation doped (NTD) semiconductor thermistors fabricated from natural and controlled isotopic composition germanium are reported. The near ideal doping uniformity that can be achieved with the NTD process, the device simplicity of NTD Ge thermistors and the high performance of cooled junction field effect transistor preamplifiers led to the widespread acceptance of these thermal sensors in ground-based, airborne and spaceborne radio telescopes. These features made possible the development of efficient bolometer arrays.

A Fast Event Preprocessor and Sequencer for the Simbol-X Low Energy Detector

NASA Astrophysics Data System (ADS)

Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

2009-05-01

The Simbol-X Low Energy Detector (LED), a 128×128 pixel DEPFET (Depleted Field Effect Transistor) array, will be read out at a very high rate (8000 frames/second) and, therefore, requires a very fast on board electronics. We present an FPGA-based LED camera electronics consisting of an Event Preprocessor (EPP) for on board data preprocessing and filtering of the Simbol-X low-energy detector and a related Sequencer (SEQ) to generate the necessary signals to control the readout.

A Water-Based Silver-Nanowire Screen-Print Ink for the Fabrication of Stretchable Conductors and Wearable Thin-Film Transistors

DOE PAGES

Liang, Jiajie; Tong, Kwing; Pei, Qibing

2016-05-09

Silver nanowire is a very promising material for fabricating compliant conductors which are essential for stretchable/wearable electronic devices. Screen printing is a cost-effective and scalable technology to fabricate large-area thin film coatings with modest pattern resolution. The biggest challenge to prepare a screen printable silver nanowire ink stems from the low viscosity of silver nanowire dispersions and that the addition of a thickening agent could dramatically increase the inter-nanowire contact resistance in the resulting coating. Herein, we report the synthesis of a water-based silver nanowire ink, which was formulated with low solid contents, high viscosity at 0.1 s -1 shearmore » rate, and appropriate rheological behavior suitable for screen printing. Silver nanowire coating patterns were screen printed with uniform sharp edges, ~50 μm resolution, and electrical conductivity as high as 4.67 × 10 4 S cm -1. The screen printed silver nanowires were then used to fabricate a composite conductor that retained a conductivity greater than 10,000 S cm -1 under 70% tensile strain. Fully printed and stretchable/wearable thin-film transistor arrays were also fabricated by employing the screen printed composite conductor as the source, drain, and gate, drop cast semiconducting carbon nanotubes as the channel, and a dielectric elastomer. The 10 × 6 thin-film transistor arrays had a fabrication yield of 91.7%, average mobility of 33.8 ± 3.7 cm 2V -1s -1, ON/OFF ratio ~1000, and remained stable during 1,000 cycles of wearing on and peeling off a glass tube with 5 mm diameter.« less

A Water-Based Silver-Nanowire Screen-Print Ink for the Fabrication of Stretchable Conductors and Wearable Thin-Film Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liang, Jiajie; Tong, Kwing; Pei, Qibing

Silver nanowire is a very promising material for fabricating compliant conductors which are essential for stretchable/wearable electronic devices. Screen printing is a cost-effective and scalable technology to fabricate large-area thin film coatings with modest pattern resolution. The biggest challenge to prepare a screen printable silver nanowire ink stems from the low viscosity of silver nanowire dispersions and that the addition of a thickening agent could dramatically increase the inter-nanowire contact resistance in the resulting coating. Herein, we report the synthesis of a water-based silver nanowire ink, which was formulated with low solid contents, high viscosity at 0.1 s -1 shearmore » rate, and appropriate rheological behavior suitable for screen printing. Silver nanowire coating patterns were screen printed with uniform sharp edges, ~50 μm resolution, and electrical conductivity as high as 4.67 × 10 4 S cm -1. The screen printed silver nanowires were then used to fabricate a composite conductor that retained a conductivity greater than 10,000 S cm -1 under 70% tensile strain. Fully printed and stretchable/wearable thin-film transistor arrays were also fabricated by employing the screen printed composite conductor as the source, drain, and gate, drop cast semiconducting carbon nanotubes as the channel, and a dielectric elastomer. The 10 × 6 thin-film transistor arrays had a fabrication yield of 91.7%, average mobility of 33.8 ± 3.7 cm 2V -1s -1, ON/OFF ratio ~1000, and remained stable during 1,000 cycles of wearing on and peeling off a glass tube with 5 mm diameter.« less

Highly effective field-effect mobility amorphous InGaZnO TFT mediated by directional silver nanowire arrays.

PubMed

Liu, Hung-Chuan; Lai, Yi-Chun; Lai, Chih-Chung; Wu, Bing-Shu; Zan, Hsiao-Wen; Yu, Peichen; Chueh, Yu-Lun; Tsai, Chuang-Chuang

2015-01-14

In this work, we demonstrate sputtered amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a record high effective field-effect mobility of 174 cm(2)/V s by incorporating silver nanowire (AgNW) arrays to channel electron transport. Compared to the reference counterpart without nanowires, the over 5-fold enhancement in the effective field-effect mobility exhibits clear dependence on the orientation as well as the surface coverage ratio of silver nanowires. Detailed material and device analyses reveal that during the room-temperature IGZO sputtering indium and oxygen diffuse into the nanowire matrix while the nanowire morphology and good contact between IGZO and nanowires are maintained. The unchanged morphology and good interfacial contact lead to high mobility and air-ambient-stable characteristics up to 3 months. Neither hysteresis nor degraded bias stress reliability is observed. The proposed AgNW-mediated a-IGZO TFTs are promising for development of large-scale, flexible, transparent electronics.

In vitro cyto-biocompatibility study of thin-film transistors substrates using an organotypic culture method.

PubMed

Leclerc, Eric; Duval, Jean-Luc; Egles, Christophe; Ihida, Satoshi; Toshiyoshi, Hiroshi; Tixier-Mita, Agnès

2017-01-01

Thin-Film-Transistors Liquid-Crystal Display has become a standard in the field of displays. However, the structure of these devices presents interest not only in that field, but also for biomedical applications. One of the key components, called here TFT substrate, is a glass substrate with a dense and large array of thousands of transparent micro-electrodes that can be considered as a large scale multi-electrode array(s). Multi-electrode array(s) are widely used for in vitro electrical investigations on neurons and brain, allowing excitation, registration, and recording of their activity. However, the range of application of conventional multi-electrode array(s) is usually limited to some tens of cells in a homogeneous cell culture, because of a small area, small number and a low density of the micro-electrodes. TFT substrates do not have these limitations and the authors are currently studying the possibility to use TFT substrates as new tools for in vitro electrical investigation on tissues and organoids. In this respect, experiments to determine the cyto-biocompatibility of TFT substrates with tissues were conducted and are presented in this study. The investigation was performed using an organotypic culture method with explants of brain and liver tissues of chick embryos. The results in term of morphology, cell migration, cell density and adhesion were compared with the results from Thermanox ® , a conventional plastic for cell culture, and with polydimethylsiloxane, a hydrophobic silicone. The results with TFT substrates showed similar results as for the Thermanox ® , despite the TFT hydrophobicity. TFT substrates have a weak cell adhesion and promote cell migration similarly to Thermanox ® . It could be concluded that the TFT substrates are cyto-biocompatible with the two studied organs.

Quasi-Ballistic Carbon Nanotube Array Transistors with Current Density Exceeding Si and GaAs

DTIC Science & Technology

2016-09-02

performance of surfactant- encapsulated and conjugated polymer –wrapped CNTs in aligned arrays prepared by dielectrophoresis (20) and shear-casting (21); how... conjugated polymer poly[(9,9-dioctylfluorenyl- 2,7-diyl)-alt-co-(6,60-(2,20-bipyridine))] (PFO-BPy) in toluene to se- lectively wrap the semiconducting...Malenfant, J. Humes, J. Kroeger, A hybrid enrichment process combining conjugated polymer extraction and silica gel adsorption for high purity

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs.

PubMed

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-03-07

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)-a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance-information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

NASA Astrophysics Data System (ADS)

Shauly, Eitan N.; Levi, Shimon; Schwarzband, Ishai; Adan, Ofer; Latinsky, Sergey

2015-04-01

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor's sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define "robust" and "less-robust" transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.

Electronic nanobiosensors based on two-dimensional materials

NASA Astrophysics Data System (ADS)

Ping, Jinglei

Atomically-thick two-dimensional (2D) nanomaterials have tremendous potential to be applied as transduction elements in biosensors and bioelectronics. We developed scalable methods for synthesis and large-area transfer of two-dimensional nanomaterials, particularly graphene and metal dichalcogenides (so called ``MX2'' materials). We also developed versatile fabrication methods for large arrays of field-effect transistors (FETs) and micro-electrodes with these nanomaterials based on either conventional photolithography or innovative approaches that minimize contamination of the 2D layer. By functionalizing the FETs with a computationally redesigned water-soluble mu-opioid receptor, we created selective and sensitive biosensors suitable for detection of the drug target naltrexone and the neuropeptide enkephalin at pg/mL concentrations. We also constructed DNA-functionalized biosensors and nano-particle decorated biosensors by applying related bio-nano integration techniques. Our methodology paves the way for multiplexed nanosensor arrays with all-electronic readout suitable for inexpensive point-of-care diagnostics, drug-development and biomedical research. With graphene field-effect transistors, we investigated the graphene/solution interface and developed a quantitative model for the effect of ionic screening on the graphene carrier density based on theories of the electric double layer. Finally, we have developed a technique for measuring low-level Faradaic charge-transfer current (fA) across the graphene/solution interface via real-time charge monitoring of graphene microelectrodes in ionic solution. This technique enables the development of flexible and transparent pH sensors that are promising for in vivo applications. The author acknowledges the support from the Defense Advanced Research Projects Agency (DARPA) and the U. S. Army Research Office under Grant Number W911NF1010093.

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Antenna-Coupled Superconducting Tunnel Junctions with Single-Electron Transistor Readout for Detection of Sub-mm Radiation

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Wollack, E. J.; Schoelkopf, R. J.; Teufel, J.; Krebs, Carolyn (Technical Monitor)

2002-01-01

Antenna-coupled superconducting tunnel junction detectors have the potential for photon-counting sensitivity at sub-mm wavelengths. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Transistor Effect in Improperly Connected Transistors.

ERIC Educational Resources Information Center

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Note: a 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy.

PubMed

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A M

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Scaling and Graphical Transport-Map Analysis of Ambipolar Schottky-Barrier Thin-Film Transistors Based on a Parallel Array of Si Nanowires.

PubMed

Jeon, Dae-Young; Pregl, Sebastian; Park, So Jeong; Baraban, Larysa; Cuniberti, Gianaurelio; Mikolajick, Thomas; Weber, Walter M

2015-07-08

Si nanowire (Si-NW) based thin-film transistors (TFTs) have been considered as a promising candidate for next-generation flexible and wearable electronics as well as sensor applications with high performance. Here, we have fabricated ambipolar Schottky-barrier (SB) TFTs consisting of a parallel array of Si-NWs and performed an in-depth study related to their electrical performance and operation mechanism through several electrical parameters extracted from the channel length scaling based method. Especially, the newly suggested current-voltage (I-V) contour map clearly elucidates the unique operation mechanism of the ambipolar SB-TFTs, governed by Schottky-junction between NiSi2 and Si-NW. Further, it reveals for the first-time in SB based FETs the important internal electrostatic coupling between the channel and externally applied voltages. This work provides helpful information for the realization of practical circuits with ambipolar SB-TFTs that can be transferred to different substrate technologies and applications.

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

NASA Astrophysics Data System (ADS)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis.

PubMed

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L; Terés, Lluís; Baumann, Reinhard R

2016-09-21

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

A 128×96 Pixel Stack-Type Color Image Sensor: Stack of Individual Blue-, Green-, and Red-Sensitive Organic Photoconductive Films Integrated with a ZnO Thin Film Transistor Readout Circuit

NASA Astrophysics Data System (ADS)

Seo, Hokuto; Aihara, Satoshi; Watabe, Toshihisa; Ohtake, Hiroshi; Sakai, Toshikatsu; Kubota, Misao; Egami, Norifumi; Hiramatsu, Takahiro; Matsuda, Tokiyoshi; Furuta, Mamoru; Hirao, Takashi

2011-02-01

A color image was produced by a vertically stacked image sensor with blue (B)-, green (G)-, and red (R)-sensitive organic photoconductive films, each having a thin-film transistor (TFT) array that uses a zinc oxide (ZnO) channel to read out the signal generated in each organic film. The number of the pixels of the fabricated image sensor is 128×96 for each color, and the pixel size is 100×100 µm2. The current on/off ratio of the ZnO TFT is over 106, and the B-, G-, and R-sensitive organic photoconductive films show excellent wavelength selectivity. The stacked image sensor can produce a color image at 10 frames per second with a resolution corresponding to the pixel number. This result clearly shows that color separation is achieved without using any conventional color separation optical system such as a color filter array or a prism.

Review on thin-film transistor technology, its applications, and possible new applications to biological cells

NASA Astrophysics Data System (ADS)

Tixier-Mita, Agnès; Ihida, Satoshi; Ségard, Bertrand-David; Cathcart, Grant A.; Takahashi, Takuya; Fujita, Hiroyuki; Toshiyoshi, Hiroshi

2016-04-01

This paper presents a review on state-of-the-art of thin-film transistor (TFT) technology and its wide range of applications, not only in liquid crystal displays (TFT-LCDs), but also in sensing devices. The history of the evolution of the technology is first given. Then the standard applications of TFT-LCDs, and X-ray detectors, followed by state-of-the-art applications in the field of chemical and biochemical sensing are presented. TFT technology allows the fabrication of dense arrays of independent and transparent microelectrodes on large glass substrates. The potential of these devices as electrical substrates for biological cell applications is then described. The possibility of using TFT array substrates as new tools for electrical experiments on biological cells has been investigated for the first time by our group. Dielectrophoresis experiments and impedance measurements on yeast cells are presented here. Their promising results open the door towards new applications of TFT technology.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

NASA Astrophysics Data System (ADS)

Kalinin, Stanislav; Kühnemuth, Ralf; Vardanyan, Hayk; Seidel, Claus A. M.

2012-09-01

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.; Prokop, Norman F.

2010-01-01

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Thin-film-transistor array: an exploratory attempt for high throughput cell manipulation using electrowetting principle

NASA Astrophysics Data System (ADS)

Shaik, F. Azam; Cathcart, G.; Ihida, S.; Lereau-Bernier, M.; Leclerc, E.; Sakai, Y.; Toshiyoshi, H.; Tixier-Mita, A.

2017-05-01

In lab-on-a-chip (LoC) devices, microfluidic displacement of liquids is a key component. electrowetting on dielectric (EWOD) is a technique to move fluids, with the advantage of not requiring channels, pumps or valves. Fluids are discretized into droplets on microelectrodes and moved by applying an electric field via the electrodes to manipulate the contact angle. Micro-objects, such as biological cells, can be transported inside of these droplets. However, the design of conventional microelectrodes, made by standard micro-fabrication techniques, fixes the path of the droplets, and limits the reconfigurability of paths and thus limits the parallel processing of droplets. In that respect, thin film transistor (TFT) technology presents a great opportunity as it allows infinitely reconfigurable paths, with high parallelizability. We propose here to investigate the possibility of using TFT array devices for high throughput cell manipulation using EWOD. A COMSOL based 2D simulation coupled with a MATLAB algorithm was used to simulate the contact angle modulation, displacement and mixing of droplets. These simulations were confirmed by experimental results. The EWOD technique was applied to a droplet of culture medium containing HepG2 carcinoma cells and demonstrated no negative effects on the viability of the cells. This confirms the possibility of applying EWOD techniques to cellular applications, such as parallel cell analysis.

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Apparatus for sensing patterns of electrical field variations across a surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, William L.; Devine, Roderick A. B.

An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials createdmore » by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.« less

Organic Light-Emitting Diode-on-Silicon Pixel Circuit Using the Source Follower Structure with Active Load for Microdisplays

NASA Astrophysics Data System (ADS)

Kwak, Bong-Choon; Lim, Han-Sin; Kwon, Oh-Kyong

2011-03-01

In this paper, we propose a pixel circuit immune to the electrical characteristic variation of organic light-emitting diodes (OLEDs) for organic light-emitting diode-on-silicon (OLEDoS) microdisplays with a 0.4 inch video graphics array (VGA) resolution and a 6-bit gray scale. The proposed pixel circuit is implemented using five p-channel metal oxide semiconductor field-effect transistors (MOSFETs) and one storage capacitor. The proposed pixel circuit has a source follower with a diode-connected transistor as an active load for improving the immunity against the electrical characteristic variation of OLEDs. The deviation in the measured emission current ranges from -0.165 to 0.212 least significant bit (LSB) among 11 samples while the anode voltage of OLED is 0 V. Also, the deviation in the measured emission current ranges from -0.262 to 0.272 LSB in pixel samples, while the anode voltage of OLED varies from 0 to 2.5 V owing to the electrical characteristic variation of OLEDs.

A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

NASA Astrophysics Data System (ADS)

Bartsch, Sebastian T.; Rusu, A.; Ionescu, Adrian M.

2012-06-01

Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption.

Highly Sensitive Ammonia Gas Sensor Based on Single-Crystal Poly(3-hexylthiophene) (P3HT) Organic Field Effect Transistor.

PubMed

Mun, Seohyun; Park, Yoonkyung; Lee, Yong-Eun Koo; Sung, Myung Mo

2017-11-28

A highly sensitive organic field-effect transistor (OFET)-based sensor for ammonia in the range of 0.01 to 25 ppm was developed. The sensor was fabricated by employing an array of single-crystal poly(3-hexylthiophene) (P3HT) nanowires as the organic semiconductor (OSC) layer of an OFET with a top-contact geometry. The electrical characteristics (field-effect mobility, on/off current ratio) of the single-crystal P3HT nanowire OFET were about 2 orders of magnitude larger than those of the P3HT thin film OFET with the same geometry. The P3HT nanowire OFET showed excellent sensitivity to ammonia, about 3 times higher than that of the P3HT thin film OFET at 25 ppm ammonia. The ammonia response of the OFET was reversible and was not affected by changes in relative humidity from 45 to 100%. The high ammonia sensitivity of the P3HT nanowire OFET is believed to result from the single crystal nature and high surface/volume ratio of the P3HT nanowire used in the OSC layer.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Human T cells monitored by impedance spectrometry using field-effect transistor arrays: a novel tool for single-cell adhesion and migration studies.

PubMed

Law, Jessica Ka Yan; Susloparova, Anna; Vu, Xuan Thang; Zhou, Xiao; Hempel, Felix; Qu, Bin; Hoth, Markus; Ingebrandt, Sven

2015-05-15

Cytotoxic T lymphocytes (CTLs) play an important role in the immune system by recognizing and eliminating pathogen-infected and tumorigenic cells. In order to achieve their function, T cells have to migrate throughout the whole body and identify the respective targets. In conventional immunology studies, interactions between CTLs and targets are usually investigated using tedious and time-consuming immunofluorescence imaging. However, there is currently no straightforward measurement tool available to examine the interaction strengths. In the present study, adhesion strengths and migration of single human CD8(+) T cells on pre-coated field-effect transistor (FET) devices (i.e. fibronectin, anti-CD3 antibody, and anti-LFA-1 antibody) were measured using impedance spectroscopy. Adhesion strengths to different protein and antibody coatings were compared. By fitting the data to an electronically equivalent circuit model, cell-related parameters (cell membrane capacitance referring to cell morphology and seal resistance referring to adhesion strength) were obtained. This electronically-assessed adhesion strength provides a novel, fast, and important index describing the interaction efficiency. Furthermore, the size of our detection transistor gates as well as their sensitivity reaches down to single cell resolution. Real-time motions of individually migrating T cells can be traced using our FET devices. The in-house fabricated FETs used in the present study are providing a novel and very efficient insight to individual cell interactions. Copyright © 2014 Elsevier B.V. All rights reserved.

CMOS image sensor with contour enhancement

NASA Astrophysics Data System (ADS)

Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

2010-10-01

Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

PubMed

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Engineering the Ideal Array (BRIEFING CHARTS)

DTIC Science & Technology

2007-03-05

48 V, f = 10 GHz GaN HEMT Transistor i t Dramatically higher: • Output power • Efficiency • Bandwidth GaN HEMT Power Amplifier lifi ...functions – RF amplifiers – 4-bit phase shifters – Amplitude controllers – Summing network – Power control – Latches for phase state – Address

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

Aligning Solution-Derived Carbon Nanotube Film with Full Surface Coverage for High-Performance Electronics Applications.

PubMed

Zhu, Ma-Guang; Si, Jia; Zhang, Zhiyong; Peng, Lian-Mao

2018-06-01

The main challenge for application of solution-derived carbon nanotubes (CNTs) in high performance field-effect transistor (FET) is how to align CNTs into an array with high density and full surface coverage. A directional shrinking transfer method is developed to realize high density aligned array based on randomly orientated CNT network film. Through transferring a solution-derived CNT network film onto a stretched retractable film followed by a shrinking process, alignment degree and density of CNT film increase with the shrinking multiple. The quadruply shrunk CNT films present well alignment, which is identified by the polarized Raman spectroscopy and electrical transport measurements. Based on the high quality and high density aligned CNT array, the fabricated FETs with channel length of 300 nm present ultrahigh performance including on-state current I on of 290 µA µm -1 (V ds = -1.5 V and V gs = -2 V) and peak transconductance g m of 150 µS µm -1 , which are, respectively, among the highest corresponding values in the reported CNT array FETs. High quality and high semiconducting purity CNT arrays with high density and full coverage obtained through this method promote the development of high performance CNT-based electronics. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS detector arrays in a virtual 10-kilopixel camera for coherent terahertz real-time imaging.

PubMed

Boppel, Sebastian; Lisauskas, Alvydas; Max, Alexander; Krozer, Viktor; Roskos, Hartmut G

2012-02-15

We demonstrate the principle applicability of antenna-coupled complementary metal oxide semiconductor (CMOS) field-effect transistor arrays as cameras for real-time coherent imaging at 591.4 GHz. By scanning a few detectors across the image plane, we synthesize a focal-plane array of 100×100 pixels with an active area of 20×20 mm2, which is applied to imaging in transmission and reflection geometries. Individual detector pixels exhibit a voltage conversion loss of 24 dB and a noise figure of 41 dB for 16 μW of the local oscillator (LO) drive. For object illumination, we use a radio-frequency (RF) source with 432 μW at 590 GHz. Coherent detection is realized by quasioptical superposition of the image and the LO beam with 247 μW. At an effective frame rate of 17 Hz, we achieve a maximum dynamic range of 30 dB in the center of the image and more than 20 dB within a disk of 18 mm diameter. The system has been used for surface reconstruction resolving a height difference in the μm range.

Ultra-low output impedance RF power amplifier for parallel excitation.

PubMed

Chu, Xu; Yang, Xing; Liu, Yunfeng; Sabate, Juan; Zhu, Yudong

2009-04-01

Inductive coupling between coil elements of a transmit array is one of the key challenges faced by parallel RF transmission. An ultra-low output impedance RF power amplifier (PA) concept was introduced to address this challenge. In an example implementation, an output-matching network was designed to transform the drain-source impedance of the metallic oxide semiconductor field effect transistor (MOSFET) into a very low value for suppressing interelement coupling effect, and meanwhile, to match the input impedance of the coil to the optimum load of the MOSFET for maximizing the available output power. Two prototype amplifiers with 500-W output rating were developed accordingly, and were further evaluated with a transmit array in phantom experiments. Compared to the conventional 50-Omega sources, the new approach exhibited considerable effectiveness suppressing the effects of interelement coupling. The experiments further indicated that the isolation performance was comparable to that achieved by optimized overlap decoupling. The new approach, benefiting from a distinctive current-source characteristic, also exhibited a superior robustness against load variation. Feasibility of the new approach in high-field MR was demonstrated on a 3T clinical scanner.

Effect of channel-width and chirality on graphene field-effect transistor based real-time biomolecule sensing

NASA Astrophysics Data System (ADS)

Lyu, Letian; Jaswal, Perveshwer; Xu, Guangyu

2018-03-01

Graphene field-effect transistors (GFET) hold promise in biomolecule sensing due to the outstanding properties of graphene materials. Charges in biomolecules are transduced into a change in the GFET current, which allows real-time monitoring of the biomolecule concentrations. Here we theoretically evaluate the performance of GFET based real-time biomolecule sensing, aiming to better understand the width-scaling limit in GFET based biosensors. In particular, we study the effect of the channel-width and the chirality on FET sensitivity by taking the percentage change of the FET current per unit charge density as the sensing signal. Firstly, GFETs made of graphene nanoribbons (GNR) and graphene sheets (GS) show comparable sensing signals to each other when gated at 1011 - 1012 cm-2 carrier densities. Sensing signals in GNRs are enhanced when gated near the sub-band thresholds, and increase their values in wider GNRs due to the change in device conductance and quantum capacitance. Secondly, the GNR chirality is found to fine tune the sensing signals. Armchair GNRs with smaller energy bandgaps appear to have an enhanced sensing signal close to 1011 cm-2 carrier densities. These results may help understand the scaling limit in GFET based biosensors along the width direction, and shed light on forming all-electrical bio-arrays.

Facile fabrication of efficient organic CMOS circuits.

PubMed

Dzwilewski, Andrzej; Matyba, Piotr; Edman, Ludvig

2010-01-14

Organic electronic circuits based on a combination of n- and p-type transistors (so-called CMOS circuits) are attractive, since they promise the realization of a manifold of versatile and low-cost electronic devices. Here, we report a novel photoinduced transformation method, which allows for a particularly straightforward fabrication of highly functional organic CMOS circuits. A solution-deposited single-layer film, comprising a mixture of the n-type semiconductor [6,6]-phenyl-C(61)-butyric acid methyl ester (PCBM) and the p-type semiconductor poly-3-hexylthiophene (P3HT) in a 3:1 mass ratio, was utilized as the common active material in an array of transistors. Selected film areas were exposed to laser light, with the result that the irradiated PCBM monomers were photochemically transformed into a low-solubility and high-mobility dimeric state. Thereafter, the entire film was developed via immersion into a developer solution, which selectively removed the nonexposed, and monomeric, PCBM component. The end result was that the transistors in the exposed film areas are n-type, as dimeric PCBM is the majority component in the active material, while the transistors in the nonexposed film areas are p-type, as P3HT is the sole remaining material. We demonstrate the merit of the method by utilizing the resulting combination of n-type and p-type transistors for the realization of CMOS inverters with a high gain of approximately 35.

Origin of high photoconductive gain in fully transparent heterojunction nanocrystalline oxide image sensors and interconnects.

PubMed

Jeon, Sanghun; Song, Ihun; Lee, Sungsik; Ryu, Byungki; Ahn, Seung-Eon; Lee, Eunha; Kim, Young; Nathan, Arokia; Robertson, John; Chung, U-In

2014-11-05

A technique for invisible image capture using a photosensor array based on transparent conducting oxide semiconductor thin-film transistors and transparent interconnection technologies is presented. A transparent conducting layer is employed for the sensor electrodes as well as interconnection in the array, providing about 80% transmittance at visible-light wavelengths. The phototransistor is a Hf-In-Zn-O/In-Zn-O heterostructure yielding a high quantum-efficiency in the visible range. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

NASA Technical Reports Server (NTRS)

1983-01-01

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis

PubMed Central

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L.; Terés, Lluís; Baumann, Reinhard R.

2016-01-01

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement. PMID:27649784

Exposure to volatile organic compounds and kidney dysfunction in thin film transistor liquid crystal display (TFT-LCD) workers.

PubMed

Chang, Ta-Yuan; Huang, Kuei-Hung; Liu, Chiu-Shong; Shie, Ruei-Hao; Chao, Keh-Ping; Hsu, Wen-Hsin; Bao, Bo-Ying

2010-06-15

Many volatile organic compounds (VOCs) are emitted during the manufacturing of thin film transistor liquid crystal displays (TFT-LCDs), exposure to some of which has been reported to be associated with kidney dysfunction, but whether such an effect exists in TFT-LCD industry workers is unknown. This cross-sectional study aimed to investigate the association between exposure to VOCs and kidney dysfunction among TFT-LCD workers. The results showed that ethanol (1811.0+/-1740.4 ppb), acetone (669.0+/-561.0 ppb), isopropyl alcohol (187.0+/-205.3 ppb) and propylene glycol monomethyl ether acetate (PGMEA) (102.9+/-102.0 ppb) were the four dominant VOCs present in the workplace. The 63 array workers studied had a risk of kidney dysfunction 3.21-fold and 3.84-fold that of 61 cell workers and 18 module workers, respectively. Workers cumulatively exposed to a total level of isopropyl alcohol, PGMEA and propylene glycol monomethyl ether> or =324 ppb-year had a significantly higher risk of kidney dysfunction (adjusted OR=3.41, 95% CI=1.14-10.17) compared with those exposed to <25 ppb-year after adjustment for potential confounding factors. These findings indicated that array workers might be the group at greatest risk of kidney dysfunction within the TFT-LCD industry, and cumulative exposure to specific VOCs might be associated with kidney dysfunction. Crown Copyright 2010. Published by Elsevier B.V. All rights reserved.

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

Thin film memory matrix using amorphous and high resistive layers

NASA Technical Reports Server (NTRS)

Thakoor, Anilkumar P. (Inventor); Lambe, John (Inventor); Moopen, Alexander (Inventor)

1989-01-01

Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Direct selective growth of ZnO nanowire arrays from inkjet-printed zinc acetate precursor on a heated substrate

PubMed Central

2013-01-01

Inkjet printing of functional materials has drawn tremendous interest as an alternative to the conventional photolithography-based microelectronics fabrication process development. We introduce direct selective nanowire array growth by inkjet printing of Zn acetate precursor ink patterning and subsequent hydrothermal ZnO local growth without nozzle clogging problem which frequently happens in nanoparticle inkjet printing. The proposed process can directly grow ZnO nanowires in any arbitrary patterned shape, and it is basically very fast, low cost, environmentally benign, and low temperature. Therefore, Zn acetate precursor inkjet printing-based direct nanowire local growth is expected to give extremely high flexibility in nanomaterial patterning for high-performance electronics fabrication especially at the development stage. As a proof of concept of the proposed method, ZnO nanowire network-based field effect transistors and ultraviolet photo-detectors were demonstrated by direct patterned grown ZnO nanowires as active layer. PMID:24252130

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Microdose analysis of ion strikes on SRAM cells

NASA Astrophysics Data System (ADS)

Scheick, L.

2003-12-01

A method of measuring the effect from exposure to highly localized ionizing radiation on microstructures is described. The voltage at which a commercial SRAM cell cannot hold a programmed state changes with microdose. The microdose distribution across the array, in addition to the analysis of the occurrence of anomalous shifts in operating bias due to rare, large energy-deposition events is studied. The effect of multiple hits on a SRAM cell is presented. A general theory on multiple hits from which basic device parameters can be extracted is presented. SPICE, as well as analysis of basic device physics, is used to analyze the damage to individual transistors and the response of a SRAM cell.

Densely Aligned Graphene Nanoribbon Arrays and Bandgap Engineering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Su, Justin; Chen, Changxin; Gong, Ming

Graphene has attracted great interest for future electronics due to its high mobility and high thermal conductivity. However, a two-dimensional graphene sheet behaves like a metal, lacking a bandgap needed for the key devices components such as field effect transistors (FETs) in digital electronics. It has been shown that, partly due to quantum confinement, graphene nanoribbons (GNRs) with ~2 nm width can open up sufficient bandgaps and evolve into semiconductors to exhibit high on/off ratios useful for FETs. However, a challenging problem has been that, such ultra-narrow GNRs (~2 nm) are difficult to fabricate, especially for GNRs with smooth edgesmore » throughout the ribbon length. Despite high on/off ratios, these GNRs show very low mobility and low on-state conductance due to dominant scattering effects by imperfections and disorders at the edges. Wider GNRs (>5 nm) show higher mobility, higher conductance but smaller bandgaps and low on/off ratios undesirable for FET applications. It is highly desirable to open up bandgaps in graphene or increase the bandgaps in wide GNRs to afford graphene based semiconductors for high performance (high on-state current and high on/off ratio) electronics. Large scale ordering and dense packing of such GNRs in parallel are also needed for device integration but have also been challenging thus far. It has been shown theoretically that uniaxial strains can be applied to a GNR to engineer its bandgap. The underlying physics is that under uniaxial strain, the Dirac point moves due to stretched C-C bonds, leading to an increase in the bandgap of armchair GNRs by up to 50% of its original bandgap (i.e. bandgap at zero strain). For zigzag GNRs, due to the existence of the edge states, changes of bandgap are smaller under uniaxial strain and can be increased by ~30%. This work proposes a novel approach to the fabrication of densely aligned graphene nanoribbons with highly smooth edges afforded by anisotropic etching and uniaxial strain for bandgap engineering of GNRs towards high on/off ratio and high on-state current GNR devices. First, we will develop a novel approach for the fabrication of high density GNR arrays (pitch <50 nm, tunable down to 30nm) with pre-defined edge orientation and smooth edges using a free standing nano-mask derived from diblock copolymer assembly for patterning of graphene sheets. Anisotropic graphene edges will be developed to afford smooth edges along crystallographic lattice directions. Then, we will fabricate GNR devices on flexible substrates and apply uniaxial strain to engineer the bandgap of the GNRs. The bandgap of GNRs could be increased by up to 50% under uniaxial strain according to theoretical calculations and will be investigated through electrical transport measurements. Micro-Raman spectroscopy of single GNRs and parallel arrays will be used to probe and quantify the uniaxial strain. Electrical measurements will be used to probe the on/off ratio of GNR FET devices and confirm the bandgap tuning effects. Finally, we plan to use dense parallel arrays of GNRs to demonstrate strained GNR field effect transistors with high on/off ratios and high on-state current, and compare strained GNR FETs with carbon nanotube and Si based field effect transistor (FET) devices.« less

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

NASA Astrophysics Data System (ADS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Uniaxial alignment of triisopropylsilylethynyl pentacene via zone-casting technique.

PubMed

Su, Yajun; Gao, Xiang; Liu, Jiangang; Xing, Rubo; Han, Yanchun

2013-09-14

Uniaxially aligned triisopropylsilylethynyl pentacene (TIPS-pentacene) crystals over a large area were fabricated using zone-casting technique. The array of TIPS-pentacene displayed a high orientation degree with a dichroic ratio (DR) of 0.80. The crystals were arranged with c axis perpendicular to the substrate and the long axis of the ribbon corresponded to the a axis of TIPS-pentacene. The properties of the solutions and the processing parameters were shown to influence the formation of the oriented TIPS-pentacene crystalline array. Solvent with a low boiling point (such as chloroform) favoured the orientation of the ribbon-like crystals. The concentration of the solution should be appropriate, ensuring the crystallization velocity of TIPS-pentacene matching with the receding of the meniscus. Besides, we proved that the casting speed should be large enough to induce a sufficient concentration gradient. The orientation mechanism of TIPS-pentacene was attributed to a synergy of the ordered nuclei and a match between the crystallization velocity and the casting speed. Field effect transistors (FETs) based on the oriented TIPS-pentacene crystalline array showed a mobility of 0.67 cm(2) V(-1) s(-1).

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

Time-dependent observation of individual cellular binding events to field-effect transistors.

PubMed

Schäfer, S; Eick, S; Hofmann, B; Dufaux, T; Stockmann, R; Wrobel, G; Offenhäusser, A; Ingebrandt, S

2009-01-01

Electrolyte-gate field-effect transistors (EG-FETs) gained continuously more importance in the field of bioelectronics. The reasons for this are the intrinsic properties of these FETs. Binding of analysts or changes in the electrolyte composition are leading to variations of the drain-source current. Furthermore, due to the signal amplification upon voltage-to-current conversion even small extracellular signals can be detected. Here we report about impedance spectroscopy with an FET array to characterize passive components of a cell attached to the transistor gate. We developed a 16-channel readout system, which provides a simultaneous, lock-in based readout. A test signal of known amplitude and phase was applied via the reference electrode. We monitored the electronic transfer function of the FETs with the attached cell. The resulting frequency spectrum was used to investigate the surface adhesion of individual HEK293 cells. We applied different chemical treatments with either the serinpeptidase trypsin or the ionophor amphotericin B (AmpB). Binding studies can be realized by a time-dependent readout of the lock-in amplifier at a constant frequency. We observed cell detachment upon trypsin activity as well as membrane decomposition induced by AmpB. The results were interpreted in terms of an equivalent electrical circuit model of the complete system. The presented method could in future be applied to monitor more relevant biomedical manipulations of individual cells. Due to the utilization of the silicon technology, our method could be easily up-scaled to many output channels for high throughput pharmacological screening.

Performance of In-Pixel Circuits for Photon Counting Arrays (PCAs) Based on Polycrystalline Silicon TFTs

PubMed Central

Liang, Albert K.; Koniczek, Martin; Antonuk, Larry E.; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A.; Lu, Jeng Ping

2017-01-01

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si) — a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance — information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% FWHM at 70 keV; and the digital components should work well even in the presence of significant TFT variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ~240 and 290 μm. PMID:26878107

Bar-Coated Ultrathin Semiconductors from Polymer Blend for One-Step Organic Field-Effect Transistors.

PubMed

Ge, Feng; Liu, Zhen; Lee, Seon Baek; Wang, Xiaohong; Zhang, Guobing; Lu, Hongbo; Cho, Kilwon; Qiu, Longzhen

2018-06-27

One-step deposition of bi-functional semiconductor-dielectric layers for organic field-effect transistors (OFETs) is an effective way to simplify the device fabrication. However, the proposed method has rarely been reported in large-area flexible organic electronics. Herein, we demonstrate wafer-scale OFETs by bar coating the semiconducting and insulating polymer blend solution in one-step. The semiconducting polymer poly(3-hexylthiophene) (P3HT) segregates on top of the blend film, whereas dielectric polymethyl methacrylate (PMMA) acts as the bottom layer, which is achieved by a vertical phase separation structure. The morphology of blend film can be controlled by varying the concentration of P3HT and PMMA solutions. The wafer-scale one-step OFETs, with a continuous ultrathin P3HT film of 2.7 nm, exhibit high electrical reproducibility and uniformity. The one-step OFETs extend to substrate-free arrays that can be attached everywhere on varying substrates. In addition, because of the well-ordered molecular arrangement, the moderate charge transport pathway is formed, which resulted in stable OFETs under various organic solvent vapors and lights of different wavelengths. The results demonstrate that the one-step OFETs have promising potential in the field of large-area organic wearable electronics.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Functionalized Silk Materials

DTIC Science & Technology

2010-06-10

properties, such as toughness, biocompatibility and biodegrability. Trends in spider silk-like block copolymer secondary structure and assembly behavior...to construct transistors on ultrathin sheets of polyimide . Briefly, the doped silicon nanomembranes were transfer printed onto a film of polyimide ...layer of polyimide was used to encapsulate the active devices. Dry etching the polymer layers completed the fabrication of an array of isolated

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

NASA Astrophysics Data System (ADS)

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-09-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation.

Amorphous In-Ga-Zn-O Thin Film Transistor Current-Scaling Pixel Electrode Circuit for Active-Matrix Organic Light-Emitting Displays

NASA Astrophysics Data System (ADS)

Chen, Charlene; Abe, Katsumi; Fung, Tze-Ching; Kumomi, Hideya; Kanicki, Jerzy

2009-03-01

In this paper, we analyze application of amorphous In-Ga-Zn-O thin film transistors (a-InGaZnO TFTs) to current-scaling pixel electrode circuit that could be used for 3-in. quarter video graphics array (QVGA) full color active-matrix organic light-emitting displays (AM-OLEDs). Simulation results, based on a-InGaZnO TFT and OLED experimental data, show that both device sizes and operational voltages can be reduced when compare to the same circuit using hydrogenated amorphous silicon (a-Si:H) TFTs. Moreover, the a-InGaZnO TFT pixel circuit can compensate for the drive TFT threshold voltage variation (ΔVT) within acceptable operating error range.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-Based Current Amplifier.

PubMed

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2016-06-01

To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. The resonant detection coil is connected in parallel with the gate of a high electron mobility transistor (HEMT) transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor's source to a negative resistance on its gate. High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 μW, 14 dB gain was obtained with excellent noise performance. An integrated current amplifier based on a HEMT can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. Magn Reson Med 75:2573-2578, 2016. Published 2015. This article is a U.S. Government work and is in the public domain in the USA. Published 2015 This article is a U.S. Government work and is in the public domain in the USA.

Dielectrophoresis-Assisted Integration of 1024 Carbon Nanotube Sensors into a CMOS Microsystem.

PubMed

Seichepine, Florent; Rothe, Jörg; Dudina, Alexandra; Hierlemann, Andreas; Frey, Urs

2017-05-01

Carbon-nanotube (CNT)-based sensors offer the potential to detect single-molecule events and picomolar analyte concentrations. An important step toward applications of such nanosensors is their integration in large arrays. The availability of large arrays would enable multiplexed and parallel sensing, and the simultaneously obtained sensor signals would facilitate statistical analysis. A reliable method to fabricate an array of 1024 CNT-based sensors on a fully processed complementary-metal-oxide-semiconductor microsystem is presented. A high-yield process for the deposition of CNTs from a suspension by means of liquid-coupled floating-electrode dielectrophoresis (DEP), which yielded 80% of the sensor devices featuring between one and five CNTs, is developed. The mechanism of floating-electrode DEP on full arrays and individual devices to understand its self-limiting behavior is studied. The resistance distributions across the array of CNT devices with respect to different DEP parameters are characterized. The CNT devices are then operated as liquid-gated CNT field-effect-transistors (LG-CNTFET) in liquid environment. Current dependency to the gate voltage of up to two orders of magnitude is recorded. Finally, the sensors are validated by studying the pH dependency of the LG-CNTFET conductance and it is demonstrated that 73% of the CNT sensors of a given microsystem show a resistance decrease upon increasing the pH value. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mercuric iodide medical imagers for low-exposure radiography and fluoroscopy

NASA Astrophysics Data System (ADS)

Zentai, George; Partain, Larry; Pavlyuchkova, Raisa; Proano, Cesar; Breen, Barry N.; Taieb, A.; Dagan, Ofer; Schieber, Michael; Gilboa, Haim; Thomas, Jerry

2004-05-01

Photoconductive polycrystalline mercuric iodide deposited on flat panel thin film transistor (TFT) arrays is being developed for direct digital X-ray detectors that can perform both radiographic and fluoroscopic medical imaging. The mercuric iodide is either vacuum deposited by Physical Vapor Deposition (PVD) or coated onto the array by a wet Particle-In-Binder (PIB) process. The PVD deposition technology has been scaled up to the 20 cm x 25 cm size required in common medical imaging applications. A TFT array with a pixel pitch of 127 microns is used for these imagers. Arrays of 10 cm x 10 cm size have been used to evaluate performance of mercuric iodide imagers. Radiographic and fluoroscopic images of diagnostic quality at up to 15 pulses per second were demonstrated. As we previously reported, the resolution is limited to the TFT array Nyquist frequency of ~3.9 lp/mm (127 micron pixel pitch). Detective Quantum Efficiency (DQE) has been measured as a function of spatial frequency for these imagers. The DQE is lower than the theoretically calculated value due to some additional noise sources of the electronics and the array. We will retest the DQE after eliminating these noise sources. Reliability and stress testing was also began for polycrystalline mercuric iodide PVD and PIB detectors. These are simplified detectors based upon a stripe electrode or circular electrode structure. The detectors were stressed under various voltage bias, temperature and time conditions. The effects of the stress tests on the detector dark current and sensitivity were determined.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Single-Molecule Bioelectronics

PubMed Central

Rosenstein, Jacob K.; Lemay, Serge G.; Shepard, Kenneth L.

2014-01-01

Experimental techniques which interface single biomolecules directly with microelectronic systems are increasingly being used in a wide range of powerful applications, from fundamental studies of biomolecules to ultra-sensitive assays. Here we review several technologies which can perform electronic measurements of single molecules in solution: ion channels, nanopore sensors, carbon nanotube field-effect transistors, electron tunneling gaps, and redox cycling. We discuss the shared features among these techniques that enable them to resolve individual molecules, and discuss their limitations. Recordings from each of these methods all rely on similar electronic instrumentation, and we discuss the relevant circuit implementations and potential for scaling these single-molecule bioelectronic interfaces to high-throughput arrayed sensing platforms. PMID:25529538

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Recent progress in photoactive organic field-effect transistors.

PubMed

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Flexible, foldable, actively multiplexed, high-density electrode array for mapping brain activity in vivo.

PubMed

Viventi, Jonathan; Kim, Dae-Hyeong; Vigeland, Leif; Frechette, Eric S; Blanco, Justin A; Kim, Yun-Soung; Avrin, Andrew E; Tiruvadi, Vineet R; Hwang, Suk-Won; Vanleer, Ann C; Wulsin, Drausin F; Davis, Kathryn; Gelber, Casey E; Palmer, Larry; Van der Spiegel, Jan; Wu, Jian; Xiao, Jianliang; Huang, Yonggang; Contreras, Diego; Rogers, John A; Litt, Brian

2011-11-13

Arrays of electrodes for recording and stimulating the brain are used throughout clinical medicine and basic neuroscience research, yet are unable to sample large areas of the brain while maintaining high spatial resolution because of the need to individually wire each passive sensor at the electrode-tissue interface. To overcome this constraint, we developed new devices that integrate ultrathin and flexible silicon nanomembrane transistors into the electrode array, enabling new dense arrays of thousands of amplified and multiplexed sensors that are connected using fewer wires. We used this system to record spatial properties of cat brain activity in vivo, including sleep spindles, single-trial visual evoked responses and electrographic seizures. We found that seizures may manifest as recurrent spiral waves that propagate in the neocortex. The developments reported here herald a new generation of diagnostic and therapeutic brain-machine interface devices.

64 x 64 thresholding photodetector array for optical pattern recognition

NASA Astrophysics Data System (ADS)

Langenbacher, Harry; Chao, Tien-Hsin; Shaw, Timothy; Yu, Jeffrey W.

1993-10-01

A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

The Design and Development of the SMEX-Lite Power System

NASA Technical Reports Server (NTRS)

Rakow, Glenn P.; Schnurr, Richard G., Jr.; Solly, Michael A.

1998-01-01

This paper describes the design and development of a 250W orbit average electrical power system electronic Power Node and software for use in Low Earth Orbit missions. The mass of the Power Node is 3.6 Kg (8 lb.). The dimensions of the Power Node are 30cm x 26cm x 7.9cm (11 in. x 10.25 in x 3.1 in.) The design was realized using software, Field Programmable Gate Array (FPGA) digital logic and surface mount technology. The design is generic enough to reduce the non-recurring engineering for different mission configurations. The Power Node charges one to five, low cost, 22-cell 4 AH D-cell battery packs independently. The battery charging algorithms are executed in the power software to reduce the mass and size of the power electronic. The Power Node implements a peak-power tracking algorithm using an innovative hardware/software approach. The power software task is hosted on the spacecraft processor. The power software task generates a MIL-STD-1553 command packet to update the Power Node control settings. The settings for the battery voltage and current limits, as well as minimum solar array voltage used to implement peak power tracking are contained in this packet. Several advanced topologies are used in the Power Node. These include synchronous rectification in the bus regulators, average current control in the battery chargers and quasi-resonant converters for the Field Effect Transistor (FET) transistor drive electronics. Lastly, the main bus regulator uses a feed-forward topology with the PWM implemented in an FPGA.

Digital radiology using active matrix readout: amplified pixel detector array for fluoroscopy.

PubMed

Matsuura, N; Zhao, W; Huang, Z; Rowlands, J A

1999-05-01

Active matrix array technology has made possible the concept of flat panel imaging systems for radiography. In the conventional approach a thin-film circuit built on glass contains the necessary switching components (thin-film transistors or TFTs) to readout an image formed in either a phosphor or photoconductor layer. Extension of this concept to real time imaging--fluoroscopy--has had problems due to the very low noise required. A new design strategy for fluoroscopic active matrix flat panel detectors has therefore been investigated theoretically. In this approach, the active matrix has integrated thin-film amplifiers and readout electronics at each pixel and is called the amplified pixel detector array (APDA). Each amplified pixel consists of three thin-film transistors: an amplifier, a readout, and a reset TFT. The performance of the APDA approach compared to the conventional active matrix was investigated for two semiconductors commonly used to construct active matrix arrays--hydrogenated amorphous silicon and polycrystalline silicon. The results showed that with amplification close to the pixel, the noise from the external charge preamplifiers becomes insignificant. The thermal and flicker noise of the readout and the amplifying TFTs at the pixel become the dominant sources of noise. The magnitude of these noise sources is strongly dependent on the TFT geometry and its fabrication process. Both of these could be optimized to make the APDA active matrix operate at lower noise levels than is possible with the conventional approach. However, the APDA cannot be made to operate ideally (i.e., have noise limited only by the amount of radiation used) at the lowest exposure rate required in medical fluoroscopy.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Transparent Fingerprint Sensor System for Large Flat Panel Display.

PubMed

Seo, Wonkuk; Pi, Jae-Eun; Cho, Sung Haeung; Kang, Seung-Youl; Ahn, Seong-Deok; Hwang, Chi-Sun; Jeon, Ho-Sik; Kim, Jong-Uk; Lee, Myunghee

2018-01-19

In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 μm × 50 μm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger's ridges and valleys through the fingerprint sensor array.

Transparent Fingerprint Sensor System for Large Flat Panel Display

PubMed Central

Seo, Wonkuk; Pi, Jae-Eun; Cho, Sung Haeung; Kang, Seung-Youl; Ahn, Seong-Deok; Hwang, Chi-Sun; Jeon, Ho-Sik; Kim, Jong-Uk

2018-01-01

In this paper, we introduce a transparent fingerprint sensing system using a thin film transistor (TFT) sensor panel, based on a self-capacitive sensing scheme. An armorphousindium gallium zinc oxide (a-IGZO) TFT sensor array and associated custom Read-Out IC (ROIC) are implemented for the system. The sensor panel has a 200 × 200 pixel array and each pixel size is as small as 50 μm × 50 μm. The ROIC uses only eight analog front-end (AFE) amplifier stages along with a successive approximation analog-to-digital converter (SAR ADC). To get the fingerprint image data from the sensor array, the ROIC senses a capacitance, which is formed by a cover glass material between a human finger and an electrode of each pixel of the sensor array. Three methods are reviewed for estimating the self-capacitance. The measurement result demonstrates that the transparent fingerprint sensor system has an ability to differentiate a human finger’s ridges and valleys through the fingerprint sensor array. PMID:29351218

Convolving optically addressed VLSI liquid crystal SLM

NASA Astrophysics Data System (ADS)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays.

PubMed

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-11-07

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.

EHW Approach to Temperature Compensation of Electronics

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Current progress and technical challenges of flexible liquid crystal displays

NASA Astrophysics Data System (ADS)

Fujikake, Hideo; Sato, Hiroto

2009-02-01

We focused on several technical approaches to flexible liquid crystal (LC) display in this report. We have been developing flexible displays using plastic film substrates based on polymer-dispersed LC technology with molecular alignment control. In our representative devices, molecular-aligned polymer walls keep plastic-substrate gap constant without LC alignment disorder, and aligned polymer networks create monostable switching of fast-response ferroelectric LC (FLC) for grayscale capability. In the fabrication process, a high-viscosity FLC/monomer solution was printed, sandwiched and pressed between plastic substrates. Then the polymer walls and networks were sequentially formed based on photo-polymerization-induced phase separation in the nematic phase by two exposure processes of patterned and uniform ultraviolet light. The two flexible backlight films of direct illumination and light-guide methods using small three-primary-color light-emitting diodes were fabricated to obtain high-visibility display images. The fabricated flexible FLC panels were driven by external transistor arrays, internal organic thin film transistor (TFT) arrays, and poly-Si TFT arrays. We achieved full-color moving-image displays using the flexible FLC panel and the flexible backlight film based on field-sequential-color driving technique. Otherwise, for backlight-free flexible LC displays, flexible reflective devices of twisted guest-host nematic LC and cholesteric LC were discussed with molecular-aligned polymer walls. Singlesubstrate device structure and fabrication method using self-standing polymer-stabilized nematic LC film and polymer ceiling layer were also proposed for obtaining LC devices with excellent flexibility.

Amorphous silicon thin film transistor active-matrix organic light-emitting diode displays fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Nichols, Jonathan A.

Organic light-emitting diode (OLED) displays are of immense interest because they have several advantages over liquid crystal displays, the current dominant flat panel display technology. OLED displays are emissive and therefore are brighter, have a larger viewing angle, and do not require backlights and filters, allowing thinner, lighter, and more power efficient displays. The goal of this work was to advance the state-of-the-art in active-matrix OLED display technology. First, hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) active-matrix OLED pixels and arrays were designed and fabricated on glass substrates. The devices operated at low voltages and demonstrated that lower performance TFTs could be utilized in active-matrix OLED displays, possibly allowing lower cost processing and the use of polymeric substrates. Attempts at designing more control into the display at the pixel level were also made. Bistable (one bit gray scale) active-matrix OLED pixels and arrays were designed and fabricated. Such pixels could be used in novel applications and eventually help reduce the bandwidth requirements in high-resolution and large-area displays. Finally, a-Si:H TFT active-matrix OLED pixels and arrays were fabricated on a polymeric substrate. Displays fabricated on a polymeric substrates would be lightweight; flexible, more rugged, and potentially less expensive to fabricate. Many of the difficulties associated with fabricating active-matrix backplanes on flexible substrates were studied and addressed.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-based Current Amplifier

PubMed Central

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2015-01-01

Purpose To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. Methods The resonant detection coil is connected in parallel with the gate of a HEMT transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor’s source to a negative resistance on its gate. Results High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 µW, 14 dB gain was obtained with excellent noise performance. Conclusion An integrated current amplifier based on a High Electron Mobility Transistor (HEMT) can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. PMID:26192998

Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes

NASA Astrophysics Data System (ADS)

Shauly, Eitan; Parag, Allon; Khmaisy, Hafez; Krispil, Uri; Adan, Ofer; Levi, Shimon; Latinski, Sergey; Schwarzband, Ishai; Rotstein, Israel

2011-04-01

A fully automated system for process variability analysis of high density standard cell was developed. The system consists of layout analysis with device mapping: device type, location, configuration and more. The mapping step was created by a simple DRC run-set. This database was then used as an input for choosing locations for SEM images and for specific layout parameter extraction, used by SPICE simulation. This method was used to analyze large arrays of standard cell blocks, manufactured using Tower TS013LV (Low Voltage for high-speed applications) Platforms. Variability of different physical parameters like and like Lgate, Line-width-roughness and more as well as of electrical parameters like drive current (Ion), off current (Ioff) were calculated and statistically analyzed, in order to understand the variability root cause. Comparison between transistors having the same W/L but with different layout configurations and different layout environments (around the transistor) was made in terms of performances as well as process variability. We successfully defined "robust" and "less-robust" transistors configurations, and updated guidelines for Design-for-Manufacturing (DfM).

Ultra-high mobility transparent organic thin film transistors grown by an off-centre spin-coating method.

PubMed

Yuan, Yongbo; Giri, Gaurav; Ayzner, Alexander L; Zoombelt, Arjan P; Mannsfeld, Stefan C B; Chen, Jihua; Nordlund, Dennis; Toney, Michael F; Huang, Jinsong; Bao, Zhenan

2014-01-01

Organic semiconductors with higher carrier mobility and better transparency have been actively pursued for numerous applications, such as flat-panel display backplane and sensor arrays. The carrier mobility is an important figure of merit and is sensitively influenced by the crystallinity and the molecular arrangement in a crystal lattice. Here we describe the growth of a highly aligned meta-stable structure of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) from a blended solution of C8-BTBT and polystyrene by using a novel off-centre spin-coating method. Combined with a vertical phase separation of the blend, the highly aligned, meta-stable C8-BTBT films provide a significantly increased thin film transistor hole mobility up to 43 cm(2) Vs(-1) (25 cm(2) Vs(-1) on average), which is the highest value reported to date for all organic molecules. The resulting transistors show high transparency of >90% over the visible spectrum, indicating their potential for transparent, high-performance organic electronics.

Large-area fabrication of patterned ZnO-nanowire arrays using light stamping lithography.

PubMed

Hwang, Jae K; Cho, Sangho; Seo, Eun K; Myoung, Jae M; Sung, Myung M

2009-12-01

We demonstrate selective adsorption and alignment of ZnO nanowires on patterned poly(dimethylsiloxane) (PDMS) thin layers with (aminopropyl)siloxane self-assembled monolayers (SAMs). Light stamping lithography (LSL) was used to prepare patterned PDMS thin layers as neutral passivation regions on Si substrates. (3-Aminopropyl)triethoxysilane-based SAMs were selectively formed only on regions exposing the silanol groups of the Si substrates. The patterned positively charged amino groups define and direct the selective adsorption of ZnO nanowires with negative surface charges in the protic solvent. This procedure can be adopted in automated printing machines that generate patterned ZnO-nanowire arrays on large-area substrates. To demonstrate its usefulness, the LSL method was applied to prepare ZnO-nanowire transistor arrays on 4-in. Si wafers.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer.

PubMed

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V A L

2013-03-07

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al(2)O(3)) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al(2)O(3) dielectric layer) could be potentially integrated with large area flexible electronics.

Spray-coated carbon nanotube thin-film transistors with striped transport channels

NASA Astrophysics Data System (ADS)

Jeong, Minho; Lee, Kunhak; Choi, Eunsuk; Kim, Ahsung; Lee, Seung-Beck

2012-12-01

We present results for the transfer characteristics of carbon nanotube thin-film transistors (CNT-TFTs) that utilize single-walled carbon nanotube thin-films prepared by direct spray-coating on the substrate. By varying the number of spray-coatings (Nsp) and the concentration of nanotubes in solution (CNT), it was possible to control the conductivity of the spray-coated nanotube thin-film from 129 to 0.1 kΩ/□. Also, by introducing stripes into the channel of the CNT-TFT, and thereby reducing the number of metallic percolation paths between source and drain, it was possible to enhance the on/off current ratio 1000-fold, from 10 to 104, demonstrating that it may be possible to utilize spray-coating as a method to fabricate CNT-TFTs for large area switching array applications.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

PubMed Central

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-01-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation. PMID:27645425

The bipolar silicon microstrip detector: A proposal for a novel precision tracking device

NASA Astrophysics Data System (ADS)

Horisberger, R.

1990-03-01

It is proposed to combine the technology of fully depleted silicon microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. Teh resulting structure has amplifying properties and is referred to as bipolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

NASA satellite communications application research, phase 2 addendum. Efficient high power, solid state amplifier for EHF communications

NASA Technical Reports Server (NTRS)

Benet, James

1994-01-01

This document is an addendum to the NASA Satellite Communications Application Research (SCAR) Phase 2 Final Report, 'Efficient High Power, Solid State Amplifier for EHF Communications.' This report describes the work performed from 1 August 1993 to 11 March 1994, under contract number NASW-4513. During this reporting period an array of transistor amplifiers was repaired by replacing all MMIC amplifier chips. The amplifier array was then tested using three different feedhorn configurations. Descriptions, procedures, and results of this testing are presented in this report, and conclusions are drawn based on the test results obtained.

Impedance spectroscopy with field-effect transistor arrays for the analysis of anti-cancer drug action on individual cells.

PubMed

Susloparova, A; Koppenhöfer, D; Vu, X T; Weil, M; Ingebrandt, S

2013-02-15

In this study, impedance spectroscopy measurements of silicon-based open-gate field-effect transistor (FET) devices were utilized to study the adhesion status of cancer cells at a single cell level. We developed a trans-impedance amplifier circuit for the FETs with a higher bandwidth compared to a previously described system. The new system was characterized with a fast lock-in amplifier, which enabled measuring of impedance spectra up to 50 MHz. We studied cellular activities, including cell adhesion and anti-cancer drug induced apoptosis of human embryonic kidney (HEK293) and human lung adenocarcinoma epithelial (H441) cells. A well-known chemotherapeutic drug, topotecan hydrochloride, was used to investigate the effect of this drug to tumor cells cultured on the FET devices. The presence of the drug resulted in a 20% change in the amplitude of the impedance spectra at 200 kHz as a result of the induced apoptosis process. Real-time impedance measurements were performed inside an incubator at a constant frequency. The experimental results can be interpreted with an equivalent electronic circuit to resolve the influence of the system parameters. The developed method could be applied for the analysis of the specificity and efficacy of novel anti-cancer drugs in cancer therapy research on a single cell level in parallelized measurements. Copyright © 2012 Elsevier B.V. All rights reserved.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

Guided growth of horizontal GaN nanowires on quartz and their transfer to other substrates.

PubMed

Goren-Ruck, Lior; Tsivion, David; Schvartzman, Mark; Popovitz-Biro, Ronit; Joselevich, Ernesto

2014-03-25

The guided growth of horizontal nanowires has so far been demonstrated on a limited number of substrates. In most cases, the nanowires are covalently bonded to the substrate where they grow and cannot be transferred to other substrates. Here we demonstrate the guided growth of well-aligned horizontal GaN nanowires on quartz and their subsequent transfer to silicon wafers by selective etching of the quartz while maintaining their alignment. The guided growth was observed on different planes of quartz with varying degrees of alignment. We characterized the crystallographic orientations of the nanowires and proposed a new mechanism of "dynamic graphoepitaxy" for their guided growth on quartz. The transfer of the guided nanowires enabled the fabrication of back-gated field-effect transistors from aligned nanowire arrays on oxidized silicon wafers and the production of crossbar arrays. The guided growth of transferrable nanowires opens up the possibility of massively parallel integration of nanowires into functional systems on virtually any desired substrate.

Development of a unit cell for a Ge:Ga detector array

NASA Technical Reports Server (NTRS)

1988-01-01

Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.

Sn nanothreads in GaAs: experiment and simulation

NASA Astrophysics Data System (ADS)

Semenikhin, I.; Vyurkov, V.; Bugaev, A.; Khabibullin, R.; Ponomarev, D.; Yachmenev, A.; Maltsev, P.; Ryzhii, M.; Otsuji, T.; Ryzhii, V.

2016-12-01

The gated GaAs structures like the field-effect transistor with the array of the Sn nanothreads was fabricated via delta-doping of vicinal GaAs surface by Sn atoms with a subsequent regrowth. That results in the formation of the chains of Sn atoms at the terrace edges. Two device models were developed. The quantum model accounts for the quantization of the electron energy spectrum in the self-consistent two-dimensional electric potential, herewith the electron density distribution in nanothread arrays for different gate voltages is calculated. The classical model ignores the quantization and electrons are distributed in space according to 3D density of states and Fermi-Dirac statistics. It turned out that qualitatively both models demonstrate similar behavior, nevertheless, the classical one is in better quantitative agreement with experimental data. Plausibly, the quantization could be ignored because Sn atoms are randomly placed along the thread axis. The terahertz hot-electron bolometers (HEBs) could be based on the structure under consideration.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Intrinsic evolution of controllable oscillators in FPTA-2

NASA Technical Reports Server (NTRS)

Sekanina, Lukas; Zebulum, Ricardo S.

2005-01-01

Simple one- and two-bit controllable oscillators were intrinsically evolved using only four cells of Field Programmable Transistor Array (FPTA-2). These oscillators can produce different oscillations for different setting of control signals. Therefore, they could be used, in principle, to compose complex networks of oscillators that could exhibit rich dynamical behavior in order to perform a computation or to model a desired system.

Fabrication of an X-Ray Imaging Detector

NASA Technical Reports Server (NTRS)

Alcorn, G. E.; Burgess, A. S.

1986-01-01

X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.

Standard Transistor Array (Star): SIMLOG/TESTGN programmer's guide, volume 2, addendum 2

NASA Technical Reports Server (NTRS)

Carroll, B. D.

1979-01-01

A brief introduction to the SIMLOG/TESTGN system of programs is given. SIMLOG is a logic simulation program, whereas TESTGN is a program for generating test sequences from output produced by SIMLOG. The structures of the two programs are described. Data base, main program, and subprogram details are also given. Guidelines for program modifications are discussed. Commented program listings are included.

Two-dimensional array of cold-electron bolometers for high-sensitivity polarization measurements

NASA Astrophysics Data System (ADS)

Kuzmin, L. S.

2012-01-01

A new concept of a two-dimensional array of cold-electron bolometers with distributed dipole antennas in the focal plane for high-sensitivity polarization measurements is proposed. The concept gives a unique combination of high polarization resolution due to a large uniforms array of cold-electron bolometers and optimal matching with junction field effect transistor (JFET) amplifiers because of flexibility in direct-current connections. The noise characteristics are improved due to arriving-signal power distribution among numerous cold-electron bolometers and an increase in their response. This should lead to a significant increase in the sensitivity and dynamic range compared with competing alternative bolometer technologies. The reliability of the twodimensional array significantly increases due to a series-parallel connection of a large number of cold-electron bolometers. High polarization resolution should be ensured due to uniform covering of a substrate by a two-dimensional array over a large area and the absence of the beam compression to small lumped elements. The fundamental sensitivity limit of the cold-electron bolometer array is smaller than photon noise which is considered to be the ultimate level restricted by the background radiation. Estimates of noise of bolometers with the JFET reading system show the possibility of realizing the ultimate sensitivity below the photon-noise level 5 ・10-17 W/Hz1/2 at a frequency of 350 GHz for an optical load with a power of 5 pW. These parameters correspond to the requirements to the receiving system of a BOOMERanG balloon telescope.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Nanowire active-matrix circuitry for low-voltage macroscale artificial skin.

PubMed

Takei, Kuniharu; Takahashi, Toshitake; Ho, Johnny C; Ko, Hyunhyub; Gillies, Andrew G; Leu, Paul W; Fearing, Ronald S; Javey, Ali

2010-10-01

Large-scale integration of high-performance electronic components on mechanically flexible substrates may enable new applications in electronics, sensing and energy. Over the past several years, tremendous progress in the printing and transfer of single-crystalline, inorganic micro- and nanostructures on plastic substrates has been achieved through various process schemes. For instance, contact printing of parallel arrays of semiconductor nanowires (NWs) has been explored as a versatile route to enable fabrication of high-performance, bendable transistors and sensors. However, truly macroscale integration of ordered NW circuitry has not yet been demonstrated, with the largest-scale active systems being of the order of 1 cm(2) (refs 11,15). This limitation is in part due to assembly- and processing-related obstacles, although larger-scale integration has been demonstrated for randomly oriented NWs (ref. 16). Driven by this challenge, here we demonstrate macroscale (7×7 cm(2)) integration of parallel NW arrays as the active-matrix backplane of a flexible pressure-sensor array (18×19 pixels). The integrated sensor array effectively functions as an artificial electronic skin, capable of monitoring applied pressure profiles with high spatial resolution. The active-matrix circuitry operates at a low operating voltage of less than 5 V and exhibits superb mechanical robustness and reliability, without performance degradation on bending to small radii of curvature (2.5 mm) for over 2,000 bending cycles. This work presents the largest integration of ordered NW-array active components, and demonstrates a model platform for future integration of nanomaterials for practical applications.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Electrical and Optical Characterization of Nanowire based Semiconductor Devices

NASA Astrophysics Data System (ADS)

Ayvazian, Talin

This research project is focused on a new strategy for the creation of nanowire based semiconductor devices. The main goal is to understand and optimize the electrical and optical properties of two types of nanoscale devices; in first type lithographically patterned nanowire electrodeposition (LPNE) method has been utilized to fabricate nanowire field effect transistors (NWFET) and second type involved the development of light emitting semiconductor nanowire arrays (NWLED). Field effect transistors (NWFETs) have been prepared from arrays of polycrystalline cadmium selenide (pc-CdSe) nanowires using a back gate configuration. pc-CdSe nanowires were fabricated using the lithographically patterned nanowire electrode- position (LPNE) process on SiO2 /Si substrates. After electrodeposition, pc-CdSe nanowires were thermally annealed at 300 °C x 4 h either with or without exposure to CdCl 2 in methanol a grain growth promoter. The influence of CdCl2 treatment was to increase the mean grain diameter as determined by X-ray diffraction pattern and to convert the crystal structure from cubic to wurtzite. Transfer characteristics showed an increase of the field effect mobility (mu eff) by an order of magnitude and increase of the Ion/I off ratio by a factor of 3-4. Light emitting devices (NW-LED) based on lithographically patterned pc-CdSe nanowire arrays have been investigated. Electroluminescence (EL) spectra of CdSe nanowires under various biases exhibited broad emission spectra centered at 750 nm close to the band gap of CdSe (1.7eV). To enhance the intensity of the emitted light and the external quantum efficiency (EQE), the distance between the contacts were reduced from 5 mum to less than 1 mum which increased the efficiency by an order of magnitude. Also, increasing the annealing temperature of nanowires from 300 °C x4 h to 450 This research project is focused on a new strategy for the creation of nanowire based semiconductor devices. The main goal is to understand and optimize the electrical and optical properties of two types of nanoscale devices; in first type lithographically patterned nanowire electrodeposition (LPNE) method has been utilized to fabricate nanowire field effect transistors (NWFET) and second type involved the development of light emitting semiconductor nanowire arrays (NWLED). Field effect transistors (NWFETs) have been prepared from arrays of polycrystalline cadmium selenide (pc-CdSe) nanowires using a back gate configuration. pc-CdSe nanowires were fabricated using the lithographically patterned nanowire electrode- position (LPNE) process on SiO2 /Si substrates. After electrodeposition, pc-CdSe nanowires were thermally annealed at 300 °C x 4 h either with or without exposure to CdCl2 in methanol- a grain growth promoter. The influence of CdCl2 treatment was to increase the mean grain diameter as determined by X-ray diffraction pattern and to convert the crystal structure from cubic to wurtzite. Transfer characteristics showed an increase of the field effect mobility (mueff<) by an order of magnitude and increase of the Ion/Ioff ratio by a factor of 3-4. Light emitting devices (NW-LED) based on lithographically patterned pc-CdSe nanowire arrays have been investigated. Electroluminescence (EL) spectra of CdSe nanowires under various biases exhibited broad emission spectra centered at 750 nm close to the band gap of CdSe (1.7eV). To enhance the intensity of the emitted light and the external quantum efficiency (EQE), the distance between the contacts were reduced from 5 mum to less than 1 mum which increased the efficiency by an order of magnitude. Also, increasing the annealing temperature of nanowires from 300 °C x4 h to 450 °C x 1h enhanced grain growth confirmed by structural characterization including X-ray diffraction (XRD), Scanning electron microscopy (SEM) and Raman Spectroscopy. Correspondingly the light emission intensity and EQE improved due to this grain growth. Kelvin probe force microscopy (KPFM) was utilized to understand mechanism of light emission in CdSe nanowires. Arrays of CdTe nanowires were electrodeposited using LPNE process where the elec- trodeposition of pc-CdTe was carried out at two temperatures: 20 °C (cold) and 55 °C (hot). Transmission electron microscopy (TEM) and X-ray diffraction (XRD) re- sults revealed higher crystallinity, larger grain size and presence of Te for nanowires prepared at 55°C compared to nanowires deposited at 20°C. Nanowires prepared at 55°C showed higher electrical conductivity and enhanced electroluminescence proper- ties, including higher light emission intensity and improved External Quantum Efficiency (EQE). Electrical conduction mechanism also investigated for CdTe nanowires. Thermionic emission over schottky barrier height was identified as the dominant charge transport mechanism in pc-CdTe nanowires.°C x 1h enhanced grain growth confirmed by structural characterization including X-ray diffraction (XRD), Scanning electron microscopy (SEM) and Raman Spectroscopy. Correspondingly the light emission intensity and EQE improved due to this grain growth. Kelvin probe force microscopy (KPFM) was utilized to understand mechanism of light emission in CdSe nanowires. Arrays of CdTe nanowires were electrodeposited using LPNE process where the electrodeposition of pc-CdTe was carried out at two temperatures: 20 °C (cold) and 55 °C (hot). Transmission electron microscopy (TEM) and X-ray diffraction (XRD) re- sults revealed higher crystallinity, larger grain size and presence of Te for nanowires prepared at 55°C compared to nanowires deposited at 20°C. Nanowires prepared at 55°C showed higher electrical conductivity and enhanced electroluminescence properties, including higher light emission intensity and improved External Quantum Efficiency (EQE). Electrical conduction mechanism also investigated for CdTe nanowires. Thermionic emission over schottky barrier height was identified as the dominant charge transport mechanism in pc-CdTe nanowires.

N Channel JFET Based Digital Logic Gate Structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Scalable graphene aptasensors for drug quantification

NASA Astrophysics Data System (ADS)

Vishnubhotla, Ramya; Ping, Jinglei; Gao, Zhaoli; Lee, Abigail; Saouaf, Olivia; Vrudhula, Amey; Johnson, A. T. Charlie

2017-11-01

Simpler and more rapid approaches for therapeutic drug-level monitoring are highly desirable to enable use at the point-of-care. We have developed an all-electronic approach for detection of the HIV drug tenofovir based on scalable fabrication of arrays of graphene field-effect transistors (GFETs) functionalized with a commercially available DNA aptamer. The shift in the Dirac voltage of the GFETs varied systematically with the concentration of tenofovir in deionized water, with a detection limit less than 1 ng/mL. Tests against a set of negative controls confirmed the specificity of the sensor response. This approach offers the potential for further development into a rapid and convenient point-of-care tool with clinically relevant performance.

Simulation analysis of rectifying microfluidic mixing with field-effect-tunable electrothermal induced flow.

PubMed

Liu, Weiyu; Ren, Yukun; Tao, Ye; Yao, Bobin; Li, You

2018-03-01

We report herein field-effect control on in-phase electrothermal streaming from a theoretical point of view, a phenomenon termed "alternating-current electrothermal-flow field effect transistor" (ACET-FFET), in the context of a new technology for handing analytes in microfluidics. Field-effect control through a gate terminal endows ACET-FFET the ability to generate arbitrary symmetry breaking in the transverse vortex flow pattern, which makes it attractive for mixing microfluidic samples. A computational model is developed to study the feasibility of this new microfluidic device design for micromixing. The influence of various parameters on developing an efficient mixer is investigated, and an integrated layout of discrete electrode array is suggested for achieving high-throughput mixing. Our physical demonstration with field-effect electrothermal flow control using a simple electrode structure proves invaluable for designing active micromixers for modern micro total analytical system. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V. A. L.

2013-02-01

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics.The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics. Electronic supplementary information (ESI) available: UV-vis spectrum of Au nanoparticle aqueous solution, transfer characteristics of the transistors without inserting an Au nanoparticle monolayer, AFM image of the pentacene layer, transfer characteristics at different program voltages and memory windows with respect to the P/E voltage. See DOI: 10.1039/c2nr32579a

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

Graphene FETs Based on High Resolution Nanoribbons for HF Low Power Applications

NASA Astrophysics Data System (ADS)

Mele, David; Mehdhbi, Sarah; Fadil, Dalal; Wei, Wei; Ouerghi, Abdelkarim; Lepilliet, Sylvie; Happy, Henri; Pallecchi, Emiliano

2018-03-01

In this paper we present high frequency field effect transistors based on graphene nanoribbons arrays (GNRFETs). The nanoribbons serve as a channel for the transistors and are fabricated with a process based on e-beam lithography and dry etching of high mobility hydrogen intercalated epitaxial graphene. The widths of the nanoribbons vary from 50 to 20 nm, less than half those measured in previous reports for GNRFETs. Hall measurements reveal that the devices are p-doped, with mobility on the order of 2300 cm2/Vs. From DC characteristics, we find that the maximum ratio IMAX/IMIN is 5 obtained at 50 nm ribbons width. The IV characteristics of the GNRFETs are slightly non-linear at high bias without a full saturation. Therefore, despite the aggressive scaling of the graphene nanoribbon width, a bandgap is still not observed in our measurements. The high frequency performances of our GNRFETs are already significant at low bias. At 300 mV drain source voltage, the highest intrinsic (extrinsic) cut-off frequency ft reaches 82 (18) GHz and the extrinsic maximum oscillation frequency fmax is 20 GHz, which is promising for low power applications.

Enzymatic glucose detection using ZnO nanorods on the gate region of AlGaN /GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Wang, H. T.; Ren, F.; Pearton, S. J.; Morey, T. E.; Dennis, D. M.; Johnson, J. W.; Rajagopal, P.; Roberts, J. C.; Piner, E. L.; Linthicum, K. J.

2007-12-01

ZnO nanorod-gated AlGaN /GaN high electron mobility transistors (HEMTs) are demonstrated for the detection of glucose. A ZnO nanorod array was selectively grown on the gate area using low temperature hydrothermal decomposition to immobilize glucose oxidase (GOx). The one-dimensional ZnO nanorods provide a large effective surface area with high surface-to-volume ratio and provide a favorable environment for the immobilization of GOx. The AlGaN /GaN HEMT drain-source current showed a rapid response of less than 5s when target glucose in a buffer with a pH value of 7.4 was added to the GOx immobilized on the ZnO nanorod surface. We could detect a wide range of concentrations from 0.5nMto125μM. The sensor exhibited a linear range from 0.5nMto14.5μM and an experiment limit of detection of 0.5nM. This demonstrates the possibility of using AlGaN /GaN HEMTs for noninvasive exhaled breath condensate based glucose detection of diabetic application.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Multiscale examination and modeling of electron transport in nanoscale materials and devices

NASA Astrophysics Data System (ADS)

Banyai, Douglas R.

For half a century the integrated circuits (ICs) that make up the heart of electronic devices have been steadily improving by shrinking at an exponential rate. However, as the current crop of ICs get smaller and the insulating layers involved become thinner, electrons leak through due to quantum mechanical tunneling. This is one of several issues which will bring an end to this incredible streak of exponential improvement of this type of transistor device, after which future improvements will have to come from employing fundamentally different transistor architecture rather than fine tuning and miniaturizing the metal-oxide-semiconductor field effect transistors (MOSFETs) in use today. Several new transistor designs, some designed and built here at Michigan Tech, involve electrons tunneling their way through arrays of nanoparticles. We use a multi-scale approach to model these devices and study their behavior. For investigating the tunneling characteristics of the individual junctions, we use a first-principles approach to model conduction between sub-nanometer gold particles. To estimate the change in energy due to the movement of individual electrons, we use the finite element method to calculate electrostatic capacitances. The kinetic Monte Carlo method allows us to use our knowledge of these details to simulate the dynamics of an entire device---sometimes consisting of hundreds of individual particles---and watch as a device 'turns on' and starts conducting an electric current. Scanning tunneling microscopy (STM) and the closely related scanning tunneling spectroscopy (STS) are a family of powerful experimental techniques that allow for the probing and imaging of surfaces and molecules at atomic resolution. However, interpretation of the results often requires comparison with theoretical and computational models. We have developed a new method for calculating STM topographs and STS spectra. This method combines an established method for approximating the geometric variation of the electronic density of states, with a modern method for calculating spin-dependent tunneling currents, offering a unique balance between accuracy and accessibility.

1990 MTT-S International Microwave Symposium and Exhibition and Microwave and Millimeter-Wave Monolithic IC Symposium, Dallas, TX, May 7-10, 1990, Proceedings

NASA Astrophysics Data System (ADS)

McQuiddy, David N., Jr.; Sokolov, Vladimir

1990-12-01

The present conference discusses microwave filters, lightwave technology for microwave antennas, planar and quasi-planar guides, mixers and VCOs, cavity filters, discontinuity and coupling effects, control circuits, power dividers and phase shifters, microwave ICs, biological effects and medical applications, CAD and modeling for MMICs, directional couplers, MMIC design trends, microwave packaging and manufacturing, monolithic ICs, and solid-state devices and circuits. Also discussed are microwave and mm-wave superconducting technology, MICs for communication systems, the merging of optical and microwave technologies, microwave power transistors, ferrite devices, network measurements, advanced transmission-line structures, FET devices and circuits, field theory of IC discontinuities, active quasi-optical techniques, phased-array techniques and circuits, nonlinear CAD, sub-mm wave devices, and high power devices.

Methods for growth of relatively large step-free SiC crystal surfaces

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor); Powell, J. Anthony (Inventor)

2002-01-01

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Label-free electrical detection of pyrophosphate generated from DNA polymerase reactions on field-effect devices.

PubMed

Credo, Grace M; Su, Xing; Wu, Kai; Elibol, Oguz H; Liu, David J; Reddy, Bobby; Tsai, Ta-Wei; Dorvel, Brian R; Daniels, Jonathan S; Bashir, Rashid; Varma, Madoo

2012-03-21

We introduce a label-free approach for sensing polymerase reactions on deoxyribonucleic acid (DNA) using a chelator-modified silicon-on-insulator field-effect transistor (SOI-FET) that exhibits selective and reversible electrical response to pyrophosphate anions. The chemical modification of the sensor surface was designed to include rolling-circle amplification (RCA) DNA colonies for locally enhanced pyrophosphate (PPi) signal generation and sensors with immobilized chelators for capture and surface-sensitive detection of diffusible reaction by-products. While detecting arrays of enzymatic base incorporation reactions is typically accomplished using optical fluorescence or chemiluminescence techniques, our results suggest that it is possible to develop scalable and portable PPi-specific sensors and platforms for broad biomedical applications such as DNA sequencing and microbe detection using surface-sensitive electrical readout techniques.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

PubMed Central

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Direct observation of single-charge-detection capability of nanowire field-effect transistors.

PubMed

Salfi, J; Savelyev, I G; Blumin, M; Nair, S V; Ruda, H E

2010-10-01

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

A Thermally Powered ISFET Array for On-Body pH Measurement.

PubMed

Douthwaite, Matthew; Koutsos, Ermis; Yates, David C; Mitcheson, Paul D; Georgiou, Pantelis

2017-12-01

Recent advances in electronics and electrochemical sensors have led to an emerging class of next generation wearables, detecting analytes in biofluids such as perspiration. Most of these devices utilize ion-selective electrodes (ISEs) as a detection method; however, ion-sensitive field-effect transistors (ISFETs) offer a solution with improved integration and a low power consumption. This work presents a wearable, thermoelectrically powered system composed of an application-specific integrated circuit (ASIC), two commercial power management integrated circuits and a network of commercial thermoelectric generators (TEGs). The ASIC is fabricated in 0.35 m CMOS and contains an ISFET array designed to read pH as a current, a processing module which averages the signal to reduce noise and encodes it into a frequency, and a transmitter. The output frequency has a measured sensitivity of 6 to 8 kHz/pH for a pH range of 7-5. It is shown that the sensing array and processing module has a power consumption 6 W and, therefore, can be entirely powered by body heat using a TEG. Array averaging is shown to reduce noise at these low power levels to 104 V (input referred integrated noise), reducing the minimum detectable limit of the ASIC to 0.008 pH units. The work forms the foundation and proves the feasibility of battery-less, on-body electrochemical for perspiration analysis in sports science and healthcare applications.

High-mobility field-effect transistor based on crystalline ZnSnO3 thin films

NASA Astrophysics Data System (ADS)

Minato, Hiroya; Fujiwara, Kohei; Tsukazaki, Atsushi

2018-05-01

We propose crystalline ZnSnO3 as a new channel material for field-effect transistors. By molecular-beam epitaxy on LiNbO3(0001) substrates, we synthesized films of ZnSnO3, which crystallizes in the LiNbO3-type polar structure. Field-effect transistors on ZnSnO3 exhibit n-type operation with field-effect mobility of as high as 45 cm2V-1s-1 at room temperature. Systematic examination of the transistor operation for channels with different Zn/Sn compositional ratios revealed that the observed high-mobility reflects the nature of stoichiometric ZnSnO3 phase. Moreover, we found an indication of coupling of transistor characteristics with intrinsic spontaneous polarization in ZnSnO3, potentially leading to a distinct type of polarization-induced conduction.

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

DOEpatents

Turner, Steven Richard

2006-12-26

A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

Electrical Characterization of Signal Processing Microcircuit

DTIC Science & Technology

1989-04-01

Transistor Array 14 Liner Microcircuits Analog Switches Analog MUX Device Characterization Analog Multiplexer References nS report Covere tV Whe m ^~~ 11Ur...ity Assurance Branch of the Rome Air Development Center pertainIng to the electrical characterization and MIL- M -38510 specifi- cation of analog...PAGI ELECTRICAL CHARACTERIZATION OF SIGNAL PROCESSING MICROCIRCUITS SECTION TITLE PAGE I Introduction I-i II Analog Multipliers, MIL- M -38510/139 II-i III

Hardware Evolution of Analog Speed Controllers for a DC Motor

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Ferguson, Michael I.

2003-01-01

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

NASA Technical Reports Server (NTRS)

1977-01-01

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

Nanotube antibody biosensor arrays for the detection of circulating breast cancer cells

NASA Astrophysics Data System (ADS)

Shao, Ning; Wickstrom, Eric; Panchapakesan, Balaji

2008-11-01

Recent reports have shown that nanoscale electronic devices can be used to detect a change in electrical properties when receptor proteins bind to their corresponding antibodies functionalized on the surface of the device, in extracts from as few as ten lysed tumor cells. We hypothesized that nanotube-antibody devices could sensitively and specifically detect entire live cancer cells. We report for the first time a single nanotube field effect transistor array, functionalized with IGF1R-specific and Her2-specific antibodies, which exhibits highly sensitive and selective sensing of live, intact MCF7 and BT474 human breast cancer cells in human blood. Those two cell lines both overexpress IGF1R and Her2, at different levels. Single or small bundle of nanotube devices that were functionalized with IGF1R-specific or Her2-specific antibodies showed 60% decreases in conductivity upon interaction with BT474 or MCF7 breast cancer cells in two µl drops of blood. Control experiments with non-specific antibodies or with MCF10A control breast cells produced a less than 5% decrease in electrical conductivity, illustrating the high sensitivity for whole cell binding by these single nanotube-antibody devices. We postulate that the free energy change due to multiple simultaneous cell-antibody binding events exerted stress along the nanotube surface, decreasing its electrical conductivity due to an increase in band gap. Because the free energy change upon cell-antibody binding, the stress exerted on the nanotube, and the change in conductivity are specific to a specific antigen-antibody interaction; these properties might be used as a fingerprint for the molecular sensing of circulating cancer cells. From optical microscopy observations during sensing, it appears that the binding of a single cell to a single nanotube field effect transistor produced the change in electrical conductivity. Thus we report a nanoscale oncometer with single cell sensitivity with a diameter 1000 times smaller than a cancer cell that functions in a drop of fresh blood.

Analysis of long-channel nanotube field-effect-transistors (NT FETs)

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Kwak, Dochan (Technical Monitor)

2001-01-01

This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays

NASA Astrophysics Data System (ADS)

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-10-01

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems. Electronic supplementary information (ESI) available: Electrical characterization of fabricated n- and p-type nanowires, and influence of Debye screening on PSA sensing. See DOI: 10.1039/c4nr03210a

4 Kelvin Cryogenic Characterization of Commercial pHEMT Transistors at 9 kHz to 8.5 GHz Range

NASA Astrophysics Data System (ADS)

Ibarra-Medel, E.; Velázquez, M.; Ventura, S.; Ferrusca, D.; Gómez-Rivera, V.

2016-07-01

Nowadays, the technology innovations in large format array detectors at low temperature for millimetric observational astronomy demand the development of electronics capable to keep their functionality at cryogenic temperatures. In kinetic inductance detectors, the first stage of electronics readout requires high-bandwidth low-noise amplifiers (LNAs). These devices are commonly fabricated in monolithic microwave integrated circuit (MMIC) processes which commercially achieve a noise temperature level of 5 K. An alternative approach to the MMIC are the hybrid microwave circuit which mixes RF lumped elements and discrete electronic components. This paper describes the characterization of six commercial pHEMT transistors tested at cryogenic temperatures. DC properties such as I-V curves and transconductance (g_m) were measured for each transistor; these measurements allow us to calculate the best bias point versus gain, with the lowest noise figure and power consumption within the range of 9 kHz to 8.5 GHz at the operating temperature of 4 K. Experimental results suggest that the characterized pHEMTs have a noise figure that allow them to be used in hybrid LNAs arranges with a comparable MMIC performance.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Detection of Sub-fM DNA with Target Recycling and Self-Assembly Amplification on Graphene Field-Effect Biosensors

PubMed Central

2018-01-01

All-electronic DNA biosensors based on graphene field-effect transistors (GFETs) offer the prospect of simple and cost-effective diagnostics. For GFET sensors based on complementary probe DNA, the sensitivity is limited by the binding affinity of the target oligonucleotide, in the nM range for 20 mer targets. We report a ∼20 000× improvement in sensitivity through the use of engineered hairpin probe DNA that allows for target recycling and hybridization chain reaction. This enables detection of 21 mer target DNA at sub-fM concentration and provides superior specificity against single-base mismatched oligomers. The work is based on a scalable fabrication process for biosensor arrays that is suitable for multiplexed detection. This approach overcomes the binding-affinity-dependent sensitivity of nucleic acid biosensors and offers a pathway toward multiplexed and label-free nucleic acid testing with high accuracy and selectivity. PMID:29768011

Wafer scale BN on sapphire substrates for improved graphene transport.

PubMed

Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

2018-06-11

Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

Detection of Sub-fM DNA with Target Recycling and Self-Assembly Amplification on Graphene Field-Effect Biosensors.

PubMed

Gao, Zhaoli; Xia, Han; Zauberman, Jonathan; Tomaiuolo, Maurizio; Ping, Jinglei; Zhang, Qicheng; Ducos, Pedro; Ye, Huacheng; Wang, Sheng; Yang, Xinping; Lubna, Fahmida; Luo, Zhengtang; Ren, Li; Johnson, Alan T Charlie

2018-06-13

All-electronic DNA biosensors based on graphene field-effect transistors (GFETs) offer the prospect of simple and cost-effective diagnostics. For GFET sensors based on complementary probe DNA, the sensitivity is limited by the binding affinity of the target oligonucleotide, in the nM range for 20 mer targets. We report a ∼20 000× improvement in sensitivity through the use of engineered hairpin probe DNA that allows for target recycling and hybridization chain reaction. This enables detection of 21 mer target DNA at sub-fM concentration and provides superior specificity against single-base mismatched oligomers. The work is based on a scalable fabrication process for biosensor arrays that is suitable for multiplexed detection. This approach overcomes the binding-affinity-dependent sensitivity of nucleic acid biosensors and offers a pathway toward multiplexed and label-free nucleic acid testing with high accuracy and selectivity.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

NASA Technical Reports Server (NTRS)

Shu, Peter; Waczynski, Augustyn; Kan, Emily; Wen, Yiting; Rosenberry, Robert

2012-01-01

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

A monocrystal graphene domain biosensor array with differential output for real-time monitoring of glucose and normal saline.

PubMed

Shi, Junjie; Li, Xin; Chen, Qian; Gao, Kun; Song, Hui; Guo, Shixi; Li, Quanfu; Fang, Ming; Liu, Weihua; Liu, Hongzhong; Wang, Xiaoli

2015-05-07

A biosensor array with differential output based on a monocrystal graphene domain is proposed to realize high resolution measurements. The differential output structure can eliminate the noise that comes from graphene crystal orientation and grain boundary, as well as the fluctuation that comes from the contact resistance and experiment process, so as to improve resolution in the lower concentration. We have fabricated a high quality monocrystal graphene domain that has millimeter size by the chemical vapor deposition method. Two identical graphene ribbons that are cut from the same domain are used as field effect transistor source-to-drain channels for the reference and the test of differential output, respectively. The experimental results show that the source-to-drain current has a fast response shorter than 0.5 second in glucose, normal saline and pH buffer solutions of different concentrations. Sensitivity increases exponentially with the increase of concentration of the tested liquid and the high resolution range is 0.01-2 wt% in glucose and 0.0009-0.018 wt% in saline, and the highest resolutions of glucose and saline are 0.01 wt% and 0.0009 wt%, respectively. We have fabricated a 1 × 4 array structure with differential outputs that pave the way for rapidly detecting ultra-low concentration of analytes.

Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays

NASA Astrophysics Data System (ADS)

Laborde, C.; Pittino, F.; Verhoeven, H. A.; Lemay, S. G.; Selmi, L.; Jongsma, M. A.; Widdershoven, F. P.

2015-09-01

Platforms that offer massively parallel, label-free biosensing can, in principle, be created by combining all-electrical detection with low-cost integrated circuits. Examples include field-effect transistor arrays, which are used for mapping neuronal signals and sequencing DNA. Despite these successes, however, bioelectronics has so far failed to deliver a broadly applicable biosensing platform. This is due, in part, to the fact that d.c. or low-frequency signals cannot be used to probe beyond the electrical double layer formed by screening salt ions, which means that under physiological conditions the sensing of a target analyte located even a short distance from the sensor (∼1 nm) is severely hampered. Here, we show that high-frequency impedance spectroscopy can be used to detect and image microparticles and living cells under physiological salt conditions. Our assay employs a large-scale, high-density array of nanoelectrodes integrated with CMOS electronics on a single chip and the sensor response depends on the electrical properties of the analyte, allowing impedance-based fingerprinting. With our platform, we image the dynamic attachment and micromotion of BEAS, THP1 and MCF7 cancer cell lines in real time at submicrometre resolution in growth medium, demonstrating the potential of the platform for label/tracer-free high-throughput screening of anti-tumour drug candidates.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.

PubMed

Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

2017-09-01

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

Carbon Based Transistors and Nanoelectronic Devices

NASA Astrophysics Data System (ADS)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the effect of nanotube network density was explained in detail. On the other hand, graphene transfer technology was explored here as well. Annealing techniques were utilized to deposit clean graphene on arbitrary substrates. Raman spectroscopy and Raman data analysis was used to confirm the clean process. Furthermore, suspended graphene membrane was fabricated using single and multi-layer graphene films. This can make a major impact on graphene based transistors and bio-nano sensors technology.

Medium power amplifiers covering 90 - 130 GHz for telescope local oscillators

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Bryerton, Eric; Pukala, David; Peralta, Alejandro; Hu, Ming; Schmitz, Adele

2005-01-01

This paper describes a set of power amplifier (PA) modules containing InP High Electron Mobility Transistor (HEMT) Monolithic Millimeter-wave Integrated Circuit (MMIC) chips. The chips were designed and optimized for local oscillator sources in the 90-130 GHz band for the Atacama Large Millimeter Array telescope. The modules feature 20-45 mW of output power, to date the highest power from solid state HEMT MMIC modules above 110 GHz.

Unclassified Publications of Lincoln Laboratory, 1 January-31 December 1987. Volume 13

DTIC Science & Technology

1987-12-31

Visible-Laser Photochemical Etching of Cr , Mo, and W 5901 High-Speed Electronic Beam Steering Using Injection Locking of a Laser-Diode Array...of High- Power Broad-Area Diode Lasers High-Temperature Point-Contact Transistors and Schottky Diodes Formed on Synthetic Boron- Doped Diamond...SPEECHES MS No. 593IB C02 Laser Radar 6550B Recent Advances in Transition-Metal- Doped Lasers 6714D Radiation Damage in Dry

N-Heterocyclic-Carbene-Treated Gold Surfaces in Pentacene Organic Field-Effect Transistors: Improved Stability and Contact at the Interface.

PubMed

Lv, Aifeng; Freitag, Matthias; Chepiga, Kathryn M; Schäfer, Andreas H; Glorius, Frank; Chi, Lifeng

2018-04-16

N-Heterocyclic carbenes (NHCs), which react with the surface of Au electrodes, have been successfully applied in pentacene transistors. With the application of NHCs, the charge-carrier mobility of pentacene transistors increased by five times, while the contact resistance at the pentacene-Au interface was reduced by 85 %. Even after annealing the NHC-Au electrodes at 200 °C for 2 h before pentacene deposition, the charge-carrier mobility of the pentacene transistors did not decrease. The distinguished performance makes NHCs as excellent alternatives to thiols as metal modifiers for the application in organic field-effect transistors (OFETs). © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Conducting glasses recovered from thin film transistor liquid crystal display wastes for dye-sensitized solar cell cathodes.

PubMed

Chen, C-C; Chang, F-C; Peng, C Y; Wang, H Paul

2015-01-01

Transparent conductive glasses such as thin film transistor (TFT) array and colour filter glasses were recovered from the TFT-liquid crystal display panel wastes by dismantling and sonic cleaning. Noble metals (i.e. platinum (Pt)) and indium tin oxide (ITO) are generally used in the cathode of a dye-sensitized solar cell (DSSC). To reduce the DSSC cost, Pt was replaced with nano nickel-encapsulated carbon-shell (Ni@C) nanoparticles, which were prepared by carbonization of Ni²⁺-β-cyclodextrin at 673 K for 2 h. The recovered conductive glasses were used in the DSSC electrodes in the substitution of relatively expensive ITO. Interestingly, the efficiency of the DSSC having the Ni@C-coated cathode is as high as 2.54%. Moreover, the cost of the DSSC using the recovered materials can be reduced by at least 24%.

Single Molecule Enzymology via Nanoelectronic Circuits

NASA Astrophysics Data System (ADS)

Collins, Philip

Traditional single-molecule techniques rely on fluorescence or force transduction to monitor conformational changes and biochemical activity. Recent demonstrations of single-molecule monitoring with electronic transistors are poised to add to the single-molecule research toolkit. The transistor-based technique is sensitive to the motion of single charged side chain residues and can transduce those motions with microsecond resolution, opening the doors to single-molecule enzymology with unprecedented resolution. Furthermore, the solid-state platform provides opportunities for parallelization in arrays and long-duration monitoring of one molecule's activity or processivity, all without the limitations caused by photo-oxidation or mutagenic fluorophore incorporation. This presentation will review some of these advantages and their particular application to DNA polymerase I processing single-stranded DNA templates. This research was supported financially by the NIH NCI (R01 CA133592-01), the NIH NIGMS (1R01GM106957-01) and the NSF (DMR-1104629 and ECCS-1231910).

High Resolution Displays Using NCAP Liquid Crystals

NASA Astrophysics Data System (ADS)

Macknick, A. Brian; Jones, Phil; White, Larry

1989-07-01

Nematic curvilinear aligned phase (NCAP) liquid crystals have been found useful for high information content video displays. NCAP materials are liquid crystals which have been encapsulated in a polymer matrix and which have a light transmission which is variable with applied electric fields. Because NCAP materials do not require polarizers, their on-state transmission is substantially better than twisted nematic cells. All dimensional tolerances are locked in during the encapsulation process and hence there are no critical sealing or spacing issues. By controlling the polymer/liquid crystal morphology, switching speeds of NCAP materials have been significantly improved over twisted nematic systems. Recent work has combined active matrix addressing with NCAP materials. Active matrices, such as thin film transistors, have given displays of high resolution. The paper will discuss the advantages of NCAP materials specifically designed for operation at video rates on transistor arrays; applications for both backlit and projection displays will be discussed.

An integrated micro-manipulation and biosensing platform built in glass-based LTPS TFT technology

NASA Astrophysics Data System (ADS)

Chen, Lei-Guang; Wu, Dong-Yi; S-C Lu, Michael

2012-09-01

The glass-based low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) process, widely known for making liquid crystal displays, is utilized in this work to realize a fully integrated, microbead-based micro-manipulation and biosensing platform. The operation utilizes arrays of microelectrodes made of transparent iridium tin oxide (ITO) to move the immobilized polystyrene microbeads to the sensor surface by dielectrophoresis (DEP). Detection of remaining microbeads after a specific antigen/antibody reaction is accomplished by photo-detectors under the transparent electrodes. It was found that microbeads can be driven successfully by the 30 × 30 µm2 microelectrodes separated by 10 µm with no more than 6 Vp-p, which is compatible with the operating range of thin-film transistors. Microbeads immobilized with antimouse immunoglobulin (IgG) and prostate-specific antigen (PSA) antibody were successfully detected after specific binding, illustrating the potential of LTPS TFT microarrays for more versatile biosensing applications.

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

NASA Technical Reports Server (NTRS)

MacLeod, Todd, C.; Ho, Fat Duen

2006-01-01

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Application of the Johnson criteria to graphene transistors

NASA Astrophysics Data System (ADS)

Kelly, M. J.

2013-12-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications.

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Effect of temperature on the characteristics of silicon nanowire transistor.

PubMed

Hashim, Yasir; Sidek, Othman

2012-10-01

This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a transistor. The findings reveal the negative effect of higher working temperature on the use of SiNWTs in electronic circuits, such as digital circuits and amplifiers circuits, because of the lower I(ON)/I(OFF) ratio, higher DIBL, and higher SS at higher temperature. Moreover, the ON state is the optimum condition for using a transistor as a temperature nano-sensor.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

A Transfer Hamiltonian Model for Devices Based on Quantum Dot Arrays

PubMed Central

Illera, S.; Prades, J. D.; Cirera, A.; Cornet, A.

2015-01-01

We present a model of electron transport through a random distribution of interacting quantum dots embedded in a dielectric matrix to simulate realistic devices. The method underlying the model depends only on fundamental parameters of the system and it is based on the Transfer Hamiltonian approach. A set of noncoherent rate equations can be written and the interaction between the quantum dots and between the quantum dots and the electrodes is introduced by transition rates and capacitive couplings. A realistic modelization of the capacitive couplings, the transmission coefficients, the electron/hole tunneling currents, and the density of states of each quantum dot have been taken into account. The effects of the local potential are computed within the self-consistent field regime. While the description of the theoretical framework is kept as general as possible, two specific prototypical devices, an arbitrary array of quantum dots embedded in a matrix insulator and a transistor device based on quantum dots, are used to illustrate the kind of unique insight that numerical simulations based on the theory are able to provide. PMID:25879055

A transfer hamiltonian model for devices based on quantum dot arrays.

PubMed

Illera, S; Prades, J D; Cirera, A; Cornet, A

2015-01-01

We present a model of electron transport through a random distribution of interacting quantum dots embedded in a dielectric matrix to simulate realistic devices. The method underlying the model depends only on fundamental parameters of the system and it is based on the Transfer Hamiltonian approach. A set of noncoherent rate equations can be written and the interaction between the quantum dots and between the quantum dots and the electrodes is introduced by transition rates and capacitive couplings. A realistic modelization of the capacitive couplings, the transmission coefficients, the electron/hole tunneling currents, and the density of states of each quantum dot have been taken into account. The effects of the local potential are computed within the self-consistent field regime. While the description of the theoretical framework is kept as general as possible, two specific prototypical devices, an arbitrary array of quantum dots embedded in a matrix insulator and a transistor device based on quantum dots, are used to illustrate the kind of unique insight that numerical simulations based on the theory are able to provide.

Influence of polymer dielectrics on C60-based field-effect transistors

NASA Astrophysics Data System (ADS)

Zhou, Jianlin; Zhang, Fujia; Lan, Lifeng; Wen, Shangsheng; Peng, Junbiao

2007-12-01

Fullerene C60 organic field-effect transistors (OFETs) have been fabricated based on two different polymer dielectric materials, poly(methylmethacrylate) (PMMA) and cross-linkable poly(4-vinylphenol). The large grain size of C60 film and small number of traps at the interface of PMMA /C60 were obtained with high electron mobility of 0.66cm2/Vs in the PMMA transistor. The result suggests that the C60 semiconductor cooperating with polymer dielectric is a promising application in the fabrication of n-type organic transistors because of low threshold voltage and high electron mobility.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Tactile Feedback Display with Spatial and Temporal Resolutions

PubMed Central

Vishniakou, Siarhei; Lewis, Brian W.; Niu, Xiaofan; Kargar, Alireza; Sun, Ke; Kalajian, Michael; Park, Namseok; Yang, Muchuan; Jing, Yi; Brochu, Paul; Sun, Zhelin; Li, Chun; Nguyen, Truong; Pei, Qibing; Wang, Deli

2013-01-01

We report the electronic recording of the touch contact and pressure using an active matrix pressure sensor array made of transparent zinc oxide thin-film transistors and tactile feedback display using an array of diaphragm actuators made of an interpenetrating polymer elastomer network. Digital replay, editing and manipulation of the recorded touch events were demonstrated with both spatial and temporal resolutions. Analog reproduction of the force is also shown possible using the polymer actuators, despite of the high driving voltage. The ability to record, store, edit, and replay touch information adds an additional dimension to digital technologies and extends the capabilities of modern information exchange with the potential to revolutionize physical learning, social networking, e-commerce, robotics, gaming, medical and military applications. PMID:23982053

Tactile feedback display with spatial and temporal resolutions.

PubMed

Vishniakou, Siarhei; Lewis, Brian W; Niu, Xiaofan; Kargar, Alireza; Sun, Ke; Kalajian, Michael; Park, Namseok; Yang, Muchuan; Jing, Yi; Brochu, Paul; Sun, Zhelin; Li, Chun; Nguyen, Truong; Pei, Qibing; Wang, Deli

2013-01-01

We report the electronic recording of the touch contact and pressure using an active matrix pressure sensor array made of transparent zinc oxide thin-film transistors and tactile feedback display using an array of diaphragm actuators made of an interpenetrating polymer elastomer network. Digital replay, editing and manipulation of the recorded touch events were demonstrated with both spatial and temporal resolutions. Analog reproduction of the force is also shown possible using the polymer actuators, despite of the high driving voltage. The ability to record, store, edit, and replay touch information adds an additional dimension to digital technologies and extends the capabilities of modern information exchange with the potential to revolutionize physical learning, social networking, e-commerce, robotics, gaming, medical and military applications.

Multi-oxide active layer deposition using Applied Materials Pivot array coater for high-mobility metal oxide TFT

NASA Astrophysics Data System (ADS)

Park, Hyun Chan; Scheer, Evelyn; Witting, Karin; Hanika, Markus; Bender, Marcus; Hsu, Hao Chien; Yim, Dong Kil

2015-11-01

By controlling a thin indium tin oxide (ITO), indium zinc oxide interface layer between gate insulator and indium gallium zinc oxide (IGZO), the thin-film transistor (TFT) performance can reach higher mobility as conventional IGZO as well as superior stability. For large-area display application, Applied Materials static PVD array coater (Applied Materials GmbH & Co. KG, Alzenau, Germany) using rotary targets has been developed to enable uniform thin layer deposition in display industry. Unique magnet motion parameter optimization in Pivot sputtering coater is shown to provide very uniform thin ITO layer to reach TFT performance with high mobility, not only on small scale, but also on Gen8.5 (2500 × 2200 mm glass size) production system.

Tactile Feedback Display with Spatial and Temporal Resolutions

NASA Astrophysics Data System (ADS)

Vishniakou, Siarhei; Lewis, Brian W.; Niu, Xiaofan; Kargar, Alireza; Sun, Ke; Kalajian, Michael; Park, Namseok; Yang, Muchuan; Jing, Yi; Brochu, Paul; Sun, Zhelin; Li, Chun; Nguyen, Truong; Pei, Qibing; Wang, Deli

2013-08-01

We report the electronic recording of the touch contact and pressure using an active matrix pressure sensor array made of transparent zinc oxide thin-film transistors and tactile feedback display using an array of diaphragm actuators made of an interpenetrating polymer elastomer network. Digital replay, editing and manipulation of the recorded touch events were demonstrated with both spatial and temporal resolutions. Analog reproduction of the force is also shown possible using the polymer actuators, despite of the high driving voltage. The ability to record, store, edit, and replay touch information adds an additional dimension to digital technologies and extends the capabilities of modern information exchange with the potential to revolutionize physical learning, social networking, e-commerce, robotics, gaming, medical and military applications.

Applications of Nanostructured Graphene in Optoelectronics as Transparent Conductors and Photodetectors

NASA Astrophysics Data System (ADS)

Xu, Guowei

Graphene, a single layer of carbon atoms arranged in a hexagonal lattice, has unique properties of high carrier mobility, high optical transmittance, chemical inertness and flexibility, making it attractive for electronic and optoelectronic applications, such as graphene transistors, ultrahigh capacitors, transparent conductors (TCs), photodetectors. This work explores novel schemes of nanostructured graphene for optoelectronic applications including advanced TCs and photodetectors. In nanophotonic graphene nanohole arrays patterned using nanoimprinting lithography (NIL), highly efficient chemical doping was achieved on the hole edges. This provides a unique scheme for improving both optical transmittance and electrical conductivity of graphene-based TCs. In plasmonic graphene, Ag nanoparticles were decorated on graphene using thermally assisted self-assembly and NIL. Much enhanced conductivity by a factor of 2-4 was achieved through electron doping in graphene from Ag nanoparticles. More importantly, surface plasmonic effect has been incorporated into plasmonic graphene as advanced TCs with light trapping, which is critical to ultrathin-film optoelectronics such as photovoltaics and photodetectors. Based on plasmonic graphene electric double-layer (EDL) transistor, a novel scheme of photodetection has been demonstrated using plasmonic enhanced local field gating. The resulting tuning of interfacial capacitance as well as the quantum capacitance of graphene manifested as extraordinary photoconductivity and hence photoresponse.

Theory and Device Modeling for Nano-Structured Transistor Channels

DTIC Science & Technology

2011-06-01

zinc oxide ( ZnO ) thin film transistors ( TFTs ) that contain nanocrystalline grains on the order of ~20nm. The authors of ref. 1 present results...problem in order to determine the threshold voltage. 15. SUBJECT TERMS nano-structured transistor , mesoscopic, zinc oxide , ZnO , field-effect...and R. Neidhard, “Microwave ZnO Thin - Film Transistors ”, IEEE Electron Dev. Lett. 29, 1024 (2008); doi: 10.1109/LED.2008.2001635.

AlGaSb Buffer Layers for Sb-Based Transistors

DTIC Science & Technology

2010-01-01

transistor ( HEMT ), molecular beam epitaxy (MBE), field-effect transistor (FET), buffer layer INTRODUCTION High-electron-mobility transistors ( HEMTs ) with InAs...monolayers/s. The use of thinner buffer layers reduces molecular beam epitaxial growth time and source consumption. The buffer layers also exhibit...source. In addition, some of the flux from an Sb cell in a molecular beam epitaxy (MBE) system will deposit near the mouth of the cell, eventually

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Microcircuit Reliability Bibliography. Volume 4. 1976 Annual Reference Supplement. (Document Numbers 11045-11745)

DTIC Science & Technology

1976-04-01

State Electron- Res. Lab., Eindhoven, Neth.) icw 16, no. 12, 1315-20, Dec. 1973 ATMOS-AN ELECTRICALLY REPROGRAMMABLE READ-ONLY MEMORY DEVICE. IEEE Trans...transistor is described that can be used nular and array geometry contacts by as an electrically reprogrammable read- the pr~nciple of superposition. It is...digital tuning techniques for FM and typical automobile systems can be readily television, and pocket pagers. Tn. implemented by COS1440S monolithic

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Fabrication of Electrophoretic Display Driven by Membrane Switch Array

NASA Astrophysics Data System (ADS)

Senda, Kazuo; Usui, Hiroaki

2010-04-01

Electrophoretic devices (EPDs) and organic light-emitting diodes (OLEDs) have potential application in a large-area flexible displays, such as digital signage. For this purpose, a new backplane is capable of driving a large unit is required instead of thin-film transistors. In this paper we describe the fabrication of a membrane switch array suitable for driving large-scale flat-panel displays. An array of membrane switches was prepared using flexible printed circuit (FPC) technology of polyimide films, by combining low-temperature processes of lamination and copper electroplating methods. An array of 256 matrix switches with a pixel size of 7 mm2 was prepared to drive the EPD front panel. The switches were driven at a voltage of about 40 V and a frequency of 10 Hz. The operation characteristics agreed well with the result of the theoretical calculation. The calculation also suggested that driving voltage can be lowered by increasing pixel size. The contact resistance of the membrane switch was as low as 0.2 Ω, which implies the wide applicability of this device for driving a variety of elements.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

NASA Astrophysics Data System (ADS)

Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Moreno-Cadenas, J. A.; Escobosa-Echavarría, A.

2011-03-01

In this report, the performance of a particular pixel's architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistor's aspect ratio used in the matrix array is critical for the pixel's amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2014-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2011-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Silicon Field Effect Transistors as Dual-Use Sensor-Heater Hybrids

PubMed Central

Reddy, Bobby; Elibol, Oguz H.; Nair, Pradeep R.; Dorvel, Brian R.; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2011-01-01

We demonstrate the temperature mediated applications of a previously proposed novel localized dielectric heating method on the surface of dual purpose silicon field effect transistor (FET) sensor-heaters and perform modeling and characterization of the underlying mechanisms. The FETs are first shown to operate as electrical sensors via sensitivity to changes in pH in ionic fluids. The same devices are then demonstrated as highly localized heaters via investigation of experimental heating profiles and comparison to simulation results. These results offer further insight into the heating mechanism and help determine the spatial resolution of the technique. Two important biosensor platform applications spanning different temperature ranges are then demonstrated: a localized heat-mediated DNA exchange reaction and a method for dense selective functionalization of probe molecules via the heat catalyzed complete desorption and reattachment of chemical functionalization to the transistor surfaces. Our results show that the use of silicon transistors can be extended beyond electrical switching and field-effect sensing to performing localized temperature controlled chemical reactions on the transistor itself. PMID:21214189

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

PubMed

Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

2016-04-26

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Polarization dependent photo-induced bias stress effect in organic transistors.

NASA Astrophysics Data System (ADS)

Podzorov, Vitaly; Choi, Hyun Ho; Najafov, Hikmet; Saranin, Danila; Kharlamov, Nikolai A.; Kuznetzov, Denis V.; Didenko, Sergei I.; Cho, Kilwon; Briseno, Alejandro L.; Rutgers-Misis Collaboration; Ru-P Collaboration; Ru-Um Collaboration; Um-P Collaboration

Photo-induced charge transfer between a semiconductor and a gate insulator that occurs in organic transistors operating under illumination leads to a shift of the onset gate voltage in these devices. Here we report an observation of a polarization dependent photo-induced bias-stress effect in two prototypical single-crystal organic field-effect transistors, based on rubrene and TPBIQ. We find that the rate of the effect is a periodic function of polarization angle of a linearly polarized photoexcitation, with a periodicity of π. The observed phenomenon provides an effective tool for addressing the relationship between molecular packing and parameter drift in organic transistors under illumination. The work was carried out with financial support from the Ministry of Education and Science of the Russian Federation in the framework of Increase Competitiveness Program of NUST «MISiS» (No. K3-2016-004), by gov. decree 16/03/2013, N 211.

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Uniaxial angular accelerometers

NASA Astrophysics Data System (ADS)

Seleznev, A. V.; Shvab, I. A.

1985-05-01

The basic mechanical components of an angular accelerometer are the sensor, the damper, and the transducer. Penumatic dampers are simplest in construction, but the viscosity of air is very low and, therefore, dampers with special purpose oils having a high temperature stability (synthetic silicon or organosilicon oils) are most widely used. The most common types of viscous dampers are lamellar with meshed opposed arrays of fixed and movable vanes in the dashpot, piston dampers regulated by an adjustable-length capillary tube, and dampers with paddle wheel in closed tank. Another type of damper is an impact-inertial one with large masses absorbing the rotational energy upon collision with the sensor. Conventional measuring elements are resistive, capacitive, electromagnetic, photoelectric, and penumatic or hydraulic. Novel types of angular accelerometers are based on inertia of gas jets, electron beams, and ion beams, the piezoelectric effect in p-n junctions of diode and transistors, the electrokinetic effect in fluids, and cryogenic suspension of the sensor.

Controlled Trapping of Onion-Like Carbon (OLC) via Dielectrophoresis

NASA Astrophysics Data System (ADS)

Olariu, Marius; Arcire, Alexandru; Plonska-Brzezinska, Marta E.

2017-01-01

Manipulation of onion-like carbon (OLC), also known as carbon nano-onions (CNOs), at the level of various arrays of microelectrodes is vital in practical applications such as biological and chemical sensing, ultracapacitors (supercapacitors), electromagnetic shielding, catalysis, tribology, optical limiting and molecular junctions in scanning tunneling microscopy, and field-effect transistors. In spite of technological developments in this area, rigorous handling of carbon nano-onions towards desired locations within a device remains a challenge, and the quantity of OLC required significantly influences the price of the final electrical or electronic device. We present herein an experimental study on electromanipulation and trapping of onion-like carbon (OLC) at the level of gold-patterned interdigitated microelectrodes through dielectrophoresis. The influence of the magnitude as well as frequency of the alternating-current (AC) voltage employed for OLC trapping is discussed in detail. The effects of tuning the AC field strength and frequency on the OLC trapping behavior are also considered.

Stencil Nano Lithography Based on a Nanoscale Polymer Shadow Mask: Towards Organic Nanoelectronics

PubMed Central

Yun, Hoyeol; Kim, Sangwook; Kim, Hakseong; Lee, Junghyun; McAllister, Kirstie; Kim, Junhyung; Pyo, Sengmoon; Sung Kim, Jun; Campbell, Eleanor E. B.; Hyoung Lee, Wi; Wook Lee, Sang

2015-01-01

A stencil lithography technique has been developed to fabricate organic-material-based electronic devices with sub-micron resolution. Suspended polymethylmethacrylate (PMMA) membranes were used as shadow masks for defining organic channels and top electrodes. Arrays of pentacene field effect transistors (FETs) with various channel lengths from 50 μm down to 500 nm were successfully produced from the same batch using this technique. Electrical transport measurements showed that the electrical contacts of all devices were stable and the normalized contact resistances were much lower than previously studied organic FETs. Scaling effects, originating from the bulk space charge current, were investigated by analyzing the channel-length-dependent mobility and hysteresis behaviors. This novel lithography method provides a reliable means for studying the fundamental transport properties of organic materials at the nanoscale as well as enabling potential applications requiring the fabrication of integrated organic nanoelectronic devices. PMID:25959389

Stencil nano lithography based on a nanoscale polymer shadow mask: towards organic nanoelectronics.

PubMed

Yun, Hoyeol; Kim, Sangwook; Kim, Hakseong; Lee, Junghyun; McAllister, Kirstie; Kim, Junhyung; Pyo, Sengmoon; Sung Kim, Jun; Campbell, Eleanor E B; Hyoung Lee, Wi; Wook Lee, Sang

2015-05-11

A stencil lithography technique has been developed to fabricate organic-material-based electronic devices with sub-micron resolution. Suspended polymethylmethacrylate (PMMA) membranes were used as shadow masks for defining organic channels and top electrodes. Arrays of pentacene field effect transistors (FETs) with various channel lengths from 50 μm down to 500 nm were successfully produced from the same batch using this technique. Electrical transport measurements showed that the electrical contacts of all devices were stable and the normalized contact resistances were much lower than previously studied organic FETs. Scaling effects, originating from the bulk space charge current, were investigated by analyzing the channel-length-dependent mobility and hysteresis behaviors. This novel lithography method provides a reliable means for studying the fundamental transport properties of organic materials at the nanoscale as well as enabling potential applications requiring the fabrication of integrated organic nanoelectronic devices.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Electrical and structural properties of ZnO synthesized via infiltration of lithographically defined polymer templates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang-Yong Nam; Stein, Aaron; Kisslinger, Kim

We investigate the electrical and structural properties of infiltration-synthesized ZnO. In-plane ZnO nanowire arrays with prescribed positional registrations are generated by infiltrating diethlyzinc and water vapor into lithographically defined SU-8 polymer templates and removing organic matrix by oxygen plasma ashing. Transmission electron microscopy reveals that homogeneously amorphous as-infiltrated polymer templates transform into highly nanocrystalline ZnO upon removal of organic matrix. Field-effect transistor device measurements show that the synthesized ZnO after thermal annealing displays a typical n-type behavior, ~1019 cm -3 carrier density, and ~0.1 cm 2 V -1 s -1 electron mobility, reflecting highly nanocrystalline internal structure. The results demonstratemore » the potential application of infiltration synthesis in fabricating metal oxide electronic devices.« less

Electrical and structural properties of ZnO synthesized via infiltration of lithographically defined polymer templates

DOE PAGES

Chang-Yong Nam; Stein, Aaron; Kisslinger, Kim; ...

2015-11-17

We investigate the electrical and structural properties of infiltration-synthesized ZnO. In-plane ZnO nanowire arrays with prescribed positional registrations are generated by infiltrating diethlyzinc and water vapor into lithographically defined SU-8 polymer templates and removing organic matrix by oxygen plasma ashing. Transmission electron microscopy reveals that homogeneously amorphous as-infiltrated polymer templates transform into highly nanocrystalline ZnO upon removal of organic matrix. Field-effect transistor device measurements show that the synthesized ZnO after thermal annealing displays a typical n-type behavior, ~1019 cm -3 carrier density, and ~0.1 cm 2 V -1 s -1 electron mobility, reflecting highly nanocrystalline internal structure. The results demonstratemore » the potential application of infiltration synthesis in fabricating metal oxide electronic devices.« less

Silicon nanowires reliability and robustness investigation using AFM-based techniques

NASA Astrophysics Data System (ADS)

Bieniek, Tomasz; Janczyk, Grzegorz; Janus, Paweł; Grabiec, Piotr; Nieprzecki, Marek; Wielgoszewski, Grzegorz; Moczała, Magdalena; Gotszalk, Teodor; Buitrago, Elizabeth; Badia, Montserrat F.; Ionescu, Adrian M.

2013-07-01

Silicon nanowires (SiNWs) have undergone intensive research for their application in novel integrated systems such as field effect transistor (FET) biosensors and mass sensing resonators profiting from large surface-to-volume ratios (nano dimensions). Such devices have been shown to have the potential for outstanding performances in terms of high sensitivity, selectivity through surface modification and unprecedented structural characteristics. This paper presents the results of mechanical characterization done for various types of suspended SiNWs arranged in a 3D array. The characterization has been performed using techniques based on atomic force microscopy (AFM). This investigation is a necessary prerequisite for the reliable and robust design of any biosensing system. This paper also describes the applied investigation methodology and reports measurement results aggregated during series of AFM-based tests.

Creation of reduced graphene oxide based field effect transistors and their utilization in the detection and discrimination of nucleoside triphosphates.

PubMed

Yu, Chunmeng; Chang, Xingmao; Liu, Jing; Ding, Liping; Peng, Junxia; Fang, Yu

2015-05-27

Two low-cost, micropatterned, solution-gated field effect transistors (modified FET and unmodified FET) based on reduced graphene oxide (RGO) were developed and used for detection and discrimination of nucleoside triphosphates (NTPs). The modified FET was realized by simple deposition of a positively charged bis-pyrenyl derivative, py-diIM-py, onto the conducting RGO strips of the unmodified FET. The electrical properties and sensing behaviors of the as-prepared devices were studied comprehensively. Electrical transfer property tests revealed that both of the two FETs exhibit V-shaped ambipolar field effect behavior from p-type region to n-type region. Sensing performance studies demonstrated that modification of the native FET with py-diIM-py improves its sensing ability to NTPs-GTP and ATP in particular. The detection limit of GTP and ATP was as low as 400 nM, which is the lowest value for graphene-based electronic sensors reported so far. Furthermore, based on the cross-reactive responses of the two devices to NTPs, NTPs can be conveniently distinguished via combining use of the two devices. The enhancement of the modifier (py-diIM-py) to the sensing performance of the FET is tentatively attributed to its possible mediation role in sticking onto RGO strips and accumulating analytes by electrostatic association with the relevant species. Because they are sensitive and fast in response, simple and low-cost in preparation, and possibly useful in sensor-array fabrication, the developed sensors show great potential in real-life application.

A Field-Effect Transistor (FET) model for ASAP

NASA Technical Reports Server (NTRS)

Ming, L.

1965-01-01

The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Two-port active coupled microstrip antenna

NASA Astrophysics Data System (ADS)

Avitabile, G. F.; Maci, S.; Biffi Gentili, G.; Roselli, L.; Manes, G. F.

1992-12-01

A multilayer structure, based on a patch antenna coupled through a nonresonant slot to a pair of feeding microstrips is a versatile module which can be used as a radiating and resonating element in a number of different configurations. Direct connection to a low cost transistor in a feedback loop results in a very simple active antenna, as reported in the Letter. Different termination conditions at the four microstrip ports give rise to a number of alternative configurations for active generation/detection and multipatch arrays.

Dosimetry and microdosimetry using COTS ICs: A comparative study

NASA Technical Reports Server (NTRS)

Scheick, L.; Swift, G.; Guertin, S.; Roth, D.; McNulty, P.; Nguyen, D.

2002-01-01

A new method using an array of MOS transistors formeasuring dose absorbed from ionizing radiation is compared to previous dosimetric methods., The accuracy and precision of dosimetry based on COTS SRAMs, DRAMs, and WPROMs are compared and contrasted. Applications of these devices in various space missions will be discussed. TID results are presented for this summary and microdosimetricresults will be added to the full paper. Finally, an analysis of the optimal condition for a digital dosimeter will be presented.

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Thermal transistor utilizing gas-liquid transition.

PubMed

Komatsu, Teruhisa S; Ito, Nobuyasu

2011-01-01

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Investigation of the Sensitivity, Selectivity, and Reversibility of the Chemically-Sensitive Field-Effect Transistor (CHEMFET) to Detect Nitrogen Dioxide, Dimethyl Methylphosphonate, and Boron Trifluoride

DTIC Science & Technology

1993-09-01

SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN DIOXIDE, DIMETHYL METHYLPHOSPHONATE, AND BORON TRIFLUORIDE CHAPTER 1 1 Introduction Our rapidly...AND REVERSIBILITY OF THE CHEMICALLY-SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN 3 E I1• DIOXIDE, DIMETHYL METHYLPHOSPHONATE, ELECTE...AND BORON TRIFLUORIDE Neal Terence Hauschild Second Lieutenant, USAF AFIT/GE/ENG/9 3S-10 93-23815I II11l11l11 l gll I 1i 1111 11 I DEPARTMENT OF THE

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Hafnium transistor design for neural interfacing.

PubMed

Parent, David W; Basham, Eric J

2008-01-01

A design methodology is presented that uses the EKV model and the g(m)/I(D) biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

A Probe for Measuring Spacecraft Surface Potentials Using a Direct-Gate Field Effect Transistor.

DTIC Science & Technology

1983-09-30

SURFACE POTENTIALS USING A DIRECT-GATE FIELD EFFECT TRANSISTOR Mark N. Horenstein Anton Havretic Trustees of Boston University 881 Commonwealth Avenue...1933 Transistor 6. PERFORMING ORG. REPORT NUMBER 7. AUTHOR(s) S. CONTRACT OR GRANT NUMBER(&) ’_5 Mark N. Horenstein Anton Mavretic F19628-82-K-00 34...at AFGL. These tests can be considered the bench mark tests for device performance, with all elements of the monitoring system optimized to eliminate

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Fabrication and characterization of controllable grain boundary arrays in solution-processed small molecule organic semiconductor films

NASA Astrophysics Data System (ADS)

Wo, Songtao; Headrick, Randall L.; Anthony, John E.

2012-04-01

We have produced solution-processed thin films of 6,13-bis(tri-isopropyl-silylethynyl) pentacene with grain sizes from a few micrometers up to millimeter scale by lateral crystallization from a rectangular stylus. Grains are oriented along the crystallization direction, and the grain size transverse to the crystallization direction depends inversely on the writing speed, hence forming a regular array of oriented grain boundaries with controllable spacing. We utilize these controllable arrays to systematically study the role of large-angle grain boundaries in carrier transport and charge trapping in thin film transistors. The effective mobility scales with the grain size, leading to an estimate of the potential drop at individual large-angle grain boundaries of more than 1 volt. This result indicates that the structure of grain boundaries is not molecularly abrupt, which may be a general feature of solution-processed small molecule organic semiconductor thin films, where relatively high energy grain boundaries are typically formed. Transient measurements after switching from positive to negative gate bias or between large and small negative gate bias reveal reversible charge trapping, with time constants on the order of 10 s and trap densities that are correlated with grain boundary density. We suggest that charge diffusion along grain boundaries and other defects is the rate-determining mechanism of the reversible trapping.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

PubMed

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

MOSFET's for Cryogenic Amplifiers

NASA Technical Reports Server (NTRS)

Dehaye, R.; Ventrice, C. A.

1987-01-01

Study seeks ways to build transistors that function effectively at liquid-helium temperatures. Report discusses physics of metaloxide/semiconductor field-effect transistors (MOSFET's) and performances of these devices at cryogenic temperatures. MOSFET's useful in highly sensitive cryogenic preamplifiers for infrared astronomy.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Interaction of solid organic acids with carbon nanotube field effect transistors

NASA Astrophysics Data System (ADS)

Klinke, Christian; Afzali, Ali; Avouris, Phaedon

2006-10-01

A series of solid organic acids were used to p-dope carbon nanotubes. The extent of doping is shown to be dependent on the pKa value of the acids. Highly fluorinated carboxylic acids and sulfonic acids are very effective in shifting the threshold voltage and making carbon nanotube field effect transistors to be more p-type devices. Weaker acids like phosphonic or hydroxamic acids had less effect. The doping of the devices was accompanied by a reduction of the hysteresis in the transfer characteristics. In-solution doping survives standard fabrication processes and renders p-doped carbon nanotube field effect transistors with good transport characteristics.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

NASA Astrophysics Data System (ADS)

Zhou, Hong; Maize, Kerry; Qiu, Gang; Shakouri, Ali; Ye, Peide D.

2017-08-01

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Lead iodide perovskite light-emitting field-effect transistor

PubMed Central

Chin, Xin Yu; Cortecchia, Daniele; Yin, Jun; Bruno, Annalisa; Soci, Cesare

2015-01-01

Despite the widespread use of solution-processable hybrid organic–inorganic perovskites in photovoltaic and light-emitting applications, determination of their intrinsic charge transport parameters has been elusive due to the variability of film preparation and history-dependent device performance. Here we show that screening effects associated to ionic transport can be effectively eliminated by lowering the operating temperature of methylammonium lead iodide perovskite (CH3NH3PbI3) field-effect transistors. Field-effect carrier mobility is found to increase by almost two orders of magnitude below 200 K, consistent with phonon scattering-limited transport. Under balanced ambipolar carrier injection, gate-dependent electroluminescence is also observed from the transistor channel, with spectra revealing the tetragonal to orthorhombic phase transition. This demonstration of CH3NH3PbI3 light-emitting field-effect transistors provides intrinsic transport parameters to guide materials and solar cell optimization, and will drive the development of new electro-optic device concepts, such as gated light-emitting diodes and lasers operating at room temperature. PMID:26108967

Uncooled Terahertz real-time imaging 2D arrays developed at LETI: present status and perspectives

NASA Astrophysics Data System (ADS)

Simoens, François; Meilhan, Jérôme; Dussopt, Laurent; Nicolas, Jean-Alain; Monnier, Nicolas; Sicard, Gilles; Siligaris, Alexandre; Hiberty, Bruno

2017-05-01

As for other imaging sensor markets, whatever is the technology, the commercial spread of terahertz (THz) cameras has to fulfil simultaneously the criteria of high sensitivity and low cost and SWAP (size, weight and power). Monolithic silicon-based 2D sensors integrated in uncooled THz real-time cameras are good candidates to meet these requirements. Over the past decade, LETI has been studying and developing such arrays with two complimentary technological approaches, i.e. antenna-coupled silicon bolometers and CMOS Field Effect Transistors (FET), both being compatible to standard silicon microelectronics processes. LETI has leveraged its know-how in thermal infrared bolometer sensors in developing a proprietary architecture for THz sensing. High technological maturity has been achieved as illustrated by the demonstration of fast scanning of large field of view and the recent birth of a commercial camera. In the FET-based THz field, recent works have been focused on innovative CMOS read-out-integrated circuit designs. The studied architectures take advantage of the large pixel pitch to enhance the flexibility and the sensitivity: an embedded in-pixel configurable signal processing chain dramatically reduces the noise. Video sequences at 100 frames per second using our 31x31 pixels 2D Focal Plane Arrays (FPA) have been achieved. The authors describe the present status of these developments and perspectives of performance evolutions are discussed. Several experimental imaging tests are also presented in order to illustrate the capabilities of these arrays to address industrial applications such as non-destructive testing (NDT), security or quality control of food.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Vertical GaN Devices for Power Electronics in Extreme Environments

DTIC Science & Technology

2016-03-31

electronics applications. In this paper vertical p-n diodes and transistors fabricated on pseudo bulk low defect density (104 to 106 cm-2) GaN substrates are...holes in p-GaN has deleterious effect on p-n junction behavior (Fig. 2), p-GaN contacts, and channel control in junction field-effect transistors at...and transistors ) utilizing p-n junctions are suitable for most practical applications including automotive (210K < T < 423K) but may have limitations

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2017-03-01

energy levels on a GaN-on-silicon high electron mobility transistor was created. Based on physical results of 2.0-MeV protons irradiation to fluence...and the physical device at 2.0-MeV proton irradiation , predictions were made for 5.0, 10.0, 20.0 and 40.0-MeV proton irradiation . The model generally...nitride, high electron mobility transistor, electronics, 2 MeV proton irradiation , radiation effects 15. NUMBER OF PAGES 87 16. PRICE CODE 17. SECURITY

Localized heating on silicon field effect transistors: device fabrication and temperature measurements in fluid.

PubMed

Elibol, Oguz H; Reddy, Bobby; Nair, Pradeep R; Dorvel, Brian; Butler, Felice; Ahsan, Zahab S; Bergstrom, Donald E; Alam, Muhammad A; Bashir, Rashid

2009-10-07

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs).

PubMed

Kim, Choong-Ki; Kim, Eungtaek; Lee, Myung Keun; Park, Jun-Young; Seol, Myeong-Lok; Bae, Hagyoul; Bang, Tewook; Jeon, Seung-Bae; Jun, Sungwoo; Park, Sang-Hee K; Choi, Kyung Cheol; Choi, Yang-Kyu

2016-09-14

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.

Highly stable field emission from ZnO nanowire field emitters controlled by an amorphous indium–gallium–zinc-oxide thin film transistor

NASA Astrophysics Data System (ADS)

Li, Xiaojie; Wang, Ying; Zhang, Zhipeng; Ou, Hai; She, Juncong; Deng, Shaozhi; Xu, Ningsheng; Chen, Jun

2018-04-01

Lowering the driving voltage and improving the stability of nanowire field emitters are essential for them to be applied in devices. In this study the characteristics of zinc oxide (ZnO) nanowire field emitter arrays (FEAs) controlled by an amorphous indium–gallium–zinc-oxide thin film transistor (a-IGZO TFT) were studied. A low driving voltage along with stabilization of the field emission current were achieved. Modulation of field emission currents up to three orders of magnitude was achieved at a gate voltage of 0–32 V for a constant anode voltage. Additionally, a-IGZO TFT control can dramatically reduce the emission current fluctuation (i.e., from 46.11 to 1.79% at an emission current of ∼3.7 µA). Both the a-IGZO TFT and ZnO nanowire FEAs were prepared on glass substrates in our research, demonstrating the feasibility of realizing large area a-IGZO TFT-controlled ZnO nanowire FEAs.

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

NASA Astrophysics Data System (ADS)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-06-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-05-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

The QUIET Instrument

NASA Technical Reports Server (NTRS)

Gaier, T.; Kangaslahti, P.; Lawrence, C. R.; Leitch, E. M.; Wollack, E. J.

2012-01-01

The Q/U Imaging ExperimenT (QUIET) is designed to measure polarization in the Cosmic Microwave Background, targeting the imprint of inflationary gravitational waves at large angular scales ( approx 1 deg.) . Between 2008 October and 2010 December, two independent receiver arrays were deployed sequentially on a 1.4 m side-fed Dragonian telescope. The polarimeters which form the focal planes use a highly compact design based on High Electron Mobility Transistors (HEMTs) that provides simultaneous measurements of the Stokes parameters Q, U, and I in a single module. The 17-element Q-band polarimeter array, with a central frequency of 43.1 GHz, has the best sensitivity (69 micro Ks(exp 1/2)) and the lowest instrumental systematic errors ever achieved in this band, contributing to the tensor-to-scalar ratio at r < 0.1. The 84-element W-band polarimeter array has a sensitivity of 87 micro Ks(exp 1/2) at a central frequency of 94.5 GHz. It has the lowest systematic errors to date, contributing at r < 0.01 (QUIET Collaboration 2012) The two arrays together cover multipoles in the range l approximately equals 25-975 . These are the largest HEMT-ba.sed arrays deployed to date. This article describes the design, calibration, performance of, and sources of systematic error for the instrument,

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

NASA Astrophysics Data System (ADS)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Real-time reliable determination of binding kinetics of DNA hybridization using a multi-channel graphene biosensor

NASA Astrophysics Data System (ADS)

Xu, Shicai; Zhan, Jian; Man, Baoyuan; Jiang, Shouzhen; Yue, Weiwei; Gao, Shoubao; Guo, Chengang; Liu, Hanping; Li, Zhenhua; Wang, Jihua; Zhou, Yaoqi

2017-03-01

Reliable determination of binding kinetics and affinity of DNA hybridization and single-base mismatches plays an essential role in systems biology, personalized and precision medicine. The standard tools are optical-based sensors that are difficult to operate in low cost and to miniaturize for high-throughput measurement. Biosensors based on nanowire field-effect transistors have been developed, but reliable and cost-effective fabrication remains a challenge. Here, we demonstrate that a graphene single-crystal domain patterned into multiple channels can measure time- and concentration-dependent DNA hybridization kinetics and affinity reliably and sensitively, with a detection limit of 10 pM for DNA. It can distinguish single-base mutations quantitatively in real time. An analytical model is developed to estimate probe density, efficiency of hybridization and the maximum sensor response. The results suggest a promising future for cost-effective, high-throughput screening of drug candidates, genetic variations and disease biomarkers by using an integrated, miniaturized, all-electrical multiplexed, graphene-based DNA array.

Gallium nitride junction field-effect transistor

DOEpatents

Zolper, John C.; Shul, Randy J.

1999-01-01

An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.