80 MeV C{sup 6+} ion irradiation effects on the DC electrical characteristics of silicon NPN power transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bharathi, M. N.; Vinayakprasanna, N. H.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in

The total dose effects of 80 MeV C{sup 6+} ions on the DC electrical characteristics of Silicon NPN rf power transistors have been studied in the dose range of 100 krad to 100 Mrad. The SRIM simulation was used to understand the energy loss and range of the ions in the transistor structure. The different electrical parameters such as Gummel characteristics, excess base current (ΔI{sub B} = I{sub Bpost} - I{sub Bpre}), dc forward current gain (h{sub FE}), transconductance (g{sub m}), displacement damage factor (K) and output characteristics (V{sub CE}-I{sub C}) were studied systematically before and after irradiation. The significantmore » degradation in base current (I{sub B}) and h{sub FE} was observed after irradiation. Isochronal annealing study was conducted on the irradiated transistors to analyze the recovery in different electrical parameters. These results were compared with {sup 60}C0 gamma irradiation results in the same dose range.« less

Temperature dependence of frequency response characteristics in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Lu, Xubing; Minari, Takeo; Liu, Chuan; Kumatani, Akichika; Liu, J.-M.; Tsukagoshi, Kazuhito

2012-04-01

The frequency response characteristics of semiconductor devices play an essential role in the high-speed operation of electronic devices. We investigated the temperature dependence of dynamic characteristics in pentacene-based organic field-effect transistors and metal-insulator-semiconductor capacitors. As the temperature decreased, the capacitance-voltage characteristics showed large frequency dispersion and a negative shift in the flat-band voltage at high frequencies. The cutoff frequency shows Arrhenius-type temperature dependence with different activation energy values for various gate voltages. These phenomena demonstrate the effects of charge trapping on the frequency response characteristics, since decreased mobility prevents a fast charge response for alternating current signals at low temperatures.

Linear conduction in N-type organic field effect transistors with nanometric channel lengths and graphene as electrodes

NASA Astrophysics Data System (ADS)

Chianese, F.; Candini, A.; Affronte, M.; Mishra, N.; Coletti, C.; Cassinese, A.

2018-05-01

In this work, we test graphene electrodes in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivative. By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied bias, in contrast with the supralinear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrode devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ˜140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current in short channel OFETs.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Organic Field Effect Transistors for Large Format Electronics

DTIC Science & Technology

2003-06-19

calculated output characteristics for a p-channel substrate insulator Organic layer Source Drain Gate 6 pentacene OFET with 2µm source to drain spacing...conventional transistors. Figure 3. Calculated output characteristics of a pentacene OFET with image charge induced contact barrier...Cross section view of a part of an OFET in the vicinity of a source or drain contact. local ordering due to surface energy effects. The development of

Improved Field-Effect Transistor Equations for Computer Simulation.

ERIC Educational Resources Information Center

Kidd, Richard; Ardini, James

1979-01-01

Presents a laboratory experiment that was developed to acquaint physics students with field-effect transistor characteristics and circuits. Computer-drawn curves supplementing student laboratory exercises can be generated to provide more permanent, usable data than those taken from a curve tracer. (HM)

Solution-processed single-walled carbon nanotube field effect transistors and bootstrapped inverters for disintegratable, transient electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Sung Hun, E-mail: harin74@gmail.com, E-mail: jhl@snu.ac.kr, E-mail: jrogers@illinois.edu; Shin, Jongmin; Cho, In-Tak

2014-07-07

This paper presents materials, device designs, and physical/electrical characteristics of a form of nanotube electronics that is physically transient, in the sense that all constituent elements dissolve and/or disperse upon immersion into water. Studies of contact effects illustrate the ability to use water soluble metals such as magnesium for source/drain contacts in nanotube based field effect transistors. High mobilities and on/off ratios in transistors that use molybdenum, silicon nitride, and silicon oxide enable full swing characteristics for inverters at low voltages (∼5 V) and with high gains (∼30). Dissolution/disintegration tests of such systems on water soluble sheets of polyvinyl alcohol demonstratemore » physical transience within 30 min.« less

A Single Polyaniline Nanofiber Field Effect Transistor and Its Gas Sensing Mechanisms

PubMed Central

Chen, Dajing; Lei, Sheng; Chen, Yuquan

2011-01-01

A single polyaniline nanofiber field effect transistor (FET) gas sensor fabricated by means of electrospinning was investigated to understand its sensing mechanisms and optimize its performance. We studied the morphology, field effect characteristics and gas sensitivity of conductive nanofibers. The fibers showed Schottky and Ohmic contacts based on different electrode materials. Higher applied gate voltage contributes to an increase in gas sensitivity. The nanofiber transistor showed a 7% reversible resistance change to 1 ppm NH3 with 10 V gate voltage. The FET characteristics of the sensor when exposed to different gas concentrations indicate that adsorption of NH3 molecules reduces the carrier mobility in the polyaniline nanofiber. As such, nanofiber-based sensors could be promising for environmental and industrial applications. PMID:22163969

The analysis of ion-selective field-effect transistor operation in chemical sensors

NASA Astrophysics Data System (ADS)

Hotra, Zenon; Holyaka, Roman; Hladun, Michael; Humenuk, Iryna

2003-09-01

In this paper we present the research results of influence of substrate potential in ion-selective field-effect transistors (ISFET) on output signal of chemical sensors, e.g. PH-meters. It is shown that the instability of substrate-source p-n junction bias in well-known chemical sensors, which use grounded reference electrode - ISFET gate, affect on sensor characteristics in negative way. The analytical description and research results of 'substrate effect' on ISFET characteristics are considered.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Comparison of effect of 5 MeV proton and Co-60 gamma irradiation on silicon NPN rf power transistors and N-channel depletion MOSFETs

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Pradeep, T. M.; Hegde, Vinayakprasanna N.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Bhushan, K. G.

2017-12-01

NPN transistors and N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 5 MeV protons and 60Co gamma radiation in the dose ranging from 1 Mrad(Si) to 100 Mrad(Si). The different electrical characteristics of the NPN transistor such as Gummel characteristics, excess base current (ΔIB), dc current gain (hFE), transconductance (gm), displacement damage factor (K) and output characteristics were studied as a function of total dose. The different electrical characteristics of N-channel MOSFETs such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (µ) and drain saturation current (IDSat) were studied systematically before and after irradiation in the same dose ranges. A considerable increase in the base current (IB) and decrease in the hFE, gm and collector saturation current (ICSat) were observed after irradiation in the case of the NPN transistor. In the N-channel MOSFETs, the ΔNit and ΔNot were found to increase and Vth, gm, µ and IDSat were found to decrease with increase in the radiation dose. The 5 MeV proton irradiation results of both the NPN transistor and N-channel MOSFETs were compared with 60Co gamma-irradiated devices in the same dose ranges. It was observed that the degradation in 5 MeV proton-irradiated devices is more when compared with the 60Co gamma-irradiated devices at higher total doses.

High-mobility field-effect transistor based on crystalline ZnSnO3 thin films

NASA Astrophysics Data System (ADS)

Minato, Hiroya; Fujiwara, Kohei; Tsukazaki, Atsushi

2018-05-01

We propose crystalline ZnSnO3 as a new channel material for field-effect transistors. By molecular-beam epitaxy on LiNbO3(0001) substrates, we synthesized films of ZnSnO3, which crystallizes in the LiNbO3-type polar structure. Field-effect transistors on ZnSnO3 exhibit n-type operation with field-effect mobility of as high as 45 cm2V-1s-1 at room temperature. Systematic examination of the transistor operation for channels with different Zn/Sn compositional ratios revealed that the observed high-mobility reflects the nature of stoichiometric ZnSnO3 phase. Moreover, we found an indication of coupling of transistor characteristics with intrinsic spontaneous polarization in ZnSnO3, potentially leading to a distinct type of polarization-induced conduction.

Mobility overestimation due to gated contacts in organic field-effect transistors

PubMed Central

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Effect of Zinc Oxide Film Deposition Position on the Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Low-Temperature Magnetron Sputtering

NASA Astrophysics Data System (ADS)

Takechi, Kazushige; Nakata, Mitsuru; Eguchi, Toshimasa; Otsuki, Shigeyoshi; Yamaguchi, Hirotaka; Kaneko, Setsuo

2008-09-01

We report on the effect of zinc oxide (ZnO) film deposition position on the characteristics of ZnO thin-film transistors (TFTs) fabricated by magnetron sputtering with no intentional heating of the substrate. We evaluate the properties of ZnO (channel semiconductor) films deposited at various positions with respect to the target position. We show that the film deposition at a position off-centered from the target results in good TFT characteristics. This might be due to the fact that the off-centered deposition position is effective for suppressing the effect of energetic negative ions in the plasma.

Planar-Processed Polymer Transistors.

PubMed

Xu, Yong; Sun, Huabin; Shin, Eul-Yong; Lin, Yen-Fu; Li, Wenwu; Noh, Yong-Young

2016-10-01

Planar-processed polymer transistors are proposed where the effective charge injection and the split unipolar charge transport are all on the top surface of the polymer film, showing ideal device characteristics with unparalleled performance. This technique provides a great solution to the problem of fabrication limitations, the ambiguous operating principle, and the performance improvements in practical applications of conjugated-polymer transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The role of optoelectronic feedback on Franz-Keldysh voltage modulation of transistor lasers

NASA Astrophysics Data System (ADS)

Chang, Chi-Hsiang; Chang, Shu-Wei; Wu, Chao-Hsin

2016-03-01

Possessing both the high-speed characteristics of heterojunction bipolar transistors (HBTs) and enhanced radiative recombination of quantum wells (QWs), the light-emitting transistor (LET) which operates in the regime of spontaneous emissions has achieved up to 4.3 GHz modulation bandwidth. A 40 Gbit/s transmission rate can be even achieved using transistor laser (TL). The transistor laser provides not only the current modulation but also direct voltage-controlled modulation scheme of optical signals via Franz-Keldysh (FK) photon-assisted tunneling effect. In this work, the effect of FK absorption on the voltage modulation of TLs is investigated. In order to analyze the dynamics and optical responses of voltage modulation in TLs, the conventional rate equations relevant to diode lasers (DLs) are first modified to include the FK effect intuitively. The theoretical results of direct-current (DC) and small-signal alternating-current (AC) characteristics of optical responses are both investigated. While the DC characteristics look physical, the intrinsic optical response of TLs under the FK voltage modulation shows an AC enhancement with a 20 dB peak, which however is not observed in experiment. A complete model composed of the intrinsic optical transfer function and an electrical transfer function fed back by optical responses is proposed to explain the behaviors of voltage modulation in TLs. The abnormal AC peak disappears through this optoelectronic feedback. With the electrical response along with FK-included photon-carrier rate equations taken into account, the complete voltage-controlled optical modulation response of TLs is demonstrated.

Study of zeolite influence on analytical characteristics of urea biosensor based on ion-selective field-effect transistors

PubMed Central

2014-01-01

A possibility of the creation of potentiometric biosensor by adsorption of enzyme urease on zeolite was investigated. Several variants of zeolites (nano beta, calcinated nano beta, silicalite, and nano L) were chosen for experiments. The surface of pH-sensitive field-effect transistors was modified with particles of zeolites, and then the enzyme was adsorbed. As a control, we used the method of enzyme immobilization in glutaraldehyde vapour (without zeolites). It was shown that all used zeolites can serve as adsorbents (with different effectiveness). The biosensors obtained by urease adsorption on zeolites were characterized by good analytical parameters (signal reproducibility, linear range, detection limit and the minimal drift factor of a baseline). In this work, it was shown that modification of the surface of pH-sensitive field-effect transistors with zeolites can improve some characteristics of biosensors. PMID:24636423

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

Noise characteristics of single-walled carbon nanotube network transistors.

PubMed

Kim, Un Jeong; Kim, Kang Hyun; Kim, Kyu Tae; Min, Yo-Sep; Park, Wanjun

2008-07-16

The noise characteristics of randomly networked single-walled carbon nanotubes grown directly by plasma enhanced chemical vapor deposition (PECVD) are studied with field effect transistors (FETs). Due to the geometrical complexity of nanotube networks in the channel area and the large number of tube-tube/tube-metal junctions, the inverse frequency, 1/f, dependence of the noise shows a similar level to that of a single single-walled carbon nanotube transistor. Detailed analysis is performed with the parameters of number of mobile carriers and mobility in the different environment. This shows that the change in the number of mobile carriers resulting in the mobility change due to adsorption and desorption of gas molecules (mostly oxygen molecules) to the tube surface is a key factor in the 1/f noise level for carbon nanotube network transistors.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-11-01

Tunnel field-effect transistor (TFET) is very attractive in replacing a MOSFET, particularly for low-power nanoelectronic circuits. The U-shaped channel TFET (U-TFET) was proposed to improve the drain-source current with a reduced footprint. In this work, the impact of the source height (HS) on the characteristic of the U-shaped channel tunnel field-effect transistor (U-TFET) is investigated by using TCAD simulation. It is found that with a fixed gate height (HG) the drain-source current has a negative correlation with HS. This is because when the gate region is deeper than the source region, the electric field near the corner of the tunneling junction can be enhanced and the tunneling rate is increased. When HS becomes very thin, the drain-source current is limited by the source region volume. The U-TFET with an n+ pocket is also studied and the same trend is observed.

Nonvolatile memory characteristics of organic thin film transistors using poly(2-hydroxyethyl methacrylate)-based polymer multilayer dielectric

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Su, Yan-Kuin; Yu, Hsin-Chieh; Huang, Chun-Yuan; Huang, Tsung-Syun

2011-10-01

A wide hysteresis width characteristic (memory window) was observed in the organic thin film transistors (OTFTs) using poly(2-hydroxyethyl methacrylate) (PHEMA)-based polymer multilayers. In this study, a strong memory effect was also found in the pentacene-based OTFTs and the electric characteristics were improved by introducing PHEMA/poly(methyl methacrylate) (PMMA)/PHEMA trilayer to replace the conventional PHEMA monolayer or PMMA/PHEMA and PHEMA/PMMA bilayer as the dielectric layers of OTFTs. The memory effect was originated from the electron trapping and slow polarization of the dielectrics. The hydroxyl (-OH) groups inside the polymer dielectric were the main charge storage sites of the electrons. This charge-storage phenomenon could lead to a wide flat-band voltage shift (memory window, △VFB = 22 V) which is essential for the OTFTs' memory-related applications. Moreover, the fabricated transistors also exhibited significant switchable channel current due to the charge-storage and slow charge relaxation.

Effect of Hydrogen in Zinc Oxide Thin-Film Transistor Grown by Metal Organic Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Jo, Jungyol; Seo, Ogweon; Jeong, Euihyuk; Seo, Hyunseok; Lee, Byeongon; Choi, Yearn-Ik

2007-04-01

We studied the transport characteristics of ZnO grown by metal organic chemical vapor deposition (MOCVD) at temperatures between 200 and 500 °C. The crystal quality, measured by X-ray diffraction, improved as the growth temperature increased. However, the mobility measured in the thin-film transistor (TFT) decreased in films grown at higher temperatures. In our experiments, a ZnO TFT grown at 250 °C showed good electrical characteristics, with a 13 cm2 V-1 s-1 mobility and a 103 on/off ratio. We conclude that hydrogen incorporated during MOCVD growth plays an important role in determining the transistor characteristics. This was supported by results of secondary ion mass spectroscopy (SIMS), where a higher hydrogen concentration was observed in films grown at lower temperatures.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Current-voltage characteristics in organic field-effect transistors. Effect of interface dipoles

NASA Astrophysics Data System (ADS)

Sworakowski, Juliusz

2015-07-01

The role of polar molecules present at dielectric/semiconductor interfaces of organic field-effect transistors (OFETs) has been assessed employing the electrostatic model put forward in a recently published paper (Sworakowski et al., 2014). The interface dipoles create dipolar traps in the surface region of the semiconductor, their depths decreasing with the distance from the interface. This feature results in appearance of mobility gradients in the direction perpendicular to the dielectric/semiconductor interface, manifesting themselves in modification of the shapes of current-voltage characteristics. The effect may account for differences in carrier mobilities determined from the same experimental data using methods scanning different ranges of channel thicknesses (e.g., transconductances vs. transfer characteristics), differences between turn-on voltages and threshold voltages, and gate voltage dependence of mobility.

Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion

NASA Astrophysics Data System (ADS)

Cazimajou, T.; Legallais, M.; Mouis, M.; Ternon, C.; Salem, B.; Ghibaudo, G.

2018-05-01

We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.

An analytical model for bio-electronic organic field-effect transistor sensors

NASA Astrophysics Data System (ADS)

Macchia, Eleonora; Giordano, Francesco; Magliulo, Maria; Palazzo, Gerardo; Torsi, Luisa

2013-09-01

A model for the electrical characteristics of Functional-Bio-Interlayer Organic Field-Effect Transistors (FBI-OFETs) electronic sensors is here proposed. Specifically, the output current-voltage characteristics of a streptavidin (SA) embedding FBI-OFET are modeled by means of the analytical equations of an enhancement mode p-channel OFET modified according to an ad hoc designed equivalent circuit that is also independently simulated with pspice. An excellent agreement between the model and the experimental current-voltage output characteristics has been found upon exposure to 5 nM of biotin. A good agreement is also found with the SA OFET parameters graphically extracted from the device transfer I-V curves.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Combined electrical transport and capacitance spectroscopy of a MoS2-LiNbO3 field effect transistor

NASA Astrophysics Data System (ADS)

Michailow, Wladislaw; Schülein, Florian J. R.; Möller, Benjamin; Preciado, Edwin; Nguyen, Ariana E.; von Son, Gretel; Mann, John; Hörner, Andreas L.; Wixforth, Achim; Bartels, Ludwig; Krenner, Hubert J.

2017-01-01

We have measured both the current-voltage ( ISD - VGS ) and capacitance-voltage (C- VGS ) characteristics of a MoS2-LiNbO3 field effect transistor. From the measured capacitance, we calculate the electron surface density and show that its gate voltage dependence follows the theoretical prediction resulting from the two-dimensional free electron model. This model allows us to fit the measured ISD - VGS characteristics over the entire range of VGS . Combining this experimental result with the measured current-voltage characteristics, we determine the field effect mobility as a function of gate voltage. We show that for our device, this improved combined approach yields significantly smaller values (more than a factor of 4) of the electron mobility than the conventional analysis of the current-voltage characteristics only.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Material Synthesis and Device Aspects of Monolayer Tungsten Diselenide.

PubMed

Yao, Zihan; Liu, Jialun; Xu, Kai; Chow, Edmond K C; Zhu, Wenjuan

2018-03-27

In this paper, we investigate the synthesis of WSe 2 by chemical vapor deposition and study the current transport and device scaling of monolayer WSe 2 . We found that the device characteristics of the back-gated WSe 2 transistors with thick oxides are very sensitive to the applied drain bias, especially for transistors in the sub-micrometer regime. The threshold voltage, subthreshold swing, and extracted field-effect mobility vary with the applied drain bias. The output characteristics in the long-channel transistors show ohmic-like behavior, while that in the short-channel transistors show Schottky-like behavior. Our investigation reveals that these phenomena are caused by the drain-induced barrier lowering (short-channel effect). For back-gated WSe 2 transistors with 280 nm oxide, the short-channel effect appears when the channel length is shorter than 0.4 µm. This extremely long electrostatic scaling length is due to the thick back-gate oxides. In addition, we also found that the hydrogen flow rate and the amount of WO 3 precursor play an important role in the morphology of the WSe 2 . The hole mobility of the monolayer WSe 2 is limited by Columbic scattering below 250 K, while it is limited by phonon scattering above 250 K. These findings are very important for the synthesis of WSe 2 and accurate characterization of the electronic devices based on 2D materials.

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Transistors and tunnel diodes enabled by large-scale MoS2 nanosheets grown on GaN

NASA Astrophysics Data System (ADS)

San Yip, Pak; Zou, Xinbo; Cho, Wai Ching; Wu, Kam Lam; Lau, Kei May

2017-07-01

We report growth, fabrication, and device results of MoS2-based transistors and diodes implemented on a single 2D/3D material platform. The 2D/3D platform consists of a large-area MoS2 thin film grown on SiO2/p-GaN substrates. Atomic force microscopy, scanning electron microscopy, and Raman spectroscopy were used to characterize the thickness and quality of the as-grown MoS2 film, showing that the large-area MoS2 nanosheet has a smooth surface morphology constituted by small grains. Starting from the same material, both top-gated MoS2 field effect transistors and MoS2/SiO2/p-GaN heterojunction diodes were fabricated. The transistors exhibited a high on/off ratio of 105, a subthreshold swing of 74 mV dec-1, field effect mobility of 0.17 cm2 V-1 s-1, and distinctive current saturation characteristics. For the heterojunction diodes, current-rectifying characteristics were demonstrated with on-state current density of 29 A cm-2 and a current blocking property up to -25 V without breakdown. The reported transistors and diodes enabled by the same 2D/3D material stack present promising building blocks for constructing future nanoscale electronics.

Field effects in graphene in an interface contact with aqueous solutions of acetic acid and potassium hydroxide

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Yu.; Lebedev, S. P.; Lebedev, A. A.; Kumzerov, Yu. A.

2017-10-01

For the creation of new promising chemical sensors, it is very important to study the influence of the interface between graphene and aqueous solutions of acids and alkalis on the transistor characteristics of graphene. Transistor structures on the basis of graphene grown by thermal decomposition of silicon carbide were created and studied. For the interface of graphene with aqueous solutions of acetic acid and potassium hydroxide in the transistor geometry, with a variation in the gate-to-source voltage, the field effect corresponding to the hole type of charge carriers in graphene was observed. It is established that an increase in the concentration of molecular ions in these solutions leads to an increase in the dependence of the resistance of the transistor on the gate voltage.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

PubMed Central

Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

2017-01-01

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

5 MeV Proton irradiation effects on 200 GHz silicon-germanium heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Hegde, Vinayakprasanna N.; Pradeep, T. M.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Cressler, J. D.

2017-12-01

The total dose effects of 5 MeV proton and Co-60 gamma irradiation in the dose range from 1 to 100 Mrad on advanced 200 GHz Silicon-Germanium heterojunction bipolar transistors (SiGe HBTs) are investigated. The SRIM simulation study was conducted to understand the energy loss of 5 MeV proton ions in SiGe HBT structure. Pre- and post-radiation DC figure of merits such as forward- and inverse-mode Gummel characteristics, excess base current, DC current gain and output characteristics were used to quantify the radiation tolerance of the devices. The results show that the proton creates a significant amount of damages in the surface and bulk of the transistor when compared with gamma irradiation. The SiGe HBTs shows robust ionizing radiation tolerance even up to a total dose of 100 Mrad for both radiations.

Removing the current-limit of vertical organic field effect transistors

NASA Astrophysics Data System (ADS)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Improved Hot Carrier Reliability Characteristics of Metal Oxide Semiconductor Field Effect Transistors with High-k Gate Dielectric by Using High Pressure Deuterium Post Metallization Annealing

NASA Astrophysics Data System (ADS)

Park, Hokyung; Choi, Rino; Lee, Byoung Hun; Hwang, Hyunsang

2007-09-01

High pressure deuterium annealing on the hot carrier reliability characteristics of HfSiO metal oxide semiconductor field effect transistor (MOSFET) was investigated. Comparing with the conventional forming gas (H2/Ar=10%/96%, 480 °C, 30 min) annealed sample, MOSFET annealed in 5 atm pure deuterium ambient at 400 °C showed the improvement of linear drain current, reduction of interface trap density, and improvement of the hot carrier reliability characteristics. These improvements can be attributed to the effective passivation of the interface trap site after high pressure annealing and heavy mass effect of deuterium. These results indicate that high pressure pure deuterium annealing can be a promising process for improving device performance as well as hot carrier reliability, together.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

NASA Astrophysics Data System (ADS)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

The effects of neutron and gamma rays on the electrical and switching characteristics of power semiconductor switches must be known and understood by the designer of the power conditioning, control, and transmission subsystem of space nuclear power systems. The SP-100 radiation requirements at 25 m from the nuclear source are a neutron fluence of 10(exp 13) n/sq cm and a gamma dose of 0.5 Mrads. Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN Bipolar Junction Transistors (BJTs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Static Induction Transistors (SITs) are presented. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Post-irradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Omura, Yasuhisa; Mori, Yoshiaki; Sato, Shingo; Mallik, Abhijit

2018-04-01

This paper discusses the role of trap-assisted-tunneling process in controlling the ON- and OFF-state current levels and its impacts on the current-voltage characteristics of a tunnel field-effect transistor. Significant impacts of high-density traps in the source region are observed that are discussed in detail. With regard to recent studies on isoelectronic traps, it has been discovered that deep level density must be minimized to suppress the OFF-state leakage current, as is well known, whereas shallow levels can be utilized to control the ON-state current level. A possible mechanism is discussed based on simulation results.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

Trap density of states in small-molecule organic semiconductors: A quantitative comparison of thin-film transistors with single crystals

NASA Astrophysics Data System (ADS)

Kalb, Wolfgang L.; Haas, Simon; Krellner, Cornelius; Mathis, Thomas; Batlogg, Bertram

2010-04-01

We show that it is possible to reach one of the ultimate goals of organic electronics: producing organic field-effect transistors with trap densities as low as in the bulk of single crystals. We studied the spectral density of localized states in the band gap [trap density of states (trap DOS)] of small-molecule organic semiconductors as derived from electrical characteristics of organic field-effect transistors or from space-charge-limited current measurements. This was done by comparing data from a large number of samples including thin-film transistors (TFT’s), single crystal field-effect transistors (SC-FET’s) and bulk samples. The compilation of all data strongly suggests that structural defects associated with grain boundaries are the main cause of “fast” hole traps in TFT’s made with vacuum-evaporated pentacene. For high-performance transistors made with small-molecule semiconductors such as rubrene it is essential to reduce the dipolar disorder caused by water adsorbed on the gate dielectric surface. In samples with very low trap densities, we sometimes observe a steep increase in the trap DOS very close (<0.15eV) to the mobility edge with a characteristic slope of 10-20 meV. It is discussed to what degree band broadening due to the thermal fluctuation of the intermolecular transfer integral is reflected in this steep increase in the trap DOS. Moreover, we show that the trap DOS in TFT’s with small-molecule semiconductors is very similar to the trap DOS in hydrogenated amorphous silicon even though polycrystalline films of small-molecules with van der Waals-type interaction on the one hand are compared with covalently bound amorphous silicon on the other hand.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries.

PubMed

Lee, Yi-Ying; Hsu, Chih-Yuan; Lin, Ling-Jiun; Chang, Chih-Chun; Cheng, Hsiao-Chun; Yeh, Tsung-Hsien; Hu, Rei-Hsing; Lin, Che; Xie, Zhen; Chen, Bor-Sen

2013-10-27

Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components.According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries

PubMed Central

2013-01-01

Background Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Results Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components. According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. Conclusion This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching. PMID:24160305

Analysis of charge injection and contact resistance as a function of electrode surface treatment in ambipolar polymer transistors

NASA Astrophysics Data System (ADS)

Lee, Seon Jeng; Kim, Chaewon; Jung, Seok-Heon; Di Pietro, Riccardo; Lee, Jin-Kyun; Kim, Jiyoung; Kim, Miso; Lee, Mi Jung

2018-01-01

Ambipolar organic field-effect transistors (OFETs) have both of hole and electron enhancements in charge transport. The characteristics of conjugated diketopyrrolopyrrole ambipolar OFETs depend on the metal-contact surface treatment for charge injection. To investigate the charge-injection characteristics of ambipolar transistors, these devices are processed via various types of self-assembled monolayer treatments and annealing. We conclude that treatment by the self-assembled monolayer 1-decanethiol gives the best enhancement of electron charge injection at both 100 and 300 °C annealing temperature. In addition, the contact resistance is calculated by using two methods: One is the gated four-point probe (gFPP) method that gives the voltage drop between channels, and the other is the simultaneous contact resistance extraction method, which extracts the contact resistance from the general transfer curve. We confirm that the gFPP method and the simultaneous extraction method give similar contact resistance, which means that we can extract contact resistance from the general transfer curve without any special contact pattern. Based on these characteristics of ambipolar p- and n-type transistors, we fabricate inverter devices with only one active layer. [Figure not available: see fulltext.

Nitrogen plasma-treated multilayer graphene-based field effect transistor fabrication and electronic characteristics

NASA Astrophysics Data System (ADS)

Su, Wei-Jhih; Chang, Hsuan-Chen; Honda, Shin-ichi; Lin, Pao-Hung; Huang, Ying-Sheng; Lee, Kuei-Yi

2017-08-01

Chemical doping with hetero-atoms is an effective method used to change the characteristics of materials. Nitrogen doping technology plays a critical role in regulating the electronic properties of graphene. Nitrogen plasma treatment was used in this work to dope nitrogen atoms to modulate multilayer graphene electrical properties. The measured I-V multilayer graphene-base field-effect transistor characteristics (GFETs) showed a V-shaped transfer curve with the hole and electron region separated from the measured current-voltage (I-V) minimum. GFETs fabricated with multilayer graphene from chemical vapor deposition (CVD) exhibited p-type behavior because of oxygen adsorption. After using different nitrogen plasma treatment times, the minimum in I-V characteristic shifted into the negative gate voltage region with increased nitrogen concentration and the GFET channel became an n-type semiconductor. GFETs could be easily fabricated using this method with potential for various applications. The GFET transfer characteristics could be tuned precisely by adjusting the nitrogen plasma treatment time.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

NASA Astrophysics Data System (ADS)

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

PubMed Central

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor. PMID:28134275

An innovative large scale integration of silicon nanowire-based field effect transistors

NASA Astrophysics Data System (ADS)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

pH-sensitive ion-selective field-effect transistor with zirconium dioxide film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vlasov, Yu.G.; Bratov, A.V.; Tarantov, Yu.A.

1988-09-20

Miniature semiconductor pH sensors for liquid media, i.e., ion-selective field-effect transistors (ISFETs), are silicon field-effect transistors with a two-layer dielectric consisting of a passivating SiO/sub 2/ layer adjoining the silicon and a layer of pH-sensitive material in contact with the electrolyte solution to be tested. This study was devoted to the characteristics of pH-sensitive ISFETs with ZrO/sub 2/ films. The base was p-type silicon (KDB-10) with a (100) surface orientation. A ZrO/sub 2/ layer 10-50 nm thick was applied over the SiO/sub 2/ layer by electron-beam deposition. The measurements were made in aqueous KNO/sub 3/ or KCl solutions.

Electrical characteristics of organic perylene single-crystal-based field-effect transistors

NASA Astrophysics Data System (ADS)

Lee, Jin-Woo; Kang, Han-Saem; Kim, Min-Ki; Kim, Kihyun; Cho, Mi-Yeon; Kwon, Young-Wan; Joo, Jinsoo; Kim, Jae-Il; Hong, Chang-Seop

2007-12-01

We report on the fabrication of organic field-effect transistors (OFETs) using perylene single crystal as the active material and their electrical characteristics. Perylene single crystals were directly grown from perylene powder in a furnace using a relatively short growth time of 1-3 h. The crystalline structure of the perylene single crystals was characterized by means of a single-crystal x-ray diffractometer. In order to place the perylene single crystal onto the Au electrodes of the field-effect transistor, a polymethlymethacrylate thin layer was spin-coated on top of the crystal surface. The OFETs fabricated using the perylene single crystal showed a typical p-type operating mode. The field-effect mobility of the perylene crystal based OFETs was measured to be ˜9.62×10-4 cm2/V s at room temperature. The anisotropy of the mobility implying the existence of different mobilities when applying currents in different directions was observed for the OFETs, and the existence of traps in the perylene crystal was found through the measurements of the temperature-dependent mobility at various operating drain voltages.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

NASA Astrophysics Data System (ADS)

Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

2018-03-01

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

Accelerated life testing and temperature dependence of device characteristics in GaAs CHFET devices

NASA Technical Reports Server (NTRS)

Gallegos, M.; Leon, R.; Vu, D. T.; Okuno, J.; Johnson, A. S.

2002-01-01

Accelerated life testing of GaAs complementary heterojunction field effect transistors (CHFET) was carried out. Temperature dependence of single and synchronous rectifier CHFET device characteristics were also obtained.

Electrical characteristics of Graphene based Field Effect Transistor (GFET) biosensor for ADH detection

NASA Astrophysics Data System (ADS)

Selvarajan, Reena Sri; Hamzah, Azrul Azlan; Majlis, Burhanuddin Yeop

2017-08-01

First pristine graphene was successfully produced by mechanical exfoliation and electrically characterized in 2004 by Andre Geim and Konstantin Novoselov at University of Manchester. Since its discovery in 2004, graphene also known as `super' material that has enticed many researchers and engineers to explore its potential in ultrasensitive detection of analytes in biosensing applications. Among myriad reported sensors, biosensors based on field effect transistors (FETs) have attracted much attention. Thus, implementing graphene as conducting channel material hastens the opportunities for production of ultrasensitive biosensors for future device applications. Herein, we have reported electrical characteristics of graphene based field effect transistor (GFET) for ADH detection. GFET was modelled and simulated using Lumerical DEVICE charge transport solver (DEVICE CT). Electrical characteristics comprising of transfer and output characteristics curves are reported in this study. The device shows ambipolar curve and achieved a minimum conductivity of 0.23912 e5A at Dirac point. However, the curve shifts to the left and introduces significant changes in the minimum conductivity as drain voltage is increased. Output characteristics of GFET exhibits linear Id - Vd dependence characteristics for gate voltage ranging from 0 to 1.5 V. In addition, behavior of electrical transport through GFET was analyzed for various simulation temperatures. It clearly proves that the electrical transport in GFET is dependent on the simulation temperature as it may vary the maximum resistance in channel of the device. Therefore, this unique electrical characteristics of GFET makes it as a promising candidate for ultrasensitive detection of small biomolecules such as ADH in biosensing applications.

Subthreshold characteristics of pentacene field-effect transistors influenced by grain boundaries

NASA Astrophysics Data System (ADS)

Park, Jaehoon; Jeong, Ye-Sul; Park, Kun-Sik; Do, Lee-Mi; Bae, Jin-Hyuk; Sun Choi, Jong; Pearson, Christopher; Petty, Michael

2012-05-01

Grain boundaries in polycrystalline pentacene films significantly affect the electrical characteristics of pentacene field-effect transistors (FETs). Upon reversal of the gate voltage sweep direction, pentacene FETs exhibited hysteretic behaviours in the subthreshold region, which was more pronounced for the FET having smaller pentacene grains. No shift in the flat-band voltage of the metal-insulator-semiconductor capacitor elucidates that the observed hysteresis was mainly caused by the influence of localized trap states existing at pentacene grain boundaries. From the results of continuous on/off switching operation of the pentacene FETs, hole depletion during the off period is found to be limited by pentacene grain boundaries. It is suggested that the polycrystalline nature of a pentacene film plays an important role on the dynamic characteristics of pentacene FETs.

AlN metal-semiconductor field-effect transistors using Si-ion implantation

NASA Astrophysics Data System (ADS)

Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

2018-04-01

We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

Scattering effects on the performance of carbon nanotube field effect transistor in a compact model

NASA Astrophysics Data System (ADS)

Hamieh, S. D.; Desgreys, P.; Naviner, J. F.

2010-01-01

Carbon nanotube field-effect transistors (CNTFET) are being extensively studied as possible successors to CMOS. Device simulators have been developed to estimate their performance in sub-10-nm and device structures have been fabricated. In this work, a new compact model of single-walled semiconducting CNTFET is proposed implementing the calculation of energy conduction sub-band minima and the treatment of scattering effects through energy shift in CNTFET. The developed model has been used to simulate I-V characteristics using VHDL-AMS simulator.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

High speed capacitor-inverter based carbon nanotube full adder.

PubMed

Navi, K; Rashtian, M; Khatir, A; Keshavarzian, P; Hashemipour, O

2010-03-18

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shervin, Shahab; Asadirad, Mojtaba; Materials Science and Engineering Program, University of Houston, Houston, Texas 77204

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strainmore » in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Han, Dong-Suk; Kang, Yu-Jin; Park, Jae-Hyung

Highlights: • We developed and investigated source/drain electrodes in oxide TFTs. • The Mo S/D electrodes showed good output characteristics. • Intrinsic TFT parameters were calculated by the transmission line method. - Abstract: This paper investigates the feasibility of a low-resistivity electrode material (Mo) for source/drain (S/D) electrodes in thin film transistors (TFTs). The effective resistances between Mo source/drain electrodes and amorphous zinc–tin-oxide (a-ZTO) thin film transistors were studied. Intrinsic TFT parameters were calculated by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low source/drain voltage. The TFTs fabricated with Momore » source/drain electrodes showed good transfer characteristics with a field-effect mobility of 10.23 cm{sup 2}/V s. In spite of slight current crowding effects, the Mo source/drain electrodes showed good output characteristics with a steep rise in the low drain-to-source voltage (V{sub DS}) region.« less

Neutron and gamma irradiation effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1990-01-01

The performance characteristics of high-power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Neutron and gamma irradiation effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1990-01-01

The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

Organic field-effect transistors using single crystals.

PubMed

Hasegawa, Tatsuo; Takeya, Jun

2009-04-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20-40 cm 2 Vs -1 , achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps.

Organic field-effect transistors using single crystals

PubMed Central

Hasegawa, Tatsuo; Takeya, Jun

2009-01-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for ‘plastic electronics’. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20–40 cm2 Vs−1, achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps. PMID:27877287

Comparison between the effects of positive noncatastrophic HMB ESD stress in n-channel and p-channel power MOSFET's

NASA Astrophysics Data System (ADS)

Zupac, Dragan; Kosier, Steven L.; Schrimpf, Ronald D.; Galloway, Kenneth F.; Baum, Keith W.

1991-10-01

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain.

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

PubMed

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

Chemical free device fabrication of two dimensional van der Waals materials based transistors by using one-off stamping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Young Tack, E-mail: 023273@kist.re.kr, E-mail: stunalren@gmail.com; Choi, Won Kook; Materials and Life Science Research Division, Korea Institute of Science and Technology

We report on a chemical free one-off imprinting method to fabricate two dimensional (2D) van der Waals (vdWs) materials based transistors. Such one-off imprinting technique is the simplest and effective way to prevent unintentional chemical reaction or damage of 2D vdWs active channel during device fabrication process. 2D MoS{sub 2} nanosheets based transistors with a hexagonal-boron-nitride (h-BN) passivation layer, prepared by one-off imprinting, show negligible variations of transfer characteristics after chemical vapor deposition process. In addition, this method enables the fabrication of all 2D MoS{sub 2} transistors consisting of h-BN gate insulator, and graphene source/drain and gate electrodes without anymore » chemical damage.« less

The Impact of the Shallow-Trench Isolation Effect on Flicker Noise of Source Follower MOSFETs in a CMOS Image Sensor.

PubMed

Fan, C C; Chiu, Y C; Liu, C; Lai, W W; Cheng, C H; Lin, D L; Li, G R; Lo, Y H; Chang, C W; Tsai, C C; Chang, C Y

2018-06-01

The flicker noise of source follower transistors is the dominant noise source in image sensors. This paper reports a systematic study of the shallow trench isolation effect in transistors with different sizes under high temperature conditions that correspond to the quantity of empty defect sites. The effects of shallow trench isolation sidewall defects on flicker noise characteristics are investigated. In addition, the low-frequency noise and subthreshold swing degrade simultaneously in accordance to the device gate width scaling. Both serious subthreshold leakage and considerable noise can be attributed to the high trap density near the STI edge. Consequently, we propose a coincidental relationship between the noise level and the subthreshold characteristic; its trend is identical to the experiments and simulation results.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Investigation of transport properties of coronene.TCNQ cocrystal microrods with coronene microrods and TCNQ microsheets

NASA Astrophysics Data System (ADS)

Wu, Hao-Di; Wang, Feng-Xia; Zhang, Meng; Pan, Ge-Bo

2015-07-01

Coronene.TCNQ cocrystal microrods, coronene microrods, and TCNQ microsheets were constructed by a drop-casting method. Prototype devices were fabricated and their field-effect-transistor (FET) performances were investigated. It is found that coronene.TCNQ microrods had exhibited an n-type characteristic and showed better FET performances than TCNQ microsheets.Coronene.TCNQ cocrystal microrods, coronene microrods, and TCNQ microsheets were constructed by a drop-casting method. Prototype devices were fabricated and their field-effect-transistor (FET) performances were investigated. It is found that coronene.TCNQ microrods had exhibited an n-type characteristic and showed better FET performances than TCNQ microsheets. Electronic supplementary information (ESI) available: Device fabrication and measurements. See DOI: 10.1039/c5nr02778k

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface.

PubMed

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-10-07

Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

Environmental Effects on Hysteresis of Transfer Characteristics in Molybdenum Disulfide Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Shimazu, Yoshihiro; Tashiro, Mitsuki; Sonobe, Satoshi; Takahashi, Masaki

2016-07-01

Molybdenum disulfide (MoS2) has recently received much attention for nanoscale electronic and photonic applications. To explore the intrinsic properties and enhance the performance of MoS2-based field-effect transistors, thorough understanding of extrinsic effects such as environmental gas and contact resistance of the electrodes is required. Here, we report the effects of environmental gases on the transport properties of back-gated multilayered MoS2 field-effect transistors. Comparisons between different gases (oxygen, nitrogen, and air and nitrogen with varying relative humidities) revealed that water molecules acting as charge-trapping centers are the main cause of hysteresis in the transfer characteristics. While the hysteresis persisted even after pumping out the environmental gas for longer than 10 h at room temperature, it disappeared when the device was cooled to 240 K, suggesting a considerable increase in the time constant of the charge trapping/detrapping at these modestly low temperatures. The suppression of the hysteresis or instability in the easily attainable temperature range without surface passivation is highly advantageous for the device application of this system. The humidity dependence of the threshold voltages in the transfer curves indicates that the water molecules dominantly act as hole-trapping centers. A strong dependence of the on-state current on oxygen pressure was also observed.

Photocurrent spectroscopy of pentacene thin film transistors

NASA Astrophysics Data System (ADS)

Breban, Mihaela

We demonstrate the application of photocurrent modulation spectroscopy in characterizing the performance of organic thin-film transistors. A parallel analysis of the direct current and photocurrent voltage characteristics provides a model free determination of the field-effect mobility and the density of free carriers in the transistor channel as a function of the applied gate voltage. Applying this technique to pentacene thin-film transistors demonstrates that the mobility increases as V1/3g . The free-carrier density is approximately 1/10 of the expected capacitive charge, and the mobility increases monotonically with the free carrier density, consistent with the trap and release model of transport. Also, the modulated photocurrent spectroscopy can be used as a probe of defect states in pentacene thin film transistors, measuring simultaneously the magnitude and the phase of the photocurrent as a function of the modulation frequency. This is accomplished by modeling the photo-carrier generation process as exciton dissociation via interaction with localized traps. Experimental data reveal a Gaussian distribution of localized states centered around 0.3 eV above the highest occupied molecular orbital. We also investigated the effect of the gate dielectric material with our probe and found that the position of the extracted Gaussian slightly shifts, consistent with the expected image charge effect for Pn through the dielectric substrate. Also shifts in the Gaussian position for samples fabricated with variable deposition conditions are correlated with changes in Pn morphology. The morphological differences between Pn films were also detected in current-voltage characteristics and photocurrent spectra. However, the origin of the ubiquitous 0.3 eV defect in Pn seems to be unrelated to structural differences in Pn films.

Percolative effects on noise in pentacene transistors

NASA Astrophysics Data System (ADS)

Conrad, B. R.; Cullen, W. G.; Yan, W.; Williams, E. D.

2007-12-01

Noise in pentacene thin film transistors has been measured as a function of device thickness from well above the effective conduction channel thickness to only two conducting layers. Over the entire thickness range, the spectral noise form is 1/f, and the noise parameter varies inversely with gate voltage, confirming that the noise is due to mobility fluctuations, even in the thinnest films. Hooge's parameter varies as an inverse power law with conductivity for all film thicknesses. The magnitude and transport characteristics of the spectral noise are well explained in terms of percolative effects arising from the grain boundary structure.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

Quantum simulation of an ultrathin body field-effect transistor with channel imperfections

NASA Astrophysics Data System (ADS)

Vyurkov, V.; Semenikhin, I.; Filippov, S.; Orlikovsky, A.

2012-04-01

An efficient program for the all-quantum simulation of nanometer field-effect transistors is elaborated. The model is based on the Landauer-Buttiker approach. Our calculation of transmission coefficients employs a transfer-matrix technique involving the arbitrary precision (multiprecision) arithmetic to cope with evanescent modes. Modified in such way, the transfer-matrix technique turns out to be much faster in practical simulations than that of scattering-matrix. Results of the simulation demonstrate the impact of realistic channel imperfections (random charged centers and wall roughness) on transistor characteristics. The Landauer-Buttiker approach is developed to incorporate calculation of the noise at an arbitrary temperature. We also validate the ballistic Landauer-Buttiker approach for the usual situation when heavily doped contacts are indispensably included into the simulation region.

Modeling of static electrical properties in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Gwoziecki, Romain; Coppard, Romain; Benwadih, Mohamed; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

A modeling of organic field-effect transistors' (OFETs') electrical characteristics is presented. This model is based on a one-dimensional (1-D) Poisson's equation solution that solves the potential profile in the organic semiconducting film. Most importantly, it demonstrates that, due to the common open-surface configuration used in organic transistors, the conduction occurs in the film volume below threshold. This is because the potential at the free surface is not fixed to zero but rather rises also with the gate bias. The tail of carrier concentration at the free surface is therefore significantly modulated by the gate bias, which partially explains the gate-voltage dependent contact resistance. At the same time in the so-called subthreshold region, we observe a clear charge trapping from the difference between C-V and I-V measurements; hence a traps study by numerical simulation is also performed. By combining the analytical modeling and the traps analysis, the questions on the C-V and I-V characteristics are answered. Finally, the combined results obtained with traps fit well the experimental data in both pentacene and bis(triisopropylsilylethynyl)-pentacene OFETs.

Hydrothermally Processed Photosensitive Field-Effect Transistor Based on ZnO Nanorod Networks

NASA Astrophysics Data System (ADS)

Kumar, Ashish; Bhargava, Kshitij; Dixit, Tejendra; Palani, I. A.; Singh, Vipul

2016-11-01

Formation of a stable, reproducible zinc oxide (ZnO) nanorod-network-based photosensitive field-effect transistor using a hydrothermal process at low temperature has been demonstrated. K2Cr2O7 additive was used to improve adhesion and facilitate growth of the ZnO nanorod network over the SiO2/Si substrate. Transistor characteristics obtained in the dark resemble those of the n-channel-mode field-effect transistor (FET). The devices showed I on/ I off ratio above 8 × 102 under dark condition, field-effect mobility of 4.49 cm2 V-1 s-1, and threshold voltage of -12 V. Further, under ultraviolet (UV) illumination, the FET exhibited sensitivity of 2.7 × 102 in off-state (-10 V) versus 1.4 in on-state (+9.7 V) of operation. FETs based on such nanorod networks showed good photoresponse, which is attributed to the large surface area of the nanorod network. The growth temperature for ZnO nanorod networks was kept at 110°C, enabling a low-temperature, cost-effective, simple approach for high-performance ZnO-based FETs for large-scale production. The role of network interfaces in the FET performance is also discussed.

High-power flexible AlGaN/GaN heterostructure field-effect transistors with suppression of negative differential conductance

NASA Astrophysics Data System (ADS)

Oh, Seung Kyu; Cho, Moon Uk; Dallas, James; Jang, Taehoon; Lee, Dong Gyu; Pouladi, Sara; Chen, Jie; Wang, Weijie; Shervin, Shahab; Kim, Hyunsoo; Shin, Seungha; Choi, Sukwon; Kwak, Joon Seop; Ryou, Jae-Hyun

2017-09-01

We investigate thermo-electronic behaviors of flexible AlGaN/GaN heterostructure field-effect transistors (HFETs) for high-power operation of the devices using Raman thermometry, infrared imaging, and current-voltage characteristics. A large negative differential conductance observed in HFETs on polymeric flexible substrates is confirmed to originate from the decreasing mobility of the two-dimensional electron gas channel caused by the self-heating effect. We develop high-power transistors by suppressing the negative differential conductance in the flexible HFETs using chemical lift-off and modified Ti/Au/In metal bonding processes with copper (Cu) tapes for high thermal conductivity and low thermal interfacial resistance in the flexible hybrid structures. Among different flexible HFETs, the ID of the HFETs on Cu with Ni/Au/In structures decreases only by 11.3% with increasing drain bias from the peak current to the current at VDS = 20 V, which is close to that of the HFETs on Si (9.6%), solving the problem of previous flexible AlGaN/GaN transistors.

Solution-processed field-effect transistors based on dihexylquaterthiophene films with performances exceeding those of vacuum-sublimed films.

PubMed

Leydecker, Tim; Trong Duong, Duc; Salleo, Alberto; Orgiu, Emanuele; Samorì, Paolo

2014-12-10

Solution-processable oligothiophenes are model systems for charge transport and fabrication of organic field-effect transistors (OFET) . Herein we report a structure vs function relationship study focused on the electrical characteristics of solution-processed dihexylquaterthiophene (DH4T)-based OFET. We show that by combining the tailoring of all interfaces in the bottom-contact bottom-gate transistor, via chemisorption of ad hoc molecules on electrodes and dielectric, with suitable choice of the film preparation conditions (including solvent type, concentration, volume, and deposition method), it is possible to fabricate devices exhibiting field-effect mobilities exceeding those of vacuum-processed DH4T transistors. In particular, the evaporation rate of the solvent, the processing temperature, as well as the concentration of the semiconducting material were found to hold a paramount importance in driving the self-assembly toward the formation of highly ordered and low-dimensional supramolecular architectures, confirming the kinetically governed nature of the self-assembly process. Among the various architectures, hundreds-of-micrometers long and thin DH4T crystallites exhibited enhanced charge transport.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Thickness-dependent electron mobility of single and few-layer MoS{sub 2} thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Ji Heon; Kim, Tae Ho; Lee, Hyunjea

We investigated the dependence of electron mobility on the thickness of MoS{sub 2} nanosheets by fabricating bottom-gate single and few-layer MoS{sub 2} thin-film transistors with SiO{sub 2} gate dielectrics and Au electrodes. All the fabricated MoS{sub 2} transistors showed on/off-current ratio of ∼10{sup 7} and saturated output characteristics without high-k capping layers. As the MoS{sub 2} thickness increased from 1 to 6 layers, the field-effect mobility of the fabricated MoS{sub 2} transistors increased from ∼10 to ∼18 cm{sup 2}V{sup −1}s{sup −1}. The increased subthreshold swing of the fabricated transistors with MoS{sub 2} thickness suggests that the increase of MoS{sub 2}more » mobility with thickness may be related to the dependence of the contact resistance and the dielectric constant of MoS{sub 2} layer on its thickness.« less

Electronic Model of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry (Technical Monitor)

2001-01-01

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Influence of non-adherent yeast cells on electrical characteristics of diamond-based field-effect transistors

NASA Astrophysics Data System (ADS)

Procházka, Václav; Cifra, Michal; Kulha, Pavel; Ižák, Tibor; Rezek, Bohuslav; Kromka, Alexander

2017-02-01

Diamond thin films provide unique features as substrates for cell cultures and as bio-electronic sensors. Here we employ solution-gated field effect transistors (SGFET) based on nanocrystalline diamond thin films with H-terminated surface which exhibits the sub-surface p-type conductive channel. We study an influence of yeast cells (Saccharomyces cerevisiae) on electrical characteristics of the diamond SGFETs. Two different cell culture solutions (sucrose and yeast peptone dextrose-YPD) are used, with and without the cells. We have found that transfer characteristics of the SGFETs exhibit a negative shift of the gate voltage by -26 mV and -42 mV for sucrose and YPD with cells in comparison to blank solutions without the cells. This effect is attributed to a local pH change in close vicinity of the H-terminated diamond surface due to metabolic processes of the yeast cells. The pH sensitivity of the diamond-based SGFETs, the role of cell and protein adhesion on the gate surface and the role of negative surface charge of yeast cells on the SGFETs electrical characteristics are discussed as well.

Characterization of Screen-Printed Organic Electrochemical Transistors to Detect Cations of Different Sizes.

PubMed

Contat-Rodrigo, Laura; Pérez-Fuster, Clara; Lidón-Roger, José Vicente; Bonfiglio, Annalisa; García-Breijo, Eduardo

2016-09-28

A novel screen-printing fabrication method was used to prepare organic electrochemical transistors (OECTs) based on poly(3,4-ethylenedioxythiophene) doped with polysterene sulfonate (PEDOT:PSS). Initially, three types of these screen-printed OECTs with a different channel and gate areas ratio were compared in terms of output characteristics, transfer characteristics, and current modulation in a phosphate buffered saline (PBS) solution. Results confirm that transistors with a gate electrode larger than the channel exhibit higher modulation. OECTs with this geometry were therefore chosen to investigate their ion-sensitive properties in aqueous solutions of cations of different sizes (sodium and rhodamine B). The effect of the gate electrode was additionally studied by comparing these all-PEDOT:PSS transistors with OECTs with the same geometry but with a non-polarizable metal gate (Ag). The operation of the all-PEDOT:PSS OECTs yields a response that is not dependent on a Na⁺ or rhodamine concentration. The weak modulation of these transistors can be explained assuming that PEDOT:PSS behaves like a supercapacitor. In contrast, the operation of Ag-Gate OECTs yields a response that is dependent on ion concentration due to the redox reaction taking place at the gate electrode with Cl - counter-ions. This indicates that, for cation detection, the response is maximized in OECTs with non-polarizable gate electrodes.

Charge transport in organic multi-layer devices under electric and optical fields

NASA Astrophysics Data System (ADS)

Park, June Hyoung

2007-12-01

Charge transport in small organic molecules and conjugated conducting polymers under electric or optical fields is studied by using field effect transistors and photo-voltaic cells with multiple thin layers. With these devices, current under electric field, photo-current under optical field, and luminescence of optical materials are measured to characterize organic and polymeric materials. For electric transport studies, poly(3,4-ethylenedioxythiophene) doped by polystyrenesulfonic acid is used, which is conductive with conductivity of approximately 25 S/cm. Despite their high conductance, field effect transistors based on the films are successfully built and characterized by monitoring modulations of drain current by gate voltage and IV characteristic curves. Due to very thin insulating layers of poly(vinylphenol), the transistors are relative fast under small gate voltage variation although heavy ions are involved in charge transport. In IV characteristic curves, saturation effects can be observed. Analysis using conventional field effect transistor model indicates high mobility of charge carriers, 10 cm2/V·sec, which is not consistent with the mobility of the conducting polymer. It is proposed that the effect of a small density of ions injected via polymer dielectric upon application of gate voltage and the ion compensation of key hopping sites accounts for the operation of the field effect transistors. For the studies of transport under optical field, photovoltaic cells with 3 different dendrons, which are efficient to harvest photo-excited electrons, are used. These dendrons consist of two electron-donors (tetraphenylporphyrin) and one electron-accepter (naphthalenediimide). Steady-state fluorescence measurements show that inter-molecular interaction is dominant in solid dendron film, although intra-molecular interaction is still present. Intra-molecular interaction is suggested by different fluorescence lifetimes between solutions of donor and dendrons. This intra-molecular interaction has two processes, transport via pi-stackings and transport via linking functional groups in the dendrons. IV characteristic spectra of the photovoltaic cells suggest that the transport route of photo-excited charges depends on wavelength of incident light on the cells. For excitation by the Soret band and the lowest Q band, a photo-excited electron can transport directly to a neighbor dendron. For excitation by high-energy Q bands, a photo-excited electron transports via the electron-accepters.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Accurate description of charge transport in organic field effect transistors using an experimentally extracted density of states

NASA Astrophysics Data System (ADS)

Roelofs, W. S. C.; Mathijssen, S. G. J.; Janssen, R. A. J.; de Leeuw, D. M.; Kemerink, M.

2012-02-01

The width and shape of the density of states (DOS) are key parameters to describe the charge transport of organic semiconductors. Here we extract the DOS using scanning Kelvin probe microscopy on a self-assembled monolayer field effect transistor (SAMFET). The semiconductor is only a single monolayer which has allowed extraction of the DOS over a wide energy range, pushing the methodology to its fundamental limit. The measured DOS consists of an exponential distribution of deep states with additional localized states on top. The charge transport has been calculated in a generic variable range-hopping model that allows any DOS as input. We show that with the experimentally extracted DOS an excellent agreement between measured and calculated transfer curves is obtained. This shows that detailed knowledge of the density of states is a prerequisite to consistently describe the transfer characteristics of organic field effect transistors.

Investigation of the evolution of nitrogen defects in flash-lamp-annealed InGaZnO films and their effects on transistor characteristics

NASA Astrophysics Data System (ADS)

Eom, Tae-Yil; Ahn, Chee-Hong; Kang, Jun-Gu; Saad Salman, Muhammad; Lee, Sun-Young; Kim, Yong-Hoon; Lee, Hoo-Jeong; Kang, Chan-Mo; Kang, Chiwon

2018-06-01

In this study, we show the evolution of nitrogen defects during a sol–gel reaction in flash-lamp-annealed InGaZnO (IGZO) films and their effects on the device characteristics of their thin-film transistors (TFTs). The flash lamp annealing (FLA) of the IGZO TFT for 16 s helps achieve a mobility of approximately 7 cm2 V‑1 s‑1. However, further extension of the annealing time results only in drastic increases in carrier concentration and off-current. The X-ray photoelectron spectroscopy (XPS) analysis of the N 1s peak unravels the presence of oxygen-vacancy-associated nitrogen defects and their evolution with annealing time, which is possibly responsible for the increase in carrier concentration.

Performance regeneration of InGaZnO transistors with ultra-thin channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Binglei; Li, He; Zhang, Xijian, E-mail: zhangxijian@sdu.edu.cn, E-mail: songam@sdu.edu.cn

2015-03-02

Thin-film transistors (TFTs) based on ultra-thin amorphous indium gallium zinc oxide (a-IGZO) semiconductors down to 4 nm were studied motivated by the increasing cost of indium. At and below 5 nm, it was found that the field-effect mobility was severely degraded, the threshold voltage increased, and the output characteristics became abnormal showing no saturated current. By encapsulating a layer of polymethyl methacrylate on the IGZO TFTs, the performance of the 5-nm-thick device was effectively recovered. The devices also showed much higher on/off ratios, improved hysteresis, and normal output characteristic curves as compared with devices not encapsulated. The stability of the encapsulated devicesmore » was also studied over a four month period.« less

Analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Hui Fang; Sun, Wen; Han, Xin Feng

2018-06-01

An analytical model of surface potential profiles and transfer characteristics for hetero stacked tunnel field-effect transistors (HS-TFETs) is presented for the first time, where hetero stacked materials are composed of two different bandgaps. The bandgap of the underlying layer is smaller than that of the upper layer. Under different device parameters (upper layer thickness, underlying layer thickness, and hetero stacked materials) and temperature, the validity of the model is demonstrated by the agreement of its results with the simulation results. Moreover, the results show that the HS-TFETs can obtain predominant performance with relatively slow changes of subthreshold swing (SS) over a wide drain current range, steep average subthreshold swing, high on-state current, and large on–off state current ratio.

A computational study of a novel graphene nanoribbon field effect transistor

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Two dimensional simulation of patternable conducting polymer electrode based organic thin film transistor

NASA Astrophysics Data System (ADS)

Nair, Shiny; Kathiresan, M.; Mukundan, T.

2018-02-01

Device characteristics of organic thin film transistor (OTFT) fabricated with conducting polyaniline:polystyrene sulphonic acid (PANi-PSS) electrodes, patterned by the Parylene lift-off method are systematically analyzed by way of two dimensional numerical simulation. The device simulation was performed taking into account field-dependent mobility, low mobility layer at the electrode-semiconductor interface, trap distribution in pentacene film and trapped charge at the organic/insulator interface. The electrical characteristics of bottom contact thin film transistor with PANi-PSS electrodes and pentacene active material is superior to those with palladium electrodes due to a lower charge injection barrier. Contact resistance was extracted in both cases by the transfer line method (TLM). The extracted charge concentration and potential profile from the two dimensional numerical simulation was used to explain the observed electrical characteristics. The simulated device characteristics not only matched the experimental electrical characteristics, but also gave an insight on the charge injection, transport and trap properties of the OTFTs as a function of different electrode materials from the perspectives of transistor operation.

Field-effect transistors as electrically controllable nonlinear rectifiers for the characterization of terahertz pulses

NASA Astrophysics Data System (ADS)

Lisauskas, Alvydas; Ikamas, Kestutis; Massabeau, Sylvain; Bauer, Maris; ČibiraitÄ--, DovilÄ--; Matukas, Jonas; Mangeney, Juliette; Mittendorff, Martin; Winnerl, Stephan; Krozer, Viktor; Roskos, Hartmut G.

2018-05-01

We propose to exploit rectification in field-effect transistors as an electrically controllable higher-order nonlinear phenomenon for the convenient monitoring of the temporal characteristics of THz pulses, for example, by autocorrelation measurements. This option arises because of the existence of a gate-bias-controlled super-linear response at sub-threshold operation conditions when the devices are subjected to THz radiation. We present measurements for different antenna-coupled transistor-based THz detectors (TeraFETs) employing (i) AlGaN/GaN high-electron-mobility and (ii) silicon CMOS field-effect transistors and show that the super-linear behavior in the sub-threshold bias regime is a universal phenomenon to be expected if the amplitude of the high-frequency voltage oscillations exceeds the thermal voltage. The effect is also employed as a tool for the direct determination of the speed of the intrinsic TeraFET response which allows us to avoid limitations set by the read-out circuitry. In particular, we show that the build-up time of the intrinsic rectification signal of a patch-antenna-coupled CMOS detector changes from 20 ps in the deep sub-threshold voltage regime to below 12 ps in the vicinity of the threshold voltage.

PRESSURE TRANSDUCER

DOEpatents

Sander, H.H.

1959-10-01

A pressure or mechanical force transducer particularly adaptable to miniature telemetering systems is described. Basically the device consists of a transistor located within a magnetic field adapted to change in response to mechanical force. The conduction characteristics of the transistor in turn vary proportionally with changes in the magnetic flux across the transistor such that the output (either frequency of amplitude) of the transistor circuit is proportional to mechanical force or pressure.

Organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Electrically controlled wire-channel GaN/AlGaN transistor for terahertz plasma applications

NASA Astrophysics Data System (ADS)

Cywiński, G.; Yahniuk, I.; Kruszewski, P.; Grabowski, M.; Nowakowski-Szkudlarek, K.; Prystawko, P.; Sai, P.; Knap, W.; Simin, G. S.; Rumyantsev, S. L.

2018-03-01

We report on a design of fin-shaped channel GaN/AlGaN field-effect transistors developed for studying resonant terahertz plasma oscillations. Unlike common two dimensional FinFET transistor design, the gates were deposited only to the sides of the two dimensional electron gas channel, i.e., metal layers were not deposited on the top of the AlGaN. This side gate configuration allowed us to electrically control the conductivity of the channel by changing its width while keeping the carrier density and mobility virtually unchanged. Computer simulations and analytical model describe well the general shape of the characteristics. The side gate control of the channel width of these transistors allowed us to eliminate the so-called oblique plasma wave modes and paves the way towards future terahertz detectors and emitters using high quality factor plasma wave resonances.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

Modeling of phonon scattering in n-type nanowire transistors using one-shot analytic continuation technique

NASA Astrophysics Data System (ADS)

Bescond, Marc; Li, Changsheng; Mera, Hector; Cavassilas, Nicolas; Lannoo, Michel

2013-10-01

We present a one-shot current-conserving approach to model the influence of electron-phonon scattering in nano-transistors using the non-equilibrium Green's function formalism. The approach is based on the lowest order approximation (LOA) to the current and its simplest analytic continuation (LOA+AC). By means of a scaling argument, we show how both LOA and LOA+AC can be easily obtained from the first iteration of the usual self-consistent Born approximation (SCBA) algorithm. Both LOA and LOA+AC are then applied to model n-type silicon nanowire field-effect-transistors and are compared to SCBA current characteristics. In this system, the LOA fails to describe electron-phonon scattering, mainly because of the interactions with acoustic phonons at the band edges. In contrast, the LOA+AC still well approximates the SCBA current characteristics, thus demonstrating the power of analytic continuation techniques. The limits of validity of LOA+AC are also discussed, and more sophisticated and general analytic continuation techniques are suggested for more demanding cases.

pn-Heterojunction effects of perylene tetracarboxylic diimide derivatives on pentacene field-effect transistor.

PubMed

Yu, Seong Hun; Kang, Boseok; An, Gukil; Kim, BongSoo; Lee, Moo Hyung; Kang, Moon Sung; Kim, Hyunjung; Lee, Jung Heon; Lee, Shichoon; Cho, Kilwon; Lee, Jun Young; Cho, Jeong Ho

2015-01-28

We investigated the heterojunction effects of perylene tetracarboxylic diimide (PTCDI) derivatives on the pentacene-based field-effect transistors (FETs). Three PTCDI derivatives with different substituents were deposited onto pentacene layers and served as charge transfer dopants. The deposited PTCDI layer, which had a nominal thickness of a few layers, formed discontinuous patches on the pentacene layers and dramatically enhanced the hole mobility in the pentacene FET. Among the three PTCDI molecules tested, the octyl-substituted PTCDI, PTCDI-C8, provided the most efficient hole-doping characteristics (p-type) relative to the fluorophenyl-substituted PTCDIs, 4-FPEPTC and 2,4-FPEPTC. The organic heterojunction and doping characteristics were systematically investigated using atomic force microscopy, 2D grazing incidence X-ray diffraction studies, and ultraviolet photoelectron spectroscopy. PTCDI-C8, bearing octyl substituents, grew laterally on the pentacene layer (2D growth), whereas 2,4-FPEPTC, with fluorophenyl substituents, underwent 3D growth. The different growth modes resulted in different contact areas and relative orientations between the pentacene and PTCDI molecules, which significantly affected the doping efficiency of the deposited adlayer. The differences between the growth modes and the thin-film microstructures in the different PTCDI patches were attributed to a mismatch between the surface energies of the patches and the underlying pentacene layer. The film-morphology-dependent doping effects observed here offer practical guidelines for achieving more effective charge transfer doping in thin-film transistors.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Carrier statistics and quantum capacitance effects on mobility extraction in two-dimensional crystal semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Ma, Nan; Jena, Debdeep

2015-03-01

In this work, the consequence of the high band-edge density of states on the carrier statistics and quantum capacitance in transition metal dichalcogenide two-dimensional semiconductor devices is explored. The study questions the validity of commonly used expressions for extracting carrier densities and field-effect mobilities from the transfer characteristics of transistors with such channel materials. By comparison to experimental data, a new method for the accurate extraction of carrier densities and mobilities is outlined. The work thus highlights a fundamental difference between these materials and traditional semiconductors that must be considered in future experimental measurements.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact

PubMed Central

Lin, Yu-Ru; Tsai, Wan-Ting; Wu, Yung-Chun; Lin, Yu-Hsien

2017-01-01

This study demonstrated an ultra thin poly-Si junctionless nanosheet field-effect transistor (JL NS-FET) with nickel silicide contact. For the nickel silicide film, two-step annealing and a Ti capping layer were adopted to form an ultra thin uniform nickel silicide film with low sheet resistance (Rs). The JL NS-FET with nickel silicide contact exhibited favorable electrical properties, including a high driving current (>107A), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this study compared the electrical characteristics of JL NS-FETs with and without nickel silicide contact. PMID:29112139

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact.

PubMed

Lin, Yu-Ru; Tsai, Wan-Ting; Wu, Yung-Chun; Lin, Yu-Hsien

2017-11-07

This study demonstrated an ultra thin poly-Si junctionless nanosheet field-effect transistor (JL NS-FET) with nickel silicide contact. For the nickel silicide film, two-step annealing and a Ti capping layer were adopted to form an ultra thin uniform nickel silicide film with low sheet resistance (Rs). The JL NS-FET with nickel silicide contact exhibited favorable electrical properties, including a high driving current (>10⁷A), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this study compared the electrical characteristics of JL NS-FETs with and without nickel silicide contact.

AlGaN/GaN field effect transistors for power electronics—Effect of finite GaN layer thickness on thermal characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hodges, C., E-mail: chris.hodges@bristol.ac.uk; Anaya Calvo, J.; Kuball, M.

2013-11-11

AlGaN/GaN heterostructure field effect transistors with a 150 nm thick GaN channel within stacked Al{sub x}Ga{sub 1−x}N layers were investigated using Raman thermography. By fitting a thermal simulation to the measured temperatures, the thermal conductivity of the GaN channel was determined to be 60 W m{sup −1} K{sup −1}, over 50% less than typical GaN epilayers, causing an increased peak channel temperature. This agrees with a nanoscale model. A low thermal conductivity AlGaN buffer means the GaN spreads heat; its properties are important for device thermal characteristics. When designing power devices with thin GaN layers, as well as electrical considerations, the reducedmore » channel thermal conductivity must be considered.« less

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Lim, Cheol-Min

2018-02-01

In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

Memristive device based on a depletion-type SONOS field effect transistor

NASA Astrophysics Data System (ADS)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

2008-01-01

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Codoping of zinc and tungsten for practical high-performance amorphous indium-based oxide thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kizu, Takio, E-mail: KIZU.Takio@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Tsukagoshi, Kazuhito, E-mail: KIZU.Takio@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp

2015-09-28

Using practical high-density sputtering targets, we investigated the effect of Zn and W codoping on the thermal stability of the amorphous film and the electrical characteristics in thin film transistors. zinc oxide is a potentially conductive component while W oxide is an oxygen vacancy suppressor in oxide films. The oxygen vacancy from In-O and Zn-O was suppressed by the W additive because of the high oxygen bond dissociation energy. With controlled codoping of W and Zn, we demonstrated a high mobility with a maximum mobility of 40 cm{sup 2}/V s with good stability under a negative bias stress in InWZnO thinmore » film transistors.« less

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

PubMed

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

Effect of quantum well position on the distortion characteristics of transistor laser

NASA Astrophysics Data System (ADS)

Piramasubramanian, S.; Ganesh Madhan, M.; Radha, V.; Shajithaparveen, S. M. S.; Nivetha, G.

2018-05-01

The effect of quantum well position on the modulation and distortion characteristics of a 1300 nm transistor laser is analyzed in this paper. Standard three level rate equations are numerically solved to study this characteristics. Modulation depth, second order harmonic and third order intermodulation distortion of the transistor laser are evaluated for different quantum well positions for a 900 MHz RF signal modulation. From the DC analysis, it is observed that optical power is maximum, when the quantum well is positioned near base-emitter interface. The threshold current of the device is found to increase with increasing the distance between the quantum well and the base-emitter junction. A maximum modulation depth of 0.81 is predicted, when the quantum well is placed at 10 nm from the base-emitter junction, under RF modulation. The magnitude of harmonic and intermodulation distortion are found to decrease with increasing current and with an increase in quantum well distance from the emitter base junction. A minimum second harmonic distortion magnitude of -25.96 dBc is predicted for quantum well position (230 nm) near to the base-collector interface for 900 MHz modulation frequency at a bias current of 20 Ibth. Similarly, a minimum third order intermodulation distortion of -38.2 dBc is obtained for the same position and similar biasing conditions.

Charge-Trapping-Induced Non-Ideal Behaviors in Organic Field-Effect Transistors.

PubMed

Un, Hio-Ieng; Cheng, Peng; Lei, Ting; Yang, Chi-Yuan; Wang, Jie-Yu; Pei, Jian

2018-05-01

Organic field-effect transistors (OFETs) with impressively high hole mobilities over 10 cm 2 V -1 s -1 and electron mobilities over 1 cm 2 V -1 s -1 have been reported in the past few years. However, significant non-ideal electrical characteristics, e.g., voltage-dependent mobilities, have been widely observed in both small-molecule and polymer systems. This issue makes the accurate evaluation of the electrical performance impossible and also limits the practical applications of OFETs. Here, a semiconductor-unrelated, charge-trapping-induced non-ideality in OFETs is reported, and a revised model for the non-ideal transfer characteristics is provided. The trapping process can be directly observed using scanning Kelvin probe microscopy. It is found that such trapping-induced non-ideality exists in OFETs with different types of charge carriers (p-type or n-type), different types of dielectric materials (inorganic and organic) that contain different functional groups (OH, NH 2 , COOH, etc.). As fas as it is known, this is the first report for the non-ideal transport behaviors in OFETs caused by semiconductor-independent charge trapping. This work reveals the significant role of dielectric charge trapping in the non-ideal transistor characteristics and also provides guidelines for device engineering toward ideal OFETs. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Current-voltage characteristics influenced by the nanochannel diameter and surface charge density in a fluidic field-effect-transistor.

PubMed

Singh, Kunwar Pal; Guo, Chunlei

2017-06-21

The nanochannel diameter and surface charge density have a significant impact on current-voltage characteristics in a nanofluidic transistor. We have simulated the effect of the channel diameter and surface charge density on current-voltage characteristics of a fluidic nanochannel with positive surface charge on its walls and a gate electrode on its surface. Anion depletion/enrichment leads to a decrease/increase in ion current with gate potential. The ion current tends to increase linearly with gate potential for narrow channels at high surface charge densities and narrow channels are more effective to control the ion current at high surface charge densities. The current-voltage characteristics are highly nonlinear for wide channels at low surface charge densities and they show different regions of current change with gate potential. The ion current decreases with gate potential after attaining a peak value for wide channels at low values of surface charge densities. At low surface charge densities, the ion current can be controlled by a narrow range of gate potentials for wide channels. The current change with source drain voltage shows ohmic, limiting and overlimiting regions.

Summary of Research 2000: Department of Electrical and Computer Engineering

DTIC Science & Technology

2001-12-01

provides promising radiation hardening characteristics but the effect of microdose issues are not understood. As transistors shrink, trapping of small...examines the effects of enacting a microdose single event effect (SEE) upon a thick gate oxide of an SOI MOS capacitor in order to determine the degree

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks

PubMed Central

Rogers, John A.; Bao, Zhenan; Baldwin, Kirk; Dodabalapur, Ananth; Crone, Brian; Raju, V. R.; Kuck, Valerie; Katz, Howard; Amundson, Karl; Ewing, Jay; Drzaic, Paul

2001-01-01

Electronic systems that use rugged lightweight plastics potentially offer attractive characteristics (low-cost processing, mechanical flexibility, large area coverage, etc.) that are not easily achieved with established silicon technologies. This paper summarizes work that demonstrates many of these characteristics in a realistic system: organic active matrix backplane circuits (256 transistors) for large (≈5 × 5-inch) mechanically flexible sheets of electronic paper, an emerging type of display. The success of this effort relies on new or improved processing techniques and materials for plastic electronics, including methods for (i) rubber stamping (microcontact printing) high-resolution (≈1 μm) circuits with low levels of defects and good registration over large areas, (ii) achieving low leakage with thin dielectrics deposited onto surfaces with relief, (iii) constructing high-performance organic transistors with bottom contact geometries, (iv) encapsulating these transistors, (v) depositing, in a repeatable way, organic semiconductors with uniform electrical characteristics over large areas, and (vi) low-temperature (≈100°C) annealing to increase the on/off ratios of the transistors and to improve the uniformity of their characteristics. The sophistication and flexibility of the patterning procedures, high level of integration on plastic substrates, large area coverage, and good performance of the transistors are all important features of this work. We successfully integrate these circuits with microencapsulated electrophoretic “inks” to form sheets of electronic paper. PMID:11320233

Protein Viability on Au Nanoparticles during an Electrospray and Electrostatic-Force-Directed Assembly Process

DOE PAGES

Mao, Shun; Lu, Ganhua; Yu, Kehan; ...

2010-01-01

We study the protein viability on Au nanoparticles during an electrospray and electrostatic-force-directed assembly process, through which Au nanoparticle-antibody conjugates are assembled onto the surface of carbon nanotubes (CNTs) to fabricate carbon nanotube field-effect transistor (CNTFET) biosensors. Enzyme-linked immunosorbent assay (ELISA) and field-effect transistor (FET) measurements have been used to investigate the antibody activity after the nanoparticle assembly. Upon the introduction of matching antigens, the colored reaction from the ELISA and the change in the electrical characteristic of the CNTFET device confirm that the antibody activity is preserved during the assembly process.

Influence of thermocleavable functionality on organic field-effect transistor performance of small molecules

NASA Astrophysics Data System (ADS)

Mahale, Rajashree Y.; Dharmapurikar, Satej S.; Chini, Mrinmoy Kumar; Venugopalan, Vijay

2017-06-01

Diketopyrrolopyrrole based donor-acceptor-donor conjugated small molecules using ethylene dioxythiophene as a donor was synthesized. Electron deficient diketopyrrolopyrrole unit was substituted with thermocleavable (tert-butyl acetate) side chains. The thermal treatment of the molecules at 160 °C eliminated the tert-butyl ester group results in the formation of corresponding acid. Optical and theoretical studies revealed that the molecules adopted a change in molecular arrangement after thermolysis. The conjugated small molecules possessed p-channel charge transport characteristics in organic field effect transistors. The charge carrier mobility was increased after thermolysis of tert-butyl ester group to 5.07 × 10-5 cm2/V s.

Solution-processed small molecule-polymer blend organic thin-film transistors with hole mobility greater than 5 cm2/Vs.

PubMed

Smith, Jeremy; Zhang, Weimin; Sougrat, Rachid; Zhao, Kui; Li, Ruipeng; Cha, Dongkyu; Amassian, Aram; Heeney, Martin; McCulloch, Iain; Anthopoulos, Thomas D

2012-05-08

Using phase-separated organic semiconducting blends containing a small molecule, as the hole transporting material, and a conjugated amorphous polymer, as the binder material, we demonstrate solution-processed organic thin-film transistors with superior performance characteristics that include; hole mobility >5 cm(2) /Vs, current on/off ratio ≥10(6) and narrow transistor parameter spread. These exceptional characteristics are attributed to the electronic properties of the binder polymer and the advantageous nanomorphology of the blend film. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Cody; Hunt, Mitchell; Ho, Fat D.; MacLeod, Todd C.

2012-01-01

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

Traps and Interface Fixed Charge Effects on a Solution-Processed n-Type Polymeric-Based Organic Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Hafsi, B.; Boubaker, A.; Guerin, D.; Lenfant, S.; Kalboussi, A.; Lmimouni, K.

2017-02-01

Organic field-effect transistors based on poly{[ N, N0- bis(2-octyldodecyl)- naphthalene-1,4,5,8- bis(dicarboximide)-2,6-diyl]-alt-5,50-(2,20-bithiophene)}, [P(NDI2OD-T2)n], were fabricated and characterized. The effect of octadecyltrichlorosilane (OTS) a self-assembled monolayer (SAM) grafted on to a SiO2 gate dielectric was investigated. A significant improvement of the charge mobility ( μ), up to 0.22 cm2/V s, was reached thanks to the OTS treatment. Modifying some technological parameters relating to fabrication, such as solvents, was also studied. We have analyzed the electrical properties of these thin-film transistors by using a two-dimensional drift-diffusion simulator, Integrated System Engineering-Technology Computer Aided Design (ISE-TCAD®). We studied the fixed surface charges at the organic semiconductor/oxide interface and the bulk traps effect. The dependence of the threshold voltage on the density and energy level of the trap states has also been considered. We finally found a good agreement between the output and transfer characteristics for experimental and simulated data.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Electrical characteristics of proton-irradiated Sc2O3 passivated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Luo, B.; Kim, Jihyun; Ren, F.; Gillespie, J. K.; Fitch, R. C.; Sewell, J.; Dettmer, R.; Via, G. D.; Crespo, A.; Jenkins, T. J.; Gila, B. P.; Onstine, A. H.; Allums, K. K.; Abernathy, C. R.; Pearton, S. J.; Dwivedi, R.; Fogarty, T. N.; Wilkins, R.

2003-03-01

Sc2O3-passivated AlGaN/GaN high electron mobility transistors (HEMTs) were irradiated with 40 MeV protons to a fluence corresponding to approximately 10 years in low-earth orbit (5×109 cm-2). Devices with an AlGaN cap layer showed less degradation in dc characteristics than comparable GaN-cap devices, consistent with differences in average band energy. The changes in device performance could be attributed completely to bulk trapping effects, demonstrating that the effectiveness of the Sc2O3 layers in passivating surface states in the drain-source region was undiminished by the proton irradiation. Sc2O3-passivated AlGaN/HEMTs appear to be attractive candidates for space and terrestrial applications where resistance to high fluxes of ionizing radiation is a criteria.

Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D., E-mail: t.anthopoulos@imperial.ac.uk

2015-03-02

Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm{sup 2}V{sup −1}s{sup −1} and 16 cm{sup 2}V{sup −1}s{sup −1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (≤250 °C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50 μm-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even whenmore » bent to tensile radii of 4 mm.« less

Nanocrystal-mediated charge screening effects in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, C. J.; Yeom, D. H.; Jeong, D. Y.; Lee, M. G.; Moon, B. M.; Kim, S. S.; Choi, C. Y.; Koo, S. M.

2009-03-01

ZnO nanowire field-effect transistors having an omega-shaped floating gate (OSFG) have been successfully fabricated by directly coating CdTe nanocrystals (˜6±2.5 nm) at room temperature, and compared to simultaneously prepared control devices without nanocrystals. Herein, we demonstrate that channel punchthrough may occur when the depletion from the OSFG takes place due to the trapped charges in the nanocrystals. Electrical measurements on the OSFG nanowire devices showed static-induction transistorlike behavior in the drain output IDS-VDS characteristics and a hysteresis window as large as ˜3.1 V in the gate transfer IDS-VGS characteristics. This behavior is ascribed to the presence of the CdTe nanocrystals, and is indicative of the trapping and emission of electrons in the nanocrystals. The numerical simulations clearly show qualitatively the same characteristics as the experimental data and confirm the effect, showing that the change in the potential distribution across the channel, induced by both the wrapping-around gate and the drain, affects the transport characteristics of the device. The cross-sectional energy band and potential profile of the OSFG channel corresponding to the "programed (noncharged)" and "erased (charged)" operations for the device are also discussed on the basis of the numerical capacitance-voltage simulations.

Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

NASA Astrophysics Data System (ADS)

Estrada, M.; Hernandez-Barrios, Y.; Cerdeira, A.; Ávila-Herrera, F.; Tinoco, J.; Moldovan, O.; Lime, F.; Iñiguez, B.

2017-09-01

A crystalline-like temperature dependence of the electrical characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) is reported, in which the drain current reduces as the temperature is increased. This behavior appears for values of drain and gate voltages above which a change in the predominant conduction mechanism occurs. After studying the possible conduction mechanisms, it was determined that, for gate and drain voltages below these values, hopping is the predominant mechanism with the current increasing with temperature, while for values above, the predominant conduction mechanism becomes percolation in the conduction band or band conduction and IDS reduces as the temperature increases. It was determined that this behavior appears, when the effect of trapping is reduced, either by varying the density of states, their characteristic energy or both. Simulations were used to further confirm the causes of the observed behavior.

Air-stable n-channel organic thin-film transistors with high field-effect mobility based on N ,N'-bis(heptafluorobutyl)-3,4:9,10-perylene diimide

NASA Astrophysics Data System (ADS)

Oh, Joon Hak; Liu, Shuhong; Bao, Zhenan; Schmidt, Rüdiger; Würthner, Frank

2007-11-01

The thin-film transistor characteristics of n-channel organic semiconductor, N ,N'-bis(2,2,3,3,4,4,4-heptafluorobutyl)-perylene tetracarboxylic diimide, are described. The slip-stacked face-to-face molecular packing allows a very dense parallel arrangement of the molecules, leading to field-effect mobility as high as 0.72cm2V-1s-1. The mobility only slightly decreased after exposure to air and remained stable for more than 50days. Our results reveal that molecular packing effects such as close stacking of perylene diimide units and segregation effects imparted by the fluorinated side chains are crucial for the air stability.

Synthesis of bilayer MoS2 and corresponding field effect characteristics

NASA Astrophysics Data System (ADS)

Fang, Mingxu; Feng, Yulin; Wang, Fang; Yang, Zhengchun; Zhang, Kailiang

2017-06-01

Two-dimensional transition-metal dichalcogenides such as MoS2 are promising materials for next-generation nano-electronic devices. The physical properties of MoS2 are determined by layer number according to the variation of band-gap. Here, we synthesize large-size bilayer-MoS2 with triangle and hexagonal nanosheets in one step by chemical vapor deposition, Monolayer and bilayer-MoS2 back-gate field effect transistors are also fabricated and the performance including mobility and on/off ratios are compared. The bilayer-MoS2 back-gate field effect transistor shows superior performance with field effect mobility of ∼21.27cm2V-1s-1, and Ion/Ioff ratio of ∼3.9×107.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

2018-01-01

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Radiation-stimulated processes in transistor temperature sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pavlyk, B. V.; Grypa, A. S.

2016-05-15

The features of the radiation-stimulated changes in the I–V and C–V characteristics of the emitter–base junction in KT3117 transistors are considered. It is shown that an increase in the current through the emitter junction is observed at the initial stage of irradiation (at doses of D < 4000 Gy for the “passive” irradiation mode and D < 5200 Gy for the “active” mode), which is caused by the effect of radiation-stimulated ordering of the defect-containing structure of the p–n junction. It is also shown that the X-ray irradiation (D < 14000 Gy), the subsequent relaxation (96 h), and thermal annealingmore » (2 h at 400 K) of the transistor temperature sensors under investigation result in an increase in their radiation resistance.« less

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Flexible thin-film transistors on plastic substrate at room temperature.

PubMed

Han, Dedong; Wang, Wei; Cai, Jian; Wang, Liangliang; Ren, Yicheng; Wang, Yi; Zhang, Shengdong

2013-07-01

We have fabricated flexible thin-film transistors (TFTs) on plastic substrates using Aluminum-doped ZnO (AZO) as an active channel layer at room temperature. The AZO-TFTs showed n-channel device characteristics and operated in enhancement mode. The device shows a threshold voltage of 1.3 V, an on/off ratio of 2.7 x 10(7), a field effect mobility of 21.3 cm2/V x s, a subthreshold swing of 0.23 V/decade, and the off current of less than 10(-12) A at room temperature. Recently, the flexible displays have become a very hot topic. Flexible thin film transistors are key devices for realizing flexible displays. We have investigated AZO-TFT on flexible plastic substrate, and high performance flexible TFTs have been obtained.

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Sha Li, Chen; Li, Yu Ning; Wu, Yi Liang; Ong, Beng S.; Loutfy, Rafik O.

2008-06-01

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process.

Characterization and Modeling of Nano-organic Thin Film Phototransistors Based on 6,13(Triisopropylsilylethynyl)-Pentacene: Photovoltaic Effect

NASA Astrophysics Data System (ADS)

Jouili, A.; Mansouri, S.; Al-Ghamdi, Ahmed A.; El Mir, L.; Farooq, W. A.; Yakuphanoglu, F.

2017-04-01

Organic thin film transistors based on 6,13(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) with various channel widths and thicknesses of the active layer (300 nm and 135 nm) were photo-characterized. The photoresponse behavior and the gate field dependence of the charge transport were analyzed in detail. The surface properties of TIPS-pentacene deposited on silicon dioxide substrate were investigated using an atomic force microscope. We confirm that the threshold voltage values of the TIPS-pentacene transistor depend on the intensity of white light illumination. With the multiple trapping and release model, we have developed an analytical model that was applied to reproduce the experimental output characteristics of organic thin film transistors based on TIPS-pentacene under dark and under light illumination.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Electrical characteristics of high-power AlGaN-GaN high electron mobility transistors irradiated with protons and heavy ions

NASA Astrophysics Data System (ADS)

Sin, Yongkun; Bonsall, Jeremy; Lingley, Zachary; Brodie, Miles; Mason, Maribeth

2017-02-01

High electron mobility transistors (HEMTs) based on AlGaN-GaN hetero-structures are finding an increasing number of commercial and military applications that require high voltage, high power, and high efficiency operation. In recent years, leading GaN HEMT manufacturers have reported excellent RF power characteristics and encouraging reliability, but long-term reliability in the space environment still remains a major concern due to a large number of defects and traps present both in the bulk as well as at the surface, leading to undesirable characteristics including current collapse. Furthermore, degradation mechanisms in GaN HEMTs are still not well understood. Thus, reliability and radiation effects of GaN HEMTs should be studied before solid state power amplifiers (SSPAs) based on GaN HEMT technology are successfully deployed in space satellite systems. For the present study, we investigated electrical characteristics of high-power GaN HEMTs irradiated with protons and heavy ions under various irradiation and biasing conditions.

Effect of interface-dependent crystalline boundary on sub-threshold characteristics in a solution-processed 6,13-bis(triisopropylsilylethynyl)-pentacene thin-film transistor

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Kang, In Man; Bae, Jin-Hyuk

2014-03-01

We demonstrate how the sub-threshold characteristics are affected by the density of crystalline domain boundaries directly governed by an organic semiconductor (OSC) - a gate insulator interface in a solution-processed 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) thin-film transistor (TFT). For generation of an engineered interface, a self assembled monolayer of octadecyltricholorosilane (OTS) was produced between a solution processed TIPS-pentacene film and a silicon dioxide layer. The interfacial charge trap density (Ntrap) deduced from the sub-threshold characteristics was significantly minimized after OTS treatment due to reduced crystal domain boundaries in the TIPS-pentacene film. In addition, the carrier mobility exhibits a value twice as large by OTS treatment. It is found that less crystal domain boundaries in the solution-processed OSC obtained from the engineered interface play an important role in inducing improved sub-threshold characteristics together with increased carrier mobility in organic TFTs.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Comprehensive review on the development of high mobility in oxide thin film transistors

NASA Astrophysics Data System (ADS)

Choi, Jun Young; Lee, Sang Yeol

2017-11-01

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility ( μ FE ), subthreshold swing (S.S) and threshold voltage ( V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V. A. L.

2013-02-01

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics.The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics. Electronic supplementary information (ESI) available: UV-vis spectrum of Au nanoparticle aqueous solution, transfer characteristics of the transistors without inserting an Au nanoparticle monolayer, AFM image of the pentacene layer, transfer characteristics at different program voltages and memory windows with respect to the P/E voltage. See DOI: 10.1039/c2nr32579a

Thin-film transistors with a graphene oxide nanocomposite channel.

PubMed

Jilani, S Mahaboob; Gamot, Tanesh D; Banerji, P

2012-12-04

Graphene oxide (GO) and graphene oxide-zinc oxide nanocomposites (GO-ZnO) were used as channel materials on SiO(2)/Si to fabricate thin-film transistors (TFT) with an aluminum source and drain. Pure GO-based TFT showed poor field-effect characteristics. However, GO-ZnO-nanocomposite-based TFT showed better field-effect performance because of the anchoring of ZnO nanostructures in the GO matrix, which causes a partial reduction in GO as is found from X-ray photoelectron spectroscopic data. The field-effect mobility of charge carriers at a drain voltage of 1 V was found to be 1.94 cm(2)/(V s). The transport of charge carriers in GO-ZnO was explained by a fluctuation-induced tunneling mechanism.

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction

NASA Astrophysics Data System (ADS)

Mohamad, B.; Leroux, C.; Reimbold, G.; Ghibaudo, G.

2018-01-01

For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.

Effects of Gold Nanoparticles on Pentacene Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Lee, Keanchuan; Weis, Martin; Ou-Yang, Wei; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2011-04-01

The effect of gold nanoparticles (NPs) on pentacene organic field-effect transistors (OFETs) was being investigated by both DC and AC methods, which are current-voltage (I-V) measurements in steady-state and impedance spectroscopy (IS) respectively. Here poly(vinyl alcohol) (PVA) and PVA blended with Au NPs as composite are spin-coated on SiO2 as gate-insulator for top-contact pentacene OFET. The characteristics of the device were being investigated based on the contact resistance, trapped charges, effective mobility and threshold voltage based on transfer characteristics of OFET. Results revealed that OFET with NPs exhibited larger hysteresis and higher contact resistance at high voltage region. IS measurements were performed and the fitting of results by the Maxwell-Wagner equivalent circuit showed that for device with NPs a series of capacitance and resistance which represents trapping must be introduced in order to have agreeable fitting. The fitting had helped to clarify the reason behind the higher contact resistance and bigger hysteresis which was mainly caused by the space charge field formed by the traps when Au NPs were introduced into the device.

Transfer characteristics and low-frequency noise in single- and multi-layer MoS{sub 2} field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharma, Deepak; Theiss Research, Inc., La Jolla, California 92037; Department of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia 22030

Leveraging nanoscale field-effect transistors (FETs) in integrated circuits depends heavily on its transfer characteristics and low-frequency noise (LFN) properties. Here, we report the transfer characteristics and LFN in FETs fabricated with molybdenum disulfide (MoS{sub 2}) with different layer (L) counts. 4L to 6L devices showed highest I{sub ON}-I{sub OFF} ratio (≈10{sup 8}) whereas LFN was maximum for 1L device with normalized power spectral density (PSD) ≈1.5 × 10{sup −5 }Hz{sup −1}. For devices with L ≈ 6, PSD was minimum (≈2 × 10{sup −8 }Hz{sup −1}). Further, LFN for single and few layer devices satisfied carrier number fluctuation (CNF) model in both weak andmore » strong accumulation regimes while thicker devices followed Hooge's mobility fluctuation model in the weak accumulation regime and CNF model in strong accumulation regime, respectively. Transfer-characteristics and LFN experimental data are explained with the help of model incorporating Thomas-Fermi charge screening and inter-layer resistance coupling.« less

Multiscale modeling and computation of nano-electronic transistors and transmembrane proton channels

NASA Astrophysics Data System (ADS)

Chen, Duan

The miniaturization of nano-scale electronic transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. In biology, proton dynamics and transport across membrane proteins are of paramount importance to the normal function of living cells. Similar physical characteristics are behind the two subjects, and model simulations share common mathematical interests/challenges. In this thesis work, multiscale and multiphysical models are proposed to study the mechanisms of nanotransistors and proton transport in transmembrane at the atomic level. For nano-electronic transistors, we introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential. This framework enables us to put microscopic and macroscopic descriptions on an equal footing at nano-scale. Additionally, this model includes layered structures and random doping effect of nano-transistors. For transmembrane proton channels, we describe proton dynamics quantum mechanically via a density functional approach while implicitly treat numerous solvent molecules as a dielectric continuum. The densities of all other ions in the solvent are assumed to obey the Boltzmann distribution. The impact of protein molecular structure and its charge polarization on the proton transport is considered in atomic details. We formulate a total free energy functional to include kinetic and potential energies of protons, as well as electrostatic energy of all other ions on an equal footing. For both nano-transistors and proton channels systems, the variational principle is employed to derive nonlinear governing equations. The Poisson-Kohn-Sham equations are derived for nano-transistors while the generalized Poisson-Boltzmann equation and Kohn-Sham equation are obtained for proton channels. Related numerical challenges in simulations are addressed: the matched interface and boundary (MIB) method, the Dirichlet-to-Neumann mapping (DNM) technique, and the Krylov subspace and preconditioner theory are introduced to improve the computational efficiency of the Poisson-type equation. The quantum transport theory is employed to solve the Kohn-Sham equation. The Gummel iteration and relaxation technique are utilized for overall self-consistent iterations. Finally, applications are considered and model validations are verified by realistic nano-transistors and transmembrane proteins. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our threedimensional numerical simulations. For these devices, the current uctuation and voltage threshold lowering effect induced by discrete dopants are explored. For proton transport, a realistic channel protein, the Gramicidin A (GA) is used to demonstrate the performance of the proposed proton channel model and validate the efficiency of the proposed mathematical algorithms. The electrostatic characteristics of the GA channel is analyzed with a wide range of model parameters. Proton channel conductances are studied over a number of applied voltages and reference concentrations. Comparisons with experimental data are utilized to verify our model predictions.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

PubMed Central

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

1.55 Micrometer Sub-Micron Finger, Interdigitated MSM Photodetector Arrays with Low Dark Current

DTIC Science & Technology

2010-02-02

pf a- IGZO TFTs. IV. RF Characteristics of Room Temperature Deposited Indium Zinc Oxide Thin - Film Transistors Depletion-mode indium zinc...III. High Performance Indium Gallium Zinc Oxide Thin Film Transistors Fabricated On Polyethylene Terephthalate Substrates High-performance...amorphous (a-) InGaZnO-based thin film transistors (TFTs) were fabricated on flexible polyethylene terephthalate (PET) substrates coated with indium

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

NASA Technical Reports Server (NTRS)

Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

1981-01-01

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NASA Astrophysics Data System (ADS)

Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-09-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

Improvement in interfacial characteristics of low-voltage carbon nanotube thin-film transistors with solution-processed boron nitride thin films

NASA Astrophysics Data System (ADS)

Jeon, Jun-Young; Ha, Tae-Jun

2017-08-01

In this article, we demonstrate the potential of solution-processed boron nitride (BN) thin films for high performance single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) with low-voltage operation. The use of BN thin films between solution-processed high-k dielectric layers improved the interfacial characteristics of metal-insulator-metal devices, thereby reducing the current density by three orders of magnitude. We also investigated the origin of improved device performance in SWCNT-TFTs by employing solution-processed BN thin films as an encapsulation layer. The BN encapsulation layer improves the electrical characteristics of SWCNT-TFTs, which includes the device key metrics of linear field-effect mobility, sub-threshold swing, and threshold voltage as well as the long-term stability against the aging effect in air. Such improvements can be achieved by reduced interaction of interfacial localized states with charge carriers. We believe that this work can open up a promising route to demonstrate the potential of solution-processed BN thin films on nanoelectronics.

Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

NASA Astrophysics Data System (ADS)

Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

2017-03-01

A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Hysteresis mechanism and control in pentacene organic field-effect transistors with polymer dielectric

NASA Astrophysics Data System (ADS)

Huang, Wei; Shi, Wei; Han, Shijiao; Yu, Junsheng

2013-05-01

Hysteresis mechanism of pentacene organic field-effect transistors (OFETs) with polyvinyl alcohol (PVA) and/or polymethyl methacrylate (PMMA) dielectrics is studied. Through analyzing the electrical characteristics of OFETs with various PVA/PMMA arrangements, it shows that charge, which is trapped in PVA bulk and at the interface of pentacene/PVA, is one of the origins of hysteresis. The results also show that memory window is proportional to both trap amount in PVA and charge density at the gate/PVA or PVA/pentacene interfaces. Hence, the controllable memory window of around 0 ˜ 10 V can be realized by controlling the thickness and combination of triple-layer polymer dielectrics.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

High-temperature performance of MoS2 thin-film transistors: Direct current and pulse current-voltage characteristics

NASA Astrophysics Data System (ADS)

Jiang, C.; Rumyantsev, S. L.; Samnakay, R.; Shur, M. S.; Balandin, A. A.

2015-02-01

We report on fabrication of MoS2 thin-film transistors (TFTs) and experimental investigations of their high-temperature current-voltage characteristics. The measurements show that MoS2 devices remain functional to temperatures of at least as high as 500 K. The temperature increase results in decreased threshold voltage and mobility. The comparison of the direct current (DC) and pulse measurements shows that the direct current sub-linear and super-linear output characteristics of MoS2 thin-films devices result from the Joule heating and the interplay of the threshold voltage and mobility temperature dependences. At temperatures above 450 K, a kink in the drain current occurs at zero gate voltage irrespective of the threshold voltage value. This intriguing phenomenon, referred to as a "memory step," was attributed to the slow relaxation processes in thin films similar to those in graphene and electron glasses. The fabricated MoS2 thin-film transistors demonstrated stable operation after two months of aging. The obtained results suggest new applications for MoS2 thin-film transistors in extreme-temperature electronics and sensors.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Effect of the mobility on (I-V) characteristics of the MOSFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Benzaoui, Ouassila, E-mail: o-benzaoui@yahoo.fr; Azizi, Cherifa, E-mail: aziziche@yahoo.fr

2013-12-16

MOSFET Transistor was the subject of many studies and research works (electronics, data-processing, telecommunications...) in order to exploit its interesting and promising characteristics. The aim of this contribution is devoted to the effect of the mobility on the static characteristics I-V of the MOSFET. The study enables us to calculate the drain current as function of bias in both linear and saturated modes; this effect is evaluated using a numerical simulation program. The influence of mobility was studied. Obtained results allow us to determine the mobility law in the MOSFET which gives optimal (I-V) characteristics of the component.

Transport properties of field-effect transistor with Langmuir-Blodgett films of C60 dendrimer and estimation of impurity levels

NASA Astrophysics Data System (ADS)

Kawasaki, Naoko; Nagano, Takayuki; Kubozono, Yoshihiro; Sako, Yuuki; Morimoto, Yu; Takaguchi, Yutaka; Fujiwara, Akihiko; Chu, Chih-Chien; Imae, Toyoko

2007-12-01

Field-effect transistor (FET) device has been fabricated with Langmuir-Blodgett films of C60 dendrimer. The device showed n-channel normally off characteristics with the field-effect mobility of 2.7×10-3cm2V-1s-1 at 300K, whose value is twice as high as that (1.4×10-3cm2V-1s-1) for the FET with spin-coated films of C60 dendrimer. This originates from the formation of ordered π-conduction network of C60 moieties. From the temperature dependence of field-effect mobility, a structural phase transition has been observed at around 300K. Furthermore, the density of states for impurity levels was estimated in the Langmuir-Blodgett films.

Transistor Effect in Improperly Connected Transistors.

ERIC Educational Resources Information Center

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Ion-selective electrolyte-gated field-effect transistors: prerequisites for proper functioning

NASA Astrophysics Data System (ADS)

Kofler, Johannes; Schmoltner, Kerstin; List-Kratochvil, Emil J. W.

2014-10-01

Electrolyte-gated organic field-effect transistors (EGOFETs) used as transducers and amplifiers in potentiometric sensors have recently attracted a significant amount of scientific interest. For that reason, the fundamental prerequisites to achieve a proper potentiometric signal amplification and transduction are examined. First, polarizable as well as non-polarizable semiconductor- and gate-electrolyte- interface combinations are investigated by normal pulse voltammetry. The results of these measurements are correlated with the corresponding transistor characteristics, clarifying the functional principle of EGOFETs and the requirements for high signal amplification. In addition to a good electrical performance, the EGOFET-transducers should also be compatible with the targeted sensing application. Accordingly, the influence of different gate materials and electrolytes on the sensing abilities, are discussed. Even though all physical requirements are met, EGOFETs typically exhibit irreversible degradation, if the gate potential exceeds a certain level. For that reason, EGOFETs have to be operated using a constant source-drain operation mode which is presented by means of an H+ (pH) sensitive ion-sensor.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

effect of the parameters of AlN/GaN/AlGaN and AlN/GaN/InAlN heterostructures with a two-dimensional electron gas on their electrical properties and the characteristics of transistors on their basis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsatsulnikov, A. F., E-mail: andrew@beam.ioffe.ru; Lundin, V. W.; Zavarin, E. E.

The effect of the layer thickness and composition in AlGaN/AlN/GaN and InAlN/AlN/GaN transistor heterostructures with a two-dimensional electron gas on their electrical and the static parameters of test transistors fabricated from such heterostructures are experimentally and theoretically studied. It is shown that the use of an InAlN barrier layer instead of AlGaN results in a more than twofold increase in the carrier concentration in the channel, which leads to a corresponding increase in the saturation current. In situ dielectric-coating deposition on the InAlN/AlN/GaN heterostructure surface during growth process allows an increase in the maximum saturation current and breakdown voltages whilemore » retaining high transconductance.« less

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study of vertical type organic light emitting transistor using ZnO

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2006-04-01

We propose a new type organic light emitting transistor (OLET) combining static induction transistor (SIT) with double hetero junction type organic light emitting diodes (OLED) using n-type zinc oxide (ZnO) films which works as a transparent and electron injection layer. The device characteristics of newly developed OLED and ZnO-SIT showed relatively high luminance of about 500 cd/m2 at 7.6 mA/cm2 and is able to control by gate voltage as low as a few volts, respectively. The crystal structures of the ZnO films as a function of Ar/O II flow ratio and the basic characteristics of the thin film transistor (TFT) and SIT depending on the ZnO sputtering conditions are investigated. The results obtained here show that the OLET using ZnO film is a suitable element for flexible sheet displays.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends.

PubMed

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-08-02

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends

PubMed Central

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-01-01

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed. PMID:28773772

Trap density of states in n-channel organic transistors: variable temperature characteristics and band transport

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Joung-min, E-mail: cho.j.ad@m.titech.ac.jp; Akiyama, Yuto; Kakinuma, Tomoyuki

2013-10-15

We have investigated trap density of states (trap DOS) in n-channel organic field-effect transistors based on N,N ’-bis(cyclohexyl)naphthalene diimide (Cy-NDI) and dimethyldicyanoquinonediimine (DMDCNQI). A new method is proposed to extract trap DOS from the Arrhenius plot of the temperature-dependent transconductance. Double exponential trap DOS are observed, in which Cy-NDI has considerable deep states, by contrast, DMDCNQI has substantial tail states. In addition, numerical simulation of the transistor characteristics has been conducted by assuming an exponential trap distribution and the interface approximation. Temperature dependence of transfer characteristics are well reproduced only using several parameters, and the trap DOS obtained from the simulatedmore » characteristics are in good agreement with the assumed trap DOS, indicating that our analysis is self-consistent. Although the experimentally obtained Meyer-Neldel temperature is related to the trap distribution width, the simulation satisfies the Meyer-Neldel rule only very phenomenologically. The simulation also reveals that the subthreshold swing is not always a good indicator of the total trap amount, because it also largely depends on the trap distribution width. Finally, band transport is explored from the simulation having a small number of traps. A crossing point of the transfer curves and negative activation energy above a certain gate voltage are observed in the simulated characteristics, where the critical V{sub G} above which band transport is realized is determined by the sum of the trapped and free charge states below the conduction band edge.« less

Field Effect Transistors Based on Composite Films of Poly(4-vinylphenol) with ZnO Nanoparticles

NASA Astrophysics Data System (ADS)

Boughias, Ouiza; Belkaid, Mohammed Said; Zirmi, Rachid; Trigaud, Thierry; Ratier, Bernard; Ayoub, Nouh

2018-04-01

In order to adjust the characteristic of pentacene thin film transistor, we modified the dielectric properties of the gate insulator, poly(4-vinylphenol), or PVP. PVP is an organic polymer with a low dielectric constant, limiting the performance of organic thin film transistors (OTFTs). To increase the dielectric constant of PVP, a controlled amount of ZnO nanoparticles was homogeneously dispersed in a dielectric layer. The effect of the concentration of ZnO on the relative permittivity of PVP was measured using impedance spectroscopy and it has been demonstrated that the permittivity increases from 3.6 to 5.5 with no percolation phenomenon even at a concentration of 50 vol.%. The performance of OTFTs in terms of charge carrier mobility, threshold voltage and linkage current was evaluated. The results indicate a dramatic increase in both the field effect mobility and the linkage current by a factor of 10. It has been demonstrated that the threshold voltage can be adjusted. It shifts from 8 to 0 when the volume concentration of ZnO varied from 0 vol.% to 50 vol.%.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

NASA Astrophysics Data System (ADS)

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min-1), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 105, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm2 V-1 s-1. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing.

PubMed

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-13

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min(-1)), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10(5), a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm(2) V(-1) s(-1). The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Determination of trap distributions from current characteristics of pentacene field-effect transistors with surface modified gate oxide

NASA Astrophysics Data System (ADS)

Scheinert, Susanne; Pernstich, Kurt P.; Batlogg, Bertram; Paasch, Gernot

2007-11-01

It has been demonstrated [K. P. Pernstich, S. Haas, D. Oberhoff, C. Goldmann, D. J. Gundlach, B. Batlogg, A. N. Rashid, and G. Schitter, J. Appl. Phys. 96, 6431 (2004)] that a controllable shift of the threshold voltage in pentacene thin film transistors is caused by the use of organosilanes with different functional groups forming a self-assembled monolayer (SAM) on the gate oxide. The observed broadening of the subthreshold region indicates that the SAM creates additional trap states. Indeed, it is well known that traps strongly influence the behavior of organic field-effect transistors (OFETs). Therefore, the so-called "amorphous silicon (a-Si) model" has been suggested to be an appropriate model to describe OFETs. The main specifics of this model are transport of carriers above a mobility edge obeying Boltzmann statistics and exponentially distributed tail states and deep trap states. Here, approximate trap distributions are determined by adjusting two-dimensional numerical simulations to the experimental data. It follows from a systematic variation of parameters describing the trap distributions that the existence of both donorlike and acceptorlike trap distributions near the valence band, respectively, and a fixed negative interface charge have to be assumed. For two typical devices with different organosilanes the electrical characteristics can be described well with a donorlike bulk trap distribution, an acceptorlike interface distribution, and/or a fixed negative interface charge. As expected, the density of the fixed or trapped interface charge depends strongly on the surface treatment of the dielectric. There are some limitations in determining the trap distributions caused by either slow time-dependent processes resulting in differences between transfer and output characteristics, or in the uncertainty of the effective mobility.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer

NASA Astrophysics Data System (ADS)

Jiménez Tejada, Juan A.; Lopez-Varo, Pilar; Chaure, Nandu B.; Chambrier, Isabelle; Cammidge, Andrew N.; Cook, Michael J.; Jafari-Fini, Ali; Ray, Asim K.

2018-03-01

70 nm thick solution-processed films of a palladium phthalocyanine (PdPc6) derivative bearing eight hexyl (-C6H13) chains at non-peripheral positions have been employed as active layers in the fabrication of bottom-gate bottom-contact organic thin film transistors (OTFTs) deposited on highly doped p-type Si (110) substrates with SiO2 gate dielectric. The dependence of the transistor electrical performance upon the mesophase behavior of the PdPc6 films has been investigated by measuring the output and transfer characteristics of the OTFT having its active layer ex situ vacuum annealed at temperatures between 500 °C and 200 °C. A clear correlation between the annealing temperature and the threshold voltage and carrier mobility of the transistors, and the transition temperatures extracted from the differential scanning calorimetric curves for bulk materials has been established. This direct relation has been obtained by means of a compact electrical model in which the contact effects are taken into account. The precise determination of the contact-voltage drain-current curves allows for obtaining such a relation.

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

PubMed

Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

2018-05-09

The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

NASA Astrophysics Data System (ADS)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

The physical analysis on electrical junction of junctionless FET

NASA Astrophysics Data System (ADS)

Chen, Lun-Chun; Yeh, Mu-Shih; Lin, Yu-Ru; Lin, Ko-Wei; Wu, Min-Hsin; Thirunavukkarasu, Vasanthan; Wu, Yung-Chun

2017-02-01

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization.

Organic Light-Emitting Diode-on-Silicon Pixel Circuit Using the Source Follower Structure with Active Load for Microdisplays

NASA Astrophysics Data System (ADS)

Kwak, Bong-Choon; Lim, Han-Sin; Kwon, Oh-Kyong

2011-03-01

In this paper, we propose a pixel circuit immune to the electrical characteristic variation of organic light-emitting diodes (OLEDs) for organic light-emitting diode-on-silicon (OLEDoS) microdisplays with a 0.4 inch video graphics array (VGA) resolution and a 6-bit gray scale. The proposed pixel circuit is implemented using five p-channel metal oxide semiconductor field-effect transistors (MOSFETs) and one storage capacitor. The proposed pixel circuit has a source follower with a diode-connected transistor as an active load for improving the immunity against the electrical characteristic variation of OLEDs. The deviation in the measured emission current ranges from -0.165 to 0.212 least significant bit (LSB) among 11 samples while the anode voltage of OLED is 0 V. Also, the deviation in the measured emission current ranges from -0.262 to 0.272 LSB in pixel samples, while the anode voltage of OLED varies from 0 to 2.5 V owing to the electrical characteristic variation of OLEDs.

Enhanced photoresponse characteristics of transistors using CVD-grown MoS2/WS2 heterostructures

NASA Astrophysics Data System (ADS)

Shan, Junjie; Li, Jinhua; Chu, Xueying; Xu, Mingze; Jin, Fangjun; Fang, Xuan; Wei, Zhipeng; Wang, Xiaohua

2018-06-01

Semiconductor heterostructures based on transition metal dichalcogenides provide a broad platform to research two-dimensional nanomaterials and design atomically thin devices for fundamental and applied interests. The MoS2/WS2 heterostructure was prepared on SiO2/Si substrate by chemical vapor deposition (CVD) in our research. And the optical properties of the heterostructure was characterized by Raman and photoluminescence (PL) spectroscopy. The similar 2 orders of magnitude decrease of PL intensity in MoS2/WS2 heterostructures was tested, which is attribute to the electrical and optical modulation effects are connected with the interfacial charge transfer between MoS2 and WS2 films. Using MoS2/WS2 heterostructure as channel material of the phototransistor, we demonstrated over 50 folds enhanced photoresponsivity of multilayer MoS2 field-effect transistor. The results indicate that the MoS2/WS2 films can be a promising heterostructure material to enhance the photoresponse characteristics of MoS2-based phototransistors.

Characterization of high-dose and high-energy implanted gate and source diode and analysis of lateral spreading of p gate profile in high voltage SiC static induction transistors

NASA Astrophysics Data System (ADS)

Onose, Hidekatsu; Kobayashi, Yutaka; Onuki, Jin

2017-03-01

The effect of the p gate dose on the characteristics of the gate-source diode in SiC static induction transistors (SIT) was investigated. It was found that a dose of 1.5 × 1014 cm-2 yields a pn junction breakdown voltage higher than 60 V and good forward characteristics. A normally on SiC SIT was fabricated and demonstrated. A blocking voltage higher than 2.0 kV at a gate-source voltage of -50 V and on-resistance of 70 mΩ cm2 were obtained. Device simulations were performed to investigate the effect of the lateral spreading. By comparing the measured I-V curves with simulation results, the lateral spreading factor was estimated to be about 0.5. The lateral spreading detrimentally affected the electrical properties of the SIT made using implantations at energies higher than 1 MeV.

Negative differential resistance in BN co-doped coaxial carbon nanotube field effect transistor

NASA Astrophysics Data System (ADS)

Shah, Khurshed A.; Parvaiz, M. Shunaid

2016-12-01

The CNTFETs are the most promising advanced alternatives to the conventional FETs due to their outstanding structure and electrical properties. In this paper, we report the I-V characteristics of zig-zag (4, 0) semiconducting coaxial carbon nanotube field effect transistor (CNTFET) using the non-equilibrium Green's function formalism. The CNTFET is co-doped with two, four and six boron-nitrogen (BN) atoms separately near the electrodes using the substitutional doping method and the I-V characteristics were calculated for each model using Atomistic Tool Kit software (version 13.8.1) and its virtual interface. The results reveal that all models show negative differential resistance (NDR) behavior with the maximum peak to valley current ratio (PVCR) of 3.2 at 300 K for the four atom doped model. The NDR behavior is due to the band to band tunneling (BTBT) in semiconducting CNTFET and decreases as the doping in the channel increases. The results are beneficial for next generation designing of nano devices and their potential applications in electronic industry.

Surface Modulation of Graphene Field Effect Transistors on Periodic Trench Structure.

PubMed

Jin, Jun Eon; Choi, Jun Hee; Yun, Hoyeol; Jang, Ho-Kyun; Lee, Byung Chul; Choi, Ajeong; Joo, Min-Kyu; Dettlaff-Weglikowska, Urszula; Roth, Siegmar; Lee, Sang Wook; Lee, Jae Woo; Kim, Gyu Tae

2016-07-20

In this work, graphene field effect transistors (FETs) were fabricated on a trench structure made by carbonized poly(methylmethacrylate) to modify the graphene surface. The trench-structured devices showed different characteristics depending on the channel orientation and the pitch size of the trenches as well as channel area in the FETs. Periodic corrugations and barriers of suspended graphene on the trench structure were measured by atomic force microscopy and electrostatic force microscopy. Regular barriers of 160 mV were observed for the trench structure with graphene. To confirm the transfer mechanism in the FETs depending on the channel orientation, the ratio of experimental mobility (3.6-3.74) was extracted from the current-voltage characteristics using equivalent circuit simulation. It is shown that the number of barriers increases as the pitch size decreases because the number of corrugations increases from different trench pitches. The noise for the 140 nm pitch trench is 1 order of magnitude higher than that for the 200 nm pitch trench.

Organic transistors for electrophysiology (Presentation Recording)

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan

2015-10-01

Efficient local transduction of biological signals is of critical importance for mapping brain activity and diagnosing pathological conditions. Traditional devices used to record electrophysiological signals are passive electrodes that require (pre)amplification with downstream electronics. Organic electrochemical transistors (OECTs) that utilize conducting polymer films as the channel have shown considerable promise as amplifying transducers due to their stability in aqueous conditions and high transconductance (>3 mS). The materials properties and physics of such transistors, however, remains largely unexplored thus limiting their potential. Here we show that the uptake of ionic charge from an electrolyte into a poly(3,4-ethylenedioxythiophene) doped with polystyrene sulfonate (PEDOT:PSS) OECT channel leads to a dependence of the effective capacitance on the entire volume of the film. Subsequently, device transconductance and time response vary with channel thickness, a defining characteristic that differentiates OECTs from field effect transistors, and provides a new degree of freedom for device engineering. Using this understanding we tailor OECTs for a variety of low (1-100 Hz) and high (1-10 kHz) frequency applications, including human electroencephalography, where high transconductance devices impart richer signal content without the need for additional amplification circuitry. We also show that the materials figure of merit OECTs is the product of hole mobility and volumetric capacitance of the channel, leading to design rules for novel high performance materials.

Extended behavioural modelling of FET and lattice-mismatched HEMT devices

NASA Astrophysics Data System (ADS)

Khawam, Yahya; Albasha, Lutfi

2017-07-01

This study presents an improved large signal model that can be used for high electron mobility transistors (HEMTs) and field effect transistors using measurement-based behavioural modelling techniques. The steps for accurate large and small signal modelling for transistor are also discussed. The proposed DC model is based on the Fager model since it compensates between the number of model's parameters and accuracy. The objective is to increase the accuracy of the drain-source current model with respect to any change in gate or drain voltages. Also, the objective is to extend the improved DC model to account for soft breakdown and kink effect found in some variants of HEMT devices. A hybrid Newton's-Genetic algorithm is used in order to determine the unknown parameters in the developed model. In addition to accurate modelling of a transistor's DC characteristics, the complete large signal model is modelled using multi-bias s-parameter measurements. The way that the complete model is performed is by using a hybrid multi-objective optimisation technique (Non-dominated Sorting Genetic Algorithm II) and local minimum search (multivariable Newton's method) for parasitic elements extraction. Finally, the results of DC modelling and multi-bias s-parameters modelling are presented, and three-device modelling recommendations are discussed.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

Defect healing at room temperature in pentacene thin films and improved transistor performance

NASA Astrophysics Data System (ADS)

Kalb, Wolfgang L.; Meier, Fabian; Mattenberger, Kurt; Batlogg, Bertram

2007-11-01

We report on a healing of defects at room temperature in the organic semiconductor pentacene. This peculiar effect is a direct consequence of the weak intermolecular interaction which is characteristic of organic semiconductors. Pentacene thin-film transistors were fabricated and characterized by in situ gated four-terminal measurements. Under high vacuum conditions (base pressure of order 10-8mbar ), the device performance is found to improve with time. The effective field-effect mobility increases by as much as a factor of 2 and mobilities up to 0.45cm2/Vs were achieved. In addition, the contact resistance decreases by more than an order of magnitude and there is a significant reduction in current hysteresis. Oxygen and nitrogen exposure as well as annealing experiments show the improvement of the electronic parameters to be driven by a thermally promoted process and not by chemical doping. In order to extract the spectral density of trap states from the transistor characteristics, we have implemented a powerful scheme which allows for a calculation of the trap densities with high accuracy in a straightforward fashion. We show the performance improvement to be due to a reduction in the density of shallow traps ⩽0.15eV from the valence band edge, while the energetically deeper traps are essentially unaffected. This work contributes to an understanding of the shallow traps in organic semiconductors and identifies structural point defects within the grains of the polycrystalline thin films as a major cause.

Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2018-06-01

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

Silicon-compatible high-hole-mobility transistor with an undoped germanium channel for low-power application

NASA Astrophysics Data System (ADS)

Cho, Seongjae; Man Kang, In; Rok Kim, Kyung; Park, Byung-Gook; Harris, James S.

2013-11-01

In this work, Ge-based high-hole-mobility transistor with Si compatibility is designed, and its performance is evaluated. A 2-dimensional hole gas is effectively constructed by a AlGaAs/Ge/Si heterojunction with a sufficiently large valence band offset. Moreover, an intrinsic Ge channel is exploited so that high hole mobility is preserved without dopant scattering. Effects of design parameters such as gate length, Ge channel thickness, and aluminum fraction in the barrier material on device characteristics are thoroughly investigated through device simulations. A high on-current above 30 μA/μm along with a low subthreshold swing was obtained from an optimized planar device for low-power applications.

Triggering the Electrolyte-Gated Organic Field-Effect Transistor output characteristics through gate functionalization using diazonium chemistry: Application to biodetection of 2,4-dichlorophenoxyacetic acid.

PubMed

Nguyen, T T K; Nguyen, T N; Anquetin, G; Reisberg, S; Noël, V; Mattana, G; Touzeau, J; Barbault, F; Pham, M C; Piro, B

2018-08-15

We investigated an Electrolyte-Gated Organic Field-Effect transistor based on poly(N-alkyldiketopyrrolo-pyrrole dithienylthieno[3,2-b]thiophene) as organic semiconductor whose gate electrode was functionalized by electrografting a functional diazonium salt capable to bind an antibody specific to 2,4-dichlorophenoxyacetic acid (2,4-D), an herbicide well-known to be a soil and water pollutant. Molecular docking computations were performed to design the functional diazonium salt to rationalize the antibody capture on the gate surface. Sensing of 2,4-D was performed through a displacement immunoassay. The limit of detection was estimated at around 2.5 fM. Copyright © 2018 Elsevier B.V. All rights reserved.

A new method to determine the 2DEG density distribution for passivated AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Fu, Chen; Lin, Zhaojun; Cui, Peng; Lv, Yuanjie; Zhou, Yang; Dai, Gang; Luan, Chongbiao; Liu, Huan; Cheng, Aijie

2018-01-01

A new method to determine the two-dimensional electron gas (2DEG) density distribution of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) after the Si3N4 passivation process has been presented. Detailed device characteristics were investigated and better transport properties have been observed for the passivated devices. The strain variation and the influence of the surface trapping states were analyzed. By using the polarization Coulomb field (PCF) scattering theory, the 2DEG density after passivation was both quantitively and qualitatively determined, which has been increased by 45% under the access regions and decreased by 2% under the gate region.

Effects of addition of Ta and Y ions to InZnO thin film transistors by sol-gel process.

PubMed

Son, Dae-Ho; Kim, Dae-Hwan; Kim, Jung-Hye; Park, Si-Nae; Sung, Shi-Joon; Kang, Jin-Kyu

2013-06-01

We have investigated the effects of the addition of tantalum (Ta) and yttrium (Y) ions to InZnO thin film transistors (TFTs) using the sol-gel process. TaInZnO and YInZnO TFTs had significantly lower off current and higher on-to-off current ratio than InZnO TFTs. Ta and Y ions have strong affinity to oxygen and so suppress the formation of free electron carriers in thin films; they play an important role in enhancing the electrical characteristic due to their high oxygen bonding ability. The optimized TaInZnO and YInZnO TFTs showed high on/off ratio and low subthreshold swing.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

NASA Astrophysics Data System (ADS)

Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

2008-11-01

Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

PubMed

Yan, Xiao; Liu, Chunsen; Li, Chao; Bao, Wenzhong; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2017-09-01

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe 2 /WSe 2 van der Waals heterostructures with SnSe 2 as the p-layer and WSe 2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10 4 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec -1 for exceeding two decades of drain current with a minimum of 37 mV dec -1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I ON /I OFF ratio of the transfer characteristics is >10 6 , accompanying a high ON current >10 -5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Device considerations for development of conductance-based biosensors

PubMed Central

Lee, Kangho; Nair, Pradeep R.; Scott, Adina; Alam, Muhammad A.; Janes, David B.

2009-01-01

Design and fabrication of electronic biosensors based on field-effect-transistor (FET) devices require understanding of interactions between semiconductor surfaces and organic biomolecules. From this perspective, we review practical considerations for electronic biosensors with emphasis on molecular passivation effects on FET device characteristics upon immobilization of organic molecules and an electrostatic model for FET-based biosensors. PMID:24753627

Study on copper phthalocyanine and perylene-based ambipolar organic light-emitting field-effect transistors produced using neutral beam deposition method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dae-Kyu; Oh, Jeong-Do; Shin, Eun-Sol

2014-04-28

The neutral cluster beam deposition (NCBD) method has been applied to the production and characterization of ambipolar, heterojunction-based organic light-emitting field-effect transistors (OLEFETs) with a top-contact, multi-digitated, long-channel geometry. Organic thin films of n-type N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide and p-type copper phthalocyanine were successively deposited on the hydroxyl-free polymethyl-methacrylate (PMMA)-coated SiO{sub 2} dielectrics using the NCBD method. Characterization of the morphological and structural properties of the organic active layers was performed using atomic force microscopy and X-ray diffraction. Various device parameters such as hole- and electron-carrier mobilities, threshold voltages, and electroluminescence (EL) were derived from the fits of the observed current-voltage andmore » current-voltage-light emission characteristics of OLEFETs. The OLEFETs demonstrated good field-effect characteristics, well-balanced ambipolarity, and substantial EL under ambient conditions. The device performance, which is strongly correlated with the surface morphology and the structural properties of the organic active layers, is discussed along with the operating conduction mechanism.« less

A study of effects of electrode contacts on performance of organic-based light-emitting field-effect transistors

NASA Astrophysics Data System (ADS)

Kim, Dae-Kyu; Choi, Jong-Ho

2018-02-01

Herein is presented a comparative performance analysis of heterojunction organic-based light-emitting field-effect transistors (OLEFETs) with symmetric (Au only) and asymmetric (Au and LiF/Al) electrode contacts. The devices had a top source-drain contact with long-channel geometry and were produced by sequentially depositing p-type pentacene and n-type N,N‧-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) using a neutral cluster beam deposition apparatus. The spectroscopic, structural and morphological properties of the organic thin films were examined using photoluminescence (PL) spectroscopy, X-ray diffraction (XRD) method, laser scanning confocal and atomic force microscopy (LSCM, AFM). Based upon the growth of high-quality, well-packed crystalline thin films, the devices demonstrated ambipolar field-effect characteristics, stress-free operational stability, and light emission under ambient conditions. Various device parameters were derived from the fits of the observed characteristics. The hole mobilities were nearly equal irrespective of the electrode contacts, whereas the electron mobilities of the transistors with LiF/Al drain electrodes were higher due to the low injection barrier. For the OLEFETs with symmetric electrodes, electroluminescence (EL) occurred only in the vicinity of the hole-injecting electrode, whereas for the OLEFETs with asymmetric electrodes, the emission occurred in the vicinity of both hole- and electron-injecting electrodes. By tuning the carrier injection and transport through high- and low-work function metals, the hole-electron recombination sites could be controlled. The operating conduction and light emission mechanism are discussed with the aid of EL images obtained using a charge-coupled device (CCD) camera.

Development of improved pyroelectric detectors. Measurements of pyroelectric material characteristics and FET characteristics

NASA Technical Reports Server (NTRS)

Weiner, S.; Beerman, H. P.; Schwarz, F. C.

1990-01-01

Research was undertaken to improve the detectivity of the pyroelectric detector with the ultimate goal of operation at or near the temperature-noise limit. Two general areas of investigation were undertaken: (1) to improve responsivity through the use of new materials; and (2) to reduce noise through improved field effect transistor characteristics, and improved electroding of the pyroelectric material. FET's are being obtained from various manufacturers, evaulated, and selected units tested for evaluation of characteristics critical to their use as preamplifiers with pyroelectric detectors.

Heterojunction bipolar transistor technology for data acquisition and communication

NASA Technical Reports Server (NTRS)

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Linear-log counting-rate meter uses transconductance characteristics of a silicon planar transistor

NASA Technical Reports Server (NTRS)

Eichholz, J. J.

1969-01-01

Counting rate meter compresses a wide range of data values, or decades of current. Silicon planar transistor, operating in the zero collector-base voltage mode, is used as a feedback element in an operational amplifier to obtain the log response.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

PubMed

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

Simulation Model of A Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry W. (Technical Monitor)

2002-01-01

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

Oxide Semiconductor-Based Flexible Organic/Inorganic Hybrid Thin-Film Transistors Fabricated on Polydimethylsiloxane Elastomer.

PubMed

Jung, Soon-Won; Choi, Jeong-Seon; Park, Jung Ho; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lim, Sang Chul; Lee, Sang Seok; Chu, Hye Yong

2016-03-01

We demonstrate flexible organic/inorganic hybrid thin-film transistors (TFTs) on a polydimethysilox- ane (PDMS) elastomer substrate. The active channel and gate insulator of the hybrid TFT are composed of In-Ga-Zn-O (IGZO) and blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF- TrFE)] with poly(methyl methacrylate) (PMMA), respectively. It has been confirmed that the fabri- cated TFT display excellent characteristics: the recorded field-effect mobility, sub-threshold voltage swing, and I(on)/I(off) ratio were approximately 0.35 cm2 V(-1) s(-1), 1.5 V/decade, and 10(4), respectively. These characteristics did not experience any degradation at a bending radius of 15 mm. These results correspond to the first demonstration of a hybrid-type TFT using an organic gate insulator/oxide semiconducting active channel structure fabricated on PDMS elastomer, and demonstrate the feasibility of a promising device in a flexible electronic system.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Light induced instabilities in amorphous indium-gallium-zinc-oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Chowdhury, Md Delwar Hossain; Migliorato, Piero; Jang, Jin

2010-10-01

The effect of exposure to ultraviolet radiation on the characteristics of amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) fabricated by sputtering is investigated. After illumination with 1.5 mW cm-2 of 365 nm radiation, in the absence of any bias stress, a persistent negative shift in the characteristics is observed in the dark. The magnitude of the shift increases with exposure time, saturating after about 10 min. Under these conditions the subthreshold exhibits a rigid shift of around 3.6 V and 7.5 V for TFTs with an active layer thickness of 20 nm and 50 nm, respectively. The shift in the dark increases (decreases) when a negative (positive) bias stress is applied under illumination. The instability behavior caused by exposure to light, in the absence of any bias stress, can be explained on the basis of ionization of neutral oxygen vacancies.

Charge transport and velocity distribution in ambipolar organic thin film Transistors based on a diketopyrrolopyrrole-benzothiadiazole copolymer

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun; Sonar, Prashant; Singh, Samarendra Pratap; Dodabalapur, Ananth

2011-03-01

There have been reports of charge transport mechanisms in organic thin film transistors (OTFTs) focusing on steady-state characteristics but these measurements provide limited information. Time-resolved measurements can provide additional information in understanding transport mechanisms but existing reports have focused on unipolar organic characteristics. No previous reports on ambipolar organic devices have involved entire velocity distribution and charge transport mechanisms. Recently, we have fabricated ambipolar OTFTs based on a diketopyrrolopyrrole-benzothiadiazole copolymer (PDPP-TBT) with a field-effect mobility of more than 0.2 cm2 V- 1 s - 1 . Velocity distributions are measured by performing specialized dynamic measurements while keeping the RC-time constant of the measurement circuit small. This yields a distribution in arrival times of charge carriers from source to drain which can be converted to velocity distributions. We will also describe dynamic transport measurements on high-k-dielectric PDPP-TBT OTFTs.

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Non-linear effects and thermoelectric efficiency of quantum dot-based single-electron transistors.

PubMed

Talbo, Vincent; Saint-Martin, Jérôme; Retailleau, Sylvie; Dollfus, Philippe

2017-11-01

By means of advanced numerical simulation, the thermoelectric properties of a Si-quantum dot-based single-electron transistor operating in sequential tunneling regime are investigated in terms of figure of merit, efficiency and power. By taking into account the phonon-induced collisional broadening of energy levels in the quantum dot, both heat and electrical currents are computed in a voltage range beyond the linear response. Using our homemade code consisting in a 3D Poisson-Schrödinger solver and the resolution of the Master equation, the Seebeck coefficient at low bias voltage appears to be material independent and nearly independent on the level broadening, which makes this device promising for metrology applications as a nanoscale standard of Seebeck coefficient. Besides, at higher voltage bias, the non-linear characteristics of the heat current are shown to be related to the multi-level effects. Finally, when considering only the electronic contribution to the thermal conductance, the single-electron transistor operating in generator regime is shown to exhibit very good efficiency at maximum power.

Trap-state-dominated suppression of electron conduction in carbon nanotube thin-film transistors.

PubMed

Qian, Qingkai; Li, Guanhong; Jin, Yuanhao; Liu, Junku; Zou, Yuan; Jiang, Kaili; Fan, Shoushan; Li, Qunqing

2014-09-23

The often observed p-type conduction of single carbon nanotube field-effect transistors is usually attributed to the Schottky barriers at the metal contacts induced by the work function differences or by the doping effect of the oxygen adsorption when carbon nanotubes are exposed to air, which cause the asymmetry between electron and hole injections. However, for carbon nanotube thin-film transistors, our contrast experiments between oxygen doping and electrostatic doping demonstrate that the doping-generated transport barriers do not introduce any observable suppression of electron conduction, which is further evidenced by the perfect linear behavior of transfer characteristics with the channel length scaling. On the basis of the above observation, we conclude that the environmental adsorbates work by more than simply shifting the Fermi level of the CNTs; more importantly, these adsorbates cause a poor gate modulation efficiency of electron conduction due to the relatively large trap state density near the conduction band edge of the carbon nanotubes, for which we further propose quantitatively that the adsorbed oxygen-water redox couple is responsible.

A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Sedki, Amor; André, Nicolas; Kilchytska, Valéria; Gérard, Pierre; Ali, Zeeshan; Udrea, Florin; Flandre, Denis

2018-01-01

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

Investigation of InP/In0.65Ga0.35As metamorphic p-channel doped-channel field-effect transistor

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui

2016-07-01

In this article, the device mechanism and characteristics of InP/InGaAs metamorphic p-channel field-effect transistor (FET), which has a high indium mole fraction of InGaAs channel, grown on the GaAs substrate is demonstrated. The device was fabricated on the top of the InxGa1-xP graded metamorphic buffer layer, and the In0.65Ga0.35As pseudomorphic channel was employed to elevate the transistor performance. For the p-type FET, due to the considerably large valence band discontinuity at InP/In0.65Ga0.35As heterojunction and a relatively thin as well as heavily doped pseudomorphic In0.65Ga0.35As channel between two undoped InP layers, a maximum extrinsic transconductance of 27.3 mS/mm and a maximum saturation current density of -54.3 mA/mm are obtained. Consequently, the studied metamorphic FET is suitable for the development in signal amplification, integrated circuits, and low supply-voltage complementary logic inverters.

Enhancement of field effect mobility of poly(3-hexylthiophene) thin film transistors by soft-lithographical nanopatterning on the gate-dielectric surface

NASA Astrophysics Data System (ADS)

Park, Jeong-Ho; Kang, Seok-Ju; Park, Jeong-Woo; Lim, Bogyu; Kim, Dong-Yu

2007-11-01

The submicroscaled octadecyltrichlorosilane (OTS) line patterns on gate-dielectric surfaces were introduced into the fabrication of organic field effect transistors (OFETs). These spin-cast regioregular poly(3-hexylthiophene) films on soft-lithographically patterned SiO2 surfaces yielded a higher hole mobility (˜0.072cm2/Vs ) than those of unpatterned (˜0.015cm2/Vs) and untreated (˜5×10-3cm2/Vs) OFETs. The effect of mobility enhancement as a function of the patterned line pitch was investigated in structural and geometric characteristics. The resulting improved mobility is likely attributed to the formation of efficient π-π stacking as a result of guide-assisted, local self-organization-involved molecular interactions between the poly(3-hexylthiophene) polymer and the geometrical OTS patterns.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Ensemble Monte Carlo particle investigation of hot electron induced source-drain burnout characteristics of GaAs field-effect transistors

NASA Astrophysics Data System (ADS)

Moglestue, C.; Buot, F. A.; Anderson, W. T.

1995-08-01

The lattice heating rate has been calculated for GaAs field-effect transistors of different source-drain channel design by means of the ensemble Monte Carlo particle model. Transport of carriers in the substrate and the presence of free surface charges are also included in our simulation. The actual heat generation was obtained by accounting for the energy exchanged with the lattice of the semiconductor during phonon scattering. It was found that the maximum heating rate takes place below the surface near the drain end of the gate. The results correlate well with a previous hydrodynamic energy transport estimate of the electronic energy density, but shifted slightly more towards the drain. These results further emphasize the adverse effects of hot electrons on the Ohmic contacts.

Gallium Arsenide Pilot Line for High Performance Components

DTIC Science & Technology

1992-05-28

two transistors’ characteristics were a close enough match to use as pull -up, high resistance loads in the cell. FET Data Unfortunately, data obtained...length transistors in 4K SRAM II, we can predict the performance of the memory chip. Since there is essentially no active pull up capability in the c a...Second, the 2/2 Am DFET’s threshold and "ON" current could be adjusted. Or third, a different size DFET pull -up transistor could be used which more

Programmable, automated transistor test system

NASA Technical Reports Server (NTRS)

Truong, L. V.; Sundburg, G. R.

1986-01-01

A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.

Structured-gate organic field-effect transistors

NASA Astrophysics Data System (ADS)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Ultrashort channel silicon nanowire transistors with nickel silicide source/drain contacts.

PubMed

Tang, Wei; Dayeh, Shadi A; Picraux, S Tom; Huang, Jian Yu; Tu, King-Ning

2012-08-08

We demonstrate the shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) by a controlled reaction with Ni leads on an in situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 °C. NiSi(2) is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of 17 nm to 3.6 μm. Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs, and that limits transport parameter extraction from SB-FETs using conventional field-effect transconductance measurements.

Ferroelectric-induced carrier modulation for ambipolar transition metal dichalcogenide transistors

NASA Astrophysics Data System (ADS)

Yin, Lei; Wang, Zhenxing; Wang, Feng; Xu, Kai; Cheng, Ruiqing; Wen, Yao; Li, Jie; He, Jun

2017-03-01

For multifarious electronic and optoelectronic applications, it is indispensable exploration of stable and simple method to modulate electrical behavior of transition metal dichalcogenides (TMDs). In this study, an effective method to adjust the electrical properties of ambipolar TMDs is developed by introducing the dipole electric field from poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric polymer. The transition from ambipolar to p-type conductive characteristics is realized, and the transistor performances are also significantly enhanced. Hole density of MoTe2- and WSe2-based back-gate field effect transistors increases by 4.4 and 2.5 times. Moreover, the corresponding hole mobilities are strikingly improved from 0.27 to 10.7 cm2 V-1 s-1 and from 1.6 to 59.8 cm2 V-1 s-1, respectively. After optimizing, p-channel MoTe2 phototransistors present ultrahigh responsivity of 3521 A/W, which is superior to most layered phototransistors. The remarkable control of conductive type, carrier concentration, and field-effect mobility of ambipolar TMDs via P(VDF-TrFE) treatment paves a way for realization of high-performance and versatile electronic and optoelectronic devices.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

Effects of surface passivation dielectrics on carrier transport in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Oh, Sejoon; Jang, Han-Soo; Choi, Chel-Jong; Cho, Jaehee

2018-04-01

Dielectric layers prepared by different deposition methods were used for the surface passivation of AlGaN/GaN heterostructure field-effect transistors (HFETs) and the corresponding electrical characteristics were examined. Increases in the sheet charge density and the maximum drain current by approximately 45% and 28%, respectively, were observed after the deposition of a 100 nm-thick SiO2 layer by plasma-enhanced chemical vapor deposition (PECVD) on the top of the AlGaN/GaN HFETs. However, SiO2 deposited by a radio frequency (rf) sputter system had the opposite effect. As the strain applied to AlGaN was influenced by the deposition methods used for the dielectric layers, the carrier transport in the two-dimensional electron gas formed at the interface between AlGaN and GaN was affected accordingly.

Tuning charge transport in pentacene thin-film transistors using the strain-induced electron-phonon coupling modification

NASA Astrophysics Data System (ADS)

Lin, Yow-Jon; Chang, Hsing-Cheng; Liu, Day-Shan

2015-03-01

Tuning charge transport in the bottom-contact pentacene-based organic thin-film transistors (OTFTs) using a MoO x capping layer that serves to the electron-phonon coupling modification is reported. For OTFTs with a MoO x front gate, the enhanced field-effect carrier mobility is investigated. The time domain data confirm the electron-trapping model. To understand the origin of a mobility enhancement, an analysis of the temperature-dependent Hall-effect characteristics is presented. Similarly, the Hall-effect carrier mobility was dramatically increased by capping a MoO x layer on the pentacene front surface. However, the carrier concentration is not affected. The Hall-effect carrier mobility exhibits strong temperature dependence, indicating the dominance of tunneling (hopping) at low (high) temperatures. A mobility enhancement is considered to come from the electron-phonon coupling modification that results from the contribution of long-lifetime electron trapping.

Molecular transistors based on BDT-type molecular bridges.

PubMed

Wheeler, W D; Dahnovsky, Yu

2008-10-21

In this work we study the effect of electron correlations in molecular transistors with molecular bridges based on 1,4-benzene-dithiol (BDT) and 2-nitro-1,4-benzene-dithiol (nitro-BDT) by using ab initio electron propagator calculations. We find that there is no gate field effect for the BDT based transistor in accordance with the experimental data. After verifying the computational method on the BDT molecule, we consider a transistor with a nitro-BDT molecular bridge. From the electron propagator calculations, we predict strong negative differential resistance at small positive and negative values of source-drain voltages. The explanation of the peak and the minimum in the current is given in terms of the molecular orbital picture and switch-on (-off) properties due to the voltage dependencies of the Dyson poles (ionization potentials). When the current is off, the electronic states on both electrodes are populated resulting in the vanishing tunneling probability due to the Pauli principle. Besides the minimum and the maximum in the I-V characteristics, we find a strong gate field effect in the conductance where the peak at V(sd) = 0.15 eV and E(g) = 4x10(-3) a.u. switches to the minimum at E(g) = -4x10(-3) a.u. A similar behavior is discovered at the negative V(sd). Such a feature can be used for fast current modulation by changing the polarity of a gate field.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

PubMed

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Understanding channel and contact effects on transport in 1-dimensional nanotransistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swartzentruber, Brian S.; Delker, Collin James; Yoo, Jinkyoung

Nanowire transistors are generally formed by metal contacts to a uniformly doped nanowire. The transistor can be modeled as a series combination of resistances from both the channel and the contacts. In this study, a simple model is proposed consisting of a resistive channel in series with two Schottky metal-semiconductor contacts modeled using the WKB approximation. This model captures several phenomena commonly observed in nanowire transistor measurements, including the mobility as a function of gate potential, mobility reduction with respect to bulk mobility, and non-linearities in output characteristics. For example, the maximum measured mobility as a function of gate voltagemore » in a nanowire transistor can be predicted based on the semiconductor bulk mobility in addition to barrier height and other properties of the contact. The model is then extended to nanowires with axial p-n junctions having an inde- pendent gate over each wire segment by splitting the channel resistance into a series component for each doping segment. Finally, the contact-channel model is applied to low-frequency noise analysis in nanowire devices, where the noise can be generated in both the channel and the contacts. Because contacts play a major, yet often neglected, role in nanowire transistor operation, they must be accounted for in order to extract meaningful parameters from I-V and noise measurements.« less

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor.

PubMed

Vitale, Wolfgang A; Casu, Emanuele A; Biswas, Arnab; Rosca, Teodor; Alper, Cem; Krammer, Anna; Luong, Gia V; Zhao, Qing-T; Mantl, Siegfried; Schüler, Andreas; Ionescu, A M

2017-03-23

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO 2 ) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

In situ preparation, electrical and surface analytical characterization of pentacene thin film transistors

PubMed Central

Lassnig, R.; Striedinger, B.; Hollerer, M.; Fian, A.; Stadlober, B.; Winkler, A.

2015-01-01

The fabrication of organic thin film transistors with highly reproducible characteristics presents a very challenging task. We have prepared and analyzed model pentacene thin film transistors under ultra-high vacuum conditions, employing surface analytical tools and methods. Intentionally contaminating the gold contacts and SiO2 channel area with carbon through repeated adsorption, dissociation, and desorption of pentacene proved to be very advantageous in the creation of devices with stable and reproducible parameters. We mainly focused on the device properties, such as mobility and threshold voltage, as a function of film morphology and preparation temperature. At 300 K, pentacene displays Stranski-Krastanov growth, whereas at 200 K fine-grained, layer-like film growth takes place, which predominantly influences the threshold voltage. Temperature dependent mobility measurements demonstrate good agreement with the established multiple trapping and release model, which in turn indicates a predominant concentration of shallow traps in the crystal grains and at the oxide-semiconductor interface. Mobility and threshold voltage measurements as a function of coverage reveal that up to four full monolayers contribute to the overall charge transport. A significant influence on the effective mobility also stems from the access resistance at the gold contact-semiconductor interface, which is again strongly influenced by the temperature dependent, characteristic film growth mode. PMID:25814770

In situ preparation, electrical and surface analytical characterization of pentacene thin film transistors

NASA Astrophysics Data System (ADS)

Lassnig, R.; Striedinger, B.; Hollerer, M.; Fian, A.; Stadlober, B.; Winkler, A.

2014-09-01

The fabrication of organic thin film transistors with highly reproducible characteristics presents a very challenging task. We have prepared and analyzed model pentacene thin film transistors under ultra-high vacuum conditions, employing surface analytical tools and methods. Intentionally contaminating the gold contacts and SiO2 channel area with carbon through repeated adsorption, dissociation, and desorption of pentacene proved to be very advantageous in the creation of devices with stable and reproducible parameters. We mainly focused on the device properties, such as mobility and threshold voltage, as a function of film morphology and preparation temperature. At 300 K, pentacene displays Stranski-Krastanov growth, whereas at 200 K fine-grained, layer-like film growth takes place, which predominantly influences the threshold voltage. Temperature dependent mobility measurements demonstrate good agreement with the established multiple trapping and release model, which in turn indicates a predominant concentration of shallow traps in the crystal grains and at the oxide-semiconductor interface. Mobility and threshold voltage measurements as a function of coverage reveal that up to four full monolayers contribute to the overall charge transport. A significant influence on the effective mobility also stems from the access resistance at the gold contact-semiconductor interface, which is again strongly influenced by the temperature dependent, characteristic film growth mode.

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

PubMed Central

Vidor, Fábio F.; Meyers, Thorsten; Hilleringmann, Ulrich

2016-01-01

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates. PMID:28335282

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications.

PubMed

Vidor, Fábio F; Meyers, Thorsten; Hilleringmann, Ulrich

2016-08-23

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high- k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the I ON / I OFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V / V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

EFFECTS OF REACTOR RADIATION ON THE ELECTRICAL PROPERTIES OF ELECTRONIC COMPONENTS. PART II. VACUUM TUBES, TRANSISTORS AND TRANSFORMERS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miglicco, P.S.; Spears, A.B.; Howell, D.B.

1957-11-22

Several types of vacuum tubes, transistors and transformers were irradiated with the Convair-Fort Worth Ground Test Reactor. The components were subjected to five different fluxes ranging from 10/sup 6/ to 10/sup 10/n/sub F// cm/sup 2/-sec and 10/sup 8/ to 10/sup 12/ gamma /cm/sup 2/-sec. The total integrated flux received was 10/sup 14/n/sub F//cm/sup 2/ and 10/sup 16/ gamma / cm/sup 2/. An attempt was made to separate radiation damage as a function of dose rate from radiation damage as a function of dose. The components were irradiated first at several low dose rates so that dose rate effects could bemore » studied while the accumulated dose was small, and then at a high dose rate to obtain the desired dose. However, because of the long time required to complete a data gathering cycle, the accumulated dose hindered the separation of dose rate and dose effects. Thus, in the report, the damage to the components is reported as a function of integrated flux. For reference, the integrated flux accumulated at each power level is given. The transformers exhibited the greatest resistance to irradiation. Every important parameter of the transistors deteriorated in the radiation field. Postirradiation tests at room temperature showed no significant recovery in the transistor's characteristics. The plate current of 65% of the tubes tested increased during irradiation. This effect, based on postirradiation tests, is considered permanent. (auth)« less

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

3D assembly of carbon nanotubes for fabrication of field-effect transistors through nanomanipulation and electron-beam-induced deposition

NASA Astrophysics Data System (ADS)

Yu, Ning; Shi, Qing; Nakajima, Masahiro; Wang, Huaping; Yang, Zhan; Sun, Lining; Huang, Qiang; Fukuda, Toshio

2017-10-01

Three-dimensional carbon nanotube field-effect transistors (3D CNTFETs) possess predictable characteristics that rival those of planar CNTFETs and Si-based MOSFETs. However, due to the lack of a reliable assembly technology, they are rarely reported on, despite the amount of attention they receive. To address this problem, we propose the novel concept of a 3D CNTFET and develop its assembly strategy based on nanomanipulation and the electron-beam-induced deposition (EBID) technique inside a scanning electron microscope (SEM). In particular, the electrodes in our transistor design are three metallic cuboids of the same size, and their front, top and back surfaces are all wrapped up in CNTs. The assembly strategy is employed to build the structure through a repeated basic process of pick-up, placement, fixing and cutting of CNTs. The pick-up and placement is performed through one nanomanipulator with four degrees of freedom. Fixing is carried out through the EBID technique so as to improve the mechanical and electrical characteristics of the CNT/electrodes connection. CNT cutting is undertaken using the typical method of electrical breakdown. Experimental results showed that two CNTs were successfully assembled on the front sides of the cubic electrodes. This validates our assembly method for the 3D CNTFET. Also, when contact resistance was measured, tens of kilohms of resistance was observed at the CNT-EBID deposition-FET electrodes junction.. This manifests the electrical reliability of our assembly strategy.

Doping Nitrogen in InGaZnO Thin Film Transistor with Double Layer Channel Structure.

PubMed

Chang, Sheng-Po; Shan, Deng

2018-04-01

This paper presents the electrical characteristics of doping nitrogen in an amorphous InGaZnO thin film transistor. The IGZO:N film, which acted as a channel layer, was deposited using RF sputtering with a nitrogen and argon gas mixture at room temperature. The optimized parameters of the IGZO:N/IGZO TFT are as follows: threshold voltage is 0.5 V, field effect mobility is 14.34 cm2V-1S-1. The on/off current ratio is 106 and subthreshold swing is 1.48 V/decade. The positive gate bias stress stability of InGaZnO doping with nitrogen shows improvement compared to doping with oxygen.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

The influence of visible light on transparent zinc tin oxide thin film transistors

NASA Astrophysics Data System (ADS)

Görrn, P.; Lehnhardt, M.; Riedl, T.; Kowalsky, W.

2007-11-01

The characteristics of transparent zinc tin oxide thin film transistors (TTFTs) upon illumination with visible light are reported. Generally, a reversible decrease of threshold voltage Vth, saturation field effect mobility μsat, and an increase of the off current are found. The time scale of the recovery in the dark is governed by the persistent photoconductivity in the semiconductor. Devices with tuned [Zn]:[Sn] ratio show a shift of Vth of less 2V upon illumination at 5mW/cm2 (brightness >30000cd/m2) throughout the visible spectrum. These results demonstrate TTFTs which are candidates as pixel drivers in transparent active-matrix organic light emitting diode displays.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Lin, Wei-Chun; Chen, Hao-Wei

2018-06-01

This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Effects of channel thickness on oxide thin film transistor with double-stacked channel layer

NASA Astrophysics Data System (ADS)

Lee, Kimoon; Kim, Yong-Hoon; Yoon, Sung-Min; Kim, Jiwan; Oh, Min Suk

2017-11-01

To improve the field effect mobility and control the threshold voltage ( V th ) of oxide thin film transistors (TFTs), we fabricated the oxide TFTs with double-stacked channel layers which consist of thick Zn-Sn-O (ZTO) and very thin In-Zn-O (IZO) layers. We investigated the effects of the thickness of thin conductive layer and the conductivity of thick layer on oxide TFTs with doublestacked channel layer. When we changed the thickness of thin conductive IZO channel layer, the resistivity values were changed. This resistivity of thin channel layer affected on the saturation field effect mobility and the off current of TFTs. In case of the thick ZTO channel layer which was deposited by sputtering in Ar: O2 = 10: 1, the device showed better performances than that which was deposited in Ar: O2 = 1: 1. Our TFTs showed high mobility ( μ FE ) of 40.7 cm2/Vs and V th of 4.3 V. We assumed that high mobility and the controlled V th were caused by thin conductive IZO layer and thick stable ZTO layer. Therefore, this double-stacked channel structure can be very promising way to improve the electrical characteristics of various oxide thin film transistors.

Temperature dependence of DC transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure

NASA Astrophysics Data System (ADS)

Chou, Kuan-Yu; Hsu, Nai-Wen; Su, Yi-Hsin; Chou, Chung-Tao; Chiu, Po-Yuan; Chuang, Yen; Li, Jiun-Yun

2018-02-01

We investigate DC characteristics of a two-dimensional electron gas (2DEG) in an undoped Si/SiGe heterostructure and its temperature dependence. An insulated-gate field-effect transistor was fabricated, and transfer characteristics were measured at 4 K-300 K. At low temperatures (T < 45 K), source electrons are injected into the buried 2DEG channel first and drain current increases with the gate voltage. By increasing the gate voltage further, the current saturates followed by a negative transconductance observed, which can be attributed to electron tunneling from the buried channel to the surface channel. Finally, the drain current is saturated again at large gate biases due to parallel conduction of buried and surface channels. By increasing the temperature, an abrupt increase in threshold voltage is observed at T ˜ 45 K and it is speculated that negatively charged impurities at the Al2O3/Si interface are responsible for the threshold voltage shift. At T > 45 K, the current saturation and negative transconductance disappear and the device acts as a normal transistor.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

NASA Astrophysics Data System (ADS)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Investigation of Corner Effect and Identification of Tunneling Regimes in L-Shaped Tunnel Field-Effect-Transistor.

PubMed

Najam, Faraz; Yu, Yun Seop

2018-09-01

Corner-effect existing in L-shaped tunnel field-effect-transistor (LTFET) was investigated using numerical simulations and band diagram analysis. It was found that the corner-effect is caused by the convergence of electric field in the sharp source corner present in an LTFET, thereby increasing the electric field in the sharp source corner region. It was found that in the corner-effect region tunneling starts early, as a function of applied bias, as compared to the rest of the channel not affected by corner-effect. Further, different tunneling regimes as a function of applied bias were identified in the LTFET including source to channel and channel to channel tunneling regimes. Presence of different tunneling regimes in LTFET was analytically justified with a set of equations developed to model source to channel, and channel to channel tunneling currents. Drain-current-gate-voltage (Ids-Vgs) characteristics obtained from the equations is in reasonable qualitative agreement with numerical simulation.

Interface trap of p-type gate integrated AlGaN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Kyu Sang

2017-09-01

In this work, the impact of trap states at the p-(Al)GaN/AlGaN interface has been investigated for the normally-off mode p-(Al)GaN/AlGaN/GaN heterostructure field-effect transistors (HFETs) by means of frequency dependent conductance. From the current-voltage (I-V) measurement, it was found that the p-AlGaN gate integrated device has higher drain current and lower gate leakage current compared to the p-GaN gate integrated device. We obtained the interface trap density and the characteristic time constant for the p-type gate integrated HFETs under the forward gate voltage of up to 6 V. As a result, the interface trap density (characteristic time constant) of the p-GaN gate device was lower (longer) than that of the p-AlGaN. Furthermore, it was analyzed that the trap state energy level of the p-GaN gate device was located at the shallow level relative to the p-AlGaN gate device, which accounts for different gate leakage current of each devices.

Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

NASA Astrophysics Data System (ADS)

Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

2016-09-01

In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Design-Oriented Introduction of Nanotechnology into the Electrical and Computer Engineering Curriculum

ERIC Educational Resources Information Center

Kim, Donghwi; Kamoua, Ridha; Pacelli, Andrea

2006-01-01

Nanoelectronics has the potential, and is indeed expected, to revolutionize information technology by the use of the impressive characteristics of nano-devices such as carbon nanotube transistors, molecular diodes and transistors, etc. A great effort is being put into creating an introductory course in nano-technology. However, practically all…

Electrical characteristics and density of states of thin-film transistors based on sol-gel derived ZnO channel layers with different annealing temperatures

NASA Astrophysics Data System (ADS)

Wang, S.; Mirkhani, V.; Yapabandara, K.; Cheng, R.; Hernandez, G.; Khanal, M. P.; Sultan, M. S.; Uprety, S.; Shen, L.; Zou, S.; Xu, P.; Ellis, C. D.; Sellers, J. A.; Hamilton, M. C.; Niu, G.; Sk, M. H.; Park, M.

2018-04-01

We report on the fabrication and electrical characterization of bottom gate thin-film transistors (TFTs) based on a sol-gel derived ZnO channel layer. The effect of annealing of ZnO active channel layers on the electrical characteristics of the ZnO TFTs was systematically investigated. Photoluminescence (PL) spectra indicate that the crystal quality of the ZnO improves with increasing annealing temperature. Both the device turn-on voltage (Von) and threshold voltage (VT) shift to a positive voltage with increasing annealing temperature. As the annealing temperature is increased, both the subthreshold slope and the interfacial defect density (Dit) decrease. The field effect mobility (μFET) increases with annealing temperature, peaking at 800 °C and decreases upon further temperature increase. An improvement in transfer and output characteristics was observed with increasing annealing temperature. However, when the annealing temperature reaches 900 °C, the TFTs demonstrate a large degradation in both transfer and output characteristics, which is possibly produced by non-continuous coverage of the film. By using the temperature-dependent field effect measurements, the localized sub-gap density of states (DOSs) for ZnO TFTs with different annealing temperatures were determined. The DOSs for the subthreshold regime decrease with increasing annealing temperature from 600 °C to 800 °C and no substantial change was observed with further temperature increase to 900 °C.

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

NASA Astrophysics Data System (ADS)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce; Hall, David; Niaz, Iftikhar Ahmad; Zhou, Yuchun; Sham, L. J.; Lo, Yu-Hwa

2015-08-01

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanism based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition.

PubMed

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-12-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al 2 O 3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a , which can explain the experimental observation. A high-field effect mobility of 9.4 cm 2 /Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 10 7 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-01-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al2O3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a, which can explain the experimental observation. A high-field effect mobility of 9.4 cm2/Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 107 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

The role of polarization coulomb field scattering in the electron mobility of AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Liu, Yan; Lin, Zhaojun; Zhao, Jingtao; Yang, Ming; Shi, Wenjing; Lv, Yuanjie; Feng, Zhihong

2016-04-01

The electron mobility for the prepared AlGaN/AlN/GaN heterostructure field-effect transistor (HFET) with the ratio of the gate length to the drain-to-source distance being less than 1/2 has been studied by comparing the measured electron mobility with the theoretical value. The measured electron mobility is derived from the measured capacitance-voltage (C-V) and current-voltage (I-V) characteristics, and the theoretical mobility is determined by using Matthiessen's law, involving six kinds of important scattering mechanisms. For the prepared device at room temperature, longitudinal optical phonon scattering (LO scattering) was found to have a remarkable effect on the value of the electron mobility, and polarization Coulomb field scattering (PCF scattering ) was found to be important to the changing trend of the electron mobility versus the two-dimensional electron gas (2DEG) density.

Numerical simulation of offset-drain amorphous oxide-based thin-film transistors

NASA Astrophysics Data System (ADS)

Jeong, Jaewook

2016-11-01

In this study, we analyzed the electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with an offset-drain structure by technology computer aided design (TCAD) simulation. When operating in a linear region, an enhancement-type TFT shows poor field-effect mobility because most conduction electrons are trapped in acceptor-like defects in an offset region when the offset length (L off) exceeds 0.5 µm, whereas a depletion-type TFT shows superior field-effect mobility owing to the high free electron density in the offset region compared with the trapped electron density. When operating in the saturation region, both types of TFTs show good field-effect mobility comparable to that of a reference TFT with a large gate overlap. The underlying physics of the depletion and enhancement types of offset-drain TFTs are systematically analyzed.

Understanding charge transport in lead iodide perovskite thin-film field-effect transistors

PubMed Central

Senanayak, Satyaprasad P.; Yang, Bingyan; Thomas, Tudor H.; Giesbrecht, Nadja; Huang, Wenchao; Gann, Eliot; Nair, Bhaskaran; Goedel, Karl; Guha, Suchi; Moya, Xavier; McNeill, Christopher R.; Docampo, Pablo; Sadhanala, Aditya; Friend, Richard H.; Sirringhaus, Henning

2017-01-01

Fundamental understanding of the charge transport physics of hybrid lead halide perovskite semiconductors is important for advancing their use in high-performance optoelectronics. We use field-effect transistors (FETs) to probe the charge transport mechanism in thin films of methylammonium lead iodide (MAPbI3). We show that through optimization of thin-film microstructure and source-drain contact modifications, it is possible to significantly minimize instability and hysteresis in FET characteristics and demonstrate an electron field-effect mobility (μFET) of 0.5 cm2/Vs at room temperature. Temperature-dependent transport studies revealed a negative coefficient of mobility with three different temperature regimes. On the basis of electrical and spectroscopic studies, we attribute the three different regimes to transport limited by ion migration due to point defects associated with grain boundaries, polarization disorder of the MA+ cations, and thermal vibrations of the lead halide inorganic cages. PMID:28138550

Directionally Aligned Amorphous Polymer Chains via Electrohydrodynamic-Jet Printing: Analysis of Morphology and Polymer Field-Effect Transistor Characteristics.

PubMed

Kim, Yebyeol; Bae, Jaehyun; Song, Hyun Woo; An, Tae Kyu; Kim, Se Hyun; Kim, Yun-Hi; Park, Chan Eon

2017-11-15

Electrohydrodynamic-jet (EHD-jet) printing provides an opportunity to directly assembled amorphous polymer chains in the printed pattern. Herein, an EHD-jet printed amorphous polymer was employed as the active layer for fabrication of organic field-effect transistors (OFETs). Under optimized conditions, the field-effect mobility (μ FET ) of the EHD-jet printed OFETs was 5 times higher than the highest μ FET observed in the spin-coated OFETs, and this improvement was achieved without the use of complex surface templating or additional pre- or post-deposition processing. As the chain alignment can be affected by the surface energy of the dielectric layer in EHD-jet printed OFETs, dielectric layers with varying wettability were examined. Near-edge X-ray absorption fine structure measurements were performed to compare the amorphous chain alignment in OFET active layers prepared by EHD-jet printing and spin coating.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Fully transparent thin film transistors based on zinc oxide channel layer and molybdenum doped indium oxide electrodes

NASA Astrophysics Data System (ADS)

MÄ dzik, Mateusz; Elamurugu, Elangovan; Viegas, Jaime

2016-03-01

In this work we report the fabrication of thin film transistors (TFT) with zinc oxide channel and molybdenum doped indium oxide (IMO) electrodes, achieved by room temperature sputtering. A set of devices was fabricated, with varying channel width and length from 5μm to 300μm. Output and transfer characteristics were then extracted to study the performance of thin film transistors, namely threshold voltage and saturation current, enabling to determine optimal fabrication process parameters. Optical transmission in the UV-VIS-IR are also reported.

Electric Field-aided Selective Activation for Indium-Gallium-Zinc-Oxide Thin Film Transistors.

PubMed

Lee, Heesoo; Chang, Ki Soo; Tak, Young Jun; Jung, Tae Soo; Park, Jeong Woo; Kim, Won-Gi; Chung, Jusung; Jeong, Chan Bae; Kim, Hyun Jae

2016-10-11

A new technique is proposed for the activation of low temperature amorphous InGaZnO thin film transistor (a-IGZO TFT) backplanes through application of a bias voltage and annealing at 130 °C simultaneously. In this 'electrical activation', the effects of annealing under bias are selectively focused in the channel region. Therefore, electrical activation can be an effective method for lower backplane processing temperatures from 280 °C to 130 °C. Devices fabricated with this method exhibit equivalent electrical properties to those of conventionally-fabricated samples. These results are analyzed electrically and thermodynamically using infrared microthermography. Various bias voltages are applied to the gate, source, and drain electrodes while samples are annealed at 130 °C for 1 hour. Without conventional high temperature annealing or electrical activation, current-voltage curves do not show transfer characteristics. However, electrically activated a-IGZO TFTs show superior electrical characteristics, comparable to the reference TFTs annealed at 280 °C for 1 hour. This effect is a result of the lower activation energy, and efficient transfer of electrical and thermal energy to a-IGZO TFTs. With this approach, superior low-temperature a-IGZO TFTs are fabricated successfully.

Inert gas annealing effect in solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Lee, Seungwoon; Jeong, Jaewook

2017-08-01

In this paper, the annealing effect of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs), under ambient He (He-device), is systematically analyzed by comparison with those under ambient O2 (O2-device) and N2 (N2-device), respectively. The He-device shows high field-effect mobility and low subthreshold slope owing to the minimization of the ambient effect. The degradation of the O2- and N2-device performances originate from their respective deep acceptor-like and shallow donor-like characteristics, which can be verified by comparison with the He-device. However, the three devices show similar threshold voltage instability under prolonged positive bias stress due to the effect of excess oxygen. Therefore, annealing in ambient He is the most suitable method for the fabrication of reference TFTs to study the various effects of the ambient during the annealing process in solution-processed a-IGZO TFTs.

Effect of Pentacene-dielectric Affinity on Pentacene Thin Film Growth Morphology in Organic Field-effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

S Kim; M Jang; H Yang

2011-12-31

Organic field-effect transistors (OFETs) are fabricated by depositing a thin film of semiconductor on the functionalized surface of a SiO{sub 2} dielectric. The chemical and morphological structures of the interface between the semiconductor and the functionalized dielectric are critical for OFET performance. We have characterized the effect of the affinity between semiconductor and functionalized dielectric on the properties of the semiconductor-dielectric interface. The crystalline microstructure/nanostructure of the pentacene semiconductor layers, grown on a dielectric substrate that had been functionalized with either poly(4-vinyl pyridine) or polystyrene (to control hydrophobicity), and grown under a series of substrate temperatures and deposition rates, weremore » characterized by X-ray diffraction, photoemission spectroscopy, and atomic force microscopy. By comparing the morphological features of the semiconductor thin films with the device characteristics (field-effect mobility, threshold voltage, and hysteresis) of the OFET devices, the effect of affinity-driven properties on charge modulation, charge trapping, and charge carrier transport could be described.« less

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

NASA Astrophysics Data System (ADS)

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J.; Janes, David B.

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including `see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In2O3 and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with ~82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics.

PubMed

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J; Janes, David B

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Effect of organic buffer layer in the electrical properties of amorphous-indium gallium zinc oxide thin film transistor.

PubMed

Wang, Jian-Xun; Hyung, Gun Woo; Li, Zhao-Hui; Son, Sung-Yong; Kwon, Sang Jik; Kim, Young Kwan; Cho, Eou Sik

2012-07-01

In this research, we reported on the fabrication of top-contact amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with an organic buffer layer between inorganic gate dielectric and active layer in order to improve the electrical properties of devices. By inserting an organic buffer layer, it was possible to make an affirmation of the improvements in the electrical characteristics of a-IGZO TFTs such as subthreshold slope (SS), on/off current ratio (I(ON/OFF)), off-state current, and saturation field-effect mobility (muFE). The a-IGZO TFTs with the cross-linked polyvinyl alcohol (c-PVA) buffer layer exhibited the pronounced improvements of the muFE (17.4 cm2/Vs), SS (0.9 V/decade), and I(ON/OFF) (8.9 x 10(6)).

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

NASA Technical Reports Server (NTRS)

Duen Ho, Fat; Macleod, Todd C.

1998-01-01

The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Evaluation of Electrical Characteristics and Trap-State Density in Bottom-Gate Polycrystalline Thin Film Transistors Processed with High-Pressure Water Vapor Annealing

NASA Astrophysics Data System (ADS)

Kunii, Masafumi

2006-02-01

This paper discusses electrical characteristics and trap-state density in polycrystalline silicon (poly-Si) used in bottom-gate poly-Si thin film transistors (TFTs) processed with high-pressure water vapor annealing (HWA). The threshold voltage uniformity of the HWA-processed TFTs is improved by 42% for N-channel and 38% for P-channel TFTs in terms of standard deviation, and carrier mobility is enhanced by 10% or greater for both N- and P-channel TFTs than those TFTs processed conventionally. Subthreshold swing is also improved by HWA, showing that HWA postannealing is effective for improving the Si/SiO2 interface of the bottom-gate TFTs. Two types of TFTs having different poly-Si crystallinities are examined to investigate carrier transport in poly-Si processed by HWA postannealing. The evaluation of trap-state density for the two types of poly-Si reveals that HWA postannealing is more efficient for N-channel than for P-channel TFTs. Furthermore, HWA postannealing is more effective for poly-Si with high crystallinity to improve TFT characteristics. The analysis of the trap-state distributions and the activation energy of TFT drain current indicate that HWA deactivates dangling bonds highly localized at poly-Si grain boundaries (GBs). Thus, HWA postannealing effects can be interpreted by a GB barrier potential model similar to that applied to conventional hydrogenation.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Low-frequency noise in MoSe{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Suprem R., E-mail: srdaspurdue@gmail.com, E-mail: janes@purdue.edu; Kwon, Jiseok; Prakash, Abhijith

One of the important performance metrics of emerging nanoelectronic devices, including low dimensional Field Effect Transistors (FETs), is the magnitude of the low-frequency noise. Atomically thin 2D semiconductor channel materials such as MoX{sub 2} (X ≡ S, Se) have shown promising transistor characteristics such as I{sub ON}/I{sub OFF} ratio exceeding 10{sup 6} and low I{sub OFF}, making them attractive as channel materials for next generation nanoelectronic devices. However, MoS{sub 2} FETs demonstrated to date exhibit high noise levels under ambient conditions. In this letter, we report at least two orders of magnitude smaller values of Hooge parameter in a back-gatedmore » MoSe{sub 2} FET (10 atomic layers) with nickel S/D contacts and measured at atmospheric pressure and temperature. The channel dominated regime of noise was extracted from the total noise spectrum and is shown to follow a mobility fluctuation model with 1/f dependence. The low noise in MoSe{sub 2} FETs is comparable to other 1D nanoelectronic devices such as carbon nanotube FETs (CNT-FETs) and paves the way for use in future applications in precision sensing and communications.« less

High-Performance Flexible Thin-Film Transistors Based on Single-Crystal-like Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process.

PubMed

Gao, Ying; Asadirad, Mojtaba; Yao, Yao; Dutta, Pavel; Galstyan, Eduard; Shervin, Shahab; Lee, Keon-Hwa; Pouladi, Sara; Sun, Sicong; Li, Yongkuan; Rathi, Monika; Ryou, Jae-Hyun; Selvamanickam, Venkat

2016-11-02

Single-crystal-like silicon (Si) thin films on bendable and scalable substrates via direct deposition are a promising material platform for high-performance and cost-effective devices of flexible electronics. However, due to the thick and unintentionally highly doped semiconductor layer, the operation of transistors has been hampered. We report the first demonstration of high-performance flexible thin-film transistors (TFTs) using single-crystal-like Si thin films with a field-effect mobility of ∼200 cm 2 /V·s and saturation current, I/l W > 50 μA/μm, which are orders-of-magnitude higher than the device characteristics of conventional flexible TFTs. The Si thin films with a (001) plane grown on a metal tape by a "seed and epitaxy" technique show nearly single-crystalline properties characterized by X-ray diffraction, Raman spectroscopy, reflection high-energy electron diffraction, and transmission electron microscopy. The realization of flexible and high-performance Si TFTs can establish a new pathway for extended applications of flexible electronics such as amplification and digital circuits, more than currently dominant display switches.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Geometric dependence of the parasitic components and thermal properties of HEMTs

NASA Astrophysics Data System (ADS)

Vun, Peter V.; Parker, Anthony E.; Mahon, Simon J.; Fattorini, Anthony

2007-12-01

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Enhanced performance of amorphous In-Ga-Zn-O thin-film transistors using different metals for source/drain electrodes

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-09-01

In this paper, we propose an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with off-planed source/drain electrodes. We applied different metals for the source/drain electrodes with Ni and Ti to control the work function as high and low. When we measured the configuration of Ni to drain and source to Ti, the a-IGZO TFT showed increased driving current, decreased leakage current, a high on/off current ratio, low subthreshold swing, and high mobility. In addition, we conducted a reliability test with a gate bias stress test at various temperatures. The results of the reliability test showed the Ni drain and Ti drain had an equivalent effective energy barrier height. Thus, we confirmed that the proposed off-planed structure improved the electrical characteristics of the fabricated devices without any degradation of characteristics. Through the a-IGZO TFT with different source/drain electrode metal engineering, we realized high-performance TFTs for next-generation display devices.

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE PAGES

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; ...

2014-11-26

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hasanah, Lilik, E-mail: lilikhasanah@upi.edu; Suhendi, Endi; Tayubi, Yuyu Rahmat

In this work we discuss the surface roughness of Si interface impact to the tunneling current of the Si/Si{sub 1-x}Ge{sub x}/Si heterojunction bipolar transistor. The Si interface surface roughness can be analyzed from electrical characteristics through the transversal electron velocity obtained as fitting parameter factor. The results showed that surface roughness increase as Ge content of virtual substrate increase This model can be used to investigate the effect of Ge content of the virtual substrate to the interface surface condition through current-voltage characteristic.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

Electrical properties of solution-deposited ZnO thin-film transistors by low-temperature annealing.

PubMed

Lim, Chul; Oh, Ji Young; Koo, Jae Bon; Park, Chan Woo; Jung, Soon-Won; Na, Bock Soon; Chu, Hye Yong

2014-11-01

Flexible oxide thin-film transistors (Oxide-TFTs) have emerged as next generation transistors because of their applicability in electronic device. In particular, the major driving force behind solution-processed zinc oxide film research is its prospective use in printing for electronics. A low-temperature process to improve the performance of solution-processed n-channel ZnO thin-film transistors (TFTs) fabricated via spin-coating and inkjet-printing is introduced here. ZnO nanoparticles were synthesized using a facile sonochemical method that was slightly modified based on a previously reported method. The influence of the annealing atmosphere on both nanoparticle-based TFT devices fabricated via spin-coating and those created via inkjet printing was investigated. For the inkjet-printed TFTs, the characteristics were improved significantly at an annealing temperature of 150 degrees C. The field effect mobility, V(th), and the on/off current ratios were 3.03 cm2/Vs, -3.3 V, and 10(4), respectively. These results indicate that annealing at 150 degrees C 1 h is sufficient to obtain a mobility (μ(sat)) as high as 3.03 cm2/Vs. Also, the active layer of the solution-based ZnO nanoparticles allowed the production of high-performance TFTs for low-cost, large-area electronics and flexible devices.

A hybrid pulse combining topology utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer.

PubMed

Li, Jiangtao; Zhao, Zheng; Sun, Yi; Liu, Yuhao; Ren, Ziyuan; He, Jiaxin; Cao, Hui; Zheng, Minjun

2017-03-01

Numerous applications driven by pulsed voltage require pulses to be with high amplitude, high repetitive frequency, and narrow width, which could be satisfied by utilizing avalanche transistors. The output improvement is severely limited by power capacities of transistors. Pulse combining is an effective approach to increase the output amplitude while still adopting conventional pulse generating modules. However, there are drawbacks in traditional topologies including the saturation tendency of combining efficiency and waveform oscillation. In this paper, a hybrid pulse combining topology was adopted utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer. The factors affecting the combining efficiency were determined including the output time synchronization of Marx circuits, and the quantity and position of magnetic cores. The numbers of the parallel modules and the stages were determined by the output characteristics of each combining method. Experimental results illustrated the ability of generating pulses with 2-14 kV amplitude, 7-11 ns width, and a maximum 10 kHz repetitive rate on a matched 50-300 Ω resistive load. The hybrid topology would be a convinced pulse combining method for similar nanosecond pulse generators based on the solid-state switches.

Electronic system for data acquisition to study radiation effects on operating MOSFET transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alves de Oliveira, Juliano; Assis de Melo, Marco Antônio; Guazzelli da Silveira, Marcilei A.

In this work we present the development of an acquisition system for characterizing transistors under X-ray radiation. The system is able to carry out the acquisition and to storage characteristic transistor curves. To test the acquisition system we have submitted polarized P channel MOS transistors under continuous 10-keV X-ray doses up to 1500 krad. The characterization system can operate in the saturation region or in the linear region in order to observe the behavior of the currents or voltages involved during the irradiation process. Initial tests consisted of placing the device under test (DUT) in front of the X-ray beammore » direction, while its drain current was constantly monitored through the prototype generated in this work, the data are stored continuously and system behavior was monitored during the test. In order to observe the behavior of the DUT during the radiation tests, we used an acquisition system that consists of an ultra-low consumption16-bit Texas Instruments MSP430 microprocessor. Preliminary results indicate linear behavior of the voltage as a function of the exposure time and fast recovery. These features may be favorable to use this device as a radiation dosimeter to monitor low rate X-ray.« less

Nanoscale-Barrier Formation Induced by Low-Dose Electron-Beam Exposure in Ultrathin MoS2 Transistors.

PubMed

Matsunaga, Masahiro; Higuchi, Ayaka; He, Guanchen; Yamada, Tetsushi; Krüger, Peter; Ochiai, Yuichi; Gong, Yongji; Vajtai, Robert; Ajayan, Pulickel M; Bird, Jonathan P; Aoki, Nobuyuki

2016-10-05

Utilizing an innovative combination of scanning-probe and spectroscopic techniques, supported by first-principles calculations, we demonstrate how electron-beam exposure of field-effect transistors, implemented from ultrathin molybdenum disulfide (MoS 2 ), may cause nanoscale structural modifications that in turn significantly modify the electrical operation of these devices. Quite surprisingly, these modifications are induced by even the relatively low electron doses used in conventional electron-beam lithography, which are found to induce compressive strain in the atomically thin MoS 2 . Likely arising from sulfur-vacancy formation in the exposed regions, the strain gives rise to a local widening of the MoS 2 bandgap, an idea that is supported both by our experiment and by the results of first-principles calculations. A nanoscale potential barrier develops at the boundary between exposed and unexposed regions and may cause extrinsic variations in the resulting electrical characteristics exhibited by the transistor. The widespread use of electron-beam lithography in nanofabrication implies that the presence of such strain must be carefully considered when seeking to harness the potential of atomically thin transistors. At the same time, this work also promises the possibility of exploiting the strain as a means to achieve "bandstructure engineering" in such devices.

A hybrid pulse combining topology utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer

NASA Astrophysics Data System (ADS)

Li, Jiangtao; Zhao, Zheng; Sun, Yi; Liu, Yuhao; Ren, Ziyuan; He, Jiaxin; Cao, Hui; Zheng, Minjun

2017-03-01

Numerous applications driven by pulsed voltage require pulses to be with high amplitude, high repetitive frequency, and narrow width, which could be satisfied by utilizing avalanche transistors. The output improvement is severely limited by power capacities of transistors. Pulse combining is an effective approach to increase the output amplitude while still adopting conventional pulse generating modules. However, there are drawbacks in traditional topologies including the saturation tendency of combining efficiency and waveform oscillation. In this paper, a hybrid pulse combining topology was adopted utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer. The factors affecting the combining efficiency were determined including the output time synchronization of Marx circuits, and the quantity and position of magnetic cores. The numbers of the parallel modules and the stages were determined by the output characteristics of each combining method. Experimental results illustrated the ability of generating pulses with 2-14 kV amplitude, 7-11 ns width, and a maximum 10 kHz repetitive rate on a matched 50-300 Ω resistive load. The hybrid topology would be a convinced pulse combining method for similar nanosecond pulse generators based on the solid-state switches.

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

NASA Astrophysics Data System (ADS)

Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

2017-10-01

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system.

PubMed

Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

2017-10-06

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

All-ion-implanted planar-gate current aperture vertical Ga2O3 MOSFETs with Mg-doped blocking layer

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Goto, Ken; Morikawa, Yoji; Kuramata, Akito; Yamakoshi, Shigenobu; Murakami, Hisashi; Kumagai, Yoshinao; Higashiwaki, Masataka

2018-06-01

A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.

Performance improvement of organic thin film transistors by using active layer with sandwich structure

NASA Astrophysics Data System (ADS)

Ni, Yao; Zhou, Jianlin; Kuang, Peng; Lin, Hui; Gan, Ping; Hu, Shengdong; Lin, Zhi

2017-08-01

We report organic thin film transistors (OTFTs) with pentacene/fluorinated copper phthalo-cyanine (F16CuPc)/pentacene (PFP) sandwich configuration as active layers. The sandwich devices not only show hole mobility enhancement but also present a well control about threshold voltage and off-state current. By investigating various characteristics, including current-voltage hysteresis, organic film morphology, capacitance-voltage curve and resistance variation of active layers carefully, it has been found the performance improvement is mainly attributed to the low carrier traps and the higher conductivity of the sandwich active layer due to the additional induced carriers in F16CuPc/pentacene. Therefore, using proper multiple active layer is an effective way to gain high performance OTFTs.

Observation of Van Hove Singularities and Temperature Dependence of Electrical Characteristics in Suspended Carbon Nanotube Schottky Barrier Transistors

NASA Astrophysics Data System (ADS)

Zhang, Jian; Liu, Siyu; Nshimiyimana, Jean Pierre; Deng, Ya; Hu, Xiao; Chi, Xiannian; Wu, Pei; Liu, Jia; Chu, Weiguo; Sun, Lianfeng

2018-06-01

A Van Hove singularity (VHS) is a singularity in the phonon or electronic density of states of a crystalline solid. When the Fermi energy is close to the VHS, instabilities will occur, which can give rise to new phases of matter with desirable properties. However, the position of the VHS in the band structure cannot be changed in most materials. In this work, we demonstrate that the carrier densities required to approach the VHS are reached by gating in a suspended carbon nanotube Schottky barrier transistor. Critical saddle points were observed in regions of both positive and negative gate voltage, and the conductance flattened out when the gate voltage exceeded the critical value. These novel physical phenomena were evident when the temperature is below 100 K. Further, the temperature dependence of the electrical characteristics was also investigated in this type of Schottky barrier transistor.

New Driving Scheme to Improve Hysteresis Characteristics of Organic Thin Film Transistor-Driven Active-Matrix Organic Light Emitting Diode Display

NASA Astrophysics Data System (ADS)

Yamamoto, Toshihiro; Nakajima, Yoshiki; Takei, Tatsuya; Fujisaki, Yoshihide; Fukagawa, Hirohiko; Suzuki, Mitsunori; Motomura, Genichi; Sato, Hiroto; Tokito, Shizuo; Fujikake, Hideo

2011-02-01

A new driving scheme for an active-matrix organic light emitting diode (AMOLED) display was developed to prevent the picture quality degradation caused by the hysteresis characteristics of organic thin film transistors (OTFTs). In this driving scheme, the gate electrode voltage of a driving-OTFT is directly controlled through the storage capacitor so that the operating point for the driving-OTFT is on the same hysteresis curve for every pixel after signal data are stored in the storage capacitor. Although the number of OTFTs in each pixel for the AMOLED display is restricted because OTFT size should be large enough to drive organic light emitting diodes (OLEDs) due to their small carrier mobility, it can improve the picture quality for an OTFT-driven flexible OLED display with the basic two transistor-one capacitor circuitry.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Recent progress in photoactive organic field-effect transistors.

PubMed

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Voltage-spike analysis for a free-running parallel inverter

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1974-01-01

Unwanted and sometimes damaging high-amplitude voltage spikes occur during each half cycle in many transistor saturable-core inverters at the moment when the core saturates and the transistors switch. The analysis shows that spikes are an intrinsic characteristic of certain types of inverters even with negligible leakage inductance and purely resistive load. The small but unavoidable after-saturation inductance of the saturable-core transformer plays an essential role in creating these undesired thigh-voltage spikes. State-plane analysis provides insight into the complex interaction between core and transistors, and shows the circuit parameters upon which the magnitude of these spikes depends.

Biosensors based on enzyme field-effect transistors for determination of some substrates and inhibitors.

PubMed

Dzyadevych, Sergei V; Soldatkin, Alexey P; Korpan, Yaroslav I; Arkhypova, Valentyna N; El'skaya, Anna V; Chovelon, Jean-Marc; Martelet, Claude; Jaffrezic-Renault, Nicole

2003-10-01

This paper is a review of the authors' publications concerning the development of biosensors based on enzyme field-effect transistors (ENFETs) for direct substrates or inhibitors analysis. Such biosensors were designed by using immobilised enzymes and ion-selective field-effect transistors (ISFETs). Highly specific, sensitive, simple, fast and cheap determination of different substances renders them as promising tools in medicine, biotechnology, environmental control, agriculture and the food industry. The biosensors based on ENFETs and direct enzyme analysis for determination of concentrations of different substrates (glucose, urea, penicillin, formaldehyde, creatinine, etc.) have been developed and their laboratory prototypes were fabricated. Improvement of the analytical characteristics of such biosensors may be achieved by using a differential mode of measurement, working solutions with different buffer concentrations and specific agents, negatively or positively charged additional membranes, or genetically modified enzymes. These approaches allow one to decrease the effect of the buffer capacity influence on the sensor response in an aim to increase the sensitivity of the biosensors and to extend their dynamic ranges. Biosensors for the determination of concentrations of different toxic substances (organophosphorous pesticides, heavy metal ions, hypochlorite, glycoalkaloids, etc.) were designed on the basis of reversible and/or irreversible enzyme inhibition effect(s). The conception of an enzymatic multibiosensor for the determination of different toxic substances based on the enzyme inhibition effect is also described. We will discuss the respective advantages and disadvantages of biosensors based on the ENFETs developed and also demonstrate their practical application.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

NASA Astrophysics Data System (ADS)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts

NASA Astrophysics Data System (ADS)

Cho, Sang-Hyeok; Cho, Kwanghee; Park, No-Won; Park, Soonyong; Koh, Jung-Hyuk; Lee, Sang-Kwon

2017-05-01

We report p-type tin monoselenide (SnSe) single crystals, grown in double-sealed quartz ampoules using a modified Bridgman technique at 920 °C. X-ray powder diffraction (XRD) and energy dispersive X-ray spectroscopy (EDX) measurements clearly confirm that the grown SnSe consists of single-crystal SnSe. Electrical transport of multi-layer SnSe nanoflakes, which were prepared by exfoliation from bulk single crystals, was conducted using back-gated field-effect transistor (FET) structures with Au and Ti contacts on SiO2/Si substrates, revealing that multi-layer SnSe nanoflakes exhibit p-type semiconductor characteristics owing to the Sn vacancies on the surfaces of SnSe nanoflakes. In addition, a strong carrier screening effect was observed in 70-90-nm-thick SnSe nanoflake FETs. Furthermore, the effect of the metal contacts to multi-layer SnSe nanoflake-based FETs is also discussed with two different metals, such as Ti/Au and Au contacts.

Confinement-induced InAs/GaSb heterojunction electron-hole bilayer tunneling field-effect transistor

NASA Astrophysics Data System (ADS)

Padilla, J. L.; Medina-Bailon, C.; Alper, C.; Gamiz, F.; Ionescu, A. M.

2018-04-01

Electron-Hole Bilayer Tunneling Field-Effect Transistors are typically based on band-to-band tunneling processes between two layers of opposite charge carriers where tunneling directions and gate-induced electric fields are mostly aligned (so-called line tunneling). However, the presence of intense electric fields associated with the band bending required to trigger interband tunneling, along with strong confinement effects, has made these types of devices to be regarded as theoretically appealing but technologically impracticable. In this work, we propose an InAs/GaSb heterostructure configuration that, although challenging in terms of process flow design and fabrication, could be envisaged for alleviating the electric fields inside the channel, whereas, at the same time, making quantum confinement become the mechanism that closes the broken gap allowing the device to switch between OFF and ON states. The utilization of induced doping prevents the harmful effect of band tails on the device performance. Simulation results lead to extremely steep slope characteristics endorsing its potential interest for ultralow power applications.

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

The effect of annealing ambient on the characteristics of an indium-gallium-zinc oxide thin film transistor.

PubMed

Park, Soyeon; Bang, Seokhwan; Lee, Seungjun; Park, Joohyun; Ko, Youngbin; Jeon, Hyeongtag

2011-07-01

In this study, the effects of different annealing conditions (air, O2, N2, vacuum) on the chemical and electrical characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFT) were investigated. The contact resistance and interface properties between the IGZO film and the gate dielectric improved after an annealing treatment. However, the chemical bonds in the IGZO bulk changed under various annealing atmospheres, which, in turn, altered the characteristics of the TFTs. The TFTs annealed in vacuum and N2 ambients exhibited undesired switching properties due to the high carrier concentration (>10(17) cm(-3)) of the IGZO active layer. In contrast, the IGZO TFTs annealed in air and oxygen ambients displayed clear transfer characteristics due to an adequately adjusted carrier concentration in the operating range of the TFT. Such an optimal carrier concentration arose through the stabilization of unstable chemical bonds in the IGZO film. With regard to device performance, the TFTs annealed in O2 and air exhibited saturation mobility values of 8.29 and 7.54 cm2/Vs, on-off ratios of 7.34 x 10(8) and 3.95 x 10(8), and subthreshold swing (SS) values of 0.23 and 0.19 V/decade, respectively. Therefore, proper annealing ambients contributed to internal modifications in the IGZO structure and led to an enhancement in the oxidation state of the metal. As a result, defects such as oxygen vacancies were eliminated. Oxygen annealing is thus effective for controlling the carrier concentration of the active layer, decreasing electron traps, and enhancing TFT performance.

A drain current model for amorphous InGaZnO thin film transistors considering temperature effects

NASA Astrophysics Data System (ADS)

Cai, M. X.; Yao, R. H.

2018-03-01

Temperature dependent electrical characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) are investigated considering the percolation and multiple trapping and release (MTR) conduction mechanisms. Carrier-density and temperature dependent carrier mobility in a-IGZO is derived with the Boltzmann transport equation, which is affected by potential barriers above the conduction band edge with Gaussian-like distributions. The free and trapped charge densities in the channel are calculated with Fermi-Dirac statistics, and the field effective mobility of a-IGZO TFTs is then deduced based on the MTR theory. Temperature dependent drain current model for a-IGZO TFTs is finally derived with the obtained low field mobility and free charge density, which is applicable to both non-degenerate and degenerate conductions. This physical-based model is verified by available experiment results at various temperatures.

Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

2015-04-01

1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

Amplified Emission and Field-Effect Transistor Characteristics of One-Dimensionally Structured 2,5-Bis(4-biphenylyl)thiophene Crystals.

PubMed

Hashimoto, Kazumasa; Sasaki, Fumio; Hotta, Shu; Yanagi, Hisao

2016-04-01

One-dimensional (1D) structures of 2,5-bis(4-biphenylyl)thiophene (BP1T) crystals are fabricated for light amplification and field-effect transistor (FET) measurements. A strip-shaped 1D structure (10 µm width) made by photolitography of a vapor-deposited polycrystalline film shows amplified spontaneous emission and lasing oscillations under optical pumping. An FET fabricated with this 1D structure exhibits hole-conduction with a mobility of µh = 8.0 x 10(-3) cm2/Vs. Another 1 D-structured FET is fabricated with epitaxially grown needle-like crystals of BP1T. This needle-crystal FET exhibits higher mobility of µh = 0.34 cm2/Vs. This improved hole mobility is attributed to the single-crystal channel of epitaxial needles while the grain boudaries in the polycrystalline 1 D-structure decrease the carrier transport.

Investigation of silicide-induced-dopant-activation for steep tunnel junction in tunnel field effect transistor (TFET)

NASA Astrophysics Data System (ADS)

Kim, Sihyun; Kwon, Dae Woong; Park, Euyhwan; Lee, Junil; Lee, Roongbin; Lee, Jong-Ho; Park, Byung-Gook

2018-02-01

Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

Bottom-gate poly-Si thin-film transistors by nickel silicide seed-induced lateral crystallization with self-aligned lightly doped layer

NASA Astrophysics Data System (ADS)

Lee, Sol Kyu; Seok, Ki Hwan; Chae, Hee Jae; Lee, Yong Hee; Han, Ji Su; Jo, Hyeon Ah; Joo, Seung Ki

2017-03-01

We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm2/Vs.

Influence of gate width on gate-channel carrier mobility in AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Ming; Ji, Qizheng; Gao, Zhiliang; Zhang, Shufeng; Lin, Zhaojun; Yuan, Yafei; Song, Bo; Mei, Gaofeng; Lu, Ziwei; He, Jihao

2017-11-01

For the fabricated AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate widths, the gate-channel carrier mobility is experimentally obtained from the measured current-voltage and capacitance-voltage curves. Under each gate voltage, the mobility gets lower with gate width increasing. Analysis shows that the phenomenon results from the polarization Coulomb field (PCF) scattering, which originates from the irregularly distributed polarization charges at the AlGaN/GaN interface. The device with a larger gate width is with a larger PCF scattering potential and a stronger PCF scattering intensity. As a function of gate width, PCF scattering potential shows a same trend with the mobility variation. And the theoretically calculated mobility values fits well with the experimentally obtained values. Varying gate widths will be a new perspective for the improvement of device characteristics by modulating the gate-channel carrier mobility.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

NASA Astrophysics Data System (ADS)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Theoretical and experimental studies of the current–voltage and capacitance–voltage of HEMT structures and field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tarasova, E. A.; Obolenskaya, E. S., E-mail: obolensk@rf.unn.ru; Hananova, A. V.

The sensitivity of classical n{sup +}/n{sup –} GaAs and AlGaN/GaN structures with a 2D electron gas (HEMT) and field-effect transistors based on these structures to γ-neutron exposure is studied. The levels of their radiation hardness were determined. A method for experimental study of the structures on the basis of a differential analysis of their current–voltage characteristics is developed. This method makes it possible to determine the structure of the layers in which radiation-induced defects accumulate. A procedure taking into account changes in the plate area of the experimentally measured barrier-contact capacitance associated with the emergence of clusters of radiation-induced defectsmore » that form dielectric inclusions in the 2D-electron-gas layer is presented for the first time.« less

Long-term stability assessment of AlGaN/GaN field effect transistors modified with peptides: Device characteristics vs. surface properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rohrbaugh, Nathaniel; Bryan, Isaac; Bryan, Zachary

AlGaN/GaN Field Effect Transistors (FETs) are promising biosensing devices. Functionalization of these devices is explored in this study using an in situ approach with phosphoric acid etchant and a phosphonic acid derivative. Devices are terminated on peptides and soaked in water for up to 168 hrs to examine FETs for both device responses and surface chemistry changes. Measurements demonstrated threshold voltage shifting after the functionalization and soaking processes, but demonstrated stable FET behavior throughout. X-ray photoelectron spectroscopy and atomic force microscopy confirmed peptides attachment to device surfaces before and after water soaking. Results of this work point to the stabilitymore » of peptide coated functionalized AlGaN/GaN devices in solution and support further research of these devices as disposable, long term, in situ biosensors.« less

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

An EKV-based high voltage MOSFET model with improved mobility and drift model

NASA Astrophysics Data System (ADS)

Chauhan, Yogesh Singh; Gillon, Renaud; Bakeroot, Benoit; Krummenacher, Francois; Declercq, Michel; Ionescu, Adrian Mihai

2007-11-01

An EKV-based high voltage MOSFET model is presented. The intrinsic channel model is derived based on the charge based EKV-formalism. An improved mobility model is used for the modeling of the intrinsic channel to improve the DC characteristics. The model uses second order dependence on the gate bias and an extra parameter for the smoothening of the saturation voltage of the intrinsic drain. An improved drift model [Chauhan YS, Anghel C, Krummenacher F, Ionescu AM, Declercq M, Gillon R, et al. A highly scalable high voltage MOSFET model. In: IEEE European solid-state device research conference (ESSDERC), September 2006. p. 270-3; Chauhan YS, Anghel C, Krummenacher F, Maier C, Gillon R, Bakeroot B, et al. Scalable general high voltage MOSFET model including quasi-saturation and self-heating effect. Solid State Electron 2006;50(11-12):1801-13] is used for the modeling of the drift region, which gives smoother transition on output characteristics and also models well the quasi-saturation region of high voltage MOSFETs. First, the model is validated on the numerical device simulation of the VDMOS transistor and then, on the measured characteristics of the SOI-LDMOS transistor. The accuracy of the model is better than our previous model [Chauhan YS, Anghel C, Krummenacher F, Maier C, Gillon R, Bakeroot B, et al. Scalable general high voltage MOSFET model including quasi-saturation and self-heating effect. Solid State Electron 2006;50(11-12):1801-13] especially in the quasi-saturation region of output characteristics.

Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination

NASA Astrophysics Data System (ADS)

Cho, Yong-Jung; Kim, Woo-Sic; Lee, Yeol-Hyeong; Park, Jeong Ki; Kim, Geon Tae; Kim, Ohyun

2018-06-01

We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that VO2+ were generated near the drain side of TFT, but the hump was not induced when VO2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because VO2+ were created near the drain side, then were migrated to the source side of the TFT.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Analysis of Carbon Nanotube Field-Effect-Transistors (FETs)

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

1999-01-01

This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.

Symmetric voltage-controlled variable resistance

NASA Technical Reports Server (NTRS)

Vanelli, J. C.

1978-01-01

Feedback network makes resistance of field-effect transistor (FET) same for current flowing in either direction. It combines control voltage with source and load voltages to give symmetric current/voltage characteristics. Since circuit produces same magnitude output voltage for current flowing in either direction, it introduces no offset in presense of altering polarity signals. It is therefore ideal for sensor and effector circuits in servocontrol systems.

Silicon induced stability and mobility of indium zinc oxide based bilayer thin film transistors

NASA Astrophysics Data System (ADS)

Chauhan, Ram Narayan; Tiwari, Nidhi; Liu, Po-Tsun; Shieh, Han-Ping D.; Kumar, Jitendra

2016-11-01

Indium zinc oxide (IZO), silicon containing IZO, and IZO/IZO:Si bilayer thin films have been prepared by dual radio frequency magnetron sputtering on glass and SiO2/Si substrates for studying their chemical compositions and electrical characteristics in order to ascertain reliability for thin film transistor (TFT) applications. An attempt is therefore made here to fabricate single IZO and IZO/IZO:Si bilayer TFTs to study the effect of film thickness, silicon incorporation, and bilayer active channel on device performance and negative bias illumination stress (NBIS) stability. TFTs with increasing single active IZO layer thickness exhibit decrease in carrier mobility but steady improvement in NBIS; the best values being μFE ˜ 27.0, 22.0 cm2/Vs and ΔVth ˜ -13.00, -6.75 V for a channel thickness of 7 and 27 nm, respectively. While silicon incorporation is shown to reduce the mobility somewhat, it raises the stability markedly (ΔVth ˜ -1.20 V). Further, IZO (7 nm)/IZO:Si (27 nm) bilayer based TFTs display useful characteristics (field effect mobility, μFE = 15.3 cm2/Vs and NBIS value, ΔVth =-0.75 V) for their application in transparent electronics.

Carrier polarity engineering in carbon nanotube field-effect transistors by induced charges in polymer insulator

NASA Astrophysics Data System (ADS)

Aikawa, Shinya; Kim, Sungjin; Thurakitseree, Theerapol; Einarsson, Erik; Inoue, Taiki; Chiashi, Shohei; Tsukagoshi, Kazuhito; Maruyama, Shigeo

2018-01-01

We present that the electrical conduction type in carbon nanotube field-effect transistors (CNT-FETs) can be converted by induced charges in a polyvinyl alcohol (PVA) insulator. When the CNT channels are covered with pure PVA, the FET characteristics clearly change from unipolar p-type to ambipolar. The addition of ammonium ions (NH4+) in the PVA leads to further conversion to unipolar n-type conduction. The capacitance - voltage characteristics indicate that a high density of positive charges is induced at the PVA/SiO2 interface and within the bulk PVA. Electrons are electrostatically accumulated in the CNT channels due to the presence of the positive charges, and thus, stable n-type conduction of PVA-coated CNT-FETs is observed, even under ambient conditions. The mechanism for conversion of the conduction type is considered to be electrostatic doping due to the large amount of positive charges in the PVA. A blue-shift of the Raman G-band peak was observed for CNTs coated with NH4+-doped PVA, which corresponds to unipolar n-type CNT-FET behavior. These results confirm that carrier polarity engineering in CNT-FETs can be achieved with a charged PVA passivation layer.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

PubMed Central

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-01-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design. PMID:28145438

Full-range electrical characteristics of WS{sub 2} transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Jatinder; Bellus, Matthew Z.; Chiu, Hsin-Ying, E-mail: chiu@ku.edu

We fabricated transistors formed by few layers to bulk single crystal WS{sub 2} to quantify the factors governing charge transport. We established a capacitor network to analyze the full-range electrical characteristics of the channel, highlighting the role of quantum capacitance and interface trap density. We find that the transfer characteristics are mainly determined by the interplay between quantum and oxide capacitances. In the OFF-state, the interface trap density (<10{sup 12} cm{sup –2}) is a limiting factor for the subthreshold swing. Furthermore, the superior crystalline quality and the low interface trap density enabled the subthreshold swing to approach the theoretical limit onmore » a back-gated device on SiO{sub 2}/Si substrate.« less

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce

2015-08-03

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanismmore » based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.« less

Carbon nanotube transistor based high-frequency electronics

NASA Astrophysics Data System (ADS)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks. Carbon nanotube transistor based high-frequency electronics.

Graphene Oxide/Poly(3-hexylthiophene) Nanocomposite Thin-Film Phototransistor for Logic Circuit Applications

NASA Astrophysics Data System (ADS)

Mansouri, S.; Coskun, B.; El Mir, L.; Al-Sehemi, Abdullah G.; Al-Ghamdi, Ahmed; Yakuphanoglu, F.

2018-04-01

Graphene is a sheet-structured material that lacks a forbidden band, being a good candidate for use in radiofrequency applications. We have elaborated graphene-oxide-doped poly(3-hexylthiophene) nanocomposite to increase the interlayer distance and thereby open a large bandgap for use in the field of logic circuits. Graphene oxide/poly(3-hexylthiophene) (GO/P3HT) nanocomposite thin-film transistors (TFTs) were fabricated on silicon oxide substrate by spin coating method. The current-voltage ( I- V) characteristics of TFTs with various P3HT compositions were studied in the dark and under light illumination. The photocurrent, charge carrier mobility, subthreshold voltage, density of interface states, density of occupied states, and I ON/ I OFF ratio of the devices strongly depended on the P3HT weight ratio in the composite. The effects of white-light illumination on the electrical parameters of the transistors were investigated. The results indicated that GO/P3HT nanocomposite thin-film transistors have high potential for use in radiofrequency applications, and their feasibility for use in digital applications has been demonstrated.

Nonlinear Contact Effects in Staggered Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fischer, Axel; Zündorf, Hilke; Kaschura, Felix; Widmer, Johannes; Leo, Karl; Kraft, Ulrike; Klauk, Hagen

2017-11-01

The static and dynamic electrical characteristics of thin-film transistors (TFTs) are often limited by the parasitic contact resistances, especially for TFTs with a small channel length. For the smallest possible contact resistance, the staggered device architecture has a general advantage over the coplanar architecture of a larger injection area. Since the charge transport occurs over an extended area, it is inherently more difficult to develop an accurate analytical device model for staggered TFTs. Most analytical models for staggered TFTs, therefore, assume that the contact resistance is linear, even though this is commonly accepted not to be the case. Here, we introduce a semiphenomenological approach to accurately fit experimental data based on a highly discretized equivalent network circuit explicitly taking into account the inherent nonlinearity of the contact resistance. The model allows us to investigate the influence of nonlinear contact resistances on the static and dynamic performance of staggered TFTs for different contact layouts with a relatively short computation time. The precise extraction of device parameters enables us to calculate the transistor behavior as well as the potential for optimization in real circuits.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

Use of vacuum tubes in test instrumentation for measuring characteristics of fast high-voltage semiconductor devices

NASA Technical Reports Server (NTRS)

Berning, D.

1981-01-01

Circuits are described that permit measurement of fast events occurring in power semiconductors. These circuits were developed for the dynamic characterization of transistors used in inductive-load switching applications. Fast voltage clamping using vacuum diodes is discussed, and reference is made to a unique circuit that was built for performing nondestructive, reverse-bias, second-breakdown tests on transistors.

Electric Field-aided Selective Activation for Indium-Gallium-Zinc-Oxide Thin Film Transistors

NASA Astrophysics Data System (ADS)

Lee, Heesoo; Chang, Ki Soo; Tak, Young Jun; Jung, Tae Soo; Park, Jeong Woo; Kim, Won-Gi; Chung, Jusung; Jeong, Chan Bae; Kim, Hyun Jae

2016-10-01

A new technique is proposed for the activation of low temperature amorphous InGaZnO thin film transistor (a-IGZO TFT) backplanes through application of a bias voltage and annealing at 130 °C simultaneously. In this ‘electrical activation’, the effects of annealing under bias are selectively focused in the channel region. Therefore, electrical activation can be an effective method for lower backplane processing temperatures from 280 °C to 130 °C. Devices fabricated with this method exhibit equivalent electrical properties to those of conventionally-fabricated samples. These results are analyzed electrically and thermodynamically using infrared microthermography. Various bias voltages are applied to the gate, source, and drain electrodes while samples are annealed at 130 °C for 1 hour. Without conventional high temperature annealing or electrical activation, current-voltage curves do not show transfer characteristics. However, electrically activated a-IGZO TFTs show superior electrical characteristics, comparable to the reference TFTs annealed at 280 °C for 1 hour. This effect is a result of the lower activation energy, and efficient transfer of electrical and thermal energy to a-IGZO TFTs. With this approach, superior low-temperature a-IGZO TFTs are fabricated successfully.

Electric Field-aided Selective Activation for Indium-Gallium-Zinc-Oxide Thin Film Transistors

PubMed Central

Lee, Heesoo; Chang, Ki Soo; Tak, Young Jun; Jung, Tae Soo; Park, Jeong Woo; Kim, Won-Gi; Chung, Jusung; Jeong, Chan Bae; Kim, Hyun Jae

2016-01-01

A new technique is proposed for the activation of low temperature amorphous InGaZnO thin film transistor (a-IGZO TFT) backplanes through application of a bias voltage and annealing at 130 °C simultaneously. In this ‘electrical activation’, the effects of annealing under bias are selectively focused in the channel region. Therefore, electrical activation can be an effective method for lower backplane processing temperatures from 280 °C to 130 °C. Devices fabricated with this method exhibit equivalent electrical properties to those of conventionally-fabricated samples. These results are analyzed electrically and thermodynamically using infrared microthermography. Various bias voltages are applied to the gate, source, and drain electrodes while samples are annealed at 130 °C for 1 hour. Without conventional high temperature annealing or electrical activation, current-voltage curves do not show transfer characteristics. However, electrically activated a-IGZO TFTs show superior electrical characteristics, comparable to the reference TFTs annealed at 280 °C for 1 hour. This effect is a result of the lower activation energy, and efficient transfer of electrical and thermal energy to a-IGZO TFTs. With this approach, superior low-temperature a-IGZO TFTs are fabricated successfully. PMID:27725695

Bandlike Transport in Ferroelectric-Based Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Laudari, A.; Guha, S.

2016-10-01

The dielectric constant of polymer-ferroelectric dielectrics may be tuned by changing the temperature, offering a platform for monitoring changes in interfacial transport with the polarization strength in organic field-effect transistors (FETs). Temperature-dependent transport studies of FETs are carried out from a solution-processed organic semiconductor, 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene), using both ferroelectric- and nonferroelectric-gate insulators. Nonferroelectric dielectric-based TIPS-pentacene FETs show a clear activated transport, in contrast to the ferroelectric dielectric polymer, poly(vinylidene fluoride-trifluoroethylene), where a negative temperature coefficient of the mobility is observed in the ferroelectric temperature range. The current-voltage (I -V ) characteristics from TIPS-pentacene diodes signal a space-charge-limited conduction (SCLC) for a discrete set of trap levels, suggesting that charge injection and transport occurs through regions of ordering in the semiconductor. The carrier mobility extracted from temperature-dependent I -V characteristics from the trap-free SCLC region shows a negative coefficient beyond 200 K, similar to the trend observed in FETs with the ferroelectric dielectric. At moderate temperatures, the polarization-fluctuation-dominant transport inherent in a ferroelectric dielectric, in conjunction with the nature of traps, results in an effective detrapping of the shallow-trap states into more mobile states in TIPS-pentacene.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Field-induced strain degradation of AlGaN/GaN high electron mobility transistors on a nanometer scale

NASA Astrophysics Data System (ADS)

Lin, Chung-Han; Doutt, D. R.; Mishra, U. K.; Merz, T. A.; Brillson, L. J.

2010-11-01

Nanoscale Kelvin probe force microscopy and depth-resolved cathodoluminescence spectroscopy reveal an electronic defect evolution inside operating AlGaN/GaN high electron mobility transistors with degradation under electric-field-induced stress. Off-state electrical stress results in micron-scale areas within the extrinsic drain expanding and decreasing in electric potential, midgap defects increasing by orders-of-magnitude at the AlGaN layer, and local Fermi levels lowering as gate-drain voltages increase above a characteristic stress threshold. The pronounced onset of defect formation, Fermi level movement, and transistor degradation at the threshold gate-drain voltage of J. A. del Alamo and J. Joh [Microelectron. Reliab. 49, 1200 (2009)] is consistent with crystal deformation and supports the inverse piezoelectric model of high electron mobility transistor degradation.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain.

PubMed

Lee, Sungsik; Nathan, Arokia

2016-10-21

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation. Copyright © 2016, American Association for the Advancement of Science.

Thermal transistor behavior of a harmonic chain

NASA Astrophysics Data System (ADS)

Kim, Sangrak

2017-09-01

Thermal transistor behavior of a harmonic chain with three heat reservoirs is explicitly analyzed. Temperature profile and heat currents of the rather general system are formulated and then heat currents for the simplest system are exactly calculated. The matrix connecting the three temperatures of the reservoirs and those of the particles comprises a stochastic matrix. The ratios R 1 and R 2 between heat currents, characterizing thermal signals can be expressed in terms of two external variables and two material parameters. It is shown that the ratios R 1 and R 2 can have wide range of real values. The thermal system shows a thermal transistor behavior such as the amplification of heat current by appropriately controlling the two variables and two parameters. We explicitly demonstrate the characteristics and mechanisms of thermal transistor with the simplest model.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Neuromorphic transistor achieved by redox reaction of WO3 thin film

NASA Astrophysics Data System (ADS)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

Prediction of the thermal annealing of thick oxide metal-oxide-semiconductor dosimeters irradiated in a harsh radiation environment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ravotti, F.; Glaser, M.; Saigne, F.

Radiation-sensing metal-oxide-semiconductor field-effect transistors produced by the laboratory LAAS-CNRS were exposed to a harsh hadron field that represents the real radiation environment expected at the CERN Large Hadron Collider experiments. The long-term stability of the transistor's I{sub ds}-V{sub gs} characteristic was investigated using the isochronal annealing technique. In this work, devices exposed to high intensity hadron levels ({phi}{>=}10{sup 12} neutrons/cm{sup 2}) show evidences of displacement damages in the I{sub ds}-V{sub gs} annealing behavior. By comparing experimental and simulated results over 14 months, the isochronal annealing method, originally devoted to oxide trapped charge, is shown to enable prediction of the recoverymore » of silicon bulk defects.« less

Deposition of tetracene thin films on SiO2/Si substrates by rapid expansion of supercritical solutions using carbon dioxide

NASA Astrophysics Data System (ADS)

Fujii, Tatsuya; Takahashi, Yuta; Uchida, Hirohisa

2015-03-01

We report on a novel deposition technique of tetracene (naphthacene) thin films on SiO2/Si substrates by rapid expansion of supercritical solutions (RESS) using CO2. Optical microscopy and scanning electron microscopy show that the thin films consist of a high density of submicron-sized grains. The growth mode of the grains followed the Volmer-Weber mode. X-ray diffraction shows that the thin films have regularly arranged structures in both the horizontal and vertical directions of the substrate. A fabricated top-contacted organic thin-film transistor with the tetracene active layer showed p-type transistor characteristics with a field-effect mobility of 5.1 × 10-4 cm2 V-1 s-1.

High-Performance Sensors Based on Resistance Fluctuations of Single-Layer-Graphene Transistors.

PubMed

Amin, Kazi Rafsanjani; Bid, Aveek

2015-09-09

One of the most interesting predicted applications of graphene-monolayer-based devices is as high-quality sensors. In this article, we show, through systematic experiments, a chemical vapor sensor based on the measurement of low-frequency resistance fluctuations of single-layer-graphene field-effect-transistor devices. The sensor has extremely high sensitivity, very high specificity, high fidelity, and fast response times. The performance of the device using this scheme of measurement (which uses resistance fluctuations as the detection parameter) is more than 2 orders of magnitude better than a detection scheme in which changes in the average value of the resistance is monitored. We propose a number-density-fluctuation-based model to explain the superior characteristics of a noise-measurement-based detection scheme presented in this article.

Recovery in dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors with thermal annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Byung-Jae; Hwang, Ya-Hsi; Ahn, Shihyun

The recovery effects of thermal annealing on dc and rf performance of off-state step-stressed AlGaN/GaN high electron mobility transistors were investigated. After stress, reverse gate leakage current and sub-threshold swing increased and drain current on-off ratio decreased. However, these degradations were completely recovered after thermal annealing at 450 °C for 10 mins for devices stressed either once or twice. The trap densities, which were estimated by temperature-dependent drain-current sub-threshold swing measurements, increased after off-state step-stress and were reduced after subsequent thermal annealing. In addition, the small signal rf characteristics of stressed devices were completely recovered after thermal annealing.

Fabrication of InGaN thin-film transistors using pulsed sputtering deposition.

PubMed

Itoh, Takeki; Kobayashi, Atsushi; Ueno, Kohei; Ohta, Jitsuo; Fujioka, Hiroshi

2016-07-07

We report the first demonstration of operational InGaN-based thin-film transistors (TFTs) on glass substrates. The key to our success was coating the glass substrate with a thin amorphous layer of HfO2, which enabled a highly c-axis-oriented growth of InGaN films using pulsed sputtering deposition. The electrical characteristics of the thin films were controlled easily by varying their In content. The optimized InGaN-TFTs exhibited a high on/off ratio of ~10(8), a field-effect mobility of ~22 cm(2) V(-1) s(-1), and a maximum current density of ~30 mA/mm. These results lay the foundation for developing high-performance electronic devices on glass substrates using group III nitride semiconductors.

Effects of the F₄TCNQ-Doped Pentacene Interlayers on Performance Improvement of Top-Contact Pentacene-Based Organic Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Lin, Wei-Chun; Chang, Hsiang-Sheng; Lin, Yu-Zuo; Huang, Bohr-Ran

2016-01-13

In this paper, the top-contact (TC) pentacene-based organic thin-film transistor (OTFT) with a tetrafluorotetracyanoquinodimethane (F₄TCNQ)-doped pentacene interlayer between the source/drain electrodes and the pentacene channel layer were fabricated using the co-evaporation method. Compared with a pentacene-based OTFT without an interlayer, OTFTs with an F₄TCNQ:pentacene ratio of 1:1 showed considerably improved electrical characteristics. In addition, the dependence of the OTFT performance on the thickness of the F₄TCNQ-doped pentacene interlayer is weaker than that on a Teflon interlayer. Therefore, a molecular doping-type F₄TCNQ-doped pentacene interlayer is a suitable carrier injection layer that can improve the TC-OTFT performance and facilitate obtaining a stable process window.

Fabrication of field-effect transistor utilizing oriented thin film of octahexyl-substituted phthalocyanine and its electrical anisotropy based on columnar structure

NASA Astrophysics Data System (ADS)

Ohmori, Masashi; Nakatani, Mitsuhiro; Kajii, Hirotake; Miyamoto, Ayano; Yoneya, Makoto; Fujii, Akihiko; Ozaki, Masanori

2018-03-01

Field-effect transistors with molecularly oriented thin films of metal-free non-peripherally octahexyl-substituted phthalocyanine (C6PcH2), which characteristically form a columnar structure, have been fabricated, and the electrical anisotropy of C6PcH2 has been investigated. The molecularly oriented thin films of C6PcH2 were prepared by the bar-coating technique, and the uniform orientation in a large area and the surface roughness at a molecular level were observed by polarized spectroscopy and atomic force microscopy, respectively. The field effect mobilities parallel and perpendicular to the column axis of C6PcH2 were estimated to be (1.54 ± 0.24) × 10-2 and (2.10 ± 0.23) × 10-3 cm2 V-1 s-1, respectively. The electrical anisotropy based on the columnar structure has been discussed by taking the simulated results obtained by density functional theory calculation into consideration.

Study of tunneling transport in Si-based tunnel field-effect transistors with ON current enhancement utilizing isoelectronic trap

NASA Astrophysics Data System (ADS)

Mori, Takahiro; Morita, Yukinori; Miyata, Noriyuki; Migita, Shinji; Fukuda, Koichi; Mizubayashi, Wataru; Masahara, Meishoku; Yasuda, Tetsuji; Ota, Hiroyuki

2015-02-01

The temperature dependence of the tunneling transport characteristics of Si diodes with an isoelectronic impurity has been investigated in order to clarify the mechanism of the ON-current enhancement in Si-based tunnel field-effect transistors (TFETs) utilizing an isoelectronic trap (IET). The Al-N complex impurity was utilized for IET formation. We observed three types of tunneling current components in the diodes: indirect band-to-band tunneling (BTBT), trap-assisted tunneling (TAT), and thermally inactive tunneling. The indirect BTBT and TAT current components can be distinguished with the plot described in this paper. The thermally inactive tunneling current probably originated from tunneling consisting of two paths: tunneling between the valence band and the IET trap and tunneling between the IET trap and the conduction band. The probability of thermally inactive tunneling with the Al-N IET state is higher than the others. Utilization of the thermally inactive tunneling current has a significant effect in enhancing the driving current of Si-based TFETs.

Organic-inorganic proximity effect in the magneto-conductance of vertical organic field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khachatryan, B.; Devir-Wolfman, A. H.; Ehrenfreund, E., E-mail: eitane@technion.ac.il

Vertical organic field effect transistors having a patterned source electrode and an a-SiO{sub 2} insulation layer show high performance as a switching element with high transfer characteristics. By measuring the low field magneto-conductance under ambient conditions at room temperature, we show here that the proximity of the inorganic a-SiO{sub 2} insulation to the organic conducting channel affects considerably the magnetic response. We propose that in n-type devices, electrons in the organic conducting channel and spin bearing charged defects in the inorganic a-SiO{sub 2} insulation layer (e.g., O{sub 2} = Si{sup +·}) form oppositely charged spin pairs whose singlet-triplet spin configurations are mixedmore » through the relatively strong hyperfine field of {sup 29}Si. By increasing the contact area between the insulation layer and the conducting channel, the ∼2% magneto-conductance response may be considerably enhanced.« less

On the AlGaInP-bulk and AlGaInP/GaAs-superlattice confinement effects for heterostructure-emitter bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw

2015-02-09

The confinement effect and electrical characteristics of heterostructure-emitter bipolar transistors with an AlGaInP bulk-confinement layer and an AlGaInP/GaAs superlattice-confinement layer are first demonstrated and compared by experimentally results. In the two devices, the relatively large valence band discontinuity at AlGaInP/GaAs heterojunction provides excellent confinement effect for holes to enhance current gain. As to the AlGaInP/GaAs superlattice-confinement device, part of thermionic-emission electrons will be trapped in the GaAs quantum wells of the superlattice. This will result in lower collector current and current gain as compared with the bulk-confinement device. Nevertheless, the superlattice-confinement device exhibits a larger current-gain cutoff frequency, which canmore » be attributed that the tunneling behavior is included in the carrier transportation and transporting time across the emitter region could be substantially reduced.« less

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

N Channel JFET Based Digital Logic Gate Structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Photojunction field-effect transistor based on a colloidal quantum dot absorber channel layer.

PubMed

Adinolfi, Valerio; Kramer, Illan J; Labelle, André J; Sutherland, Brandon R; Hoogland, S; Sargent, Edward H

2015-01-27

The performance of photodetectors is judged via high responsivity, fast speed of response, and low background current. Many previously reported photodetectors based on size-tuned colloidal quantum dots (CQDs) have relied either on photodiodes, which, since they are primary photocarrier devices, lack gain; or photoconductors, which provide gain but at the expense of slow response (due to delayed charge carrier escape from sensitizing centers) and an inherent dark current vs responsivity trade-off. Here we report a photojunction field-effect transistor (photoJFET), which provides gain while breaking prior photoconductors' response/speed/dark current trade-off. This is achieved by ensuring that, in the dark, the channel is fully depleted due to a rectifying junction between a deep-work-function transparent conductive top contact (MoO3) and a moderately n-type CQD film (iodine treated PbS CQDs). We characterize the rectifying behavior of the junction and the linearity of the channel characteristics under illumination, and we observe a 10 μs rise time, a record for a gain-providing, low-dark-current CQD photodetector. We prove, using an analytical model validated using experimental measurements, that for a given response time the device provides a two-orders-of-magnitude improvement in photocurrent-to-dark-current ratio compared to photoconductors. The photoJFET, which relies on a junction gate-effect, enriches the growing family of CQD photosensitive transistors.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Solid-gate control of insulator to 2D metal transition at SrTiO3 surface

NASA Astrophysics Data System (ADS)

Schulman, Alejandro; Stoliar, Pablo; Kitoh, Ai; Rozenberg, Marcelo; Inoue, Isao H.

As miniaturization of the semiconductor transistor approaches its limit, semiconductor industries are facing a major challenge to extend information processing beyond what can be attainable by conventional Si-based transistors. Innovative combinations of new materials and new processing platforms are desired. Recent discovery of the 2D electron gas (2DEG) at the surface of SrTiO3 (STO) and its electrostatic control, have carried it to the top of promising materials to be utilized in innovative devices. We report an electrostatic control of the carrier density of the 2DEG formed at the channel of bilayer-gated STO field-effect devices. By applying a gate electric field at room temperature, its highly insulating channel exhibits a transition to metallic one. This transition is accompanied by non-monotonic voltage-gain transfer characteristic with both negative and positive slope regions and unexpected enhancement of the sheet carrier density. We will introduce a numerical model to rationalize the observed features in terms of the established physics of field-effect transistors and the physics of percolation. Furthermore, we have found a clear signature of a Kondo effect that arises due to the interaction between the dilute 2DEG and localized Ti 3d orbitals originated by oxygen vacancies near the channel. On leave from CIC nanoGUNE, Spain.

Novel H+-Ion Sensor Based on a Gated Lateral BJT Pair

PubMed Central

Yuan, Heng; Zhang, Jixing; Cao, Chuangui; Zhang, Gangyuan; Zhang, Shaoda

2015-01-01

An H+-ion sensor based on a gated lateral bipolar junction transistor (BJT) pair that can operate without the classical reference electrode is proposed. The device is a special type of ion-sensitive field-effect transistor (ISFET). Classical ISFETs have the advantage of miniaturization, but  they are difficult to fabricate by a single fabrication process because of the bulky and brittle reference electrode materials. Moreover, the reference electrodes need to be separated from the sensor device in some cases. The proposed device is composed of two gated lateral BJT components, one of which had a silicide layer while the other was without the layer. The two components were operated under the metal-oxide semiconductor field-effect transistor (MOSFET)-BJT hybrid mode, which can be controlled by emitter voltage and base current. Buffer solutions with different pH values were used as the sensing targets to verify the characteristics of the proposed device. Owing to their different sensitivities, both components could simultaneously detect the H+-ion concentration and function as a reference to each other. Per the experimental results, the sensitivity of the proposed device was found to be approximately 0.175 μA/pH. This experiment demonstrates enormous potential to lower the cost of the ISFET-based sensor technology. PMID:26703625

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

SOI MESFETs on high-resistivity, trap-rich substrates

NASA Astrophysics Data System (ADS)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Nonlinear current-voltage characteristics and enhanced negative differential conductance in graphene field effect transistors.

PubMed

Wang, Lin; Chen, Xiaoshuang; Hu, Yibin; Yu, Anqi; Lu, Wei

2014-11-07

Recent observations of the negative differential conductance (NDC) phenomenon in graphene field-effect transistors (FET) open up new opportunities for their application in graphene-based fast switches, frequency multipliers and, most importantly, in high frequency oscillators up to the terahertz regime. Unlike conventional two-terminal NDC devices that rely on resonant tunneling and inter-valley transferring, in the present work, it has been shown that the universal NDC phenomenon of graphene-based FETs originates from their intrinsic nonlinear carrier transport under a strong electric field. The operation of graphene-NDC devices depends strongly on the interface between graphene and dielectric materials, the scattering-limited carrier mobility, and on the saturation velocity. To reveal such NDC behavior, the output characteristics of GFET are investigated rigorously, with both an analytical model and self-consistent transport equation, and with a multi-electrical parameter simulation. It is demonstrated that the contact-induced doping effect plays an important role in the operational efficiency of graphene-based NDC devices, rather than the ambipolar behavior associated with the competition between electron and hole conductances. In the absence of a NDC regime or beyond one, ambipolar transport starts at Vds > 2Vgs at the drain end, and as the dielectric layer begins to thin down, the kink-like saturation output characteristic is enhanced by the quantum capacitance contribution. These observations reveal the intrinsic mechanism of the NDC effect and open up new opportunities for the performance improvement of GFETs in future high-frequency applications, beyond the current paradigm based on two-terminal diodes.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

NASA Astrophysics Data System (ADS)

Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Münzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Tröster, Gerhard; Anthopoulos, Thomas D.

2017-03-01

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V-1 s-1 and 0.013 cm2 V-1 s-1, respectively, current on/off ratio in the range 102-104, and maximum operating voltages between -3.5 and -10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as -3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Top-down nanofabrication of silicon nanoribbon field effect transistor (Si-NR FET) for carcinoembryonic antigen detection.

PubMed

Bao, Zengtao; Sun, Jialin; Zhao, Xiaoqian; Li, Zengyao; Cui, Songkui; Meng, Qingyang; Zhang, Ye; Wang, Tong; Jiang, Yanfeng

2017-01-01

Sensitive and quantitative detection of tumor markers is highly required in the clinic for cancer diagnosis and consequent treatment. A field-effect transistor-based (FET-based) nanobiosensor emerges with characteristics of being label-free, real-time, having high sensitivity, and providing direct electrical readout for detection of biomarkers. In this paper, a top-down approach is proposed and implemented to fulfill a novel silicon nano-ribbon FET, which acts as biomarker sensor for future clinical application. Compared with the bottom-up approach, a top-down fabrication approach can confine width and length of the silicon FET precisely to control its electrical properties. The silicon nanoribbon (Si-NR) transistor is fabricated on a Silicon-on-Insulator (SOI) substrate by a top-down approach with complementary metal oxide semiconductor (CMOS)-compatible technology. After the preparation, the surface of Si-NR is functionalized with 3-aminopropyltriethoxysilane (APTES). Glutaraldehyde is utilized to bind the amino terminals of APTES and antibody on the surface. Finally, a microfluidic channel is integrated on the top of the device, acting as a flowing channel for the carcinoembryonic antigen (CEA) solution. The Si-NR FET is 120 nm in width and 25 nm in height, with ambipolar electrical characteristics. A logarithmic relationship between the changing ratio of the current and the CEA concentration is measured in the range of 0.1-100 ng/mL. The sensitivity of detection is measured as 10 pg/mL. The top-down fabricated biochip shows feasibility in direct detecting of CEA with the benefits of real-time, low cost, and high sensitivity as a promising biosensor for tumor early diagnosis.

Effect of cleaning procedures on the electrical properties of carbon nanotube transistors—A statistical study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tittmann-Otto, J., E-mail: jana.tittmann-otto@zfm.tu-chemnitz.de; Hermann, S.; Hartmann, M.

The interface between a carbon nanotube (CNT) and its environment can dramatically affect the electrical properties of CNT-based field-effect transistors (FETs). For such devices, the channel environment plays a significant role inducing doping or charge traps giving rise to hysteresis in the transistor characteristics. Thereby the fabrication process strongly determines the extent of those effects and the final device performance. In CNT-based devices obtained from dispersions, a proper individualization of the nanotubes is mandatory. This is generally realized by an ultrasonic treatment combined with surfactant molecules, which enwrap nanotubes forming micelle aggregates. To minimize impact on device performance, it ismore » of vital importance to consider post-deposition treatments for removal of surfactant molecules and other impurities. In this context, we investigated the effect of several wet chemical cleaning and thermal post treatments on the electrical characteristics as well as physical properties of more than 600 devices fabricated only by wafer-level compatible technologies. We observed that nitric acid and water treatments improved the maximum-current of devices. Additionally, we found that the ethanol treatment successfully lowered hysteresis in the transfer characteristics. The effect of the chemical cleaning procedures was found to be more significant on CNT-metal contacts than for the FET channels. Moreover, we investigated the effect of an additional thermal cleaning step under vacuum after the chemical cleaning, which had an exceptional impact on the hysteresis behavior including hysteresis reversal. The presence of surfactant molecules on CNT was evidenced by X-ray photoelectron and Raman spectroscopies. By identifying the role of surfactant molecules and assessing the enhancement of device performance as a direct consequence of several cleaning procedures, these results are important for the development of CNT-based electronics at the wafer-level.« less

Effect of cleaning procedures on the electrical properties of carbon nanotube transistors—A statistical study

NASA Astrophysics Data System (ADS)

Tittmann-Otto, J.; Hermann, S.; Kalbacova, J.; Hartmann, M.; Toader, M.; Rodriguez, R. D.; Schulz, S. E.; Zahn, D. R. T.; Gessner, T.

2016-03-01

The interface between a carbon nanotube (CNT) and its environment can dramatically affect the electrical properties of CNT-based field-effect transistors (FETs). For such devices, the channel environment plays a significant role inducing doping or charge traps giving rise to hysteresis in the transistor characteristics. Thereby the fabrication process strongly determines the extent of those effects and the final device performance. In CNT-based devices obtained from dispersions, a proper individualization of the nanotubes is mandatory. This is generally realized by an ultrasonic treatment combined with surfactant molecules, which enwrap nanotubes forming micelle aggregates. To minimize impact on device performance, it is of vital importance to consider post-deposition treatments for removal of surfactant molecules and other impurities. In this context, we investigated the effect of several wet chemical cleaning and thermal post treatments on the electrical characteristics as well as physical properties of more than 600 devices fabricated only by wafer-level compatible technologies. We observed that nitric acid and water treatments improved the maximum-current of devices. Additionally, we found that the ethanol treatment successfully lowered hysteresis in the transfer characteristics. The effect of the chemical cleaning procedures was found to be more significant on CNT-metal contacts than for the FET channels. Moreover, we investigated the effect of an additional thermal cleaning step under vacuum after the chemical cleaning, which had an exceptional impact on the hysteresis behavior including hysteresis reversal. The presence of surfactant molecules on CNT was evidenced by X-ray photoelectron and Raman spectroscopies. By identifying the role of surfactant molecules and assessing the enhancement of device performance as a direct consequence of several cleaning procedures, these results are important for the development of CNT-based electronics at the wafer-level.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Direct observation of single-charge-detection capability of nanowire field-effect transistors.

PubMed

Salfi, J; Savelyev, I G; Blumin, M; Nair, S V; Ruda, H E

2010-10-01

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.

Morphological Influence of Solution-Processed Zinc Oxide Films on Electrical Characteristics of Thin-Film Transistors.

PubMed

Lee, Hyeonju; Zhang, Xue; Hwang, Jaeeun; Park, Jaehoon

2016-10-19

We report on the morphological influence of solution-processed zinc oxide (ZnO) semiconductor films on the electrical characteristics of ZnO thin-film transistors (TFTs). Different film morphologies were produced by controlling the spin-coating condition of a precursor solution, and the ZnO films were analyzed using atomic force microscopy, X-ray diffraction, X-ray photoemission spectroscopy, and Hall measurement. It is shown that ZnO TFTs have a superior performance in terms of the threshold voltage and field-effect mobility, when ZnO crystallites are more densely packed in the film. This is attributed to lower electrical resistivity and higher Hall mobility in a densely packed ZnO film. In the results of consecutive TFT operations, a positive shift in the threshold voltage occurred irrespective of the film morphology, but the morphological influence on the variation in the field-effect mobility was evident. The field-effect mobility in TFTs having a densely packed ZnO film increased continuously during consecutive TFT operations, which is in contrast to the mobility decrease observed in the less packed case. An analysis of the field-effect conductivities ascribes these results to the difference in energetic traps, which originate from structural defects in the ZnO films. Consequently, the morphological influence of solution-processed ZnO films on the TFT performance can be understood through the packing property of ZnO crystallites.

Morphological Influence of Solution-Processed Zinc Oxide Films on Electrical Characteristics of Thin-Film Transistors

PubMed Central

Lee, Hyeonju; Zhang, Xue; Hwang, Jaeeun; Park, Jaehoon

2016-01-01

We report on the morphological influence of solution-processed zinc oxide (ZnO) semiconductor films on the electrical characteristics of ZnO thin-film transistors (TFTs). Different film morphologies were produced by controlling the spin-coating condition of a precursor solution, and the ZnO films were analyzed using atomic force microscopy, X-ray diffraction, X-ray photoemission spectroscopy, and Hall measurement. It is shown that ZnO TFTs have a superior performance in terms of the threshold voltage and field-effect mobility, when ZnO crystallites are more densely packed in the film. This is attributed to lower electrical resistivity and higher Hall mobility in a densely packed ZnO film. In the results of consecutive TFT operations, a positive shift in the threshold voltage occurred irrespective of the film morphology, but the morphological influence on the variation in the field-effect mobility was evident. The field-effect mobility in TFTs having a densely packed ZnO film increased continuously during consecutive TFT operations, which is in contrast to the mobility decrease observed in the less packed case. An analysis of the field-effect conductivities ascribes these results to the difference in energetic traps, which originate from structural defects in the ZnO films. Consequently, the morphological influence of solution-processed ZnO films on the TFT performance can be understood through the packing property of ZnO crystallites. PMID:28773973

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

The fabrication and optical detection of a vertical structure organic thin film transistor

NASA Astrophysics Data System (ADS)

Zhang, H.; Wang, D.; Jia, P.

2014-03-01

Using vacuum evaporation and sputtering process, we prepared a photoelectric transistor with the vertical structure of Cu/copper phthalocyanine (CuPc)/Al/copper phthalocyanine (CuPc)/ITO. The material of CuPc semiconductor has good photosensitive properties. Excitons will be generated after the optical signal irradiation in semiconductor material, and then transformed into photocurrent under the built-in electric field formed by the Schottky contact, as the organic transistor drive current makes the output current enlarged. The results show that the I-V characteristics of transistor are unsaturated. When device was irradiated by full band (white) light, its working current significantly increased. In full band white light, when Vec = 3 V, the ratio of light and no light current was ranged for 2.9-6.4 times. Device in the absence of light current amplification coefficient is 16.5, and white light amplification coefficient is 98.65.

Effect of hydrogen on the device performance and stability characteristics of amorphous InGaZnO thin-film transistors with a SiO2/SiNx/SiO2 buffer

NASA Astrophysics Data System (ADS)

Han, Ki-Lim; Ok, Kyung-Chul; Cho, Hyeon-Su; Oh, Saeroonter; Park, Jin-Seong

2017-08-01

We investigate the influence of the multi-layered buffer consisting of SiO2/SiNx/SiO2 on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). The multi-layered buffer inhibits permeation of water from flexible plastic substrates and prevents degradation of overlying organic layers. The a-IGZO TFTs with a multi-layered buffer suffer less positive bias temperature stress instability compared to the device with a single SiO2 buffer layer after annealing at 250 °C. Hydrogen from the SiNx layer diffuses into the active layer and reduces electron trapping at loosely bound oxygen defects near the SiO2/a-IGZO interface. Quantitative analysis shows that a hydrogen density of 1.85 × 1021 cm-3 is beneficial to reliability. However, the multi-layered buffer device annealed at 350 °C resulted in conductive characteristics due to the excess carrier concentration from the higher hydrogen density of 2.12 × 1021 cm-3.

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

DOEpatents

Turner, Steven Richard

2006-12-26

A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

Throwing computing into reverse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frank, Michael P.

For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipatemore » that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.« less

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Graphene oxide-zinc oxide nanocomposite as channel layer for field effect transistors: effect of ZnO loading on field effect transport.

PubMed

Jilani, S Mahaboob; Banerji, Pallab

2014-10-08

The effects of ZnO on graphene oxide (GO)-ZnO nanocomposites are investigated to tune the conductivity in GO under field effect regime. Zinc oxides with different concentrations from 5 wt % to 25 wt % are used in a GO matrix to increase the conductivity in the composite. Six sets of field effect transistors with pristine GO and GO-ZnO as the channel layer at varying ZnO concentrations were fabricated. From the transfer characteristics, it is observed that GO exhibited an insulating behavior and the transistors with low ZnO (5 wt %) concentration initially showed p-type conductivity that changes to n-type with increases in ZnO loading. This n-type dominance in conductivity is a consequence of the transfer of electrons from ZnO to the GO matrix. From X-ray photoelectron spectroscopic measurements, it is observed that the progressive reduction in the C-OH oxygen group took place with increases in ZnO loading. Thus, from insulating GO to p- and then n-type, conductivity in GO could be achieved with reduction in the C-OH oxygen group by photocatalytic reduction of GO with varying degrees of ZnO. The restoration of sp(2) electron network in the GO matrix with the anchoring of ZnO nanostructures was observed from Raman spectra. From UV-visible spectra, the band gap in pristine GO was found to be 3.98 eV and reduced to 2.8 eV with increase in ZnO attachment.

Organic field-effect transistor with octadecyltrichlorosilane (OTS) self-assembled monolayers on gate oxide: effect of OTS quality

NASA Astrophysics Data System (ADS)

Devynck, M.; Tardy, P.; Wantz, G.; Nicolas, Y.; Hirsch, L.

2011-12-01

The effect of OTS (octadecyltrichlorosilane) Self-Assembled Monolayer (SAM) grafted on SiO2 gate dielectric of pentacene-based OFETs (organic field-effect transistors) is investigated. A significant improvement of the charge mobility (μ), up to 0.74 cm2/V s, is reached thanks to OTS treatment. However, in spite of improved performances, several drawbacks, such as an increase in mobility dispersion, substantial hysteresis in IDS-VG characteristics and high threshold voltages (VT), are observed. Changing solvent and deposition method turns out to have no significant effect on the mobility dispersion. A more accurate approach on the evolution of the mobility and the threshold voltage dispersion with OTS storage time highlights the effect of the OTS solution aging. Even if no difference is evidenced in the surface energy and roughness of the OTS layer, electrical characteristics exhibit considerable deterioration with OTS solution storage time. Using an "aged" OTS solution, opened under air, kept under argon and distilled before use, results in an increase of the IDS-VG hysteresis as well as in VT and in mobility dispersion. In comparison, fresh-OTS-based OFETs present a very low hysteresis, a threshold voltage close to 0 and a much lower mobility dispersion. It is demonstrated that aged OTS solutions contain impurities that are not removed by distillation process, which leads to a less densely packed layer causing interfacial charge traps thus deteriorated performances.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

Pursuing Polymer Dielectric Interfacial Effect in Organic Transistors for Photosensing Performance Optimization.

PubMed

Wu, Xiaohan; Chu, Yingli; Liu, Rui; Katz, Howard E; Huang, Jia

2017-12-01

Polymer dielectrics in organic field-effect transistors (OFETs) are essential to provide the devices with overall flexibility, stretchability, and printability and simultaneously introduce charge interaction on the interface with organic semiconductors (OSCs). The interfacial effect between various polymer dielectrics and OSCs significantly and intricately influences device performance. However, understanding of this effect is limited because the interface is buried and the interfacial charge interaction is difficult to stimulate and characterize. Here, this challenge is overcome by utilizing illumination to stimulate the interfacial effect in various OFETs and to characterize the responses of the effect by measuring photoinduced changes of the OFETs performances. This systemic investigation reveals the mechanism of the intricate interfacial effect in detail, and mathematically explains how the photosensitive OFETs characteristics are determined by parameters including polar group of the polymer dielectric and the OSC side chain. By utilizing this mechanism, performance of organic electronics can be precisely controlled and optimized. OFETs with strong interfacial effect can also show a signal additivity caused by repeated light pulses, which is applicable for photostimulated synapse emulator. Therefore, this work enlightens a detailed understanding on the interface effect and provides novel strategies for optimizing OFET photosensory performances.

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

PubMed Central

Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

2016-01-01

The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP. PMID:27924838

Inverter Circuits using Pentacene and ZnO Transistors

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2007-04-01

We report two types of integrated circuits based on a pentacene static-induction transistor (SIT), a pentacene thin-film transistor (TFT) and a zinc oxide (ZnO) TFT. The operating characteristics of a p-p inverter using pentacene SITs and a complementary inverter using a p-channel pentacene TFT and an n-channel ZnO TFT are described. The basic operation of logic circuits at a low voltage was achieved for the first time using the pentacene SIT inverter and complementary circuits with hybrid inorganic and organic materials. Furthermore, we describe the electrical properties of the ZnO films depending on sputtering conditions, and the complementary circuits using ZnO and pentacene TFTs.

Monolithically integrated two-dimensional arrays of optoelectronic threshold devices for neural network applications

NASA Technical Reports Server (NTRS)

Kim, J. H.; Katz, J.; Lin, S. H.; Psaltis, D.

1989-01-01

A monolithic 10 x 10 two-dimensional array of 'optical neuron' optoelectronic threshold elements for neural network applications has been designed, fabricated, and tested. Overall array dimensions are 5 x 5 mm, while the individual neurons, composed of an LED that is driven by a double-heterojunction bipolar transistor, are 250 x 250 microns. The overall integrated structure exhibited semiconductor-controlled rectifier characteristics, with a breakover voltage of 75 V and a reverse-breakdown voltage of 60 V; this is attributable to the parasitic p-n-p transistor which exists as a result of the sharing of the same n-AlGaAs collector between the transistors and the LED.

Carrier Conduction and Light Emission by Modification of Poly(alkylfluorene) Interface under Vacuum Ultraviolet Light Irradiation

NASA Astrophysics Data System (ADS)

Ohmori, Yutaka; Kajii, Hirotake; Terashima, Daiki; Kusumoto, Yusuke

2013-03-01

Organic field effect transistors (OFETs) have been extensively studied for flexible electronics. The characteristics of poly(9,9-dioctylfluorenyl-2,7-dyl) (F8) modified by thermal or light are strongly dependent on the carrier transport and optical characteristics. We investigate all solution-processed OFETs with Ag nano-ink as gate electrodes patterned by Vacuum Ultraviolet (VUV) (172 nm). Bi-layer gate insulators of amorphous fluoro-polymer CYTOP (Asahi Glass Corp.) and poly(methylmethacrylate) (PMMA) were used. Top-gate-type OFETs with ITO source/drain electrode utilizing F8 or poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT) as an active layer were fabricated, and investigated the carrier conduction and emission characteristic. Without VUV irradiation, both OFETs showed the ambipolar and light-emitting characteristics. On the other hand, F8 devices with VUV exhibited only p-type conduction. The quenching centers were generated in F8 layer by VUV irradiation, which are related to the electron trap sites at the interface. OFETs with F8BT showed both p- and n-type conduction even after VUV. F8BT suffers less damage by VUV and maintain light emission. Light emitting transistors were realized utilizing F8BT patterned by VUV irradiation. This research was partially supported financially by MEXT. The authors thank Harima Chemicals Inc. for providing Ag nano-ink.

High-performance multilayer WSe 2 field-effect transistors with carrier type control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Oyedele, Akinola; Zhang, Cheng

In this paper, high-performance multilayer WSe 2 field-effect transistor (FET) devices with carrier type control are demonstrated via thickness modulation and a remote oxygen plasma surface treatment. Carrier type control in multilayer WSe 2 FET devices with Cr/Au contacts is initially demonstrated by modulating the WSe 2 thickness. The carrier type evolves with increasing WSe 2 channel thickness, being p-type, ambipolar, and n-type at thicknesses <3, ~4, and >5 nm, respectively. The thickness-dependent carrier type is attributed to changes in the bandgap of WSe 2 as a function of the thickness and the carrier band offsets relative to the metalmore » contacts. Furthermore, we present a strong hole carrier doping effect via remote oxygen plasma treatment. It non-degenerately converts n-type characteristics into p-type and enhances field-effect hole mobility by three orders of magnitude. Finally, this work demonstrates progress towards the realization of high-performance multilayer WSe 2 FETs with carrier type control, potentially extendable to other transition metal dichalcogenides, for future electronic and optoelectronic applications.« less

High-performance multilayer WSe 2 field-effect transistors with carrier type control

DOE PAGES

Pudasaini, Pushpa Raj; Oyedele, Akinola; Zhang, Cheng; ...

2017-07-06

In this paper, high-performance multilayer WSe 2 field-effect transistor (FET) devices with carrier type control are demonstrated via thickness modulation and a remote oxygen plasma surface treatment. Carrier type control in multilayer WSe 2 FET devices with Cr/Au contacts is initially demonstrated by modulating the WSe 2 thickness. The carrier type evolves with increasing WSe 2 channel thickness, being p-type, ambipolar, and n-type at thicknesses <3, ~4, and >5 nm, respectively. The thickness-dependent carrier type is attributed to changes in the bandgap of WSe 2 as a function of the thickness and the carrier band offsets relative to the metalmore » contacts. Furthermore, we present a strong hole carrier doping effect via remote oxygen plasma treatment. It non-degenerately converts n-type characteristics into p-type and enhances field-effect hole mobility by three orders of magnitude. Finally, this work demonstrates progress towards the realization of high-performance multilayer WSe 2 FETs with carrier type control, potentially extendable to other transition metal dichalcogenides, for future electronic and optoelectronic applications.« less

Interface studies of N2 plasma-treated ZnSnO nanowire transistors using low-frequency noise measurements.

PubMed

Kim, Seongmin; Kim, Hwansoo; Janes, David B; Ju, Sanghyun

2013-08-02

Due to the large surface-to-volume ratio of nanowires, the quality of nanowire-insulator interfaces as well as the nanowire surface characteristics significantly influence the electrical characteristics of nanowire transistors (NWTs). To improve the electrical characteristics by doping or post-processing, it is important to evaluate the interface characteristics and stability of NWTs. In this study, we have synthesized ZnSnO (ZTO) nanowires using the chemical vapor deposition method, characterized the composition of ZTO nanowires using x-ray photoelectron spectroscopy, and fabricated ZTO NWTs. We have characterized the current-voltage characteristics and low-frequency noise of ZTO NWTs in order to investigate the effects of interface states on subthreshold slope (SS) and the noise before and after N2 plasma treatments. The as-fabricated device exhibited a SS of 0.29 V/dec and Hooge parameter of ~1.20 × 10(-2). Upon N2 plasma treatment with N2 gas flow rate of 40 sccm (20 sccm), the SS improved to 0.12 V/dec (0.21 V/dec) and the Hooge parameter decreased to ~4.99 × 10(-3) (8.14 × 10(-3)). The interface trap densities inferred from both SS and low-frequency noise decrease upon plasma treatment, with the highest flow rate yielding the smallest trap density. These results demonstrate that the N2 plasma treatment decreases the interface trap states and defects on ZTO nanowires, thereby enabling the fabrication of high-quality nanowire interfaces.

DC and small-signal physical models for the AlGaAs/GaAs high electron mobility transistor

NASA Technical Reports Server (NTRS)

Sarker, J. C.; Purviance, J. E.

1991-01-01

Analytical and numerical models are developed for the microwave small-signal performance, such as transconductance, gate-to-source capacitance, current gain cut-off frequency and the optimum cut-off frequency of the AlGaAs/GaAs High Electron Mobility Transistor (HEMT), in both normal and compressed transconductance regions. The validated I-V characteristics and the small-signal performances of four HeMT's are presented.

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

NASA Astrophysics Data System (ADS)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown to provide consistently accurate values for base sheet resistance for both Si- and SiGe-base transistors over a wide range of temperatures. A model for plasma-induced bandgap narrowing suitable for implementation in a numerical simulator has been developed. The appropriate method of incorporating this model in a drift -diffusion solver is described. The importance of including this model for low temperature simulation is demonstrated. With these models in place, the enhanced simulator has been used for evaluating and designing the Si- and SiGe-base bipolar transistors. Silicon-germanium heterojunction bipolar transistors offer significant performance and cost advantages over conventional technologies in the production of integrated circuits for communications, computer and transportation applications. Their high frequency performance at low cost, will find widespread use in the currently exploding wireless communication market. However, the high performance SiGe-base transistors are prone to have a low common-emitter breakdown voltage. In this dissertation, a modification in the collector design is proposed for improving the breakdown voltage without sacrificing the high frequency performance. A comprehensive simulation study of p-n-p SiGe-base transistors has been performed. Different figures of merit such as drive current, current gain, cut -off frequency and Early voltage were compared between a graded germanium profile and an abrupt germanium profile. The differences in the performance level between the two profiles diminishes as the base width is scaled down.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bolat, S., E-mail: bolat@ee.bilkent.edu.tr, E-mail: aokyay@ee.bilkent.edu.tr; Tekcan, B.; UNAM, National Nanotechnology Research Center, Bilkent University, Ankara 06800

We report GaN thin film transistors (TFT) with a thermal budget below 250 °C. GaN thin films are grown at 200 °C by hollow cathode plasma-assisted atomic layer deposition (HCPA-ALD). HCPA-ALD-based GaN thin films are found to have a polycrystalline wurtzite structure with an average crystallite size of 9.3 nm. TFTs with bottom gate configuration are fabricated with HCPA-ALD grown GaN channel layers. Fabricated TFTs exhibit n-type field effect characteristics. N-channel GaN TFTs demonstrated on-to-off ratios (I{sub ON}/I{sub OFF}) of 10{sup 3} and sub-threshold swing of 3.3 V/decade. The entire TFT device fabrication process temperature is below 250 °C, which is the lowest process temperaturemore » reported for GaN based transistors, so far.« less

Effects of the F4TCNQ-Doped Pentacene Interlayers on Performance Improvement of Top-Contact Pentacene-Based Organic Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Lin, Wei-Chun; Chang, Hsiang-Sheng; Lin, Yu-Zuo; Huang, Bohr-Ran

2016-01-01

In this paper, the top-contact (TC) pentacene-based organic thin-film transistor (OTFT) with a tetrafluorotetracyanoquinodimethane (F4TCNQ)-doped pentacene interlayer between the source/drain electrodes and the pentacene channel layer were fabricated using the co-evaporation method. Compared with a pentacene-based OTFT without an interlayer, OTFTs with an F4TCNQ:pentacene ratio of 1:1 showed considerably improved electrical characteristics. In addition, the dependence of the OTFT performance on the thickness of the F4TCNQ-doped pentacene interlayer is weaker than that on a Teflon interlayer. Therefore, a molecular doping-type F4TCNQ-doped pentacene interlayer is a suitable carrier injection layer that can improve the TC-OTFT performance and facilitate obtaining a stable process window. PMID:28787845

Atomtronics: Realizing the behavior of electronic components in ultracold atomic systems

NASA Astrophysics Data System (ADS)

Pepino, Ron

2007-06-01

Atomtronics focuses on creating an analogy of electronic devices and circuits with ultracold atoms. Such an analogy can come from the highly tunable band structure of ultracold neutral atoms trapped in optical lattices. Solely by tuning the parameters of the optical lattice, we demonstrate that conditions can be created that cause atoms in lattices to exhibit the same behavior as electrons moving through solid state media. We present our model and show how the atomtronic diode, field effect transistor, and bipolar junction transistor can all be realized. Our analogs of these fundamental components exhibit precisely-controlled atomic signal amplification, trimming, and switching (on/off) characteristics. In addition, the evolution of dynamics of the superfluid atomic currents within these systems is completely reversible. This implies a possible use of atomtronic systems in the development of quantum computational devices.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Improvement in negative bias illumination stress stability of In-Ga-Zn-O thin film transistors using HfO2 gate insulators by controlling atomic-layer-deposition conditions

NASA Astrophysics Data System (ADS)

Na, So-Yeong; Kim, Yeo-Myeong; Yoon, Da-Jeong; Yoon, Sung-Min

2017-12-01

The effects of atomic layer deposition (ALD) conditions for the HfO2 gate insulators (GI) on the device characteristics of the InGaZnO (IGZO) thin film transistors (TFTs) were investigated when the ALD temperature and Hf precursor purge time were varied to 200, 225, and 250 °C, and 15 and 30 s, respectively. The HfO2 thin films showed low leakage current density of 10-8 A cm-2, high dielectric constant of over 20, and smooth surface roughness at all ALD conditions. The IGZO TFTs using the HfO2 GIs showed good device characteristics such as a saturation mobility as high as 11 cm2 V-1 s-1, a subthreshold swing as low as 0.10 V/dec, and all the devices could be operated at a gate voltage as low as  ±3 V. While there were no marked differences in transfer characteristics and PBS stabilities among the fabricated devices, the NBIS instabilities could be improved by increasing the ALD temperature for the formation of HfO2 GIs by reducing the oxygen vacancies within the IGZO channel.

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Effect of the asymmetry of the coupling of the redox molecule to the electrodes in the one-level electrochemical bridged tunneling contact on the Coulomb blockade and the operation of molecular transistor.

PubMed

Medvedev, Igor G

2014-09-28

Effect of the asymmetry of the redox molecule (RM) coupling to the working electrodes on the Coulomb blockade and the operation of molecular transistor is considered under ambient conditions for the case of the non-adiabatic tunneling through the electrochemical contact having a one-level RM. The expressions for the tunnel current, the positions of the peaks of the tunnel current/overpotential dependencies, and their full widths at the half maximum are obtained for arbitrary values of the parameter d describing the coupling asymmetry of the tunneling contact and the effect of d on the different characteristics of the tunneling contact is studied. The tunnel current/overpotential and the differential conductance/bias voltage dependencies are calculated and interpreted. In particular, it is shown that the effect of the Coulomb blockade on the tunnel current and the differential conductance has a number of new features in the case of the large coupling asymmetry. It is also shown that, for rather large values of the solvent reorganization energy, the coupling asymmetry enhanced strongly amplification and rectification of the tunnel current in the most of the regions of the parameter space specifying the tunneling contact. The regions of the parameter space where both strong amplification and strong rectification take place are also revealed. The obtained results allow us to prove the possibility of the realization of the effective electrochemical transistor based on the one-level RM.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

A comparative study on electrical characteristics of 1-kV pnp and npn SiC bipolar junction transistors

NASA Astrophysics Data System (ADS)

Okuda, Takafumi; Kimoto, Tsunenobu; Suda, Jun

2018-04-01

We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.