Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Ordered polymer nanofibers enhance output brightness in bilayer light-emitting field-effect transistors.

PubMed

Hsu, Ben B Y; Seifter, Jason; Takacs, Christopher J; Zhong, Chengmei; Tseng, Hsin-Rong; Samuel, Ifor D W; Namdas, Ebinazar B; Bazan, Guillermo C; Huang, Fei; Cao, Yong; Heeger, Alan J

2013-03-26

Polymer light emitting field effect transistors are a class of light emitting devices that reveal interesting device physics. Device performance can be directly correlated to the most fundamental polymer science. Control over surface properties of the transistor dielectric can dramatically change the polymer morphology, introducing ordered phase. Electronic properties such as carrier mobility and injection efficiency on the interface can be promoted by ordered nanofibers in the polymer. Moreover, by controlling space charge in the polymer interface, the recombination zone can be spatially extended and thereby enhance the optical output.

Theoretical Investigation of Device Aspects of Semiconductor Superlattices.

DTIC Science & Technology

1983-09-01

n-i-p-i devices include bulk field effect transistors, ultrasensitive or ultrafast IR photodetectors , tunable light-emitting devices, and ultrafast...transistor4 ultrasensitive or ultrafast IR photodetectors , tunable light-emitt tg devices, and ultrafast optical modulators. Particularlylppealing...differential conductivity ( NDC ) ......................... 19 3.2.2. Spontaneous and stimulated FIR emission from interlayer transitions

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Liquid crystals for organic transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Hanna, Jun-ichi; Iino, Hiroaki

2016-09-01

Liquid crystals are a new type of organic semiconductors exhibiting molecular orientation in self-organizing manner, and have high potential for device applications. In fact, various device applications have been proposed so far, including photosensors, solar cells, light emitting diodes, field effect transistors, and so on.. However, device performance in those fabricated with liquid crystals is less than those of devices fabricated with conventional materials in spite of unique features of liquid crystals. Here we discuss how we can utilize the liquid crystallinity in organic transistors and how we can overcome conventional non-liquid crystalline organic transistor materials. Then, we demonstrate high performance organic transistors fabricated with a smectic E liquid crystal of Ph-BTBT-10, which show high mobility of over 10cm2/Vs and high thermal durability of over 200oC in OFETs fabricated with its spin-coated polycrystalline thin films.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Total-dose radiation effects data for semiconductor devices, volume 1. [radiation resistance of components for the Galileo Project

NASA Technical Reports Server (NTRS)

Price, W. E.; Martin, K. E.; Nichols, D. K.; Gauthier, M. K.; Brown, S. F.

1981-01-01

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. Data are presented by JPL for various NASA space programs on diodes, bipolar transistors, field effect transistors, silicon-controlled rectifiers, and optical devices. A vendor identification code list is included along with semiconductor device electrical parameter symbols and abbreviations.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

PubMed

Dey, Anil W; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik

2013-01-01

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Interaction of solid organic acids with carbon nanotube field effect transistors

NASA Astrophysics Data System (ADS)

Klinke, Christian; Afzali, Ali; Avouris, Phaedon

2006-10-01

A series of solid organic acids were used to p-dope carbon nanotubes. The extent of doping is shown to be dependent on the pKa value of the acids. Highly fluorinated carboxylic acids and sulfonic acids are very effective in shifting the threshold voltage and making carbon nanotube field effect transistors to be more p-type devices. Weaker acids like phosphonic or hydroxamic acids had less effect. The doping of the devices was accompanied by a reduction of the hysteresis in the transfer characteristics. In-solution doping survives standard fabrication processes and renders p-doped carbon nanotube field effect transistors with good transport characteristics.

Current crowding mediated large contact noise in graphene field-effect transistors

PubMed Central

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-01-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene–metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V−1 s−1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal–channel interface, which could be generic to two-dimensional material-based electronic devices. PMID:27929087

Current crowding mediated large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-12-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene-metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V-1 s-1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal-channel interface, which could be generic to two-dimensional material-based electronic devices.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS₂ Transistors.

PubMed

Ma, Jiyeon; Yoo, Geonwook

2018-09-01

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Transistor-based interface circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2007-02-13

Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

Triggering Mechanism for Neutron Induced Single-Event Burnout in Power Devices

NASA Astrophysics Data System (ADS)

Shoji, Tomoyuki; Nishida, Shuichi; Hamada, Kimimori

2013-04-01

Cosmic ray neutrons can trigger catastrophic failures in power devices. It has been reported that parasitic transistor action causes single-event burnout (SEB) in power metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). However, power diodes do not have an inherent parasitic transistor. In this paper, we describe the mechanism triggering SEB in power diodes for the first time using transient device simulation. Initially, generated electron-hole pairs created by incident recoil ions generate transient current, which increases the electron density in the vicinity of the n-/n+ boundary. The space charge effect of the carriers leads to an increase in the strength of the electric field at the n-/n+ boundary. Finally, the onset of impact ionization at the n-/n+ boundary can trigger SEB. Furthermore, this failure is closely related to diode secondary breakdown. It was clarified that the impact ionization at the n-/n+ boundary is a key point of the mechanism triggering SEB in power devices.

Total Dose Effects in Conventional Bipolar Transistors

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swift, G. W.; Rax, B. G.

1994-01-01

This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.

Analytic model for low-frequency noise in nanorod devices.

PubMed

Lee, Jungil; Yu, Byung Yong; Han, Ilki; Choi, Kyoung Jin; Ghibaudo, Gerard

2008-10-01

In this work analytic model for generation of excess low-frequency noise in nanorod devices such as field-effect transistors are developed. In back-gate field-effect transistors where most of the surface area of the nanorod is exposed to the ambient, the surface states could be the major noise source via random walk of electrons for the low-frequency or 1/f noise. In dual gate transistors, the interface states and oxide traps can compete with each other as the main noise source via random walk and tunneling, respectively.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Multimode Silicon Nanowire Transistors

PubMed Central

2014-01-01

The combined capabilities of both a nonplanar design and nonconventional carrier injection mechanisms are subject to recent scientific investigations to overcome the limitations of silicon metal oxide semiconductor field effect transistors. In this Letter, we present a multimode field effect transistors device using silicon nanowires that feature an axial n-type/intrinsic doping junction. A heterostructural device design is achieved by employing a self-aligned nickel-silicide source contact. The polymorph operation of the dual-gate device enabling the configuration of one p- and two n-type transistor modes is demonstrated. Not only the type but also the carrier injection mode can be altered by appropriate biasing of the two gate terminals or by inverting the drain bias. With a combined band-to-band and Schottky tunneling mechanism, in p-type mode a subthreshold swing as low as 143 mV/dec and an ON/OFF ratio of up to 104 is found. As the device operates in forward bias, a nonconventional tunneling transistor is realized, enabling an effective suppression of ambipolarity. Depending on the drain bias, two different n-type modes are distinguishable. The carrier injection is dominated by thermionic emission in forward bias with a maximum ON/OFF ratio of up to 107 whereas in reverse bias a Schottky tunneling mechanism dominates the carrier transport. PMID:25303290

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

NASA Astrophysics Data System (ADS)

Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

2018-05-01

An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

Mobility overestimation due to gated contacts in organic field-effect transistors

PubMed Central

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Healing of voids in the aluminum metallization of integrated circuit chips

NASA Technical Reports Server (NTRS)

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

1990-01-01

The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Hu, Zhaoying; Tulevski, George S.; Hannon, James B.; Afzali, Ali; Liehr, Michael; Park, Hongsik

2015-06-01

Carbon nanotubes (CNTs) have been widely studied as a channel material of scaled transistors for high-speed and low-power logic applications. In order to have sufficient drive current, it is widely assumed that CNT-based logic devices will have multiple CNTs in each channel. Understanding the effects of the number of CNTs on device performance can aid in the design of CNT field-effect transistors (CNTFETs). We have fabricated multi-CNT-channel CNTFETs with an 80-nm channel length using precise self-assembly methods. We describe compact statistical models and Monte Carlo simulations to analyze failure probability and the variability of the on-state current and threshold voltage. The results show that multichannel CNTFETs are more resilient to process variation and random environmental fluctuations than single-CNT devices.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

Material Synthesis and Device Aspects of Monolayer Tungsten Diselenide.

PubMed

Yao, Zihan; Liu, Jialun; Xu, Kai; Chow, Edmond K C; Zhu, Wenjuan

2018-03-27

In this paper, we investigate the synthesis of WSe 2 by chemical vapor deposition and study the current transport and device scaling of monolayer WSe 2 . We found that the device characteristics of the back-gated WSe 2 transistors with thick oxides are very sensitive to the applied drain bias, especially for transistors in the sub-micrometer regime. The threshold voltage, subthreshold swing, and extracted field-effect mobility vary with the applied drain bias. The output characteristics in the long-channel transistors show ohmic-like behavior, while that in the short-channel transistors show Schottky-like behavior. Our investigation reveals that these phenomena are caused by the drain-induced barrier lowering (short-channel effect). For back-gated WSe 2 transistors with 280 nm oxide, the short-channel effect appears when the channel length is shorter than 0.4 µm. This extremely long electrostatic scaling length is due to the thick back-gate oxides. In addition, we also found that the hydrogen flow rate and the amount of WO 3 precursor play an important role in the morphology of the WSe 2 . The hole mobility of the monolayer WSe 2 is limited by Columbic scattering below 250 K, while it is limited by phonon scattering above 250 K. These findings are very important for the synthesis of WSe 2 and accurate characterization of the electronic devices based on 2D materials.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

MOSFET's for Cryogenic Amplifiers

NASA Technical Reports Server (NTRS)

Dehaye, R.; Ventrice, C. A.

1987-01-01

Study seeks ways to build transistors that function effectively at liquid-helium temperatures. Report discusses physics of metaloxide/semiconductor field-effect transistors (MOSFET's) and performances of these devices at cryogenic temperatures. MOSFET's useful in highly sensitive cryogenic preamplifiers for infrared astronomy.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fabricating photoswitches and field-effect transistors from self-assembled tetra(2-isopropyl-5-methyphenoxy) copper phthalocyanines nanowires.

PubMed

Cheng, Chuanwei; Gao, Junshan; Xu, Guoyue; Zhang, Haiqian; Li, Yingying; Luo, Yan

2009-05-01

Tetra(2-isopropyl-5-methyphenoxy) copper phthalocyanine (CuPc) nanowires synthesized by a facile, low temperature self-assembled route, were incorporated into nano-devices: photoswitch and organic field-effect transistor. The devices were capable of switching on/off reversibly and fast by turning the 808 nm infrared light on/off. And the carrier mobility micro of CuPc nanowires incorporated in the devices was -0.02 cm2/V x s. The prelimenary results in this study show the potential application of metal phthalocyanine nanowires in low-cost fabrication of nano photo-electric devices.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

Near-Infrared to Visible Organic Upconversion Devices Based on Organic Light-Emitting Field Effect Transistors.

PubMed

Li, Dongwei; Hu, Yongsheng; Zhang, Nan; Lv, Ying; Lin, Jie; Guo, Xiaoyang; Fan, Yi; Luo, Jinsong; Liu, Xingyuan

2017-10-18

The near-infrared (NIR) to visible upconversion devices have attracted great attention because of their potential applications in the fields of night vision, medical imaging, and military security. Herein, a novel all-organic upconversion device architecture has been first proposed and developed by incorporating a NIR absorption layer between the carrier transport layer and the emission layer in heterostructured organic light-emitting field effect transistors (OLEFETs). The as-prepared devices show a typical photon-to-photon upconversion efficiency as high as 7% (maximum of 28.7% under low incident NIR power intensity) and millisecond-scale response time, which are the highest upconversion efficiency and one of the fastest response time among organic upconversion devices as referred to the previous reports up to now. The high upconversion performance mainly originates from the gain mechanism of field-effect transistor structures and the unique advantage of OLEFETs to balance between the photodetection and light emission. Meanwhile, the strategy of OLEFETs also offers the advantage of high integration so that no extra OLED is needed in the organic upconversion devices. The results would pave way for low-cost, flexible and portable organic upconversion devices with high efficiency and simplified processing.

Current control circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2005-03-15

Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Lead iodide perovskite light-emitting field-effect transistor

PubMed Central

Chin, Xin Yu; Cortecchia, Daniele; Yin, Jun; Bruno, Annalisa; Soci, Cesare

2015-01-01

Despite the widespread use of solution-processable hybrid organic–inorganic perovskites in photovoltaic and light-emitting applications, determination of their intrinsic charge transport parameters has been elusive due to the variability of film preparation and history-dependent device performance. Here we show that screening effects associated to ionic transport can be effectively eliminated by lowering the operating temperature of methylammonium lead iodide perovskite (CH3NH3PbI3) field-effect transistors. Field-effect carrier mobility is found to increase by almost two orders of magnitude below 200 K, consistent with phonon scattering-limited transport. Under balanced ambipolar carrier injection, gate-dependent electroluminescence is also observed from the transistor channel, with spectra revealing the tetragonal to orthorhombic phase transition. This demonstration of CH3NH3PbI3 light-emitting field-effect transistors provides intrinsic transport parameters to guide materials and solar cell optimization, and will drive the development of new electro-optic device concepts, such as gated light-emitting diodes and lasers operating at room temperature. PMID:26108967

Large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

Fluctuations in the electrical resistance at the interface of atomically thin materials and metals, or the contact noise, can adversely affect the device performance but remains largely unexplored. We have investigated contact noise in graphene field effect transistors of varying device geometry and contact configuration, with channel carrier mobility ranging from 5,000 to 80,000 cm2V-1s-1. A phenomenological model developed for contact noise due to current crowding for two dimensional conductors, shows a dominant contact contribution to the measured resistance noise in all graphene field effect transistors when measured in the two-probe or invasive four probe configurations, and surprisingly, also in nearly noninvasive four probe (Hall bar) configuration in the high mobility devices. We identify the fluctuating electrostatic environment of the metal-channel interface as the major source of contact noise, which could be generic to two dimensional material-based electronic devices. The work was financially supported by the Department of Science and Technology, India and Tokyo Electron Limited.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Linear conduction in N-type organic field effect transistors with nanometric channel lengths and graphene as electrodes

NASA Astrophysics Data System (ADS)

Chianese, F.; Candini, A.; Affronte, M.; Mishra, N.; Coletti, C.; Cassinese, A.

2018-05-01

In this work, we test graphene electrodes in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivative. By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied bias, in contrast with the supralinear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrode devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ˜140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current in short channel OFETs.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Johnson, R. Wayne; Askew, Ray; Bromstead, James; Weir, Bennett

1991-01-01

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Vacuum-processed polyethylene as a dielectric for low operating voltage organic field effect transistors

PubMed Central

Kanbur, Yasin; Irimia-Vladu, Mihai; Głowacki, Eric D.; Voss, Gundula; Baumgartner, Melanie; Schwabegger, Günther; Leonat, Lucia; Ullah, Mujeeb; Sarica, Hizir; Erten-Ela, Sule; Schwödiauer, Reinhard; Sitter, Helmut; Küçükyavuz, Zuhal; Bauer, Siegfried; Sariciftci, Niyazi Serdar

2012-01-01

We report on the fabrication and performance of vacuum-processed organic field effect transistors utilizing evaporated low-density polyethylene (LD-PE) as a dielectric layer. With C60 as the organic semiconductor, we demonstrate low operating voltage transistors with field effect mobilities in excess of 4 cm2/Vs. Devices with pentacene showed a mobility of 0.16 cm2/Vs. Devices using tyrian Purple as semiconductor show low-voltage ambipolar operation with equal electron and hole mobilities of ∼0.3 cm2/Vs. These devices demonstrate low hysteresis and operational stability over at least several months. Grazing-angle infrared spectroscopy of evaporated thin films shows that the structure of the polyethylene is similar to solution-cast films. We report also on the morphological and dielectric properties of these films. Our experiments demonstrate that polyethylene is a stable dielectric supporting both hole and electron channels. PMID:23483783

Theory and Device Modeling for Nano-Structured Transistor Channels

DTIC Science & Technology

2011-06-01

zinc oxide ( ZnO ) thin film transistors ( TFTs ) that contain nanocrystalline grains on the order of ~20nm. The authors of ref. 1 present results...problem in order to determine the threshold voltage. 15. SUBJECT TERMS nano-structured transistor , mesoscopic, zinc oxide , ZnO , field-effect...and R. Neidhard, “Microwave ZnO Thin - Film Transistors ”, IEEE Electron Dev. Lett. 29, 1024 (2008); doi: 10.1109/LED.2008.2001635.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Silicon Carbide Transistor For Detecting Hydrocarbon Gases

NASA Technical Reports Server (NTRS)

Shields, Virgil B.; Ryan, Margaret A.; Williams, Roger M.

1996-01-01

Proposed silicon carbide variable-potential insulated-gate field-effect transistor specially designed for use in measuring concentrations of hydrocarbon gases. Devices like this prove useful numerous automotive, industrial, aeronautical, and environmental monitoring applications.

Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naquin, Clint; Lee, Mark; Edwards, Hal

2014-11-24

Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility ofmore » exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.« less

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Proton irradiation effects on gallium nitride-based devices

NASA Astrophysics Data System (ADS)

Karmarkar, Aditya P.

Proton radiation effects on state-of-the-art gallium nitride-based devices were studied using Schottky diodes and high electron-mobility transistors. The device degradation was studied over a wide range of proton fluences. This study allowed for a correlation between proton irradiation effects between different types of devices and enhanced the understanding of the mechanisms responsible for radiation damage in GaN-based devices. Proton irradiation causes reduced carrier concentration and increased series resistance and ideality factor in Schottky diodes. 1.0-MeV protons cause greater degradation than 1.8-MeV protons because of their higher non-ionizing energy loss. The displacement damage in Schottky diodes recovers during annealing. High electron-mobility transistors exhibit extremely high radiation tolerance, continuing to perform up to a fluence of ˜1014 cm-2 of 1.8-MeV protons. Proton irradiation creates defect complexes in the thin-film structure. Decreased sheet carrier mobility due to increased carrier scattering and decreased sheet carrier density due to carrier removal by the defect centers are the primary damage mechanisms. Interface disorder at either the Schottky or the Ohmic contact plays a relatively unimportant part in overall device degradation in both Schottky diodes and high electron-mobility transistors.

Effect of direct current sputtering power on the behavior of amorphous indium-gallium-zinc-oxide thin-film transistors under negative bias illumination stress: A combination of experimental analyses and device simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jang, Jun Tae; Kim, Dong Myong; Choi, Sung-Jin

The effect of direct current sputtering power of indium-gallium-zinc-oxide (IGZO) on the performance and stability of the corresponding thin-film transistor devices was studied. The field effect mobility increases as the IGZO sputter power increases, at the expense of device reliability under negative bias illumination stress (NBIS). Device simulation based on the extracted sub-gap density of states indicates that the field effect mobility is improved as a result of the number of acceptor-like states decreasing. The degradation by NBIS is suggested to be induced by the formation of peroxides in IGZO rather than charge trapping.

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Modified Reference SPS with Solid State Transmitting Antenna

NASA Technical Reports Server (NTRS)

Woodcock, G. R.; Sperber, B. R.

1980-01-01

The development of solid state microwave power amplifiers for a solar power satellite transmitting antenna is discussed. State-of-the-art power-added efficiency, gain, and single device power of various microwave solid state devices are compared. The GaAs field effect transistors and the Si-bipolar transistors appear potentially feasible for solar power satellite use. The integration of solid state devices into antenna array elements is examined and issues concerning antenna integration and consequent satellite configurations are examined.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Scattering effects on the performance of carbon nanotube field effect transistor in a compact model

NASA Astrophysics Data System (ADS)

Hamieh, S. D.; Desgreys, P.; Naviner, J. F.

2010-01-01

Carbon nanotube field-effect transistors (CNTFET) are being extensively studied as possible successors to CMOS. Device simulators have been developed to estimate their performance in sub-10-nm and device structures have been fabricated. In this work, a new compact model of single-walled semiconducting CNTFET is proposed implementing the calculation of energy conduction sub-band minima and the treatment of scattering effects through energy shift in CNTFET. The developed model has been used to simulate I-V characteristics using VHDL-AMS simulator.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Inert gas annealing effect in solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Lee, Seungwoon; Jeong, Jaewook

2017-08-01

In this paper, the annealing effect of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs), under ambient He (He-device), is systematically analyzed by comparison with those under ambient O2 (O2-device) and N2 (N2-device), respectively. The He-device shows high field-effect mobility and low subthreshold slope owing to the minimization of the ambient effect. The degradation of the O2- and N2-device performances originate from their respective deep acceptor-like and shallow donor-like characteristics, which can be verified by comparison with the He-device. However, the three devices show similar threshold voltage instability under prolonged positive bias stress due to the effect of excess oxygen. Therefore, annealing in ambient He is the most suitable method for the fabrication of reference TFTs to study the various effects of the ambient during the annealing process in solution-processed a-IGZO TFTs.

Extended-gate organic field-effect transistor for the detection of histamine in water

NASA Astrophysics Data System (ADS)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

Polymer-based doping control for performance enhancement of wet-processed short-channel CNTFETs

NASA Astrophysics Data System (ADS)

Hartmann, Martin; Schubel, René; Claus, Martin; Jordan, Rainer; Schulz, Stefan E.; Hermann, Sascha

2018-01-01

The electrical transport properties of short-channel transistors based on single-walled carbon nanotubes (CNT) are significantly affected by bundling along with solution processing. We report that especially high off currents of CNT transistors are not only related to the incorporation of metallic CNTs but also to the incorporation of CNT bundles. By applying device passivation with poly(4-vinylpyridine), the impact of CNT bundling on the device performance can be strongly reduced due to increased gate efficiency as well as reduced oxygen and water-induced p-type doping, boosting essential field-effect transistor performance parameters by several orders of magnitude. Moreover, this passivation approach allows the hysteresis and threshold voltage of CNT transistors to be tuned.

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui

2014-01-01

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (-27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

Ferroelectric-Driven Performance Enhancement of Graphene Field-Effect Transistors Based on Vertical Tunneling Heterostructures.

PubMed

Yuan, Shuoguo; Yang, Zhibin; Xie, Chao; Yan, Feng; Dai, Jiyan; Lau, Shu Ping; Chan, Helen L W; Hao, Jianhua

2016-12-01

A vertical graphene heterostructure field-effect transistor (VGHFET) using an ultrathin ferroelectric film as a tunnel barrier is developed. The heterostructure is capable of providing new degrees of tunability and functionality via coupling between the ferroelectricity and the tunnel current of the VGHFET, which results in a high-performance device. The results pave the way for developing novel atomic-scale 2D heterostructures and devices. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Removing the current-limit of vertical organic field effect transistors

NASA Astrophysics Data System (ADS)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

Use of cermet thin film resistors with nitride passivated metal insulator field effect transistor

NASA Technical Reports Server (NTRS)

Brown, G. A.; Harrap, V.

1971-01-01

Film deposition of cermet resistors on same chip with metal nitride oxide silicon field effect transistors permits protection of contamination sensitive active devices from contaminants produced in cermet deposition and definition processes. Additional advantages include lower cost, greater reliability, and space savings.

Large scale integration of graphene transistors for potential applications in the back end of the line

NASA Astrophysics Data System (ADS)

Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

2015-06-01

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Patterning technology for solution-processed organic crystal field-effect transistors

PubMed Central

Li, Yun; Sun, Huabin; Shi, Yi; Tsukagoshi, Kazuhito

2014-01-01

Organic field-effect transistors (OFETs) are fundamental building blocks for various state-of-the-art electronic devices. Solution-processed organic crystals are appreciable materials for these applications because they facilitate large-scale, low-cost fabrication of devices with high performance. Patterning organic crystal transistors into well-defined geometric features is necessary to develop these crystals into practical semiconductors. This review provides an update on recentdevelopment in patterning technology for solution-processed organic crystals and their applications in field-effect transistors. Typical demonstrations are discussed and examined. In particular, our latest research progress on the spin-coating technique from mixture solutions is presented as a promising method to efficiently produce large organic semiconducting crystals on various substrates for high-performance OFETs. This solution-based process also has other excellent advantages, such as phase separation for self-assembled interfaces via one-step spin-coating, self-flattening of rough interfaces, and in situ purification that eliminates the impurity influences. Furthermore, recommendations for future perspectives are presented, and key issues for further development are discussed. PMID:27877656

Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Tang, Fengzai; Lee, Kean B.; Guiney, Ivor; Frentrup, Martin; Barnard, Jonathan S.; Divitini, Giorgio; Zaidi, Zaffar H.; Martin, Tomas L.; Bagot, Paul A.; Moody, Michael P.; Humphreys, Colin J.; Houston, Peter A.; Oliver, Rachel A.; Wallis, David J.

2018-01-01

We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

A Probe for Measuring Spacecraft Surface Potentials Using a Direct-Gate Field Effect Transistor.

DTIC Science & Technology

1983-09-30

SURFACE POTENTIALS USING A DIRECT-GATE FIELD EFFECT TRANSISTOR Mark N. Horenstein Anton Havretic Trustees of Boston University 881 Commonwealth Avenue...1933 Transistor 6. PERFORMING ORG. REPORT NUMBER 7. AUTHOR(s) S. CONTRACT OR GRANT NUMBER(&) ’_5 Mark N. Horenstein Anton Mavretic F19628-82-K-00 34...at AFGL. These tests can be considered the bench mark tests for device performance, with all elements of the monitoring system optimized to eliminate

Integration of Organic Electrochemical and Field-Effect Transistors for Ultraflexible, High Temporal Resolution Electrophysiology Arrays.

PubMed

Lee, Wonryung; Kim, Dongmin; Rivnay, Jonathan; Matsuhisa, Naoji; Lonjaret, Thomas; Yokota, Tomoyuki; Yawo, Hiromu; Sekino, Masaki; Malliaras, George G; Someya, Takao

2016-11-01

Integration of organic electrochemical transistors and organic field-effect transistors is successfully realized on a 600 nm thick parylene film toward an electrophysiology array. A single cell of an integrated device and a 2 × 2 electrophysiology array succeed in detecting electromyogram with local stimulation of the motor nerve bundle of a transgenic rat by a laser pulse. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Organic transistors for electrophysiology (Presentation Recording)

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan

2015-10-01

Efficient local transduction of biological signals is of critical importance for mapping brain activity and diagnosing pathological conditions. Traditional devices used to record electrophysiological signals are passive electrodes that require (pre)amplification with downstream electronics. Organic electrochemical transistors (OECTs) that utilize conducting polymer films as the channel have shown considerable promise as amplifying transducers due to their stability in aqueous conditions and high transconductance (>3 mS). The materials properties and physics of such transistors, however, remains largely unexplored thus limiting their potential. Here we show that the uptake of ionic charge from an electrolyte into a poly(3,4-ethylenedioxythiophene) doped with polystyrene sulfonate (PEDOT:PSS) OECT channel leads to a dependence of the effective capacitance on the entire volume of the film. Subsequently, device transconductance and time response vary with channel thickness, a defining characteristic that differentiates OECTs from field effect transistors, and provides a new degree of freedom for device engineering. Using this understanding we tailor OECTs for a variety of low (1-100 Hz) and high (1-10 kHz) frequency applications, including human electroencephalography, where high transconductance devices impart richer signal content without the need for additional amplification circuitry. We also show that the materials figure of merit OECTs is the product of hole mobility and volumetric capacitance of the channel, leading to design rules for novel high performance materials.

Long-term stability assessment of AlGaN/GaN field effect transistors modified with peptides: Device characteristics vs. surface properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rohrbaugh, Nathaniel; Bryan, Isaac; Bryan, Zachary

AlGaN/GaN Field Effect Transistors (FETs) are promising biosensing devices. Functionalization of these devices is explored in this study using an in situ approach with phosphoric acid etchant and a phosphonic acid derivative. Devices are terminated on peptides and soaked in water for up to 168 hrs to examine FETs for both device responses and surface chemistry changes. Measurements demonstrated threshold voltage shifting after the functionalization and soaking processes, but demonstrated stable FET behavior throughout. X-ray photoelectron spectroscopy and atomic force microscopy confirmed peptides attachment to device surfaces before and after water soaking. Results of this work point to the stabilitymore » of peptide coated functionalized AlGaN/GaN devices in solution and support further research of these devices as disposable, long term, in situ biosensors.« less

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

High-speed low-power photonic transistor devices based on optically-controlled gain or absorption to affect optical interference.

PubMed

Huang, Yingyan; Ho, Seng-Tiong

2008-10-13

We show that a photonic transistor device can be realized via the manipulation of optical interference by optically controlled gain or absorption in novel ways, resulting in efficient transistor signal gain and switching action. Exemplary devices illustrate two complementary device types with high operating speed, microm size, microW switching power, and switching gain. They can act in tandem to provide a wide variety of operations including wavelength conversion, pulse regeneration, and logical operations. These devices could have a Transistor Figure-of-Merits >10(5) times higher than current chi((3)) approaches and are highly attractive.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Single event burnout sensitivity of embedded field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koga, R.; Crain, S.H.; Crawford, K.B.

Observations of single event burnout (SEB) in embedded field effect transistors are reported. Both SEB and other single event effects are presented for several pulse width modulation and high frequency devices. The microscope has been employed to locate and to investigate the damaged areas. A model of the damage mechanism based on the results so obtained is described.

Single event burnout sensitivity of embedded field effect transistors

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, S. H.; Crawford, K. B.; Yu, P.; Gordon, M. J.

1999-12-01

Observations of single event burnout (SEB) in embedded field effect transistors are reported. Both SEB and other single event effects are presented for several pulse width modulation and high frequency devices. The microscope has been employed to locate and to investigate the damaged areas. A model of the damage mechanism based on the results so obtained is described.

Modelling switching-time effects in high-frequency power conditioning networks

NASA Technical Reports Server (NTRS)

Owen, H. A.; Sloane, T. H.; Rimer, B. H.; Wilson, T. G.

1979-01-01

Power transistor networks which switch large currents in highly inductive environments are beginning to find application in the hundred kilohertz switching frequency range. Recent developments in the fabrication of metal-oxide-semiconductor field-effect transistors in the power device category have enhanced the movement toward higher switching frequencies. Models for switching devices and of the circuits in which they are imbedded are required to properly characterize the mechanisms responsible for turning on and turning off effects. Easily interpreted results in the form of oscilloscope-like plots assist in understanding the effects of parametric studies using topology oriented computer-aided analysis methods.

Chemical free device fabrication of two dimensional van der Waals materials based transistors by using one-off stamping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Young Tack, E-mail: 023273@kist.re.kr, E-mail: stunalren@gmail.com; Choi, Won Kook; Materials and Life Science Research Division, Korea Institute of Science and Technology

We report on a chemical free one-off imprinting method to fabricate two dimensional (2D) van der Waals (vdWs) materials based transistors. Such one-off imprinting technique is the simplest and effective way to prevent unintentional chemical reaction or damage of 2D vdWs active channel during device fabrication process. 2D MoS{sub 2} nanosheets based transistors with a hexagonal-boron-nitride (h-BN) passivation layer, prepared by one-off imprinting, show negligible variations of transfer characteristics after chemical vapor deposition process. In addition, this method enables the fabrication of all 2D MoS{sub 2} transistors consisting of h-BN gate insulator, and graphene source/drain and gate electrodes without anymore » chemical damage.« less

Tunable SnSe2 /WSe2 Heterostructure Tunneling Field Effect Transistor.

PubMed

Yan, Xiao; Liu, Chunsen; Li, Chao; Bao, Wenzhong; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2017-09-01

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band-edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe 2 /WSe 2 van der Waals heterostructures with SnSe 2 as the p-layer and WSe 2 as the n-layer. The energy band alignment changes from a staggered gap band offset (type-II) to a broken gap (type-III) when changing the negative back-gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10 4 ) or an n-type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec -1 for exceeding two decades of drain current with a minimum of 37 mV dec -1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I ON /I OFF ratio of the transfer characteristics is >10 6 , accompanying a high ON current >10 -5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low-power consumption devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Cryogenetically Cooled Field Effect Transistors for Low-Noise Systems

NASA Technical Reports Server (NTRS)

Wollack, Edward J.; Rabin, Douglas M. (Technical Monitor)

2002-01-01

Recent tends in the design, fabrication and use of High-Electron-Mobility-Transistors (HEMT) in low noise amplifiers are reviewed. Systems employing these devices have achieved the lowest system noise for wavelengths greater than three millimeters with relatively modest cryogenic cooling requirements in a variety of ground and space based applications. System requirements which arise in employing such devices in imaging applications are contrasted with other leading coherent detector candidates at microwave wavelengths. Fundamental and practical limitations which arise in the context of microwave application of field effect devices at cryogenic temperatures will be discussed from a component and systems point of view.

Cryogenically Cooled Field Effect Transistors for Low-Noise Systems

NASA Technical Reports Server (NTRS)

Wollack, Edward J.

2002-01-01

Recent tends in the design, fabrication and use of High-Electron-Mobility-Transistors (HEMT) in low noise amplifiers are reviewed. Systems employing these devices have achieved the lowest system noise for wavelengths greater than three millimeters with relatively modest cryogenic cooling requirements in a variety of ground and space based applications. System requirements which arise in employing such devices in imaging applications are contrasted with other leading coherent detector candidates at microwave wavelengths. Fundamental and practical limitations which arise in the context of microwave application of field effect devices at cryogenic temperatures will be discussed from a component and systems point of view.

GRC-2011-C-03754

NASA Image and Video Library

2007-09-26

Molecular Electronics; Polymeric Films; Two-Terminal and Three-Terminal Devices Intended for the Development and/or Demonstration of Molecular Electronics Devices such as Field Effect Transistors, FETs

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Flexible thin-film transistors on plastic substrate at room temperature.

PubMed

Han, Dedong; Wang, Wei; Cai, Jian; Wang, Liangliang; Ren, Yicheng; Wang, Yi; Zhang, Shengdong

2013-07-01

We have fabricated flexible thin-film transistors (TFTs) on plastic substrates using Aluminum-doped ZnO (AZO) as an active channel layer at room temperature. The AZO-TFTs showed n-channel device characteristics and operated in enhancement mode. The device shows a threshold voltage of 1.3 V, an on/off ratio of 2.7 x 10(7), a field effect mobility of 21.3 cm2/V x s, a subthreshold swing of 0.23 V/decade, and the off current of less than 10(-12) A at room temperature. Recently, the flexible displays have become a very hot topic. Flexible thin film transistors are key devices for realizing flexible displays. We have investigated AZO-TFT on flexible plastic substrate, and high performance flexible TFTs have been obtained.

Fully-printed high-performance organic thin-film transistors and circuitry on one-micron-thick polymer films

NASA Astrophysics Data System (ADS)

Fukuda, Kenjiro; Takeda, Yasunori; Yoshimura, Yudai; Shiwaku, Rei; Tran, Lam Truc; Sekine, Tomohito; Mizukami, Makoto; Kumaki, Daisuke; Tokito, Shizuo

2014-06-01

Thin, ultra-flexible devices that can be manufactured in a process that covers a large area will be essential to realizing low-cost, wearable electronic applications including foldable displays and medical sensors. The printing technology will be instrumental in fabricating these novel electronic devices and circuits; however, attaining fully printed devices on ultra-flexible films in large areas has typically been a challenge. Here we report on fully printed organic thin-film transistor devices and circuits fabricated on 1-μm-thick parylene-C films with high field-effect mobility (1.0 cm2 V-1 s-1) and fast operating speeds (about 1 ms) at low operating voltages. The devices were extremely light (2 g m-2) and exhibited excellent mechanical stability. The devices remained operational even under 50% compressive strain without significant changes in their performance. These results represent significant progress in the fabrication of fully printed organic thin-film transistor devices and circuits for use in unobtrusive electronic applications such as wearable sensors.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

PubMed Central

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Vertical GaN Devices for Power Electronics in Extreme Environments

DTIC Science & Technology

2016-03-31

electronics applications. In this paper vertical p-n diodes and transistors fabricated on pseudo bulk low defect density (104 to 106 cm-2) GaN substrates are...holes in p-GaN has deleterious effect on p-n junction behavior (Fig. 2), p-GaN contacts, and channel control in junction field-effect transistors at...and transistors ) utilizing p-n junctions are suitable for most practical applications including automotive (210K < T < 423K) but may have limitations

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2017-03-01

energy levels on a GaN-on-silicon high electron mobility transistor was created. Based on physical results of 2.0-MeV protons irradiation to fluence...and the physical device at 2.0-MeV proton irradiation , predictions were made for 5.0, 10.0, 20.0 and 40.0-MeV proton irradiation . The model generally...nitride, high electron mobility transistor, electronics, 2 MeV proton irradiation , radiation effects 15. NUMBER OF PAGES 87 16. PRICE CODE 17. SECURITY

Heterogeneous Integration of Epitaxial Ge on Si using AlAs/GaAs Buffer Architecture: Suitability for Low-power Fin Field-Effect Transistors

PubMed Central

Hudait, Mantu K.; Clavel, Michael; Goley, Patrick; Jain, Nikhil; Zhu, Yan

2014-01-01

Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370 cm2/Vs at 290 K and 457 cm2/Vs at 90 K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications. PMID:25376723

Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Anh Khoa Augustin; IMEC, 75 Kapeldreef, B-3001 Leuven; Pourtois, Geoffrey

2016-01-25

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, andmore » sets the limit of the scaling in future transistor designs.« less

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene-carbon nanotube transistors

NASA Astrophysics Data System (ADS)

Chae, Sang Hoon; Yu, Woo Jong; Bae, Jung Jun; Duong, Dinh Loc; Perello, David; Jeong, Hye Yun; Ta, Quang Huy; Ly, Thuc Hue; Vu, Quoc An; Yun, Minhee; Duan, Xiangfeng; Lee, Young Hee

2013-05-01

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10-13 A. The resulting devices exhibited an excellent on/off ratio of ~105, a high mobility of ~40 cm2 V-1 s-1 and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Photosensitive graphene transistors.

PubMed

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Accelerated life testing and temperature dependence of device characteristics in GaAs CHFET devices

NASA Technical Reports Server (NTRS)

Gallegos, M.; Leon, R.; Vu, D. T.; Okuno, J.; Johnson, A. S.

2002-01-01

Accelerated life testing of GaAs complementary heterojunction field effect transistors (CHFET) was carried out. Temperature dependence of single and synchronous rectifier CHFET device characteristics were also obtained.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

Improving the radiation hardness of graphene field effect transistors

DOE PAGES

Alexandrou, Konstantinos; Masurkar, Amrita; Edrees, Hassan; ...

2016-10-11

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. In this paper, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. Finally,more » we believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.« less

Improving the radiation hardness of graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alexandrou, Konstantinos; Masurkar, Amrita; Edrees, Hassan

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. In this paper, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. Finally,more » we believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.« less

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2014-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2011-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Planar-Processed Polymer Transistors.

PubMed

Xu, Yong; Sun, Huabin; Shin, Eul-Yong; Lin, Yen-Fu; Li, Wenwu; Noh, Yong-Young

2016-10-01

Planar-processed polymer transistors are proposed where the effective charge injection and the split unipolar charge transport are all on the top surface of the polymer film, showing ideal device characteristics with unparalleled performance. This technique provides a great solution to the problem of fabrication limitations, the ambiguous operating principle, and the performance improvements in practical applications of conjugated-polymer transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

PubMed

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Comparison of effect of 5 MeV proton and Co-60 gamma irradiation on silicon NPN rf power transistors and N-channel depletion MOSFETs

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Pradeep, T. M.; Hegde, Vinayakprasanna N.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Bhushan, K. G.

2017-12-01

NPN transistors and N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 5 MeV protons and 60Co gamma radiation in the dose ranging from 1 Mrad(Si) to 100 Mrad(Si). The different electrical characteristics of the NPN transistor such as Gummel characteristics, excess base current (ΔIB), dc current gain (hFE), transconductance (gm), displacement damage factor (K) and output characteristics were studied as a function of total dose. The different electrical characteristics of N-channel MOSFETs such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (µ) and drain saturation current (IDSat) were studied systematically before and after irradiation in the same dose ranges. A considerable increase in the base current (IB) and decrease in the hFE, gm and collector saturation current (ICSat) were observed after irradiation in the case of the NPN transistor. In the N-channel MOSFETs, the ΔNit and ΔNot were found to increase and Vth, gm, µ and IDSat were found to decrease with increase in the radiation dose. The 5 MeV proton irradiation results of both the NPN transistor and N-channel MOSFETs were compared with 60Co gamma-irradiated devices in the same dose ranges. It was observed that the degradation in 5 MeV proton-irradiated devices is more when compared with the 60Co gamma-irradiated devices at higher total doses.

75 FR 30794 - Notice of Intent To Grant Exclusive Patent License; AmberWave Systems Corporation

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-02

..., power transistor devices, and power devices in the United States, the Government-owned inventions... amplifiers, radio frequency power transistor devices, and power devices and their use for the fabrication of...

Room Temperature Silicene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Akinwande, Deji

Silicene, a buckled Si analogue of graphene, holds significant promise for future electronics beyond traditional CMOS. In our predefined experiments via encapsulated delamination with native electrodes approach, silicene devices exhibit an ambipolar charge transport behavior, corroborating theories on Dirac band in Ag-free silicene. Monolayer silicene device has extracted field-effect mobility within the theoretical expectation and ON/OFF ratio greater than monolayer graphene, while multilayer silicene devices show decreased mobility and gate modulation. Air-stability of silicene devices depends on the number of layers of silicene and intrinsic material structure determined by growth temperature. Few or multi-layer silicene devices maintain their ambipolar behavior for days in contrast to minutes time scale for monolayer counterparts under similar conditions. Multilayer silicene grown at different temperatures below 300oC possess different intrinsic structures and yield different electrical property and air-stability. This work suggests a practical prospect to enable more air-stable silicene devices with layer and growth condition control, which can be leveraged for other air-sensitive 2D materials. In addition, we describe quantum and classical transistor device concepts based on silicene and related buckled materials that exploit the 2D topological insulating phenomenon. The transistor device physics offer the potential for ballistic transport that is robust against scattering and can be employed for both charge and spin transport. This work was supported by the ARO.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Intrinsically stretchable and transparent thin-film transistors based on printable silver nanowires, carbon nanotubes and an elastomeric dielectric

PubMed Central

Liang, Jiajie; Li, Lu; Chen, Dustin; Hajagos, Tibor; Ren, Zhi; Chou, Shu-Yu; Hu, Wei; Pei, Qibing

2015-01-01

Thin-film field-effect transistor is a fundamental component behind various mordern electronics. The development of stretchable electronics poses fundamental challenges in developing new electronic materials for stretchable thin-film transistors that are mechanically compliant and solution processable. Here we report the fabrication of transparent thin-film transistors that behave like an elastomer film. The entire fabrication is carried out by solution-based techniques, and the resulting devices exhibit a mobility of ∼30 cm2 V−1 s−1, on/off ratio of 103–104, switching current >100 μA, transconductance >50 μS and relative low operating voltages. The devices can be stretched by up to 50% strain and subjected to 500 cycles of repeated stretching to 20% strain without significant loss in electrical property. The thin-film transistors are also used to drive organic light-emitting diodes. The approach and results represent an important progress toward the development of stretchable active-matrix displays. PMID:26173436

Germanium Based Field-Effect Transistors: Challenges and Opportunities

PubMed Central

Goley, Patrick S.; Hudait, Mantu K.

2014-01-01

The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed. PMID:28788569

Thermal-noise suppression in nano-scale Si field-effect transistors by feedback control based on single-electron detection

NASA Astrophysics Data System (ADS)

Chida, Kensaku; Nishiguchi, Katsuhiko; Yamahata, Gento; Tanaka, Hirotaka; Fujiwara, Akira

2015-08-01

We perform feedback (FB) control for suppressing thermal fluctuation in the number of electrons in a silicon single-electron (SE) device composed of a small transistor and capacitor. SEs enter and leave the capacitor via the transistor randomly at thermal equilibrium, which is monitored in real time using a high-charge-sensitivity detector. In order to suppress such random motion or thermal fluctuation of the electrons, SEs are injected and removed using the transistor according to the monitored change in the number of electrons in the capacitor, which is exactly the FB control. As a result, thermal fluctuation in the number of electrons in a SE device is suppressed by 60%, which corresponds to the so-called FB cooling from 300 to 110 K. Moreover, a thermodynamics analysis of this FB cooling reveals that entropy in the capacitor is reduced and the device is at non-equilibrium; i.e., the free energy of the device increases. Since this entropy reduction originates from information about the electrons' motion monitored by the detector, our results by the FB control represent one type of information-to-energy conversion.

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

Intrinsically stretchable and healable semiconducting polymer for organic transistors

NASA Astrophysics Data System (ADS)

Oh, Jin Young; Rondeau-Gagné, Simon; Chiu, Yu-Cheng; Chortos, Alex; Lissel, Franziska; Wang, Ging-Ji Nathan; Schroeder, Bob C.; Kurosawa, Tadanori; Lopez, Jeffrey; Katsumata, Toru; Xu, Jie; Zhu, Chenxin; Gu, Xiaodan; Bae, Won-Gyu; Kim, Yeongin; Jin, Lihua; Chung, Jong Won; Tok, Jeffrey B.-H.; Bao, Zhenan

2016-11-01

Thin-film field-effect transistors are essential elements of stretchable electronic devices for wearable electronics. All of the materials and components of such transistors need to be stretchable and mechanically robust. Although there has been recent progress towards stretchable conductors, the realization of stretchable semiconductors has focused mainly on strain-accommodating engineering of materials, or blending of nanofibres or nanowires into elastomers. An alternative approach relies on using semiconductors that are intrinsically stretchable, so that they can be fabricated using standard processing methods. Molecular stretchability can be enhanced when conjugated polymers, containing modified side-chains and segmented backbones, are infused with more flexible molecular building blocks. Here we present a design concept for stretchable semiconducting polymers, which involves introducing chemical moieties to promote dynamic non-covalent crosslinking of the conjugated polymers. These non-covalent crosslinking moieties are able to undergo an energy dissipation mechanism through breakage of bonds when strain is applied, while retaining high charge transport abilities. As a result, our polymer is able to recover its high field-effect mobility performance (more than 1 square centimetre per volt per second) even after a hundred cycles at 100 per cent applied strain. Organic thin-film field-effect transistors fabricated from these materials exhibited mobility as high as 1.3 square centimetres per volt per second and a high on/off current ratio exceeding a million. The field-effect mobility remained as high as 1.12 square centimetres per volt per second at 100 per cent strain along the direction perpendicular to the strain. The field-effect mobility of damaged devices can be almost fully recovered after a solvent and thermal healing treatment. Finally, we successfully fabricated a skin-inspired stretchable organic transistor operating under deformations that might be expected in a wearable device.

Intrinsically stretchable and healable semiconducting polymer for organic transistors.

PubMed

Oh, Jin Young; Rondeau-Gagné, Simon; Chiu, Yu-Cheng; Chortos, Alex; Lissel, Franziska; Wang, Ging-Ji Nathan; Schroeder, Bob C; Kurosawa, Tadanori; Lopez, Jeffrey; Katsumata, Toru; Xu, Jie; Zhu, Chenxin; Gu, Xiaodan; Bae, Won-Gyu; Kim, Yeongin; Jin, Lihua; Chung, Jong Won; Tok, Jeffrey B-H; Bao, Zhenan

2016-11-17

Thin-film field-effect transistors are essential elements of stretchable electronic devices for wearable electronics. All of the materials and components of such transistors need to be stretchable and mechanically robust. Although there has been recent progress towards stretchable conductors, the realization of stretchable semiconductors has focused mainly on strain-accommodating engineering of materials, or blending of nanofibres or nanowires into elastomers. An alternative approach relies on using semiconductors that are intrinsically stretchable, so that they can be fabricated using standard processing methods. Molecular stretchability can be enhanced when conjugated polymers, containing modified side-chains and segmented backbones, are infused with more flexible molecular building blocks. Here we present a design concept for stretchable semiconducting polymers, which involves introducing chemical moieties to promote dynamic non-covalent crosslinking of the conjugated polymers. These non-covalent crosslinking moieties are able to undergo an energy dissipation mechanism through breakage of bonds when strain is applied, while retaining high charge transport abilities. As a result, our polymer is able to recover its high field-effect mobility performance (more than 1 square centimetre per volt per second) even after a hundred cycles at 100 per cent applied strain. Organic thin-film field-effect transistors fabricated from these materials exhibited mobility as high as 1.3 square centimetres per volt per second and a high on/off current ratio exceeding a million. The field-effect mobility remained as high as 1.12 square centimetres per volt per second at 100 per cent strain along the direction perpendicular to the strain. The field-effect mobility of damaged devices can be almost fully recovered after a solvent and thermal healing treatment. Finally, we successfully fabricated a skin-inspired stretchable organic transistor operating under deformations that might be expected in a wearable device.

HgNO3 sensitivity of AlGaN/GaN field effect transistors functionalized with phytochelating peptides

NASA Astrophysics Data System (ADS)

Rohrbaugh, Nathaniel; Hernandez-Balderrama, Luis; Kaess, Felix; Kirste, Ronny; Collazo, Ramon; Ivanisevic, Albena

2016-06-01

This study examined the conductance sensitivity of AlGaN/GaN field effect transistors in response to varying Hg/HNO3 solutions. FET surfaces were covalently functionalized with phytochelatin-5 peptides in order to detect Hg in solution. Results showed a resilience of peptide-AlGaN/GaN bonds in the presence of strong HNO3 aliquots, with significant degradation in FET ID signal. However, devices showed strong and varied response to Hg concentrations of 1, 10, 100, and 1000 ppm. The gathered statistically significant results indicate that peptide terminated AlGaN/GaN devices are capable of differentiating between Hg solutions and demonstrate device sensitivity.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Reducing flicker noise in chemical vapor deposition graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Arnold, Heather N.; Sangwan, Vinod K.; Schmucker, Scott W.; Cress, Cory D.; Luck, Kyle A.; Friedman, Adam L.; Robinson, Jeremy T.; Marks, Tobin J.; Hersam, Mark C.

2016-02-01

Single-layer graphene derived from chemical vapor deposition (CVD) holds promise for scalable radio frequency (RF) electronic applications. However, prevalent low-frequency flicker noise (1/f noise) in CVD graphene field-effect transistors is often up-converted to higher frequencies, thus limiting RF device performance. Here, we achieve an order of magnitude reduction in 1/f noise in field-effect transistors based on CVD graphene transferred onto silicon oxide substrates by utilizing a processing protocol that avoids aqueous chemistry after graphene transfer. Correspondingly, the normalized noise spectral density (10-7-10-8 μm2 Hz-1) and noise amplitude (4 × 10-8-10-7) in these devices are comparable to those of exfoliated and suspended graphene. We attribute the reduction in 1/f noise to a decrease in the contribution of fluctuations in the scattering cross-sections of carriers arising from dynamic redistribution of interfacial disorder.

Microscopic origin of low frequency noise in MoS{sub 2} field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ghatak, Subhamoy; Jain, Manish; Ghosh, Arindam

2014-09-01

We report measurement of low frequency 1/f noise in molybdenum di-sulphide (MoS{sub 2}) field-effect transistors in multiple device configurations including MoS{sub 2} on silicon dioxide as well as MoS{sub 2}-hexagonal boron nitride (hBN) heterostructures. All as-fabricated devices show similar magnitude of noise with number fluctuation as the dominant mechanism at high temperatures and density, although the calculated density of traps is two orders of magnitude higher than that at the SiO{sub 2} interface. Measurements on the heterostructure devices with vacuum annealing and dual gated configuration reveals that along with the channel, metal-MoS{sub 2} contacts also play a significant role inmore » determining noise magnitude in these devices.« less

Cyclic and low temperature effects on microcircuits

NASA Technical Reports Server (NTRS)

Weissflug, V. A.; Sisul, E. V.

1977-01-01

Cyclic temperature and low temperature operating life tests, and pre-/post-life device evaluations were used to determine the degrading effects of thermal environments on microcircuit reliability. Low power transistor-transistor-logic gates and linear devices were included in each test group. Device metallization systems included aluminum metallization/aluminum wire, aluminum metallization/gold wire, and gold metallization/gold wire. Fewer than 2% electrical failures were observed during the cyclic and low temperature life tests and the post-life evaluations revealed approximately 2% bond pull failures. Reconstruction of aluminum die metallization was observed in all devices and the severity of the reconstruction appeared to be directly related to the magnitude of the temperature excursion. All types of bonds except the gold/gold bonds were weakened by exposure to repeated cyclic temperature stress.

Single-transistor-clocked flip-flop

DOEpatents

Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

2005-08-30

The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Specifics of Pulsed Arc Welding Power Supply Performance Based On A Transistor Switch

NASA Astrophysics Data System (ADS)

Krampit, N. Yu; Kust, T. S.; Krampit, M. A.

2016-08-01

Specifics of designing a pulsed arc welding power supply device are presented in the paper. Electronic components for managing large current was analyzed. Strengths and shortcomings of power supply circuits based on thyristor, bipolar transistor and MOSFET are outlined. As a base unit for pulsed arc welding was chosen MOSFET transistor, which is easy to manage. Measures to protect a transistor are given. As for the transistor control device is a microcontroller Arduino which has a low cost and adequate performance of the work. Bead transfer principle is to change the voltage on the arc in the formation of beads on the wire end. Microcontroller controls transistor when the arc voltage reaches the threshold voltage. Thus there is a separation and transfer of beads without splashing. Control strategies tested on a real device and presented. The error in the operation of the device is less than 25 us, it can be used controlling drop transfer at high frequencies (up to 1300 Hz).

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shervin, Shahab; Asadirad, Mojtaba; Materials Science and Engineering Program, University of Houston, Houston, Texas 77204

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strainmore » in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.« less

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

Solution-Processed Organic and Halide Perovskite Transistors on Hydrophobic Surfaces.

PubMed

Ward, Jeremy W; Smith, Hannah L; Zeidell, Andrew; Diemer, Peter J; Baker, Stephen R; Lee, Hyunsu; Payne, Marcia M; Anthony, John E; Guthold, Martin; Jurchescu, Oana D

2017-05-31

Solution-processable electronic devices are highly desirable due to their low cost and compatibility with flexible substrates. However, they are often challenging to fabricate due to the hydrophobic nature of the surfaces of the constituent layers. Here, we use a protein solution to modify the surface properties and to improve the wettability of the fluoropolymer dielectric Cytop. The engineered hydrophilic surface is successfully incorporated in bottom-gate solution-deposited organic field-effect transistors (OFETs) and hybrid organic-inorganic trihalide perovskite field-effect transistors (HTP-FETs) fabricated on flexible substrates. Our analysis of the density of trapping states at the semiconductor-dielectric interface suggests that the increase in the trap density as a result of the chemical treatment is minimal. As a result, the devices exhibit good charge carrier mobilities, near-zero threshold voltages, and low electrical hysteresis.

Organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Temperature dependence of frequency response characteristics in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Lu, Xubing; Minari, Takeo; Liu, Chuan; Kumatani, Akichika; Liu, J.-M.; Tsukagoshi, Kazuhito

2012-04-01

The frequency response characteristics of semiconductor devices play an essential role in the high-speed operation of electronic devices. We investigated the temperature dependence of dynamic characteristics in pentacene-based organic field-effect transistors and metal-insulator-semiconductor capacitors. As the temperature decreased, the capacitance-voltage characteristics showed large frequency dispersion and a negative shift in the flat-band voltage at high frequencies. The cutoff frequency shows Arrhenius-type temperature dependence with different activation energy values for various gate voltages. These phenomena demonstrate the effects of charge trapping on the frequency response characteristics, since decreased mobility prevents a fast charge response for alternating current signals at low temperatures.

Nano-Transistor Modeling: Two Dimensional Green's Function Method

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

Two quantum mechanical effects that impact the operation of nanoscale transistors are inversion layer energy quantization and ballistic transport. While the qualitative effects of these features are reasonably understood, a comprehensive study of device physics in two dimensions is lacking. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL (Drain Induced Barrier Lowering), and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI).

Displacement Damage in Bipolar Linear Integrated Circuits

NASA Technical Reports Server (NTRS)

Rax, B. G.; Johnston, A. H.; Miyahira, T.

2000-01-01

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Effects of V2O5/Au bi-layer electrodes on the top contact Pentacene-based organic thin film transistors

NASA Astrophysics Data System (ADS)

Borthakur, Tribeni; Sarma, Ranjit

2017-05-01

Top-contact Pentacene-based organic thin film transistors (OTFTs) with a thin layer of Vanadium Pent-oxide between Pentacene and Au layer are fabricated. Here we have found that the devices with V2O5/Au bi-layer source-drain electrode exhibit better field-effect mobility, high on-off ratio, low threshold voltage and low sub-threshold slope than the devices with Au only. The field-effect mobility, current on-off ratio, threshold voltage and sub-threshold slope of V2O5/Au bi-layer OTFT estimated from the device with 15 nm thick V2O5 layer is .77 cm2 v-1 s-1, 7.5×105, -2.9 V and .36 V/decade respectively.

Producing smart sensing films by means of organic field effect transistors.

PubMed

Manunza, Ileana; Orgiu, Emanuele; Caboni, Alessandra; Barbaro, Massimo; Bonfiglio, Annalisa

2006-01-01

We have fabricated the first example of totally flexible field effect device for chemical detection based on an organic field effect transistor (OFET) made by pentacene films grown on flexible plastic structures. The ion sensitivity is achieved by employing a thin Mylar foil as gate dielectric. A sensitivity of the device to the pH of the electrolyte solution has been observed A similar structure can be used also for detecting mechanical deformations on flexible surfaces. Thanks to the flexibility of the substrate and the low cost of the employed technology, these devices open the way for the production of flexible chemical and strain gauge sensors that can be employed in a variety of innovative applications such as wearable electronics, e-textiles, new man-machine interfaces.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Low-temperature phase transitions in a soluble oligoacene and their effect on device performance and stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, J. W.; Goetz, K. P.; Obaid, A.

The use of organic semiconductors in high-performance organic field-effect transistors requires a thorough understanding of the effects that processing conditions, thermal, and bias-stress history have on device operation. Here, we evaluate the temperature dependence of the electrical properties of transistors fabricated with 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene, a material that has attracted much attention recently due to its exceptional electrical properties. We have discovered a phase transition at T = 205 K and discuss its implications on device performance and stability. We examined the impact of this low-temperature phase transition on the thermodynamic, electrical, and structural properties of both single crystals and thin films of this material.more » Our results show that while the changes to the crystal structure are reversible, the induced thermal stress yields irreversible degradation of the devices.« less

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Extended behavioural modelling of FET and lattice-mismatched HEMT devices

NASA Astrophysics Data System (ADS)

Khawam, Yahya; Albasha, Lutfi

2017-07-01

This study presents an improved large signal model that can be used for high electron mobility transistors (HEMTs) and field effect transistors using measurement-based behavioural modelling techniques. The steps for accurate large and small signal modelling for transistor are also discussed. The proposed DC model is based on the Fager model since it compensates between the number of model's parameters and accuracy. The objective is to increase the accuracy of the drain-source current model with respect to any change in gate or drain voltages. Also, the objective is to extend the improved DC model to account for soft breakdown and kink effect found in some variants of HEMT devices. A hybrid Newton's-Genetic algorithm is used in order to determine the unknown parameters in the developed model. In addition to accurate modelling of a transistor's DC characteristics, the complete large signal model is modelled using multi-bias s-parameter measurements. The way that the complete model is performed is by using a hybrid multi-objective optimisation technique (Non-dominated Sorting Genetic Algorithm II) and local minimum search (multivariable Newton's method) for parasitic elements extraction. Finally, the results of DC modelling and multi-bias s-parameters modelling are presented, and three-device modelling recommendations are discussed.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE PAGES

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

2017-11-13

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Growth of nanotubes and chemical sensor applications

NASA Astrophysics Data System (ADS)

Hone, James; Kim, Philip; Huang, X. M. H.; Chandra, B.; Caldwell, R.; Small, J.; Hong, B. H.; Someya, T.; Huang, L.; O'Brien, S.; Nuckolls, Colin P.

2004-12-01

We have used a number of methods to grow long aligned single-walled carbon nanotubes. Geometries include individual long tubes, dense parallel arrays, and long freely suspended nanotubes. We have fabricated a variety of devices for applications such as multiprobe resistance measurement and high-current field effect transistors. In addition, we have measured conductance of single-walled semiconducting carbon nanotubes in field-effect transistor geometry and investigated the device response to water and alcoholic vapors. We observe significant changes in FET drain current when the device is exposed to various kinds of different solvent. These responses are reversible and reproducible over many cycles of vapor exposure. Our experiments demonstrate that carbon nanotube FETs are sensitive to a wide range of solvent vapors at concentrations in the ppm range.

Investigation of transport properties of coronene.TCNQ cocrystal microrods with coronene microrods and TCNQ microsheets

NASA Astrophysics Data System (ADS)

Wu, Hao-Di; Wang, Feng-Xia; Zhang, Meng; Pan, Ge-Bo

2015-07-01

Coronene.TCNQ cocrystal microrods, coronene microrods, and TCNQ microsheets were constructed by a drop-casting method. Prototype devices were fabricated and their field-effect-transistor (FET) performances were investigated. It is found that coronene.TCNQ microrods had exhibited an n-type characteristic and showed better FET performances than TCNQ microsheets.Coronene.TCNQ cocrystal microrods, coronene microrods, and TCNQ microsheets were constructed by a drop-casting method. Prototype devices were fabricated and their field-effect-transistor (FET) performances were investigated. It is found that coronene.TCNQ microrods had exhibited an n-type characteristic and showed better FET performances than TCNQ microsheets. Electronic supplementary information (ESI) available: Device fabrication and measurements. See DOI: 10.1039/c5nr02778k

Silicon-compatible high-hole-mobility transistor with an undoped germanium channel for low-power application

NASA Astrophysics Data System (ADS)

Cho, Seongjae; Man Kang, In; Rok Kim, Kyung; Park, Byung-Gook; Harris, James S.

2013-11-01

In this work, Ge-based high-hole-mobility transistor with Si compatibility is designed, and its performance is evaluated. A 2-dimensional hole gas is effectively constructed by a AlGaAs/Ge/Si heterojunction with a sufficiently large valence band offset. Moreover, an intrinsic Ge channel is exploited so that high hole mobility is preserved without dopant scattering. Effects of design parameters such as gate length, Ge channel thickness, and aluminum fraction in the barrier material on device characteristics are thoroughly investigated through device simulations. A high on-current above 30 μA/μm along with a low subthreshold swing was obtained from an optimized planar device for low-power applications.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

NASA Astrophysics Data System (ADS)

Davidović, Vojkan; Danković, Danijel; Ilić, Aleksandar; Manić, Ivica; Golubović, Snežana; Djorić-Veljković, Snežana; Prijić, Zoran; Prijić, Aneta; Stojadinović, Ninoslav

2018-04-01

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Liquid crystal-on-organic field-effect transistor sensory devices for perceptive sensing of ultralow intensity gas flow touch.

PubMed

Seo, Jooyeok; Park, Soohyeong; Nam, Sungho; Kim, Hwajeong; Kim, Youngkyoo

2013-01-01

We demonstrate liquid crystal-on-organic field-effect transistor (LC-on-OFET) sensory devices that can perceptively sense ultralow level gas flows. The LC-on-OFET devices were fabricated by mounting LC molecules (4-cyano-4'-pentylbiphenyl - 5CB) on the polymer channel layer of OFET. Results showed that the presence of LC molecules on the channel layer resulted in enhanced drain currents due to a strong dipole effect of LC molecules. Upon applying low intensity nitrogen gas flows, the drain current was sensitively increased depending on the intensity and time of nitrogen flows. The present LC-on-OFET devices could detect extremely low level nitrogen flows (0.7 sccm-11 μl/s), which could not be felt by human skins, thanks to a synergy effect between collective behavior of LC molecules and charge-sensitive channel layer of OFET. The similar sensation was also achieved using the LC-on-OFET devices with a polymer film skin, suggesting viable practical applications of the present LC-on-OFET sensory devices.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

Novel H+-Ion Sensor Based on a Gated Lateral BJT Pair

PubMed Central

Yuan, Heng; Zhang, Jixing; Cao, Chuangui; Zhang, Gangyuan; Zhang, Shaoda

2015-01-01

An H+-ion sensor based on a gated lateral bipolar junction transistor (BJT) pair that can operate without the classical reference electrode is proposed. The device is a special type of ion-sensitive field-effect transistor (ISFET). Classical ISFETs have the advantage of miniaturization, but  they are difficult to fabricate by a single fabrication process because of the bulky and brittle reference electrode materials. Moreover, the reference electrodes need to be separated from the sensor device in some cases. The proposed device is composed of two gated lateral BJT components, one of which had a silicide layer while the other was without the layer. The two components were operated under the metal-oxide semiconductor field-effect transistor (MOSFET)-BJT hybrid mode, which can be controlled by emitter voltage and base current. Buffer solutions with different pH values were used as the sensing targets to verify the characteristics of the proposed device. Owing to their different sensitivities, both components could simultaneously detect the H+-ion concentration and function as a reference to each other. Per the experimental results, the sensitivity of the proposed device was found to be approximately 0.175 μA/pH. This experiment demonstrates enormous potential to lower the cost of the ISFET-based sensor technology. PMID:26703625

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

The 20 GHz power GaAs FET development

NASA Technical Reports Server (NTRS)

Crandell, M.

1986-01-01

The development of power Field Effect Transistors (FET) operating in the 20 GHz frequency band is described. The major efforts include GaAs FET device development (both 1 W and 2 W devices), and the development of an amplifier module using these devices.

Integrated single-walled carbon nanotube/microfluidic devices for the study of the sensing mechanism of nanotube sensors.

PubMed

Fu, Qiang; Liu, Jie

2005-07-21

A method to fabricate integrated single-walled carbon nanotube/microfluidic devices was developed. This simple process could be used to directly prepare nanotube thin film transistors within the microfluidic channel and to register SWNT devices with the microfludic channel without the need of an additional alignment step. The microfluidic device was designed to have several inlets that deliver multiple liquid flows to a single main channel. The location and width of each flow in the main channel could be controlled by the relative flow rates. This capability enabled us to study the effect of the location and the coverage area of the liquid flow that contained charged molecules on the conduction of the nanotube devices, providing important information on the sensing mechanism of carbon nanotube sensors. The results showed that in a sensor based on a nanotube thin film field effect transistor, the sensing signal came from target molecules absorbed on or around the nanotubes. The effect from adsorption on metal electrodes was weak.

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2011 CFR

2011-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2012 CFR

2012-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2013 CFR

2013-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2014 CFR

2014-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Energy-Filtered Tunnel Transistor: A New Device Concept Toward Extremely-Low Energy Consumption Electronics

DTIC Science & Technology

2015-12-17

temperature . New device architecture that utilizes cold-electron transport for ultra-low energy consumption electronics has been designed in a configuration...the oxygen has also been found important for the SiC>2 sputter deposition. The sputter was carried out at room temperature . Our optimized process...have been pursued for two electronic devices, 1) room- temperature single-electron transistors, and 2) ultralow energy consumption transistors. For

Low-voltage self-assembled monolayer field-effect transistors on flexible substrates.

PubMed

Schmaltz, Thomas; Amin, Atefeh Y; Khassanov, Artoem; Meyer-Friedrichsen, Timo; Steinrück, Hans-Georg; Magerl, Andreas; Segura, Juan José; Voitchovsky, Kislon; Stellacci, Francesco; Halik, Marcus

2013-08-27

Self-assembled monolayer field-effect transistors (SAMFETs) of BTBT functionalized phosphonic acids are fabricated. The molecular design enables device operation with charge carrier mobilities up to 10(-2) cm(2) V(-1) s(-1) and for the first time SAMFETs which operate on rough, flexible PEN substrates even under mechanical substrate bending. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Organic Light-Emitting Transistors: Materials, Device Configurations, and Operations.

PubMed

Zhang, Congcong; Chen, Penglei; Hu, Wenping

2016-03-09

Organic light-emitting transistors (OLETs) represent an emerging class of organic optoelectronic devices, wherein the electrical switching capability of organic field-effect transistors (OFETs) and the light-generation capability of organic light-emitting diodes (OLEDs) are inherently incorporated in a single device. In contrast to conventional OFETs and OLEDs, the planar device geometry and the versatile multifunctional nature of OLETs not only endow them with numerous technological opportunities in the frontier fields of highly integrated organic electronics, but also render them ideal scientific scaffolds to address the fundamental physical events of organic semiconductors and devices. This review article summarizes the recent advancements on OLETs in light of materials, device configurations, operation conditions, etc. Diverse state-of-the-art protocols, including bulk heterojunction, layered heterojunction and laterally arranged heterojunction structures, as well as asymmetric source-drain electrodes, and innovative dielectric layers, which have been developed for the construction of qualified OLETs and for shedding new and deep light on the working principles of OLETs, are highlighted by addressing representative paradigms. This review intends to provide readers with a deeper understanding of the design of future OLETs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Memristive device based on a depletion-type SONOS field effect transistor

NASA Astrophysics Data System (ADS)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulle; Robinson, Daryl C.; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

Current saturation and voltage gain in bilayer graphene field effect transistors.

PubMed

Szafranek, B N; Fiori, G; Schall, D; Neumaier, D; Kurz, H

2012-03-14

The emergence of graphene with its unique electrical properties has triggered hopes in the electronic devices community regarding its exploitation as a channel material in field effect transistors. Graphene is especially promising for devices working at frequencies in the 100 GHz range. So far, graphene field effect transistors (GFETs) have shown cutoff frequencies up to 300 GHz, while exhibiting poor voltage gains, another important figure of merit for analog high frequency applications. In the present work, we show that the voltage gain of GFETs can be improved significantly by using bilayer graphene, where a band gap is introduced through a vertical electric displacement field. At a displacement field of -1.7 V/nm the bilayer GFETs exhibit an intrinsic voltage gain up to 35, a factor of 6 higher than the voltage gain in corresponding monolayer GFETs. The transconductance, which limits the cutoff frequency of a transistor, is not degraded by the displacement field and is similar in both monolayer and bilayer GFETs. Using numerical simulations based on an atomistic p(z) tight-binding Hamiltonian we demonstrate that this approach can be extended to sub-100 nm gate lengths. © 2012 American Chemical Society

Nature of size effects in compact models of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Torkhov, N. A., E-mail: trkf@mail.ru; Scientific-Research Institute of Semiconductor Devices, Tomsk 634050; Tomsk State University of Control Systems and Radioelectronics, Tomsk 634050

Investigations have shown that in the local approximation (for sizes L < 100 μm), AlGaN/GaN high electron mobility transistor (HEMT) structures satisfy to all properties of chaotic systems and can be described in the language of fractal geometry of fractional dimensions. For such objects, values of their electrophysical characteristics depend on the linear sizes of the examined regions, which explain the presence of the so-called size effects—dependences of the electrophysical and instrumental characteristics on the linear sizes of the active elements of semiconductor devices. In the present work, a relationship has been established for the linear model parameters of themore » equivalent circuit elements of internal transistors with fractal geometry of the heteroepitaxial structure manifested through a dependence of its relative electrophysical characteristics on the linear sizes of the examined surface areas. For the HEMTs, this implies dependences of their relative static (A/mm, mA/V/mm, Ω/mm, etc.) and microwave characteristics (W/mm) on the width d of the sink-source channel and on the number of sections n that leads to a nonlinear dependence of the retrieved parameter values of equivalent circuit elements of linear internal transistor models on n and d. Thus, it has been demonstrated that the size effects in semiconductors determined by the fractal geometry must be taken into account when investigating the properties of semiconductor objects on the levels less than the local approximation limit and designing and manufacturing field effect transistors. In general, the suggested approach allows a complex of problems to be solved on designing, optimizing, and retrieving the parameters of equivalent circuits of linear and nonlinear models of not only field effect transistors but also any arbitrary semiconductor devices with nonlinear instrumental characteristics.« less

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

PubMed Central

Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

2017-01-01

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

NASA Astrophysics Data System (ADS)

Dhakras, Prathamesh; Agnihotri, Pratik; Lee, Ji Ung

2017-06-01

The three pillars of semiconductor device technologies are (1) the p-n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Vertical field-effect transistor based on wave-function extension

NASA Astrophysics Data System (ADS)

Sciambi, A.; Pelliccione, M.; Lilly, M. P.; Bank, S. R.; Gossard, A. C.; Pfeiffer, L. N.; West, K. W.; Goldhaber-Gordon, D.

2011-08-01

We demonstrate a mechanism for a dual layer, vertical field-effect transistor, in which nearly depleting one layer will extend its wave function to overlap the other layer and increase tunnel current. We characterize this effect in a specially designed GaAs/AlGaAs device, observing a tunnel current increase of two orders of magnitude at cryogenic temperatures, and we suggest extrapolations of the design to other material systems such as graphene.

Quantum Optical Transistor and Other Devices Based on Nanostructures

NASA Astrophysics Data System (ADS)

Li, Jin-Jin; Zhu, Ka-Di

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to nanostructures. This provides an important clue toward the realization of quantum optical devices, such as quantum optical transistor, slow light device, fast light device, or light storage device. In contrast to conventional electronic transistor, a quantum optical transistor uses photons as signal carriers rather than electrons, which has a faster and more powerful transfer efficiency. Under the radiation of a strong pump laser, a signal laser can be amplified or attenuated via passing through a single quantum dot coupled to a photonic crystal (PC) nanocavity system. Such a switching and amplifying behavior can really implement the quantum optical transistor. By simply turning on or off the input pump laser, the amplified or attenuated signal laser can be obtained immediately. Based on this transistor, we further propose a method to measure the vacuum Rabi splitting of exciton in all-optical domain. Besides, we study the light propagation in a coupled QD and nanomechanical resonator (NR) system. We demonstrate that it is possible to achieve the slow light, fast light, and quantum memory for light on demand, which is based on the mechanically induced coherent population oscillation (MICPO) and exciton polaritons. These QD devices offer a route toward the use of all-optical technique to investigate the coupled QD systems and will make contributions to quantum internets and quantum computers.

Polarization dependent photo-induced bias stress effect in organic transistors.

NASA Astrophysics Data System (ADS)

Podzorov, Vitaly; Choi, Hyun Ho; Najafov, Hikmet; Saranin, Danila; Kharlamov, Nikolai A.; Kuznetzov, Denis V.; Didenko, Sergei I.; Cho, Kilwon; Briseno, Alejandro L.; Rutgers-Misis Collaboration; Ru-P Collaboration; Ru-Um Collaboration; Um-P Collaboration

Photo-induced charge transfer between a semiconductor and a gate insulator that occurs in organic transistors operating under illumination leads to a shift of the onset gate voltage in these devices. Here we report an observation of a polarization dependent photo-induced bias-stress effect in two prototypical single-crystal organic field-effect transistors, based on rubrene and TPBIQ. We find that the rate of the effect is a periodic function of polarization angle of a linearly polarized photoexcitation, with a periodicity of π. The observed phenomenon provides an effective tool for addressing the relationship between molecular packing and parameter drift in organic transistors under illumination. The work was carried out with financial support from the Ministry of Education and Science of the Russian Federation in the framework of Increase Competitiveness Program of NUST «MISiS» (No. K3-2016-004), by gov. decree 16/03/2013, N 211.

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Device considerations for development of conductance-based biosensors

PubMed Central

Lee, Kangho; Nair, Pradeep R.; Scott, Adina; Alam, Muhammad A.; Janes, David B.

2009-01-01

Design and fabrication of electronic biosensors based on field-effect-transistor (FET) devices require understanding of interactions between semiconductor surfaces and organic biomolecules. From this perspective, we review practical considerations for electronic biosensors with emphasis on molecular passivation effects on FET device characteristics upon immobilization of organic molecules and an electrostatic model for FET-based biosensors. PMID:24753627

Improving performance of armchair graphene nanoribbon field effect transistors via boron nitride doping

NASA Astrophysics Data System (ADS)

Goharrizi, A. Yazdanpanah; Sanaeepur, M.; Sharifi, M. J.

2015-09-01

Device performance of 10 nm length armchair graphene nanoribbon field effect transistors with 1.5 nm and 4 nm width (13 and 33 atoms in width respectively) are compared in terms of Ion /Ioff , trans-conductance, and sub-threshold swing. While narrow devices suffer from edge roughness wider devices are subject to more substrate surface roughness and reduced bandgap. Boron Nitride doping is employed to compensate reduced bandgap in wider devices. Simultaneous effects of edge and substrate surface roughness are considered. Results show that in the presence of both the edge and substrate surface roughness the 4 nm wide device with boron nitride doping shows improved performance with respect to the 1.5 nm one (both of which incorporate the same bandgap AGNR as channel material). Electronic simulations are performed via NEGF method along with tight-binding Hamiltonian. Edge and surface roughness are created by means of one and two dimensional auto correlation functions respectively. Electronic characteristics are averaged over a large number of devices due to statistic nature of both the edge and surface roughness.

Dry etching method for compound semiconductors

DOEpatents

Shul, Randy J.; Constantine, Christopher

1997-01-01

A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.

Dry etching method for compound semiconductors

DOEpatents

Shul, R.J.; Constantine, C.

1997-04-29

A dry etching method is disclosed. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators. 1 fig.

JFET/SOS (Junction Field-Effect Transistor/Silicon-on-Sapphire) Devices: Gamma-Radiation-Induced Effects.

DTIC Science & Technology

1988-03-01

Results, ATR-86A(8501)-1, The Aerospace Corporation: El Segundo, Calif. (20 May 1987). 3. D. Neaman , W. Shedd, and B. Buchanan, "Permanently Ionizing...Radiation Effects in Dielectrically Bounded Field-Effect Transistors," IEEE Trans.. Nucl. Sci. NS-20 [6], 158-165 (Decembe. 1973). 4. D. Neaman , W. Shedd...1974). 5. D. Neaman , W. Shedd, and B. Buchanan, "Silicon-Sapphire Interface Charge Trapping -- Effects of Sapphire Type and Epi Growth Conditions

Contact Resistance and Channel Conductance of Graphene Field-Effect Transistors under Low-Energy Electron Irradiation

PubMed Central

Giubileo, Filippo; Di Bartolomeo, Antonio; Martucciello, Nadia; Romeo, Francesco; Iemmo, Laura; Romano, Paola; Passacantando, Maurizio

2016-01-01

We studied the effects of low-energy electron beam irradiation up to 10 keV on graphene-based field effect transistors. We fabricated metallic bilayer electrodes to contact mono- and bi-layer graphene flakes on SiO2, obtaining specific contact resistivity ρc≈19 kΩ·µm2 and carrier mobility as high as 4000 cm2·V−1·s−1. By using a highly doped p-Si/SiO2 substrate as the back gate, we analyzed the transport properties of the device and the dependence on the pressure and on the electron bombardment. We demonstrate herein that low energy irradiation is detrimental to the transistor current capability, resulting in an increase in contact resistance and a reduction in carrier mobility, even at electron doses as low as 30 e−/nm2. We also show that irradiated devices recover their pristine state after few repeated electrical measurements. PMID:28335335

Low-frequency (1/f) noise in nanocrystal field-effect transistors.

PubMed

Lai, Yuming; Li, Haipeng; Kim, David K; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2014-09-23

We investigate the origins and magnitude of low-frequency noise in high-mobility nanocrystal field-effect transistors and show the noise is of 1/f-type. Sub-band gap states, in particular, those introduced by nanocrystal surfaces, have a significant influence on the 1/f noise. By engineering the device geometry and passivating nanocrystal surfaces, we show that in the linear and saturation regimes the 1/f noise obeys Hooge's model of mobility fluctuations, consistent with transport of a high density of accumulated carriers in extended electronic states of the NC thin films. In the subthreshold regime, the Fermi energy moves deeper into the mobility gap and sub-band gap trap states give rise to a transition to noise dominated by carrier number fluctuations as described in McWhorter's model. CdSe nanocrystal field-effect transistors have a Hooge parameter of 3 × 10(-2), comparable to other solution-deposited, thin-film devices, promising high-performance, low-cost, low-noise integrated circuitry.

Electrostatic melting in a single-molecule field-effect transistor with applications in genomic identification

PubMed Central

Vernick, Sefi; Trocchia, Scott M.; Warren, Steven B.; Young, Erik F.; Bouilly, Delphine; Gonzalez, Ruben L.; Nuckolls, Colin; Shepard, Kenneth L.

2017-01-01

The study of biomolecular interactions at the single-molecule level holds great potential for both basic science and biotechnology applications. Single-molecule studies often rely on fluorescence-based reporting, with signal levels limited by photon emission from single optical reporters. The point-functionalized carbon nanotube transistor, known as the single-molecule field-effect transistor, is a bioelectronics alternative based on intrinsic molecular charge that offers significantly higher signal levels for detection. Such devices are effective for characterizing DNA hybridization kinetics and thermodynamics and enabling emerging applications in genomic identification. In this work, we show that hybridization kinetics can be directly controlled by electrostatic bias applied between the device and the surrounding electrolyte. We perform the first single-molecule experiments demonstrating the use of electrostatics to control molecular binding. Using bias as a proxy for temperature, we demonstrate the feasibility of detecting various concentrations of 20-nt target sequences from the Ebolavirus nucleoprotein gene in a constant-temperature environment. PMID:28516911

Thermal transistor utilizing gas-liquid transition.

PubMed

Komatsu, Teruhisa S; Ito, Nobuyasu

2011-01-01

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Performance regeneration of InGaZnO transistors with ultra-thin channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Binglei; Li, He; Zhang, Xijian, E-mail: zhangxijian@sdu.edu.cn, E-mail: songam@sdu.edu.cn

2015-03-02

Thin-film transistors (TFTs) based on ultra-thin amorphous indium gallium zinc oxide (a-IGZO) semiconductors down to 4 nm were studied motivated by the increasing cost of indium. At and below 5 nm, it was found that the field-effect mobility was severely degraded, the threshold voltage increased, and the output characteristics became abnormal showing no saturated current. By encapsulating a layer of polymethyl methacrylate on the IGZO TFTs, the performance of the 5-nm-thick device was effectively recovered. The devices also showed much higher on/off ratios, improved hysteresis, and normal output characteristic curves as compared with devices not encapsulated. The stability of the encapsulated devicesmore » was also studied over a four month period.« less

A computational study of a novel graphene nanoribbon field effect transistor

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Development and fabrication of an augmented power transistor

NASA Technical Reports Server (NTRS)

Geisler, M. J.; Hill, F. E.; Ostop, J. A.

1983-01-01

The development of device design and processing techniques for the fabrication of an augmented power transistor capable of fast switching and high voltage power conversion is discussed. The major device goals sustaining voltages in the range of 800 to 1000 V at 80 A and 50 A, respectively, at a gain of 14. The transistor switching rise and fall times were both to have been less than 0.5 microseconds. The development of a passivating glass technique to shield the device high voltage junction from moisture and ionic contaminants is discussed as well as the development of an isolated package that separates the thermal and electrical interfaces. A new method was found to alloy the transistors to the molybdenum disc at a relatively low temperature. The measured electrical performance compares well with the predicted optimum design specified in the original proposed design. A 40 mm diameter transistor was fabricated with seven times the emitter area of the earlier 23 mm diameter device.

A gallium phosphide high-temperature bipolar junction transistor

NASA Technical Reports Server (NTRS)

Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

1981-01-01

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Effect of electrode design on crosstalk between neighboring organic field-effect transistors based on one single crystal

NASA Astrophysics Data System (ADS)

Li, Mengjie; Tang, Qingxin; Tong, Yanhong; Zhao, Xiaoli; Zhou, Shujun; Liu, Yichun

2018-03-01

The design of high-integration organic circuits must be such that the interference between neighboring devices is eliminated. Here, rubrene crystals were used to study the effect of the electrode design on crosstalk between neighboring organic field-effect transistors (OFETs). Results show that a decreased source/drain interval and gate electrode width can decrease the diffraction distance of the current, and therefore can weaken the crosstalk. In addition, the inherent low carrier concentration in organic semiconductors can create a high-resistance barrier at the space between gate electrodes of neighboring devices, limiting or even eliminating the crosstalk as a result of the gate electrode width being smaller than the source/drain electrode width.

A pH sensor based on electric properties of nanotubes on a glass substrate

PubMed Central

Nakamura, Motonori; Ishii, Atsushi; Subagyo, Agus; Hosoi, Hirotaka; Sueoka, Kazuhisa; Mukasa, Koichi

2007-01-01

We fabricated a pH-sensitive device on a glass substrate based on properties of carbon nanotubes. Nanotubes were immobilized specifically on chemically modified areas on a substrate followed by deposition of metallic source and drain electrodes on the area. Some nanotubes connected the source and drain electrodes. A top gate electrode was fabricated on an insulating layer of silane coupling agent on the nanotube. The device showed properties of ann-type field effect transistor when a potential was applied to the nanotube from the top gate electrode. Before fabrication of the insulating layer, the device showed that thep-type field effect transistor and the current through the source and drain electrodes depend on the buffer pH. The current increases with decreasing pH of the CNT solution. This device, which can detect pH, is applicable for use as a biosensor through modification of the CNT surface. PMID:21806848

Current conduction in junction gate field effect transistors. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Kim, C.

1970-01-01

The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.

Localized heating on silicon field effect transistors: device fabrication and temperature measurements in fluid.

PubMed

Elibol, Oguz H; Reddy, Bobby; Nair, Pradeep R; Dorvel, Brian; Butler, Felice; Ahsan, Zahab S; Bergstrom, Donald E; Alam, Muhammad A; Bashir, Rashid

2009-10-07

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

The effects of neutron and gamma rays on the electrical and switching characteristics of power semiconductor switches must be known and understood by the designer of the power conditioning, control, and transmission subsystem of space nuclear power systems. The SP-100 radiation requirements at 25 m from the nuclear source are a neutron fluence of 10(exp 13) n/sq cm and a gamma dose of 0.5 Mrads. Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN Bipolar Junction Transistors (BJTs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Static Induction Transistors (SITs) are presented. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Post-irradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Silicon Field Effect Transistors as Dual-Use Sensor-Heater Hybrids

PubMed Central

Reddy, Bobby; Elibol, Oguz H.; Nair, Pradeep R.; Dorvel, Brian R.; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2011-01-01

We demonstrate the temperature mediated applications of a previously proposed novel localized dielectric heating method on the surface of dual purpose silicon field effect transistor (FET) sensor-heaters and perform modeling and characterization of the underlying mechanisms. The FETs are first shown to operate as electrical sensors via sensitivity to changes in pH in ionic fluids. The same devices are then demonstrated as highly localized heaters via investigation of experimental heating profiles and comparison to simulation results. These results offer further insight into the heating mechanism and help determine the spatial resolution of the technique. Two important biosensor platform applications spanning different temperature ranges are then demonstrated: a localized heat-mediated DNA exchange reaction and a method for dense selective functionalization of probe molecules via the heat catalyzed complete desorption and reattachment of chemical functionalization to the transistor surfaces. Our results show that the use of silicon transistors can be extended beyond electrical switching and field-effect sensing to performing localized temperature controlled chemical reactions on the transistor itself. PMID:21214189

Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Renteria, J.; Jiang, C.; Samnakay, R.

2014-04-14

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2 × 10{sup 19} eV{sup −1}cm{sup −3}more » and 2.5 × 10{sup 20} eV{sup −1}cm{sup −3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.« less

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Microstructural control of charge transport in organic blend thin-film transistors

DOE PAGES

Hunter, Simon; Chen, Jihua; Anthopoulos, Thomas D.

2014-07-17

In this paper, the charge-transport processes in organic p-channel transistors based on the small-molecule 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TES ADT), the polymer poly(triarylamine)(PTAA) and blends thereof are investigated. In the case of blend films, lateral conductive atomic force microscopy in combination with energy filtered transmission electron microscopy are used to study the evolution of charge transport as a function of blends composition, allowing direct correlation of the film's elemental composition and morphology with hole transport. Low-temperature transport measurements reveal that optimized blend devices exhibit lower temperature dependence of hole mobility than pristine PTAA devices while also providing a narrower bandgap trap distribution thanmore » pristine diF-TES ADT devices. These combined effects increase the mean hole mobility in optimized blends to 2.4 cm 2/Vs; double the value measured for best diF-TES ADT-only devices. The bandgap trap distribution in transistors based on different diF-TES ADT:PTAA blend ratios are compared and the act of blending these semiconductors is seen to reduce the trap distribution width yet increase the average trap energy compared to pristine diF-TES ADT-based devices. In conclusion, our measurements suggest that an average trap energy of <75 meV and a trap distribution of <100 meV is needed to achieve optimum hole mobility in transistors based on diF-TES ADT:PTAA blends.« less

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

PubMed

Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

2013-10-04

Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

PubMed

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Self-Heating Effects In Polysilicon Source Gated Transistors

PubMed Central

Sporea, R. A.; Burridge, T.; Silva, S. R. P.

2015-01-01

Source-gated transistors (SGTs) are thin-film devices which rely on a potential barrier at the source to achieve high gain, tolerance to fabrication variability, and low series voltage drop, relevant to a multitude of energy-efficient, large-area, cost effective applications. The current through the reverse-biased source barrier has a potentially high positive temperature coefficient, which may lead to undesirable thermal runaway effects and even device failure through self-heating. Using numerical simulations we show that, even in highly thermally-confined scenarios and at high current levels, self-heating is insufficient to compromise device integrity. Performance is minimally affected through a modest increase in output conductance, which may limit the maximum attainable gain. Measurements on polysilicon devices confirm the simulated results, with even smaller penalties in performance, largely due to improved heat dissipation through metal contacts. We conclude that SGTs can be reliably used for high gain, power efficient analog and digital circuits without significant performance impact due to self-heating. This further demonstrates the robustness of SGTs. PMID:26351099

On the AlGaInP-bulk and AlGaInP/GaAs-superlattice confinement effects for heterostructure-emitter bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw

2015-02-09

The confinement effect and electrical characteristics of heterostructure-emitter bipolar transistors with an AlGaInP bulk-confinement layer and an AlGaInP/GaAs superlattice-confinement layer are first demonstrated and compared by experimentally results. In the two devices, the relatively large valence band discontinuity at AlGaInP/GaAs heterojunction provides excellent confinement effect for holes to enhance current gain. As to the AlGaInP/GaAs superlattice-confinement device, part of thermionic-emission electrons will be trapped in the GaAs quantum wells of the superlattice. This will result in lower collector current and current gain as compared with the bulk-confinement device. Nevertheless, the superlattice-confinement device exhibits a larger current-gain cutoff frequency, which canmore » be attributed that the tunneling behavior is included in the carrier transportation and transporting time across the emitter region could be substantially reduced.« less

Emerging ferroelectric transistors with nanoscale channel materials: the possibilities, the limitations

NASA Astrophysics Data System (ADS)

Hong, Xia

2016-03-01

Combining the nonvolatile, locally switchable polarization field of a ferroelectric thin film with a nanoscale electronic material in a field effect transistor structure offers the opportunity to examine and control a rich variety of mesoscopic phenomena and interface coupling. It is also possible to introduce new phases and functionalities into these hybrid systems through rational design. This paper reviews two rapidly progressing branches in the field of ferroelectric transistors, which employ two distinct classes of nanoscale electronic materials as the conducting channel, the two-dimensional (2D) electron gas graphene and the strongly correlated transition metal oxide thin films. The topics covered include the basic device physics, novel phenomena emerging in the hybrid systems, critical mechanisms that control the magnitude and stability of the field effect modulation and the mobility of the channel material, potential device applications, and the performance limitations of these devices due to the complex interface interactions and challenges in achieving controlled materials properties. Possible future directions for this field are also outlined, including local ferroelectric gate control via nanoscale domain patterning and incorporating other emergent materials in this device concept, such as the simple binary ferroelectrics, layered 2D transition metal dichalcogenides, and the 4d and 5d heavy metal compounds with strong spin-orbit coupling.

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

NASA Astrophysics Data System (ADS)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce; Hall, David; Niaz, Iftikhar Ahmad; Zhou, Yuchun; Sham, L. J.; Lo, Yu-Hwa

2015-08-01

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanism based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

Thermo-piezo-electro-mechanical simulation of AlGaN (aluminum gallium nitride) / GaN (gallium nitride) High Electron Mobility Transistors

NASA Astrophysics Data System (ADS)

Stevens, Lorin E.

Due to the current public demand of faster, more powerful, and more reliable electronic devices, research is prolific these days in the area of high electron mobility transistor (HEMT) devices. This is because of their usefulness in RF (radio frequency) and microwave power amplifier applications including microwave vacuum tubes, cellular and personal communications services, and widespread broadband access. Although electrical transistor research has been ongoing since its inception in 1947, the transistor itself continues to evolve and improve much in part because of the many driven researchers and scientists throughout the world who are pushing the limits of what modern electronic devices can do. The purpose of the research outlined in this paper was to better understand the mechanical stresses and strains that are present in a hybrid AlGaN (Aluminum Gallium Nitride) / GaN (Gallium Nitride) HEMT, while under electrically-active conditions. One of the main issues currently being researched in these devices is their reliability, or their consistent ability to function properly, when subjected to high-power conditions. The researchers of this mechanical study have performed a static (i.e. frequency-independent) reliability analysis using powerful multiphysics computer modeling/simulation to get a better idea of what can cause failure in these devices. Because HEMT transistors are so small (micro/nano-sized), obtaining experimental measurements of stresses and strains during the active operation of these devices is extremely challenging. Physical mechanisms that cause stress/strain in these structures include thermo-structural phenomena due to mismatch in both coefficient of thermal expansion (CTE) and mechanical stiffness between different materials, as well as stress/strain caused by "piezoelectric" effects (i.e. mechanical deformation caused by an electric field, and conversely voltage induced by mechanical stress) in the AlGaN and GaN device portions (both piezoelectric materials). This piezoelectric effect can be triggered by voltage applied to the device's gate contact and the existence of an HEMT-unique "two-dimensional electron gas" (2DEG) at the GaN-AlGaN interface. COMSOL Multiphysics computer software has been utilized to create a finite element (i.e. piece-by-piece) simulation to visualize both temperature and stress/strain distributions that can occur in the device, by coupling together (i.e. solving simultaneously) the thermal, electrical, structural, and piezoelectric effects inherent in the device. The 2DEG has been modeled not with the typically-used self-consistent quantum physics analytical equations, rather as a combined localized heat source* (thermal) and surface charge density* (electrical) boundary condition. Critical values of stress/strain and their respective locations in the device have been identified. Failure locations have been estimated based on the critical values of stress and strain, and compared with reports in literature. The knowledge of the overall stress/strain distribution has assisted in determining the likely device failure mechanisms and possible mitigation approaches. The contribution and interaction of individual stress mechanisms including piezoelectric effects and thermal expansion caused by device self-heating (i.e. fast-moving electrons causing heat) have been quantified. * Values taken from results of experimental studies in literature.

Position-dependent performance of copper phthalocyanine based field-effect transistors by gold nanoparticles modification.

PubMed

Luo, Xiao; Li, Yao; Lv, Wenli; Zhao, Feiyu; Sun, Lei; Peng, Yingquan; Wen, Zhanwei; Zhong, Junkang; Zhang, Jianping

2015-01-21

A facile fabrication and characteristics of copper phthalocyanine (CuPc)-based organic field-effect transistor (OFET) using the gold nanoparticles (Au NPs) modification is reported, thereby achieving highly improved performance. The effect of Au NPs located at three different positions, that is, at the SiO2/CuPc interface (device B), embedding in the middle of CuPc layer (device C), and on the top of CuPc layer (device D), is investigated, and the results show that device D has the best performance. Compared with the device without Au NPs (reference device A), device D displays an improvement of field-effect mobility (μ(sat)) from 1.65 × 10(-3) to 5.51 × 10(-3) cm(2) V(-1) s(-1), and threshold voltage decreases from -23.24 to -16.12 V. Therefore, a strategy for the performance improvement of the CuPc-based OFET with large field-effect mobility and saturation drain current is developed, on the basis of the concept of nanoscale Au modification. The model of an additional electron transport channel formation by FET operation at the Au NPs/CuPc interface is therefore proposed to explain the observed performance improvement. Optimum CuPc thickness is confirmed to be about 50 nm in the present study. The device-to-device uniformity and time stability are discussed for future application.

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

NASA Technical Reports Server (NTRS)

Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

2002-01-01

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

Ultraclean individual suspended single-walled carbon nanotube field effect transistor

NASA Astrophysics Data System (ADS)

Liu, Siyu; Zhang, Jian; Nshimiyimana, Jean Pierre; Chi, Xiannian; Hu, Xiao; Wu, Pei; Liu, Jia; Wang, Gongtang; Sun, Lianfeng

2018-04-01

In this work, we report an effective technique of fabricating ultraclean individual suspended single-walled carbon nanotube (SWNT) transistors. The surface tension of molten silver is utilized to suspend an individual SWNT between a pair of Pd electrodes during annealing treatment. This approach avoids the usage and the residues of organic resist attached to SWNTs, resulting ultraclean SWNT devices. And the resistance per micrometer of suspended SWNTs is found to be smaller than that of non-suspended SWNTs, indicating the effect of the substrate on the electrical properties of SWNTs. The ON-state resistance (˜50 kΩ), mobility of 8600 cm2 V-1 s-1 and large on/off ratio (˜105) of semiconducting suspended SWNT devices indicate its advantages and potential applications.

General strategy for biodetection in high ionic strength solutions using transistor-based nanoelectronic sensors.

PubMed

Gao, Ning; Zhou, Wei; Jiang, Xiaocheng; Hong, Guosong; Fu, Tian-Ming; Lieber, Charles M

2015-03-11

Transistor-based nanoelectronic sensors are capable of label-free real-time chemical and biological detection with high sensitivity and spatial resolution, although the short Debye screening length in high ionic strength solutions has made difficult applications relevant to physiological conditions. Here, we describe a new and general strategy to overcome this challenge for field-effect transistor (FET) sensors that involves incorporating a porous and biomolecule permeable polymer layer on the FET sensor. This polymer layer increases the effective screening length in the region immediately adjacent to the device surface and thereby enables detection of biomolecules in high ionic strength solutions in real-time. Studies of silicon nanowire field-effect transistors with additional polyethylene glycol (PEG) modification show that prostate specific antigen (PSA) can be readily detected in solutions with phosphate buffer (PB) concentrations as high as 150 mM, while similar devices without PEG modification only exhibit detectable signals for concentrations ≤10 mM. Concentration-dependent measurements exhibited real-time detection of PSA with a sensitivity of at least 10 nM in 100 mM PB with linear response up to the highest (1000 nM) PSA concentrations tested. The current work represents an important step toward general application of transistor-based nanoelectronic detectors for biochemical sensing in physiological environments and is expected to open up exciting opportunities for in vitro and in vivo biological sensing relevant to basic biology research through medicine.

Multifunctional Self-Assembled Monolayers for Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Cernetic, Nathan

Organic field effect transistors (OFETs) have the potential to reach commercialization for a wide variety of applications such as active matrix display circuitry, chemical and biological sensing, radio-frequency identification devices and flexible electronics. In order to be commercially competitive with already at-market amorphous silicon devices, OFETs need to approach similar performance levels. Significant progress has been made in developing high performance organic semiconductors and dielectric materials. Additionally, a common route to improve the performance metric of OFETs is via interface modification at the critical dielectric/semiconductor and electrode/semiconductor interface which often play a significant role in charge transport properties. These metal oxide interfaces are typically modified with rationally designed multifunctional self-assembled monolayers. As means toward improving the performance metrics of OFETs, rationally designed multifunctional self-assembled monolayers are used to explore the relationship between surface energy, SAM order, and SAM dipole on OFET performance. The studies presented within are (1) development of a multifunctional SAM capable of simultaneously modifying dielectric and metal surface while maintaining compatibility with solution processed techniques (2) exploration of the relationship between SAM dipole and anchor group on graphene transistors, and (3) development of self-assembled monolayer field-effect transistor in which the traditional thick organic semiconductor is replaced by a rationally designed self-assembled monolayer semiconductor. The findings presented within represent advancement in the understanding of the influence of self-assembled monolayers on OFETs as well as progress towards rationally designed monolayer transistors.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

NASA Astrophysics Data System (ADS)

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor.

Monitoring Single-Molecule Protein Dynamics with a Carbon Nanotube Transistor

NASA Astrophysics Data System (ADS)

Collins, Philip G.

2014-03-01

Nanoscale electronic devices like field-effect transistors have long promised to provide sensitive, label-free detection of biomolecules. Single-walled carbon nanotubes press this concept further by not just detecting molecules but also monitoring their dynamics in real time. Recent measurements have demonstrated this premise by monitoring the single-molecule processivity of three different enzymes: lysozyme, protein Kinase A, and the Klenow fragment of DNA polymerase I. With all three enzymes, single molecules tethered to nanotube transistors were electronically monitored for 10 or more minutes, allowing us to directly observe a range of activity including rare transitions to chemically inactive and hyperactive conformations. The high bandwidth of the nanotube transistors further allow every individual chemical event to be clearly resolved, providing excellent statistics from tens of thousands of turnovers by a single enzyme. Initial success with three different enzymes indicates the generality and attractiveness of the nanotube devices as a new tool to complement other single-molecule techniques. Research on transduction mechanisms provides the design rules necessary to further generalize this architecture and apply it to other proteins. The purposeful incorporation of just one amino acid is sufficient to fabricate effective, single molecule sensors from a wide range of enzymes or proteins.

All-Electrical Spin Field Effect Transistor in van der Waals Heterostructures at Room Temperature

NASA Astrophysics Data System (ADS)

Dankert, André; Dash, Saroj

Spintronics aims to exploit the spin degree of freedom in solid state devices for data storage and information processing. Its fundamental concepts (creation, manipulation and detection of spin polarization) have been demonstrated in semiconductors and spin transistor structures using electrical and optical methods. However, an unsolved challenge is the realization of all-electrical methods to control the spin polarization in a transistor manner at ambient temperatures. Here we combine graphene and molybdenum disulfide (MoS2) in a van der Waals heterostructure to realize a spin field-effect transistor (spin-FET) at room temperature. These two-dimensional crystals offer a unique platform due to their contrasting properties, such as weak spin-orbit coupling (SOC) in graphene and strong SOC in MoS2. The gate-tuning of the Schottky barrier at the MoS2/graphene interface and MoS2 channel yields spins to interact with high SOC material and allows us to control the spin polarization and lifetime. This all-electrical spin-FET at room temperature is a substantial step in the field of spintronics and opens a new platform for testing a plethora of exotic physical phenomena, which can be key building blocks in future device architectures.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

PubMed Central

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor. PMID:28134275

High transconductance organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

PubMed Central

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Deformable Organic Nanowire Field-Effect Transistors.

PubMed

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Total-dose radiation effects data for semiconductor devices: 1985 supplement, volume 1

NASA Technical Reports Server (NTRS)

Martin, K. E.; Gauthier, M. K.; Coss, J. R.; Dantas, A. R. V.; Price, W. E.

1985-01-01

Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-01

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green’s function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors.

PubMed

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-04

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green's function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

Device Physics of Contact Issues for the Overestimation and Underestimation of Carrier Mobility in Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Liu, Chuan; Li, Gongtan; Di Pietro, Riccardo; Huang, Jie; Noh, Yong-Young; Liu, Xuying; Minari, Takeo

2017-09-01

Very high values of carrier mobility have been recently reported in newly developed materials for field-effect transistors (FETs) or thin-film transistors (TFTs). However, there is an increasing concern of whether the values are overestimated. In this paper, we investigate how much contact resistance a FET or TFT can tolerate to allow the conventional current-voltage equations, which is derived for no contact resistance. We contend that mobility in transistors with resistive contact can be underestimated with the presence of the injection barrier, whereas mobility in transistors with gated Schottky contact can be overestimated by more than 10 times. The latter phenomenon occurs even in long-channel devices, and it becomes more severe when using low-k dielectrics. This is because the band bending and injection barrier experience a complicated evolution on account of electrostatic doping in the semiconducting layer; thus, they do not follow a capacitance approximation. When the band bending is weak, the accumulation is as weak as that in the subthreshold regime. Accordingly, the carrier concentration nonlinearly increases with the gate field. This mechanism can occur with or without exhibiting the "kink" feature in the transfer curves, which has been suggested as the signature of overestimation. For precision, carrier mobility should be presented against gate voltage and should be examined by other recommended extraction methods.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

PubMed

Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

2016-04-26

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Localized Heating on Silicon Field Effect Transistors: Device Fabrication and Temperature Measurements in Fluid

PubMed Central

Elibol, Oguz H.; Reddy, Bobby; Nair, Pradeep R.; Dorvel, Brian; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2010-01-01

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications. PMID:19967115

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

Large scale electromechanical transistor with application in mass sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to bemore » used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.« less

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulie; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decision-making ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline (PANi) is an intriguing material because its electrical conductivity can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain, and when combined with polyethylene oxide (PEO), can be formed into nanofibers with diameters ranging from approximately 50 to 500 nm (depending on the deposition conditions). The initial goal of this work was to demonstrate transistor behavior in these nanofibers, thus creating a foundation for future logic devices.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Intrinsic magnetic refrigeration of a single electron transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ciccarelli, C.; Ferguson, A. J.; Campion, R. P.

In this work, we show that aluminium doped with low concentrations of magnetic impurities can be used to fabricate quantum devices with intrinsic cooling capabilities. We fabricate single electron transistors made of aluminium doped with 2% Mn by using a standard multi angle evaporation technique and show that the quantity of metal used to fabricate the devices generates enough cooling power to achieve a drop of 160 mK in the electron temperature at the base temperature of our cryostat (300 mK). The cooling mechanism is based on the magneto-caloric effect from the diluted Mn moments.

Transport properties of field-effect transistor with Langmuir-Blodgett films of C60 dendrimer and estimation of impurity levels

NASA Astrophysics Data System (ADS)

Kawasaki, Naoko; Nagano, Takayuki; Kubozono, Yoshihiro; Sako, Yuuki; Morimoto, Yu; Takaguchi, Yutaka; Fujiwara, Akihiko; Chu, Chih-Chien; Imae, Toyoko

2007-12-01

Field-effect transistor (FET) device has been fabricated with Langmuir-Blodgett films of C60 dendrimer. The device showed n-channel normally off characteristics with the field-effect mobility of 2.7×10-3cm2V-1s-1 at 300K, whose value is twice as high as that (1.4×10-3cm2V-1s-1) for the FET with spin-coated films of C60 dendrimer. This originates from the formation of ordered π-conduction network of C60 moieties. From the temperature dependence of field-effect mobility, a structural phase transition has been observed at around 300K. Furthermore, the density of states for impurity levels was estimated in the Langmuir-Blodgett films.

Effective enhancement of hydrophilicity of solution indium zinc oxide-based thin-film transistors by oxygen plasma treatment of deposition layer surface

NASA Astrophysics Data System (ADS)

You, Hsin-Chiang; Wang, Yu-Chih

2016-06-01

In this paper, we describe the use of a simple and efficient sol-gel solution method for synthesizing indium zinc oxide (IZO) films for use as semiconductor channel layers in thin-film transistors (TFTs) on p-type silicon substrates. The performance of IZO-based TFTs was investigated, and the effect of oxygen plasma treatment on the surface of dielectric SiN x was observed. Oxygen plasma treatment effectively enhanced the electron mobility in IZO-based TFT devices from 0.005 to 1.56 cm2 V-1 s-1, an increase of more than 312 times, and effectively enhanced device performance. X-ray photoelectron spectroscopy analysis of the IZO film was performed to clarify element bonding.

A microwave field-driven transistor-like skyrmionic device with the microwave current-assisted skyrmion creation

NASA Astrophysics Data System (ADS)

Xia, Jing; Huang, Yangqi; Zhang, Xichao; Kang, Wang; Zheng, Chentian; Liu, Xiaoxi; Zhao, Weisheng; Zhou, Yan

2017-10-01

Magnetic skyrmion is a topologically protected domain-wall structure at nanoscale, which could serve as a basic building block for advanced spintronic devices. Here, we propose a microwave field-driven skyrmionic device with the transistor-like function, where the motion of a skyrmion in a voltage-gated ferromagnetic nanotrack is studied by micromagnetic simulations. It is demonstrated that the microwave field can drive the motion of a skyrmion by exciting the propagating spin waves, and the skyrmion motion can be governed by a gate voltage. We also investigate the microwave current-assisted creation of a skyrmion to facilitate the operation of the transistor-like skyrmionic device on the source terminal. It is found that the microwave current with an appropriate frequency can reduce the threshold current density required for the creation of a skyrmion from the ferromagnetic background. The proposed transistor-like skyrmionic device operated with the microwave field and current could be useful for building future skyrmion-based circuits.

α,ω-dihexyl-sexithiophene thin films for solution-gated organic field-effect transistors

NASA Astrophysics Data System (ADS)

Schamoni, Hannah; Noever, Simon; Nickel, Bert; Stutzmann, Martin; Garrido, Jose A.

2016-02-01

While organic semiconductors are being widely investigated for chemical and biochemical sensing applications, major drawbacks such as the poor device stability and low charge carrier mobility in aqueous electrolytes have not yet been solved to complete satisfaction. In this work, solution-gated organic field-effect transistors (SGOFETs) based on the molecule α,ω-dihexyl-sexithiophene (DH6T) are presented as promising platforms for in-electrolyte sensing. Thin films of DH6T were investigated with regard to the influence of the substrate temperature during deposition on the grain size and structural order. The performance of SGOFETs can be improved by choosing suitable growth parameters that lead to a two-dimensional film morphology and a high degree of structural order. Furthermore, the capability of the SGOFETs to detect changes in the pH or ionic strength of the gate electrolyte is demonstrated and simulated. Finally, excellent transistor stability is confirmed by continuously operating the device over a period of several days, which is a consequence of the low threshold voltage of DH6T-based SGOFETs. Altogether, our results demonstrate the feasibility of high performance and highly stable organic semiconductor devices for chemical or biochemical applications.

Suppression of 1/f noise in near-ballistic h-BN-graphene-h-BN heterostructure field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stolyarov, Maxim A.; Liu, Guanxiong; Balandin, Alexander A., E-mail: balandin@ee.ucr.edu

2015-07-13

We have investigated low-frequency 1/f noise in the boron nitride–graphene–boron nitride heterostructure field-effect transistors on Si/SiO{sub 2} substrates (f is a frequency). The device channel was implemented with a single layer graphene encased between two layers of hexagonal boron nitride. The transistors had the charge carrier mobility in the range from ∼30 000 to ∼36 000 cm{sup 2}/Vs at room temperature. It was established that the noise spectral density normalized to the channel area in such devices can be suppressed to ∼5 × 10{sup −9 }μm{sup 2 }Hz{sup −1}, which is a factor of ×5 – ×10 lower than that in non-encapsulated graphene devices on Si/SiO{sub 2}. The physicalmore » mechanism of noise suppression was attributed to screening of the charge carriers in the channel from traps in SiO{sub 2} gate dielectric and surface defects. The obtained results are important for the electronic and optoelectronic applications of graphene.« less

Low-frequency noise in MoSe{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Das, Suprem R., E-mail: srdaspurdue@gmail.com, E-mail: janes@purdue.edu; Kwon, Jiseok; Prakash, Abhijith

One of the important performance metrics of emerging nanoelectronic devices, including low dimensional Field Effect Transistors (FETs), is the magnitude of the low-frequency noise. Atomically thin 2D semiconductor channel materials such as MoX{sub 2} (X ≡ S, Se) have shown promising transistor characteristics such as I{sub ON}/I{sub OFF} ratio exceeding 10{sup 6} and low I{sub OFF}, making them attractive as channel materials for next generation nanoelectronic devices. However, MoS{sub 2} FETs demonstrated to date exhibit high noise levels under ambient conditions. In this letter, we report at least two orders of magnitude smaller values of Hooge parameter in a back-gatedmore » MoSe{sub 2} FET (10 atomic layers) with nickel S/D contacts and measured at atmospheric pressure and temperature. The channel dominated regime of noise was extracted from the total noise spectrum and is shown to follow a mobility fluctuation model with 1/f dependence. The low noise in MoSe{sub 2} FETs is comparable to other 1D nanoelectronic devices such as carbon nanotube FETs (CNT-FETs) and paves the way for use in future applications in precision sensing and communications.« less

Interface trap of p-type gate integrated AlGaN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Kyu Sang

2017-09-01

In this work, the impact of trap states at the p-(Al)GaN/AlGaN interface has been investigated for the normally-off mode p-(Al)GaN/AlGaN/GaN heterostructure field-effect transistors (HFETs) by means of frequency dependent conductance. From the current-voltage (I-V) measurement, it was found that the p-AlGaN gate integrated device has higher drain current and lower gate leakage current compared to the p-GaN gate integrated device. We obtained the interface trap density and the characteristic time constant for the p-type gate integrated HFETs under the forward gate voltage of up to 6 V. As a result, the interface trap density (characteristic time constant) of the p-GaN gate device was lower (longer) than that of the p-AlGaN. Furthermore, it was analyzed that the trap state energy level of the p-GaN gate device was located at the shallow level relative to the p-AlGaN gate device, which accounts for different gate leakage current of each devices.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Radiation Effects in III-V Nanowire Devices

DTIC Science & Technology

2016-09-01

Nanowire Devices Distribution Statement A. Approved for public release; distribution is unlimited. September 2016 HDTRA1-11-1-0021 Steven R...Name: Prof. S. R. J. Brueck Organization/Institution: University of New Mexico Project Title: Radiation Effects in III-V Nanowire Devices What are...the agency approved application or plan. The objectives of this program were to: a) develop a new nanowire transistor technology based on nanoscale

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors.

PubMed

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-04-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc 6 ) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO 2 ) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10 -2 cm 2 V -1 s -1 and 10 6 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

PubMed Central

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-01-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc6) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones. PMID:27877383

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Multi-turn transmit coil to increase b1 efficiency in current source amplification.

PubMed

Gudino, N; Griswold, M A

2013-04-01

A multi-turn transmit surface coil design was presented to improve B1 efficiency when used with current source amplification. Three different coil designs driven by an on-coil current-mode class-D amplifier with current envelope feedback were tested on the benchtop and through imaging in a 1.5 T scanner. Case temperature of the power field-effect transistor at the amplifier output stage was measured to evaluate heat dissipation for the different current levels and coil configurations. In addition, a lower power rated device was tested to exploit the potential gain in B1 obtained with the multi-turn coil. As shown both on the benchtop and in a 1.5 T scanner, B1 was increased by almost 3-fold without increasing heat dissipation on the power device at the amplifier's output using a multi-turn surface coil. Similar gain was obtained when connecting a lower power rated field-effect transistor to the multi-turn coil. In addition to reduce heat dissipation per B1 in the device, higher B1 per current efficiency allows the use of field-effect transistors with lower current ratings and lower port capacitances, which could improve the overall performance of the on-coil current source transmit system. Copyright © 2013 Wiley Periodicals, Inc.

Silicon nanowire biologically sensitive field effect transistors: electrical characteristics and applications.

PubMed

Rim, Taiuk; Baek, Chang-Ki; Kim, Kihyun; Jeong, Yoon-Ha; Lee, Jeong-Soo; Meyyappan, M

2014-01-01

The interest in biologically sensitive field effect transistors (BioFETs) is growing explosively due to their potential as biosensors in biomedical, environmental monitoring and security applications. Recently, adoption of silicon nanowires in BioFETs has enabled enhancement of sensitivity, device miniaturization, decreasing power consumption and emerging applications such as the 3D cell probe. In this review, we describe the device physics and operation of the silicon nanowire BioFETs along with recent advances in the field. The silicon nanowire BioFETs are basically the same as the conventional field-effect transistors (FETs) with the exceptions of nanowire channel instead of thin film and a liquid gate instead of the conventional gate. Therefore, the silicon device physics is important to understand the operation of the BioFETs. Herein, physical characteristics of the silicon nanowire FETs are described and the operational principles of the BioFETs are classified according to the number of gates and the analysis domain of the measured signal. Even the bottom-up process has merits on low-cost fabrication; the top-down process technique is highlighted here due to its reliability and reproducibility. Finally, recent advances in the silicon nanowire BioFETs in the literature are described and key features for commercialization are discussed.

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

NASA Astrophysics Data System (ADS)

Bhuvaneshwari, Y. V.; Kranti, Abhinav

2017-12-01

In this work, we use the modified McLarty function to understand and extract accumulation (μ acc) and bulk (μ bulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (N d) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ 1 and θ 2) by a single method. The extracted results indicate that μ acc can reach higher values than μ bulk due to the screening effect. Results also show that θ 2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ 1) in JL devices designed with higher N d (≥1019 cm-3) is mainly affected by series resistance (R sd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ 1 factor is governed by both the intrinsic mobility reduction factor (θ 10) and R sd. Additionally, the impact of variation in oxide thickness (T ox), gate length (L g), N d and temperature on θ 1 and θ 2 has been investigated for JL transistor. The weak dependence of μ bulk and μ acc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

Effect of Al2O3 encapsulation on multilayer MoSe2 thin-film transistors

NASA Astrophysics Data System (ADS)

Lee, Hyun Ah; Yeoul Kim, Seong; Kim, Jiyoung; Choi, Woong

2017-03-01

We report the effect of Al2O3 encapsulation on the device performance of multilayer MoSe2 thin-film transistors based on statistical investigation of 29 devices with a SiO2 bottom-gate dielectric. On average, Al2O3 encapsulation by atomic layer deposition increased the field-effect mobility from 10.1 cm2 V-1 s-1 to 14.8 cm2 V-1 s-1, decreased the on/off-current ratio from 8.5  ×  105 to 2.3  ×  105 and negatively shifted the threshold voltage from  -1.1 V to  -8.1 V. Calculation based on the Y-function method indicated that the enhancement of intrinsic carrier mobility occurred independently of the reduction of contact resistance after Al2O3 encapsulation. Furthermore, contrary to previous reports in the literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method for improving the carrier mobility of multilayer MoSe2 transistors, providing important implications on the application of MoSe2 and other 2D materials into high-performance transistors.

Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

PubMed Central

Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

2014-01-01

Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

Effect of substrate and temperature on the electronic properties of monolayer molybdenum disulfide field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Qizhi; Fang, Jiajia; Zhang, Guangru; Wang, Quan

2018-03-01

The use of two-dimensional nanostructured molybdenum disulfide (MoS2) films in field-effect transistors (FETs) in place of graphene was investigated. Monolayer MoS2 films were fabricated by chemical vapor deposition. The output and transfer curves of supported and suspended MoS2 FETs were measured. The mobility of the suspended device reached 364.2 cm2 V-1 s-1 at 150 °C. The hysteresis of the supported device in transfer curves was much larger than that of the suspended device, and it increased at higher temperatures. These results indicate that the device mobility was limited by Coulomb scattering at ambient temperature, and surface/interface phonon scattering at 150 °C, and the injection of electrons, via quantum tunneling through the Schottky barrier at the contact, was enhanced at higher temperatures and led to the increase of the hysteresis. The suspended MoS2 films show potential for application as a channel material in electronic devices, and further understanding the causes of hysteresis in a material is important for its use in technologies, such as memory devices and sensing cells.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Restorative effect of oxygen annealing on device performance in HfIZO thin-film transistors

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2015-03-01

Metal-oxide based thin-film transistors (oxide-TFTs) are very promising for use in next generation electronics such as transparent displays requiring high switching and driving performance. In this study, we demonstrate an optimized process to secure excellent device performance with a favorable shift of the threshold voltage toward 0V in amorphous hafnium-indium-zinc-oxide (a-HfIZO) TFTs by using post-treatment with oxygen annealing. This enhancement results from the improved interfacial characteristics between gate dielectric and semiconductor layers due to the reduction in the density of interfacial states related to oxygen vacancies afforded by oxygen annealing. The device statistics confirm the improvement in the device-to-device and run-to-run uniformity. We also report on the photo-induced stability in such oxide-TFTs against long-term UV irradiation, which is significant for transparent displays.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Fabrication of metal nanopatterns for organic field effect transistor electrodes by cracking and transfer printing

NASA Astrophysics Data System (ADS)

Wang, Xiaonan; Fu, Tingting; Wang, Zhe

2018-04-01

In this paper, we demonstrate a novel method for fabricating metal nanopatterns using cracking to address the limitations of traditional techniques. Parallel crack arrays were created in a polydimethylsiloxane (PDMS) mold using a combination of surface modification and control of strain fields. The elastic PDMS containing the crack arrays was subsequently used as a stamp to prepare nanoscale metal patterns on a substrate by transfer printing. To illustrate the functionality of this technique, we employed the metal patterns as the source and drain contacts of an organic field effect transistor. Using this approach, we fabricated transistors with channel lengths ranging from 70-600 nm. The performance of these devices when the channel length was reduced was studied. The drive current density increases as expected, indicating the creation of operational transistors with recognizable properties.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

NASA Astrophysics Data System (ADS)

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-02-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future.

Electrical properties of solution-deposited ZnO thin-film transistors by low-temperature annealing.

PubMed

Lim, Chul; Oh, Ji Young; Koo, Jae Bon; Park, Chan Woo; Jung, Soon-Won; Na, Bock Soon; Chu, Hye Yong

2014-11-01

Flexible oxide thin-film transistors (Oxide-TFTs) have emerged as next generation transistors because of their applicability in electronic device. In particular, the major driving force behind solution-processed zinc oxide film research is its prospective use in printing for electronics. A low-temperature process to improve the performance of solution-processed n-channel ZnO thin-film transistors (TFTs) fabricated via spin-coating and inkjet-printing is introduced here. ZnO nanoparticles were synthesized using a facile sonochemical method that was slightly modified based on a previously reported method. The influence of the annealing atmosphere on both nanoparticle-based TFT devices fabricated via spin-coating and those created via inkjet printing was investigated. For the inkjet-printed TFTs, the characteristics were improved significantly at an annealing temperature of 150 degrees C. The field effect mobility, V(th), and the on/off current ratios were 3.03 cm2/Vs, -3.3 V, and 10(4), respectively. These results indicate that annealing at 150 degrees C 1 h is sufficient to obtain a mobility (μ(sat)) as high as 3.03 cm2/Vs. Also, the active layer of the solution-based ZnO nanoparticles allowed the production of high-performance TFTs for low-cost, large-area electronics and flexible devices.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

PubMed Central

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-01-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future. PMID:25655666

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Demonstrated

NASA Technical Reports Server (NTRS)

Mueller, Carl H.; Theofylaktos, Onoufrios; Robinson, Daryl C.; Miranda, Felix A.

2004-01-01

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decisionmaking ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline/polyethylene oxide (PANi/PEO) nanofibers are of interest because they have electrical conductivities that can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain. At the NASA Glenn Research Center, we have observed field effect transistor (FET) behavior in electrospun PANi/PEO nanofibers doped with camphorsulfonic acid. The nanofibers were deposited onto Au electrodes, which had been prepatterned onto oxidized silicon substrates. The preceding scanning electron image shows the device used in the transistor measurements. Saturation channel currents are observed at surprisingly low source/drain voltages (see the following graph). The hole mobility in the depletion regime is 1.4x10(exp -4)sq cm/V sec, whereas the one-dimensional charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx.10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating one-dimensional polymer FET's.

Solution-processed single-walled carbon nanotube field effect transistors and bootstrapped inverters for disintegratable, transient electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Sung Hun, E-mail: harin74@gmail.com, E-mail: jhl@snu.ac.kr, E-mail: jrogers@illinois.edu; Shin, Jongmin; Cho, In-Tak

2014-07-07

This paper presents materials, device designs, and physical/electrical characteristics of a form of nanotube electronics that is physically transient, in the sense that all constituent elements dissolve and/or disperse upon immersion into water. Studies of contact effects illustrate the ability to use water soluble metals such as magnesium for source/drain contacts in nanotube based field effect transistors. High mobilities and on/off ratios in transistors that use molybdenum, silicon nitride, and silicon oxide enable full swing characteristics for inverters at low voltages (∼5 V) and with high gains (∼30). Dissolution/disintegration tests of such systems on water soluble sheets of polyvinyl alcohol demonstratemore » physical transience within 30 min.« less

Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

NASA Astrophysics Data System (ADS)

Shauly, Eitan; Rotstein, Israel; Peltinov, Ram; Latinski, Sergei; Adan, Ofer; Levi, Shimon; Menadeva, Ovadya

2009-03-01

The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmaxTM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Top-Contact Pentacene-Based Organic Thin Film Transistor (OTFT) with N, N'-Bis(3-Methyl Phenyl)- N, N'-Diphenyl Benzidine (TPD)/Au Bilayer Source-Drain Electrode

NASA Astrophysics Data System (ADS)

Borthakur, Tribeni; Sarma, Ranjit

2018-01-01

A top-contact Pentacene-based organic thin film transistor (OTFT) with N, N'-Bis (3-methyl phenyl)- N, N'-diphenyl benzidine (TPD)/Au bilayer source-drain electrode is reported. The devices with TPD/Au bilayer source-drain (S-D) electrodes show better performance than the single layer S-D electrode OTFT devices. The field-effect mobility of 4.13 cm2 v-1 s-1, the on-off ratio of 1.86 × 107, the threshold voltage of -4 v and the subthreshold slope of .27 v/decade, respectively, are obtained from the device with a TPD/Au bilayer source-drain electrode.

Thermal management of microwave power heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Bozada, C.; Cerny, C.; De Salvo, G.; Dettmer, R.; Ebel, J.; Gillespie, J.; Havasy, C.; Jenkins, T.; Ito, C.; Nakano, K.; Pettiford, C.; Quach, T.; Sewell, J.; Via, G. D.; Anholt, R.

1997-10-01

A comprehensive study of the device layout effects on thermal resistance in thermally-shunted heterojunction bipolar transistors (HBTs) was completed. The thermal resistance scales linearly with emitter dot diameter for single element HBTs. For multiple emitter element devices, the thermal resistance scales with area. HBTs with dot geometrics have lower thermal impedance than bar HBTs with equivalent emitter area. The thermal resistance of a 200 μm 2 emitter area device was reduced from 266°C/W to 146°C/W by increasing the shunt thickness from 3 μm to 20 μm and placing a thermal shunt landing between the fingers. Also, power-added efficiencies at 10 GHz were improved from 30% to 68% by this thermal resistance reduction.

Carbon nanostructure-based field-effect transistors for label-free chemical/biological sensors.

PubMed

Hu, PingAn; Zhang, Jia; Li, Le; Wang, Zhenlong; O'Neill, William; Estrela, Pedro

2010-01-01

Over the past decade, electrical detection of chemical and biological species using novel nanostructure-based devices has attracted significant attention for chemical, genomics, biomedical diagnostics, and drug discovery applications. The use of nanostructured devices in chemical/biological sensors in place of conventional sensing technologies has advantages of high sensitivity, low decreased energy consumption and potentially highly miniaturized integration. Owing to their particular structure, excellent electrical properties and high chemical stability, carbon nanotube and graphene based electrical devices have been widely developed for high performance label-free chemical/biological sensors. Here, we review the latest developments of carbon nanostructure-based transistor sensors in ultrasensitive detection of chemical/biological entities, such as poisonous gases, nucleic acids, proteins and cells.

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Electrical characteristics of Graphene based Field Effect Transistor (GFET) biosensor for ADH detection

NASA Astrophysics Data System (ADS)

Selvarajan, Reena Sri; Hamzah, Azrul Azlan; Majlis, Burhanuddin Yeop

2017-08-01

First pristine graphene was successfully produced by mechanical exfoliation and electrically characterized in 2004 by Andre Geim and Konstantin Novoselov at University of Manchester. Since its discovery in 2004, graphene also known as `super' material that has enticed many researchers and engineers to explore its potential in ultrasensitive detection of analytes in biosensing applications. Among myriad reported sensors, biosensors based on field effect transistors (FETs) have attracted much attention. Thus, implementing graphene as conducting channel material hastens the opportunities for production of ultrasensitive biosensors for future device applications. Herein, we have reported electrical characteristics of graphene based field effect transistor (GFET) for ADH detection. GFET was modelled and simulated using Lumerical DEVICE charge transport solver (DEVICE CT). Electrical characteristics comprising of transfer and output characteristics curves are reported in this study. The device shows ambipolar curve and achieved a minimum conductivity of 0.23912 e5A at Dirac point. However, the curve shifts to the left and introduces significant changes in the minimum conductivity as drain voltage is increased. Output characteristics of GFET exhibits linear Id - Vd dependence characteristics for gate voltage ranging from 0 to 1.5 V. In addition, behavior of electrical transport through GFET was analyzed for various simulation temperatures. It clearly proves that the electrical transport in GFET is dependent on the simulation temperature as it may vary the maximum resistance in channel of the device. Therefore, this unique electrical characteristics of GFET makes it as a promising candidate for ultrasensitive detection of small biomolecules such as ADH in biosensing applications.

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

Theoretical study on the top- and enclosed-contacted single-layer MoS{sub 2} piezotronic transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Wei, E-mail: wliu@binn.cas.cn, E-mail: zlwang@gatech.edu; Zhou, Yongli; Zhang, Aihua

Recently, the piezotronic effect has been observed in two-dimensional single-layer MoS{sub 2} materials, which have potential applications in force and pressure triggered or controlled electronic devices, sensors, and human-machine interfaces. However, classical theory faces the difficulty in explaining the mechanism of the piezotronic effect for the top- and enclosed-contacted MoS{sub 2} transistors, since the piezoelectric charges are assumed to exist only at the edge of the MoS{sub 2} flake that is far from the electronic transport pathway. In the present study, we identify the piezoelectric charges at the MoS{sub 2}/metal-MoS{sub 2} interface by employing both the density functional theory andmore » finite element method simulations. This interface is on the transport pathway of both top- and enclosed-contacted MoS{sub 2} transistors, thus it is capable of controlling their transport properties. This study deepens the understanding of piezotronic effect and provides guidance for the design of two-dimensional piezotronic devices.« less

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

NASA Astrophysics Data System (ADS)

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min-1), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 105, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm2 V-1 s-1. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing.

PubMed

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-13

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min(-1)), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10(5), a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm(2) V(-1) s(-1). The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

Application of Transistors in Textiles: Monitoring Water Transportation Behaviour in Fibrous Assemblies

NASA Astrophysics Data System (ADS)

Chatterjee, Arobindo; Singh, Pratibha; Ghosh, Subrata

2017-06-01

Simple semiconductor device has been used for amplifying the analog signals, obtained with the change in electrical resistance in fibrous assembly and converting these amplified copies of signals to digital signals. This paper deals with the application of transistors as amplifier, as well as switch. Different circuit configurations using transistors have been tried for sensing and reciprocating the real time data on suitable display device. It is found that transistors configured as common-emitter amplifiers can precisely sense the liquid at the surface of fibrous assembly at different levels with respect to time.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

NASA Astrophysics Data System (ADS)

Cui, Ning; Liang, Renrong; Wang, Jing; Xu, Jun

2012-06-01

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Piezoelectric potential gated field-effect transistor based on a free-standing ZnO wire.

PubMed

Fei, Peng; Yeh, Ping-Hung; Zhou, Jun; Xu, Sheng; Gao, Yifan; Song, Jinhui; Gu, Yudong; Huang, Yanyi; Wang, Zhong Lin

2009-10-01

We report an external force triggered field-effect transistor based on a free-standing piezoelectric fine wire (PFW). The device consists of an Ag source electrode and an Au drain electrode at two ends of a ZnO PFW, which were separated by an insulating polydimethylsiloxane (PDMS) thin layer. The working principle of the sensor is proposed based on the piezoelectric potential gating effect. Once subjected to a mechanical impact, the bent ZnO PFW cantilever creates a piezoelectric potential distribution across it width at its root and simultaneously produces a local reverse depletion layer with much higher donor concentration than normal, which can dramatically change the current flowing from the source electrode to drain electrode when the device is under a fixed voltage bias. Due to the free-standing structure of the sensor device, it has a prompt response time less than 20 ms and quite high and stable sensitivity of 2%/microN. The effect from contact resistance has been ruled out.

Confinement-induced InAs/GaSb heterojunction electron-hole bilayer tunneling field-effect transistor

NASA Astrophysics Data System (ADS)

Padilla, J. L.; Medina-Bailon, C.; Alper, C.; Gamiz, F.; Ionescu, A. M.

2018-04-01

Electron-Hole Bilayer Tunneling Field-Effect Transistors are typically based on band-to-band tunneling processes between two layers of opposite charge carriers where tunneling directions and gate-induced electric fields are mostly aligned (so-called line tunneling). However, the presence of intense electric fields associated with the band bending required to trigger interband tunneling, along with strong confinement effects, has made these types of devices to be regarded as theoretically appealing but technologically impracticable. In this work, we propose an InAs/GaSb heterostructure configuration that, although challenging in terms of process flow design and fabrication, could be envisaged for alleviating the electric fields inside the channel, whereas, at the same time, making quantum confinement become the mechanism that closes the broken gap allowing the device to switch between OFF and ON states. The utilization of induced doping prevents the harmful effect of band tails on the device performance. Simulation results lead to extremely steep slope characteristics endorsing its potential interest for ultralow power applications.

1T1R Nonvolatile Memory with Al/TiO₂/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor.

PubMed

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-12-09

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 5 cm²/Vs, low threshold voltage of -1.1 V, and low leakage current of 10 -12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO₂-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications.

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

NASA Astrophysics Data System (ADS)

Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

2017-04-01

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

Impact of Illumination on Charge Injection and Accumulation in Organic Transistor in Presence of Plasmonic Nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Keanchuan; Weis, Martin; Chen, Xiangyu; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2013-04-01

Effects of illumination on the carrier injection and transport due to photogenerated carriers were investigated in pentacene organic field-effect transistor (OFET). A plasmonic nanoparticles self-assembled monolayer (SAM) was incorporated in pentacene FET to act to enhance the photo-carrier generation. The influence of nanoparticles (NPs) on the photogeneration as well as on the charge trapping has been investigated using the current-voltage (I-V) and impedance spectroscopy (IS) measurements. The I-V results proved higher amount of photogenerated charge in presence of NPs even though this device has the contact resistance about two orders higher and effective mobility an order lower than the reference device without plasmonic NPs. The IS analysis of relaxation times verified strong influence of NPs on the charge trapping.

Characterization of vertical GaN p-n diodes and junction field-effect transistors on bulk GaN down to cryogenic temperatures

NASA Astrophysics Data System (ADS)

Kizilyalli, I. C.; Aktas, O.

2015-12-01

There is great interest in wide-bandgap semiconductor devices and most recently in vertical GaN structures for power electronic applications such as power supplies, solar inverters and motor drives. In this paper the temperature-dependent electrical behavior of vertical GaN p-n diodes and vertical junction field-effect transistors fabricated on bulk GaN substrates of low defect density (104 to 106 cm-2) is described. Homoepitaxial MOCVD growth of GaN on its native substrate and the ability to control the doping in the drift layers in GaN have allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40 μm and net carrier electron concentrations as low as 1 × 1015 cm-3. This parameter range is suitable for applications requiring breakdown voltages of 1.2 kV to 5 kV. Mg, which is used as a p-type dopant in GaN, is a relatively deep acceptor (E A ≈ 0.18 eV) and susceptible to freeze-out at temperatures below 200 K. The loss of holes in p-GaN has a deleterious effect on p-n junction behavior, p-GaN contacts and channel control in junction field-effect transistors at temperatures below 200 K. Impact ionization-based avalanche breakdown (BV > 1200 V) in GaN p-n junctions is characterized between 77 K and 423 K for the first time. At higher temperatures the p-n junction breakdown voltage improves due to increased phonon scattering. A positive temperature coefficient in the breakdown voltage is demonstrated down to 77 K; however, the device breakdown characteristics are not as abrupt at temperatures below 200 K. On the other hand, contact resistance to p-GaN is reduced dramatically above room temperature, improving the overall device performance in GaN p-n diodes in all cases except where the n-type drift region resistance dominates the total forward resistance. In this case, the electron mobility can be deconvolved and is found to decrease with T -3/2, consistent with a phonon scattering model. Also, normally-on vertical junction field-effect transistors with BV = 1000 V and drain currents of 4 A are fabricated and characterized over the same temperature range. It is demonstrated that vertical GaN devices (diodes and transistors) utilizing p-n junctions are suitable for most practical applications including automotive ones (210 K < T < 423 K). While devices are functional at cryogenic temperatures (77 K) there may be some limitations to their performance due the freeze-out of Mg acceptors.

MOSFET analog memory circuit achieves long duration signal storage

NASA Technical Reports Server (NTRS)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Biomimetic Trehalose Biosensor Using Gustatory Receptor (Gr5a) Expressed in Drosophila Cells and Ion-Sensitive Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Lau, Hui-Chong; Bae, Tae-Eon; Jang, Hyun-June; Kwon, Jae-Young; Cho, Won-Ju; Lim, Jeong-Ok

2013-04-01

The development of potential applications of biosensors using the sensory systems of vertebrates and invertebrates has progressed rapidly, especially in clinical diagnosis. The biosensor developed here involves the use of Drosophila cells expressing the gustatory receptor Gr5a and an ion-sensitive field-effect transistor (ISFET) sensor device. Gustatory receptor Gr5a is expressed abundantly in gustatory neurons and acts as a primary marker for tastants, especially sugar, in Drosophila. As a result, it could potentially serve as a good candidate for potential biomarkers of diseases in which the current knowledge of the cause and treatment is limited. The developed ISFET was based on the outstanding electrical characteristics of the metal-oxide-semiconductor field-effect transistor (MOSFET) with a subthreshold swing of 85 mV/dec, low leakage current of <10-12 and high on/off current ratio of 7.3×106. The SiO2 sensing membrane with a pH sensitivity of 34.9 mV/pH and drift rate 1.17 mV/h was sufficient for biosensing applications. In addition, the sensor device also showed significant compatibility with the Drosophila cells expressing Gr5a and their response to sugar, particularly trehalose. Moreover, the interactions between the transfected Drosophila cells and trehalose were consistent and reliable. This suggests that the developed ISFET sensor device could have potential use in the future as a screening device in diagnosis.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Carbon nanotube and graphene device modeling and simulation

NASA Astrophysics Data System (ADS)

Yoon, Young Ki

The performance of the semiconductors has been improved and the price has gone down for decades. It has been continuously scaled down in size year by year, and now it encounters the fundamental scaling limit. We, therefore, should prepare a new era beyond the conventional semiconductor technologies. One of the most promising devices is possible by carbon nanotube (CNT) or graphene nanoribbon (GNR) in terms of its excellent charge transport properties. Their fundamental material properties and device physics are totally different to those of the conventional devices. In this nano-regime, more sophisticated device modeling and simulation are really needed to elucidate nano-device operation and to save our resources from errors. The numerical simulation works in this dissertation will provide novel view points on the emerging devices. In this dissertation, CNT and GNR devices are numerically studied. The first part of this work is on CNT devices, and a common structure of CNT device has CNT channel, metal source and drain contacts, and gate electrode. We investigate the strain, geometry, and scattering effects on the device performance of CNT field-effect transistors (FETs). It is shown that even a small amount of strain can result in a large effect on the performance of CNTFETs due to the variation of the bandgap and band-structure-limited velocity. A type of strain which produces a larger bandgap results in increased Schottky barrier (SB) height and decreased band-structure-limited velocity, and hence a smaller minimum leakage current, smaller on current, larger maximum achievable Ion/Ioff, and larger intrinsic delay. We also examine geometry effect of partial gate CNTFETs. In the growth process of vertical CNT, underlap between the gate and the bottom electrode is advantageous for transistor operation because it suppresses ambipolar conduction of SBFETs. Both n-type and p-type transistor operations with balanced performance metrics can be achieved on a single partial gate FET by using proper bias schemes. The effect of phonon scattering on the intrinsic delay and cut-off frequency of Schottky barrier CNTFETs is also examined. Carriers are mostly scattered by optical and zone boundary phonons beyond the beginning of the channel. The scattering has a small direct effect on the DC on current of the CNTFET, but it results in significant decrease of intrinsic cut-off frequency and increase of intrinsic delay. Semiconducting CNT is useful for the channel in CNTFETs, whereas metallic CNT can be used as an electrode. If a porous CNT film is used as a source electrode, vertical thin-film transistors (TFTs) can be constructed. Vertical organic FET (OFET) shows clear transistor switching behavior allowing orders of magnitude modulation of the source-drain current even in the presence of electrostatic screening by the source electrode. The channel length should be carefully engineered due to the trade-off between device characteristics in the subthreshold and above-threshold regions. The second subject is device simulations of GNRFETs. Even though GNR is also graphene-based quasi-1D nanostructure like CNT, the differences in shape, boundary condition, and existence of edges and dangling bonds make it operate in a different way. Atomistic 3D simulation study of the performance of GNR SBFETs is presented. The impacts of non-idealities on device performance have been investigated. The edges of GNR, which do not exist in CNT, can be advantages or disadvantages. If an appropriate control by different edge atoms is possible, it would be definitely positive. Totally new electronic band structure is obtained by different edge-termination atoms. In addition, only a fraction of impurity atom can also much affect on the material properties of GNR. In order to perform device simulations of non-uniform GNR devices, multiscale simulation scheme can be used in non-equilibrium Green's function (NEGF) formalism and density-functional method.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

Review of GaN-based devices for terahertz operation

NASA Astrophysics Data System (ADS)

Ahi, Kiarash

2017-09-01

GaN provides the highest electron saturation velocity, breakdown voltage, operation temperature, and thus the highest combined frequency-power performance among commonly used semiconductors. The industrial need for compact, economical, high-resolution, and high-power terahertz (THz) imaging and spectroscopy systems are promoting the utilization of GaN for implementing the next generation of THz systems. As it is reviewed, the mentioned characteristics of GaN together with its capabilities of providing high two-dimensional election densities and large longitudinal optical phonon of ˜90 meV make it one of the most promising semiconductor materials for the future of the THz emitters, detectors, mixers, and frequency multiplicators. GaN-based devices have shown capabilities of operation in the upper THz frequency band of 5 to 12 THz with relatively high photon densities in room temperature. As a result, THz imaging and spectroscopy systems with high resolution and deep depth of penetration can be realized through utilizing GaN-based devices. A comprehensive review of the history and the state of the art of GaN-based electronic devices, including plasma heterostructure field-effect transistors, negative differential resistances, hetero-dimensional Schottky diodes, impact avalanche transit times, quantum-cascade lasers, high electron mobility transistors, Gunn diodes, and tera field-effect transistors together with their impact on the future of THz imaging and spectroscopy systems is provided.

Graphene field-effect transistors as room-temperature terahertz detectors.

PubMed

Vicarelli, L; Vitiello, M S; Coquillat, D; Lombardo, A; Ferrari, A C; Knap, W; Polini, M; Pellegrini, V; Tredicucci, A

2012-10-01

The unique optoelectronic properties of graphene make it an ideal platform for a variety of photonic applications, including fast photodetectors, transparent electrodes in displays and photovoltaic modules, optical modulators, plasmonic devices, microcavities, and ultra-fast lasers. Owing to its high carrier mobility, gapless spectrum and frequency-independent absorption, graphene is a very promising material for the development of detectors and modulators operating in the terahertz region of the electromagnetic spectrum (wavelengths in the hundreds of micrometres), still severely lacking in terms of solid-state devices. Here we demonstrate terahertz detectors based on antenna-coupled graphene field-effect transistors. These exploit the nonlinear response to the oscillating radiation field at the gate electrode, with contributions of thermoelectric and photoconductive origin. We demonstrate room temperature operation at 0.3 THz, showing that our devices can already be used in realistic settings, enabling large-area, fast imaging of macroscopic samples.

One-Dimensional Nanostructures and Devices of II–V Group Semiconductors

PubMed Central

2009-01-01

The II–V group semiconductors, with narrow band gaps, are important materials with many applications in infrared detectors, lasers, solar cells, ultrasonic multipliers, and Hall generators. Since the first report on trumpet-like Zn3P2nanowires, one-dimensional (1-D) nanostructures of II–V group semiconductors have attracted great research attention recently because these special 1-D nanostructures may find applications in fabricating new electronic and optoelectronic nanoscale devices. This article covers the 1-D II–V semiconducting nanostructures that have been synthesized till now, focusing on nanotubes, nanowires, nanobelts, and special nanostructures like heterostructured nanowires. Novel electronic and optoelectronic devices built on 1-D II–V semiconducting nanostructures will also be discussed, which include metal–insulator-semiconductor field-effect transistors, metal-semiconductor field-effect transistors, andp–nheterojunction photodiode. We intent to provide the readers a brief account of these exciting research activities. PMID:20596452

Two dimensional analytical model for a reconfigurable field effect transistor

NASA Astrophysics Data System (ADS)

Ranjith, R.; Jayachandran, Remya; Suja, K. J.; Komaragiri, Rama S.

2018-02-01

This paper presents two-dimensional potential and current models for a reconfigurable field effect transistor (RFET). Two potential models which describe subthreshold and above-threshold channel potentials are developed by solving two-dimensional (2D) Poisson's equation. In the first potential model, 2D Poisson's equation is solved by considering constant/zero charge density in the channel region of the device to get the subthreshold potential characteristics. In the second model, accumulation charge density is considered to get above-threshold potential characteristics of the device. The proposed models are applicable for the device having lightly doped or intrinsic channel. While obtaining the mathematical model, whole body area is divided into two regions: gated region and un-gated region. The analytical models are compared with technology computer-aided design (TCAD) simulation results and are in complete agreement for different lengths of the gated regions as well as at various supply voltage levels.

Electrical characteristics of proton-irradiated Sc2O3 passivated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Luo, B.; Kim, Jihyun; Ren, F.; Gillespie, J. K.; Fitch, R. C.; Sewell, J.; Dettmer, R.; Via, G. D.; Crespo, A.; Jenkins, T. J.; Gila, B. P.; Onstine, A. H.; Allums, K. K.; Abernathy, C. R.; Pearton, S. J.; Dwivedi, R.; Fogarty, T. N.; Wilkins, R.

2003-03-01

Sc2O3-passivated AlGaN/GaN high electron mobility transistors (HEMTs) were irradiated with 40 MeV protons to a fluence corresponding to approximately 10 years in low-earth orbit (5×109 cm-2). Devices with an AlGaN cap layer showed less degradation in dc characteristics than comparable GaN-cap devices, consistent with differences in average band energy. The changes in device performance could be attributed completely to bulk trapping effects, demonstrating that the effectiveness of the Sc2O3 layers in passivating surface states in the drain-source region was undiminished by the proton irradiation. Sc2O3-passivated AlGaN/HEMTs appear to be attractive candidates for space and terrestrial applications where resistance to high fluxes of ionizing radiation is a criteria.

A new method to determine the 2DEG density distribution for passivated AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Fu, Chen; Lin, Zhaojun; Cui, Peng; Lv, Yuanjie; Zhou, Yang; Dai, Gang; Luan, Chongbiao; Liu, Huan; Cheng, Aijie

2018-01-01

A new method to determine the two-dimensional electron gas (2DEG) density distribution of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) after the Si3N4 passivation process has been presented. Detailed device characteristics were investigated and better transport properties have been observed for the passivated devices. The strain variation and the influence of the surface trapping states were analyzed. By using the polarization Coulomb field (PCF) scattering theory, the 2DEG density after passivation was both quantitively and qualitatively determined, which has been increased by 45% under the access regions and decreased by 2% under the gate region.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

PubMed

Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

2014-11-12

Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Lee, Yong Hee; Joo, Seung Ki

2017-06-01

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. He received the B.S. degree in School of Advanced Materials Engineering from Kookmin University, Seoul, South Korea in 2012, and the M.S. degree in Department of Materials Science and Engineering from Seoul National University, Seoul, South Korea in 2014. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and top-gate polycrystalline-silicon thin-film transistors. He received the M.S. degree in innovation technology from Ecol Polytechnique, Palaiseau, France in 2013. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and copper-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1974, and the M.S. and Ph.D. degrees in material science and engineering from Stanford University, Stanford, CA, USA, in 1980 and 1983, respectively. He is currently a Professor with the Department of Materials Science and Engineering, Seoul National University, Seoul.

In-plane Schottky-barrier field-effect transistors based on 1T/2H heterojunctions of transition-metal dichalcogenides

NASA Astrophysics Data System (ADS)

Fan, Zhi-Qiang; Jiang, Xiang-Wei; Luo, Jun-Wei; Jiao, Li-Ying; Huang, Ru; Li, Shu-Shen; Wang, Lin-Wang

2017-10-01

As Moore's law approaches its end, two-dimensional (2D) materials are intensely studied for their potentials as one of the "More than Moore' (MM) devices. However, the ultimate performance limits and the optimal design parameters for such devices are still unknown. One common problem for the 2D-material-based device is the relative weak on-current. In this study, two-dimensional Schottky-barrier field-effect transistors (SBFETs) consisting of in-plane heterojunctions of 1T metallic-phase and 2H semiconducting-phase transition-metal dichalcogenides (TMDs) are studied following the recent experimental synthesis of such devices at a much larger scale. Our ab initio simulation reveals the ultimate performance limits of such devices and offers suggestions for better TMD materials. Our study shows that the Schottky-barrier heights (SBHs) of the in-plane 1T/2H contacts are smaller than the SBHs of out-of-plane contacts, and the contact coupling is also stronger in the in-plane contact. Due to the atomic thickness of the monolayer TMD, the average subthreshold swing of the in-plane TMD-SBFETs is found to be close to the limit of 60 mV/dec, and smaller than that of the out-of-plane TMD-SBFET device. Different TMDs are considered and it is found that the in-plane WT e2-SBFET provides the best performance and can satisfy the performance requirement of the sub-10-nm high-performance transistor outlined by the International Technology Roadmap for Semiconductors, and thus could be developed into a viable sub-10-nm MM device in the future.

Method for manufacturing compound semiconductor field-effect transistors with improved DC and high frequency performance

DOEpatents

Zolper, John C.; Sherwin, Marc E.; Baca, Albert G.

2000-01-01

A method for making compound semiconductor devices including the use of a p-type dopant is disclosed wherein the dopant is co-implanted with an n-type donor species at the time the n-channel is formed and a single anneal at moderate temperature is then performed. Also disclosed are devices manufactured using the method. In the preferred embodiment n-MESFETs and other similar field effect transistor devices are manufactured using C ions co-implanted with Si atoms in GaAs to form an n-channel. C exhibits a unique characteristic in the context of the invention in that it exhibits a low activation efficiency (typically, 50% or less) as a p-type dopant, and consequently, it acts to sharpen the Si n-channel by compensating Si donors in the region of the Si-channel tail, but does not contribute substantially to the acceptor concentration in the buried p region. As a result, the invention provides for improved field effect semiconductor and related devices with enhancement of both DC and high-frequency performance.

A study of effects of electrode contacts on performance of organic-based light-emitting field-effect transistors

NASA Astrophysics Data System (ADS)

Kim, Dae-Kyu; Choi, Jong-Ho

2018-02-01

Herein is presented a comparative performance analysis of heterojunction organic-based light-emitting field-effect transistors (OLEFETs) with symmetric (Au only) and asymmetric (Au and LiF/Al) electrode contacts. The devices had a top source-drain contact with long-channel geometry and were produced by sequentially depositing p-type pentacene and n-type N,N‧-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) using a neutral cluster beam deposition apparatus. The spectroscopic, structural and morphological properties of the organic thin films were examined using photoluminescence (PL) spectroscopy, X-ray diffraction (XRD) method, laser scanning confocal and atomic force microscopy (LSCM, AFM). Based upon the growth of high-quality, well-packed crystalline thin films, the devices demonstrated ambipolar field-effect characteristics, stress-free operational stability, and light emission under ambient conditions. Various device parameters were derived from the fits of the observed characteristics. The hole mobilities were nearly equal irrespective of the electrode contacts, whereas the electron mobilities of the transistors with LiF/Al drain electrodes were higher due to the low injection barrier. For the OLEFETs with symmetric electrodes, electroluminescence (EL) occurred only in the vicinity of the hole-injecting electrode, whereas for the OLEFETs with asymmetric electrodes, the emission occurred in the vicinity of both hole- and electron-injecting electrodes. By tuning the carrier injection and transport through high- and low-work function metals, the hole-electron recombination sites could be controlled. The operating conduction and light emission mechanism are discussed with the aid of EL images obtained using a charge-coupled device (CCD) camera.

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Cycling excitation process: An ultra efficient and quiet signal amplification mechanism in semiconductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Yu-Hsin; Yan, Lujiang; Zhang, Alex Ce

2015-08-03

Signal amplification, performed by transistor amplifiers with its merit rated by the efficiency and noise characteristics, is ubiquitous in all electronic systems. Because of transistor thermal noise, an intrinsic signal amplification mechanism, impact ionization was sought after to complement the limits of transistor amplifiers. However, due to the high operation voltage (30-200 V typically), low power efficiency, limited scalability, and, above all, rapidly increasing excess noise with amplification factor, impact ionization has been out of favor for most electronic systems except for a few applications such as avalanche photodetectors and single-photon Geiger detectors. Here, we report an internal signal amplification mechanismmore » based on the principle of the phonon-assisted cycling excitation process (CEP). Si devices using this concept show ultrahigh gain, low operation voltage, CMOS compatibility, and, above all, quantum limit noise performance that is 30 times lower than devices using impact ionization. Established on a unique physical effect of attractive properties, CEP-based devices can potentially revolutionize the fields of semiconductor electronics.« less

Nonlinear Contact Effects in Staggered Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fischer, Axel; Zündorf, Hilke; Kaschura, Felix; Widmer, Johannes; Leo, Karl; Kraft, Ulrike; Klauk, Hagen

2017-11-01

The static and dynamic electrical characteristics of thin-film transistors (TFTs) are often limited by the parasitic contact resistances, especially for TFTs with a small channel length. For the smallest possible contact resistance, the staggered device architecture has a general advantage over the coplanar architecture of a larger injection area. Since the charge transport occurs over an extended area, it is inherently more difficult to develop an accurate analytical device model for staggered TFTs. Most analytical models for staggered TFTs, therefore, assume that the contact resistance is linear, even though this is commonly accepted not to be the case. Here, we introduce a semiphenomenological approach to accurately fit experimental data based on a highly discretized equivalent network circuit explicitly taking into account the inherent nonlinearity of the contact resistance. The model allows us to investigate the influence of nonlinear contact resistances on the static and dynamic performance of staggered TFTs for different contact layouts with a relatively short computation time. The precise extraction of device parameters enables us to calculate the transistor behavior as well as the potential for optimization in real circuits.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

PubMed

Shih, Cheng Wei; Chin, Albert

2016-08-03

At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications.

Low-voltage organic field effect transistors with a 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene semiconductor layer.

PubMed

Amin, Atefeh Y; Khassanov, Artoem; Reuter, Knud; Meyer-Friedrichsen, Timo; Halik, Marcus

2012-10-10

An asymmetric n-alkyl substitution pattern was realized in 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene (C(13)-BTBT) in order to improve the charge transport properties in organic thin-film transistors. We obtained large hole mobilities up to 17.2 cm(2)/(V·s) in low-voltage operating devices. The large mobility is related to densely packed layers of the BTBT π-systems at the channel interface dedicated to the substitution motif and confirmed by X-ray reflectivity measurements. The devices exhibit promising stability in continuous operation for several hours in ambient air.

New Frontier Process using Bio Technology

DTIC Science & Technology

2013-02-05

p.58-59,2012. (2) H.Yamazaki, M.Fujii, Y.Ueoka, Y.ishikawa, M.Fujiwara, E.Takahashi, Y.Uraoka, “Highly Reliable a-InGaZnO Thin Film Transistors ...Electron Traps in SiO2/ IGZO Interface by Cyclic Capacitance–Voltage Method”, IEEE/ 2012 International Meeting for Future of Electron Devices, Kansai...Horita, Yasuaki Ishikawa, Yukiharu Uraoka, and Shinji Koh, “Characterizatio of Graphene Based Field Effect Transistors Using Nano Probing Microscopy

The role of contact resistance in graphene field-effect devices

NASA Astrophysics Data System (ADS)

Giubileo, Filippo; Di Bartolomeo, Antonio

2017-08-01

The extremely high carrier mobility and the unique band structure, make graphene very useful for field-effect transistor applications. According to several works, the primary limitation to graphene based transistor performance is not related to the material quality, but to extrinsic factors that affect the electronic transport properties. One of the most important parasitic element is the contact resistance appearing between graphene and the metal electrodes functioning as the source and the drain. Ohmic contacts to graphene, with low contact resistances, are necessary for injection and extraction of majority charge carriers to prevent transistor parameter fluctuations caused by variations of the contact resistance. The International Technology Roadmap for Semiconductors, toward integration and down-scaling of graphene electronic devices, identifies as a challenge the development of a CMOS compatible process that enables reproducible formation of low contact resistance. However, the contact resistance is still not well understood despite it is a crucial barrier towards further improvements. In this paper, we review the experimental and theoretical activity that in the last decade has been focusing on the reduction of the contact resistance in graphene transistors. We will summarize the specific properties of graphene-metal contacts with particular attention to the nature of metals, impact of fabrication process, Fermi level pinning, interface modifications induced through surface processes, charge transport mechanism, and edge contact formation.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

PubMed Central

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

PubMed

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

The study of VOPc thin film transistors on modified substrates

NASA Astrophysics Data System (ADS)

Song, De; Xu, Qi; Cheng, Hongcang; Li, Bao-zeng; Shang, Yubin

2018-02-01

The vanadyl phthalocyanine (VOPc) organic thin film transistors (OTFTs) were fabricated on the various organosilane self-assembled monolayer (SAM) modified substrates. And the effect of the surface properties on the performance of these transistors was studied. The atomic force morphologies and X-ray diffraction (XRD) spectrums of vanadyl phthalocyanine films on different SAM-modified surfaces were studied. They reveal that the terminal functional groups of organosilane affect the growth of VOPc film and device performance. The VOPc film on octadecyltrichlorosilane (OTS) modified substrate has larger crystal size and effective crystal thickness than those on phenyltrichlorosilane (PTS), 1H,1H,2H,2H-Perfluorodec-yltrichlorosilane (FDTS) as well as non-modified substrate, which contributes the mobility of corresponding device several and several dozen times relative to other ones. The effective crystal thickness and crystal grain size of VOPc film on PTS is between that on OTS treated and that on non-modified substrate due to the stronger attractive force between VOPc and SiO2. The VOPc films' performance and effective crystal thickness on FDTS treated are worse than that on PTS due to the existents of attractive force between -CF3 and VOPc.

Real-time detection of mercury ions in water using a reduced graphene oxide/DNA field-effect transistor with assistance of a passivation layer

DOE PAGES

Chang, Jingbo; Zhou, Guihua; Gao, Xianfeng; ...

2015-08-01

Field-effect transistor (FET) sensors based on reduced graphene oxide (rGO) for detecting chemical species provide a number of distinct advantages, such as ultrasensitivity, label-free, and real-time response. However, without a passivation layer, channel materials directly exposed to an ionic solution could generate multiple signals from ionic conduction through the solution droplet, doping effect, and gating effect. Therefore, a method that provides a passivation layer on the surface of rGO without degrading device performance will significantly improve device sensitivity, in which the conductivity changes solely with the gating effect. In this work, we report rGO FET sensor devices with Hg 2+-dependentmore » DNA as a probe and the use of an Al 2O 3 layer to separate analytes from conducting channel materials. The device shows good electronic stability, excellent lower detection limit (1 nM), and high sensitivity for real-time detection of Hg 2+ in an underwater environment. Our work shows that optimization of an rGO FET structure can provide significant performance enhancement and profound fundamental understanding for the sensor mechanism.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Carbon Based Transistors and Nanoelectronic Devices

NASA Astrophysics Data System (ADS)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the effect of nanotube network density was explained in detail. On the other hand, graphene transfer technology was explored here as well. Annealing techniques were utilized to deposit clean graphene on arbitrary substrates. Raman spectroscopy and Raman data analysis was used to confirm the clean process. Furthermore, suspended graphene membrane was fabricated using single and multi-layer graphene films. This can make a major impact on graphene based transistors and bio-nano sensors technology.

Total-dose radiation effects data for semiconductor devices, volume 3

NASA Technical Reports Server (NTRS)

Price, W. E.; Martin, K. E.; Nichols, D. K.; Gauthier, M. K.; Brown, S. F.

1982-01-01

Volume 3 of this three-volume set provides a detailed analysis of the data in Volumes 1 and 2, most of which was generated for the Galileo Orbiter Program in support of NASA space programs. Volume 1 includes total ionizing dose radiation test data on diodes, bipolar transistors, field effect transistors, and miscellaneous discrete solid-state devices. Volume 2 includes similar data on integrated circuits and a few large-scale integrated circuits. The data of Volumes 1 and 2 are combined in graphic format in Volume 3 to provide a comparison of radiation sensitivities of devices of a given type and different manufacturer, a comparison of multiple tests for a single data code, a comparison of multiple tests for a single lot, and a comparison of radiation sensitivities vs time (date codes). All data were generated using a steady-state 2.5-MeV electron source (Dynamitron) or a Cobalt-60 gamma ray source. The data that compose Volume 3 represent 26 different device types, 224 tests, and a total of 1040 devices. A comparison of the effects of steady-state electrons and Cobat-60 gamma rays is also presented.

Improvement in the performance of graphene nanoribbon p-i-n tunneling field effect transistors by applying lightly doped profile on drain region

NASA Astrophysics Data System (ADS)

Naderi, Ali

2017-12-01

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrödinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain-source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

Combinatorial study of zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Acoustic transistor: Amplification and switch of sound by sound

NASA Astrophysics Data System (ADS)

Liang, Bin; Kan, Wei-wei; Zou, Xin-ye; Yin, Lei-lei; Cheng, Jian-chun

2014-08-01

We designed an acoustic transistor to manipulate sound in a manner similar to the manipulation of electric current by its electrical counterpart. The acoustic transistor is a three-terminal device with the essential ability to use a small monochromatic acoustic signal to control a much larger output signal within a broad frequency range. The output and controlling signals have the same frequency, suggesting the possibility of cascading the structure to amplify an acoustic signal. Capable of amplifying and switching sound by sound, acoustic transistors have various potential applications and may open the way to the design of conceptual devices such as acoustic logic gates.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Organic-inorganic hybrid materials as semiconducting channels in thin-film field-effect transistors

PubMed

Kagan; Mitzi; Dimitrakopoulos

1999-10-29

Organic-inorganic hybrid materials promise both the superior carrier mobility of inorganic semiconductors and the processability of organic materials. A thin-film field-effect transistor having an organic-inorganic hybrid material as the semiconducting channel was demonstrated. Hybrids based on the perovskite structure crystallize from solution to form oriented molecular-scale composites of alternating organic and inorganic sheets. Spin-coated thin films of the semiconducting perovskite (C(6)H(5)C(2)H(4)NH(3))(2)SnI(4) form the conducting channel, with field-effect mobilities of 0.6 square centimeters per volt-second and current modulation greater than 10(4). Molecular engineering of the organic and inorganic components of the hybrids is expected to further improve device performance for low-cost thin-film transistors.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Quantum transport properties of carbon nanotube field-effect transistors with electron-phonon coupling

NASA Astrophysics Data System (ADS)

Ishii, Hiroyuki; Kobayashi, Nobuhiko; Hirose, Kenji

2007-11-01

We investigated the electron-phonon coupling effects on the electronic transport properties of metallic (5,5)- and semiconducting (10,0)-carbon nanotube devices. We calculated the conductance and mobility of the carbon nanotubes with micron-order lengths at room temperature, using the time-dependent wave-packet approach based on the Kubo-Greenwood formula within a tight-binding approximation. We investigated the scattering effects of both longitudinal acoustic and optical phonon modes on the transport properties. The electron-optical phonon coupling decreases the conductance around the Fermi energy for the metallic carbon nanotubes, while the conductance of semiconductor nanotubes is decreased around the band edges by the acoustic phonons. Furthermore, we studied the Schottky-barrier effects on the mobility of the semiconducting carbon nanotube field-effect transistors for various gate voltages. We clarified how the electron mobilities of the devices are changed by the acoustic phonon.

On-wafer, cryogenic characterization of ultra-low noise HEMT devices

NASA Technical Reports Server (NTRS)

Bautista, J. J.; Laskar, J.; Szydlik, P.

1995-01-01

Significant advances in the development of high electron-mobility field-effect transistors (HEMT's) have resulted in cryogenic, low-noise amplifiers (LNA's) whose noise temperatures are within an order of magnitude of the quantum noise limit (hf/k). Further advances in HEMT technology at cryogenic temperatures may eventually lead to the replacement of maser and superconducting insulator superconducting front ends in the 1- to 100-GHz frequency band. Key to identification of the best HEMT's and optimization of cryogenic LNA's are accurate and repeatable device measurements at cryogenic temperatures. This article describes the design and operation of a cryogenic coplanar waveguide probe system for the characterization and modeling of advanced semiconductor transistors at cryogenic temperatures. Results on advanced HEMT devices are presented to illustrate the utility of the measurement system.

Laser-induced local activation of Mg-doped GaN with a high lateral resolution for high power vertical devices

NASA Astrophysics Data System (ADS)

Kurose, Noriko; Matsumoto, Kota; Yamada, Fumihiko; Roffi, Teuku Muhammad; Kamiya, Itaru; Iwata, Naotaka; Aoyagi, Yoshinobu

2018-01-01

A method for laser-induced local p-type activation of an as-grown Mg-doped GaN sample with a high lateral resolution is developed for realizing high power vertical devices for the first time. As-grown Mg-doped GaN is converted to p-type GaN in a confined local area. The transition from an insulating to a p-type area is realized to take place within about 1-2 μm fine resolution. The results show that the technique can be applied in fabricating the devices such as vertical field effect transistors, vertical bipolar transistors and vertical Schottkey diode so on with a current confinement region using a p-type carrier-blocking layer formed by this technique.

High-Performance Sensors Based on Resistance Fluctuations of Single-Layer-Graphene Transistors.

PubMed

Amin, Kazi Rafsanjani; Bid, Aveek

2015-09-09

One of the most interesting predicted applications of graphene-monolayer-based devices is as high-quality sensors. In this article, we show, through systematic experiments, a chemical vapor sensor based on the measurement of low-frequency resistance fluctuations of single-layer-graphene field-effect-transistor devices. The sensor has extremely high sensitivity, very high specificity, high fidelity, and fast response times. The performance of the device using this scheme of measurement (which uses resistance fluctuations as the detection parameter) is more than 2 orders of magnitude better than a detection scheme in which changes in the average value of the resistance is monitored. We propose a number-density-fluctuation-based model to explain the superior characteristics of a noise-measurement-based detection scheme presented in this article.

Increasing the dynamic range of CMOS photodiode imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor)

2007-01-01

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V. A. L.

2013-02-01

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics.The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics. Electronic supplementary information (ESI) available: UV-vis spectrum of Au nanoparticle aqueous solution, transfer characteristics of the transistors without inserting an Au nanoparticle monolayer, AFM image of the pentacene layer, transfer characteristics at different program voltages and memory windows with respect to the P/E voltage. See DOI: 10.1039/c2nr32579a

Flexible Organic Electronics for Use in Neural Sensing

PubMed Central

Bink, Hank; Lai, Yuming; Saudari, Sangameshwar R.; Helfer, Brian; Viventi, Jonathan; Van der Spiegel, Jan; Litt, Brian; Kagan, Cherie

2016-01-01

Recent research in brain-machine interfaces and devices to treat neurological disease indicate that important network activity exists at temporal and spatial scales beyond the resolution of existing implantable devices. High density, active electrode arrays hold great promise in enabling high-resolution interface with the brain to access and influence this network activity. Integrating flexible electronic devices directly at the neural interface can enable thousands of multiplexed electrodes to be connected using many fewer wires. Active electrode arrays have been demonstrated using flexible, inorganic silicon transistors. However, these approaches may be limited in their ability to be cost-effectively scaled to large array sizes (8×8 cm). Here we show amplifiers built using flexible organic transistors with sufficient performance for neural signal recording. We also demonstrate a pathway for a fully integrated, amplified and multiplexed electrode array built from these devices. PMID:22255558

Gallium Arsenide Monolithic Optoelectronic Circuits

NASA Astrophysics Data System (ADS)

Bar-Chaim, N.; Katz, J.; Margalit, S.; Ury, I.; Wilt, D.; Yariv, A.

1981-07-01

The optical properties of GaAs make it a very useful material for the fabrication of optical emitters and detectors. GaAs also possesses electronic properties which allow the fabrication of high speed electronic devices which are superior to conventional silicon devices. Monolithic optoelectronic circuits are formed by the integration of optical and electronic devices on a single GaAs substrate. Integration of many devices is most easily accomplished on a semi-insulating (SI) sub-strate. Several laser structures have been fabricated on SI GaAs substrates. Some of these lasers have been integrated with Gunn diodes and with metal semiconductor field effect transistors (MESFETs). An integrated optical repeater has been demonstrated in which MESFETs are used for optical detection and electronic amplification, and a laser is used to regenerate the optical signal. Monolithic optoelectronic circuits have also been constructed on conducting substrates. A heterojunction bipolar transistor driver has been integrated with a laser on an n-type GaAs substrate.

Charge injection in solution-processed organic field-effect transistors: physics, models and characterization methods.

PubMed

Natali, Dario; Caironi, Mario

2012-03-15

A high-mobility organic semiconductor employed as the active material in a field-effect transistor does not guarantee per se that expectations of high performance are fulfilled. This is even truer if a downscaled, short channel is adopted. Only if contacts are able to provide the device with as much charge as it needs, with a negligible voltage drop across them, then high expectations can turn into high performances. It is a fact that this is not always the case in the field of organic electronics. In this review, we aim to offer a comprehensive overview on the subject of current injection in organic thin film transistors: physical principles concerning energy level (mis)alignment at interfaces, models describing charge injection, technologies for interface tuning, and techniques for characterizing devices. Finally, a survey of the most recent accomplishments in the field is given. Principles are described in general, but the technologies and survey emphasis is on solution processed transistors, because it is our opinion that scalable, roll-to-roll printing processing is one, if not the brightest, possible scenario for the future of organic electronics. With the exception of electrolyte-gated organic transistors, where impressively low width normalized resistances were reported (in the range of 10 Ω·cm), to date the lowest values reported for devices where the semiconductor is solution-processed and where the most common architectures are adopted, are ∼10 kΩ·cm for transistors with a field effect mobility in the 0.1-1 cm(2)/Vs range. Although these values represent the best case, they still pose a severe limitation for downscaling the channel lengths below a few micrometers, necessary for increasing the device switching speed. Moreover, techniques to lower contact resistances have been often developed on a case-by-case basis, depending on the materials, architecture and processing techniques. The lack of a standard strategy has hampered the progress of the field for a long time. Only recently, as the understanding of the rather complex physical processes at the metal/semiconductor interfaces has improved, more general approaches, with a validity that extends to several materials, are being proposed and successfully tested in the literature. Only a combined scientific and technological effort, on the one side to fully understand contact phenomena and on the other to completely master the tailoring of interfaces, will enable the development of advanced organic electronics applications and their widespread adoption in low-cost, large-area printed circuits. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Modulation-doped β-(Al0.2Ga0.8)2O3/Ga2O3 field-effect transistor

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Sriram; Xia, Zhanbo; Joishi, Chandan; Zhang, Yuewei; McGlone, Joe; Johnson, Jared; Brenner, Mark; Arehart, Aaron R.; Hwang, Jinwoo; Lodha, Saurabh; Rajan, Siddharth

2017-07-01

Modulation-doped heterostructures are a key enabler for realizing high mobility and better scaling properties for high performance transistors. We report the realization of a modulation-doped two-dimensional electron gas (2DEG) at the β-(Al0.2Ga0.8)2O3/Ga2O3 heterojunction by silicon delta doping. The formation of a 2DEG was confirmed using capacitance voltage measurements. A modulation-doped 2DEG channel was used to realize a modulation-doped field-effect transistor. The demonstration of modulation doping in the β-(Al0.2Ga0.8)2O3/Ga2O3 material system could enable heterojunction devices for high performance electronics.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

PubMed

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

High-pressure oxygen annealing of Al2O3 passivation layer for performance enhancement of graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Kim, Yun Ji; Kim, Seung Mo; Heo, Sunwoo; Lee, Hyeji; In Lee, Ho; Chang, Kyoung Eun; Lee, Byoung Hun

2018-02-01

High-pressure annealing in oxygen ambient at low temperatures (∼300 °C) was effective in improving the performance of graphene field-effect transistors. The field-effect mobility was improved by 45% and 83% for holes and electrons, respectively. The improvement in the quality of Al2O3 and the reduction in oxygen-related charge generation at the Al2O3-graphene interface, are suggested as the reasons for this improvement. This process can be useful for the commercial implementation of graphene-based electronic devices.

Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

NASA Astrophysics Data System (ADS)

Iezekiel, Stavros; Christou, Andreas

2015-03-01

Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

Schottky barrier contrasts in single and bi-layer graphene contacts for MoS{sub 2} field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Du, Hyewon; Kim, Taekwang; Shin, Somyeong

We have investigated single- and bi-layer graphene as source-drain electrodes for n-type MoS{sub 2} transistors. Ti-MoS{sub 2}-graphene heterojunction transistors using both single-layer MoS{sub 2} (1M) and 4-layer MoS{sub 2} (4M) were fabricated in order to compare graphene electrodes with commonly used Ti electrodes. MoS{sub 2}-graphene Schottky barrier provided electron injection efficiency up to 130 times higher in the subthreshold regime when compared with MoS{sub 2}-Ti, which resulted in V{sub DS} polarity dependence of device parameters such as threshold voltage (V{sub TH}) and subthreshold swing (SS). Comparing single-layer graphene (SG) with bi-layer graphene (BG) in 4M devices, SG electrodes exhibited enhancedmore » device performance with higher on/off ratio and increased field-effect mobility (μ{sub FE}) due to more sensitive Fermi level shift by gate voltage. Meanwhile, in the strongly accumulated regime, we observed opposing behavior depending on MoS{sub 2} thickness for both SG and BG contacts. Differential conductance (σ{sub d}) of 1M increases with V{sub DS} irrespective of V{sub DS} polarity, while σ{sub d} of 4M ceases monotonic growth at positive V{sub DS} values transitioning to ohmic-like contact formation. Nevertheless, the low absolute value of σ{sub d} saturation of the 4M-graphene junction demonstrates that graphene electrode could be unfavorable for high current carrying transistors.« less

Environmental Effects on Hysteresis of Transfer Characteristics in Molybdenum Disulfide Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Shimazu, Yoshihiro; Tashiro, Mitsuki; Sonobe, Satoshi; Takahashi, Masaki

2016-07-01

Molybdenum disulfide (MoS2) has recently received much attention for nanoscale electronic and photonic applications. To explore the intrinsic properties and enhance the performance of MoS2-based field-effect transistors, thorough understanding of extrinsic effects such as environmental gas and contact resistance of the electrodes is required. Here, we report the effects of environmental gases on the transport properties of back-gated multilayered MoS2 field-effect transistors. Comparisons between different gases (oxygen, nitrogen, and air and nitrogen with varying relative humidities) revealed that water molecules acting as charge-trapping centers are the main cause of hysteresis in the transfer characteristics. While the hysteresis persisted even after pumping out the environmental gas for longer than 10 h at room temperature, it disappeared when the device was cooled to 240 K, suggesting a considerable increase in the time constant of the charge trapping/detrapping at these modestly low temperatures. The suppression of the hysteresis or instability in the easily attainable temperature range without surface passivation is highly advantageous for the device application of this system. The humidity dependence of the threshold voltages in the transfer curves indicates that the water molecules dominantly act as hole-trapping centers. A strong dependence of the on-state current on oxygen pressure was also observed.

Negative Differential Resistance and Steep Switching in Chevron Graphene Nanoribbon Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Smith, Samuel; Llinas, Juan-Pablo; Bokor, Jeffrey; Salahuddin, Sayeef

2018-01-01

Ballistic quantum transport calculations based on the non-equilbrium Green's function formalism show that field-effect transistor devices made from chevron-type graphene nanoribbons (CGNRs) could exhibit negative differential resistance with peak-to-valley ratios in excess of 4800 at room temperature as well as steep-slope switching with 6 mV/decade subtheshold swing over five orders of magnitude and ON-currents of 88$\\mu$A/$\\mu$m. This is enabled by the superlattice-like structure of these ribbons that have large periodic unit cells with regions of different effective bandgap, resulting in minibands and gaps in the density of states above the conduction band edge. The CGNR ribbon used in our proposed device has been previously fabricated with bottom-up chemical synthesis techniques and could be incorporated into an experimentally-realizable structure.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Carbon Nanotubes as FET Channel: Analog Design Optimization considering CNT Parameter Variability

NASA Astrophysics Data System (ADS)

Samar Ansari, Mohd.; Tripathi, S. K.

2017-08-01

Carbon nanotubes (CNTs), both single-walled as well as multi-walled, have been employed in a plethora of applications pertinent to semiconductor materials and devices including, but not limited to, biotechnology, material science, nanoelectronics and nano-electro mechanical systems (NEMS). The Carbon Nanotube Field Effect Transistor (CNFET) is one such electronic device which effectively utilizes CNTs to achieve a boost in the channel conduction thereby yielding superior performance over standard MOSFETs. This paper explores the effects of variability in CNT physical parameters viz. nanotube diameter, pitch, and number of CNT in the transistor channel, on the performance of a chosen analog circuit. It is further shown that from the analyses performed, an optimal design of the CNFETs can be derived for optimizing the performance of the analog circuit as per a given specification set.

Effects of Gold Nanoparticles on Pentacene Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Lee, Keanchuan; Weis, Martin; Ou-Yang, Wei; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2011-04-01

The effect of gold nanoparticles (NPs) on pentacene organic field-effect transistors (OFETs) was being investigated by both DC and AC methods, which are current-voltage (I-V) measurements in steady-state and impedance spectroscopy (IS) respectively. Here poly(vinyl alcohol) (PVA) and PVA blended with Au NPs as composite are spin-coated on SiO2 as gate-insulator for top-contact pentacene OFET. The characteristics of the device were being investigated based on the contact resistance, trapped charges, effective mobility and threshold voltage based on transfer characteristics of OFET. Results revealed that OFET with NPs exhibited larger hysteresis and higher contact resistance at high voltage region. IS measurements were performed and the fitting of results by the Maxwell-Wagner equivalent circuit showed that for device with NPs a series of capacitance and resistance which represents trapping must be introduced in order to have agreeable fitting. The fitting had helped to clarify the reason behind the higher contact resistance and bigger hysteresis which was mainly caused by the space charge field formed by the traps when Au NPs were introduced into the device.

Modeling and Design of GaN High Electron Mobility Transistors and Hot Electron Transistors through Monte Carlo Particle-based Device Simulations

NASA Astrophysics Data System (ADS)

Soligo, Riccardo

In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.

Fabrication and analysis of polymer field-effect transistors

NASA Astrophysics Data System (ADS)

Scheinert, S.; Paasch, G.

2004-05-01

Parameters of organic field-effect transistors (OFET) achieved in recent years are promising enough for R & D activities towards a commercial low-cost polymer electronics. In spite of the fast progress, preparations dominated by trial and error are concentrated essentially on higher mobility polymers and shorter channel patterning, and the analysis of measured data is based on oversimplified models. Here ways to professionalize the research on polymer field-effect transistors are discussed exploiting experience accumulated in microelectronics. First of all, designing the devices before fabricating and subsequently analyzing them requires appropriate modelling. Almost independently from the nature of the transport process, the device physics is basically described by the drift-diffusion model, combined with non-degenerate carrier statistics. Therefore, with a modified interpretation of the so-called effective density of states, existing simulation tools can be applied, except for special cases which are discussed. Analytical estimates are helpful already in designing devices, and applied to experimental data they yield input parameters for the numerical simulations. Preparations of OFET's and capacitors with poly(3-ocylthiophene) (P3OT), poly(3-dodecylthiophene) P3HT, Arylamino-poly-(phenylene-vinylene) (PPV), poly(2-methoxy, 5 ethyl (2 hexyloxy) paraphenylenevinylene) MEH-PPV, and pentacene from a soluble precursor are described, with silicon dioxide (SiO2) or poly(4-vinylphenol) (P4VP) as gate insulator, and with rather different channel length. We demonstrate the advantage of combining all steps from design/fabrication to analysis of the experimental data with analytical estimates and numerical simulation. Of special importance is the connection between mobility, transistor channel length, cut-off frequency and operation voltage, which was the starting point for the development of a low-cost fabrication of high-performance submicrometer OFET's by an underetching technique. Finally results of simulation studies are presented concerning the formation of inversion layers, the influence of a trap distribution (as in the a-Si model) and of different types of source/drain contacts on top and bottom contact OFET's, and short-channel effects in submicrometer devices.

Organic field-effect transistors using single crystals.

PubMed

Hasegawa, Tatsuo; Takeya, Jun

2009-04-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for 'plastic electronics'. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20-40 cm 2 Vs -1 , achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps.

Organic field-effect transistors using single crystals

PubMed Central

Hasegawa, Tatsuo; Takeya, Jun

2009-01-01

Organic field-effect transistors using small-molecule organic single crystals are developed to investigate fundamental aspects of organic thin-film transistors that have been widely studied for possible future markets for ‘plastic electronics’. In reviewing the physics and chemistry of single-crystal organic field-effect transistors (SC-OFETs), the nature of intrinsic charge dynamics is elucidated for the carriers induced at the single crystal surfaces of molecular semiconductors. Materials for SC-OFETs are first reviewed with descriptions of the fabrication methods and the field-effect characteristics. In particular, a benchmark carrier mobility of 20–40 cm2 Vs−1, achieved with thin platelets of rubrene single crystals, demonstrates the significance of the SC-OFETs and clarifies material limitations for organic devices. In the latter part of this review, we discuss the physics of microscopic charge transport by using SC-OFETs at metal/semiconductor contacts and along semiconductor/insulator interfaces. Most importantly, Hall effect and electron spin resonance (ESR) measurements reveal that interface charge transport in molecular semiconductors is properly described in terms of band transport and localization by charge traps. PMID:27877287

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Silicon junctionless field effect transistors as room temperature terahertz detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marczewski, J., E-mail: jmarcz@ite.waw.pl; Tomaszewski, D.; Zaborowski, M.

2015-09-14

Terahertz (THz) radiation detection by junctionless metal-oxide-semiconductor field-effect transistors (JL MOSFETs) was studied and compared with THz detection using conventional MOSFETs. It has been shown that in contrast to the behavior of standard transistors, the junctionless devices have a significant responsivity also in the open channel (low resistance) state. The responsivity for a photolithographically defined JL FET was 70 V/W and the noise equivalent power 460 pW/√Hz. Working in the open channel state may be advantageous for THz wireless and imaging applications because of its low thermal noise and possible high operating speed or large bandwidth. It has been proven that themore » junctionless MOSFETs can also operate in a zero gate bias mode, which enables simplification of the THz array circuitry. Existing models of THz detection by MOSFETs were considered and it has been demonstrated that the process of detection by these junctionless devices cannot be explained within the framework of the commonly accepted models and therefore requires a new theoretical approach.« less

Relaxed germanium-tin P-channel tunneling field-effect transistors fabricated on Si: impacts of Sn composition and uniaxial tensile strain

NASA Astrophysics Data System (ADS)

Han, Genquan; Wang, Yibo; Liu, Yan; Wang, Hongjuan; Liu, Mingshan; Zhang, Chunfu; Zhang, Jincheng; Cheng, Buwen; Hao, Yue

2015-05-01

In this work, relaxed GeSn p-channel tunneling field-effect transistors (pTFETs) with various Sn compositions are fabricated on Si. Enhancement of on-state current ION with the increase of Sn composition is observed in transistors, due to the reduction of direct bandgap EG. Ge0.93Sn0.07 and Ge0.95Sn0.05 pTFETs achieve 110% and 75% enhancement in ION, respectively, compared to Ge0.97Sn0.03 devices, at VGS - VTH = VDS = - 1.0 V. For the first time, ION enhancement in GeSn pTFET utilizing uniaxial tensile strain is reported. By applying 0.14% uniaxial tensile strain along [110] channel direction, Ge0.95Sn0.05 pTFETs achieve 12% ION improvement, over unstrained control devices at VGS - VTH = VDS = - 1.0 V. Theoretical study demonstrates that uniaxial tensile strain leads to the reduction of direct EG and affects the reduced tunneling mass, which bring the GBTBT rising, benefiting the tunneling current enhancement in GeSn TFETs.

MoS2 /Rubrene van der Waals Heterostructure: Toward Ambipolar Field-Effect Transistors and Inverter Circuits.

PubMed

He, Xuexia; Chow, WaiLeong; Liu, Fucai; Tay, BengKang; Liu, Zheng

2017-01-01

2D transition metal dichalcogenides are promising channel materials for the next-generation electronic device. Here, vertically 2D heterostructures, so called van der Waals solids, are constructed using inorganic molybdenum sulfide (MoS 2 ) few layers and organic crystal - 5,6,11,12-tetraphenylnaphthacene (rubrene). In this work, ambipolar field-effect transistors are successfully achieved based on MoS 2 and rubrene crystals with the well balanced electron and hole mobilities of 1.27 and 0.36 cm 2 V -1 s -1 , respectively. The ambipolar behavior is explained based on the band alignment of MoS 2 and rubrene. Furthermore, being a building block, the MoS 2 /rubrene ambipolar transistors are used to fabricate CMOS (complementary metal oxide semiconductor) inverters that show good performance with a gain of 2.3 at a switching threshold voltage of -26 V. This work paves a way to the novel organic/inorganic ultrathin heterostructure based flexible electronics and optoelectronic devices. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of InP/In0.65Ga0.35As metamorphic p-channel doped-channel field-effect transistor

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui

2016-07-01

In this article, the device mechanism and characteristics of InP/InGaAs metamorphic p-channel field-effect transistor (FET), which has a high indium mole fraction of InGaAs channel, grown on the GaAs substrate is demonstrated. The device was fabricated on the top of the InxGa1-xP graded metamorphic buffer layer, and the In0.65Ga0.35As pseudomorphic channel was employed to elevate the transistor performance. For the p-type FET, due to the considerably large valence band discontinuity at InP/In0.65Ga0.35As heterojunction and a relatively thin as well as heavily doped pseudomorphic In0.65Ga0.35As channel between two undoped InP layers, a maximum extrinsic transconductance of 27.3 mS/mm and a maximum saturation current density of -54.3 mA/mm are obtained. Consequently, the studied metamorphic FET is suitable for the development in signal amplification, integrated circuits, and low supply-voltage complementary logic inverters.

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Hsien; Chou, Wu-Ching, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw; Chang, Ting-Chang, E-mail: tcchang3708@gmail.com, E-mail: wuchingchou@mail.nctu.edu.tw

2014-10-21

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of themore » surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.« less

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

NASA Astrophysics Data System (ADS)

Tang, Lan-Feng; Yu, Guang; Lu, Hai; Wu, Chen-Fei; Qian, Hui-Min; Zhou, Dong; Zhang, Rong; Zheng, You-Dou; Huang, Xiao-Ming

2015-08-01

The influence of white light illumination on the stability of an amorphous InGaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed. Project supported by the State Key Program for Basic Research of China (Grant Nos. 2011CB301900 and 2011CB922100) and the Priority Academic Program Development of Jiangsu Higher Education Institutions, China.

Ultrathin solution-processed single crystals of thiophene-phenylene co-oligomers for organic field-effect devices

NASA Astrophysics Data System (ADS)

Glushkova, Anastasia V.; Poimanova, Elena Yu.; Bruevich, Vladimir V.; Luponosov, Yuriy N.; Ponomarenko, Sergei A.; Paraschuk, Dmitry Yu.

2017-08-01

Thiophene-phenylene co-oligomers (TPCO) single crystals are promising materials for organic light-emitting devices, e.g., light-emitting transistors (OLETs), due to their ability to combine high luminescence and efficient charge transport. However, optical confinement in platy single crystals strongly decreases light emission from their top surface degrading the device performance. To avoid optical waveguiding, single crystals thinner than 100 nm would be beneficial. Herein, we report on solution-processed ultrathin single crystals of TPCO and study their charge transport properties. As materials we used 1,4-bis(5'-hexyl-2,2'-bithiophene-5-yl)benzene (DH-TTPTT) and 1,4-bis(5'-decyl-2,2'-bithiophene-5-yl)benzene (DD-TTPTT). The ultrathin single crystals were studied by optical polarization, atomic-force, and transmission electron microscopies, and as active layers in organic field effect transistors (OFET). The OFET hole mobility was increased tenfold for the oligomer with longer alkyl substituents (DD-TTPTT) reaching 0.2 cm2/Vs. Our studies of crystal growth indicate that if the substrate is wetted, it has no significant effect on the crystal growth. We conclude that solution-processed ultrathin TPCO single crystals are a promising platform for organic optoelectronic field-effect devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Low-Temperature, Solution-Processed, Transparent Zinc Oxide-Based Thin-Film Transistors for Sensing Various Solvents.

PubMed

You, Hsin-Chiang; Wang, Cheng-Jyun

2017-02-26

A low temperature solution-processed thin-film transistor (TFT) using zinc oxide (ZnO) film as an exposed sensing semiconductor channel was fabricated to detect and identify various solution solvents. The TFT devices would offer applications for low-cost, rapid and highly compatible water-soluble detection and could replace conventional silicon field effect transistors (FETs) as bio-sensors. In this work, we demonstrate the utility of the TFT ZnO channel to sense various liquids, such as polar solvents (ethanol), non-polar solvents (toluene) and deionized (DI) water, which were dropped and adsorbed onto the channel. It is discussed how different dielectric constants of polar/non-polar solvents and DI water were associated with various charge transport properties, demonstrating the main detection mechanisms of the thin-film transistor.

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

Low-frequency electronic noise in single-layer MoS2 transistors.

PubMed

Sangwan, Vinod K; Arnold, Heather N; Jariwala, Deep; Marks, Tobin J; Lauhon, Lincoln J; Hersam, Mark C

2013-09-11

Ubiquitous low-frequency 1/f noise can be a limiting factor in the performance and application of nanoscale devices. Here, we quantitatively investigate low-frequency electronic noise in single-layer transition metal dichalcogenide MoS2 field-effect transistors. The measured 1/f noise can be explained by an empirical formulation of mobility fluctuations with the Hooge parameter ranging between 0.005 and 2.0 in vacuum (<10(-5) Torr). The field-effect mobility decreased, and the noise amplitude increased by an order of magnitude in ambient conditions, revealing the significant influence of atmospheric adsorbates on charge transport. In addition, single Lorentzian generation-recombination noise was observed to increase by an order of magnitude as the devices were cooled from 300 to 6.5 K.

1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

PubMed Central

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-01-01

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 2.5 cm2/Vs, low threshold voltage of −2.8 V, and low leakage current of 10−12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO2-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications. PMID:29232828

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

EDITORIAL: Flexible OLEDs and organic electronics Flexible OLEDs and organic electronics

NASA Astrophysics Data System (ADS)

Kim, Jang-Joo; Han, Min-Koo; Noh, Yong-Young

2011-03-01

Following the great discovery of the electrically conducting polymer, doped polyacetylene, which was honorably recognized in 2000 with the Nobel Prize in chemistry, conjugated molecules, i.e. organic semiconductors, have become an attractive class of active elements for various electronic or opto-electronic applications. Significant effort has been made in both academia and industry to investigate π-conjugated molecules for their unique electrical or opto-electrical properties over the last three decades. The discovery of electroluminescence in conjugated small molecules in 1982 and in polymers in 1989 was a major breakthrough, bringing those molecules to commercial applications within reach for the first time in (opto-)electronic devices, such as organic light-emitting diodes (OLEDs), photovoltaic cells (OPVs), and field-effect transistors (OFETs). Nowadays, we use OLED displays in everyday life in mobile devices. The potential of these devices, which have been fabricated with conjugated molecules, lies in the possibility to combine the advantages of solution processability, chemical tunability and material strength of polymers with the typical properties of plastics, to realize low-cost, large-area electronic devices on flexible substrates by solution deposition and direct-write graphic art printing techniques. The articles in the flexible OLEDs and organic electronics special issue in Semiconductor Science and Technology deal with a diversity of topics and effectively reflect the current status of research from all over the world on various organic electronic devices, including OLEDs, OPVs, and OFETs. Firstly, S Park et al describe the recent progress in thin-film encapsulation techniques for flexible AM-OLED and large-area OLED lightings, and their applications are discussed by J-W Park et al. Flexible active-matrix OLEDs on plastics require stable and flexible thin-film transistors processed at low temperature. Metal oxide thin-film transistors are proposed as one of the best candidates for the purpose, and J K Jeong discusses their status and perspectives. Next, several excellent research articles on OFETs follow. In particular, Y-Y Noh et al introduce an interesting method to control charge injection in top-gated OFETs by insertion of various self-assembled monolayers in their paper entitled 'Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering'. We would like to thank all the authors for their contributions, which combine new results and profound overviews of the state of the art in flexible OLEDs and organic electronics areas; it is this combination that most often adds to the value of topical issues. Special thanks also go to the staff of IOP Publishing, particularly Ms Alice Malhador, for contributing to the success of this effort. In this special issue, many wonderful reviews and research articles provide a detailed overview of recent progress in OLEDs, OPVs and OFETs as well as a scientific understanding of the device physics with these materials. We sincerely believe this special issue is a timely publication and will give productive information to a broad range of readers. Flexible OLEDs and organic electronics Contents Thin film encapsulation for flexible AM-OLED: a review Jin-Seong Park, Heeyeop Chae, Ho Kyoon Chung and Sang In Lee Large-area OLED lightings and their applications J W Park, D C Shin and S H Park Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering Yong-Young Noh, Xiaoyang Cheng, Marta Tello, Mi-Jung Lee and Henning Sirringhaus Branched polythiophene as a new amorphous semiconducting polymer for an organic field-effect transistor Makoto Karakawa, Yutaka Ie and Yoshio Aso Influence of mechanical strain on the electrical properties of flexible organic thin-film transistors Fang-Chung Chen, Tzung-Da Chen, Bing-Ruei Zeng and Ya-Wei Chung Frequency operation of low-voltage, solution-processed organic field-effect transistors M Caironi, Y-Y Noh and H Sirringhaus Nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting channel Sung-Min Yoon, Shinhyuk Yang, Chun-Won Byun, Soon-Won Jung, Min-Ki Ryu, Sang-Hee Ko Park, ByeongHoon Kim, Himchan Oh, Chi-Sun Hwang and Byoung-Gon Yu The status and perspectives of metal oxide thin-film transistors for active matrix flexible displays Jae Kyeong Jeong Vertical phase segregation of hybrid poly(3-hexylthiophene) and fullerene derivative composites controlled via velocity of solvent drying Tao Song, Zhongwei Wu, Yingfen Tu, Yizheng Jin and Baoquan Sun Variations of cell performance in ITO-free organic solar cells with increasing cell areas Jun-Seok Yeo, Jin-Mun Yun, Seok-Soon Kim, Dong-Yu Kim, Junkyung Kim and Seok-In Na

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

Models of second-order effects in metal-oxide-semiconductor field-effect transistors for computer applications

NASA Technical Reports Server (NTRS)

Benumof, Reuben; Zoutendyk, John; Coss, James

1988-01-01

Second-order effects in metal-oxide-semiconductor field-effect transistors (MOSFETs) are important for devices with dimensions of 2 microns or less. The short and narrow channel effects and drain-induced barrier lowering primarily affect threshold voltage, but formulas for drain current must also take these effects into account. In addition, the drain current is sensitive to channel length modulation due to pinch-off or velocity saturation and is diminished by electron mobility degradation due to normal and lateral electric fields in the channel. A model of a MOSFET including these considerations and emphasizing charge conservation is discussed.

Interlayer tunnel field-effect transistor (ITFET): physics, fabrication and applications

NASA Astrophysics Data System (ADS)

Kang, Sangwoo; Mou, Xuehao; Fallahazad, Babak; Prasad, Nitin; Wu, Xian; Valsaraj, Amithraj; Movva, Hema C. P.; Kim, Kyounghwan; Tutuc, Emanuel; Register, Leonard F.; Banerjee, Sanjay K.

2017-09-01

The scaling challenges of complementary metal oxide semiconductors (CMOS) are increasing with the pace of scaling showing marked signs of slowing down. This slowing has brought about a widespread search for an alternative beyond-CMOS device concept. While the charge tunneling phenomenon has been known for almost a century, and tunneling based transistors have been studied in the past few decades, its possibilities are being re-examined with the emergence of a new class of two-dimensional (2D) materials. By stacking varying 2D materials together, with two electrode layers sandwiching a tunnel dielectric layer, it could be possible to make vertical tunnel transistors without the limitations that have plagued such devices implemented within other material systems. When the two electrode layers are of the same material, under certain conditions, one can achieve resonant tunneling between the two layers, manifesting as negative differential resistance (NDR) in the interlayer current-voltage characteristics. We call this type of device an interlayer tunnel FET (ITFET). We review the basic operation principles of this device, experimental and theoretical studies, and benchmark simulation results for several digital logic gates based on a compact model that we developed. The results are placed in the context of work going on in other groups.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor.

PubMed

Nomura, Kenji; Ohta, Hiromichi; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

2003-05-23

We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of approximately 106 and a field-effect mobility of approximately 80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

A more than six orders of magnitude UV-responsive organic field-effect transistor utilizing a benzothiophene semiconductor and Disperse Red 1 for enhanced charge separation.

PubMed

Smithson, Chad S; Wu, Yiliang; Wigglesworth, Tony; Zhu, Shiping

2015-01-14

A more than six orders of magnitude UV-responsive organic field-effect transistor is developed using a benzothiophene (BTBT) semiconductor and strong donor-acceptor Disperse Red 1 as the traps to enhance charge separation. The device can be returned to its low drain current state by applying a short gate bias, and is completely reversible with excellent stability under ambient conditions. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

NASA Astrophysics Data System (ADS)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Novel gallium nitride based microwave noise and power heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Chumbes, Eduardo Martin

With the pioneering efforts of Isamu Akasaki of Meiji University and Shuji Nakamura of Nichia Chemical Industries in the late 1980's and early 1990's, the first long-lived candela-class blue and ultraviolet light emitting devices have finally come to fruition. Their success in conquering this Holy Grail in opto-electronics is due to their development of a new technology based remarkably on a class of semiconductor materials that has been practically ignored and overlooked by almost everyone for the past twenty years---the nitrides of Al, Ga and In and their alloys. The breakthroughs made from this new technology in the last decade of the 20th century has revolutionized and revitalized worldwide research and development efforts to the point where it is feasible for other important technologies such as high-density information storage, high-resolution full-color displays and efficient white light lamps and UV sensors to come much closer to realization. Equally important is the potential that this new technology can bring toward the development of efficient ultra-high power and high-temperature electronics that will revolutionize the aerospace and high-speed communication industries. Specifically, the large bandgap and strong polar properties of the group III-nitrides has at present allowed for the realization of simple doped and remarkably undoped AlGaN/GaN transistor structures on sapphire and SiC substrates with two-dimensional electron gas sheet densities significantly greater than that of conventional transistor structures based on GaAs and InP. This dissertation will look specifically at extending undoped AlGaN/GaN heterostructure field-effect transistors or HFETs towards more advanced system applications involving the integration of these devices onto a more advanced Si technology and looking at the feasibility of this integration. It will also address important issues similar devices on semi-insulating SiC substrates have in robust microwave low noise and linear amplification. Finally, it will look at incorporating high-temperature silicon nitride passivation as a key ingredient to developing a unique class of devices: metal-insulator-semiconductor field effect transistors or MISFETs as a means for providing efficient high power amplification without compromising performance associated with surface- and process-related dispersion. This dissertation will finally close with a brief outlook on the future outlook of these technologies.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Lin, Wei-Chun; Chen, Hao-Wei

2018-06-01

This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.

Wide-Temperature-Range Integrated Operational Amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

2007-01-01

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Analysis of charge injection and contact resistance as a function of electrode surface treatment in ambipolar polymer transistors

NASA Astrophysics Data System (ADS)

Lee, Seon Jeng; Kim, Chaewon; Jung, Seok-Heon; Di Pietro, Riccardo; Lee, Jin-Kyun; Kim, Jiyoung; Kim, Miso; Lee, Mi Jung

2018-01-01

Ambipolar organic field-effect transistors (OFETs) have both of hole and electron enhancements in charge transport. The characteristics of conjugated diketopyrrolopyrrole ambipolar OFETs depend on the metal-contact surface treatment for charge injection. To investigate the charge-injection characteristics of ambipolar transistors, these devices are processed via various types of self-assembled monolayer treatments and annealing. We conclude that treatment by the self-assembled monolayer 1-decanethiol gives the best enhancement of electron charge injection at both 100 and 300 °C annealing temperature. In addition, the contact resistance is calculated by using two methods: One is the gated four-point probe (gFPP) method that gives the voltage drop between channels, and the other is the simultaneous contact resistance extraction method, which extracts the contact resistance from the general transfer curve. We confirm that the gFPP method and the simultaneous extraction method give similar contact resistance, which means that we can extract contact resistance from the general transfer curve without any special contact pattern. Based on these characteristics of ambipolar p- and n-type transistors, we fabricate inverter devices with only one active layer. [Figure not available: see fulltext.

An organic transistor-based system for reference-less electrophysiological monitoring of excitable cells

PubMed Central

Spanu, A.; Lai, S.; Cosseddu, P.; Tedesco, M.; Martinoia, S.; Bonfiglio, A.

2015-01-01

In the last four decades, substantial advances have been done in the understanding of the electrical behavior of excitable cells. From the introduction in the early 70's of the Ion Sensitive Field Effect Transistor (ISFET), a lot of effort has been put in the development of more and more performing transistor-based devices to reliably interface electrogenic cells such as, for example, cardiac myocytes and neurons. However, depending on the type of application, the electronic devices used to this aim face several problems like the intrinsic rigidity of the materials (associated with foreign body rejection reactions), lack of transparency and the presence of a reference electrode. Here, an innovative system based on a novel kind of organic thin film transistor (OTFT), called organic charge modulated FET (OCMFET), is proposed as a flexible, transparent, reference-less transducer of the electrical activity of electrogenic cells. The exploitation of organic electronics in interfacing the living matters will open up new perspectives in the electrophysiological field allowing us to head toward a modern era of flexible, reference-less, and low cost probes with high-spatial and high-temporal resolution for a new generation of in-vitro and in-vivo monitoring platforms. PMID:25744085

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Percolative effects on noise in pentacene transistors

NASA Astrophysics Data System (ADS)

Conrad, B. R.; Cullen, W. G.; Yan, W.; Williams, E. D.

2007-12-01

Noise in pentacene thin film transistors has been measured as a function of device thickness from well above the effective conduction channel thickness to only two conducting layers. Over the entire thickness range, the spectral noise form is 1/f, and the noise parameter varies inversely with gate voltage, confirming that the noise is due to mobility fluctuations, even in the thinnest films. Hooge's parameter varies as an inverse power law with conductivity for all film thicknesses. The magnitude and transport characteristics of the spectral noise are well explained in terms of percolative effects arising from the grain boundary structure.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

High on/off ratios in bilayer graphene field effect transistors realized by surface dopants.

PubMed

Szafranek, B N; Schall, D; Otto, M; Neumaier, D; Kurz, H

2011-07-13

The unique property of bilayer graphene to show a band gap tunable by external electrical fields enables a variety of different device concepts with novel functionalities for electronic, optoelectronic, and sensor applications. So far the operation of bilayer graphene-based field effect transistors requires two individual gates to vary the channel's conductance and to create a band gap. In this paper, we report on a method to increase the on/off ratio in single gated bilayer graphene field effect transistors by adsorbate doping. The adsorbate dopants on the upper side of the graphene establish a displacement field perpendicular to the graphene surface breaking the inversion symmetry of the two graphene layers. Low-temperature measurements indicate that the increased on/off ratio is caused by the opening of a mobility gap.

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

NASA Astrophysics Data System (ADS)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown to provide consistently accurate values for base sheet resistance for both Si- and SiGe-base transistors over a wide range of temperatures. A model for plasma-induced bandgap narrowing suitable for implementation in a numerical simulator has been developed. The appropriate method of incorporating this model in a drift -diffusion solver is described. The importance of including this model for low temperature simulation is demonstrated. With these models in place, the enhanced simulator has been used for evaluating and designing the Si- and SiGe-base bipolar transistors. Silicon-germanium heterojunction bipolar transistors offer significant performance and cost advantages over conventional technologies in the production of integrated circuits for communications, computer and transportation applications. Their high frequency performance at low cost, will find widespread use in the currently exploding wireless communication market. However, the high performance SiGe-base transistors are prone to have a low common-emitter breakdown voltage. In this dissertation, a modification in the collector design is proposed for improving the breakdown voltage without sacrificing the high frequency performance. A comprehensive simulation study of p-n-p SiGe-base transistors has been performed. Different figures of merit such as drive current, current gain, cut -off frequency and Early voltage were compared between a graded germanium profile and an abrupt germanium profile. The differences in the performance level between the two profiles diminishes as the base width is scaled down.

Hot Electron Effects of Importance for Micron and Submicron Devices.

DTIC Science & Technology

1981-09-01

pair injected into the active region. That g(E) tron energy loss (in units of LO phonons do modify laser action has been shown in the 4 ,) stevia ...and x,) far away from the silicon-silicon-dioxide inter- Evoluton of the size of electronic devices. (a) Original transistor patent of John Bardeen face

New materials and techniques for improved mm wave devices

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.

1991-01-01

Current research on microwave and mm wave three terminal semiconductor devices is summarized with particular attention given to the development of the pseudomorphic InGaAs modulation-doped field effect transistor (MODFET). Application of the high-indium-concentration MODFET grown on InP in the temperature range of 120-150 K is also described.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Origin of bias-stress induced instability in organic thin-film transistors with semiconducting small-molecule/insulating polymer blend channel.

PubMed

Park, Ji Hoon; Lee, Young Tack; Lee, Hee Sung; Lee, Jun Young; Lee, Kimoon; Lee, Gyu Baek; Han, Jiwon; Kim, Tae Woong; Im, Seongil

2013-03-13

The stabilities of a blending type organic thin-film transistor with phase-separated TIPS-pentacene channel layer were characterized under the conditions of negative-bias-stress (NBS) and positive-bias-stress (PBS). During NBS, threshold voltage (Vth) shifts noticeably. NBS-imposed devices revealed interfacial trap density-of-states (DOS) at 1.56 and 1.66 eV, whereas initial device showed the DOS at only 1.56 eV, as measured by photoexcited charge-collection spectroscopy (PECCS) method. Possible origin of this newly created defect is related to ester group in PMMA, which induces some hole traps at the TIPS-pentacene/i-PMMA interface. PBS-imposed device showed little Vth shift but visible off-current increase as "back-channel" effect, which is attributed to the water molecules trapped on the TFT surface.