Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Calculation of the electron wave function in a graded-channel double-heterojunction modulation-doped field-effect transistor

NASA Technical Reports Server (NTRS)

Mui, D. S. L.; Patil, M. B.; Morkoc, H.

1989-01-01

Three double-heterojunction modulation-doped field-effect transistor structures with different channel composition are investigated theoretically. All of these transistors have an In(x)Ga(1-x)As channel sandwiched between two doped Al(0.3)Ga(0.7)As barriers with undoped spacer layers. In one of the structures, x varies from 0 from either heterojunction to 0.15 at the center of the channel quadratically; in the other two, constant values of x of 0 and 0.15 are used. The Poisson and Schroedinger equations are solved self-consistently for the electron wave function in all three cases. The results showed that the two-dimensional electron gas (2DEG) concentration in the channel of the quadratically graded structure is higher than the x = 0 one and slightly lower than the x = 0.15 one, and the mean distance of the 2DEG is closer to the center of the channel for this transistor than the other two. These two effects have important implications on the electron mobility in the channel.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

AlN/GaN heterostructures for normally-off transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shervin, Shahab; Asadirad, Mojtaba; Materials Science and Engineering Program, University of Houston, Houston, Texas 77204

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strainmore » in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.« less

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

NASA Astrophysics Data System (ADS)

Asai, Hidehiro; Mori, Takahiro; Matsukawa, Takashi; Hattori, Junichi; Endo, Kazuhiko; Fukuda, Koichi

2018-04-01

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate-drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The “synergistic” speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Tang, Fengzai; Lee, Kean B.; Guiney, Ivor; Frentrup, Martin; Barnard, Jonathan S.; Divitini, Giorgio; Zaidi, Zaffar H.; Martin, Tomas L.; Bagot, Paul A.; Moody, Michael P.; Humphreys, Colin J.; Houston, Peter A.; Oliver, Rachel A.; Wallis, David J.

2018-01-01

We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS₂ Transistors.

PubMed

Ma, Jiyeon; Yoo, Geonwook

2018-09-01

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Charge movement in a GaN-based hetero-structure field effect transistor structure with carbon doped buffer under applied substrate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooth, Alexander, E-mail: a.pooth@bristol.ac.uk; IQE; Uren, Michael J.

2015-12-07

Charge trapping and transport in the carbon doped GaN buffer of a GaN-based hetero-structure field effect transistor (HFET) has been investigated under both positive and negative substrate bias. Clear evidence of redistribution of charges in the carbon doped region by thermally generated holes is seen, with electron injection and capture observed during positive bias. Excellent agreement is found with simulations. It is shown that these effects are intrinsic to the carbon doped GaN and need to be controlled to provide reliable and efficient GaN-based power HFETs.

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

High-power flexible AlGaN/GaN heterostructure field-effect transistors with suppression of negative differential conductance

NASA Astrophysics Data System (ADS)

Oh, Seung Kyu; Cho, Moon Uk; Dallas, James; Jang, Taehoon; Lee, Dong Gyu; Pouladi, Sara; Chen, Jie; Wang, Weijie; Shervin, Shahab; Kim, Hyunsoo; Shin, Seungha; Choi, Sukwon; Kwak, Joon Seop; Ryou, Jae-Hyun

2017-09-01

We investigate thermo-electronic behaviors of flexible AlGaN/GaN heterostructure field-effect transistors (HFETs) for high-power operation of the devices using Raman thermometry, infrared imaging, and current-voltage characteristics. A large negative differential conductance observed in HFETs on polymeric flexible substrates is confirmed to originate from the decreasing mobility of the two-dimensional electron gas channel caused by the self-heating effect. We develop high-power transistors by suppressing the negative differential conductance in the flexible HFETs using chemical lift-off and modified Ti/Au/In metal bonding processes with copper (Cu) tapes for high thermal conductivity and low thermal interfacial resistance in the flexible hybrid structures. Among different flexible HFETs, the ID of the HFETs on Cu with Ni/Au/In structures decreases only by 11.3% with increasing drain bias from the peak current to the current at VDS = 20 V, which is close to that of the HFETs on Si (9.6%), solving the problem of previous flexible AlGaN/GaN transistors.

Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

NASA Astrophysics Data System (ADS)

Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

2018-05-01

An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Artificial semiconductor/insulator superlattice channel structure for high-performance oxide thin-film transistors

PubMed Central

Ahn, Cheol Hyoun; Senthil, Karuppanan; Cho, Hyung Koun; Lee, Sang Yeol

2013-01-01

High-performance thin-film transistors (TFTs) are the fundamental building blocks in realizing the potential applications of the next-generation displays. Atomically controlled superlattice structures are expected to induce advanced electric and optical performance due to two-dimensional electron gas system, resulting in high-electron mobility transistors. Here, we have utilized a semiconductor/insulator superlattice channel structure comprising of ZnO/Al2O3 layers to realize high-performance TFTs. The TFT with ZnO (5 nm)/Al2O3 (3.6 nm) superlattice channel structure exhibited high field effect mobility of 27.8 cm2/Vs, and threshold voltage shift of only < 0.5 V under positive/negative gate bias stress test during 2 hours. These properties showed extremely improved TFT performance, compared to ZnO TFTs. The enhanced field effect mobility and stability obtained for the superlattice TFT devices were explained on the basis of layer-by-layer growth mode, improved crystalline nature of the channel layers, and passivation effect of Al2O3 layers. PMID:24061388

Graphene Field Effect Transistor for Radiation Detection

NASA Technical Reports Server (NTRS)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Nature of size effects in compact models of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Torkhov, N. A., E-mail: trkf@mail.ru; Scientific-Research Institute of Semiconductor Devices, Tomsk 634050; Tomsk State University of Control Systems and Radioelectronics, Tomsk 634050

Investigations have shown that in the local approximation (for sizes L < 100 μm), AlGaN/GaN high electron mobility transistor (HEMT) structures satisfy to all properties of chaotic systems and can be described in the language of fractal geometry of fractional dimensions. For such objects, values of their electrophysical characteristics depend on the linear sizes of the examined regions, which explain the presence of the so-called size effects—dependences of the electrophysical and instrumental characteristics on the linear sizes of the active elements of semiconductor devices. In the present work, a relationship has been established for the linear model parameters of themore » equivalent circuit elements of internal transistors with fractal geometry of the heteroepitaxial structure manifested through a dependence of its relative electrophysical characteristics on the linear sizes of the examined surface areas. For the HEMTs, this implies dependences of their relative static (A/mm, mA/V/mm, Ω/mm, etc.) and microwave characteristics (W/mm) on the width d of the sink-source channel and on the number of sections n that leads to a nonlinear dependence of the retrieved parameter values of equivalent circuit elements of linear internal transistor models on n and d. Thus, it has been demonstrated that the size effects in semiconductors determined by the fractal geometry must be taken into account when investigating the properties of semiconductor objects on the levels less than the local approximation limit and designing and manufacturing field effect transistors. In general, the suggested approach allows a complex of problems to be solved on designing, optimizing, and retrieving the parameters of equivalent circuits of linear and nonlinear models of not only field effect transistors but also any arbitrary semiconductor devices with nonlinear instrumental characteristics.« less

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

Structure, transport and photoconductance of PbS quantum dot monolayers functionalized with a copper phthalocyanine derivative.

PubMed

André, A; Theurer, C; Lauth, J; Maiti, S; Hodas, M; Samadi Khoshkhoo, M; Kinge, S; Meixner, A J; Schreiber, F; Siebbeles, L D A; Braun, K; Scheele, M

2017-01-31

We simultaneously surface-functionalize PbS nanocrystals with Cu 4,4',4'',4'''-tetraaminophthalocyanine and assemble this hybrid material into macroscopic monolayers. Electron microscopy and X-ray scattering reveal a granular mesocrystalline structure with strong coherence between the atomic lattice and the superlattice of nanocrystals within each domain. Terahertz spectroscopy and field-effect transistor measurements indicate efficient coupling of holes throughout the hybrid thin film, in conjunction with a pronounced photoresponse. We demonstrate the potential of this material for optoelectronic applications by fabricating a light-effect transistor.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

A gallium phosphide high-temperature bipolar junction transistor

NASA Technical Reports Server (NTRS)

Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

1981-01-01

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Field effects in graphene in an interface contact with aqueous solutions of acetic acid and potassium hydroxide

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Yu.; Lebedev, S. P.; Lebedev, A. A.; Kumzerov, Yu. A.

2017-10-01

For the creation of new promising chemical sensors, it is very important to study the influence of the interface between graphene and aqueous solutions of acids and alkalis on the transistor characteristics of graphene. Transistor structures on the basis of graphene grown by thermal decomposition of silicon carbide were created and studied. For the interface of graphene with aqueous solutions of acetic acid and potassium hydroxide in the transistor geometry, with a variation in the gate-to-source voltage, the field effect corresponding to the hole type of charge carriers in graphene was observed. It is established that an increase in the concentration of molecular ions in these solutions leads to an increase in the dependence of the resistance of the transistor on the gate voltage.

Organic Power Electronics: Transistor Operation in the kA/cm2 Regime

PubMed Central

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Widmer, Johannes; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Leo, Karl

2017-01-01

In spite of interesting features as flexibility, organic thin-film transistors have commercially lagged behind due to the low mobilities of organic semiconductors associated with hopping transport. Furthermore, organic transistors usually have much larger channel lengths than their inorganic counterparts since high-resolution structuring is not available in low-cost production schemes. Here, we present an organic permeable-base transistor (OPBT) which, despite extremely simple processing without any high-resolution structuring, achieve a performance beyond what has so far been possible using organic semiconductors. With current densities above 1 kA cm−2 and switching speeds towards 100 MHz, they open the field of organic power electronics. Finding the physical limits and an effective mobility of only 0.06 cm2 V−1 s−1, this OPBT device architecture has much more potential if new materials optimized for its geometry will be developed. PMID:28303924

Organic Power Electronics: Transistor Operation in the kA/cm2 Regime.

PubMed

Klinger, Markus P; Fischer, Axel; Kaschura, Felix; Widmer, Johannes; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Leo, Karl

2017-03-17

In spite of interesting features as flexibility, organic thin-film transistors have commercially lagged behind due to the low mobilities of organic semiconductors associated with hopping transport. Furthermore, organic transistors usually have much larger channel lengths than their inorganic counterparts since high-resolution structuring is not available in low-cost production schemes. Here, we present an organic permeable-base transistor (OPBT) which, despite extremely simple processing without any high-resolution structuring, achieve a performance beyond what has so far been possible using organic semiconductors. With current densities above 1 kA cm -2 and switching speeds towards 100 MHz, they open the field of organic power electronics. Finding the physical limits and an effective mobility of only 0.06 cm 2  V -1  s -1 , this OPBT device architecture has much more potential if new materials optimized for its geometry will be developed.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Hafnium transistor design for neural interfacing.

PubMed

Parent, David W; Basham, Eric J

2008-01-01

A design methodology is presented that uses the EKV model and the g(m)/I(D) biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Structured-gate organic field-effect transistors

NASA Astrophysics Data System (ADS)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Prediction and theoretical characterization of p-type organic semiconductor crystals for field-effect transistor applications.

PubMed

Atahan-Evrenk, Sule; Aspuru-Guzik, Alán

2014-01-01

The theoretical prediction and characterization of the solid-state structure of organic semiconductors has tremendous potential for the discovery of new high performance materials. To date, the theoretical analysis mostly relied on the availability of crystal structures obtained through X-ray diffraction. However, the theoretical prediction of the crystal structures of organic semiconductor molecules remains a challenge. This review highlights some of the recent advances in the determination of structure-property relationships of the known organic semiconductor single-crystals and summarizes a few available studies on the prediction of the crystal structures of p-type organic semiconductors for transistor applications.

Dithiopheneindenofluorene (TIF) Semiconducting Polymers with Very High Mobility in Field-Effect Transistors.

PubMed

Chen, Hu; Hurhangee, Michael; Nikolka, Mark; Zhang, Weimin; Kirkus, Mindaugas; Neophytou, Marios; Cryer, Samuel J; Harkin, David; Hayoz, Pascal; Abdi-Jalebi, Mojtaba; McNeill, Christopher R; Sirringhaus, Henning; McCulloch, Iain

2017-09-01

The charge-carrier mobility of organic semiconducting polymers is known to be enhanced when the energetic disorder of the polymer is minimized. Fused, planar aromatic ring structures contribute to reducing the polymer conformational disorder, as demonstrated by polymers containing the indacenodithiophene (IDT) repeat unit, which have both a low Urbach energy and a high mobility in thin-film-transistor (TFT) devices. Expanding on this design motif, copolymers containing the dithiopheneindenofluorene repeat unit are synthesized, which extends the fused aromatic structure with two additional phenyl rings, further rigidifying the polymer backbone. A range of copolymers are prepared and their electrical properties and thin-film morphology evaluated, with the co-benzothiadiazole polymer having a twofold increase in hole mobility when compared to the IDT analog, reaching values of almost 3 cm 2 V -1 s -1 in bottom-gate top-contact organic field-effect transistors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

International Conference on Conducting Materials (ICoCom2010) Held in Sousse, Tunisia on November 3-7, 2010

DTIC Science & Technology

2010-11-01

Microscopy measurements on operating Pentacene Thin Film Transistor Rossi (Brazil) Organic Vertical Field Effect Transistor using DPIF as organic...Conductors and Related Quantum Matter Oral Session OSC7 12:00-12:20 12:20-12:40 Zulkifli (Malaysia) In-situ imaging of Structural Inhomogeneity and Local Jc

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Fabrication of High-Performance Polymer Bulk-Heterojunction Solar Cells by the Interfacial Modifications III

DTIC Science & Technology

2011-04-30

University of Tennessee) 3. "An ambipolar to n-type transformation in pentacene -based organic field-effect transistors" Org. Electron. 12, 509 (2011...OFETs). An ambipolar to n-type transformation in pentacene -based organic field-effect transistors (OFETs) of Al source-drain electrodes had been...correlated with the interfacial interactions between Al electrodes and pentacene , as characterized by analyzing Near-edge X-ray absorption fine structure

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

PubMed Central

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

PubMed

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

Study of InGaAs-based modulation doped field effect transistor structures using variable-angle spectroscopic ellipsometry

NASA Technical Reports Server (NTRS)

Alterovitz, S. A.; Sieg, R. M.; Yao, H. D.; Snyder, P. G.; Woollam, J. A.; Pamulapati, J.; Bhattacharya, P. K.; Sekula-Moise, P. A.

1991-01-01

Variable-angle spectroscopic ellipsometry was used to estimate the thicknesses of all layers within the optical penetration depth of InGaAs-based modulation doped field effect transistor structures. Strained and unstrained InGaAs channels were made by molecular beam epitaxy (MBE) on InP substrates and by metal-organic chemical vapor deposition on GaAs substrates. In most cases, ellipsometrically determined thicknesses were within 10% of the growth-calibration results. The MBE-made InGaAs strained layers showed large strain effects, indicating a probable shift in the critical points of their dielectric function toward the InP lattice-matched concentration.

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.; Ponchak, George E.

2004-01-01

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony concentration was approximately 4 x 10(exp 19) per cubic centimeter. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per square centimeter, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V (sub DS)) range, with V (sub DS) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Scattering effects on the performance of carbon nanotube field effect transistor in a compact model

NASA Astrophysics Data System (ADS)

Hamieh, S. D.; Desgreys, P.; Naviner, J. F.

2010-01-01

Carbon nanotube field-effect transistors (CNTFET) are being extensively studied as possible successors to CMOS. Device simulators have been developed to estimate their performance in sub-10-nm and device structures have been fabricated. In this work, a new compact model of single-walled semiconducting CNTFET is proposed implementing the calculation of energy conduction sub-band minima and the treatment of scattering effects through energy shift in CNTFET. The developed model has been used to simulate I-V characteristics using VHDL-AMS simulator.

Aqueous gating of van der Waals materials on bilayer nanopaper.

PubMed

Bao, Wenzhong; Fang, Zhiqiang; Wan, Jiayu; Dai, Jiaqi; Zhu, Hongli; Han, Xiaogang; Yang, Xiaofeng; Preston, Colin; Hu, Liangbing

2014-10-28

In this work, we report transistors made of van der Waals materials on a mesoporous paper with a smooth nanoscale surface. The aqueous transistor has a novel planar structure with source, drain, and gate electrodes on the same surface of the paper, while the mesoporous paper is used as an electrolyte reservoir. These transistors are enabled by an all-cellulose paper with nanofibrillated cellulose (NFC) on the top surface that leads to an excellent surface smoothness, while the rest of the microsized cellulose fibers can absorb electrolyte effectively. Based on two-dimensional van der Waals materials, including MoS2 and graphene, we demonstrate high-performance transistors with a large on-off ratio and low subthreshold swing. Such planar transistors with absorbed electrolyte gating can be used as sensors integrated with other components to form paper microfluidic systems. This study is significant for future paper-based electronics and biosensors.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

Amplified Emission and Field-Effect Transistor Characteristics of One-Dimensionally Structured 2,5-Bis(4-biphenylyl)thiophene Crystals.

PubMed

Hashimoto, Kazumasa; Sasaki, Fumio; Hotta, Shu; Yanagi, Hisao

2016-04-01

One-dimensional (1D) structures of 2,5-bis(4-biphenylyl)thiophene (BP1T) crystals are fabricated for light amplification and field-effect transistor (FET) measurements. A strip-shaped 1D structure (10 µm width) made by photolitography of a vapor-deposited polycrystalline film shows amplified spontaneous emission and lasing oscillations under optical pumping. An FET fabricated with this 1D structure exhibits hole-conduction with a mobility of µh = 8.0 x 10(-3) cm2/Vs. Another 1 D-structured FET is fabricated with epitaxially grown needle-like crystals of BP1T. This needle-crystal FET exhibits higher mobility of µh = 0.34 cm2/Vs. This improved hole mobility is attributed to the single-crystal channel of epitaxial needles while the grain boudaries in the polycrystalline 1 D-structure decrease the carrier transport.

Organic-inorganic hybrid materials as semiconducting channels in thin-film field-effect transistors

PubMed

Kagan; Mitzi; Dimitrakopoulos

1999-10-29

Organic-inorganic hybrid materials promise both the superior carrier mobility of inorganic semiconductors and the processability of organic materials. A thin-film field-effect transistor having an organic-inorganic hybrid material as the semiconducting channel was demonstrated. Hybrids based on the perovskite structure crystallize from solution to form oriented molecular-scale composites of alternating organic and inorganic sheets. Spin-coated thin films of the semiconducting perovskite (C(6)H(5)C(2)H(4)NH(3))(2)SnI(4) form the conducting channel, with field-effect mobilities of 0.6 square centimeters per volt-second and current modulation greater than 10(4). Molecular engineering of the organic and inorganic components of the hybrids is expected to further improve device performance for low-cost thin-film transistors.

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

PubMed

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Unified planar process for fabricating heterojunction bipolar transistors and buried-heterostructure lasers utilizing impurity-induced disordering

NASA Astrophysics Data System (ADS)

Thornton, R. L.; Mosby, W. J.; Chung, H. F.

1988-12-01

We describe results on a novel geometry of heterojunction bipolar transistor that has been realized by impurity-induced disordering. This structure is fabricated by a method that is compatible with techniques for the fabrication of low threshold current buried-heterostructure lasers. We have demonstrated this compatibility by fabricating a hybrid laser/transistor structure that operates as a laser with a threshold current of 6 mA at room temperature, and as a transistor with a current gain of 5.

Transport Mechanisms in Organic Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fung, A. W. P.

1996-03-01

Recent success in fabricating field-effect transistors with polycrystalline α-sexithiophene (α-6T) has allowed us to study charge transport in this organic semiconductor. The appealing structural property that the oligomer chains are seated almost perpendicular to the substrate provides a model π-conjugated system which we find exhibits band transport at low temperatures. We observe a behavioral transition around 50K which is consistent with the metal-insulator transition in Holstein's small-polaron theory. The fact that we can observe intrinsic behavior means that the ambient-temperature mobility obtained in these transistors is optimal for α-6T. Agreement with the Holstein theory provides us with a prescription for rational design of materials for organic transistor applications. Work done in collaboration with L. Torsi, A. Dodabalapur, L. J. Rothberg and H. E. Katz.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Theoretical and experimental studies of the current–voltage and capacitance–voltage of HEMT structures and field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tarasova, E. A.; Obolenskaya, E. S., E-mail: obolensk@rf.unn.ru; Hananova, A. V.

The sensitivity of classical n{sup +}/n{sup –} GaAs and AlGaN/GaN structures with a 2D electron gas (HEMT) and field-effect transistors based on these structures to γ-neutron exposure is studied. The levels of their radiation hardness were determined. A method for experimental study of the structures on the basis of a differential analysis of their current–voltage characteristics is developed. This method makes it possible to determine the structure of the layers in which radiation-induced defects accumulate. A procedure taking into account changes in the plate area of the experimentally measured barrier-contact capacitance associated with the emergence of clusters of radiation-induced defectsmore » that form dielectric inclusions in the 2D-electron-gas layer is presented for the first time.« less

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Microwave-signal generation in a planar Gunn diode with radiation exposure taken into account

DOE Office of Scientific and Technical Information (OSTI.GOV)

Obolenskaya, E. S., E-mail: bess009@mail.ru, E-mail: obolensk@rf.unn.ru; Tarasova, E. A.; Churin, A. Yu.

2016-12-15

Microwave-signal generation in planar Gunn diodes with a two-dimensional electron gas, in which we previously studied steady-state electron transport, is theoretically studied. The applicability of a control electrode similar to a field-effect transistor gate to control the parameters of the output diode microwave signal is considered. The results of physical-topological modeling of semiconductor structures with different diode active-region structures, i.e., without a quantum well, with one and two quantum wells separated by a potential barrier, are compared. The calculated results are compared with our previous experimental data on recording Gunn generation in a Schottky-gate field-effect transistor. It is theoretically andmore » experimentally shown that the power of the signal generated by the planar Gunn diode with a quantum well and a control electrode is sufficient to implement monolithic integrated circuits of different functionalities. It is theoretically and experimentally shown that the use of a control electrode on account of the introduction of corrective feedback allows a significant increase in the radiation resistance of a microwave generator with Schottky-gate field-effect transistors.« less

Solution-Processable Balanced Ambipolar Field-Effect Transistors Based on Carbonyl-Regulated Copolymers.

PubMed

Yang, Chengdong; Fang, Renren; Yang, Xiongfa; Chen, Ru; Gao, Jianhua; Fan, Hanghong; Li, Hongxiang; Hu, Wenping

2018-04-04

It is very important to develop ambipolar field effect transistors to construct complementary circuits. To obtain balanced hole- and electron-transport properties, one of the key issues is to regulate the energy levels of the frontier orbitals of the semiconductor materials by structural tailoring, so that they match well with the electrode Fermi levels. Five conjugated copolymers were synthesized and exhibited low LUMO energy levels and narrow bandgaps on account of the strong electron-withdrawing effect of the carbonyl groups. Polymer thin film transistors were prepared by using a solution method and exhibited high and balanced hole and electron mobility of up to 0.46 cm 2  V -1  s -1 , which suggested that these copolymers are promising ambipolar semiconductor materials. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors

NASA Astrophysics Data System (ADS)

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-01

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green’s function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors.

PubMed

Hur, Ji-Hyun; Kim, Deok-Kee

2018-05-04

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green's function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

NASA Astrophysics Data System (ADS)

Cui, Ning; Liang, Renrong; Wang, Jing; Xu, Jun

2012-06-01

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Geometric dependence of the parasitic components and thermal properties of HEMTs

NASA Astrophysics Data System (ADS)

Vun, Peter V.; Parker, Anthony E.; Mahon, Simon J.; Fattorini, Anthony

2007-12-01

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

80 MeV C{sup 6+} ion irradiation effects on the DC electrical characteristics of silicon NPN power transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bharathi, M. N.; Vinayakprasanna, N. H.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in

The total dose effects of 80 MeV C{sup 6+} ions on the DC electrical characteristics of Silicon NPN rf power transistors have been studied in the dose range of 100 krad to 100 Mrad. The SRIM simulation was used to understand the energy loss and range of the ions in the transistor structure. The different electrical parameters such as Gummel characteristics, excess base current (ΔI{sub B} = I{sub Bpost} - I{sub Bpre}), dc forward current gain (h{sub FE}), transconductance (g{sub m}), displacement damage factor (K) and output characteristics (V{sub CE}-I{sub C}) were studied systematically before and after irradiation. The significantmore » degradation in base current (I{sub B}) and h{sub FE} was observed after irradiation. Isochronal annealing study was conducted on the irradiated transistors to analyze the recovery in different electrical parameters. These results were compared with {sup 60}C0 gamma irradiation results in the same dose range.« less

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Total Dose Effects in Conventional Bipolar Transistors

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swift, G. W.; Rax, B. G.

1994-01-01

This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.

Solution-processed field-effect transistors based on dihexylquaterthiophene films with performances exceeding those of vacuum-sublimed films.

PubMed

Leydecker, Tim; Trong Duong, Duc; Salleo, Alberto; Orgiu, Emanuele; Samorì, Paolo

2014-12-10

Solution-processable oligothiophenes are model systems for charge transport and fabrication of organic field-effect transistors (OFET) . Herein we report a structure vs function relationship study focused on the electrical characteristics of solution-processed dihexylquaterthiophene (DH4T)-based OFET. We show that by combining the tailoring of all interfaces in the bottom-contact bottom-gate transistor, via chemisorption of ad hoc molecules on electrodes and dielectric, with suitable choice of the film preparation conditions (including solvent type, concentration, volume, and deposition method), it is possible to fabricate devices exhibiting field-effect mobilities exceeding those of vacuum-processed DH4T transistors. In particular, the evaporation rate of the solvent, the processing temperature, as well as the concentration of the semiconducting material were found to hold a paramount importance in driving the self-assembly toward the formation of highly ordered and low-dimensional supramolecular architectures, confirming the kinetically governed nature of the self-assembly process. Among the various architectures, hundreds-of-micrometers long and thin DH4T crystallites exhibited enhanced charge transport.

Strategies for Improving the Performance of Sensors Based on Organic Field-Effect Transistors.

PubMed

Wu, Xiaohan; Mao, Shun; Chen, Junhong; Huang, Jia

2018-04-01

Organic semiconductors (OSCs) have been extensively studied as sensing channel materials in field-effect transistors due to their unique charge transport properties. Stimulation caused by its environmental conditions can readily change the charge-carrier density and mobility of OSCs. Organic field-effect transistors (OFETs) can act as both signal transducers and signal amplifiers, which greatly simplifies the device structure. Over the past decades, various sensors based on OFETs have been developed, including physical sensors, chemical sensors, biosensors, and integrated sensor arrays with advanced functionalities. However, the performance of OFET-based sensors still needs to be improved to meet the requirements from various practical applications, such as high sensitivity, high selectivity, and rapid response speed. Tailoring molecular structures and micro/nanofilm structures of OSCs is a vital strategy for achieving better sensing performance. Modification of the dielectric layer and the semiconductor/dielectric interface is another approach for improving the sensor performance. Moreover, advanced sensory functionalities have been achieved by developing integrated device arrays. Here, a brief review of strategies used for improving the performance of OFET sensors is presented, which is expected to inspire and provide guidance for the design of future OFET sensors for various specific and practical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

Chemical Vapor-Deposited Hexagonal Boron Nitride as a Scalable Template for High-Performance Organic Field-Effect Transistors

DOE PAGES

Lee, Tae Hoon; Kim, Kwanpyo; Kim, Gwangwoo; ...

2017-02-27

Organic field-effect transistors have attracted much attention because of their potential use in low-cost, large-area, flexible electronics. High-performance organic transistors require a low density of grain boundaries in their organic films and a decrease in the charge trap density at the semiconductor–dielectric interface for efficient charge transport. In this respect, the role of the dielectric material is crucial because it primarily determines the growth of the film and the interfacial trap density. Here, we demonstrate the use of chemical vapor-deposited hexagonal boron nitride (CVD h-BN) as a scalable growth template/dielectric for high-performance organic field-effect transistors. The field-effect transistors based onmore » C60 films grown on single-layer CVD h-BN exhibit an average mobility of 1.7 cm 2 V –1 s –1 and a maximal mobility of 2.9 cm 2 V –1 s –1 with on/off ratios of 10 7. The structural and morphology analysis shows that the epitaxial, two-dimensional growth of C 60 on CVD h-BN is mainly responsible for the superior charge transport behavior. In conclusion, we believe that CVD h-BN can serve as a growth template for various organic semiconductors, allowing the development of large-area, high-performance flexible electronics.« less

Chemical Vapor-Deposited Hexagonal Boron Nitride as a Scalable Template for High-Performance Organic Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Tae Hoon; Kim, Kwanpyo; Kim, Gwangwoo

Organic field-effect transistors have attracted much attention because of their potential use in low-cost, large-area, flexible electronics. High-performance organic transistors require a low density of grain boundaries in their organic films and a decrease in the charge trap density at the semiconductor–dielectric interface for efficient charge transport. In this respect, the role of the dielectric material is crucial because it primarily determines the growth of the film and the interfacial trap density. Here, we demonstrate the use of chemical vapor-deposited hexagonal boron nitride (CVD h-BN) as a scalable growth template/dielectric for high-performance organic field-effect transistors. The field-effect transistors based onmore » C60 films grown on single-layer CVD h-BN exhibit an average mobility of 1.7 cm 2 V –1 s –1 and a maximal mobility of 2.9 cm 2 V –1 s –1 with on/off ratios of 10 7. The structural and morphology analysis shows that the epitaxial, two-dimensional growth of C 60 on CVD h-BN is mainly responsible for the superior charge transport behavior. In conclusion, we believe that CVD h-BN can serve as a growth template for various organic semiconductors, allowing the development of large-area, high-performance flexible electronics.« less

Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors.

PubMed

Lee, Ching-Ting; Chen, Chia-Chi; Lee, Hsin-Ying

2018-03-05

The three dimensional inverters were fabricated using novel complementary structure of stacked bottom n-type aluminum-doped zinc oxide (Al:ZnO) thin-film transistor and top p-type nickel oxide (NiO) thin-film transistor. When the inverter operated at the direct voltage (V DD ) of 10 V and the input voltage from 0 V to 10 V, the obtained high performances included the output swing of 9.9 V, the high noise margin of 2.7 V, and the low noise margin of 2.2 V. Furthermore, the high performances of unskenwed inverter were demonstrated by using the novel complementary structure of the stacked n-type Al:ZnO thin-film transistor and p-type nickel oxide (NiO) thin-film transistor.

Temperature dependence of ballistic mobility in a metamorphic InGaAs/InAlAs high electron mobility transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Jongkyong; Gang, Suhyun; Jo, Yongcheol

We have investigated the temperature dependence of ballistic mobility in a 100 nm-long InGaAs/InAlAs metamorphic high-electron-mobility transistor designed for millimeter-wavelength RF applications. To extract the temperature dependence of quasi-ballistic mobility, our experiment involves measurements of the effective mobility in the low-bias linear region of the transistor and of the collision-dominated Hall mobility using a gated Hall bar of the same epitaxial structure. The data measured from the experiment are consistent with that of modeled ballistic mobility based on ballistic transport theory. These results advance the understanding of ballistic transport in various transistors with a nano-scale channel length that is comparable tomore » the carrier's mean free path in the channel.« less

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Percolative effects on noise in pentacene transistors

NASA Astrophysics Data System (ADS)

Conrad, B. R.; Cullen, W. G.; Yan, W.; Williams, E. D.

2007-12-01

Noise in pentacene thin film transistors has been measured as a function of device thickness from well above the effective conduction channel thickness to only two conducting layers. Over the entire thickness range, the spectral noise form is 1/f, and the noise parameter varies inversely with gate voltage, confirming that the noise is due to mobility fluctuations, even in the thinnest films. Hooge's parameter varies as an inverse power law with conductivity for all film thicknesses. The magnitude and transport characteristics of the spectral noise are well explained in terms of percolative effects arising from the grain boundary structure.

Producing smart sensing films by means of organic field effect transistors.

PubMed

Manunza, Ileana; Orgiu, Emanuele; Caboni, Alessandra; Barbaro, Massimo; Bonfiglio, Annalisa

2006-01-01

We have fabricated the first example of totally flexible field effect device for chemical detection based on an organic field effect transistor (OFET) made by pentacene films grown on flexible plastic structures. The ion sensitivity is achieved by employing a thin Mylar foil as gate dielectric. A sensitivity of the device to the pH of the electrolyte solution has been observed A similar structure can be used also for detecting mechanical deformations on flexible surfaces. Thanks to the flexibility of the substrate and the low cost of the employed technology, these devices open the way for the production of flexible chemical and strain gauge sensors that can be employed in a variety of innovative applications such as wearable electronics, e-textiles, new man-machine interfaces.

Physical Modeling and Reliability Mechanisms in High Voltage AIGaN/GaN HFETs

DTIC Science & Technology

2013-02-01

heterojunction field effect transistor speed and stability has been established. The observed dependence of the LO phonon lifetime on the bulk carrier...aggregate, the cumulative data clearly point to the benefits of operation at or near resonance of LO phonon frequency and Plasmon frequency. Heterojunction ...of the structure such as quantum wells as in the case of light emitting diodes and lasers, heterojunction bipolar transistors. The FET case is

Transistor Effect in Improperly Connected Transistors.

ERIC Educational Resources Information Center

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Ballistic Spin Field Effect Transistor Based on Silicon Nanowires

NASA Astrophysics Data System (ADS)

Osintsev, Dmitri; Sverdlov, Viktor; Stanojevic, Zlatan; Selberherr, Siegfried

2011-03-01

We investigate the properties of ballistic spin field-effect transistors build on silicon nanowires. An accurate description of the conduction band based on the k . p} model is necessary in thin and narrow silicon nanostructures. The subband effective mass and subband splitting dependence on the nanowire dimensions is analyzed and used in the transport calculations. The spin transistor is formed by sandwiching the nanowire between two ferromagnetic metallic contacts. Delta-function barriers at the interfaces between the contacts and the silicon channel are introduced. The major contribution to the electric field-dependent spin-orbit interaction in confined silicon systems is due to the interface-induced inversion asymmetry which is of the Dresselhaus type. We study the current and conductance through the system for the contacts being in parallel and anti-parallel configurations. Differences between the [100] and [110] orientated structures are investigated in details. This work is supported by the European Research Council through the grant #247056 MOSILSPIN.

Vacuum-processed polyethylene as a dielectric for low operating voltage organic field effect transistors

PubMed Central

Kanbur, Yasin; Irimia-Vladu, Mihai; Głowacki, Eric D.; Voss, Gundula; Baumgartner, Melanie; Schwabegger, Günther; Leonat, Lucia; Ullah, Mujeeb; Sarica, Hizir; Erten-Ela, Sule; Schwödiauer, Reinhard; Sitter, Helmut; Küçükyavuz, Zuhal; Bauer, Siegfried; Sariciftci, Niyazi Serdar

2012-01-01

We report on the fabrication and performance of vacuum-processed organic field effect transistors utilizing evaporated low-density polyethylene (LD-PE) as a dielectric layer. With C60 as the organic semiconductor, we demonstrate low operating voltage transistors with field effect mobilities in excess of 4 cm2/Vs. Devices with pentacene showed a mobility of 0.16 cm2/Vs. Devices using tyrian Purple as semiconductor show low-voltage ambipolar operation with equal electron and hole mobilities of ∼0.3 cm2/Vs. These devices demonstrate low hysteresis and operational stability over at least several months. Grazing-angle infrared spectroscopy of evaporated thin films shows that the structure of the polyethylene is similar to solution-cast films. We report also on the morphological and dielectric properties of these films. Our experiments demonstrate that polyethylene is a stable dielectric supporting both hole and electron channels. PMID:23483783

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Fluorination of Metal Phthalocyanines: Single-Crystal Growth, Efficient N-Channel Organic Field-Effect Transistors, and Structure-Property Relationships

PubMed Central

Jiang, Hui; Ye, Jun; Hu, Peng; Wei, Fengxia; Du, Kezhao; Wang, Ning; Ba, Te; Feng, Shuanglong; Kloc, Christian

2014-01-01

The fluorination of p-type metal phthalocyanines produces n-type semiconductors, allowing the design of organic electronic circuits that contain inexpensive heterojunctions made from chemically and thermally stable p- and n-type organic semiconductors. For the evaluation of close to intrinsic transport properties, high-quality centimeter-sized single crystals of F16CuPc, F16CoPc and F16ZnPc have been grown. New crystal structures of F16CuPc, F16CoPc and F16ZnPc have been determined. Organic single-crystal field-effect transistors have been fabricated to study the effects of the central metal atom on their charge transport properties. The F16ZnPc has the highest electron mobility (~1.1 cm2 V−1 s−1). Theoretical calculations indicate that the crystal structure and electronic structure of the central metal atom determine the transport properties of fluorinated metal phthalocyanines. PMID:25524460

Effect of Al2O3 insulator thickness on the structural integrity of amorphous indium-gallium-zinc-oxide based thin film transistors.

PubMed

Kim, Hak-Jun; Hwang, In-Ju; Kim, Youn-Jea

2014-12-01

The current transparent oxide semiconductors (TOSs) technology provides flexibility and high performance. In this study, multi-stack nano-layers of TOSs were designed for three-dimensional analysis of amorphous indium-gallium-zinc-oxide (a-IGZO) based thin film transistors (TFTs). In particular, the effects of torsional and compressive stresses on the nano-sized active layers such as the a-IGZO layer were investigated. Numerical simulations were carried out to investigate the structural integrity of a-IGZO based TFTs with three different thicknesses of the aluminum oxide (Al2O3) insulator (δ = 10, 20, and 30 nm), respectively, using a commercial code, COMSOL Multiphysics. The results are graphically depicted for operating conditions.

High Mobility SiGe/Si n-Type Structures and Field Effect Transistors on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Ponchak, George E.; Mueller, Carl H.; Croke, Edward T.

2004-01-01

SiGe/Si n-type modulation doped field effect transistors (MODFETs) fabricated on sapphire substrates have been characterized at microwave frequencies for the first time. The highest measured room temperature electron mobility is 1380 sq cm/V-sec at a carrier density of 1.8 x 10(exp 12)/sq cm for a MODFET structure, and 900 sq cm/V-sec at a carrier density of 1.3 x 10/sq cm for a phosphorus ion implanted sample. A two finger, 2 x 200 micron gate n-MODFET has a peak transconductance of 37 mS/mm at a drain to source voltage of 2.5 V and a transducer gain of 6.4 dB at 1 GHz.

Effective mobility enhancement of amorphous In-Ga-Zn-O thin-film transistors by holographically generated periodic conductor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jeong, Jaewook; Kim, Joonwoo; Jeong, Soon Moon

In this study, we demonstrate a mobility enhancement structure for fully transparent amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) by embedding a holographically generated periodic nano-conductor in the back-channel regions. The intrinsic field-effect mobility was enhanced up to 2 times compared to that of a reference sample. The enhancement originated from a decrease in the effective channel length due to the highly conductive nano-conductor region. By combining conventional and holographic lithography, the performance of the a-IGZO TFT can be effectively improved without varying the composition of the channel layer.

Effective mobility enhancement of amorphous In-Ga-Zn-O thin-film transistors by holographically generated periodic conductor

NASA Astrophysics Data System (ADS)

Jeong, Jaewook; Kim, Joonwoo; Kim, Donghyun; Jeon, Heonsu; Jeong, Soon Moon; Hong, Yongtaek

2016-08-01

In this study, we demonstrate a mobility enhancement structure for fully transparent amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) by embedding a holographically generated periodic nano-conductor in the back-channel regions. The intrinsic field-effect mobility was enhanced up to 2 times compared to that of a reference sample. The enhancement originated from a decrease in the effective channel length due to the highly conductive nano-conductor region. By combining conventional and holographic lithography, the performance of the a-IGZO TFT can be effectively improved without varying the composition of the channel layer.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Ultrasound-Induced Organogel Formation Followed by Thin Film Fabrication via Simple Doctor Blading Technique for Field-Effect Transistor Applications.

PubMed

Xu, Jiaju; Wang, Yulong; Shan, Haiquan; Lin, Yiwei; Chen, Qian; Roy, V A L; Xu, Zongxiang

2016-07-27

We demonstrate doctor blading technique to fabricate high performance transistors made up of printed small molecular materials. In this regard, we synthesize a new soluble phthalocyanine, tetra-n-butyl peripheral substituted copper(II) phthalocaynine (CuBuPc), that can easily undergo gel formation upon ultrasonic irradiation, leading to the formation of three-dimensional (3D) network composed of one-dimensional (1D) nanofibers structure. Finally, taking the advantage of thixotropic nature of the CuBuPc organogel, we use the doctor blade processing technique that limits the material wastage for the fabrication of transistor devices. Due to the ultrasound induced stronger π-π interaction, the transistor fabricated by doctor blading based on CuBuPc organogel exhibits significant increase in charge carrier mobility in comparison with other solution process techniques, thus paving a way for a simple and economically viable preparation of electronic circuits.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

High current gain transistor laser

PubMed Central

Liang, Song; Qiao, Lijun; Zhu, Hongliang; Wang, Wei

2016-01-01

A transistor laser (TL), having the structure of a transistor with multi-quantum wells near its base region, bridges the functionality gap between lasers and transistors. However, light emission is produced at the expense of current gain for all the TLs reported up to now, leading to a very low current gain. We propose a novel design of TLs, which have an n-doped InP layer inserted in the emitter ridge. Numerical studies show that a current flow aperture for only holes can be formed in the center of the emitter ridge. As a result, the common emitter current gain can be as large as 143.3, which is over 15 times larger than that of a TL without the aperture. Besides, the effects of nonradiative recombination defects can be reduced greatly because the flow of holes is confined in the center region of the emitter ridge. PMID:27282466

Electroluminescence from single-wall carbon nanotube network transistors.

PubMed

Adam, E; Aguirre, C M; Marty, L; St-Antoine, B C; Meunier, F; Desjardins, P; Ménard, D; Martel, R

2008-08-01

The electroluminescence (EL) properties from single-wall carbon nanotube network field-effect transistors (NNFETs) and small bundle carbon nanotube field effect transistors (CNFETs) are studied using spectroscopy and imaging in the near-infrared (NIR). At room temperature, NNFETs produce broad (approximately 180 meV) and structured NIR spectra, while they are narrower (approximately 80 meV) for CNFETs. EL emission from NNFETs is located in the vicinity of the minority carrier injecting contact (drain) and the spectrum of the emission is red shifted with respect to the corresponding absorption spectrum. A phenomenological model based on a Fermi-Dirac distribution of carriers in the nanotube network reproduces the spectral features observed. This work supports bipolar (electron-hole) current recombination as the main mechanism of emission and highlights the drastic influence of carrier distribution on the optoelectronic properties of carbon nanotube films.

Si{sub 3}N{sub 4} layers for the in-situ passivation of GaN-based HEMT structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yunin, P. A., E-mail: yunin@ipmras.ru; Drozdov, Yu. N.; Drozdov, M. N.

2015-11-15

A method for the in situ passivation of GaN-based structures with silicon nitride in the growth chamber of a metal organic vapor phase epitaxy (MOVPE) reactor is described. The structural and electrical properties of the obtained layers are investigated. The in situ and ex situ passivation of transistor structures with silicon nitride in an electron-beam-evaporation device are compared. It is shown that ex situ passivation changes neither the initial carrier concentration nor the mobility. In situ passivation makes it possible to protect the structure surface against uncontrollable degradation upon the finishing of growth and extraction to atmosphere. In the inmore » situ passivated structure, the carrier concentration increases and the mobility decreases. This effect should be taken into account when manufacturing passivated GaN-based transistor structures.« less

Surface Modulation of Graphene Field Effect Transistors on Periodic Trench Structure.

PubMed

Jin, Jun Eon; Choi, Jun Hee; Yun, Hoyeol; Jang, Ho-Kyun; Lee, Byung Chul; Choi, Ajeong; Joo, Min-Kyu; Dettlaff-Weglikowska, Urszula; Roth, Siegmar; Lee, Sang Wook; Lee, Jae Woo; Kim, Gyu Tae

2016-07-20

In this work, graphene field effect transistors (FETs) were fabricated on a trench structure made by carbonized poly(methylmethacrylate) to modify the graphene surface. The trench-structured devices showed different characteristics depending on the channel orientation and the pitch size of the trenches as well as channel area in the FETs. Periodic corrugations and barriers of suspended graphene on the trench structure were measured by atomic force microscopy and electrostatic force microscopy. Regular barriers of 160 mV were observed for the trench structure with graphene. To confirm the transfer mechanism in the FETs depending on the channel orientation, the ratio of experimental mobility (3.6-3.74) was extracted from the current-voltage characteristics using equivalent circuit simulation. It is shown that the number of barriers increases as the pitch size decreases because the number of corrugations increases from different trench pitches. The noise for the 140 nm pitch trench is 1 order of magnitude higher than that for the 200 nm pitch trench.

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

25th Anniversary Article: Organic Field-Effect Transistors: The Path Beyond Amorphous Silicon

PubMed Central

Sirringhaus, Henning

2014-01-01

Over the past 25 years, organic field-effect transistors (OFETs) have witnessed impressive improvements in materials performance by 3–4 orders of magnitude, and many of the key materials discoveries have been published in Advanced Materials. This includes some of the most recent demonstrations of organic field-effect transistors with performance that clearly exceeds that of benchmark amorphous silicon-based devices. In this article, state-of-the-art in OFETs are reviewed in light of requirements for demanding future applications, in particular active-matrix addressing for flexible organic light-emitting diode (OLED) displays. An overview is provided over both small molecule and conjugated polymer materials for which field-effect mobilities exceeding > 1 cm2 V–1 s–1 have been reported. Current understanding is also reviewed of their charge transport physics that allows reaching such unexpectedly high mobilities in these weakly van der Waals bonded and structurally comparatively disordered materials with a view towards understanding the potential for further improvement in performance in the future. PMID:24443057

Negative Differential Resistance and Steep Switching in Chevron Graphene Nanoribbon Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Smith, Samuel; Llinas, Juan-Pablo; Bokor, Jeffrey; Salahuddin, Sayeef

2018-01-01

Ballistic quantum transport calculations based on the non-equilbrium Green's function formalism show that field-effect transistor devices made from chevron-type graphene nanoribbons (CGNRs) could exhibit negative differential resistance with peak-to-valley ratios in excess of 4800 at room temperature as well as steep-slope switching with 6 mV/decade subtheshold swing over five orders of magnitude and ON-currents of 88$\\mu$A/$\\mu$m. This is enabled by the superlattice-like structure of these ribbons that have large periodic unit cells with regions of different effective bandgap, resulting in minibands and gaps in the density of states above the conduction band edge. The CGNR ribbon used in our proposed device has been previously fabricated with bottom-up chemical synthesis techniques and could be incorporated into an experimentally-realizable structure.

Experimental synchronization of chaos in a large ring of mutually coupled single-transistor oscillators: phase, amplitude, and clustering effects.

PubMed

Minati, Ludovico

2014-12-01

In this paper, experimental evidence of multiple synchronization phenomena in a large (n = 30) ring of chaotic oscillators is presented. Each node consists of an elementary circuit, generating spikes of irregular amplitude and comprising one bipolar junction transistor, one capacitor, two inductors, and one biasing resistor. The nodes are mutually coupled to their neighbours via additional variable resistors. As coupling resistance is decreased, phase synchronization followed by complete synchronization is observed, and onset of synchronization is associated with partial synchronization, i.e., emergence of communities (clusters). While component tolerances affect community structure, the general synchronization properties are maintained across three prototypes and in numerical simulations. The clusters are destroyed by adding long distance connections with distant notes, but are otherwise relatively stable with respect to structural connectivity changes. The study provides evidence that several fundamental synchronization phenomena can be reliably observed in a network of elementary single-transistor oscillators, demonstrating their generative potential and opening way to potential applications of this undemanding setup in experimental modelling of the relationship between network structure, synchronization, and dynamical properties.

Organic-inorganic field effect transistor with SnI-based perovskite channel layer using vapor phase deposition technique

NASA Astrophysics Data System (ADS)

Matsushima, Toshinori; Yasuda, Takeshi; Fujita, Katsuhiko; Tsutsui, Tetsuo

2003-11-01

High field-effect hole mobility of (formula available in paper)and threshold voltage is -3.2 V) in organic-inorganic layered perovskite film (formula available in paper)prepared by a vapor phase deposition technique have been demonstrated through the octadecyltrichlorosilane treatment of substrate. Previously, the (formula available in paper)films prepared on the octadecyltrichlorosilane-covered substrates using a vapor evaporation showed not only intense exciton absorption and photoluminescence in the optical spectroscopy but also excellent crystallinity and large grain structure in X-ray and atomic force microscopic studies. Especially, the (formula available in paper)structure in the region below few nm closed to the surface of octadecyltrichlorosilane monolayer was drastically improved in comparison with that on the non-covered substrate. Though our initial (formula available in paper)films via a same sequence of preparation of (formula available in paper)and octadecyltrichlorosilane monolayer did not show the field-effect properties because of a lack of spectral, structural, and morphological features. The unformation of favorable (formula available in paper)structure in the very thin region, that is very important for the field-effect transistors to transport electrons or holes, closed to the surface of non-covered (formula available in paper)dielectric layer was also one of the problems for no observation of them. By adding further optimization and development, such as deposition rate of perovskite, substrate heating during deposition, and tuning device architecture, with hydrophobic treatment, the vacuum-deposited (formula available in paper)have achieved above-described high performance in organic-inorganic hybrid transistors.

Effects of Electron Beam Irradiation and Thiol Molecule Treatment on the Properties of MoS2 Field Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Barbara Yuri; Cho, Kyungjune; Pak, Jinsu; Kim, Tae-Young; Kim, Jae-Keun; Shin, Jiwon; Seo, Junseok; Chung, Seungjun; Lee, Takhee

2018-05-01

We investigated the effects of the structural defects intentionally created by electron-beam irradiation with an energy of 30 keV on the electrical properties of monolayer MoS2 field effect transistors (FETs). We observed that the created defects by electron beam irradiation on the MoS2 surface working as trap sites deteriorated the carrier mobility and carrier concentration with increasing the subthreshold swing value and shifting the threshold voltage in MoS2 FETs. The electrical properties of electron-beam irradiated MoS2 FETs were slightly improved by treating the devices with thiol-terminated molecules which presumably passivated the structural defects of MoS2. The results of this study may enhance the understanding of the electrical properties of MoS2 FETs in terms of creating and passivating defect sites.

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.; Ponchak, George E.

2003-01-01

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony, concentration was approximately 4 x 10(exp19) per cubic cm. The electron mobility was over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per sq cm, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V(sub DS)) range, with (V(sub DS)) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Enhanced sheet carrier densities in polarization controlled AlInN/AlN/GaN/InGaN field-effect transistor on Si (111)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hennig, J., E-mail: jonas.hennig@ovgu.de; Dadgar, A.; Witte, H.

2015-07-15

We report on GaN based field-effect transistor (FET) structures exhibiting sheet carrier densities of n = 2.9 10{sup 13} cm{sup −2} for high-power transistor applications. By grading the indium-content of InGaN layers grown prior to a conventional GaN/AlN/AlInN FET structure control of the channel width at the GaN/AlN interface is obtained. The composition of the InGaN layer was graded from nominally x{sub In} = 30 % to pure GaN just below the AlN/AlInN interface. Simulations reveal the impact of the additional InGaN layer on the potential well width which controls the sheet carrier density within the channel region of the devices.more » Benchmarking the In{sub x}Ga{sub 1−x}N/GaN/AlN/Al{sub 0.87}In{sub 0.13}N based FETs against GaN/AlN/AlInN FET reference structures we found increased maximum current densities of I{sub SD} = 1300 mA/mm (560 mA/mm). In addition, the InGaN layer helps to achieve broader transconductance profiles as well as reduced leakage currents.« less

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Padilla, J. L., E-mail: jose.padilladelatorre@epfl.ch; Alper, C.; Ionescu, A. M.

2015-06-29

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of themore » inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher I{sub ON} levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures.« less

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

NASA Astrophysics Data System (ADS)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

Fabrication of field-effect transistor utilizing oriented thin film of octahexyl-substituted phthalocyanine and its electrical anisotropy based on columnar structure

NASA Astrophysics Data System (ADS)

Ohmori, Masashi; Nakatani, Mitsuhiro; Kajii, Hirotake; Miyamoto, Ayano; Yoneya, Makoto; Fujii, Akihiko; Ozaki, Masanori

2018-03-01

Field-effect transistors with molecularly oriented thin films of metal-free non-peripherally octahexyl-substituted phthalocyanine (C6PcH2), which characteristically form a columnar structure, have been fabricated, and the electrical anisotropy of C6PcH2 has been investigated. The molecularly oriented thin films of C6PcH2 were prepared by the bar-coating technique, and the uniform orientation in a large area and the surface roughness at a molecular level were observed by polarized spectroscopy and atomic force microscopy, respectively. The field effect mobilities parallel and perpendicular to the column axis of C6PcH2 were estimated to be (1.54 ± 0.24) × 10-2 and (2.10 ± 0.23) × 10-3 cm2 V-1 s-1, respectively. The electrical anisotropy based on the columnar structure has been discussed by taking the simulated results obtained by density functional theory calculation into consideration.

5 MeV Proton irradiation effects on 200 GHz silicon-germanium heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Hegde, Vinayakprasanna N.; Pradeep, T. M.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Cressler, J. D.

2017-12-01

The total dose effects of 5 MeV proton and Co-60 gamma irradiation in the dose range from 1 to 100 Mrad on advanced 200 GHz Silicon-Germanium heterojunction bipolar transistors (SiGe HBTs) are investigated. The SRIM simulation study was conducted to understand the energy loss of 5 MeV proton ions in SiGe HBT structure. Pre- and post-radiation DC figure of merits such as forward- and inverse-mode Gummel characteristics, excess base current, DC current gain and output characteristics were used to quantify the radiation tolerance of the devices. The results show that the proton creates a significant amount of damages in the surface and bulk of the transistor when compared with gamma irradiation. The SiGe HBTs shows robust ionizing radiation tolerance even up to a total dose of 100 Mrad for both radiations.

Recent Progress in Obtaining Semiconducting Single-Walled Carbon Nanotubes for Transistor Applications.

PubMed

Islam, Ahmad E; Rogers, John A; Alam, Muhammad A

2015-12-22

High purity semiconducting single-walled carbon nanotubes (s-SWCNTs) with a narrow diameter distribution are required for high-performance transistors. Achieving this goal is extremely challenging because the as-grown material contains mixtures of s-SWCNTs and metallic- (m-) SWCNTs with wide diameter distributions, typically inadequate for integrated circuits. Since 2000, numerous ex situ methods have been proposed to improve the purity of the s-SWCNTs. The majority of these techniques fail to maintain the quality and integrity of the s-SWCNTs with a few notable exceptions. Here, the progress in realizing high purity s-SWCNTs in as-grown and post-processed materials is highlighted. A comparison of transistor parameters (such as on/off ratio and field-effect mobility) obtained from test structures establishes the effectiveness of various methods and suggests opportunities for future improvements. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Removing the current-limit of vertical organic field effect transistors

NASA Astrophysics Data System (ADS)

Sheleg, Gil; Greenman, Michael; Lussem, Bjorn; Tessler, Nir

2017-11-01

The reported Vertical Organic Field Effect Transistors (VOFETs) show either superior current and switching speeds or well-behaved transistor performance, especially saturation in the output characteristics. Through the study of the relationship between the device architecture or dimensions and the device performance, we find that achieving a saturation regime in the output characteristics requires that the device operates in the injection limited regime. In current structures, the existence of the injection limited regime depends on the source's injection barrier as well as on the buried semiconductor layer thickness. To overcome the injection limit imposed by the necessity of injection barrier, we suggest a new architecture to realize VOFETs. This architecture shows better gate control and is independent of the injection barrier at the source, thus allowing for several A cm-2 for a semiconductor having a mobility value of 0.1 cm2 V-1 s-1.

p-Type Transparent Electronics

DTIC Science & Technology

2003-09-25

thin - film transistors (TTFTs) reported to date in the literature are summarized. 2.2.1 Thin - Film Transistor Structure and Fabrication A TFT ...is incapable of controlling the TFT regardless of gate voltage, as described in Sec. 2.2.3.1. 2.2.4 Transparent Thin - Film Transistors (TTFTs...Transparent thin - film transistors (TTFTs) described in the literature to date are all n-channel devices. Several n-channel TTFTs (n-TTFTs) based on

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeluri, Ramya, E-mail: ramyay@ece.ucsb.edu; Lu, Jing; Keller, Stacia

2015-05-04

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm{sup 2}) and low ON-resistance (0.4 mΩ cm{sup 2}) are demonstrated. Non-planar selective area regrowth is identified as the limiting factormore » to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities.« less

Terahertz light-emitting graphene-channel transistor toward single-mode lasing

NASA Astrophysics Data System (ADS)

Yadav, Deepika; Tamamushi, Gen; Watanabe, Takayuki; Mitsushio, Junki; Tobah, Youssef; Sugawara, Kenta; Dubinov, Alexander A.; Satou, Akira; Ryzhii, Maxim; Ryzhii, Victor; Otsuji, Taiichi

2018-03-01

A distributed feedback dual-gate graphene-channel field-effect transistor (DFB-DG-GFET) was fabricated as a current-injection terahertz (THz) light-emitting laser transistor. We observed a broadband emission in a 1-7.6-THz range with a maximum radiation power of 10 μW as well as a single-mode emission at 5.2 THz with a radiation power of 0.1 μW both at 100 K when the carrier injection stays between the lower cutoff and upper cutoff threshold levels. The device also exhibited peculiar nonlinear threshold-like behavior with respect to the current-injection level. The LED-like broadband emission is interpreted as an amplified spontaneous THz emission being transcended to a single-mode lasing. Design constraints on waveguide structures for better THz photon field confinement with higher gain overlapping as well as DFB cavity structures with higher Q factors are also addressed towards intense, single-mode continuous wave THz lasing at room temperature.

Gate-controlled quantum collimation in nanocolumn resonant tunneling transistors.

PubMed

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Indlekofer, K M; Lüth, H

2009-11-18

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n++/i/n++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Use of a bilayer lattice-matched AlInGaN barrier for improving the channel carrier confinement of enhancement-mode AlInGaN/GaN hetero-structure field-effect transistors

NASA Astrophysics Data System (ADS)

Rahbardar Mojaver, Hassan; Gosselin, Jean-Lou; Valizadeh, Pouya

2017-06-01

A quaternary lattice-matched layer structure based on employing a bilayer barrier for improving the carrier confinement in the channel of enhancement-mode metal-face c-plane wurtzite AlInGaN/GaN hetero-structure field effect transistors (HFETs) is for the first time proposed. Using the commercial self-consistent Poisson-Schrödinger solver Nextnano, electronic properties of the proposed hetero-structure, including the sheet charge density and carrier confinement on the GaN side of the hetero-interface, are evaluated. Based on these evaluations, it is shown that while the proposed layer structure substantially improves the carrier confinement in the GaN channel layer, it also upholds the merits of employing a lattice-matched barrier towards achieving an enhancement-mode operation (i.e., in the absence of the piezoelectric effect). According to these simulations, in terms of maintaining the required positive threshold-voltage for the enhancement-mode operation, it is also shown that the proposed layer structure substantially outperforms the quaternary AlInGaN/GaN HFETs employing a thin AlN spacer layer.

Trap density of states in small-molecule organic semiconductors: A quantitative comparison of thin-film transistors with single crystals

NASA Astrophysics Data System (ADS)

Kalb, Wolfgang L.; Haas, Simon; Krellner, Cornelius; Mathis, Thomas; Batlogg, Bertram

2010-04-01

We show that it is possible to reach one of the ultimate goals of organic electronics: producing organic field-effect transistors with trap densities as low as in the bulk of single crystals. We studied the spectral density of localized states in the band gap [trap density of states (trap DOS)] of small-molecule organic semiconductors as derived from electrical characteristics of organic field-effect transistors or from space-charge-limited current measurements. This was done by comparing data from a large number of samples including thin-film transistors (TFT’s), single crystal field-effect transistors (SC-FET’s) and bulk samples. The compilation of all data strongly suggests that structural defects associated with grain boundaries are the main cause of “fast” hole traps in TFT’s made with vacuum-evaporated pentacene. For high-performance transistors made with small-molecule semiconductors such as rubrene it is essential to reduce the dipolar disorder caused by water adsorbed on the gate dielectric surface. In samples with very low trap densities, we sometimes observe a steep increase in the trap DOS very close (<0.15eV) to the mobility edge with a characteristic slope of 10-20 meV. It is discussed to what degree band broadening due to the thermal fluctuation of the intermolecular transfer integral is reflected in this steep increase in the trap DOS. Moreover, we show that the trap DOS in TFT’s with small-molecule semiconductors is very similar to the trap DOS in hydrogenated amorphous silicon even though polycrystalline films of small-molecules with van der Waals-type interaction on the one hand are compared with covalently bound amorphous silicon on the other hand.

Synthesis, properties, crystal structures, and semiconductor characteristics of naphtho[1,2-b:5,6-b']dithiophene and -diselenophene derivatives.

PubMed

Shinamura, Shoji; Miyazaki, Eigo; Takimiya, Kazuo

2010-02-19

In this paper we present the synthesis, structures, characterization, and applications to field-effect transistors (FETs) of naphtho[1,2-b:5,6-b']dithiophene (NDT) and -diselenophene (NDS) derivatives. Treatment of 1,5-dichloro-2,6-diethynylnaphthalenes, easily derived from commercially available 2,6-dihydroxynaphthalene, with sodium chalcogenide afforded a straightforward access to NDTs and NDSs including the parent and dioctyl and diphenyl derivatives. Physicochemical evaluations of NDT and NDS derivatives showed that these heteroarenes have a similar electronic structure with isomeric [1]benzothieno[2,3-b][1]benzothiophene (BTBT) and [1]benzoselenopheneno[2,3-b][1]benzoselenophene (BSBS) derivatives, respectively. Although attempts to fabricate solution-processed field-effect transistors (FETs) with soluble dioctyl-NDT (C(8)-NDT) and -NDS (C(8)-NDS) failed, diphenyl derivatives (DPh-NDT and DPh-NDS) afforded vapor-processed FETs showing field-effect mobility as high as 0.7 cm(2) V(-1) s(-1). These results indicated that NDT and NDS are new potential heteroarene core structures for organic semiconducting materials.

Study of novel junctionless Ge n-Tunneling Field-Effect Transistors with lightly doped drain (LDD) region

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Bin; Wang, Meng; Han, Genquan; Cui, Shimin; Zhang, Heming

2017-02-01

In this paper, a novel junctionless Ge n-Tunneling Field-Effect Transistors (TFET) structure is proposed. The simulation results show that Ion = 5.5 × 10-5A/μm is achieved. The junctionless device structure enhances Ion effectively and increases the region where significant BTBT occurs, comparing with the normal Ge-nTEFT. The impact of the lightly doped drain (LDD) region is investigated. A comparison of Ion and Ioff of the junctionless Ge n-TFET with different channel doping concentration ND and LDD doping concentration NLDD is studied. Ioff is reduced 1 order of magnitude with the optimized ND and NLDD are 1 × 1018cm-3 and 1 × 1017 cm-3, respectively. To reduce the gate induced drain leakage (GIDL) current, the impact of the sloped gate oxide structure is also studied. By employing the sloped gate oxide structure, the below 60 mV/decade subthreshold swing S = 46.2 mV/decade is achieved at Ion = 4.05 × 10-5A/μm and Ion/Ioff = 5.7 × 106.

Integrated digital inverters based on two-dimensional anisotropic ReS₂ field-effect transistors

DOE PAGES

Liu, Erfu; Fu, Yajun; Wang, Yaojia; ...

2015-05-07

Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS₂) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS₂ field-effect transistors, which exhibit competitive performance with large current on/off ratios (~10⁷) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconductingmore » materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS₂ anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications.« less

Heterogeneous Integration of Epitaxial Ge on Si using AlAs/GaAs Buffer Architecture: Suitability for Low-power Fin Field-Effect Transistors

PubMed Central

Hudait, Mantu K.; Clavel, Michael; Goley, Patrick; Jain, Nikhil; Zhu, Yan

2014-01-01

Germanium-based materials and device architectures have recently appeared as exciting material systems for future low-power nanoscale transistors and photonic devices. Heterogeneous integration of germanium (Ge)-based materials on silicon (Si) using large bandgap buffer architectures could enable the monolithic integration of electronics and photonics. In this paper, we report on the heterogeneous integration of device-quality epitaxial Ge on Si using composite AlAs/GaAs large bandgap buffer, grown by molecular beam epitaxy that is suitable for fabricating low-power fin field-effect transistors required for continuing transistor miniaturization. The superior structural quality of the integrated Ge on Si using AlAs/GaAs was demonstrated using high-resolution x-ray diffraction analysis. High-resolution transmission electron microscopy confirmed relaxed Ge with high crystalline quality and a sharp Ge/AlAs heterointerface. X-ray photoelectron spectroscopy demonstrated a large valence band offset at the Ge/AlAs interface, as compared to Ge/GaAs heterostructure, which is a prerequisite for superior carrier confinement. The temperature-dependent electrical transport properties of the n-type Ge layer demonstrated a Hall mobility of 370 cm2/Vs at 290 K and 457 cm2/Vs at 90 K, which suggests epitaxial Ge grown on Si using an AlAs/GaAs buffer architecture would be a promising candidate for next-generation high-performance and energy-efficient fin field-effect transistor applications. PMID:25376723

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Low-temperature phase transitions in a soluble oligoacene and their effect on device performance and stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, J. W.; Goetz, K. P.; Obaid, A.

The use of organic semiconductors in high-performance organic field-effect transistors requires a thorough understanding of the effects that processing conditions, thermal, and bias-stress history have on device operation. Here, we evaluate the temperature dependence of the electrical properties of transistors fabricated with 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene, a material that has attracted much attention recently due to its exceptional electrical properties. We have discovered a phase transition at T = 205 K and discuss its implications on device performance and stability. We examined the impact of this low-temperature phase transition on the thermodynamic, electrical, and structural properties of both single crystals and thin films of this material.more » Our results show that while the changes to the crystal structure are reversible, the induced thermal stress yields irreversible degradation of the devices.« less

Impact of repeated uniaxial mechanical strain on flexible a-IGZO thin film transistors with symmetric and asymmetric structures

NASA Astrophysics Data System (ADS)

Liao, Po-Yung; Chang, Ting-Chang; Su, Wan-Ching; Chen, Bo-Wei; Chen, Li-Hui; Hsieh, Tien-Yu; Yang, Chung-Yi; Chang, Kuan-Chang; Zhang, Sheng-Dong; Huang, Yen-Yu; Chang, Hsi-Ming; Chiang, Shin-Chuan

2017-06-01

This letter investigates repeated uniaxial mechanical stress-induced degradation behavior in flexible amorphous In-Ga-Zn-O thin-film transistors (TFTs) of different geometric structures. Two types of via-contact structure TFTs are investigated: symmetrical and UI structure (TFTs with I- and U-shaped asymmetric electrodes). After repeated mechanical stress, I-V curves for the symmetrical structure show a significant negative threshold voltage (VT) shift, due to mechanical stress-induced oxygen vacancy generation. However, degradation in the UI structure TFTs after stress is a negative VT shift along with the parasitic transistor characteristic in the forward-operation mode, with this hump not evident in the reverse-operation mode. This asymmetrical degradation is clarified by the mechanical strain simulation of the UI TFTs.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

α,ω-dihexyl-sexithiophene thin films for solution-gated organic field-effect transistors

NASA Astrophysics Data System (ADS)

Schamoni, Hannah; Noever, Simon; Nickel, Bert; Stutzmann, Martin; Garrido, Jose A.

2016-02-01

While organic semiconductors are being widely investigated for chemical and biochemical sensing applications, major drawbacks such as the poor device stability and low charge carrier mobility in aqueous electrolytes have not yet been solved to complete satisfaction. In this work, solution-gated organic field-effect transistors (SGOFETs) based on the molecule α,ω-dihexyl-sexithiophene (DH6T) are presented as promising platforms for in-electrolyte sensing. Thin films of DH6T were investigated with regard to the influence of the substrate temperature during deposition on the grain size and structural order. The performance of SGOFETs can be improved by choosing suitable growth parameters that lead to a two-dimensional film morphology and a high degree of structural order. Furthermore, the capability of the SGOFETs to detect changes in the pH or ionic strength of the gate electrolyte is demonstrated and simulated. Finally, excellent transistor stability is confirmed by continuously operating the device over a period of several days, which is a consequence of the low threshold voltage of DH6T-based SGOFETs. Altogether, our results demonstrate the feasibility of high performance and highly stable organic semiconductor devices for chemical or biochemical applications.

In-situ SiN{sub x}/InN structures for InN field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zervos, Ch., E-mail: hzervos@physics.uoc.gr; Georgakilas, A.; Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete

Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performancemore » was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.« less

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

NASA Technical Reports Server (NTRS)

Mueller, Carl; Alterovitz, Samuel; Croke, Edward; Ponchak, George

2004-01-01

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Novel organic semiconductors and a high capacitance gate dielectric for organic thin film transistors

NASA Astrophysics Data System (ADS)

Cai, Xiuyu

2007-12-01

Organic semiconductors are attracting more and more interest as a promising set of materials in the field of electronics research. This thesis focused on several new organic semiconductors and a novel high-kappa dielectric thin film (SrTiO3), which are two essential parts in Organic Thin Film Transistors (OTFTs). Structure and morphology of thin films of tricyanovinyl capped oligothiophenes were studied using atomic force microscopy and x-ray diffraction. Thin film transistors of one compound exhibited a reasonable electron mobility of 0.02 cm2/Vs. Temperature dependent measurements on the thin film transistor based on this compound revealed shallow trap states that were interpreted in terms of a multiple trap and release model. Moreover, inversion of the majority charge carrier type from electrons to holes was observed when the number of oligothiophene rings increased to six and ambipolar transport behavior was observed for tricyanovinyl sexithiophene. Another interesting organic semiconductor compound is the fluoalkylquarterthiophene, which showed ambipolar transport and large hysteresis in the transfer curve. Due to the bistable state at floating gate, the thin film transistor was exploited to study non-volatile floating gate memory effects. The temperature dependence of the retention time for this memory device revealed that the electron trapping was an activated process. Following the earlier work on hybrid acene-thiophene organic semiconductors, new compounds with similar structure were studied to reveal the mechanism of the air-stability exhibited by some compounds. They all formed highly crystalline thin films and showed reasonable device performances which are well correlated with the molecular structures, thin film microstructures, and solid state packing. The most air-stable compound had no observable degradation with exposure to air for 15 months. SrTiO3 was developed to be employed in OTFTs. Optimization of thin film growth was performed using reactive sputtering growth. Excellent SrTiO3 epitaixal thin film growth was revealed on conductive SrTiO 3:Nb substrates. A maximum charge carrier density of 1014 cm-2 was obtained based on pentacene and perylene diimide thin film transistors. Some new physical phenomena, such as step-like transfer characteristic curve and negative transconductance, were observed at such high field effect induced charge carrier density.

Polycrystalline silicon ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Yan, F.; Estrela, P.; Mo, Y.; Migliorato, P.; Maeda, H.; Inoue, S.; Shimoda, T.

2005-01-01

We report the operation of polycrystalline silicon ion sensitive field effect transistors. These devices can be fabricated on inexpensive disposable substrates such as glass or plastics and are, therefore, promising candidates for low cost single-use intelligent multisensors. In this work we have developed an extended gate structure with a Si3N4 sensing layer. Nearly ideal pH sensitivity (54mV /pH) and stable operation have been achieved. Temperature effects have been characterized. A penicillin sensor has been fabricated by functionalizing the sensing area with penicillinase. The sensitivity to penicillin G is about 10mV/mM, in solutions with concentration lower than the saturation value, which is about 7 mM.

Deformable Organic Nanowire Field-Effect Transistors.

PubMed

Lee, Yeongjun; Oh, Jin Young; Kim, Taeho Roy; Gu, Xiaodan; Kim, Yeongin; Wang, Ging-Ji Nathan; Wu, Hung-Chin; Pfattner, Raphael; To, John W F; Katsumata, Toru; Son, Donghee; Kang, Jiheong; Matthews, James R; Niu, Weijun; He, Mingqian; Sinclair, Robert; Cui, Yi; Tok, Jeffery B-H; Lee, Tae-Woo; Bao, Zhenan

2018-02-01

Deformable electronic devices that are impervious to mechanical influence when mounted on surfaces of dynamically changing soft matters have great potential for next-generation implantable bioelectronic devices. Here, deformable field-effect transistors (FETs) composed of single organic nanowires (NWs) as the semiconductor are presented. The NWs are composed of fused thiophene diketopyrrolopyrrole based polymer semiconductor and high-molecular-weight polyethylene oxide as both the molecular binder and deformability enhancer. The obtained transistors show high field-effect mobility >8 cm 2 V -1 s -1 with poly(vinylidenefluoride-co-trifluoroethylene) polymer dielectric and can easily be deformed by applied strains (both 100% tensile and compressive strains). The electrical reliability and mechanical durability of the NWs can be significantly enhanced by forming serpentine-like structures of the NWs. Remarkably, the fully deformable NW FETs withstand 3D volume changes (>1700% and reverting back to original state) of a rubber balloon with constant current output, on the surface of which it is attached. The deformable transistors can robustly operate without noticeable degradation on a mechanically dynamic soft matter surface, e.g., a pulsating balloon (pulse rate: 40 min -1 (0.67 Hz) and 40% volume expansion) that mimics a beating heart, which underscores its potential for future biomedical applications. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Abe, Y.; Umeda, T.; Okamoto, M.; Kosugi, R.; Harada, S.; Haruyama, M.; Kada, W.; Hanaizumi, O.; Onoda, S.; Ohshima, T.

2018-01-01

We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

Characterization of multilayer GaAs/AlGaAs transistor structures by variable angle spectroscopic ellipsometry

NASA Technical Reports Server (NTRS)

Merkel, Kenneth G.; Snyder, Paul G.; Woollam, John A.; Alterovitz, Samuel; Rai, A. K.

1989-01-01

Variable angle of incidence spectroscopic ellipsometry (VASE) has been implemented as a means of determining layer thickness, alloy composition, and growth quality of GaAs/AlGaAs samples composed of relatively thick layers as well as superlattices. The structures studied in this work contained GaAs/AlGaAs multilayers with a superlattice 'barrier' and were grown for later formation of modulation-doped field effect transistors (MODFETs). Sample modeling was performed by treating the superlattice as a bulk AlGaAs layer of unknown composition. Extremely good data fits were realized when five layer thicknesses and two alloy ratios were allowed to vary in a regression analysis. Room temperature excitonic effects associated with the e-hh(1), e-lh(1) and e-hh(2) transitions were observed in the VASE data.

Investigation of defect-induced abnormal body current in fin field-effect-transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin

2015-08-24

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.

Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors.

PubMed

Chen, Hong-Chih; Chang, Ting-Chang; Lai, Wei-Chih; Chen, Guan-Fu; Chen, Bo-Wei; Hung, Yu-Ju; Chang, Kuo-Jui; Cheng, Kai-Chung; Huang, Chen-Shuo; Chen, Kuo-Kuang; Lu, Hsueh-Hsing; Lin, Yu-Hsin

2018-02-26

This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

All-Electrical Spin Field Effect Transistor in van der Waals Heterostructures at Room Temperature

NASA Astrophysics Data System (ADS)

Dankert, André; Dash, Saroj

Spintronics aims to exploit the spin degree of freedom in solid state devices for data storage and information processing. Its fundamental concepts (creation, manipulation and detection of spin polarization) have been demonstrated in semiconductors and spin transistor structures using electrical and optical methods. However, an unsolved challenge is the realization of all-electrical methods to control the spin polarization in a transistor manner at ambient temperatures. Here we combine graphene and molybdenum disulfide (MoS2) in a van der Waals heterostructure to realize a spin field-effect transistor (spin-FET) at room temperature. These two-dimensional crystals offer a unique platform due to their contrasting properties, such as weak spin-orbit coupling (SOC) in graphene and strong SOC in MoS2. The gate-tuning of the Schottky barrier at the MoS2/graphene interface and MoS2 channel yields spins to interact with high SOC material and allows us to control the spin polarization and lifetime. This all-electrical spin-FET at room temperature is a substantial step in the field of spintronics and opens a new platform for testing a plethora of exotic physical phenomena, which can be key building blocks in future device architectures.

Fabrication and single-electron-transfer operation of a triple-dot single-electron transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Mingyu, E-mail: mingyujo@eis.hokudai.ac.jp; Uchida, Takafumi; Tsurumaki-Fukuchi, Atsushi

2015-12-07

A triple-dot single-electron transistor was fabricated on silicon-on-insulator wafer using pattern-dependent oxidation. A specially designed one-dimensional silicon wire having small constrictions at both ends was converted to a triple-dot single-electron transistor by means of pattern-dependent oxidation. The fabrication of the center dot involved quantum size effects and stress-induced band gap reduction, whereas that of the two side dots involved thickness modulation because of the complex edge structure of two-dimensional silicon. Single-electron turnstile operation was confirmed at 8 K when a 100-mV, 1-MHz square wave was applied. Monte Carlo simulations indicated that such a device with inhomogeneous tunnel and gate capacitances canmore » exhibit single-electron transfer.« less

Radiation-stimulated processes in transistor temperature sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pavlyk, B. V.; Grypa, A. S.

2016-05-15

The features of the radiation-stimulated changes in the I–V and C–V characteristics of the emitter–base junction in KT3117 transistors are considered. It is shown that an increase in the current through the emitter junction is observed at the initial stage of irradiation (at doses of D < 4000 Gy for the “passive” irradiation mode and D < 5200 Gy for the “active” mode), which is caused by the effect of radiation-stimulated ordering of the defect-containing structure of the p–n junction. It is also shown that the X-ray irradiation (D < 14000 Gy), the subsequent relaxation (96 h), and thermal annealingmore » (2 h at 400 K) of the transistor temperature sensors under investigation result in an increase in their radiation resistance.« less

Effect of In Situ Annealing Treatment on the Mobility and Morphology of TIPS-Pentacene-Based Organic Field-Effect Transistors.

PubMed

Yang, Fuqiang; Wang, Xiaolin; Fan, Huidong; Tang, Ying; Yang, Jianjun; Yu, Junsheng

2017-08-23

In this work, organic field-effect transistors (OFETs) with a bottom gate top contact structure were fabricated by using a spray-coating method, and the influence of in situ annealing treatment on the OFET performance was investigated. Compared to the conventional post-annealing method, the field-effect mobility of OFET with 60 °C in situ annealing treatment was enhanced nearly four times from 0.056 to 0.191 cm 2 /Vs. The surface morphologies and the crystallization of TIPS-pentacene films were characterized by optical microscope, atomic force microscope, and X-ray diffraction. We found that the increased mobility was mainly attributed to the improved crystallization and highly ordered TIPS-pentacene molecules.

Effect of In Situ Annealing Treatment on the Mobility and Morphology of TIPS-Pentacene-Based Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Yang, Fuqiang; Wang, Xiaolin; Fan, Huidong; Tang, Ying; Yang, Jianjun; Yu, Junsheng

2017-08-01

In this work, organic field-effect transistors (OFETs) with a bottom gate top contact structure were fabricated by using a spray-coating method, and the influence of in situ annealing treatment on the OFET performance was investigated. Compared to the conventional post-annealing method, the field-effect mobility of OFET with 60 °C in situ annealing treatment was enhanced nearly four times from 0.056 to 0.191 cm2/Vs. The surface morphologies and the crystallization of TIPS-pentacene films were characterized by optical microscope, atomic force microscope, and X-ray diffraction. We found that the increased mobility was mainly attributed to the improved crystallization and highly ordered TIPS-pentacene molecules.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Unraveling the physics of vertical organic field effect transistors through nanoscale engineering of a self-assembled transparent electrode.

PubMed

Ben-Sasson, Ariel J; Tessler, Nir

2012-09-12

While organic transistors' performances are continually pushed to achieve lower power consumption, higher working frequencies, and higher current densities, a new type of organic transistors characterized by a vertical architecture offers a radically different design approach to outperform its traditional counterparts. Naturally, the distinct vertical architecture gives way to different governing physical ground rules and structural key features such as the need for an embedded transparent electrode. In this paper, we make use of a zero-frequency electric field-transparent patterned electrode produced through block-copolymer self-assembly based lithography to control the performances of the vertical organic field effect transistor (VOFET) and to study its governing physical mechanisms. Unlike other VOFET structures, this design, involving well-defined electrode architecture, is fully tractable, allowing for detailed modeling, analysis, and optimization. We provide for the first time a complete account of the physics underpinning the VOFET operation, considering two complementary mechanisms: the virtual contact formation (Schottky barrier lowering) and the induced potential barrier (solid-state triode-like shielding). We demonstrate how each mechanism, separately, accounts for the link between controllable nanoscale structural modifications in the patterned electrode and the VOFET performances. For example, the ON/OFF current ratio increases by up to 2 orders of magnitude when the perforations aspect ratio (height/width) decreases from ∼0.2 to ∼0.1. The patterned electrode is demonstrated to be not only penetrable to zero-frequency electric fields but also transparent in the visible spectrum, featuring uniformity, spike-free structure, material diversity, amenability with flexible surfaces, low sheet resistance (20-2000 Ω sq(-1)) and high transparency (60-90%). The excellent layer transparency of the patterned electrode and the VOFET's exceptional electrical performances make them both promising elements for future transparent and/or efficient organic electronics.

Electrical characteristics of organic perylene single-crystal-based field-effect transistors

NASA Astrophysics Data System (ADS)

Lee, Jin-Woo; Kang, Han-Saem; Kim, Min-Ki; Kim, Kihyun; Cho, Mi-Yeon; Kwon, Young-Wan; Joo, Jinsoo; Kim, Jae-Il; Hong, Chang-Seop

2007-12-01

We report on the fabrication of organic field-effect transistors (OFETs) using perylene single crystal as the active material and their electrical characteristics. Perylene single crystals were directly grown from perylene powder in a furnace using a relatively short growth time of 1-3 h. The crystalline structure of the perylene single crystals was characterized by means of a single-crystal x-ray diffractometer. In order to place the perylene single crystal onto the Au electrodes of the field-effect transistor, a polymethlymethacrylate thin layer was spin-coated on top of the crystal surface. The OFETs fabricated using the perylene single crystal showed a typical p-type operating mode. The field-effect mobility of the perylene crystal based OFETs was measured to be ˜9.62×10-4 cm2/V s at room temperature. The anisotropy of the mobility implying the existence of different mobilities when applying currents in different directions was observed for the OFETs, and the existence of traps in the perylene crystal was found through the measurements of the temperature-dependent mobility at various operating drain voltages.

25th anniversary article: organic field-effect transistors: the path beyond amorphous silicon.

PubMed

Sirringhaus, Henning

2014-03-05

Over the past 25 years, organic field-effect transistors (OFETs) have witnessed impressive improvements in materials performance by 3-4 orders of magnitude, and many of the key materials discoveries have been published in Advanced Materials. This includes some of the most recent demonstrations of organic field-effect transistors with performance that clearly exceeds that of benchmark amorphous silicon-based devices. In this article, state-of-the-art in OFETs are reviewed in light of requirements for demanding future applications, in particular active-matrix addressing for flexible organic light-emitting diode (OLED) displays. An overview is provided over both small molecule and conjugated polymer materials for which field-effect mobilities exceeding > 1 cm(2) V(-1) s(-1) have been reported. Current understanding is also reviewed of their charge transport physics that allows reaching such unexpectedly high mobilities in these weakly van der Waals bonded and structurally comparatively disordered materials with a view towards understanding the potential for further improvement in performance in the future. © 2014 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Experimental synchronization of chaos in a large ring of mutually coupled single-transistor oscillators: Phase, amplitude, and clustering effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minati, Ludovico, E-mail: lminati@ieee.org, E-mail: ludovico.minati@unitn.it

In this paper, experimental evidence of multiple synchronization phenomena in a large (n = 30) ring of chaotic oscillators is presented. Each node consists of an elementary circuit, generating spikes of irregular amplitude and comprising one bipolar junction transistor, one capacitor, two inductors, and one biasing resistor. The nodes are mutually coupled to their neighbours via additional variable resistors. As coupling resistance is decreased, phase synchronization followed by complete synchronization is observed, and onset of synchronization is associated with partial synchronization, i.e., emergence of communities (clusters). While component tolerances affect community structure, the general synchronization properties are maintained across three prototypes andmore » in numerical simulations. The clusters are destroyed by adding long distance connections with distant notes, but are otherwise relatively stable with respect to structural connectivity changes. The study provides evidence that several fundamental synchronization phenomena can be reliably observed in a network of elementary single-transistor oscillators, demonstrating their generative potential and opening way to potential applications of this undemanding setup in experimental modelling of the relationship between network structure, synchronization, and dynamical properties.« less

A comparison of etched-geometry and overgrown silicon permeable base transistors by two-dimensional numerical simulations

NASA Astrophysics Data System (ADS)

Vojak, B. A.; Alley, G. D.

1983-08-01

Two-dimensional numerical simulations are used to compare etched geometry and overgrown Si permeable base transistors (PTBs), considering both the etched collector and etched emitter biasing conditions made possible by the asymmetry of the etched structure. In PTB devices, the two-dimensional nature of the depletion region near the Schottky contact base grating results in a smaller electron barrier and, therefore, a larger collector current in the etched than in the overgrown structure. The parasitic feedback effects which result at high base-to-emitter bias levels lead to a deviation from the square-law behavior found in the collector characteristics of the overgrown PBT. These structures also have lower device capacitances and smaller transconductances at high base-to-emitter voltages. As a result, overgrown and etched structures have comparable predicted maximum values of the small signal unity short-circuit current gain frequency and maximum oscillation frequency.

Soluble fullerene derivatives: The effect of electronic structure on transistor performance and air stability

NASA Astrophysics Data System (ADS)

Ball, James M.; Bouwer, Ricardo K. M.; Kooistra, Floris B.; Frost, Jarvist M.; Qi, Yabing; Domingo, Ester Buchaca; Smith, Jeremy; de Leeuw, Dago M.; Hummelen, Jan C.; Nelson, Jenny; Kahn, Antoine; Stingelin, Natalie; Bradley, Donal D. C.; Anthopoulos, Thomas D.

2011-07-01

The family of soluble fullerene derivatives comprises a widely studied group of electron transporting molecules for use in organic electronic and optoelectronic devices. For electronic applications, electron transporting (n-channel) materials are required for implementation into organic complementary logic circuit architectures. To date, few soluble candidate materials have been studied that fulfill the stringent requirements of high carrier mobility and air stability. Here we present a study of three soluble fullerenes with varying electron affinity to assess the impact of electronic structure on device performance and air stability. Through theoretical and experimental analysis of the electronic structure, characterization of thin-film structure, and characterization of transistor device properties we find that the air stability of the present series of fullerenes not only depends on the absolute electron affinity of the semiconductor but also on the disorder within the thin-film.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

The use of harmonic analysis to investigate processes in irradiated transistor structures

NASA Astrophysics Data System (ADS)

Gnap, A. K.; Zaliubovskii, I. I.; Dakhov, V. M.; Pelikhatyi, N. M.; Filippenko, V. E.

A theoretical model is developed for analyzing the behavior of transistor structures under irradiation by high-energy particles. Specifically, attention is given to the operation of a transistor switch under irradiation by 2-MeV neutrons. The proposed approach involves the replacement of the actual voltage pulse by a trapezoidal pulse, and the application of harmonic analysis to the latter. The parameters of the actual pulse can then be determined from an analysis of the constant component of the signal and the value of one of its harmonics.

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

Multiscale modeling and computation of nano-electronic transistors and transmembrane proton channels

NASA Astrophysics Data System (ADS)

Chen, Duan

The miniaturization of nano-scale electronic transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. In biology, proton dynamics and transport across membrane proteins are of paramount importance to the normal function of living cells. Similar physical characteristics are behind the two subjects, and model simulations share common mathematical interests/challenges. In this thesis work, multiscale and multiphysical models are proposed to study the mechanisms of nanotransistors and proton transport in transmembrane at the atomic level. For nano-electronic transistors, we introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential. This framework enables us to put microscopic and macroscopic descriptions on an equal footing at nano-scale. Additionally, this model includes layered structures and random doping effect of nano-transistors. For transmembrane proton channels, we describe proton dynamics quantum mechanically via a density functional approach while implicitly treat numerous solvent molecules as a dielectric continuum. The densities of all other ions in the solvent are assumed to obey the Boltzmann distribution. The impact of protein molecular structure and its charge polarization on the proton transport is considered in atomic details. We formulate a total free energy functional to include kinetic and potential energies of protons, as well as electrostatic energy of all other ions on an equal footing. For both nano-transistors and proton channels systems, the variational principle is employed to derive nonlinear governing equations. The Poisson-Kohn-Sham equations are derived for nano-transistors while the generalized Poisson-Boltzmann equation and Kohn-Sham equation are obtained for proton channels. Related numerical challenges in simulations are addressed: the matched interface and boundary (MIB) method, the Dirichlet-to-Neumann mapping (DNM) technique, and the Krylov subspace and preconditioner theory are introduced to improve the computational efficiency of the Poisson-type equation. The quantum transport theory is employed to solve the Kohn-Sham equation. The Gummel iteration and relaxation technique are utilized for overall self-consistent iterations. Finally, applications are considered and model validations are verified by realistic nano-transistors and transmembrane proteins. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our threedimensional numerical simulations. For these devices, the current uctuation and voltage threshold lowering effect induced by discrete dopants are explored. For proton transport, a realistic channel protein, the Gramicidin A (GA) is used to demonstrate the performance of the proposed proton channel model and validate the efficiency of the proposed mathematical algorithms. The electrostatic characteristics of the GA channel is analyzed with a wide range of model parameters. Proton channel conductances are studied over a number of applied voltages and reference concentrations. Comparisons with experimental data are utilized to verify our model predictions.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Organic permeable-base transistors - superb power efficiency at highest frequencies (Conference Presentation)

NASA Astrophysics Data System (ADS)

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Scholz, Reinhard; Lüssem, Björn; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Kasemann, Daniel; Leo, Karl

2016-11-01

Organic field-effect transistors (OFET) are important elements in thin-film electronics, being considered for flat-panel or flexible displays, radio frequency identification systems, and sensor arrays. To optimize the devices for high-frequency operation, the channel length, defined as the horizontal distance between the source and the drain contact, can be scaled down. Here, an architecture with a vertical current flow, in particular the Organic Permeable-Base Transistors (OPBT), opens up new opportunities, because the effective transit length in vertical direction is precisely tunable in the nanometer range by the thickness of the semiconductor layer. We present an advanced OPBT, competing with best OFETs while a low-cost, OLED-like fabrication with low-resolution shadow masks is used (Klinger et al., Adv. Mater. 27, 2015). Its design consists of a stack of three parallel electrodes separated by two semiconductor layers of C60 . The vertical current flow is controlled by the middle base electrode with nano-sized openings passivated by an native oxide. Using insulated layers to structure the active area, devices show an on/off ratio of 10⁶ , drive 11 A/cm² at an operation voltage of 1 V, and have a low subthreshold slope of 102 mV/decade. These OPBTs show a unity current-gain transit frequency of 2.2 MHz and off-state break-down fields above 1 MV/cm. Thus, our optimized setup does not only set a benchmark for vertical organic transistors, but also outperforms best lateral OFETs using similar low-cost structuring techniques in terms of power efficiency at high frequencies.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Vertical phase separation of 6,13-bis(triisopropylsilylethynyl) pentacene/poly(methyl methacrylate) blends prepared by electrostatic spray deposition for organic field-effect transistors

NASA Astrophysics Data System (ADS)

Onojima, Norio; Hara, Kazuhiro; Nakamura, Ayato

2017-05-01

Blend films composed of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) and poly(methyl methacrylate) (PMMA) were prepared by electrostatic spray deposition (ESD). ESD is considered as an intermediate process between dry and wet processes since the solvent present in small droplets can almost be evaporated before arriving at the substrate. Post-drying treatments with the time-consuming evaporation of residual solvents can be omitted. However, it is still not clear that a vertically phase-separated structure can be formed in the ESD process since the vertical phase separation of the blend films is associated with the solvent evaporation. In this study, we fabricated bottom-gate, top-contact organic field-effect transistors based on the blend films prepared by ESD and the devices exhibited transistor behavior with small hysteresis. This result demonstrates that the vertical phase separation of a blend film (upper TIPS pentacene active layer/bottom PMMA gate insulator) can occur in the facile one-step ESD process.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Integrated digital inverters based on two-dimensional anisotropic ReS2 field-effect transistors

PubMed Central

Liu, Erfu; Fu, Yajun; Wang, Yaojia; Feng, Yanqing; Liu, Huimei; Wan, Xiangang; Zhou, Wei; Wang, Baigeng; Shao, Lubin; Ho, Ching-Hwa; Huang, Ying-Sheng; Cao, Zhengyi; Wang, Laiguo; Li, Aidong; Zeng, Junwen; Song, Fengqi; Wang, Xinran; Shi, Yi; Yuan, Hongtao; Hwang, Harold Y.; Cui, Yi; Miao, Feng; Xing, Dingyu

2015-01-01

Semiconducting two-dimensional transition metal dichalcogenides are emerging as top candidates for post-silicon electronics. While most of them exhibit isotropic behaviour, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here we present atomically thin rhenium disulfide (ReS2) flakes with unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated monolayer and few-layer ReS2 field-effect transistors, which exhibit competitive performance with large current on/off ratios (∼107) and low subthreshold swings (100 mV per decade). The observed anisotropic ratio along two principle axes reaches 3.1, which is the highest among all known two-dimensional semiconducting materials. Furthermore, we successfully demonstrated an integrated digital inverter with good performance by utilizing two ReS2 anisotropic field-effect transistors, suggesting the promising implementation of large-scale two-dimensional logic circuits. Our results underscore the unique properties of two-dimensional semiconducting materials with low crystal symmetry for future electronic applications. PMID:25947630

A multi-agent quantum Monte Carlo model for charge transport: Application to organic field-effect transistors

NASA Astrophysics Data System (ADS)

Bauer, Thilo; Jäger, Christof M.; Jordan, Meredith J. T.; Clark, Timothy

2015-07-01

We have developed a multi-agent quantum Monte Carlo model to describe the spatial dynamics of multiple majority charge carriers during conduction of electric current in the channel of organic field-effect transistors. The charge carriers are treated by a neglect of diatomic differential overlap Hamiltonian using a lattice of hydrogen-like basis functions. The local ionization energy and local electron affinity defined previously map the bulk structure of the transistor channel to external potentials for the simulations of electron- and hole-conduction, respectively. The model is designed without a specific charge-transport mechanism like hopping- or band-transport in mind and does not arbitrarily localize charge. An electrode model allows dynamic injection and depletion of charge carriers according to source-drain voltage. The field-effect is modeled by using the source-gate voltage in a Metropolis-like acceptance criterion. Although the current cannot be calculated because the simulations have no time axis, using the number of Monte Carlo moves as pseudo-time gives results that resemble experimental I/V curves.

A multi-agent quantum Monte Carlo model for charge transport: Application to organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bauer, Thilo; Jäger, Christof M.; Jordan, Meredith J. T.

2015-07-28

We have developed a multi-agent quantum Monte Carlo model to describe the spatial dynamics of multiple majority charge carriers during conduction of electric current in the channel of organic field-effect transistors. The charge carriers are treated by a neglect of diatomic differential overlap Hamiltonian using a lattice of hydrogen-like basis functions. The local ionization energy and local electron affinity defined previously map the bulk structure of the transistor channel to external potentials for the simulations of electron- and hole-conduction, respectively. The model is designed without a specific charge-transport mechanism like hopping- or band-transport in mind and does not arbitrarily localizemore » charge. An electrode model allows dynamic injection and depletion of charge carriers according to source-drain voltage. The field-effect is modeled by using the source-gate voltage in a Metropolis-like acceptance criterion. Although the current cannot be calculated because the simulations have no time axis, using the number of Monte Carlo moves as pseudo-time gives results that resemble experimental I/V curves.« less

Transport properties of field-effect transistor with Langmuir-Blodgett films of C60 dendrimer and estimation of impurity levels

NASA Astrophysics Data System (ADS)

Kawasaki, Naoko; Nagano, Takayuki; Kubozono, Yoshihiro; Sako, Yuuki; Morimoto, Yu; Takaguchi, Yutaka; Fujiwara, Akihiko; Chu, Chih-Chien; Imae, Toyoko

2007-12-01

Field-effect transistor (FET) device has been fabricated with Langmuir-Blodgett films of C60 dendrimer. The device showed n-channel normally off characteristics with the field-effect mobility of 2.7×10-3cm2V-1s-1 at 300K, whose value is twice as high as that (1.4×10-3cm2V-1s-1) for the FET with spin-coated films of C60 dendrimer. This originates from the formation of ordered π-conduction network of C60 moieties. From the temperature dependence of field-effect mobility, a structural phase transition has been observed at around 300K. Furthermore, the density of states for impurity levels was estimated in the Langmuir-Blodgett films.

Chemical stability and electrical performance of dual-active-layered zinc-tin-oxide/indium-gallium-zinc-oxide thin-film transistors using a solution process.

PubMed

Kim, Chul Ho; Rim, You Seung; Kim, Hyun Jae

2013-07-10

We investigated the chemical stability and electrical properties of dual-active-layered zinc-tin-oxide (ZTO)/indium-gallium-zinc-oxide (IGZO) structures (DALZI) with the durability of the chemical damage. The IGZO film was easily corroded or removed by an etchant, but the DALZI film was effectively protected by the high chemical stability of ZTO. Furthermore, the electrical performance of the DALZI thin-film transistor (TFT) was improved by densification compared to the IGZO TFT owing to the passivation of the pin holes or pore sites and the increase in the carrier concentration due to the effect of Sn(4+) doping.

Spectral resolution of states relevant to photoinduced charge transfer in modified pentacene/ZnO field-effect transistors

NASA Astrophysics Data System (ADS)

Spalenka, Josef W.; Mannebach, Ehren M.; Bindl, Dominick J.; Arnold, Michael S.; Evans, Paul G.

2011-11-01

Pentacene field-effect transistors incorporating ZnO quantum dots can be used as a sensitive probe of the optical properties of a buried donor-acceptor interface. Photoinduced charge transfer between pentacene and ZnO in these devices varies with incident photon energy and reveals which energies will contribute most to charge transfer in other structures. A subsequent slow return to the dark state following the end of illumination arises from near-interface traps. Charge transfer has a sharp onset at 1.7 eV and peaks at 1.82 and 2.1 eV due to transitions associated with excitons, features absent in pentacene FETs without ZnO.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Length separation of single-walled carbon nanotubes and its impact on structural and electrical properties of wafer-level fabricated carbon nanotube-field-effect transistors

NASA Astrophysics Data System (ADS)

Böttger, Simon; Hermann, Sascha; Schulz, Stefan E.; Gessner, Thomas

2016-10-01

For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT-FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT-FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT-FETs fabricated with a wafer-level technology.

Semiconductor devices having a recessed electrode structure

DOEpatents

Palacios, Tomas Apostol; Lu, Bin; Matioli, Elison de Nazareth

2015-05-26

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Degradation of Au-Ti contacts of SiGe HBTs during electromagnetic field stress

NASA Astrophysics Data System (ADS)

Alaeddine, A.; Genevois, C.; Kadi, M.; Cuvilly, F.; Daoud, K.

2011-02-01

This paper addresses electromagnetic field stress effects on SiGe heterojunction bipolar transistors (HBTs)' reliability issues, focusing on the relationship between the stress-induced current and device structure degradations. The origin of leakage currents and electrical parameter shifts in failed transistors has been studied by complementary failure analysis techniques. Characterization of the structure before and after ageing was performed by transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). For the stressed samples, interface deformations of the titanium (Ti) thin film around all gold (Au) contacts have been clearly detected. These degradations include localized interface reaction between Au and Ti layers as well as their lateral atomic migration causing a significant reduction of Ti thickness. EDS analysis of the disordered region which is near the Si3N4 interface has shown significant signals from Au. These observations could be attributed to the coupling between high current densities induced by stress and thermal effects due to local heating effects.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

The role of contact resistance in graphene field-effect devices

NASA Astrophysics Data System (ADS)

Giubileo, Filippo; Di Bartolomeo, Antonio

2017-08-01

The extremely high carrier mobility and the unique band structure, make graphene very useful for field-effect transistor applications. According to several works, the primary limitation to graphene based transistor performance is not related to the material quality, but to extrinsic factors that affect the electronic transport properties. One of the most important parasitic element is the contact resistance appearing between graphene and the metal electrodes functioning as the source and the drain. Ohmic contacts to graphene, with low contact resistances, are necessary for injection and extraction of majority charge carriers to prevent transistor parameter fluctuations caused by variations of the contact resistance. The International Technology Roadmap for Semiconductors, toward integration and down-scaling of graphene electronic devices, identifies as a challenge the development of a CMOS compatible process that enables reproducible formation of low contact resistance. However, the contact resistance is still not well understood despite it is a crucial barrier towards further improvements. In this paper, we review the experimental and theoretical activity that in the last decade has been focusing on the reduction of the contact resistance in graphene transistors. We will summarize the specific properties of graphene-metal contacts with particular attention to the nature of metals, impact of fabrication process, Fermi level pinning, interface modifications induced through surface processes, charge transport mechanism, and edge contact formation.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Failure Mechanisms of GaAs Transistors - A Literature Survey

DTIC Science & Technology

1990-03-01

doping profile cannot be as sharp as with epitaxial methods. This is the result of the statistics of the implantation and the general diffusion that...Speed GaAs Logic Gates 5.1 GaAs PLANAR TRANSITOR STRUCTURES USED IN IC’S Some planar transistor structures used in IC’s with examples of the

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

The effect of asymmetrical electrode form after negative bias illuminated stress in amorphous IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Su, Wan-Ching; Chang, Ting-Chang; Liao, Po-Yung; Chen, Yu-Jia; Chen, Bo-Wei; Hsieh, Tien-Yu; Yang, Chung-I.; Huang, Yen-Yu; Chang, Hsi-Ming; Chiang, Shin-Chuan; Chang, Kuan-Chang; Tsai, Tsung-Ming

2017-03-01

This paper investigates the degradation behavior of InGaZnO thin film transistors (TFTs) under negative bias illumination stress (NBIS). TFT devices with two different source and drain layouts were exanimated: one having a parallel format electrode and the other with UI format electrode. UI means that source/drain electrodes shapes is defined as a forked-shaped structure. The I-V curve of the parallel electrode exhibited a symmetric degradation under forward and reverse sweeping in the saturation region after 1000 s NBIS. In contrast, the I-V curve of the UI electrode structure under similar conditions was asymmetric. The UI electrode structure also shows a stretch-out phenomenon in its C-V measurement. Finally, this work utilizes the ISE-Technology Computer Aided Design (ISE-TCAD) system simulations, which simulate the electron field and IV curves, to analyze the mechanisms dominating the parallel and UI device degradation behaviors.

Titanyl phthalocyanine ambipolar thin film transistors making use of carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Coppedè, Nicola; Valitova, Irina; Mahvash, Farzaneh; Tarabella, Giuseppe; Ranzieri, Paolo; Iannotta, Salvatore; Santato, Clara; Martel, Richard; Cicoira, Fabio

2014-12-01

The capability of efficiently injecting charge carriers into organic films and finely tuning their morphology and structure is crucial to improve the performance of organic thin film transistors (OTFTs). In this work, we investigate OTFTs employing carbon nanotubes (CNTs) as the source-drain electrodes and, as the organic semiconductor, thin films of titanyl phthalocyanine (TiOPc) grown by supersonic molecular beam deposition (SuMBD). While CNT electrodes have shown an unprecedented ability to improve charge injection in OTFTs, SuMBD is an effective technique to tune film morphology and structure. Varying the substrate temperature during deposition, we were able to grow both amorphous (low substrate temperature) and polycrystalline (high substrate temperature) films of TiOPc. Regardless of the film morphology and structure, CNT electrodes led to superior charge injection and transport performance with respect to benchmark Au electrodes. Vacuum annealing of polycrystalline TiOPc films with CNT electrodes yielded ambipolar OTFTs.

A new expression of Ns versus Ef to an accurate control charge model for AlGaAs/GaAs

NASA Astrophysics Data System (ADS)

Bouneb, I.; Kerrour, F.

2016-03-01

Semi-conductor components become the privileged support of information and communication, particularly appreciation to the development of the internet. Today, MOS transistors on silicon dominate largely the semi-conductors market, however the diminution of transistors grid length is not enough to enhance the performances and respect Moore law. Particularly, for broadband telecommunications systems, where faster components are required. For this reason, alternative structures proposed like hetero structures IV-IV or III-V [1] have been.The most effective components in this area (High Electron Mobility Transistor: HEMT) on IIIV substrate. This work investigates an approach for contributing to the development of a numerical model based on physical and numerical modelling of the potential at heterostructure in AlGaAs/GaAs interface. We have developed calculation using projective methods allowed the Hamiltonian integration using Green functions in Schrodinger equation, for a rigorous resolution “self coherent” with Poisson equation. A simple analytical approach for charge-control in quantum well region of an AlGaAs/GaAs HEMT structure was presented. A charge-control equation, accounting for a variable average distance of the 2-DEG from the interface was introduced. Our approach which have aim to obtain ns-Vg characteristics is mainly based on: A new linear expression of Fermi-level variation with two-dimensional electron gas density in high electron mobility and also is mainly based on the notion of effective doping and a new expression of AEc

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Photocurrent spectroscopy of pentacene thin film transistors

NASA Astrophysics Data System (ADS)

Breban, Mihaela

We demonstrate the application of photocurrent modulation spectroscopy in characterizing the performance of organic thin-film transistors. A parallel analysis of the direct current and photocurrent voltage characteristics provides a model free determination of the field-effect mobility and the density of free carriers in the transistor channel as a function of the applied gate voltage. Applying this technique to pentacene thin-film transistors demonstrates that the mobility increases as V1/3g . The free-carrier density is approximately 1/10 of the expected capacitive charge, and the mobility increases monotonically with the free carrier density, consistent with the trap and release model of transport. Also, the modulated photocurrent spectroscopy can be used as a probe of defect states in pentacene thin film transistors, measuring simultaneously the magnitude and the phase of the photocurrent as a function of the modulation frequency. This is accomplished by modeling the photo-carrier generation process as exciton dissociation via interaction with localized traps. Experimental data reveal a Gaussian distribution of localized states centered around 0.3 eV above the highest occupied molecular orbital. We also investigated the effect of the gate dielectric material with our probe and found that the position of the extracted Gaussian slightly shifts, consistent with the expected image charge effect for Pn through the dielectric substrate. Also shifts in the Gaussian position for samples fabricated with variable deposition conditions are correlated with changes in Pn morphology. The morphological differences between Pn films were also detected in current-voltage characteristics and photocurrent spectra. However, the origin of the ubiquitous 0.3 eV defect in Pn seems to be unrelated to structural differences in Pn films.

Facile fabrication of high-performance InGaZnO thin film transistor using hydrogen ion irradiation at room temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ahn, Byung Du; Park, Jin-Seong; Chung, K. B., E-mail: kbchung@dongguk.edu

Device performance of InGaZnO (IGZO) thin film transistors (TFTs) are investigated as a function of hydrogen ion irradiation dose at room temperature. Field effect mobility is enhanced, and subthreshold gate swing is improved with the increase of hydrogen ion irradiation dose, and there is no thermal annealing. The electrical device performance is correlated with the electronic structure of IGZO films, such as chemical bonding states, features of the conduction band, and band edge states below the conduction band. The decrease of oxygen deficient bonding and the changes in electronic structure of the conduction band leads to the improvement of devicemore » performance in IGZO TFT with an increase of the hydrogen ion irradiation dose.« less

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Review of Heterojunctin Bipolar Transistor Structure, Applications, and Reliability

NASA Technical Reports Server (NTRS)

Lee, C.; Kayali, S.

1993-01-01

Heterojunction Bipolar Transistors (HBTs) are increasingly employed in high frequency, high linerity, and high efficiency applications. As the utilization of these devices becomes more widespread, their operation will be viewed with more scrutiny.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

NASA Astrophysics Data System (ADS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Methodological comparison on OLED and OLET fabrication

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Hambali, Nor Azura Malini Ahmad; Wahid, Mohamad Halim Abd; Retnasamy, Vithyacharan; Shahimin, Mukhzeer Mohamad

2018-02-01

The potential of organic semiconductor devices for light generation is demonstrated by the commercialization of display technologies based on organic light emitting diode (OLED). In OLED, organic materials play the role of light emission once the current is passed through. However, OLED do have major drawbacks whereby it suffers from photon loss and exciton quenching. Organic light emitting transistor (OLET) emerged as the new technology to compensate the efficiency and brightness loss encountered in OLED. The structure has combinational capability to switch the electronic signal such as the field effect transistor (FET) as well as light generation. The aim of this study is to methodologically compare and contrast fabrication process and evaluate feasibility of both organic light emitting diode (OLED) and organic light emitting transistor (OLET). The proposed light emitting layer in this study is poly [2-methoxy-5- (2'-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV).

Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

2007-12-01

This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

A light-stimulated synaptic transistor with synaptic plasticity and memory functions based on InGaZnO{sub x}–Al{sub 2}O{sub 3} thin film structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, H. K.; Chen, T. P., E-mail: echentp@ntu.edu.sg; Liu, P.

In this work, a synaptic transistor based on the indium gallium zinc oxide (IGZO)–aluminum oxide (Al{sub 2}O{sub 3}) thin film structure, which uses ultraviolet (UV) light pulses as the pre-synaptic stimulus, has been demonstrated. The synaptic transistor exhibits the behavior of synaptic plasticity like the paired-pulse facilitation. In addition, it also shows the brain's memory behaviors including the transition from short-term memory to long-term memory and the Ebbinghaus forgetting curve. The synapse-like behavior and memory behaviors of the transistor are due to the trapping and detrapping processes of the holes, which are generated by the UV pulses, at the IGZO/Al{submore » 2}O{sub 3} interface and/or in the Al{sub 2}O{sub 3} layer.« less

The fabrication and optical detection of a vertical structure organic thin film transistor

NASA Astrophysics Data System (ADS)

Zhang, H.; Wang, D.; Jia, P.

2014-03-01

Using vacuum evaporation and sputtering process, we prepared a photoelectric transistor with the vertical structure of Cu/copper phthalocyanine (CuPc)/Al/copper phthalocyanine (CuPc)/ITO. The material of CuPc semiconductor has good photosensitive properties. Excitons will be generated after the optical signal irradiation in semiconductor material, and then transformed into photocurrent under the built-in electric field formed by the Schottky contact, as the organic transistor drive current makes the output current enlarged. The results show that the I-V characteristics of transistor are unsaturated. When device was irradiated by full band (white) light, its working current significantly increased. In full band white light, when Vec = 3 V, the ratio of light and no light current was ranged for 2.9-6.4 times. Device in the absence of light current amplification coefficient is 16.5, and white light amplification coefficient is 98.65.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Diode having trenches in a semiconductor region

DOEpatents

Palacios, Tomas Apostol; Lu, Bin; Matioli, Elison de Nazareth

2016-03-22

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

PubMed Central

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-01-01

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development. PMID:28350370

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

PubMed

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-03-28

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

Improvement in the performance of graphene nanoribbon p-i-n tunneling field effect transistors by applying lightly doped profile on drain region

NASA Astrophysics Data System (ADS)

Naderi, Ali

2017-12-01

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrödinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain-source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Electrical and Structural Origin of Self-Healing Phenomena in Pentacene Thin Films.

PubMed

Kang, Evan S H; Zhang, Hongbin; Donner, Wolfgang; von Seggern, Heinz

2017-04-01

Self-healing induced by structural phase transformation is demonstrated using pentacene field-effect transistors. During the self-healing process, the electrical properties at the pentacene interfaces improve due to the phase transformation from monolayer phase to thin-film phase. Enhanced mobility is confirmed by first-principles calculations. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Mixed Carrier Conduction in Modulation-doped Field Effect Transistors

NASA Technical Reports Server (NTRS)

Schacham, S. E.; Haugland, E. J.; Mena, R. A.; Alterovitz, S. A.

1995-01-01

The contribution of more than one carrier to the conductivity in modulation-doped field effect transistors (MODFET) affects the resultant mobility and complicates the characterization of these devices. Mixed conduction arises from the population of several subbands in the two-dimensional electron gas (2DEG), as well as the presence of a parallel path outside the 2DEG. We characterized GaAs/AlGaAs MODFET structures with both delta and continuous doping in the barrier. Based on simultaneous Hall and conductivity analysis we conclude that the parallel conduction is taking place in the AlGaAs barrier, as indicated by the carrier freezeout and activation energy. Thus, simple Hall analysis of these structures may lead to erroneous conclusions, particularly for real-life device structures. The distribution of the 2D electrons between the various confined subbands depends on the doping profile. While for a continuously doped barrier the Shubnikov-de Haas analysis shows superposition of two frequencies for concentrations below 10(exp 12) cm(exp -2), for a delta doped structure the superposition is absent even at 50% larger concentrations. This result is confirmed by self-consistent analysis, which indicates that the concentration of the second subband hardly increases.

ZnO nanorods for electronic and photonic device applications

NASA Astrophysics Data System (ADS)

Yi, Gyu-Chul; Yoo, Jinkyoung; Park, Won Il; Jung, Sug Woo; An, Sung Jin; Kim, H. J.; Kim, D. W.

2005-11-01

We report on catalyst-free growth of ZnO nanorods and their nano-scale electrical and optical device applications. Catalyst-free metalorganic vapor-phase epitaxy (MOVPE) enables fabrication of size-controlled high purity ZnO single crystal nanorods. Various high quality nanorod heterostructures and quantum structures based on ZnO nanorods were also prepared using the MOVPE method and characterized using scanning electron microscopy, transmission electron microscopy, and optical spectroscopy. From the photoluminescence spectra of ZnO/Zn 0.8Mg 0.2O nanorod multi-quantum-well structures, in particular, we observed a systematic blue-shift in their PL peak position due to quantum confinement effect of carriers in nanorod quantum structures. For ZnO/ZnMgO coaxial nanorod heterostructures, photoluminescence intensity was significantly increased presumably due to surface passivation and carrier confinement. In addition to the growth and characterizations of ZnO nanorods and their quantum structures, we fabricated nanoscale electronic devices based on ZnO nanorods. We report on fabrication and device characteristics of metal-oxidesemiconductor field effect transistors (MOSFETs), Schottky diodes, and metal-semiconductor field effect transistors (MESFETs) as examples of the nanodevices. In addition, electroluminescent devices were fabricated using vertically aligned ZnO nanorods grown p-type GaN substrates, exhibiting strong visible electroluminescence.

Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

DOEpatents

Spahn, Olga B.; Lear, Kevin L.

1998-01-01

A semiconductor structure. The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g. Al.sub.2 O.sub.3), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3-1.6 .mu.m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation.

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

NASA Technical Reports Server (NTRS)

Kim, Jae-Hoon; Lin, Steven H.

1991-01-01

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Electron and hole photoemission detection for band offset determination of tunnel field-effect transistor heterojunctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Wei; Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871; Zhang, Qin

2014-11-24

We report experimental methods to ascertain a complete energy band alignment of a broken-gap tunnel field-effect transistor based on an InAs/GaSb hetero-junction. By using graphene as an optically transparent electrode, both the electron and hole barrier heights at the InAs/GaSb interface can be quantified. For a Al{sub 2}O{sub 3}/InAs/GaSb layer structure, the barrier height from the top of the InAs and GaSb valence bands to the bottom of the Al{sub 2}O{sub 3} conduction band is inferred from electron emission whereas hole emissions reveal the barrier height from the top of the Al{sub 2}O{sub 3} valence band to the bottom ofmore » the InAs and GaSb conduction bands. Subsequently, the offset parameter at the broken gap InAs/GaSb interface is extracted and thus can be used to facilitate the development of predicted models of electron quantum tunneling efficiency and transistor performance.« less

A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Sedki, Amor; André, Nicolas; Kilchytska, Valéria; Gérard, Pierre; Ali, Zeeshan; Udrea, Florin; Flandre, Denis

2018-01-01

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

Proton irradiation effects on gallium nitride-based devices

NASA Astrophysics Data System (ADS)

Karmarkar, Aditya P.

Proton radiation effects on state-of-the-art gallium nitride-based devices were studied using Schottky diodes and high electron-mobility transistors. The device degradation was studied over a wide range of proton fluences. This study allowed for a correlation between proton irradiation effects between different types of devices and enhanced the understanding of the mechanisms responsible for radiation damage in GaN-based devices. Proton irradiation causes reduced carrier concentration and increased series resistance and ideality factor in Schottky diodes. 1.0-MeV protons cause greater degradation than 1.8-MeV protons because of their higher non-ionizing energy loss. The displacement damage in Schottky diodes recovers during annealing. High electron-mobility transistors exhibit extremely high radiation tolerance, continuing to perform up to a fluence of ˜1014 cm-2 of 1.8-MeV protons. Proton irradiation creates defect complexes in the thin-film structure. Decreased sheet carrier mobility due to increased carrier scattering and decreased sheet carrier density due to carrier removal by the defect centers are the primary damage mechanisms. Interface disorder at either the Schottky or the Ohmic contact plays a relatively unimportant part in overall device degradation in both Schottky diodes and high electron-mobility transistors.

Near-Infrared to Visible Organic Upconversion Devices Based on Organic Light-Emitting Field Effect Transistors.

PubMed

Li, Dongwei; Hu, Yongsheng; Zhang, Nan; Lv, Ying; Lin, Jie; Guo, Xiaoyang; Fan, Yi; Luo, Jinsong; Liu, Xingyuan

2017-10-18

The near-infrared (NIR) to visible upconversion devices have attracted great attention because of their potential applications in the fields of night vision, medical imaging, and military security. Herein, a novel all-organic upconversion device architecture has been first proposed and developed by incorporating a NIR absorption layer between the carrier transport layer and the emission layer in heterostructured organic light-emitting field effect transistors (OLEFETs). The as-prepared devices show a typical photon-to-photon upconversion efficiency as high as 7% (maximum of 28.7% under low incident NIR power intensity) and millisecond-scale response time, which are the highest upconversion efficiency and one of the fastest response time among organic upconversion devices as referred to the previous reports up to now. The high upconversion performance mainly originates from the gain mechanism of field-effect transistor structures and the unique advantage of OLEFETs to balance between the photodetection and light emission. Meanwhile, the strategy of OLEFETs also offers the advantage of high integration so that no extra OLED is needed in the organic upconversion devices. The results would pave way for low-cost, flexible and portable organic upconversion devices with high efficiency and simplified processing.

Room Temperature Silicene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Akinwande, Deji

Silicene, a buckled Si analogue of graphene, holds significant promise for future electronics beyond traditional CMOS. In our predefined experiments via encapsulated delamination with native electrodes approach, silicene devices exhibit an ambipolar charge transport behavior, corroborating theories on Dirac band in Ag-free silicene. Monolayer silicene device has extracted field-effect mobility within the theoretical expectation and ON/OFF ratio greater than monolayer graphene, while multilayer silicene devices show decreased mobility and gate modulation. Air-stability of silicene devices depends on the number of layers of silicene and intrinsic material structure determined by growth temperature. Few or multi-layer silicene devices maintain their ambipolar behavior for days in contrast to minutes time scale for monolayer counterparts under similar conditions. Multilayer silicene grown at different temperatures below 300oC possess different intrinsic structures and yield different electrical property and air-stability. This work suggests a practical prospect to enable more air-stable silicene devices with layer and growth condition control, which can be leveraged for other air-sensitive 2D materials. In addition, we describe quantum and classical transistor device concepts based on silicene and related buckled materials that exploit the 2D topological insulating phenomenon. The transistor device physics offer the potential for ballistic transport that is robust against scattering and can be employed for both charge and spin transport. This work was supported by the ARO.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Properties of nanosheets of 2D-borocarbonitrides related to energy devices, transistors and other areas

NASA Astrophysics Data System (ADS)

Sreedhara, M. B.; Gopalakrishnan, K.; Bharath, B.; Kumar, Ram; Kulkarni, G. U.; Rao, C. N. R.

2016-07-01

We have prepared borocarbonitrides of various compositions with extended sheet morphology, by the reaction of few-layer graphene with boric acid and urea at 900 °C and characterized them in detail. Supercapacitor performance of the borocarbonitrides has been studied in detail, the composition containing more pyridinc nitrogen exhibiting a specific capacitance of 306 F/g at 0.2 A/g. This composition also shows good oxygen reduction reaction (ORR) activity with an electron transfer number close to 4. The extended sheet structures of the BxCyNz samples has enabled us to fabricate field-effect transistors. These materials also show reasonable UV photoresponse.

Quantum-well-base heterojunction bipolar light-emitting transistor

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Chan, R.

2004-03-01

This letter reports the enhanced radiative recombination realized by incorporating InGaAs quantum wells in the base layer of light-emitting InGaP/GaAs heterojunction bipolar transistors (LETs) operating in the common-emitter configuration. Two 50 Å In1-xGaxAs (x=85%) quantum wells (QWs) acting, in effect, as electron capture centers ("traps") are imbedded in the 300 Å GaAs base layer, thus improving (as a "collector" and recombination center) the light emission intensity compared to a similar LET structure without QWs in the base. Gigahertz operation of the QW LET with simultaneously amplified electrical output and an optical output with signal modulation is demonstrated.

Dependence of Internal Crystal Structures of InAs Nanowires on Electrical Characteristics of Field Effect Transistors

NASA Astrophysics Data System (ADS)

Han, Sangmoon; Choi, Ilgyu; Lee, Kwanjae; Lee, Cheul-Ro; Lee, Seoung-Ki; Hwang, Jeongwoo; Chung, Dong Chul; Kim, Jin Soo

2018-02-01

We report on the dependence of internal crystal structures on the electrical properties of a catalyst-free and undoped InAs nanowire (NW) formed on a Si(111) substrate by metal-organic chemical vapor deposition. Cross-sectional transmission electron microscopy images, obtained from four different positions of a single InAs NW, indicated that the wurtzite (WZ) structure with stacking faults was observed mostly in the bottom region of the NW. Vertically along the InAs NW, the amount of stacking faults decreased and a zinc-blende (ZB) structure was observed. At the top of the NW, the ZB structure was prominently observed. The resistance and resistivity of the top region of the undoped InAs NW with the ZB structure were measured to be 121.5 kΩ and 0.19 Ω cm, respectively, which are smaller than those of the bottom region with the WZ structure, i.e., 251.8 kΩ and 0.39 Ω cm, respectively. The reduction in the resistance of the top region of the NW is attributed to the improvement in the crystal quality and the change in the ZB crystal structure. For a field effect transistor with an undoped InAs NW channel, the drain current versus drain-source voltage characteristic curves under various negative gate-source voltages were successfully observed at room temperature.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vexler, M. I., E-mail: shulekin@mail.ioffe.ru; Grekhov, I. V.

The features of electron tunneling from or into the silicon valence band in a metal–insulator–semiconductor system with the HfO{sub 2}(ZrO{sub 2})/SiO{sub 2} double-layer insulator are theoretically analyzed for different modes. It is demonstrated that the valence-band current plays a less important role in structures with HfO{sub 2}(ZrO{sub 2})/SiO{sub 2} than in structures containing only silicon dioxide. In the case of a very wide-gap high-K oxide ZrO{sub 2}, nonmonotonic behavior related to tunneling through the upper barrier is predicted for the valence-band–metal current component. The use of an insulator stack can offer certain advantages for some devices, including diodes, bipolar tunnel-emittermore » transistors, and resonant-tunneling diodes, along with the traditional use of high-K insulators in a field-effect transistor.« less

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Crystallization behavior of amorphous indium-gallium-zinc-oxide films and its effects on thin-film transistor performance

NASA Astrophysics Data System (ADS)

Suko, Ayaka; Jia, JunJun; Nakamura, Shin-ichi; Kawashima, Emi; Utsuno, Futoshi; Yano, Koki; Shigesato, Yuzo

2016-03-01

Amorphous indium-gallium-zinc oxide (a-IGZO) films were deposited by DC magnetron sputtering and post-annealed in air at 300-1000 °C for 1 h to investigate the crystallization behavior in detail. X-ray diffraction, electron beam diffraction, and high-resolution electron microscopy revealed that the IGZO films showed an amorphous structure after post-annealing at 300 °C. At 600 °C, the films started to crystallize from the surface with c-axis preferred orientation. At 700-1000 °C, the films totally crystallized into polycrystalline structures, wherein the grains showed c-axis preferred orientation close to the surface and random orientation inside the films. The current-gate voltage (Id-Vg) characteristics of the IGZO thin-film transistor (TFT) showed that the threshold voltage (Vth) and subthreshold swing decreased markedly after the post-annealing at 300 °C. The TFT using the totally crystallized films also showed the decrease in Vth, whereas the field-effect mobility decreased considerably.

Lateral electrochemical etching of III-nitride materials for microfabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Han, Jung

Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Acoustic transistor: Amplification and switch of sound by sound

NASA Astrophysics Data System (ADS)

Liang, Bin; Kan, Wei-wei; Zou, Xin-ye; Yin, Lei-lei; Cheng, Jian-chun

2014-08-01

We designed an acoustic transistor to manipulate sound in a manner similar to the manipulation of electric current by its electrical counterpart. The acoustic transistor is a three-terminal device with the essential ability to use a small monochromatic acoustic signal to control a much larger output signal within a broad frequency range. The output and controlling signals have the same frequency, suggesting the possibility of cascading the structure to amplify an acoustic signal. Capable of amplifying and switching sound by sound, acoustic transistors have various potential applications and may open the way to the design of conceptual devices such as acoustic logic gates.

Effects of self-assembled monolayer structural order, surface homogeneity and surface energy on pentacene morphology and thin film transistor device performance.

PubMed

Hutchins, Daniel Orrin; Weidner, Tobias; Baio, Joe; Polishak, Brent; Acton, Orb; Cernetic, Nathan; Ma, Hong; Jen, Alex K-Y

2013-01-04

A systematic study of six phosphonic acid (PA) self-assembled monolayers (SAMs) with tailored molecular structures is performed to evaluate their effectiveness as dielectric modifying layers in organic field-effect transistors (OFETs) and determine the relationship between SAM structural order, surface homogeneity, and surface energy in dictating device performance. SAM structures and surface properties are examined by near edge X-ray absorption fine structure (NEXAFS) spectroscopy, contact angle goniometry, and atomic force microscopy (AFM). Top-contact pentacene OFET devices are fabricated on SAM modified Si with a thermally grown oxide layer as a dielectric. For less ordered methyl- and phenyl-terminated alkyl ~(CH 2 ) 12 PA SAMs of varying surface energies, pentacene OFETs show high charge carrier mobilities up to 4.1 cm 2 V -1 s -1 . It is hypothesized that for these SAMs, mitigation of molecular scale roughness and subsequent control of surface homogeneity allow for large pentacene grain growth leading to high performance pentacene OFET devices. PA SAMs that contain bulky terminal groups or are highly crystalline in nature do not allow for a homogenous surface at a molecular level and result in charge carrier mobilities of 1.3 cm 2 V -1 s -1 or less. For all molecules used in this study, no causal relationship between SAM surface energy and charge carrier mobility in pentacene FET devices is observed.

Effects of self-assembled monolayer structural order, surface homogeneity and surface energy on pentacene morphology and thin film transistor device performance

PubMed Central

Hutchins, Daniel Orrin; Weidner, Tobias; Baio, Joe; Polishak, Brent; Acton, Orb; Cernetic, Nathan; Ma, Hong; Jen, Alex K.-Y.

2013-01-01

A systematic study of six phosphonic acid (PA) self-assembled monolayers (SAMs) with tailored molecular structures is performed to evaluate their effectiveness as dielectric modifying layers in organic field-effect transistors (OFETs) and determine the relationship between SAM structural order, surface homogeneity, and surface energy in dictating device performance. SAM structures and surface properties are examined by near edge X-ray absorption fine structure (NEXAFS) spectroscopy, contact angle goniometry, and atomic force microscopy (AFM). Top-contact pentacene OFET devices are fabricated on SAM modified Si with a thermally grown oxide layer as a dielectric. For less ordered methyl- and phenyl-terminated alkyl ~(CH2)12 PA SAMs of varying surface energies, pentacene OFETs show high charge carrier mobilities up to 4.1 cm2 V−1 s−1. It is hypothesized that for these SAMs, mitigation of molecular scale roughness and subsequent control of surface homogeneity allow for large pentacene grain growth leading to high performance pentacene OFET devices. PA SAMs that contain bulky terminal groups or are highly crystalline in nature do not allow for a homogenous surface at a molecular level and result in charge carrier mobilities of 1.3 cm2 V−1 s−1 or less. For all molecules used in this study, no causal relationship between SAM surface energy and charge carrier mobility in pentacene FET devices is observed. PMID:24086795

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Enhancement of field effect mobility of poly(3-hexylthiophene) thin film transistors by soft-lithographical nanopatterning on the gate-dielectric surface

NASA Astrophysics Data System (ADS)

Park, Jeong-Ho; Kang, Seok-Ju; Park, Jeong-Woo; Lim, Bogyu; Kim, Dong-Yu

2007-11-01

The submicroscaled octadecyltrichlorosilane (OTS) line patterns on gate-dielectric surfaces were introduced into the fabrication of organic field effect transistors (OFETs). These spin-cast regioregular poly(3-hexylthiophene) films on soft-lithographically patterned SiO2 surfaces yielded a higher hole mobility (˜0.072cm2/Vs ) than those of unpatterned (˜0.015cm2/Vs) and untreated (˜5×10-3cm2/Vs) OFETs. The effect of mobility enhancement as a function of the patterned line pitch was investigated in structural and geometric characteristics. The resulting improved mobility is likely attributed to the formation of efficient π-π stacking as a result of guide-assisted, local self-organization-involved molecular interactions between the poly(3-hexylthiophene) polymer and the geometrical OTS patterns.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Development of a Planar Heterojunction Bipolar Transistor for Very High Speed Logic.

DTIC Science & Technology

1983-12-01

AD- R136 341 DEVELOPMENT OF A PLANAR HETEROJUNCTION BIPOLAR i/i TRANSISTOR FOR VERV HIGH S..(U) CALIFORNIA UNIV SANTA BARBARA DEPT OF ELECTRICAL AND...GaAs material systems . Emphasis has been placed on growth and char- acterization of the above heterojunctions by Holecular Beam Epitaxy and on the...GaAs material system is used to fabricate discrete single heterojunction bipolar transistor structures. Conventional mesa-etch tech- niques will be used

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

PubMed Central

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Direct observation of single-charge-detection capability of nanowire field-effect transistors.

PubMed

Salfi, J; Savelyev, I G; Blumin, M; Nair, S V; Ruda, H E

2010-10-01

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.

High mobility organic field-effect transistor based on water-soluble deoxyribonucleic acid via spray coating

NASA Astrophysics Data System (ADS)

Shi, Wei; Han, Shijiao; Huang, Wei; Yu, Junsheng

2015-01-01

High mobility organic field-effect transistors (OFETs) by inserting water-soluble deoxyribonucleic acid (DNA) buffer layer between electrodes and pentacene film through spray coating process were fabricated. Compared with the OFETs incorporated with DNA in the conventional organic solvents of ethanol and methanol: water mixture, the water-soluble DNA based OFET exhibited an over four folds enhancement of field-effect mobility from 0.035 to 0.153 cm2/Vs. By characterizing the surface morphology and the crystalline structure of pentacene active layer through atomic force microscope and X-ray diffraction, it was found that the adoption of water solvent in DNA solution, which played a key role in enhancing the field-effect mobility, was ascribed to both the elimination of the irreversible organic solvent-induced bulk-like phase transition of pentacene film and the diminution of a majority of charge trapping at interfaces in OFETs.

Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer

NASA Astrophysics Data System (ADS)

Xu, Wenya; Dou, Junyan; Zhao, Jianwen; Tan, Hongwei; Ye, Jun; Tange, Masayoshi; Gao, Wei; Xu, Weiwei; Zhang, Xiang; Guo, Wenrui; Ma, Changqi; Okazaki, Toshiya; Zhang, Kai; Cui, Zheng

2016-02-01

Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (+/-2 V) and subthreshold swing (SS) (122-161 mV dec-1), high effective mobility (up to 17.6-37.7 cm2 V-1 s-1) and high on/off ratio (104-107). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption.Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (+/-2 V) and subthreshold swing (SS) (122-161 mV dec-1), high effective mobility (up to 17.6-37.7 cm2 V-1 s-1) and high on/off ratio (104-107). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00015k

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

Study on copper phthalocyanine and perylene-based ambipolar organic light-emitting field-effect transistors produced using neutral beam deposition method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dae-Kyu; Oh, Jeong-Do; Shin, Eun-Sol

2014-04-28

The neutral cluster beam deposition (NCBD) method has been applied to the production and characterization of ambipolar, heterojunction-based organic light-emitting field-effect transistors (OLEFETs) with a top-contact, multi-digitated, long-channel geometry. Organic thin films of n-type N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide and p-type copper phthalocyanine were successively deposited on the hydroxyl-free polymethyl-methacrylate (PMMA)-coated SiO{sub 2} dielectrics using the NCBD method. Characterization of the morphological and structural properties of the organic active layers was performed using atomic force microscopy and X-ray diffraction. Various device parameters such as hole- and electron-carrier mobilities, threshold voltages, and electroluminescence (EL) were derived from the fits of the observed current-voltage andmore » current-voltage-light emission characteristics of OLEFETs. The OLEFETs demonstrated good field-effect characteristics, well-balanced ambipolarity, and substantial EL under ambient conditions. The device performance, which is strongly correlated with the surface morphology and the structural properties of the organic active layers, is discussed along with the operating conduction mechanism.« less

Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

NASA Astrophysics Data System (ADS)

Naderi, Ali

2016-01-01

A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

Effects of channel thickness on oxide thin film transistor with double-stacked channel layer

NASA Astrophysics Data System (ADS)

Lee, Kimoon; Kim, Yong-Hoon; Yoon, Sung-Min; Kim, Jiwan; Oh, Min Suk

2017-11-01

To improve the field effect mobility and control the threshold voltage ( V th ) of oxide thin film transistors (TFTs), we fabricated the oxide TFTs with double-stacked channel layers which consist of thick Zn-Sn-O (ZTO) and very thin In-Zn-O (IZO) layers. We investigated the effects of the thickness of thin conductive layer and the conductivity of thick layer on oxide TFTs with doublestacked channel layer. When we changed the thickness of thin conductive IZO channel layer, the resistivity values were changed. This resistivity of thin channel layer affected on the saturation field effect mobility and the off current of TFTs. In case of the thick ZTO channel layer which was deposited by sputtering in Ar: O2 = 10: 1, the device showed better performances than that which was deposited in Ar: O2 = 1: 1. Our TFTs showed high mobility ( μ FE ) of 40.7 cm2/Vs and V th of 4.3 V. We assumed that high mobility and the controlled V th were caused by thin conductive IZO layer and thick stable ZTO layer. Therefore, this double-stacked channel structure can be very promising way to improve the electrical characteristics of various oxide thin film transistors.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Significance of the gate voltage-dependent mobility in the electrical characterization of organic field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Jong Beom; Lee, Dong Ryeol

2018-04-01

We studied the effect of the addition of free hole- and electron-rich organic molecules to organic semiconductors (OSCs) in organic field effect transistors (OFETs) on the gate voltage-dependent mobility. The drain current versus gate voltage characteristics were quantitatively analyzed using an OFET mobility model of power law behavior based on hopping transport in an OSC. This analysis distinguished the threshold voltage shifts, depending on the materials and structures of the OFET device, and properly estimated the hopping transport of the charge carriers induced by the gate bias within the OSC from the power law exponent parameter. The addition of pentacene or C60 molecules to a one-monolayer pentacene-based OFET shifted the threshold voltages negatively or positively, respectively, due to the structural changes that occurred in the OFET device. On the other hand, the power law parameters revealed that the addition of charge carriers of the same or opposite polarity enhanced or hindered hopping transport, respectively. This study revealed the need for a quantitative analysis of the gate voltage-dependent mobility while distinguishing this effect from the threshold voltage effect in order to understand OSC hopping transport in OFETs.

Doping Polymer Semiconductors by Organic Salts: Toward High-Performance Solution-Processed Organic Field-Effect Transistors.

PubMed

Hu, Yuanyuan; Rengert, Zachary D; McDowell, Caitlin; Ford, Michael J; Wang, Ming; Karki, Akchheta; Lill, Alexander T; Bazan, Guillermo C; Nguyen, Thuc-Quyen

2018-04-24

Solution-processed organic field-effect transistors (OFETs) were fabricated with the addition of an organic salt, trityl tetrakis(pentafluorophenyl)borate (TrTPFB), into thin films of donor-acceptor copolymer semiconductors. The performance of OFETs is significantly enhanced after the organic salt is incorporated. TrTPFB is confirmed to p-dope the organic semiconductors used in this study, and the doping efficiency as well as doping physics was investigated. In addition, systematic electrical and structural characterizations reveal how the doping enhances the performance of OFETs. Furthermore, it is shown that this organic salt doping method is feasible for both p- and n-doping by using different organic salts and, thus, can be utilized to achieve high-performance OFETs and organic complementary circuits.

The effect of nitrous oxide plasma treatment on the bias temperature stress of metal oxide thin film transistors with high mobility

NASA Astrophysics Data System (ADS)

Tseng, Wei-Hao; Fang, Shao-Wei; Lu, Chia-Yang; Chuang, Hung-Yang; Chang, Fan-Wei; Lin, Guan-Yu; Chen, Tsu-Wei; Ma, Kang-Hung; Chen, Hong-Syu; Chen, Teng-Ke; Chen, Yu-Hung; Lee, Jen-Yu; Shih, Tsung-Hsiang; Ting, Hung-Che; Chen, Chia-Yu; Lin, Yu-Hsin; Hong, Hong-Jye

2015-01-01

In this work, the effects of nitrous oxide plasma treatment on the negative bias temperature stress of indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film transistors (TFTs) were reported. ITZO TFTs were more suitable for the back channel etched-type device structure because they could withstand both Al- and Cu-acid damage. The initial threshold voltage range could be controlled to within 1 V. The root cause of poor negative bias temperature stress for ITZO was likely due to a higher mobility (∼3.3 times) and more carbon related contamination bonds (∼5.9 times) relative to IGZO. Finally, 65″ active-matrix organic light-emitting diode televisions using the ITZO and IGZO TFTs were fabricated.

A computational study of a novel graphene nanoribbon field effect transistor

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza

2017-04-01

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic (I -N--I) configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

DOEpatents

Turner, Steven Richard

2006-12-26

A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

Novel gallium nitride based microwave noise and power heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Chumbes, Eduardo Martin

With the pioneering efforts of Isamu Akasaki of Meiji University and Shuji Nakamura of Nichia Chemical Industries in the late 1980's and early 1990's, the first long-lived candela-class blue and ultraviolet light emitting devices have finally come to fruition. Their success in conquering this Holy Grail in opto-electronics is due to their development of a new technology based remarkably on a class of semiconductor materials that has been practically ignored and overlooked by almost everyone for the past twenty years---the nitrides of Al, Ga and In and their alloys. The breakthroughs made from this new technology in the last decade of the 20th century has revolutionized and revitalized worldwide research and development efforts to the point where it is feasible for other important technologies such as high-density information storage, high-resolution full-color displays and efficient white light lamps and UV sensors to come much closer to realization. Equally important is the potential that this new technology can bring toward the development of efficient ultra-high power and high-temperature electronics that will revolutionize the aerospace and high-speed communication industries. Specifically, the large bandgap and strong polar properties of the group III-nitrides has at present allowed for the realization of simple doped and remarkably undoped AlGaN/GaN transistor structures on sapphire and SiC substrates with two-dimensional electron gas sheet densities significantly greater than that of conventional transistor structures based on GaAs and InP. This dissertation will look specifically at extending undoped AlGaN/GaN heterostructure field-effect transistors or HFETs towards more advanced system applications involving the integration of these devices onto a more advanced Si technology and looking at the feasibility of this integration. It will also address important issues similar devices on semi-insulating SiC substrates have in robust microwave low noise and linear amplification. Finally, it will look at incorporating high-temperature silicon nitride passivation as a key ingredient to developing a unique class of devices: metal-insulator-semiconductor field effect transistors or MISFETs as a means for providing efficient high power amplification without compromising performance associated with surface- and process-related dispersion. This dissertation will finally close with a brief outlook on the future outlook of these technologies.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

NASA Astrophysics Data System (ADS)

Diebold, Alain C.; Antonelli, Andy; Keller, Nick

2018-05-01

The use of optical scattering to measure feature shape and dimensions, scatterometry, is now routine during semiconductor manufacturing. Scatterometry iteratively improves an optical model structure using simulations that are compared to experimental data from an ellipsometer. These simulations are done using the rigorous coupled wave analysis for solving Maxwell's equations. In this article, we describe the Mueller matrix spectroscopic ellipsometry based scatterometry. Next, the rigorous coupled wave analysis for Maxwell's equations is presented. Following this, several example measurements are described as they apply to specific process steps in the fabrication of gate-all-around (GAA) transistor structures. First, simulations of measurement sensitivity for the inner spacer etch back step of horizontal GAA transistor processing are described. Next, the simulated metrology sensitivity for sacrificial (dummy) amorphous silicon etch back step of vertical GAA transistor processing is discussed. Finally, we present the application of plasmonically active test structures for improving the sensitivity of the measurement of metal linewidths.

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

PubMed Central

Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

2012-01-01

Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

Rational Design of ZnO:H/ZnO Bilayer Structure for High-Performance Thin-Film Transistors.

PubMed

Abliz, Ablat; Huang, Chun-Wei; Wang, Jingli; Xu, Lei; Liao, Lei; Xiao, Xiangheng; Wu, Wen-Wei; Fan, Zhiyong; Jiang, Changzhong; Li, Jinchai; Guo, Shishang; Liu, Chuansheng; Guo, Tailiang

2016-03-01

The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (∼3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V(-1) s(-1), a high on/off current ratio of 10(8) and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

PubMed

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Doping Nitrogen in InGaZnO Thin Film Transistor with Double Layer Channel Structure.

PubMed

Chang, Sheng-Po; Shan, Deng

2018-04-01

This paper presents the electrical characteristics of doping nitrogen in an amorphous InGaZnO thin film transistor. The IGZO:N film, which acted as a channel layer, was deposited using RF sputtering with a nitrogen and argon gas mixture at room temperature. The optimized parameters of the IGZO:N/IGZO TFT are as follows: threshold voltage is 0.5 V, field effect mobility is 14.34 cm2V-1S-1. The on/off current ratio is 106 and subthreshold swing is 1.48 V/decade. The positive gate bias stress stability of InGaZnO doping with nitrogen shows improvement compared to doping with oxygen.

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Vacuum relaxation and annealing-induced enhancement of mobility of regioregular poly (3-hexylthiophene) field-effect transistors

NASA Astrophysics Data System (ADS)

Tian, Xue-Yan; Xu, Zheng; Zhao, Su-Ling; Zhang, Fu-Jun; Xu, Xu-Rong; Yuan, Guang-Cai; Li, Jing; Sun, Qin-Jun; Wang, Ying

2009-11-01

In order to enhance the performance of regioregular poly(3-hexylthiophene) (RR-P3HT) field-effect transistors (FETs), RR-P3HT FETs are prepared by the spin-coating method followed by vacuum placement and annealing. This paper reports that the crystal structure, the molecule interconnection, the surface morphology, and the charge carrier mobility of RR-P3HT films are affected by vacuum relaxation and annealing. The results reveal that the field-effect mobility of RR-P3HT FETs can reach 4.17 × 10-2 m2/(V · s) by vacuum relaxation at room temperature due to an enhanced local self-organization. Furthermore, it reports that an appropriate annealing temperature can facilitate the crystal structure, the orientation and the interconnection of polymer molecules. These results show that the field-effect mobility of device annealed at 150 °C for 10 minutes in vacuum at atmosphere and followed by placement for 20 hours in vacuum at room temperature is enhanced dramatically to 9.00 × 10-2 cm2/(V · s).

The interface between ferroelectric and 2D material for a Ferroelectric Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Park, Nahee; Kang, Haeyong; Lee, Sang-Goo; Lee, Young Hee; Suh, Dongseok

We have studied electrical property of ferroelectric field-effect transistor which consists of graphene on hexagonal Boron-Nitride (h-BN) gated by a ferroelectric, PMN-PT (i.e. (1-x)Pb(Mg1/3Nb2/3) O3-xPbTiO3) single-crystal substrate. The PMN-PT was expected to have an effect on polarization field into the graphene channel and to induce a giant amount of surface charge. The hexagonal Boron-Nitride (h-BN) flake was directly exfoliated on the PMN-PT substrate for preventing graphene from directly contacting on the PMN-PT substrate. It can make us to observe the effect of the interface between ferroelectric and 2D material on the device operation. Monolayer graphene as 2D channel material, which was confirmed by Raman spectroscopy, was transferred on top of the hexagonal Boron-Nitride (h-BN) by using the conventional dry-transfer method. Here, we can demonstrate that the structure of graphene/hexagonal-BN/ferroelectric field-effect transistor makes us to clearly understand the device operation as well as the interface between ferroelectric and 2D materials by inserting h-BN between them. The phenomena such as anti-hysteresis, current saturation behavior, and hump-like increase of channel current, will be discussed by in terms of ferroelectric switching, polarization-assisted charge trapping.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Numerical simulation of offset-drain amorphous oxide-based thin-film transistors

NASA Astrophysics Data System (ADS)

Jeong, Jaewook

2016-11-01

In this study, we analyzed the electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with an offset-drain structure by technology computer aided design (TCAD) simulation. When operating in a linear region, an enhancement-type TFT shows poor field-effect mobility because most conduction electrons are trapped in acceptor-like defects in an offset region when the offset length (L off) exceeds 0.5 µm, whereas a depletion-type TFT shows superior field-effect mobility owing to the high free electron density in the offset region compared with the trapped electron density. When operating in the saturation region, both types of TFTs show good field-effect mobility comparable to that of a reference TFT with a large gate overlap. The underlying physics of the depletion and enhancement types of offset-drain TFTs are systematically analyzed.

Directionally Aligned Amorphous Polymer Chains via Electrohydrodynamic-Jet Printing: Analysis of Morphology and Polymer Field-Effect Transistor Characteristics.

PubMed

Kim, Yebyeol; Bae, Jaehyun; Song, Hyun Woo; An, Tae Kyu; Kim, Se Hyun; Kim, Yun-Hi; Park, Chan Eon

2017-11-15

Electrohydrodynamic-jet (EHD-jet) printing provides an opportunity to directly assembled amorphous polymer chains in the printed pattern. Herein, an EHD-jet printed amorphous polymer was employed as the active layer for fabrication of organic field-effect transistors (OFETs). Under optimized conditions, the field-effect mobility (μ FET ) of the EHD-jet printed OFETs was 5 times higher than the highest μ FET observed in the spin-coated OFETs, and this improvement was achieved without the use of complex surface templating or additional pre- or post-deposition processing. As the chain alignment can be affected by the surface energy of the dielectric layer in EHD-jet printed OFETs, dielectric layers with varying wettability were examined. Near-edge X-ray absorption fine structure measurements were performed to compare the amorphous chain alignment in OFET active layers prepared by EHD-jet printing and spin coating.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Effect of Pentacene-dielectric Affinity on Pentacene Thin Film Growth Morphology in Organic Field-effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

S Kim; M Jang; H Yang

2011-12-31

Organic field-effect transistors (OFETs) are fabricated by depositing a thin film of semiconductor on the functionalized surface of a SiO{sub 2} dielectric. The chemical and morphological structures of the interface between the semiconductor and the functionalized dielectric are critical for OFET performance. We have characterized the effect of the affinity between semiconductor and functionalized dielectric on the properties of the semiconductor-dielectric interface. The crystalline microstructure/nanostructure of the pentacene semiconductor layers, grown on a dielectric substrate that had been functionalized with either poly(4-vinyl pyridine) or polystyrene (to control hydrophobicity), and grown under a series of substrate temperatures and deposition rates, weremore » characterized by X-ray diffraction, photoemission spectroscopy, and atomic force microscopy. By comparing the morphological features of the semiconductor thin films with the device characteristics (field-effect mobility, threshold voltage, and hysteresis) of the OFET devices, the effect of affinity-driven properties on charge modulation, charge trapping, and charge carrier transport could be described.« less

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

NASA Astrophysics Data System (ADS)

Kwon, Jang Yeon; Kyeong Jeong, Jae

2015-02-01

This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

Semiconductor structures having electrically insulating and conducting portions formed from an AlSb-alloy layer

DOEpatents

Spahn, O.B.; Lear, K.L.

1998-03-10

The semiconductor structure comprises a plurality of semiconductor layers formed on a substrate including at least one layer of a III-V compound semiconductor alloy comprising aluminum (Al) and antimony (Sb), with at least a part of the AlSb-alloy layer being chemically converted by an oxidation process to form superposed electrically insulating and electrically conducting portions. The electrically insulating portion formed from the AlSb-alloy layer comprises an oxide of aluminum (e.g., Al{sub 2}O{sub 3}), while the electrically conducting portion comprises Sb. A lateral oxidation process allows formation of the superposed insulating and conducting portions below monocrystalline semiconductor layers for forming many different types of semiconductor structures having particular utility for optoelectronic devices such as light-emitting diodes, edge-emitting lasers, vertical-cavity surface-emitting lasers, photodetectors and optical modulators (waveguide and surface normal), and for electronic devices such as heterojunction bipolar transistors, field-effect transistors and quantum-effect devices. The invention is expected to be particularly useful for forming light-emitting devices for use in the 1.3--1.6 {mu}m wavelength range, with the AlSb-alloy layer acting to define an active region of the device and to effectively channel an electrical current therein for efficient light generation. 10 figs.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Comprehensive review on the development of high mobility in oxide thin film transistors

NASA Astrophysics Data System (ADS)

Choi, Jun Young; Lee, Sang Yeol

2017-11-01

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility ( μ FE ), subthreshold swing (S.S) and threshold voltage ( V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Conceptual techniques for reducing parasitic current gain of lateral pnp transistors

NASA Technical Reports Server (NTRS)

Gallagher, R. C.; Scott, J. M.

1969-01-01

Two techniques have been conceptually proposed as possible means of reducing parasitic beta in lateral p-n-p transistors. One method uses a degenerate substrate and high concentration P /plus/ guard-ring diffusion, another places the base contact at the center of an annular ring structure.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Solution processable semiconductor thin films: Correlation between morphological, structural, optical and charge transport properties

NASA Astrophysics Data System (ADS)

Isik, Dilek

This Ph.D. thesis is a result of multidisciplinary research bringing together fundamental concepts in thin film engineering, materials science, materials processing and characterization, electrochemistry, microfabrication, and device physics. Experiments were conducted by tackling scientific problems in the field of thin films and interfaces, with the aim to correlate the morphology, crystalline structure, electronic structure of thin films with the functional properties of the films and the performances of electronic devices based thereon. Furthermore, novel strategies based on interfacial phenomena at electrolyte/thin film interfaces were explored and exploited to control the electrical conductivity of the thin films. Three main chemical systems were the object of the studies performed during this Ph.D., two types of organic semiconductors (azomethine-based oligomers and polymers and soluble pentacene derivatives) and one metal oxide semiconductor (tungsten trioxide, WO3). To explore the morphological properties of the thin films, atomic force microscopy was employed. The morphological properties were further investigated by hyperspectral fluorescence microscopy and tentatively correlated to the charge transport properties of the films. X-ray diffraction (Grazing incidence XRD, GIXRD) was used to investigate the crystallinity of the film and the effect of the heat treatment on such crystallinity, as well as to understand the molecular arrangement of the organic molecules in the thin film. The charge transport properties of the films were evaluated in thin film transistor configuration. For electrolyte gated thin film transistors, time dependent transient measurements were conducted, in parallel to more conventional transistor characterizations, to explore the specific effects played on the gating by the anion and cation constituting the electrolyte. The capacitances of the electrical double layers at the electrolyte/WO3 interface were obtained from electrochemical impedance spectroscopy. In the context of ARTICLE 1, thin film transistors based on soluble pentacene derivatives (prepared by the research group directed by Professor J. Anthony, at the University of Kentucky) were fabricated and characterized. GIXRD results performed on the thin films suggested a molecular arrangement favorable to charge transport in the source-drain direction, with the pi-pi stacking direction perpendicular to the channel. In ARTICLE 1, HMDS-treated SiO 2 substrates were used, to improve the surface coverage and to limit charge trapping at the dielectric surface. AFM showed good film coverage. The transistors showed ambipolar characteristics, attributed to the good matching between Au electrode work function and highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) of the pentacene derivative. The work reported in ARTICLE 2 deals with pi-conjugated thiopheno-azomethines (both in oligomer and polymer form) and oligothiophene analogues. In the former case, couplings in the polymer are based on azomethine (-N=C-) moieties whereas in the latter case they are based on more conventional protocols (-C=C-). The effect of the coupling protocols on the corresponding thin film transistors behavior was studied. The key conclusion of this study was that thiopheno-azomethines thin films can be effectively incorporated into organic transistors: thin films of oligothiopheno-azomethines and the oligothiophenes exhibit p-type behavior whereas thin films of polythiopheno-azomethine exhibit an ambipolar behavior. The hole mobility of the heat-treated thin films of oligothiopheno-azomethines was three orders of magnitude higher compared to its oligothiophene analogue. AFM, coupled with hyperspectral fluorescence imaging, were used to investigate the micro- and nano-scale surface coverage. For the oligothiopheno-azomethine we were able to quantitatively deduce the surface coverage. To contribute to the exploration of innovative strategies for low power consuming solution based electronics and capitalizing on the expertise of the group in the synthesis of solution deposited WO3 films the electrolyte gating approach was explored in ARTICLE 3. Ionic liquids, that are molten salts at room temperature, were employed as the electrolyte. Ionic liquids are attractive for their low volatility, non-flammability, ionic conductivity and thermal and electrochemical stability. Thin films of WO3 were deposited onto pre-patterned ITO substrates (source-drain interelectrode distance, 1 mm) prepared by wet chemical etching. SEM and AFM showed an interconnected film nanostructure. Electrolyte gated WO3 thin film transistors making use of 1-butyl-3-methyl imidazolium bis(trifluoromethylsulfonyl)imide ([BMIM][TFSI]), 1-butyl-3-methyl imidazolium hexafluoro phosphate ([BMIM][PF6]), and 1-ethyl-3-methyl imidazolium bis(trifluoromethylsulfonyl)imide ([EMIM][TFSI]) showed an n-type transistor behavior. The possibility to obtain WO3 electrolyte gated transistors represents an opportunity to fabricate electronic devices working at relatively low operating voltages (about 1 V) by using simple fabrication techniques.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Back-gated Nb-doped MoS2 junctionless field-effect-transistors

NASA Astrophysics Data System (ADS)

Mirabelli, Gioele; Schmidt, Michael; Sheehan, Brendan; Cherkaoui, Karim; Monaghan, Scott; Povey, Ian; McCarthy, Melissa; Bell, Alan P.; Nagle, Roger; Crupi, Felice; Hurley, Paul K.; Duffy, Ray

2016-02-01

Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb). The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm) deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm-3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM) structure, showing a promising contact resistivity of 1.05 × 10-7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

Nanoscale-Barrier Formation Induced by Low-Dose Electron-Beam Exposure in Ultrathin MoS2 Transistors.

PubMed

Matsunaga, Masahiro; Higuchi, Ayaka; He, Guanchen; Yamada, Tetsushi; Krüger, Peter; Ochiai, Yuichi; Gong, Yongji; Vajtai, Robert; Ajayan, Pulickel M; Bird, Jonathan P; Aoki, Nobuyuki

2016-10-05

Utilizing an innovative combination of scanning-probe and spectroscopic techniques, supported by first-principles calculations, we demonstrate how electron-beam exposure of field-effect transistors, implemented from ultrathin molybdenum disulfide (MoS 2 ), may cause nanoscale structural modifications that in turn significantly modify the electrical operation of these devices. Quite surprisingly, these modifications are induced by even the relatively low electron doses used in conventional electron-beam lithography, which are found to induce compressive strain in the atomically thin MoS 2 . Likely arising from sulfur-vacancy formation in the exposed regions, the strain gives rise to a local widening of the MoS 2 bandgap, an idea that is supported both by our experiment and by the results of first-principles calculations. A nanoscale potential barrier develops at the boundary between exposed and unexposed regions and may cause extrinsic variations in the resulting electrical characteristics exhibited by the transistor. The widespread use of electron-beam lithography in nanofabrication implies that the presence of such strain must be carefully considered when seeking to harness the potential of atomically thin transistors. At the same time, this work also promises the possibility of exploiting the strain as a means to achieve "bandstructure engineering" in such devices.

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

NASA Astrophysics Data System (ADS)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

A numerical study of the nanoribbon field-effect transistors under the ballistic and dissipative transport

NASA Astrophysics Data System (ADS)

Ghoreishi, Seyed Saleh; Yousefi, Reza; Saghafi, Kamyar; Aderang, Habib

2017-08-01

In this article, a detailed performance comparison is made between ballistic and dissipative quantum transport of metal oxide semicondutor-like graphene nanoribbon field-effect transistor, in ON and OFF-state conditions. By the self-consistent mode-space non-equilibrium Green's function approach, inter- and intraband scattering is accounted and the role of acoustic and optical phonon scattering on the performance of the devices is evaluated. We found that in this structure the dominant mechanism of scattering changes according to the ranges of voltage bias. Under large biasing conditions, the influence of optical phonon scattering becomes important. Also, the ambipolar and OFF-current are impressed by the phonon-assisted band-to-band tunneling and increased considerably compared to the ballistic conditions, although sub-threshold swing degrades due to optical phonon scattering.

Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Liu, Yan; Lin, Zhaojun; Cui, Peng; Zhao, Jingtao; Fu, Chen; Yang, Ming; Lv, Yuanjie

2017-08-01

Using a suitable dual-gate structure, the source-to-drain resistance (RSD) of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET) with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF) scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

Proton irradiation of MgO- or Sc 2O 3 passivated AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Luo, B.; Ren, F.; Allums, K. K.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Dwivedi, R.; Fogarty, T. N.; Wilkins, R.; Fitch, R. C.; Gillespie, J. K.; Jenkins, T. J.; Dettmer, R.; Sewell, J.; Via, G. D.; Crespo, A.; Baca, A. G.; Shul, R. J.

2003-06-01

AlGaN/GaN high electron mobility transistors with either MgO or Sc 2O 3 surface passivation were irradiated with 40 MeV protons at a dose of 5×10 9 cm -2. While both forward and reverse bias current were decreased in the devices as a result of decreases in channel doping and introduction of generation-recombination centers, there was no significant change observed in gate lag measurements. By sharp contrast, unpassivated devices showed significant decreases in drain current under pulsed conditions for the same proton dose. These results show the effectiveness of the oxide passivation in mitigating the effects of surface states present in the as-grown structures and also of surface traps created by the proton irradiation.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

N-Heterocyclic-Carbene-Treated Gold Surfaces in Pentacene Organic Field-Effect Transistors: Improved Stability and Contact at the Interface.

PubMed

Lv, Aifeng; Freitag, Matthias; Chepiga, Kathryn M; Schäfer, Andreas H; Glorius, Frank; Chi, Lifeng

2018-04-16

N-Heterocyclic carbenes (NHCs), which react with the surface of Au electrodes, have been successfully applied in pentacene transistors. With the application of NHCs, the charge-carrier mobility of pentacene transistors increased by five times, while the contact resistance at the pentacene-Au interface was reduced by 85 %. Even after annealing the NHC-Au electrodes at 200 °C for 2 h before pentacene deposition, the charge-carrier mobility of the pentacene transistors did not decrease. The distinguished performance makes NHCs as excellent alternatives to thiols as metal modifiers for the application in organic field-effect transistors (OFETs). © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

High Performance Vertical Organic Field Effect Transistors

DTIC Science & Technology

2010-05-01

systems. In pentacene /C60 bilayer system, [4] we showed that both the disordered structure of C60 and the charge trapping effect at the C60...much less significant than that by charge trapping at the interface. We also demonstrated that blending CdTe nanoparticles into a polymer–fullerene...for space applications b. We studied the photomultiplication effect in both evaporated ( pentacene /C60 bilayer) and bulk- heterojunction donor/acceptor

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

NASA Technical Reports Server (NTRS)

MacLeod, Todd, C.; Ho, Fat Duen

2006-01-01

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Application of the Johnson criteria to graphene transistors

NASA Astrophysics Data System (ADS)

Kelly, M. J.

2013-12-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Electron delocalization and charge mobility as a function of reduction in a metal-organic framework.

PubMed

Aubrey, Michael L; Wiers, Brian M; Andrews, Sean C; Sakurai, Tsuneaki; Reyes-Lillo, Sebastian E; Hamed, Samia M; Yu, Chung-Jui; Darago, Lucy E; Mason, Jarad A; Baeg, Jin-Ook; Grandjean, Fernande; Long, Gary J; Seki, Shu; Neaton, Jeffrey B; Yang, Peidong; Long, Jeffrey R

2018-06-04

Conductive metal-organic frameworks are an emerging class of three-dimensional architectures with degrees of modularity, synthetic flexibility and structural predictability that are unprecedented in other porous materials. However, engendering long-range charge delocalization and establishing synthetic strategies that are broadly applicable to the diverse range of structures encountered for this class of materials remain challenging. Here, we report the synthesis of K x Fe 2 (BDP) 3 (0 ≤ x ≤ 2; BDP 2-  = 1,4-benzenedipyrazolate), which exhibits full charge delocalization within the parent framework and charge mobilities comparable to technologically relevant polymers and ceramics. Through a battery of spectroscopic methods, computational techniques and single-microcrystal field-effect transistor measurements, we demonstrate that fractional reduction of Fe 2 (BDP) 3 results in a metal-organic framework that displays a nearly 10,000-fold enhancement in conductivity along a single crystallographic axis. The attainment of such properties in a K x Fe 2 (BDP) 3 field-effect transistor represents the realization of a general synthetic strategy for the creation of new porous conductor-based devices.

S,N-Heteroacene-Based Copolymers for Highly Efficient Organic Field Effect Transistors and Organic Solar Cells: Critical Impact of Aromatic Subunits in the Ladder π-System.

PubMed

Chung, Chin-Lung; Chen, Hsieh-Chih; Yang, Yun-Siou; Tung, Wei-Yao; Chen, Jian-Wei; Chen, Wen-Chang; Wu, Chun-Guey; Wong, Ken-Tsung

2018-02-21

Three novel donor-acceptor alternating polymers containing ladder-type pentacyclic heteroacenes (PBo, PBi, and PT) are synthesized, characterized, and further applied to organic field effect transistors (OFETs) and polymer solar cells. Significant aspects of quinoidal characters, electrochemical properties, optical absorption, frontier orbitals, backbone coplanarity, molecular orientation, charge carrier mobilities, morphology discrepancies, and the corresponding device performances are notably different with various heteroarenes. PT exhibits a stronger quinoidal mesomeric structure, linear and coplanar conformation, smooth surface morphology, and better bimodal crystalline structures, which is beneficial to extend the π-conjugation and promotes charge transport via 3-D transport pathways and in consequence improves overall device performances. Organic photovoltaics based on the PT polymer achieve a power conversion efficiency of 6.04% along with a high short-circuit current density (J SC ) of 14.68 mA cm -2 , and a high hole mobility of 0.1 cm 2 V -1 s -1 is fulfilled in an OFET, which is superior to those of its counterparts, PBi and PBo.

Solution-processed gadolinium doped indium-oxide thin-film transistors with oxide passivation

NASA Astrophysics Data System (ADS)

Lee, Seung-Hun; Kim, Taehun; Lee, Jihun; Avis, Christophe; Jang, Jin

2017-03-01

We studied the effect of Gd doping on the structural properties of solution processed, crystalline In2O3 for thin-film transistor (TFT) application. With increasing Gd in In2O3 up to 20%, the material structure changes into amorphous phase, and the oxygen vacancy concentration decreases from 15.4 to 8.4%, and M-OH bonds from 33.5 to 23.7%. The field-effect mobility for the Gd doped In2O3 TFTs decreases and threshold voltage shifts to the positive voltage with increasing Gd concentration. In addition, the stability of the solution processed TFTs can also be improved by increasing Gd concentration. As a result, the optimum Gd concentration is found to be ˜5% in In2O3 and the 5% Gd doped In2O3 TFTs with the Y2O3 passivation layer exhibit the linear mobility of 9.74 cm2/V s, the threshold voltage of -0.27 V, the subthreshold swing of 79 mV/dec., and excellent bias stability.

A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2017-08-01

This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson's equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

PubMed

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Effect of temperature on the characteristics of silicon nanowire transistor.

PubMed

Hashim, Yasir; Sidek, Othman

2012-10-01

This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a transistor. The findings reveal the negative effect of higher working temperature on the use of SiNWTs in electronic circuits, such as digital circuits and amplifiers circuits, because of the lower I(ON)/I(OFF) ratio, higher DIBL, and higher SS at higher temperature. Moreover, the ON state is the optimum condition for using a transistor as a temperature nano-sensor.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Carrier doping into a superconducting BaPb0.7Bi0.3O3‑δ epitaxial film using an electric double-layer transistor structure

NASA Astrophysics Data System (ADS)

Komori, S.; Kakeya, I.

2018-06-01

Doping evolution of the unconventional superconducting properties in BaBiO3-based compounds has yet to be clarified in detail due to the significant change of the oxygen concentration accompanied by the chemical substitution. We suggest that the carrier concentration of an unconventional superconductor, BaPb0.7Bi0.3O3‑δ , is controllable without inducing chemical or structural changes using an electric double-layer transistor structure. The critical temperature is found to decrease systematically with increasing carrier concentration.

Influence of polymer dielectrics on C60-based field-effect transistors

NASA Astrophysics Data System (ADS)

Zhou, Jianlin; Zhang, Fujia; Lan, Lifeng; Wen, Shangsheng; Peng, Junbiao

2007-12-01

Fullerene C60 organic field-effect transistors (OFETs) have been fabricated based on two different polymer dielectric materials, poly(methylmethacrylate) (PMMA) and cross-linkable poly(4-vinylphenol). The large grain size of C60 film and small number of traps at the interface of PMMA /C60 were obtained with high electron mobility of 0.66cm2/Vs in the PMMA transistor. The result suggests that the C60 semiconductor cooperating with polymer dielectric is a promising application in the fabrication of n-type organic transistors because of low threshold voltage and high electron mobility.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Graphene-based flexible and stretchable thin film transistors.

PubMed

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

AlGaSb Buffer Layers for Sb-Based Transistors

DTIC Science & Technology

2010-01-01

transistor ( HEMT ), molecular beam epitaxy (MBE), field-effect transistor (FET), buffer layer INTRODUCTION High-electron-mobility transistors ( HEMTs ) with InAs...monolayers/s. The use of thinner buffer layers reduces molecular beam epitaxial growth time and source consumption. The buffer layers also exhibit...source. In addition, some of the flux from an Sb cell in a molecular beam epitaxy (MBE) system will deposit near the mouth of the cell, eventually

High mobility organic field-effect transistor based on water-soluble deoxyribonucleic acid via spray coating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Wei; Han, Shijiao; Huang, Wei

High mobility organic field-effect transistors (OFETs) by inserting water-soluble deoxyribonucleic acid (DNA) buffer layer between electrodes and pentacene film through spray coating process were fabricated. Compared with the OFETs incorporated with DNA in the conventional organic solvents of ethanol and methanol: water mixture, the water-soluble DNA based OFET exhibited an over four folds enhancement of field-effect mobility from 0.035 to 0.153 cm{sup 2}/Vs. By characterizing the surface morphology and the crystalline structure of pentacene active layer through atomic force microscope and X-ray diffraction, it was found that the adoption of water solvent in DNA solution, which played a key role inmore » enhancing the field-effect mobility, was ascribed to both the elimination of the irreversible organic solvent-induced bulk-like phase transition of pentacene film and the diminution of a majority of charge trapping at interfaces in OFETs.« less

Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts

NASA Astrophysics Data System (ADS)

Cho, Sang-Hyeok; Cho, Kwanghee; Park, No-Won; Park, Soonyong; Koh, Jung-Hyuk; Lee, Sang-Kwon

2017-05-01

We report p-type tin monoselenide (SnSe) single crystals, grown in double-sealed quartz ampoules using a modified Bridgman technique at 920 °C. X-ray powder diffraction (XRD) and energy dispersive X-ray spectroscopy (EDX) measurements clearly confirm that the grown SnSe consists of single-crystal SnSe. Electrical transport of multi-layer SnSe nanoflakes, which were prepared by exfoliation from bulk single crystals, was conducted using back-gated field-effect transistor (FET) structures with Au and Ti contacts on SiO2/Si substrates, revealing that multi-layer SnSe nanoflakes exhibit p-type semiconductor characteristics owing to the Sn vacancies on the surfaces of SnSe nanoflakes. In addition, a strong carrier screening effect was observed in 70-90-nm-thick SnSe nanoflake FETs. Furthermore, the effect of the metal contacts to multi-layer SnSe nanoflake-based FETs is also discussed with two different metals, such as Ti/Au and Au contacts.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Piezoelectric potential gated field-effect transistor based on a free-standing ZnO wire.

PubMed

Fei, Peng; Yeh, Ping-Hung; Zhou, Jun; Xu, Sheng; Gao, Yifan; Song, Jinhui; Gu, Yudong; Huang, Yanyi; Wang, Zhong Lin

2009-10-01

We report an external force triggered field-effect transistor based on a free-standing piezoelectric fine wire (PFW). The device consists of an Ag source electrode and an Au drain electrode at two ends of a ZnO PFW, which were separated by an insulating polydimethylsiloxane (PDMS) thin layer. The working principle of the sensor is proposed based on the piezoelectric potential gating effect. Once subjected to a mechanical impact, the bent ZnO PFW cantilever creates a piezoelectric potential distribution across it width at its root and simultaneously produces a local reverse depletion layer with much higher donor concentration than normal, which can dramatically change the current flowing from the source electrode to drain electrode when the device is under a fixed voltage bias. Due to the free-standing structure of the sensor device, it has a prompt response time less than 20 ms and quite high and stable sensitivity of 2%/microN. The effect from contact resistance has been ruled out.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization

NASA Astrophysics Data System (ADS)

Tsai, Chun-Chien; Lee, Yao-Jen; Chiang, Ko-Yu; Wang, Jyh-Liang; Lee, I.-Che; Chen, Hsu-Hsin; Wei, Kai-Fang; Chang, Ting-Kuo; Chen, Bo-Ting; Cheng, Huang-Chung

2007-11-01

In this paper, location-controlled silicon crystal grains are fabricated by the excimer laser crystallization method which employs amorphous silicon spacer structure and prepatterned thin films. The amorphous silicon spacer in nanometer-sized width formed using spacer technology is served as seed crystal to artificially control superlateral growth phenomenon during excimer laser irradiation. An array of 1.8-μm-sized disklike silicon grains is formed, and the n-channel thin-film transistors whose channels located inside the artificially-controlled crystal grains exhibit higher performance of field-effect-mobility reaching 308cm2/Vs as compared with the conventional ones. This position-manipulated silicon grains are essential to high-performance and good uniformity devices.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Performance improvement of organic thin film transistors by using active layer with sandwich structure

NASA Astrophysics Data System (ADS)

Ni, Yao; Zhou, Jianlin; Kuang, Peng; Lin, Hui; Gan, Ping; Hu, Shengdong; Lin, Zhi

2017-08-01

We report organic thin film transistors (OTFTs) with pentacene/fluorinated copper phthalo-cyanine (F16CuPc)/pentacene (PFP) sandwich configuration as active layers. The sandwich devices not only show hole mobility enhancement but also present a well control about threshold voltage and off-state current. By investigating various characteristics, including current-voltage hysteresis, organic film morphology, capacitance-voltage curve and resistance variation of active layers carefully, it has been found the performance improvement is mainly attributed to the low carrier traps and the higher conductivity of the sandwich active layer due to the additional induced carriers in F16CuPc/pentacene. Therefore, using proper multiple active layer is an effective way to gain high performance OTFTs.

Carbon nanostructure-based field-effect transistors for label-free chemical/biological sensors.

PubMed

Hu, PingAn; Zhang, Jia; Li, Le; Wang, Zhenlong; O'Neill, William; Estrela, Pedro

2010-01-01

Over the past decade, electrical detection of chemical and biological species using novel nanostructure-based devices has attracted significant attention for chemical, genomics, biomedical diagnostics, and drug discovery applications. The use of nanostructured devices in chemical/biological sensors in place of conventional sensing technologies has advantages of high sensitivity, low decreased energy consumption and potentially highly miniaturized integration. Owing to their particular structure, excellent electrical properties and high chemical stability, carbon nanotube and graphene based electrical devices have been widely developed for high performance label-free chemical/biological sensors. Here, we review the latest developments of carbon nanostructure-based transistor sensors in ultrasensitive detection of chemical/biological entities, such as poisonous gases, nucleic acids, proteins and cells.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Measurements and sensitivities of LWR in poly spacers

NASA Astrophysics Data System (ADS)

Ayal, Guy; Shauly, Eitan; Levi, Shimon; Siany, Amit; Adan, Ofer; Shacham-Diamand, Yosi

2010-03-01

LER and LWR have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly. In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Analysis of Radiation Effects in Silicon using Kinetic Monte Carlo Methods

DOE PAGES

Hehr, Brian Douglas

2014-11-25

The transient degradation of semiconductor device performance under irradiation has long been an issue of concern. Neutron irradiation can instigate the formation of quasi-stable defect structures, thereby introducing new energy levels into the bandgap that alter carrier lifetimes and give rise to such phenomena as gain degradation in bipolar junction transistors. Normally, the initial defect formation phase is followed by a recovery phase in which defect-defect or defect-dopant interactions modify the characteristics of the damaged structure. A kinetic Monte Carlo (KMC) code has been developed to model both thermal and carrier injection annealing of initial defect structures in semiconductor materials.more » The code is employed to investigate annealing in electron-irradiated, p-type silicon as well as the recovery of base current in silicon transistors bombarded with neutrons at the Los Alamos Neutron Science Center (LANSCE) “Blue Room” facility. Our results reveal that KMC calculations agree well with these experiments once adjustments are made, within the appropriate uncertainty bounds, to some of the sensitive defect parameters.« less

Study on GaN buffer leakage current in AlGaN/GaN high electron mobility transistor structures grown by ammonia-molecular beam epitaxy on 100-mm Si(111)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ravikiran, L.; Radhakrishnan, K., E-mail: ERADHA@e.ntu.edu.sg; Ng, G. I.

2015-06-28

The effect of carbon doping on the structural and electrical properties of GaN buffer layer of AlGaN/GaN high electron mobility transistor (HEMT) structures has been studied. In the undoped HEMT structures, oxygen was identified as the dominant impurity using secondary ion mass spectroscopy and photoluminescence (PL) measurements. In addition, a notable parallel conduction channel was identified in the GaN buffer at the interface. The AlGaN/GaN HEMT structures with carbon doped GaN buffer using a CBr{sub 4} beam equivalent pressure of 1.86 × 10{sup −7} mTorr showed a reduction in the buffer leakage current by two orders of magnitude. Carbon doped GaN buffersmore » also exhibited a slight increase in the crystalline tilt with some pits on the growth surface. PL and Raman measurements indicated only a partial compensation of donor states with carbon acceptors. However, AlGaN/GaN HEMT structures with carbon doped GaN buffer with 200 nm thick undoped GaN near the channel exhibited good 2DEG characteristics.« less

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Field-effect transistor having a superlattice channel and high carrier velocities at high applied fields

DOEpatents

Chaffin, R.J.; Dawson, L.R.; Fritz, I.J.; Osbourn, G.C.; Zipperian, T.E.

1987-06-08

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space. The layer thicknesses of the quantum well layers are selected to provide a superlattice L/sub 2D/-valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley. 2 figs.

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE PAGES

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

2017-11-13

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

III-V heterostructure tunnel field-effect transistor.

PubMed

Convertino, C; Zota, C B; Schmid, H; Ionescu, A M; Moselund, K E

2018-07-04

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

III–V heterostructure tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Convertino, C.; Zota, C. B.; Schmid, H.; Ionescu, A. M.; Moselund, K. E.

2018-07-01

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III–V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

Pixel structures to compensate nonuniform threshold voltage and mobility of polycrystalline silicon thin-film transistors using subthreshold current for large-size active matrix organic light-emitting diode displays

NASA Astrophysics Data System (ADS)

Na, Jun-Seok; Kwon, Oh-Kyong

2014-01-01

We propose pixel structures for large-size and high-resolution active matrix organic light-emitting diode (AMOLED) displays using a polycrystalline silicon (poly-Si) thin-film transistor (TFT) backplane. The proposed pixel structures compensate the variations of the threshold voltage and mobility of the driving TFT using the subthreshold current. The simulated results show that the emission current error of the proposed pixel structure B ranges from -2.25 to 2.02 least significant bit (LSB) when the variations of the threshold voltage and mobility of the driving TFT are ±0.5 V and ±10%, respectively.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2014-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2011-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Graphene Oxide/Poly(3-hexylthiophene) Nanocomposite Thin-Film Phototransistor for Logic Circuit Applications

NASA Astrophysics Data System (ADS)

Mansouri, S.; Coskun, B.; El Mir, L.; Al-Sehemi, Abdullah G.; Al-Ghamdi, Ahmed; Yakuphanoglu, F.

2018-04-01

Graphene is a sheet-structured material that lacks a forbidden band, being a good candidate for use in radiofrequency applications. We have elaborated graphene-oxide-doped poly(3-hexylthiophene) nanocomposite to increase the interlayer distance and thereby open a large bandgap for use in the field of logic circuits. Graphene oxide/poly(3-hexylthiophene) (GO/P3HT) nanocomposite thin-film transistors (TFTs) were fabricated on silicon oxide substrate by spin coating method. The current-voltage ( I- V) characteristics of TFTs with various P3HT compositions were studied in the dark and under light illumination. The photocurrent, charge carrier mobility, subthreshold voltage, density of interface states, density of occupied states, and I ON/ I OFF ratio of the devices strongly depended on the P3HT weight ratio in the composite. The effects of white-light illumination on the electrical parameters of the transistors were investigated. The results indicated that GO/P3HT nanocomposite thin-film transistors have high potential for use in radiofrequency applications, and their feasibility for use in digital applications has been demonstrated.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

PubMed Central

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Indium antimonide quantum well structures for electronic device applications

NASA Astrophysics Data System (ADS)

Edirisooriya, Madhavie

The electron effective mass is smaller in InSb than in any other III-V semiconductor. Since the electron mobility depends inversely on the effective mass, InSb-based devices are attractive for field effect transistors, magnetic field sensors, ballistic transport devices, and other applications where the performance depends on a high mobility or a long mean free path. In addition, electrons in InSb have a large g-factor and strong spin orbit coupling, which makes them well suited for certain spin transport devices. The first n-channel InSb high electron mobility transistor (HEMT) was produced in 2005 with a power-delay product superior to HEMTs with a channel made from any other III-V semiconductor. The high electron mobility in the InSb quantum-well channel increases the switching speed and lowers the required supply voltage. This dissertation focuses on several materials challenges that can further increase the appeal of InSb quantum wells for transistors and other electronic device applications. First, the electron mobility in InSb quantum wells, which is the highest for any semiconductor quantum well, can be further increased by reducing scattering by crystal defects. InSb-based heteroepitaxy is usually performed on semi-insulating GaAs (001) substrates due to the lack of a lattice matched semi-insulating substrate. The 14.6% mismatch between the lattice parameters of GaAs and InSb results in the formation of structural defects such as threading dislocations and microtwins which degrade the electrical and optical properties of InSb-based devices. Chapter 1 reviews the methods and procedures for growing InSb-based heterostructures by molecular beam epitaxy. Chapters 2 and 3 introduce techniques for minimizing the crystalline defects in InSb-based structures grown on GaAs substrates. Chapter 2 discusses a method of reducing threading dislocations by incorporating AlyIn1-ySb interlayers in an AlxIn1-xSb buffer layer and the reduction of microtwin defects by growth on GaAs substrates that are oriented 2° away from the [011] direction. Chapter 3 discusses designing InSb QW layer structures that are strain balanced. By applying these defect-reducing techniques, the electron mobility in InSb quantum wells at room temperature was significantly increased. For complementary logic technology, p-channel transistors with high mobility are equally as important as n-channel transistors. However, achieving a high hole mobility in III-V semiconductors is challenging. A controlled introduction of strain in the quantum-well material is an effective technique for enhancing the hole mobility beyond its value in bulk material. The strain reduces the hole effective mass by splitting the heavy hole and light hole valence bands. Chapter 4 discusses a successful attempt to realize p-type InSb quantum well structures. The biaxial strain applied via a relaxed metamorphic buffer resulted in a significantly higher room-temperature hole mobility and a record high low-temperature hole mobility. To demonstrate the usefulness of high mobility in a device structure, magnetoresistive devices were fabricated from remotely doped InSb QWs. Such devices have numerous practical applications such as position and speed sensors and as read heads in magnetic storage systems. In a magnetoresistive device composed of a series of shorted Hall bars, the magnetoresistance is proportional to the electron mobility squared for small magnetic fields. Hence, the high electron mobility in InSb QWs makes them highly preferable for geometrical magnetoresistors. Chapter 5 reports the fabrication and characterization of InSb quantum-well magnetoresistors. The excellent transport properties of the InSb QWs resulted in high room-temperature sensitivity to applied magnetic fields. Finally, Chapter 6 provides the conclusions obtained during this research effort, and makes suggestions for future work.

Capacitance-voltage analysis of electrical properties for WSe2 field effect transistors with high-k encapsulation layer

NASA Astrophysics Data System (ADS)

Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho Kyun; You, Min Youl; Jin, Jun-Eon; Choi, Miri; Cho, Jiung; Kim, Gyu-Tae

2018-02-01

Doping effects in devices based on two-dimensional (2D) materials have been widely studied. However, detailed analysis and the mechanism of the doping effect caused by encapsulation layers has not been sufficiently explored. In this work, we present experimental studies on the n-doping effect in WSe2 field effect transistors (FETs) with a high-k encapsulation layer (Al2O3) grown by atomic layer deposition. In addition, we demonstrate the mechanism and origin of the doping effect. After encapsulation of the Al2O3 layer, the threshold voltage of the WSe2 FET negatively shifted with the increase of the on-current. The capacitance-voltage measurements of the metal insulator semiconductor (MIS) structure proved the presence of the positive fixed charges within the Al2O3 layer. The flat-band voltage of the MIS structure of Au/Al2O3/SiO2/Si was shifted toward the negative direction on account of the positive fixed charges in the Al2O3 layer. Our results clearly revealed that the fixed charges in the Al2O3 encapsulation layer modulated the Fermi energy level via the field effect. Moreover, these results possibly provide fundamental ideas and guidelines to design 2D materials FETs with high-performance and reliability.

MMIC DHBT Common-Base Amplifier for 172 GHz

NASA Technical Reports Server (NTRS)

Paidi, Vamsi; Griffith, Zack; Wei, Yun; Dahlstrom, Mttias; Urteaga, Miguel; Rodwell, Mark; Samoska, Lorene; Fung, King Man; Schlecht, Erich

2006-01-01

Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.

Silicon Field Effect Transistors as Dual-Use Sensor-Heater Hybrids

PubMed Central

Reddy, Bobby; Elibol, Oguz H.; Nair, Pradeep R.; Dorvel, Brian R.; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2011-01-01

We demonstrate the temperature mediated applications of a previously proposed novel localized dielectric heating method on the surface of dual purpose silicon field effect transistor (FET) sensor-heaters and perform modeling and characterization of the underlying mechanisms. The FETs are first shown to operate as electrical sensors via sensitivity to changes in pH in ionic fluids. The same devices are then demonstrated as highly localized heaters via investigation of experimental heating profiles and comparison to simulation results. These results offer further insight into the heating mechanism and help determine the spatial resolution of the technique. Two important biosensor platform applications spanning different temperature ranges are then demonstrated: a localized heat-mediated DNA exchange reaction and a method for dense selective functionalization of probe molecules via the heat catalyzed complete desorption and reattachment of chemical functionalization to the transistor surfaces. Our results show that the use of silicon transistors can be extended beyond electrical switching and field-effect sensing to performing localized temperature controlled chemical reactions on the transistor itself. PMID:21214189

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Thermal Gradient During Vacuum-Deposition Dramatically Enhances Charge Transport in Organic Semiconductors: Toward High-Performance N-Type Organic Field-Effect Transistors.

PubMed

Kim, Joo-Hyun; Han, Singu; Jeong, Heejeong; Jang, Hayeong; Baek, Seolhee; Hu, Junbeom; Lee, Myungkyun; Choi, Byungwoo; Lee, Hwa Sung

2017-03-22

A thermal gradient distribution was applied to a substrate during the growth of a vacuum-deposited n-type organic semiconductor (OSC) film prepared from N,N'-bis(2-ethylhexyl)-1,7-dicyanoperylene-3,4:9,10-bis(dicarboxyimide) (PDI-CN2), and the electrical performances of the films deployed in organic field-effect transistors (OFETs) were characterized. The temperature gradient at the surface was controlled by tilting the substrate, which varied the temperature one-dimensionally between the heated bottom substrate and the cooled upper substrate. The vacuum-deposited OSC molecules diffused and rearranged on the surface according to the substrate temperature gradient, producing directional crystalline and grain structures in the PDI-CN2 film. The morphological and crystalline structures of the PDI-CN2 thin films grown under a vertical temperature gradient were dramatically enhanced, comparing with the structures obtained from either uniformly heated films or films prepared under a horizontally applied temperature gradient. The field effect mobilities of the PDI-CN2-FETs prepared using the vertically applied temperature gradient were as high as 0.59 cm 2 V -1 s -1 , more than a factor of 2 higher than the mobility of 0.25 cm 2 V -1 s -1 submitted to conventional thermal annealing and the mobility of 0.29 cm 2 V -1 s -1 from the horizontally applied temperature gradient.

Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz.

PubMed

Cao, Yu; Brady, Gerald J; Gui, Hui; Rutherglen, Chris; Arnold, Michael S; Zhou, Chongwu

2016-07-26

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.

Effect of Structure and Disorder on the Charge Transport in Defined Self-Assembled Monolayers of Organic Semiconductors.

PubMed

Schmaltz, Thomas; Gothe, Bastian; Krause, Andreas; Leitherer, Susanne; Steinrück, Hans-Georg; Thoss, Michael; Clark, Timothy; Halik, Marcus

2017-09-26

Self-assembled monolayer field-effect transistors (SAMFETs) are not only a promising type of organic electronic device but also allow detailed analyses of structure-property correlations. The influence of the morphology on the charge transport is particularly pronounced, due to the confined monolayer of 2D-π-stacked organic semiconductor molecules. The morphology, in turn, is governed by relatively weak van-der-Waals interactions and is thus prone to dynamic structural fluctuations. Accordingly, combining electronic and physical characterization and time-averaged X-ray analyses with the dynamic information available at atomic resolution from simulations allows us to characterize self-assembled monolayer (SAM) based devices in great detail. For this purpose, we have constructed transistors based on SAMs of two molecules that consist of the organic p-type semiconductor benzothieno[3,2-b][1]benzothiophene (BTBT), linked to a C 11 or C 12 alkylphosphonic acid. Both molecules form ordered SAMs; however, our experiments show that the size of the crystalline domains and the charge-transport properties vary considerably in the two systems. These findings were confirmed by molecular dynamics (MD) simulations and semiempirical molecular-orbital electronic-structure calculations, performed on snapshots from the MD simulations at different times, revealing, in atomistic detail, how the charge transport in organic semiconductors is influenced and limited by dynamic disorder.

Sensitive Precise p H Measurement with Large-Area Graphene Field-Effect Transistors at the Quantum-Capacitance Limit

NASA Astrophysics Data System (ADS)

Fakih, Ibrahim; Mahvash, Farzaneh; Siaj, Mohamed; Szkopek, Thomas

2017-10-01

A challenge for p H sensing is decreasing the minimum measurable p H per unit bandwidth in an economical fashion. Minimizing noise to reach the inherent limit imposed by charge fluctuation remains an obstacle. We demonstrate here graphene-based ion-sensing field-effect transistors that saturate the physical limit of sensitivity, defined here as the change in electrical response with respect to p H , and achieve a precision limited by charge-fluctuation noise at the sensing layer. We present a model outlining the necessity for maximizing the device carrier mobility, active sensing area, and capacitive coupling in order to minimize noise. We encapsulate large-area graphene with an ultrathin layer of parylene, a hydrophobic polymer, and deposit an ultrathin, stoichiometric p H -sensing layer of either aluminum oxide or tantalum pentoxide. With these structures, we achieve gate capacitances ˜0.6 μ F /cm2 , approaching the quantum-capacitance limit inherent to graphene, along with a near-Nernstian p H response of ˜55 ±2 mV /p H . We observe field-effect mobilities as high as 7000 cm2 V-1 s-1 with minimal hysteresis as a result of the parylene encapsulation. A detection limit of 0.1 m p H in a 60-Hz electrical bandwidth is observed in optimized graphene transistors.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

PubMed

Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

2016-04-26

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Polarization dependent photo-induced bias stress effect in organic transistors.

NASA Astrophysics Data System (ADS)

Podzorov, Vitaly; Choi, Hyun Ho; Najafov, Hikmet; Saranin, Danila; Kharlamov, Nikolai A.; Kuznetzov, Denis V.; Didenko, Sergei I.; Cho, Kilwon; Briseno, Alejandro L.; Rutgers-Misis Collaboration; Ru-P Collaboration; Ru-Um Collaboration; Um-P Collaboration

Photo-induced charge transfer between a semiconductor and a gate insulator that occurs in organic transistors operating under illumination leads to a shift of the onset gate voltage in these devices. Here we report an observation of a polarization dependent photo-induced bias-stress effect in two prototypical single-crystal organic field-effect transistors, based on rubrene and TPBIQ. We find that the rate of the effect is a periodic function of polarization angle of a linearly polarized photoexcitation, with a periodicity of π. The observed phenomenon provides an effective tool for addressing the relationship between molecular packing and parameter drift in organic transistors under illumination. The work was carried out with financial support from the Ministry of Education and Science of the Russian Federation in the framework of Increase Competitiveness Program of NUST «MISiS» (No. K3-2016-004), by gov. decree 16/03/2013, N 211.

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Low nonalloyed Ohmic contact resistance to nitride high electron mobility transistors using N-face growth

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Pei, Yi; Palacios, Tomás; Shen, Likun; Chakraborty, Arpan; McCarthy, Lee S.; Keller, Stacia; DenBaars, Steven P.; Speck, James S.; Mishra, Umesh K.

2007-12-01

Nonalloyed Ohmic contacts on Ga-face n+-GaN/AlGaN/GaN high electron mobility transistor (HEMT) structures typically have significant contact resistance to the two-dimensional electron gas (2DEG) due to the AlGaN barrier. By growing the HEMT structure inverted on the N-face, electrons from the contacts were able to access the 2DEG without going through an AlGaN layer. A low contact resistance of 0.16Ωmm and specific contact resistivity of 5.5×10-7Ωcm2 were achieved without contact annealing on the inverted HEMT structure.

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

PubMed

Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

2009-01-01

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Benzo[ d ][1,2,3]thiadiazole (isoBT): Synthesis, Structural Analysis, and Implementation in Semiconducting Polymers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Zhihua; Brown, Jennifer; Drees, Martin

2016-09-13

Benzo[d][2,1,3]thiadiazole (BT) is a markedly electron-deficient heterocycle widely employed in the realization of organic semiconductors for applications spanning transistors, solar cells, photodetectors, and thermoelectrics. In this contribution, we implement the corresponding isomer, benzo[d][1,2,3]thiadiazole (isoBT), along with new 6-fluoroisoBT and 5,6-difluoro-isoBT units as synthons for constructing alternating copolymers with tetrathiophene (P1-P3). New isoBT-based small molecules as well as the corresponding BTquaterthiophene based polymers (P4-P6) are synthesized and characterized to probe architectural, electronic structural, and device performance differences between the two families. The results demonstrate that isoBT complements BT in enabling highperformance optoelectronic semiconductors with P3 exhibiting hole mobilities surpassing 0.7 cmmore » 2/(V s) in field-effect transistors and power conversion efficiencies of 9% in bulk-heterojunction solar cells.« less

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Ultrasensitive label-free detection of DNA hybridization by sapphire-based graphene field-effect transistor biosensor

NASA Astrophysics Data System (ADS)

Xu, Shicai; Jiang, Shouzhen; Zhang, Chao; Yue, Weiwei; Zou, Yan; Wang, Guiying; Liu, Huilan; Zhang, Xiumei; Li, Mingzhen; Zhu, Zhanshou; Wang, Jihua

2018-01-01

Graphene has attracted much attention in biosensing applications for its unique properties. Because of one-atom layer structure, every atom of graphene is exposed to the environment, making the electronic properties of graphene are very sensitive to charged analytes. Therefore, graphene is an ideal material for transistors in high-performance sensors. Chemical vapor deposition (CVD) method has been demonstrated the most successful method for fabricating large area graphene. However, the conventional CVD methods can only grow graphene on metallic substrate and the graphene has to be transferred to the insulating substrate for further device fabrication. The transfer process creates wrinkles, cracks, or tears on the graphene, which severely degrade electrical properties of graphene. These factors severely degrade the sensing performance of graphene. Here, we directly fabricated graphene on sapphire substrate by high temperature CVD without the use of metal catalysts. The sapphire-based graphene was patterned and make into a DNA biosensor in the configuration of field-effect transistor. The sensors show high performance and achieve the DNA detection sensitivity as low as 100 fM (10-13 M), which is at least 10 times lower than prior transferred CVD G-FET DNA sensors. The use of the sapphire-based G-FETs suggests a promising future for biosensing applications.

Emerging ferroelectric transistors with nanoscale channel materials: the possibilities, the limitations

NASA Astrophysics Data System (ADS)

Hong, Xia

2016-03-01

Combining the nonvolatile, locally switchable polarization field of a ferroelectric thin film with a nanoscale electronic material in a field effect transistor structure offers the opportunity to examine and control a rich variety of mesoscopic phenomena and interface coupling. It is also possible to introduce new phases and functionalities into these hybrid systems through rational design. This paper reviews two rapidly progressing branches in the field of ferroelectric transistors, which employ two distinct classes of nanoscale electronic materials as the conducting channel, the two-dimensional (2D) electron gas graphene and the strongly correlated transition metal oxide thin films. The topics covered include the basic device physics, novel phenomena emerging in the hybrid systems, critical mechanisms that control the magnitude and stability of the field effect modulation and the mobility of the channel material, potential device applications, and the performance limitations of these devices due to the complex interface interactions and challenges in achieving controlled materials properties. Possible future directions for this field are also outlined, including local ferroelectric gate control via nanoscale domain patterning and incorporating other emergent materials in this device concept, such as the simple binary ferroelectrics, layered 2D transition metal dichalcogenides, and the 4d and 5d heavy metal compounds with strong spin-orbit coupling.

Origin of low-frequency noise in pentacene field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/ f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities.

Method of making self-aligned lightly-doped-drain structure for MOS transistors

DOEpatents

Weiner, Kurt H.; Carey, Paul G.

2001-01-01

A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carlos-Pinedo, C.; Rodríguez-Vargas, I.; Martínez-Orozco, J. C.

In this work we present the results obtained from the calculation of the level structure of a n-type delta-doped well Field Effect Transistor when is subjected to hydrostatic pressure. We study the energy level structure as a function of hydrostatic pressure within the range of 0 to 6 kbar for different Schottky barrier height (SBH). We use an analytical expression for the effect of hydrostatic pressure on the SBH and the pressure dependence of the basic parameters of the system as the effective mass m(P) and the dielectric constant ε(P) of GaAs. We found that due to the effects ofmore » hydrostatic pressure, in addition to electronic level structure alteration, the profile of the differential capacitance per unit area C{sup −2} is affected.« less

Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate

NASA Astrophysics Data System (ADS)

Hori, Yasuko; Kuzuhara, Masaaki; Ando, Yuji; Mizuta, Masashi

2000-04-01

Electric field distribution in the channel of a field effect transistor (FET) with a field-modulating plate (FP) has been theoretically investigated using a two-dimensional ensemble Monte Carlo simulation. This analysis revealed that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric field intensity at the drain side of the gate edge under pinch-off bias conditions. This study also found that a partial overlap of the high-field region under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal-semiconductor FET with FP (FPFET) (LGF˜0.2 μm) exhibited a much lower peak electric field intensity than a conventional metal-semiconductor FET. Based on these numerically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while maintaining reasonable gain performance.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

Self-assembled electrical materials from contorted aromatics

NASA Astrophysics Data System (ADS)

Xiao, Shengxiong

This thesis describes the design, synthesis, self-assembly and electrical properties of new types of contorted polycyclic aromatic hydrocarbons. These topologically interesting contorted aromatics show promising transistor characteristics as new building blocks for organic field-effect transistors (OFETs) at different length scales. In chapter 2, a class of pentacenes that are substituted along their long edges with aromatic rings were synthesized. Their solid-state assemblies were studied by X-ray crystallography. Their performance as thin film transistors (TFTs) and single crystal field effect transistors (SCFETs) were systematically evaluated. A structure-property relationship between these highly phenylated pentacenes was found. Chapter 3 explores the new concept of whether a non-planar aromatic core could yield efficacious electronic materials, as the ultimate success in the organic electronics will require a holistic approach to creating new building blocks. Synthesis, functionalization and assembly of a new type of contorted hexabenzocoronene (HBC) whose aromatic core is heavily distorted away from planarity due to the steric congestion around its proximal carbons were discussed. Structural studies by X-ray crystallography showed that these HBC molecules stack into columnar structures in the solid state, which are ideal for conduction. Chapter 4 describes that microscale liquid crystalline thin film OFETs of tetradodecyloxy HBC showed the best transistor properties of all discotic columnar materials. Chapter 5 details the fabrication and characterization of nanoscale single crystalline fiber OFETs of octadodecyloxyl HBC. In Chapter 6 we show that a molecular scale monolayer of HBC acid chlorides could be self-assembled on SiO2 insulating layer and could be organized laterally between the ends of 2 nm carbon nanotube gaps to form high quality FETs that act as environmental and chemical sensors. Chapter 7 details the enforced one-dimensional photoconductivity studies of core-cladding HBCs in thin films. Physical properties, such as charge generation, separation/recombination, and transport in HBCs liquid crystalline thin films were discussed. Chapter 8 describes the synthesis and electrical properties of the second generation of contorted aromatics octabenzocircumbiphenyl (OBC). The significant finding about OBCs is that they can be reversibly protonated with Bronsted acids. The significance of those results is that the conductance of the semiconductive thin film could be controlled and attenuated by doping with acid, which can lead to switchable electronics. Chapter 9 presents our studies of extending the HBC synthetic strategies to the formation of other curved aromatics using "wet chemistry". First a series of nonplanar polycyclic aromatic hydrocarbons was made starting from the olefination of pentacenequinone. Then we utilize chemical reactivity, X-ray crystallography, and DFT calculations to explore three types of olefins of increasing structural complexity. Chapter 10 discusses the transformation of HBCs into bowl-shaped molecules on ruthenium metal surfaces. Surface chemistry studies using scanning tunneling microscopy (STM), reflectance absorbance infrared spectroscopy (RAIRS), and temperature-programmed desorption (TPD) characterization methods, referred to as "dry chemistry", showed the formation of an aromatic hemisphere, which is the end cap of a (6,6) arm-chair single-walled carbon nanotube.

Bipolar Spintronics: From magnetic diodes to magnetic bipolar transistors

NASA Astrophysics Data System (ADS)

Zutic, Igor

2004-03-01

We develop a theory of bipolar (electrons and holes) spin-polarized transport [1,2] in semiconductors and discuss its implications for spintronic devices [3]. In our proposal for magnetic bipolar transistors [4,5] we show how bipolar spintronics can lead to spin and magnetic field controlled active devices, not limited by the magnetoresistive effects used in all-metallic structures [3]. We focus on magnetic p-n diodes [1,2] with spatially dependent spin splitting (Zeeman or exchange) of carrier bands. An exchange splitting can be provided by ferromagnetic semiconductors [6], while a large Zeeman splitting can be realized in the presence of magnetic field in magnetically doped or narrow band gap semiconductors [3]. Our theory of magnetic diodes [1,2] can be directly applied to magnetic bipolar transistors--the three-terminal devices which consist of two magnetic p-n diodes connected in series [4,5]. Predictions of exponentially large magnetoresistance [1] and a strong coupling between the spin and charge transport leading to the spin-voltaic effect [1,7] for magnetic diodes are also relevant for magnetic bipolar transistors. In particular, in n-p-n transistors, we show the importance of considering the nonequilibrium spin leading to the spin-voltaic effect. In addition to the applied magnetic filed, the injected nonequilibrium spin can be used to dynamically control the current amplification (gain). Recent experimental progress [8,9] supports the viability of our theoretical proposals. [1] I. Zutic, J. Fabian, S. Das Sarma, Phys. Rev. Lett. 88, 066603 (2002). [2] J. Fabian, I. Zutic, S. Das Sarma, Phys. Rev. B 66, 165301 (2002). [3] I. Zutic, J. Fabian, S. Das Sarma, Rev. Mod. Phys., in press. [4] J. Fabian, I. Zutic, S. Das Sarma, cond-mat/0211639; cond-mat/0307014, Appl. Phys. Lett., in press. [5] J. Fabian and I. Zutic, cond-mat/0311456. [6] H. Ohno, Science 281, 951 (1998). [7] I. Zutic, J. Fabian, S. Das Sarma, Appl. Phys. Lett. 82, 221 (2003). [8] N. Samarth, S. H. Chun, K. C. Ku, S. J. Potashnik, P. Schiffer, Solid State Commun. 127, 173 (2003). [9] F. Tsui, L. Ma, L. He, Appl. Phys. 83, 954 (2003).

A Field-Effect Transistor (FET) model for ASAP

NASA Technical Reports Server (NTRS)

Ming, L.

1965-01-01

The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

Strained InGaAs/InAlAs Quantum Wells for Complementary III-V Transistors

DTIC Science & Technology

2014-01-01

GaAs substrates for low power and high frequency applications, J. Appl. Phys. 109 (2011) 033706. [28] A. Ali, H. Madan , A. Agrawal, I. Ramirez, R...Growth of InAsSb-channel high electron mobility transistor structures, J. Vac. Sci. Technol. B 23 (2005) 1441–1444. [30] A. Ali, H. Madan , M.J

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Investigation of the impedance modulation of thin films with a chemically-sensitive field-effect transistor

NASA Astrophysics Data System (ADS)

Wiseman, John M.

1988-12-01

This study resulted in the design and fabrication of a Chemically-Sensitive Field-Effect Transistor (CHEMFET) with an interdigitated gate electrode structure. The electrical performance of the CHEMFET, both in the time-domain and frequency domain, was evaluated for detecting changes in the molecular structure and chemical composition in three thin films: an epoxy, copper phthalocyanine (CuPc), and acetylcholinesterase (ACHE). The change in the chemical state of a film was manifested as a change in the electrical impedance of the interdigitated gate electrode structure. For the epoxy, its molecular structure changed as a result of the curing reaction. To induce a change in the chemical state of the CuPc and ACHE films they were exposed to part-per billion concentrations of a challenge gas, either nitrogen dioxide (NO2) or the the organophosphorus compound, diisopropyl methylphosphonate (DIMP). The results clearly show that the CHEMFET can detect chemical and structural changes in an epoxy and CuPc film. The sensitivity of the ACHE film was not unequivocally determined due to long term drift in the ACHE film's electrical properties. The most remarkable result of this effort was the demonstration of a unique selectivity feature in the CHEMFET's frequency dependent response to a challenge gas. The examination of the relative changes in the electrical properties of the CHEMFET at different frequencies showed that the CHEMFET can be used to distinguish between NO2 and Dimp EXPOSURE.

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Thermal transistor utilizing gas-liquid transition.

PubMed

Komatsu, Teruhisa S; Ito, Nobuyasu

2011-01-01

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Investigation of the Sensitivity, Selectivity, and Reversibility of the Chemically-Sensitive Field-Effect Transistor (CHEMFET) to Detect Nitrogen Dioxide, Dimethyl Methylphosphonate, and Boron Trifluoride

DTIC Science & Technology

1993-09-01

SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN DIOXIDE, DIMETHYL METHYLPHOSPHONATE, AND BORON TRIFLUORIDE CHAPTER 1 1 Introduction Our rapidly...AND REVERSIBILITY OF THE CHEMICALLY-SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN 3 E I1• DIOXIDE, DIMETHYL METHYLPHOSPHONATE, ELECTE...AND BORON TRIFLUORIDE Neal Terence Hauschild Second Lieutenant, USAF AFIT/GE/ENG/9 3S-10 93-23815I II11l11l11 l gll I 1i 1111 11 I DEPARTMENT OF THE

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Deposition of tetracene thin films on SiO2/Si substrates by rapid expansion of supercritical solutions using carbon dioxide

NASA Astrophysics Data System (ADS)

Fujii, Tatsuya; Takahashi, Yuta; Uchida, Hirohisa

2015-03-01

We report on a novel deposition technique of tetracene (naphthacene) thin films on SiO2/Si substrates by rapid expansion of supercritical solutions (RESS) using CO2. Optical microscopy and scanning electron microscopy show that the thin films consist of a high density of submicron-sized grains. The growth mode of the grains followed the Volmer-Weber mode. X-ray diffraction shows that the thin films have regularly arranged structures in both the horizontal and vertical directions of the substrate. A fabricated top-contacted organic thin-film transistor with the tetracene active layer showed p-type transistor characteristics with a field-effect mobility of 5.1 × 10-4 cm2 V-1 s-1.

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

A Probe for Measuring Spacecraft Surface Potentials Using a Direct-Gate Field Effect Transistor.

DTIC Science & Technology

1983-09-30

SURFACE POTENTIALS USING A DIRECT-GATE FIELD EFFECT TRANSISTOR Mark N. Horenstein Anton Havretic Trustees of Boston University 881 Commonwealth Avenue...1933 Transistor 6. PERFORMING ORG. REPORT NUMBER 7. AUTHOR(s) S. CONTRACT OR GRANT NUMBER(&) ’_5 Mark N. Horenstein Anton Mavretic F19628-82-K-00 34...at AFGL. These tests can be considered the bench mark tests for device performance, with all elements of the monitoring system optimized to eliminate

Integration of Organic Electrochemical and Field-Effect Transistors for Ultraflexible, High Temporal Resolution Electrophysiology Arrays.

PubMed

Lee, Wonryung; Kim, Dongmin; Rivnay, Jonathan; Matsuhisa, Naoji; Lonjaret, Thomas; Yokota, Tomoyuki; Yawo, Hiromu; Sekino, Masaki; Malliaras, George G; Someya, Takao

2016-11-01

Integration of organic electrochemical transistors and organic field-effect transistors is successfully realized on a 600 nm thick parylene film toward an electrophysiology array. A single cell of an integrated device and a 2 × 2 electrophysiology array succeed in detecting electromyogram with local stimulation of the motor nerve bundle of a transgenic rat by a laser pulse. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

PubMed

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

MOSFET's for Cryogenic Amplifiers

NASA Technical Reports Server (NTRS)

Dehaye, R.; Ventrice, C. A.

1987-01-01

Study seeks ways to build transistors that function effectively at liquid-helium temperatures. Report discusses physics of metaloxide/semiconductor field-effect transistors (MOSFET's) and performances of these devices at cryogenic temperatures. MOSFET's useful in highly sensitive cryogenic preamplifiers for infrared astronomy.

Interaction of solid organic acids with carbon nanotube field effect transistors

NASA Astrophysics Data System (ADS)

Klinke, Christian; Afzali, Ali; Avouris, Phaedon

2006-10-01

A series of solid organic acids were used to p-dope carbon nanotubes. The extent of doping is shown to be dependent on the pKa value of the acids. Highly fluorinated carboxylic acids and sulfonic acids are very effective in shifting the threshold voltage and making carbon nanotube field effect transistors to be more p-type devices. Weaker acids like phosphonic or hydroxamic acids had less effect. The doping of the devices was accompanied by a reduction of the hysteresis in the transfer characteristics. In-solution doping survives standard fabrication processes and renders p-doped carbon nanotube field effect transistors with good transport characteristics.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

A biopolymer transistor: electrical amplification by microtubules.

PubMed

Priel, Avner; Ramos, Arnolt J; Tuszynski, Jack A; Cantiello, Horacio F

2006-06-15

Microtubules (MTs) are important cytoskeletal structures engaged in a number of specific cellular activities, including vesicular traffic, cell cyto-architecture and motility, cell division, and information processing within neuronal processes. MTs have also been implicated in higher neuronal functions, including memory and the emergence of "consciousness". How MTs handle and process electrical information, however, is heretofore unknown. Here we show new electrodynamic properties of MTs. Isolated, taxol-stabilized MTs behave as biomolecular transistors capable of amplifying electrical information. Electrical amplification by MTs can lead to the enhancement of dynamic information, and processivity in neurons can be conceptualized as an "ionic-based" transistor, which may affect, among other known functions, neuronal computational capabilities.

Neuromorphic transistor achieved by redox reaction of WO3 thin film

NASA Astrophysics Data System (ADS)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

Variability aware compact model characterization for statistical circuit design optimization

NASA Astrophysics Data System (ADS)

Qiao, Ying; Qian, Kun; Spanos, Costas J.

2012-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

NASA Astrophysics Data System (ADS)

Zhou, Hong; Maize, Kerry; Qiu, Gang; Shakouri, Ali; Ye, Peide D.

2017-08-01

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

Lead iodide perovskite light-emitting field-effect transistor

PubMed Central

Chin, Xin Yu; Cortecchia, Daniele; Yin, Jun; Bruno, Annalisa; Soci, Cesare

2015-01-01

Despite the widespread use of solution-processable hybrid organic–inorganic perovskites in photovoltaic and light-emitting applications, determination of their intrinsic charge transport parameters has been elusive due to the variability of film preparation and history-dependent device performance. Here we show that screening effects associated to ionic transport can be effectively eliminated by lowering the operating temperature of methylammonium lead iodide perovskite (CH3NH3PbI3) field-effect transistors. Field-effect carrier mobility is found to increase by almost two orders of magnitude below 200 K, consistent with phonon scattering-limited transport. Under balanced ambipolar carrier injection, gate-dependent electroluminescence is also observed from the transistor channel, with spectra revealing the tetragonal to orthorhombic phase transition. This demonstration of CH3NH3PbI3 light-emitting field-effect transistors provides intrinsic transport parameters to guide materials and solar cell optimization, and will drive the development of new electro-optic device concepts, such as gated light-emitting diodes and lasers operating at room temperature. PMID:26108967

Polymer-Oxide Nanolayer/Al Composite Cathode for Efficient Polymer Light-Emitting Diodes

DTIC Science & Technology

2007-06-30

4. Influence of polymer gate dielectrics on n-channel conduction of pentacene -based organic field-effect transistors J. Appl. Phys. 101, 124505...molecular materials, including rubrene, 1,3,5-tris(2-N-phenyl-benzimidzolyl)benzene (TPBI), pentacene , and 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline...BCP, and pentacene . The inset in Fig. 3 presents the molecular structures. TPBI is often utilized as an effective electron injection and hole-blocking

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Thermo-piezo-electro-mechanical simulation of AlGaN (aluminum gallium nitride) / GaN (gallium nitride) High Electron Mobility Transistors

NASA Astrophysics Data System (ADS)

Stevens, Lorin E.

Due to the current public demand of faster, more powerful, and more reliable electronic devices, research is prolific these days in the area of high electron mobility transistor (HEMT) devices. This is because of their usefulness in RF (radio frequency) and microwave power amplifier applications including microwave vacuum tubes, cellular and personal communications services, and widespread broadband access. Although electrical transistor research has been ongoing since its inception in 1947, the transistor itself continues to evolve and improve much in part because of the many driven researchers and scientists throughout the world who are pushing the limits of what modern electronic devices can do. The purpose of the research outlined in this paper was to better understand the mechanical stresses and strains that are present in a hybrid AlGaN (Aluminum Gallium Nitride) / GaN (Gallium Nitride) HEMT, while under electrically-active conditions. One of the main issues currently being researched in these devices is their reliability, or their consistent ability to function properly, when subjected to high-power conditions. The researchers of this mechanical study have performed a static (i.e. frequency-independent) reliability analysis using powerful multiphysics computer modeling/simulation to get a better idea of what can cause failure in these devices. Because HEMT transistors are so small (micro/nano-sized), obtaining experimental measurements of stresses and strains during the active operation of these devices is extremely challenging. Physical mechanisms that cause stress/strain in these structures include thermo-structural phenomena due to mismatch in both coefficient of thermal expansion (CTE) and mechanical stiffness between different materials, as well as stress/strain caused by "piezoelectric" effects (i.e. mechanical deformation caused by an electric field, and conversely voltage induced by mechanical stress) in the AlGaN and GaN device portions (both piezoelectric materials). This piezoelectric effect can be triggered by voltage applied to the device's gate contact and the existence of an HEMT-unique "two-dimensional electron gas" (2DEG) at the GaN-AlGaN interface. COMSOL Multiphysics computer software has been utilized to create a finite element (i.e. piece-by-piece) simulation to visualize both temperature and stress/strain distributions that can occur in the device, by coupling together (i.e. solving simultaneously) the thermal, electrical, structural, and piezoelectric effects inherent in the device. The 2DEG has been modeled not with the typically-used self-consistent quantum physics analytical equations, rather as a combined localized heat source* (thermal) and surface charge density* (electrical) boundary condition. Critical values of stress/strain and their respective locations in the device have been identified. Failure locations have been estimated based on the critical values of stress and strain, and compared with reports in literature. The knowledge of the overall stress/strain distribution has assisted in determining the likely device failure mechanisms and possible mitigation approaches. The contribution and interaction of individual stress mechanisms including piezoelectric effects and thermal expansion caused by device self-heating (i.e. fast-moving electrons causing heat) have been quantified. * Values taken from results of experimental studies in literature.

BioMEMS for mitochondria medicine

NASA Astrophysics Data System (ADS)

Padmaraj, Divya

A BioMEMS device to study cell-mitochondrial physiological functionalities was developed. The pathogenesis of many diseases including obesity, diabetes and heart failure as well as aging has been linked to functional defects of mitochondria. The synthesis of Adenosine Tri Phosphate (ATP) is determined by the electrical potential across the inner mitochondrial membrane and by the pH difference due to proton flux across it. Therefore, electrical characterization by E-fields with complementary chemical testing was used here. The BioMEMS device was fabricated as an SU-8 based microfluidic system with gold electrodes on SiO2/Si wafers for electromagnetic interrogation. Ion Sensitive Field Effect Transistors (ISFETs) were incorporated for proton studies important in the electron transport chain, together with monitoring Na+, K+ and Ca++ ions for ion channel studies. ISFETs are chemically sensitive Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices and their threshold voltage is directly proportional to the electrolytic H+ ion variation. These ISFETs (sensitivity ˜55 mV/pH for H+) were further realized as specific ion sensitive Chemical Field Effect Transistors (CHEMFETs) by depositing a specific ion sensitive membrane on the gate. Electrodes for dielectric spectroscopy studies of mitochondria were designed as 2- and 4-probe structures for optimized operation over a wide frequency range. In addition, to limit polarization effects, a 4-electrode set-up with unique meshed pickup electrodes (7.5x7.5 mum2 loops with 4 mum wires) was fabricated. Sensitivity of impedance spectroscopy to membrane potential changes was confirmed by studying the influence of uncouplers and glucose on mitochondria. An electrical model was developed for the mitochondrial sample, and its frequency response correlated with impedance spectroscopy experiments of sarcolemmal mitochondria. Using the mesh electrode structure, we obtained a reduction of 83.28% in impedance at 200 Hz. COMSOL simulations of selected electrical structures in this sensor were compared with experimental results to better understand the physical system. A broadband permittivity analysis tool consisting of lumped and distributed structures was also developed. The frequency range of this device is from 100 Hz to 40 GHz and utilizes an interdigitated capacitor and coplanar waveguide. The simultaneous measurement of membrane potential, ion concentrations and pH would enhance diagnostics and studies of mitochondrial diseases.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Vertical GaN Devices for Power Electronics in Extreme Environments

DTIC Science & Technology

2016-03-31

electronics applications. In this paper vertical p-n diodes and transistors fabricated on pseudo bulk low defect density (104 to 106 cm-2) GaN substrates are...holes in p-GaN has deleterious effect on p-n junction behavior (Fig. 2), p-GaN contacts, and channel control in junction field-effect transistors at...and transistors ) utilizing p-n junctions are suitable for most practical applications including automotive (210K < T < 423K) but may have limitations

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2017-03-01

energy levels on a GaN-on-silicon high electron mobility transistor was created. Based on physical results of 2.0-MeV protons irradiation to fluence...and the physical device at 2.0-MeV proton irradiation , predictions were made for 5.0, 10.0, 20.0 and 40.0-MeV proton irradiation . The model generally...nitride, high electron mobility transistor, electronics, 2 MeV proton irradiation , radiation effects 15. NUMBER OF PAGES 87 16. PRICE CODE 17. SECURITY

Localized heating on silicon field effect transistors: device fabrication and temperature measurements in fluid.

PubMed

Elibol, Oguz H; Reddy, Bobby; Nair, Pradeep R; Dorvel, Brian; Butler, Felice; Ahsan, Zahab S; Bergstrom, Donald E; Alam, Muhammad A; Bashir, Rashid

2009-10-07

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Field-Induced Disorder and Carrier Localization in Molecular Organic Transistors

NASA Astrophysics Data System (ADS)

Ando, M.; Minakata, T.; Duffy, C.; Sirringhaus, H.

2009-06-01

We propose a "field-induced polymorphous disorder" model to explain bias-stress instability in molecular organic thin-film transistors, based on the experimental results showing the strong correlation between the micro-structural change in semiconductor layer composed of penrtacene molecules and the threshold voltage (Vth) shift due to electron trapping in a reversible manner under the successive bias-stress, thermal annealing, and light irradiation.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Study of vertical type organic light emitting transistor using ZnO

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2006-04-01

We propose a new type organic light emitting transistor (OLET) combining static induction transistor (SIT) with double hetero junction type organic light emitting diodes (OLED) using n-type zinc oxide (ZnO) films which works as a transparent and electron injection layer. The device characteristics of newly developed OLED and ZnO-SIT showed relatively high luminance of about 500 cd/m2 at 7.6 mA/cm2 and is able to control by gate voltage as low as a few volts, respectively. The crystal structures of the ZnO films as a function of Ar/O II flow ratio and the basic characteristics of the thin film transistor (TFT) and SIT depending on the ZnO sputtering conditions are investigated. The results obtained here show that the OLET using ZnO film is a suitable element for flexible sheet displays.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

NASA Astrophysics Data System (ADS)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

PubMed

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

Gallium nitride junction field-effect transistor

DOEpatents

Zolper, John C.; Shul, Randy J.

1999-01-01

An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

Energy-Saving Inverter

NASA Technical Reports Server (NTRS)

Rippel, W. E.; Edwards, D. B.

1984-01-01

Commutation by field-effect transistor allows more efficient operation. High voltage field-effect transistor (FET) controls silicon controlled rectifiers (SCR's). Circuit requires only one capacitor and one inductor in commutation circuit: simpler, more efficient, and more economical than conventional inverters. Adaptable to dc-to-dc converters.

Temperature Dependence of Field-Effect Mobility in Organic Thin-Film Transistors: Similarity to Inorganic Transistors.

PubMed

Okada, Jun; Nagase, Takashi; Kobayashi, Takashi; Naito, Hiroyoshi

2016-04-01

Carrier transport in solution-processed organic thin-film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8-BTBT) has been investigated in a wide temperature range from 296 to 10 K. The field-effect mobility shows thermally activated behavior whose activation energy becomes smaller with decreasing temperature. The temperature dependence of field-effect mobility found in C8-BTBT is similar to that of others materials: organic semiconducting polymers, amorphous oxide semiconductors and hydrogenated amorphous silicon. These results indicate that hopping transport between isoenergetic localized states becomes dominated in a low temperature regime in these materials.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Field-induced structural control of COx molecules adsorbed on graphene

NASA Astrophysics Data System (ADS)

Matsubara, Manaho; Okada, Susumu

2018-05-01

Using the density functional theory combined with both the van der Waals correction and the effective screening medium method, we investigate the energetics and electronic structures of CO and CO2 molecules adsorbed on graphene surfaces in the field-effect-transistor structure with respect to the external electric field by the excess electrons/holes. The binding energies of CO and CO2 molecules to graphene monotonically increase with increasing hole and electron concentrations. The increase occurs regardless of the molecular conformations to graphene and the counter electrode, indicating that the carrier injection substantially enhances the molecular adsorption on graphene. Injected carriers also modulate the stable molecular conformation, which is metastable in the absence of an electric field.

Patterned Liquid Metal Contacts for Printed Carbon Nanotube Transistors.

PubMed

Andrews, Joseph B; Mondal, Kunal; Neumann, Taylor V; Cardenas, Jorge A; Wang, Justin; Parekh, Dishit P; Lin, Yiliang; Ballentine, Peter; Dickey, Michael D; Franklin, Aaron D

2018-05-14

Flexible and stretchable electronics are poised to enable many applications that cannot be realized with traditional, rigid devices. One of the most promising options for low-cost stretchable transistors are printed carbon nanotubes (CNTs). However, a major limiting factor in stretchable CNT devices is the lack of a stable and versatile contact material that forms both the interconnects and contact electrodes. In this work, we introduce the use of eutectic gallium-indium (EGaIn) liquid metal for electrical contacts to printed CNT channels. We analyze thin-film transistors (TFTs) fabricated using two different liquid metal deposition techniques-vacuum-filling polydimethylsiloxane (PDMS) microchannel structures and direct-writing liquid metals on the CNTs. The highest performing CNT-TFT was realized using vacuum-filled microchannel deposition with an in situ annealing temperature of 150 °C. This device exhibited an on/off ratio of more than 10 4 and on-currents as high as 150 μA/mm-metrics that are on par with other printed CNT-TFTs. Additionally, we observed that at room temperature the contact resistances of the vacuum-filled microchannel structures were 50% lower than those of the direct-write structures, likely due to the poor adhesion between the materials observed during the direct-writing process. The insights gained in this study show that stretchable electronics can be realized using low-cost and solely solution processing techniques. Furthermore, we demonstrate methods that can be used to electrically characterize semiconducting materials as transistors without requiring elevated temperatures or cleanroom processes.

Facet-selective nucleation and conformal epitaxy of Ge shells on Si nanowires

DOE PAGES

Nguyen, Binh -Minh; Swartzentruber, Brian; Ro, Yun Goo; ...

2015-10-08

Knowledge of nanoscale heteroepitaxy is continually evolving as advances in material synthesis reveal new mechanisms that have not been theoretically predicted and are different than what is known about planar structures. In addition to a wide range of potential applications, core/shell nanowire structures offer a useful template to investigate heteroepitaxy at the atomistic scale. We show that the growth of a Ge shell on a Si core can be tuned from the theoretically predicted island growth mode to a conformal, crystalline, and smooth shell by careful adjustment of growth parameters in a narrow growth window that has not been exploredmore » before. In the latter growth mode, Ge adatoms preferentially nucleate islands on the {113} facets of the Si core, which outgrow over the {220} facets. Islands on the low-energy {111} facets appear to have a nucleation delay compared to the {113} islands; however, they eventually coalesce to form a crystalline conformal shell. As a result, synthesis of epitaxial and conformal Si/Ge/Si core/multishell structures enables us to fabricate unique cylindrical ring nanowire field-effect transistors, which we demonstrate to have steeper on/off characteristics than conventional core/shell nanowire transistors.« less

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Structural, optical, and electrical properties of PbSe nanocrystal solids treated thermally or with simple amines.

PubMed

Law, Matt; Luther, Joseph M; Song, Qing; Hughes, Barbara K; Perkins, Craig L; Nozik, Arthur J

2008-05-07

We describe the structural, optical, and electrical properties of films of spin-cast, oleate-capped PbSe nanocrystals that are treated thermally or chemically in solutions of hydrazine, methylamine, or pyridine to produce electronically coupled nanocrystal solids. Postdeposition heat treatments trigger nanocrystal sintering at approximately 200 degrees C, before a substantial fraction of the oleate capping group evaporates or pyrolyzes. The sintered nanocrystal films have a large hole density and are highly conductive. Most of the amine treatments preserve the size of the nanocrystals and remove much of the oleate, decreasing the separation between nanocrystals and yielding conductive films. X-ray scattering, X-ray photoelectron and optical spectroscopy, electron microscopy, and field-effect transistor electrical measurements are used to compare the impact of these chemical treatments. We find that the concentration of amines adsorbed to the NC films is very low in all cases. Treatments in hydrazine in acetonitrile remove only 2-7% of the oleate yet result in high-mobility n-type transistors. In contrast, ethanol-based hydrazine treatments remove 85-90% of the original oleate load. Treatments in pure ethanol strip 20% of the oleate and create conductive p-type transistors. Methylamine- and pyridine-treated films are also p-type. These chemically treated films oxidize rapidly in air to yield, after short air exposures, highly conductive p-type nanocrystal solids. Our results aid in the rational development of solar cells based on colloidal nanocrystal films.

New GaN based HEMT with Si3N4 or un-doped region in the barrier for high power applications

NASA Astrophysics Data System (ADS)

Razavi, S. M.; Tahmasb Pour, S.; Najari, P.

2018-06-01

New AlGaN/GaN high electron mobility transistors (HEMTs) that their barrier layers under the gate are divided into two regions horizontally are presented in this work. Upper region is Si3N4 (SI-HEMT) or un-doped AlGaN (UN-HEMT) and lower region is AlGaN with heavier doping compared to barrier layer. Upper region in SI-HEMT and UN-HEMT reduces peak electric field in the channel and then improves breakdown voltage considerably. Lower region increases electron density in the two dimensional electron gas (2-DEG) and enhances drain current significantly. For instance, saturated drain current in SI-HEMT is about 100% larger than that in the conventional one. Moreover, the maximum breakdown voltage in the proposed structures is 65 V. This value is about 30% larger than that in the conventional transistor (50 V). Also, suggested structure reduces short channel effect such as DIBL. The maximum gm is obtained in UN-HEMT and conventional devices. Proposed structures improve breakdown voltage and saturated drain current and then enhance maximum output power density. Maximum output power density in the new structures is about 150% higher than that in the conventional.

Defect healing at room temperature in pentacene thin films and improved transistor performance

NASA Astrophysics Data System (ADS)

Kalb, Wolfgang L.; Meier, Fabian; Mattenberger, Kurt; Batlogg, Bertram

2007-11-01

We report on a healing of defects at room temperature in the organic semiconductor pentacene. This peculiar effect is a direct consequence of the weak intermolecular interaction which is characteristic of organic semiconductors. Pentacene thin-film transistors were fabricated and characterized by in situ gated four-terminal measurements. Under high vacuum conditions (base pressure of order 10-8mbar ), the device performance is found to improve with time. The effective field-effect mobility increases by as much as a factor of 2 and mobilities up to 0.45cm2/Vs were achieved. In addition, the contact resistance decreases by more than an order of magnitude and there is a significant reduction in current hysteresis. Oxygen and nitrogen exposure as well as annealing experiments show the improvement of the electronic parameters to be driven by a thermally promoted process and not by chemical doping. In order to extract the spectral density of trap states from the transistor characteristics, we have implemented a powerful scheme which allows for a calculation of the trap densities with high accuracy in a straightforward fashion. We show the performance improvement to be due to a reduction in the density of shallow traps ⩽0.15eV from the valence band edge, while the energetically deeper traps are essentially unaffected. This work contributes to an understanding of the shallow traps in organic semiconductors and identifies structural point defects within the grains of the polycrystalline thin films as a major cause.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change inmore » drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.« less

Improved Field-Effect Transistor Equations for Computer Simulation.

ERIC Educational Resources Information Center

Kidd, Richard; Ardini, James

1979-01-01

Presents a laboratory experiment that was developed to acquaint physics students with field-effect transistor characteristics and circuits. Computer-drawn curves supplementing student laboratory exercises can be generated to provide more permanent, usable data than those taken from a curve tracer. (HM)

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Linear conduction in N-type organic field effect transistors with nanometric channel lengths and graphene as electrodes

NASA Astrophysics Data System (ADS)

Chianese, F.; Candini, A.; Affronte, M.; Mishra, N.; Coletti, C.; Cassinese, A.

2018-05-01

In this work, we test graphene electrodes in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivative. By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied bias, in contrast with the supralinear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrode devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ˜140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current in short channel OFETs.

Large-signal model of the bilayer graphene field-effect transistor targeting radio-frequency applications: Theory versus experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pasadas, Francisco, E-mail: Francisco.Pasadas@uab.cat; Jiménez, David

2015-12-28

Bilayer graphene is a promising material for radio-frequency transistors because its energy gap might result in a better current saturation than the monolayer graphene. Because the great deal of interest in this technology, especially for flexible radio-frequency applications, gaining control of it requires the formulation of appropriate models for the drain current, charge, and capacitance. In this work, we have developed them for a dual-gated bilayer graphene field-effect transistor. A drift-diffusion mechanism for the carrier transport has been considered coupled with an appropriate field-effect model taking into account the electronic properties of the bilayer graphene. Extrinsic resistances have been includedmore » considering the formation of a Schottky barrier at the metal-bilayer graphene interface. The proposed model has been benchmarked against experimental prototype transistors, discussing the main figures of merit targeting radio-frequency applications.« less

Localized Heating on Silicon Field Effect Transistors: Device Fabrication and Temperature Measurements in Fluid

PubMed Central

Elibol, Oguz H.; Reddy, Bobby; Nair, Pradeep R.; Dorvel, Brian; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2010-01-01

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications. PMID:19967115

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

NASA Astrophysics Data System (ADS)

Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

2017-04-01

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less