A Comprehensive Study on Energy Efficiency and Performance of Flash-based SSD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, Seon-Yeon; Kim, Youngjae; Urgaonkar, Bhuvan

2011-01-01

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation tomore » investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.« less

The Forensic Potential of Flash Memory

DTIC Science & Technology

2009-09-01

limit range of 10 to 100 years before data is lost [12]. 5. Flash Memory Logical Structure The logical structure of flash memory from least to...area is not standardized and is manufacturer specific. This information will be used by the wear leveling algorithms and as such will be proprietary...memory cells, the manufacturers of the flash implement a wear leveling algorithm . In contrast, a magnetic disk in an overwrite operation will reuse the

An upconverted photonic nonvolatile memory.

PubMed

Zhou, Ye; Han, Su-Ting; Chen, Xian; Wang, Feng; Tang, Yong-Bing; Roy, V A L

2014-08-21

Conventional flash memory devices are voltage driven and found to be unsafe for confidential data storage. To ensure the security of the stored data, there is a strong demand for developing novel nonvolatile memory technology for data encryption. Here we show a photonic flash memory device, based on upconversion nanocrystals, which is light driven with a particular narrow width of wavelength in addition to voltage bias. With the help of near-infrared light, we successfully manipulate the multilevel data storage of the flash memory device. These upconverted photonic flash memory devices exhibit high ON/OFF ratio, long retention time and excellent rewritable characteristics.

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Non Volatile Flash Memory Radiation Tests

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.; Allen, Greg

2012-01-01

Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.

Improved charge trapping properties by embedded graphene oxide quantum-dots for flash memory application

NASA Astrophysics Data System (ADS)

Jia, Xinlei; Yan, Xiaobing; Wang, Hong; Yang, Tao; Zhou, Zhenyu; Zhao, Jianhui

2018-06-01

In this work, we have investigated two kinds of charge trapping memory devices with Pd/Al2O3/ZnO/SiO2/p-Si and Pd/Al2O3/ZnO/graphene oxide quantum-dots (GOQDs)/ZnO/SiO2/p-Si structure. Compared with the single ZnO sample, the memory window of the ZnO-GOQDs-ZnO sample reaches a larger value (more than doubled) of 2.7 V under the sweeping gate voltage ± 7 V, indicating a better charge storage capability and the significant charge trapping effects by embedding the GOQDs trapping layer. The ZnO-GOQDs-ZnO devices have better date retention properties with the high and low capacitances loss of ˜ 1.1 and ˜ 6.9%, respectively, as well as planar density of the trapped charges of 1.48 × 1012 cm- 2. It is proposed that the GOQDs play an important role in the outstanding memory characteristics due to the deep quantum potential wells and the discrete distribution of the GOQDs. The long date retention time might have resulted from the high potential barrier which suppressed both the back tunneling and the leakage current. Intercalating GOQDs in the memory device is a promising method to realize large memory window, low-power consumption and excellent retention properties.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2010-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

Physical principles and current status of emerging non-volatile solid state memories

NASA Astrophysics Data System (ADS)

Wang, L.; Yang, C.-H.; Wen, J.

2015-07-01

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance. [Figure not available: see fulltext.

76 FR 41824 - In the Matter of Certain Flash Memory Chips And Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-15

... Memory Chips And Products Containing Same; Notice of Commission Determination Not To Review an Initial... unopposed motion to terminate in its entirety Inv. No. 337-TA-735, Certain Flash Memory Chips and Products... flash memory chips and products containing same by reason of infringement of certain claims of U.S...

Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

NASA Astrophysics Data System (ADS)

Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

Configurable test bed design for nanosats to qualify commercial and customized integrated circuits

NASA Astrophysics Data System (ADS)

Guareschi, W.; Azambuja, J.; Kastensmidt, F.; Reis, R.; Durao, O.; Schuch, N.; Dessbesel, G.

The use of small satellites has increased substantially in recent years due to the reduced cost of their development and launch, as well to the flexibility offered by commercial components. The test bed is a platform that allows components to be evaluated and tested in space. It is a flexible platform, which can be adjusted to a wide quantity of components and interfaces. This work proposes the design and implementation of a test bed suitable for test and evaluation of commercial circuits used in nanosatellites. The development of such a platform allows developers to reduce the efforts in the integration of components and therefore speed up the overall system development time. The proposed test bed is a configurable platform implemented using a Field Programmable Gate Array (FPGA) that controls the communication protocols and connections to the devices under test. The Flash-based ProASIC3E FPGA from Microsemi is used as a control system. This adaptive system enables the control of new payloads and softcores for test and validation in space. Thus, the integration can be easily performed through configuration parameters. It is intended for modularity. Each component connected to the test bed can have a specific interface programmed using a hardware description language (HDL). The data of each component is stored in embedded memories. Each component has its own memory space. The size of the allocated memory can be also configured. The data transfer priority can be set and packaging can be added to the logic, when needed. Communication with peripheral devices and with the Onboard Computer (OBC) is done through the pre-implemented protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) and external memory control. In loco primary tests demonstrated the control system's functionality. The commercial ProASIC3E FPGA family is not space-flight qualified, but tests have been made under Total Ionizing Dose (TID) showing its robustness up to 25 kr- ds (Si). When considering proton and heavy ions, flash-based FPGAs provide immunity to configuration loss and low bit-flips susceptibility in flash memory. In this first version of the test bed two components are connected to the controller FPGA: a commercial magnetometer and a hardened test chip. The embedded FPGA implements a Single Event Effects (SEE) hardened microprocessor and few other soft-cores to be used in space. This test bed will be used in the NanoSatC-BR1, the first Brazilian Cubesat scheduled to be launched in mid-2013.

Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2011-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

76 FR 4375 - In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-25

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-683] In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... the United States after importation of certain MLC flash memory devices and products containing same...

78 FR 49287 - Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-13

... INTERNATIONAL TRADE COMMISSION [Docket No 2971] Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of Complaint; Solicitation of Comments Relating to the Public..., Certain Flash Memory Chips and Products Containing the Same, DN 2971; the Commission solicited comments on...

Active Flash: Out-of-core Data Analytics on Flash Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S

2012-01-01

Next generation science will increasingly come to rely on the ability to perform efficient, on-the-fly analytics of data generated by high-performance computing (HPC) simulations, modeling complex physical phenomena. Scientific computing workflows are stymied by the traditional chaining of simulation and data analysis, creating multiple rounds of redundant reads and writes to the storage system, which grows in cost with the ever-increasing gap between compute and storage speeds in HPC clusters. Recent HPC acquisitions have introduced compute node-local flash storage as a means to alleviate this I/O bottleneck. We propose a novel approach, Active Flash, to expedite data analysis pipelines bymore » migrating to the location of the data, the flash device itself. We argue that Active Flash has the potential to enable true out-of-core data analytics by freeing up both the compute core and the associated main memory. By performing analysis locally, dependence on limited bandwidth to a central storage system is reduced, while allowing this analysis to proceed in parallel with the main application. In addition, offloading work from the host to the more power-efficient controller reduces peak system power usage, which is already in the megawatt range and poses a major barrier to HPC system scalability. We propose an architecture for Active Flash, explore energy and performance trade-offs in moving computation from host to storage, demonstrate the ability of appropriate embedded controllers to perform data analysis and reduction tasks at speeds sufficient for this application, and present a simulation study of Active Flash scheduling policies. These results show the viability of the Active Flash model, and its capability to potentially have a transformative impact on scientific data analysis.« less

A Fault-Tolerant Radiation-Robust Mass Storage Concept for Highly Scaled Flash Memory

NASA Astrophysics Data System (ADS)

Fuchs, Cristian M.; Trinitis, Carsten; Appel, Nicolas; Langer, Martin

2015-09-01

Future spacemissions will require vast amounts of data to be stored and processed aboard spacecraft. While satisfying operational mission requirements, storage systems must guarantee data integrity and recover damaged data throughout the mission. NAND-flash memories have become popular for space-borne high performance mass memory scenarios, though future storage concepts will rely upon highly scaled flash or other memory technologies. With modern flash memory, single bit erasure coding and RAID based concepts are insufficient. Thus, a fully run-time configurable, high performance, dependable storage concept, requiring a minimal set of logic or software. The solution is based on composite erasure coding and can be adjusted for altered mission duration or changing environmental conditions.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Dynamic Forest: An Efficient Index Structure for NAND Flash Memory

NASA Astrophysics Data System (ADS)

Yang, Chul-Woong; Yong Lee, Ki; Ho Kim, Myoung; Lee, Yoon-Joon

In this paper, we present an efficient index structure for NAND flash memory, called the Dynamic Forest (D-Forest). Since write operations incur high overhead on NAND flash memory, D-Forest is designed to minimize write operations for index updates. The experimental results show that D-Forest significantly reduces write operations compared to the conventional B+-tree.

76 FR 40931 - In the Matter of Certain Flash Memory and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-12

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-685] In the Matter of Certain Flash Memory and... for importation, and the sale within the United States after importation of certain flash memory and... other agreements, written or oral, express or implied, between the parties concerning the subject matter...

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ'S Final... States after importation of certain flash memory chips and products containing the same by reason of...

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ's Final... flash memory chips and products containing the same by reason of infringement of various claims of...

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Some Improvements in Utilization of Flash Memory Devices

NASA Technical Reports Server (NTRS)

Gender, Thomas K.; Chow, James; Ott, William E.

2009-01-01

Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

NASA Astrophysics Data System (ADS)

Sakaki, Yukiya; Yamada, Tomoaki; Matsui, Chihiro; Yamaga, Yusuke; Takeuchi, Ken

2018-04-01

In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with two-dimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

NRAM: a disruptive carbon-nanotube resistance-change memory.

PubMed

Gilmer, D C; Rueckes, T; Cleveland, L

2018-04-03

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

NRAM: a disruptive carbon-nanotube resistance-change memory

NASA Astrophysics Data System (ADS)

Gilmer, D. C.; Rueckes, T.; Cleveland, L.

2018-04-01

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

Co-design of application software and NAND flash memory in solid-state drive for relational database storage system

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Sun, Chao; Soga, Ayumi; Takeuchi, Ken

2014-01-01

A relational database management system (RDBMS) is designed based on NAND flash solid-state drive (SSD) for storage. By vertically integrating the storage engine (SE) and the flash translation layer (FTL), system performance is maximized and the internal SSD overhead is minimized. The proposed RDBMS SE utilizes physical information about the NAND flash memory which is supplied from the FTL. The query operation is also optimized for SSD. By these treatments, page-copy-less garbage collection is achieved and data fragmentation in the NAND flash memory is suppressed. As a result, RDBMS performance increases by 3.8 times, power consumption of SSD decreases by 46% and SSD life time is increased by 61%. The effectiveness of the proposed scheme increases with larger erase block sizes, which matches the future scaling trend of three-dimensional (3D-) NAND flash memories. The preferable row data size of the proposed scheme is below 500 byte for 16 kbyte page size.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Method for programming a flash memory

DOEpatents

Brosky, Alexander R.; Locke, William N.; Maher, Conrado M.

2016-08-23

A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device.

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Chen, D.; Friendlich, M.; Carts, M. A.; Seidleck, C. M.; LaBel, K. A.

2011-01-01

We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. Under some circumstanc es, radiation exposure has a significant effect on the retention of f lash memories.

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface

DTIC Science & Technology

2016-03-17

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface Austin H. Roach, Matthew J. Gadlage, James D. Ingalls, Aaron...reliability and trust of memories is very important, but because of incomplete documentation provided by commercial vendors and a lack of low-level...shown here that useful information about the trust and reliability of COTS NAND Flash components can be obtained by going beyond the standard product

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Hung, Chinglin; Takeuchi, Ken

2012-04-01

The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

NASA Astrophysics Data System (ADS)

Matsui, Chihiro; Kinoshita, Reika; Takeuchi, Ken

2018-04-01

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Space Radiation Effects in Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Johnston, A. H.

2001-01-01

Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

FPGA Flash Memory High Speed Data Acquisition

NASA Technical Reports Server (NTRS)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

NASA Astrophysics Data System (ADS)

Tokutomi, Tsukasa; Tanakamaru, Shuhei; Iwasaki, Tomoko Ogura; Takeuchi, Ken

2015-09-01

To improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012, 2013), which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2×nm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4× and 9.5× at room-temperature (RT) and 85 °C, respectively. Similarly, the acceptable BER is increased by 1.8× and 2.3×, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

NASA Technical Reports Server (NTRS)

Irom, Farokh; Allen, Gregory R.

2012-01-01

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Fast neutron irradiation tests of flash memories used in space environment at the ISIS spallation neutron source

NASA Astrophysics Data System (ADS)

Andreani, C.; Senesi, R.; Paccagnella, A.; Bagatin, M.; Gerardin, S.; Cazzaniga, C.; Frost, C. D.; Picozza, P.; Gorini, G.; Mancini, R.; Sarno, M.

2018-02-01

This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source. The two neutron beam lines are set up to mimic the space environment spectra and allow neutron irradiation tests on Flash memories in the neutron energy range above 10 MeV and up to 800 MeV. The ISIS neutron energy spectrum is similar to the one occurring in the atmospheric as well as in space and planetary environments, with intensity enhancements varying in the range 108- 10 9 and 106- 10 7 respectively. Such conditions are suitable for the characterization of the atmospheric, space and planetary neutron radiation environments, and are directly applicable for accelerated tests of electronic components as demonstrated here in benchmark measurements performed on flash memories.

An Embedded Sensor Node Microcontroller with Crypto-Processors.

PubMed

Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

2016-04-27

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed.

An Embedded Sensor Node Microcontroller with Crypto-Processors

PubMed Central

Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

2016-01-01

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed. PMID:27128925

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2010-01-01

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

Asymmetric programming: a highly reliable metadata allocation strategy for MLC NAND flash memory-based sensor systems.

PubMed

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-10-10

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme.

Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

PubMed Central

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-01-01

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme. PMID:25310473

Optimized design of embedded DSP system hardware supporting complex algorithms

NASA Astrophysics Data System (ADS)

Li, Yanhua; Wang, Xiangjun; Zhou, Xinling

2003-09-01

The paper presents an optimized design method for a flexible and economical embedded DSP system that can implement complex processing algorithms as biometric recognition, real-time image processing, etc. It consists of a floating-point DSP, 512 Kbytes data RAM, 1 Mbytes FLASH program memory, a CPLD for achieving flexible logic control of input channel and a RS-485 transceiver for local network communication. Because of employing a high performance-price ratio DSP TMS320C6712 and a large FLASH in the design, this system permits loading and performing complex algorithms with little algorithm optimization and code reduction. The CPLD provides flexible logic control for the whole DSP board, especially in input channel, and allows convenient interface between different sensors and DSP system. The transceiver circuit can transfer data between DSP and host computer. In the paper, some key technologies are also introduced which make the whole system work efficiently. Because of the characters referred above, the hardware is a perfect flat for multi-channel data collection, image processing, and other signal processing with high performance and adaptability. The application section of this paper presents how this hardware is adapted for the biometric identification system with high identification precision. The result reveals that this hardware is easy to interface with a CMOS imager and is capable of carrying out complex biometric identification algorithms, which require real-time process.

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

NASA Technical Reports Server (NTRS)

Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

2018-01-01

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Investigation of Current Spike Phenomena During Heavy Ion Irradiation of NAND Flash Memories

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Berg, Melanie; Friendlich, Mark; Wilcox, Ted; Seidleck, Christina; LaBel, Kenneth A.; Irom, Farokh; Buchner, Steven P.; McMorrow, Dale; Mavis, David G.;

Multi-Level Bitmap Indexes for Flash Memory Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Kesheng; Madduri, Kamesh; Canon, Shane

2010-07-23

Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data atmore » the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.« less

75 FR 11909 - In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-12

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission Determination Not To Review an Initial..., and the [[Page 11910

A Semi-Preemptive Garbage Collector for Solid State Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Junghee; Kim, Youngjae; Shipman, Galen M

2011-01-01

NAND flash memory is a preferred storage media for various platforms ranging from embedded systems to enterprise-scale systems. Flash devices do not have any mechanical moving parts and provide low-latency access. They also require less power compared to rotating media. Unlike hard disks, flash devices use out-of-update operations and they require a garbage collection (GC) process to reclaim invalid pages to create free blocks. This GC process is a major cause of performance degradation when running concurrently with other I/O operations as internal bandwidth is consumed to reclaim these invalid pages. The invocation of the GC process is generally governedmore » by a low watermark on free blocks and other internal device metrics that different workloads meet at different intervals. This results in I/O performance that is highly dependent on workload characteristics. In this paper, we examine the GC process and propose a semi-preemptive GC scheme that can preempt on-going GC processing and service pending I/O requests in the queue. Moreover, we further enhance flash performance by pipelining internal GC operations and merge them with pending I/O requests whenever possible. Our experimental evaluation of this semi-preemptive GC sheme with realistic workloads demonstrate both improved performance and reduced performance variability. Write-dominant workloads show up to a 66.56% improvement in average response time with a 83.30% reduced variance in response time compared to the non-preemptive GC scheme.« less

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

PubMed

Liu, Chunsen; Yan, Xiao; Wang, Jianlu; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-05-01

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe 2 and a 3D Al 2 O 3 /HfO 2 /Al 2 O 3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe 2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holbert, Keith E.; Clark, Lawrence T.

Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance tomore » megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration board exhibits radiation resilience to over 200 krad. Furthermore, our ASIC microprocessor using RHBD techniques was shown to be fully functional after an exposure of 2.5 Mrad whereas the COTS microcontroller units failed catastrophically at <100 krad. The methods developed in this work can facilitate the long-term viability of radiation-hard robotic systems, thereby avoiding obsolescence issues. As a case in point, the nuclear industry with its low purchasing power does not drive the semiconductor industry strategic plans, and the rapid advancements in electronics technology can leave legacy systems stranded.« less

PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

PubMed

Rizvi, Sanam Shahla; Chung, Tae-Sun

2010-01-01

Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

Nonvolatile Memory Technology for Space Applications

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

2010-01-01

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Takeshi; Muraguchi, Masakazu; Seo, Moon-Sik; Park, Sung-kye; Endoh, Tetsuo

2014-01-01

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10 × 1012 cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10 × 1012 cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

76 FR 13207 - In the Matter of Certain Flash Memory and Products Containing Same Notice of Request for...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-10

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-685] In the Matter of Certain Flash Memory and Products Containing Same Notice of Request for Statements on the Public Interest Section 337 of the Tariff Act of 1930 provides that if the Commission finds a violation it shall exclude the...

Review of radiation effects on ReRAM devices and technology

NASA Astrophysics Data System (ADS)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

Radiation Tests on 2Gb NAND Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, Duc N.; Guertin, Steven M.; Patterson, J. D.

2006-01-01

We report on SEE and TID tests of highly scaled Samsung 2Gbits flash memories. Both in-situ and biased interval irradiations were used to characterize the response of the total accumulated dose failures. The radiation-induced failures can be categorized as followings: single event upset (SEU) read errors in biased and unbiased modes, write errors, and single-event-functional-interrupt (SEFI) failures.

Quantitative Analysis of Signaling Networks across Differentially Embedded Tumors Highlights Interpatient Heterogeneity in Human Glioblastoma

PubMed Central

2015-01-01

Glioblastoma multiforme (GBM) is the most aggressive malignant primary brain tumor, with a dismal mean survival even with the current standard of care. Although in vitro cell systems can provide mechanistic insight into the regulatory networks governing GBM cell proliferation and migration, clinical samples provide a more physiologically relevant view of oncogenic signaling networks. However, clinical samples are not widely available and may be embedded for histopathologic analysis. With the goal of accurately identifying activated signaling networks in GBM tumor samples, we investigated the impact of embedding in optimal cutting temperature (OCT) compound followed by flash freezing in LN2 vs immediate flash freezing (iFF) in LN2 on protein expression and phosphorylation-mediated signaling networks. Quantitative proteomic and phosphoproteomic analysis of 8 pairs of tumor specimens revealed minimal impact of the different sample processing strategies and highlighted the large interpatient heterogeneity present in these tumors. Correlation analyses of the differentially processed tumor sections identified activated signaling networks present in selected tumors and revealed the differential expression of transcription, translation, and degradation associated proteins. This study demonstrates the capability of quantitative mass spectrometry for identification of in vivo oncogenic signaling networks from human tumor specimens that were either OCT-embedded or immediately flash-frozen. PMID:24927040

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Research about Memory Detection Based on the Embedded Platform

NASA Astrophysics Data System (ADS)

Sun, Hao; Chu, Jian

As is known to us all, the resources of memory detection of the embedded systems are very limited. Taking the Linux-based embedded arm as platform, this article puts forward two efficient memory detection technologies according to the characteristics of the embedded software. Especially for the programs which need specific libraries, the article puts forwards portable memory detection methods to help program designers to reduce human errors,improve programming quality and therefore make better use of the valuable embedded memory resource.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

A hot hole-programmed and low-temperature-formed SONOS flash memory

PubMed Central

2013-01-01

In this study, a high-performance TixZrySizO flash memory is demonstrated using a sol–gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600°C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 μs with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 106 s with only 5% (at 85°C) and 10% (at 125°C) charge loss. The barrier height of the TixZrySizO film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-κ sol–gel film. PMID:23899050

Research on memory management in embedded systems

NASA Astrophysics Data System (ADS)

Huang, Xian-ying; Yang, Wu

2005-12-01

Memory is a scarce resource in embedded system due to cost and size. Thus, applications in embedded systems cannot use memory randomly, such as in desktop applications. However, data and code must be stored into memory for running. The purpose of this paper is to save memory in developing embedded applications and guarantee running under limited memory conditions. Embedded systems often have small memory and are required to run a long time. Thus, a purpose of this study is to construct an allocator that can allocate memory effectively and bear a long-time running situation, reduce memory fragmentation and memory exhaustion. Memory fragmentation and exhaustion are related to the algorithm memory allocated. Static memory allocation cannot produce fragmentation. In this paper it is attempted to find an effective allocation algorithm dynamically, which can reduce memory fragmentation. Data is the critical part that ensures an application can run regularly, which takes up a large amount of memory. The amount of data that can be stored in the same size of memory is relevant with the selected data structure. Skills for designing application data in mobile phone are explained and discussed also.

Assessing Server Fault Tolerance and Disaster Recovery Implementation in Thin Client Architectures

DTIC Science & Technology

2007-09-01

server • Windows 2003 server Processor AMD Geode GX Memory 512MB Flash/256MB DDR RAM I/O/Peripheral Support • VGA-type video output (DB-15...2000 Advanced Server Processor AMD Geode NX 1500 Memory • 256MB or 512MB or 1GB DDR SDRAM • 1GB or 512MB Flash I/O/Peripheral Support • SiS741 GX

TID and SEE Response of an Advanced Samsung 4G NAND Flash Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Friendlich, M.; Howard, J. W.; Berg, M. D.; Kim, H. S.; Irwin, T. L.; LaBel, K. A.

2007-01-01

Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment.

Data Movement Dominates: Final Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, Bruce L.

Over the past three years in this project, what we have observed is that the primary reason for data movement in large-scale systems is that the per-node capacity is not large enough—i.e., one of the solutions to the data-movement problem (certainly not the only solution that is required, but a significant one nonetheless) is to increase per-node capacity so that inter-node traffic is reduced. This unfortunately is not as simple as it sounds. Today’s main memory systems for datacenters, enterprise computing systems, and supercomputers, fail to provide high per-socket capacity [Dirik & Jacob 2009; Cooper-Balis et al. 2012], except atmore » extremely high price points (factors of 10–100x the cost/bit of consumer main-memory systems) [Stokes 2008]. The reason is that our choice of technology for today’s main memory systems—i.e., DRAM, which we have used as a main-memory technology since the 1970s [Jacob et al. 2007]—can no longer keep up with our needs for density and price per bit. Main memory systems have always been built from the cheapest, densest, lowest-power memory technology available, and DRAM is no longer the cheapest, the densest, nor the lowest-power storage technology out there. It is now time for DRAM to go the way that SRAM went: move out of the way for a cheaper, slower, denser storage technology, and become a cache instead. This inflection point has happened before, in the context of SRAM yielding to DRAM. There was once a time that SRAM was the storage technology of choice for all main memories [Tomasulo 1967; Thornton 1970; Kidder 1981]. However, once DRAM hit volume production in the 1970s and 80s, it supplanted SRAM as a main memory technology because it was cheaper, and it was denser. It also happened to be lower power, but that was not the primary consideration of the day. At the time, it was recognized that DRAM was much slower than SRAM, but it was only at the supercomputer level (For instance the Cray X-MP in the 1980s and its follow-on, the Cray Y-MP, in the 1990s) that could one afford to build ever- larger main memories out of SRAM—the reasoning for moving to DRAM was that an appropriately designed memory hierarchy, built of DRAM as main memory and SRAM as a cache, would approach the performance of SRAM, at the price-per-bit of DRAM [Mashey 1999]. Today it is quite clear that, were one to build an entire multi-gigabyte main memory out of SRAM instead of DRAM, one could improve the performance of almost any computer system by up to an order of magnitude—but this option is not even considered, because to build that system would be prohibitively expensive. It is now time to revisit the same design choice in the context of modern technologies and modern systems. For reasons both technical and economic, we can no longer afford to build ever-larger main memory systems out of DRAM. Flash memory, on the other hand, is significantly cheaper and denser than DRAM and therefore should take its place. While it is true that flash is significantly slower than DRAM, one can afford to build much larger main memories out of flash than out of DRAM, and we show that an appropriately designed memory hierarchy, built of flash as main memory and DRAM as a cache, will approach the performance of DRAM, at the price-per-bit of flash. In our studies as part of this project, we have investigated Non-Volatile Main Memory (NVMM), a new main-memory architecture for large-scale computing systems, one that is specifically designed to address the weaknesses described previously. In particular, it provides the following features: non-volatility: The bulk of the storage is comprised of NAND flash, and in this organization DRAM is used only as a cache, not as main memory. Furthermore, the flash is journaled, which means that operations such as checkpoint/restore are already built into the system. 1+ terabytes of storage per socket: SSDs and DRAM DIMMs have roughly the same form factor (several square inches of PCB surface area), and terabyte SSDs are now commonplace. performance approaching that of DRAM: DRAM is used as a cache to the flash system. price-per-bit approaching that of NAND: Flash is currently well under $0.50 per gigabyte; DDR3 SDRAM is currently just over $10 per gigabyte [Newegg 2014]. Even today, one can build an easily affordable main memory system with a terabyte or more of NAND storage per CPU socket (which would be extremely expensive were one to use DRAM), and our cycle- accurate, full-system experiments show that this can be done at a performance point that lies within a factor of two of DRAM.« less

Saccades to remembered targets: the effects of smooth pursuit and illusory stimulus motion

NASA Technical Reports Server (NTRS)

Zivotofsky, A. Z.; Rottach, K. G.; Averbuch-Heller, L.; Kori, A. A.; Thomas, C. W.; Dell'Osso, L. F.; Leigh, R. J.

1996-01-01

1. Measurements were made in four normal human subjects of the accuracy of saccades to remembered locations of targets that were flashed on a 20 x 30 deg random dot display that was either stationary or moving horizontally and sinusoidally at +/-9 deg at 0.3 Hz. During the interval between the target flash and the memory-guided saccade, the "memory period" (1.4 s), subjects either fixated a stationary spot or pursued a spot moving vertically sinusoidally at +/-9 deg at 0.3 Hz. 2. When saccades were made toward the location of targets previously flashed on a stationary background as subjects fixated the stationary spot, median saccadic error was 0.93 deg horizontally and 1.1 deg vertically. These errors were greater than for saccades to visible targets, which had median values of 0.59 deg horizontally and 0.60 deg vertically. 3. When targets were flashed as subjects smoothly pursued a spot that moved vertically across the stationary background, median saccadic error was 1.1 deg horizontally and 1.2 deg vertically, thus being of similar accuracy to when targets were flashed during fixation. In addition, the vertical component of the memory-guided saccade was much more closely correlated with the "spatial error" than with the "retinal error"; this indicated that, when programming the saccade, the brain had taken into account eye movements that occurred during the memory period. 4. When saccades were made to targets flashed during attempted fixation of a stationary spot on a horizontally moving background, a condition that produces a weak Duncker-type illusion of horizontal movement of the primary target, median saccadic error increased horizontally to 3.2 deg but was 1.1 deg vertically. 5. When targets were flashed as subjects smoothly pursued a spot that moved vertically on the horizontally moving background, a condition that induces a strong illusion of diagonal target motion, median saccadic error was 4.0 deg horizontally and 1.5 deg vertically; thus the horizontal error was greater than under any other experimental condition. 6. In most trials, the initial saccade to the remembered target was followed by additional saccades while the subject was still in darkness. These secondary saccades, which were executed in the absence of visual feedback, brought the eye closer to the target location. During paradigms involving horizontal background movement, these corrections were more prominent horizontally than vertically. 7. Further measurements were made in two subjects to determine whether inaccuracy of memory-guided saccades, in the horizontal plane, was due to mislocalization at the time that the target flashed, misrepresentation of the trajectory of the pursuit eye movement during the memory period, or both. 8. The magnitude of the saccadic error, both with and without corrections made in darkness, was mislocalized by approximately 30% of the displacement of the background at the time that the target flashed. The magnitude of the saccadic error also was influenced by net movement of the background during the memory period, corresponding to approximately 25% of net background movement for the initial saccade and approximately 13% for the final eye position achieved in darkness. 9. We formulated simple linear models to test specific hypotheses about which combinations of signals best describe the observed saccadic amplitudes. We tested the possibilities that the brain made an accurate memory of target location and a reliable representation of the eye movement during the memory period, or that one or both of these was corrupted by the illusory visual stimulus. Our data were best accounted for by a model in which both the working memory of target location and the internal representation of the horizontal eye movements were corrupted by the illusory visual stimulus. We conclude that extraretinal signals played only a minor role, in comparison with visual estimates of the direction of gaze, in planning eye movements to remembered targ.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

Radiation Effects on Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Guertin, S.; Swift, G. M.; Johnston, A. H.

1998-01-01

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

Interactions of numerical and temporal stimulus characteristics on the control of response location by brief flashes of light.

PubMed

Fetterman, J Gregor; Killeen, P Richard

2011-09-01

Pigeons pecked on three keys, responses to one of which could be reinforced after 3 flashes of the houselight, to a second key after 6, and to a third key after 12. The flashes were arranged according to variable-interval schedules. Response allocation among the keys was a function of the number of flashes. When flashes were omitted, transitions occurred very late. Increasing flash duration produced a leftward shift in the transitions along a number axis. Increasing reinforcement probability produced a leftward shift, and decreasing reinforcement probability produced a rightward shift. Intermixing different flash rates within sessions separated allocations: Faster flash rates shifted the functions sooner in real time, but later in terms of flash count, and conversely for slower flash rates. A model of control by fading memories of number and time was proposed.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Effects of botanicals and combined hormone therapy on cognition in postmenopausal women.

PubMed

Maki, Pauline M; Rubin, Leah H; Fornelli, Deanne; Drogos, Lauren; Banuvar, Suzanne; Shulman, Lee P; Geller, Stacie E

2009-01-01

The aim of this study was to characterize the effects of red clover, black cohosh, and combined hormone therapy on cognitive function in comparison to placebo in women with moderate to severe vasomotor symptoms. In a phase II randomized, double-blind, placebo-controlled study, 66 midlife women (of 89 from a parent study; mean age, 53 y) with 35 or more weekly hot flashes were randomized to receive red clover (120 mg), black cohosh (128 mg), 0.625 mg conjugated equine estrogens plus 2.5 mg medroxyprogesterone acetate (CEE/MPA), or placebo. Participants completed measures of verbal memory (primary outcome) and other cognitive measures (secondary outcomes) before and during the 12th treatment month. A subset of 19 women completed objective, physiological measures of hot flashes using ambulatory skin conductance monitors. Neither of the botanical treatments had an impact on any cognitive measure. Compared with placebo, CEE/MPA led to a greater decline in verbal learning (one of five verbal memory measures). This effect just missed statistical significance (P = 0.057) in unadjusted analyses but reached significance (P = 0.02) after adjusting for vasomotor symptoms. Neither of the botanical treatment groups showed a change in verbal memory that differed from the placebo group (Ps > 0.28), even after controlling for improvements in hot flashes. In secondary outcomes, CEE/MPA led to a decrease in immediate digit recall and an improvement in letter fluency. Only CEE/MPA significantly reduced objective hot flashes. Results indicate that a red clover (phytoestrogen) supplement or black cohosh has no effects on cognitive function. CEE/MPA reduces objective hot flashes but worsens some aspects of verbal memory.

Effects of Botanicals and Combined Hormone Therapy on Cognition in Postmenopausal Women

PubMed Central

Maki, Pauline M.; Rubin, Leah H.; Fornelli, Deanne; Drogos, Lauren; Banuvar, Suzanne; Shulman, Lee P.; Geller, Stacie E.

2009-01-01

Objective To characterize the effects of red clover, black cohosh, and combined hormone therapy on cognitive function in comparison to placebo in women with moderate to severe vasomotor symptoms. Design In a Phase II randomized, double-blind, placebo-controlled study, 66 midlife women (out of 89 from a parent study; mean age=53 y) with ≥ 35 weekly hot flashes were randomized to receive red clover (120 mg), black cohosh (128 mg), CEE/MPA (0.625 mg conjugated equine estrogens plus 2.5 mg medroxyprogesterone acetate), or placebo. Participants completed measures of verbal memory (primary outcome) and other cognitive measures (secondary outcomes) before and during the 12th treatment month. A subset of 19 women completed objective, physiological measures of hot flashes using ambulatory skin conductance monitors. Results There was no impact of either of the botanical treatments on any cognitive measure. Compared to placebo, CEE/MPA led to greater decline in verbal learning (one of five verbal memory measures). This effect just missed statistical significance (p=0.057) in unadjusted analyses, but reached significance (p=.02) after adjusting for vasomotor symptoms. Neither botanical treatment group showed a change in verbal memory that differed from the placebo group (ps>0.28), even after controlling for improvements in hot flashes. In secondary outcomes, CEE/MPA led to a decrease in immediate digit recall and an improvement in letter fluency. Only CEE/MPA significantly reduced objective hot flashes. Conclusions Results indicate no effects of a red clover (phytoestrogen) supplement or black cohosh on cognitive function. CEE/MPA reduces objective hot flashes but worsens some aspects of verbal memory. PMID:19590458

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

NASA Astrophysics Data System (ADS)

Tomita, Toshihiro; Miyaji, Kousuke

2015-04-01

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

NASA Astrophysics Data System (ADS)

Guo, Jiarong

2017-04-01

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 °C. Project supported by the National Natural Science Fundation of China (No. 61376028).

Soft-error tolerance and energy consumption evaluation of embedded computer with magnetic random access memory in practical systems using computer simulations

NASA Astrophysics Data System (ADS)

Nebashi, Ryusuke; Sakimura, Noboru; Sugibayashi, Tadahiko

2017-08-01

We evaluated the soft-error tolerance and energy consumption of an embedded computer with magnetic random access memory (MRAM) using two computer simulators. One is a central processing unit (CPU) simulator of a typical embedded computer system. We simulated the radiation-induced single-event-upset (SEU) probability in a spin-transfer-torque MRAM cell and also the failure rate of a typical embedded computer due to its main memory SEU error. The other is a delay tolerant network (DTN) system simulator. It simulates the power dissipation of wireless sensor network nodes of the system using a revised CPU simulator and a network simulator. We demonstrated that the SEU effect on the embedded computer with 1 Gbit MRAM-based working memory is less than 1 failure in time (FIT). We also demonstrated that the energy consumption of the DTN sensor node with MRAM-based working memory can be reduced to 1/11. These results indicate that MRAM-based working memory enhances the disaster tolerance of embedded computers.

SSD Market Overview

NASA Astrophysics Data System (ADS)

Wong, G.

The unparalleled cost and form factor advantages of NAND flash memory has driven 35 mm photographic film, floppy disks and one-inch hard drives to extinction. Due to its compelling price/performance characteristics, NAND Flash memory is now expanding its reach into the once-exclusive domain of hard disk drives and DRAM in the form of Solid State Drives (SSDs). Driven by the proliferation of thin and light mobile devices and the need for near-instantaneous accessing and sharing of content through the cloud, SSDs are expected to become a permanent fixture in the computing infrastructure.

Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

NASA Astrophysics Data System (ADS)

Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

2017-08-01

A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller.

PubMed

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADmicroC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62 kbytes of flash memory, 8 kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40 bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100 ns and a minimum time delay between successive events of approximately 9 micros. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller

NASA Astrophysics Data System (ADS)

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADμC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62kbytes of flash memory, 8kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100ns and a minimum time delay between successive events of approximately 9μs. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

Fault-tolerant NAND-flash memory module for next-generation scientific instruments

NASA Astrophysics Data System (ADS)

Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

2015-10-01

Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

ASA-FTL: An adaptive separation aware flash translation layer for solid state drives

DOE PAGES

Xie, Wei; Chen, Yong; Roth, Philip C

2016-11-03

Here, the flash-memory based Solid State Drive (SSD) presents a promising storage solution for increasingly critical data-intensive applications due to its low latency (high throughput), high bandwidth, and low power consumption. Within an SSD, its Flash Translation Layer (FTL) is responsible for exposing the SSD’s flash memory storage to the computer system as a simple block device. The FTL design is one of the dominant factors determining an SSD’s lifespan and performance. To reduce the garbage collection overhead and deliver better performance, we propose a new, low-cost, adaptive separation-aware flash translation layer (ASA-FTL) that combines sampling, data clustering and selectivemore » caching of recency information to accurately identify and separate hot/cold data while incurring minimal overhead. We use sampling for light-weight identification of separation criteria, and our dedicated selective caching mechanism is designed to save the limited RAM resource in contemporary SSDs. Using simulations of ASA-FTL with both real-world and synthetic workloads, we have shown that our proposed approach reduces the garbage collection overhead by up to 28% and the overall response time by 15% compared to one of the most advanced existing FTLs. We find that the data clustering using a small sample size provides significant performance benefit while only incurring a very small computation and memory cost. In addition, our evaluation shows that ASA-FTL is able to adapt to the changes in the access pattern of workloads, which is a major advantage comparing to existing fixed data separation methods.« less

Optimal proximity correction: application for flash memory design

NASA Astrophysics Data System (ADS)

Chen, Y. O.; Huang, D. L.; Sung, K. T.; Chiang, J. J.; Yu, M.; Teng, F.; Chu, Lung; Rey, Juan C.; Bernard, Douglas A.; Li, Jiangwei; Li, Junling; Moroz, V.; Boksha, Victor V.

1998-06-01

Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

CD uniformity control for thick resist process

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Wang, Weihung; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2017-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked flash cell array has been proposed. In constructing 3D NAND flash memories, the higher bit number per area is achieved by increasing the number of stacked layers. Thus the so-called "staircase" patterning to form electrical connection between memory cells and word lines has become one of the primarily critical processes in 3D memory manufacture. To provide controllable critical dimension (CD) with good uniformity involving thick photo-resist has also been of particular concern for staircase patterning. The CD uniformity control has been widely investigated with relatively thinner resist associated with resolution limit dimension but thick resist coupling with wider dimension. This study explores CD uniformity control associated with thick photo-resist processing. Several critical parameters including exposure focus, exposure dose, baking condition, pattern size and development recipe, were found to strongly correlate with the thick photo-resist profile accordingly affecting the CD uniformity control. To minimize the within-wafer CD variation, the slightly tapered resist profile is proposed through well tailoring the exposure focus and dose together with optimal development recipe. Great improvements on DCD (ADI CD) and ECD (AEI CD) uniformity as well as line edge roughness were achieved through the optimization of photo resist profile.

Don’t make cache too complex: A simple probability-based cache management scheme for SSDs

PubMed Central

Cho, Sangyeun; Choi, Jongmoo

2017-01-01

Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies. However, as the flash memory stores more bits per cell, the performance and reliability of the flash memory degrade substantially. To solve this problem, a fast non-volatile memory (NVM-)based cache has been employed within SSDs to reduce the long latency required to write data. Absorbing small writes in a fast NVM cache can also reduce the number of flash memory erase operations. To maximize the benefits of an NVM cache, it is important to increase the NVM cache utilization. In this paper, we propose and study ProCache, a simple NVM cache management scheme, that makes cache-entrance decisions based on random probability testing. Our scheme is motivated by the observation that frequently written hot data will eventually enter the cache with a high probability, and that infrequently accessed cold data will not enter the cache easily. Owing to its simplicity, ProCache is easy to implement at a substantially smaller cost than similar previously studied techniques. We evaluate ProCache and conclude that it achieves comparable performance compared to a more complex reference counter-based cache-management scheme. PMID:28358897

Don't make cache too complex: A simple probability-based cache management scheme for SSDs.

PubMed

Baek, Seungjae; Cho, Sangyeun; Choi, Jongmoo

2017-01-01

Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies. However, as the flash memory stores more bits per cell, the performance and reliability of the flash memory degrade substantially. To solve this problem, a fast non-volatile memory (NVM-)based cache has been employed within SSDs to reduce the long latency required to write data. Absorbing small writes in a fast NVM cache can also reduce the number of flash memory erase operations. To maximize the benefits of an NVM cache, it is important to increase the NVM cache utilization. In this paper, we propose and study ProCache, a simple NVM cache management scheme, that makes cache-entrance decisions based on random probability testing. Our scheme is motivated by the observation that frequently written hot data will eventually enter the cache with a high probability, and that infrequently accessed cold data will not enter the cache easily. Owing to its simplicity, ProCache is easy to implement at a substantially smaller cost than similar previously studied techniques. We evaluate ProCache and conclude that it achieves comparable performance compared to a more complex reference counter-based cache-management scheme.

Printing Electronic Components from Copper-Infused Ink and Thermoplastic Mediums

NASA Astrophysics Data System (ADS)

Flowers, Patrick F.

The demand for printable electronics has sharply increased in recent years and is projected to continue to rise. Unfortunately, electronic materials which are suitable for desired applications while being compatible with available printing techniques are still often lacking. This thesis addresses two such challenging areas. In the realm of two-dimensional ink-based printing of electronics, a major barrier to the realization of printable computers that can run programs is the lack of a solution-coatable non-volatile memory with performance metrics comparable to silicon-based devices. To address this deficiency, I developed a nonvolatile memory based on Cu-SiO2 core-shell nanowires that can be printed from solution and exhibits on-off ratios of 106, switching speeds of 50 ns, a low operating voltage of 2 V, and operates for at least 104 cycles without failure. Each of these metrics is similar to or better than Flash memory (the write speed is 20 times faster than Flash). Memory architectures based on the individual memory cells demonstrated here could enable the printing of the more complex, embedded computing devices that are expected to make up an internet of things. Recently, the exploration of three-dimensional printing techniques to fabricate electronic materials began. A suitable general-purpose conductive thermoplastic filament was not available, however. In this work I examine the current state of conductive thermoplastic filaments, including a newly-released highly conductive filament that my lab has produced which we call Electrifi. I focus on the use of dual-material fused filament fabrication (FFF) to 3D print electronic components (conductive traces, resistors, capacitors, inductors) and circuits (a fully-printed high-pass filter). The resistivity of traces printed from conductive thermoplastic filaments made with carbon-black, graphene, and copper as conductive fillers was found to be 12, 0.78, and 0.014 ohm cm, respectively, enabling the creation of resistors with resistances spanning 3 orders of magnitude. The carbon black and graphene filaments were brittle and fractured easily, but the copper-based filament could be bent at least 500 times with little change in its resistance. Impedance measurements made on the thermoplastic filaments demonstrate that the copper-based filament had an impedance similar to a conductive PCB trace at 1 MHz. Dual material 3D printing was used to fabricate a variety of inductors and capacitors with properties that could be predictably tuned by modifying either the geometry of the components, or the materials used to fabricate the components. These resistors, capacitors, and inductors were combined to create a fully 3D printed high-pass filter with properties comparable to its conventional counterparts. The relatively low impedance of the copper-based filament enable its use to 3D print a receiver coil for wireless power transfer. We also demonstrate the ability to embed and connect surface mounted components in 3D printed objects with a low-cost ($1,000 in parts), open source dual-material 3D printer. This work thus demonstrates the potential for FFF 3D printing to create complex, three-dimensional circuits composed of either embedded or fully-printed electronic components.

Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

NASA Astrophysics Data System (ADS)

Kim, Do-Bin; Kwon, Dae Woong; Kim, Seunghyun; Lee, Sang-Ho; Park, Byung-Gook

2018-02-01

To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.

Flash drive memory apparatus and method

NASA Technical Reports Server (NTRS)

Hinchey, Michael G. (Inventor)

2010-01-01

A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

FPGA-based RF spectrum merging and adaptive hopset selection

NASA Astrophysics Data System (ADS)

McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

The future of memory

NASA Astrophysics Data System (ADS)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy

NASA Astrophysics Data System (ADS)

Huo, Zongliang; Jin, Lei; Han, Yulong; Li, Xinkai; Ye, Tianchun; Liu, Ming

2015-01-01

The influence of post-deposition annealing (PDA) temperature condition on charge distribution behavior of HfO2 thin films was systematically investigated by various-temperature Kelvin probe force microscopy technology. Contact potential difference profiles demonstrated that charge storage capability shrinks with decreasing annealing temperature from 1,000 to 500 °C and lower. Compared to 1,000 °C PDA, it was found that 500 °C PDA causes deeper effective trap energy level, suppresses lateral charge spreading, and improves the retention characteristics. It is concluded that low-temperature PDA can be adopted in 3D HfO2-based charge trap flash memory to improve the thermal treatment compatibility of the bottom peripheral logic and upper memory arrays.

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

Portable Electromyograph

NASA Technical Reports Server (NTRS)

De Luca, Gianluca; De Luca, Carlo J.; Bergman, Per

2004-01-01

A portable electronic apparatus records electromyographic (EMG) signals in as many as 16 channels at a sampling rate of 1,024 Hz in each channel. The apparatus (see figure) includes 16 differential EMG electrodes (each electrode corresponding to one channel) with cables and attachment hardware, reference electrodes, an input/output-and-power-adapter unit, a 16-bit analog-to-digital converter, and a hand-held computer that contains a removable 256-MB flash memory card. When all 16 EMG electrodes are in use, full-bandwidth data can be recorded in each channel for as long as 8 hours. The apparatus is powered by a battery and is small enough that it can be carried in a waist pouch. The computer is equipped with a small screen that can be used to display the incoming signals on each channel. Amplitude and time adjustments of this display can be made easily by use of touch buttons on the screen. The user can also set up a data-acquisition schedule to conform to experimental protocols or to manage battery energy and memory efficiently. Once the EMG data have been recorded, the flash memory card is removed from the EMG apparatus and placed in a flash-memory- card-reading external drive unit connected to a personal computer (PC). The PC can then read the data recorded in the 16 channels. Preferably, before further analysis, the data should be stored in the hard drive of the PC. The data files are opened and viewed on the PC by use of special- purpose software. The software for operation of the apparatus resides in a random-access memory (RAM), with backup power supplied by a small internal lithium cell. A backup copy of this software resides on the flash memory card. In the event of loss of both main and backup battery power and consequent loss of this software, the backup copy can be used to restore the RAM copy after power has been restored. Accessories for this device are also available. These include goniometers, accelerometers, foot switches, and force gauges.

Checkpoint-Restart in User Space

DOE Office of Scientific and Technical Information (OSTI.GOV)

CRUISE implements a user-space file system that stores data in main memory and transparently spills over to other storage, like local flash memory or the parallel file system, as needed. CRUISE also exposes file contents fo remote direct memory access, allowing external tools to copy files to the parallel file system in the background with reduced CPU interruption.

Driving platform for OLED lighting investigations

NASA Astrophysics Data System (ADS)

Vogel, Uwe; Elgner, Andreas; Kreye, Daniel; Amelung, Jörg; Scholles, Michael

2006-08-01

OLED technology may be excellently suitable for lighting applications by combining high efficiency, cost effective manufacturing and the use of low cost materials. Certain issues remain to be solved so far, including OLED brightness, color, lifetime, large area uniformity and encapsulation. Another aspect, that might be capable in addressing some of the mentioned issues, is OLED lighting electrical driving. We report on the design of a driving platform for OLED lighting test panels or substrates. It is intended for being a test environment for lighting substrates as well as demonstration/presentation environment. It is based on a 128-channel passive-matrix driver/controller ASIC OC2. Its key component is an MSP430-compatible 16-bit micro-controller core including embedded Flash memory (program), EEPROM (parameter), and RAM (data memory). A significant feature of the device is an electronic approach for improving the lifetime/uniformity behavior of connected OLED. The embedded micro-controller is the key to the high versatility of OC2, since by firmware modification it can be adapted to various applications and conditions. Here its application for an OLED lighting driving platform is presented. Major features of this platform are PC-control mode (via USB interface), stand-alone mode (no external control necessary, just power supply), on-board OLED panel parameter storage, flat geometry of OLED lighting panel carrier (board), AC and DC driving regimes, adjustable reverse voltage, dedicated user SW (PC/Windows-based), sub-tile patterning and single sub-tile control, combination of multiple channels for increasing driving current. This publication contains results of the project "High Brightness OLEDs for ICT & Next Generation Lighting Applications" (OLLA), funded by the European Commission.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Kim, Hak; Phan, Anthony; Seidleck, Christina; LaBel, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

NASA Technical Reports Server (NTRS)

Swift, G.

2002-01-01

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Tunable bandgap energy of fluorinated nanocrystals for flash memory applications produced by low-damage plasma treatment.

PubMed

Huang, Chi-Hsien; Lin, Chih-Ting; Wang, Jer-Chyi; Chou, Chien; Ye, Yu-Ren; Cheng, Bing-Ming; Lai, Chao-Sung

2012-11-30

A plasma system with a complementary filter to shield samples from damage during tetrafluoromethane (CF(4)) plasma treatment was proposed in order to incorporate fluorine atoms into gadolinium oxide nanocrystals (Gd(2)O(3)-NCs) for flash memory applications. X-ray photoelectron spectroscopy confirmed that fluorine atoms were successfully introduced into the Gd(2)O(3)-NCs despite the use of a filter in the plasma-enhanced chemical vapour deposition system to shield against several potentially damaging species. The number of incorporated fluorine atoms can be controlled by varying the treatment time. The optimized memory window of the resulting flash memory devices was twice that of devices treated by a filterless system because more fluorine atoms were incorporated into the Gd(2)O(3)-NCs film with very little damage. This enlarged the bandgap energy from 5.48 to 6.83 eV, as observed by ultraviolet absorption measurements. This bandgap expansion can provide a large built-in electric field that allows more charges to be stored in the Gd(2)O(3)-NCs. The maximum improvement in the retention characteristic was >60%. Because plasma damage during treatment is minimal, maximum fluorination can be achieved. The concept of simply adding a filter to a plasma system to prevent plasma damage exhibits great promise for functionalization or modification of nanomaterials for advanced nanoelectronics while introducing minimal defects.

Microdose Induced Data Loss on Floating Gate Memories

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Nguyen, Duc M.; Patterson, Jeffrey D.

2006-01-01

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

High Performance Data Transfer for Distributed Data Intensive Sciences

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fang, Chin; Cottrell, R 'Les' A.; Hanushevsky, Andrew B.

We report on the development of ZX software providing high performance data transfer and encryption. The design scales in: computation power, network interfaces, and IOPS while carefully balancing the available resources. Two U.S. patent-pending algorithms help tackle data sets containing lots of small files and very large files, and provide insensitivity to network latency. It has a cluster-oriented architecture, using peer-to-peer technologies to ease deployment, operation, usage, and resource discovery. Its unique optimizations enable effective use of flash memory. Using a pair of existing data transfer nodes at SLAC and NERSC, we compared its performance to that of bbcp andmore » GridFTP and determined that they were comparable. With a proof of concept created using two four-node clusters with multiple distributed multi-core CPUs, network interfaces and flash memory, we achieved 155Gbps memory-to-memory over a 2x100Gbps link aggregated channel and 70Gbps file-to-file with encryption over a 5000 mile 100Gbps link.« less

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

NASA Astrophysics Data System (ADS)

Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

2011-10-01

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer. In comparison to a memory capacitor with a single HfO2 trapping layer, the erase speed of a memory capacitor with a stacked HfO2/Ta2O5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔVFB = 4 V, the device with a stacked HfO2/Ta2O5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO2/Ta2O5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application.

Modeling of SONOS Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

2011-01-01

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

Non-Volatile Memory Technology Symposium 2001: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Daud, Taher; Strauss, Karl

2001-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

SONOS Nonvolatile Memory Cell Programming Characteristics

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

NEW EPICS/RTEMS IOC BASED ON ALTERA SOC AT JEFFERSON LAB

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, Jianxun; Seaton, Chad; Allison, Trent L.

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA is being designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 Hard Processor System (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via U-Boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDR3 SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications atmore » runtime. U-Boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run RTEMS and EPICS. The first design of the SoC IOC will be compatible with Jefferson Lab’s current PC104 IOCs, which have been running in CEBAF 10 years. The next design would be mounting in a chassis and connected to a daughter card via standard HSMC connectors. This standard SoC IOC will become the next generation of low-level IOC for the accelerator controls at Jefferson Lab.« less

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

DTIC Science & Technology

2010-07-22

dependent , providing a natural bandwidth match between compute cores and the memory subsystem. • High Bandwidth Dcnsity. Waveguides crossing the chip...simulate this memory access architecture on a 2S6-core chip with a concentrated 64-node network lIsing detailed traces of high-performance embedded...memory modulcs, wc placc memory access poi nts (MAPs) around the pcriphery of the chip connected to thc nctwork. These MAPs, shown in Figure 4, contain

Sentinel 2 MMFU: The first European Mass Memory System Based on NAND-Flash Storage Technology

NASA Astrophysics Data System (ADS)

Staehle, M.; Cassel, M.; Lonsdorfer, U.; Gliem, F.; Walter, D.; Fichna, T.

2011-08-01

Sentinel-2 is the multispectral optical mission of the EU-ESA GMES (Global Monitoring for Environment and Security) program, currently under development by Astrium-GmbH in Friedrichshafen (Germany) for a launch in 2013. The mission features a 490 Mbit/s optical sensor operating at high duty cycles, requiring in turn a large 2.4 Tbit on-board storage capacity.The required storage capacity motivated the selection of the NAND-Flash technology which was already secured by a lengthy period (2004-2009) of detailed testing, analysis and qualification by Astrium GmbH, IDA and ESTEC. The mass memory system is currently being realized by Astrium GmbH.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond L.; Kim, Hak; Phan, Anthony; Seidleck, Christina; Label, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

NASA Astrophysics Data System (ADS)

Liu, Yu-Heng; Jiang, Cheng-Min; Lin, Hsiao-Yi; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan

2017-07-01

We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport.

The flash memory battle: How low can we go?

NASA Astrophysics Data System (ADS)

van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

2008-03-01

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

A light writable microfluidic "flash memory": optically addressed actuator array with latched operation for microfluidic applications.

PubMed

Hua, Zhishan; Pal, Rohit; Srivannavit, Onnop; Burns, Mark A; Gulari, Erdogan

2008-03-01

This paper presents a novel optically addressed microactuator array (microfluidic "flash memory") with latched operation. Analogous to the address-data bus mediated memory address protocol in electronics, the microactuator array consists of individual phase-change based actuators addressed by localized heating through focused light patterns (address bus), which can be provided by a modified projector or high power laser pointer. A common pressure manifold (data bus) for the entire array is used to generate large deflections of the phase change actuators in the molten phase. The use of phase change material as the working media enables latched operation of the actuator array. After the initial light "writing" during which the phase is temporarily changed to molten, the actuated status is self-maintained by the solid phase of the actuator without power and pressure inputs. The microfluidic flash memory can be re-configured by a new light illumination pattern and common pressure signal. The proposed approach can achieve actuation of arbitrary units in a large-scale array without the need for complex external equipment such as solenoid valves and electrical modules, which leads to significantly simplified system implementation and compact system size. The proposed work therefore provides a flexible, energy-efficient, and low cost multiplexing solution for microfluidic applications based on physical displacements. As an example, the use of the latched microactuator array as "normally closed" or "normally open" microvalves is demonstrated. The phase-change wax is fully encapsulated and thus immune from contamination issues in fluidic environments.

Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok

2014-03-07

The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells aremore » formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.« less

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

A Layered Solution for Supercomputing Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grider, Gary

To solve the supercomputing challenge of memory keeping up with processing speed, a team at Los Alamos National Laboratory developed two innovative memory management and storage technologies. Burst buffers peel off data onto flash memory to support the checkpoint/restart paradigm of large simulations. MarFS adds a thin software layer enabling a new tier for campaign storage—based on inexpensive, failure-prone disk drives—between disk drives and tape archives.

Overlay degradation induced by film stress

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Luo, Shing-Ann; Yang, Mars; Yang, Elvis; Hung, Yung-Tai; Luoh, Tuung; Yang, T. H.; Chen, K. C.

2017-03-01

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn't directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

A Layered Solution for Supercomputing Storage

ScienceCinema

Grider, Gary

2018-06-13

To solve the supercomputing challenge of memory keeping up with processing speed, a team at Los Alamos National Laboratory developed two innovative memory management and storage technologies. Burst buffers peel off data onto flash memory to support the checkpoint/restart paradigm of large simulations. MarFS adds a thin software layer enabling a new tier for campaign storage—based on inexpensive, failure-prone disk drives—between disk drives and tape archives.

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

NASA Astrophysics Data System (ADS)

Choe, Byeong-In; Park, Byung-Gook; Lee, Jong-Ho

2013-06-01

The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Ho-Myoung; Kim, Hee-Dong; Kim, Tae Geun, E-mail: tgkim1@korea.ac.kr

Graphical abstract: The degradation tendency extracted by CP technique was almost the same in both the bulk-type and TFT-type cells. - Highlights: • D{sub it} is directly investigated from bulk-type and TFT-type CTF memory. • Charge pumping technique was employed to analyze the D{sub it} information. • To apply the CP technique to monitor the reliability of the 3D NAND flash. - Abstract: The energy distribution and density of interface traps (D{sub it}) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP)more » technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 10{sup 12} cm{sup −2} eV{sup −1} to 3.66 × 10{sup 13} cm{sup −2} eV{sup −1} due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for D{sub it} of the TFT-type cells was similar to those of bulk-type cells.« less

Phonological and Sensory Short-Term Memory Are Correlates and Both Affected in Developmental Dyslexia

ERIC Educational Resources Information Center

Laasonen, Marja; Virsu, Veijo; Oinonen, Suvi; Sandbacka, Mirja; Salakari, Anita; Service, Elisabet

2012-01-01

We investigated whether poor short-term memory (STM) in developmental dyslexia affects the processing of sensory stimulus sequences in addition to phonological material. STM for brief binary non-verbal stimuli (light flashes, tone bursts, finger touches, and their crossmodal combinations) was studied in 20 Finnish adults with dyslexia and 24…

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Memory Decline in Peri- and Post-menopausal Women: The Potential of Mind–Body Medicine to Improve Cognitive Performance

PubMed Central

Sliwinski, Jim R; Johnson, Aimee K; Elkins, Gary R

2014-01-01

Cognitive decline is a frequent complaint during the menopause transition and among post-menopausal women. Changes in memory correspond with diminished estrogen production. Further, many peri- and post-menopausal women report sleep concerns, depression, and hot flashes, and these factors may contribute to cognitive decline. Hormone therapy can increase estrogen but is contraindicated for many women. Mind–body medicine has been shown to have beneficial effects on sleep, mood, and hot flashes, among post-menopausal women. Further, mind–body medicine holds potential in addressing symptoms of cognitive decline post-menopause. This study proposes an initial framework for how mind–body interventions may improve cognitive performance and inform future research seeking to identify the common and specific factors associated with mind–body medicine for addressing memory decline in peri- and post-menopausal women. It is our hope that this article will eventually lead to a more holistic and integrative approach to the treatment of cognitive deficits in peri- and post-menopausal women. PMID:25125972

Evaluating the accuracy of the Wechsler Memory Scale-Fourth Edition (WMS-IV) logical memory embedded validity index for detecting invalid test performance.

PubMed

Soble, Jason R; Bain, Kathleen M; Bailey, K Chase; Kirton, Joshua W; Marceaux, Janice C; Critchfield, Edan A; McCoy, Karin J M; O'Rourke, Justin J F

2018-01-08

Embedded performance validity tests (PVTs) allow for continuous assessment of invalid performance throughout neuropsychological test batteries. This study evaluated the utility of the Wechsler Memory Scale-Fourth Edition (WMS-IV) Logical Memory (LM) Recognition score as an embedded PVT using the Advanced Clinical Solutions (ACS) for WAIS-IV/WMS-IV Effort System. This mixed clinical sample was comprised of 97 total participants, 71 of whom were classified as valid and 26 as invalid based on three well-validated, freestanding criterion PVTs. Overall, the LM embedded PVT demonstrated poor concordance with the criterion PVTs and unacceptable psychometric properties using ACS validity base rates (42% sensitivity/79% specificity). Moreover, 15-39% of participants obtained an invalid ACS base rate despite having a normatively-intact age-corrected LM Recognition total score. Receiving operating characteristic curve analysis revealed a Recognition total score cutoff of < 61% correct improved specificity (92%) while sensitivity remained weak (31%). Thus, results indicated the LM Recognition embedded PVT is not appropriate for use from an evidence-based perspective, and that clinicians may be faced with reconciling how a normatively intact cognitive performance on the Recognition subtest could simultaneously reflect invalid performance validity.

Shape memory system with integrated actuation using embedded particles

DOEpatents

Buckley, Patrick R [New York, NY; Maitland, Duncan J [Pleasant Hill, CA

2009-09-22

A shape memory material with integrated actuation using embedded particles. One embodiment provides a shape memory material apparatus comprising a shape memory material body and magnetic pieces in the shape memory material body. Another embodiment provides a method of actuating a device to perform an activity on a subject comprising the steps of positioning a shape memory material body in a desired position with regard to the subject, the shape memory material body capable of being formed in a specific primary shape, reformed into a secondary stable shape, and controllably actuated to recover the specific primary shape; including pieces in the shape memory material body; and actuating the shape memory material body using the pieces causing the shape memory material body to be controllably actuated to recover the specific primary shape and perform the activity on the subject.

Shape memory system with integrated actuation using embedded particles

DOEpatents

Buckley, Patrick R [New York, NY; Maitland, Duncan J [Pleasant Hill, CA

2012-05-29

A shape memory material with integrated actuation using embedded particles. One embodiment provides a shape memory material apparatus comprising a shape memory material body and magnetic pieces in the shape memory material body. Another embodiment provides a method of actuating a device to perform an activity on a subject comprising the steps of positioning a shape memory material body in a desired position with regard to the subject, the shape memory material body capable of being formed in a specific primary shape, reformed into a secondary stable shape, and controllably actuated to recover the specific primary shape; including pieces in the shape memory material body; and actuating the shape memory material body using the pieces causing the shape memory material body to be controllably actuated to recover the specific primary shape and perform the activity on the subject.

Shape memory system with integrated actuation using embedded particles

DOEpatents

Buckley, Patrick R.; Maitland, Duncan J.

2014-04-01

A shape memory material with integrated actuation using embedded particles. One embodiment provides a shape memory material apparatus comprising a shape memory material body and magnetic pieces in the shape memory material body. Another embodiment provides a method of actuating a device to perform an activity on a subject comprising the steps of positioning a shape memory material body in a desired position with regard to the subject, the shape memory material body capable of being formed in a specific primary shape, reformed into a secondary stable shape, and controllably actuated to recover the specific primary shape; including pieces in the shape memory material body; and actuating the shape memory material body using the pieces causing the shape memory material body to be controllably actuated to recover the specific primary shape and perform the activity on the subject.

[The P300-based brain-computer interface: presentation of the complex "flash + movement" stimuli].

PubMed

Ganin, I P; Kaplan, A Ia

2014-01-01

The P300 based brain-computer interface requires the detection of P300 wave of brain event-related potentials. Most of its users learn the BCI control in several minutes and after the short classifier training they can type a text on the computer screen or assemble an image of separate fragments in simple BCI-based video games. Nevertheless, insufficient attractiveness for users and conservative stimuli organization in this BCI may restrict its integration into real information processes control. At the same time initial movement of object (motion-onset stimuli) may be an independent factor that induces P300 wave. In current work we checked the hypothesis that complex "flash + movement" stimuli together with drastic and compact stimuli organization on the computer screen may be much more attractive for user while operating in P300 BCI. In 20 subjects research we showed the effectiveness of our interface. Both accuracy and P300 amplitude were higher for flashing stimuli and complex "flash + movement" stimuli compared to motion-onset stimuli. N200 amplitude was maximal for flashing stimuli, while for "flash + movement" stimuli and motion-onset stimuli it was only a half of it. Similar BCI with complex stimuli may be embedded into compact control systems requiring high level of user attention under impact of negative external effects obstructing the BCI control.

77 FR 74222 - Certain Dynamic Random Access Memory and NAND Flash Memory Devices and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-13

..., California; Kingston Technology Co., Inc. of Fountain Valley, California; Logitek International S.A. (``LISA...: Clint Gerdine, Esq., Office of the General Counsel, U.S. International Trade Commission, 500 E Street SW....m. to 5:15 p.m.) in the Office of the Secretary, U.S. International Trade Commission, 500 E Street...

Welding of silver nanowire networks via flash white light and UV-C irradiation for highly conductive and reliable transparent electrodes

NASA Astrophysics Data System (ADS)

Chung, Wan-Ho; Kim, Sang-Ho; Kim, Hak-Sung

2016-08-01

In this work, silver nanowire inks with hydroxypropyl methylcellulose (HPMC) binders were coated on polyethylene terephthalate (PET) substrates and welded via flash white light and ultraviolet C (UV-C) irradiation to produce highly conductive transparent electrodes. The coated silver nanowire films were firmly welded and embedded into PET substrate successfully at room temperature and under ambient conditions using an in-house flash white light welding system and UV-C irradiation. The effects of light irradiation conditions (light energy, irradiation time, pulse duration, and pulse number) on the silver nanowire networks were studied and optimized. Bending fatigue tests were also conducted to characterize the reliability of the welded transparent conductive silver nanowire films. The surfaces of the welded silver nanowire films were analyzed via scanning electron microscopy (SEM), while the transmittance of the structures was measured using a spectrophotometer. From the results, a highly conductive and transparent silver nanowire film with excellent reliability could be achieved at room temperature under ambient conditions via the combined flash white light and UV-C irradiation welding process.

Welding of silver nanowire networks via flash white light and UV-C irradiation for highly conductive and reliable transparent electrodes

PubMed Central

Chung, Wan-Ho; Kim, Sang-Ho; Kim, Hak-Sung

2016-01-01

In this work, silver nanowire inks with hydroxypropyl methylcellulose (HPMC) binders were coated on polyethylene terephthalate (PET) substrates and welded via flash white light and ultraviolet C (UV-C) irradiation to produce highly conductive transparent electrodes. The coated silver nanowire films were firmly welded and embedded into PET substrate successfully at room temperature and under ambient conditions using an in-house flash white light welding system and UV-C irradiation. The effects of light irradiation conditions (light energy, irradiation time, pulse duration, and pulse number) on the silver nanowire networks were studied and optimized. Bending fatigue tests were also conducted to characterize the reliability of the welded transparent conductive silver nanowire films. The surfaces of the welded silver nanowire films were analyzed via scanning electron microscopy (SEM), while the transmittance of the structures was measured using a spectrophotometer. From the results, a highly conductive and transparent silver nanowire film with excellent reliability could be achieved at room temperature under ambient conditions via the combined flash white light and UV-C irradiation welding process. PMID:27553755

Investigating of Memory - Colours of Intellectually Disabled Children and Virtual Game Addict Students

NASA Astrophysics Data System (ADS)

Sik Lányi, Cecília

We describe an investigation of memory colours. For this investigation Flash test software was developed. 75 observers used this test software in 4 groups: average elementary school children (aged: 8-9 years), intellectually disabled children (age: 9-15), virtual game addict university students (average age: 20) and university students who play with VR games rarely or never (average age: 20). In this pilot test we investigated the difference of memory colours of these 4 groups.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

NASA Astrophysics Data System (ADS)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

Aging changes in the female reproductive system

MedlinePlus

... Other common changes include: Menopause symptoms such as hot flashes, moodiness, headaches, and trouble sleeping Problems with short-term memory Decrease in breast tissue Lower sex drive (libido) and sexual response Increased risk of ...

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory.

PubMed

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In 2 Ga 2 ZnO 7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO 2 (blocking oxide)/p ++ -Si (control gate) substrate, where 3 nm thick atomic layer deposited Al 2 O 3 (tunneling oxide) and 5 nm thick low-pressure CVD Si 3 N 4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F ) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

NASA Astrophysics Data System (ADS)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Radiation Test Challenges for Scaled Commerical Memories

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

2007-01-01

As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

Mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Selinidis, Kosta S.; Jones, Chris; Doyle, Gary F.; Brown, Laura; Imhof, Joseph; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2011-11-01

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and the semiconductor mask replication process. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.

Fabrication of a smart air intake structure using shape memory alloy wire embedded composite

NASA Astrophysics Data System (ADS)

Jung, Beom-Seok; Kim, Min-Saeng; Kim, Ji-Soo; Kim, Yun-Mi; Lee, Woo-Yong; Ahn, Sung-Hoon

2010-05-01

Shape memory alloys (SMAs) have been actively studied in many fields utilizing their high energy density. Applying SMA wire-embedded composite to aerospace structures, such as air intake of jet engines and guided missiles, is attracting significant attention because it could generate a comparatively large actuating force. In this research, a scaled structure of SMA wire-embedded composite was fabricated for the air intake of aircraft. The structure was composed of several prestrained Nitinol (Ni-Ti) SMA wires embedded in ∩-shape glass fabric reinforced plastic (GFRP), and it was cured at room temperature for 72 h. The SMA wire-embedded GFRP could be actuated by applying electric current through the embedded SMA wires. The activation angle generated from the composite structure was large enough to make a smart air intake structure.

MRAM Technology Status

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as "spintronics." The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.

Positive effects of subliminal stimulation on memory.

PubMed

Chakalis, E; Lowe, G

1992-06-01

To assess the effect of subliminally embedded auditory material on short-term recall, 60 volunteer subjects undertook a face-name-occupation memory test before and after a 15-min. intervention. They were randomly assigned into three groups (a control group and two experimental groups) and allocated to one of the following conditions: (1) no sound, (2) supraliminal presentation of relaxing music, and (3) subliminal presentation of memory-improvement affirmations embedded in relaxing music. After intervention, only the subliminal group significantly improved their performance on recall of names.

82 FR 35991 - Certain Flash Memory Devices and Components Thereof; Notice of Commission Determination Not To...

Federal Register 2010, 2011, 2012, 2013, 2014

2017-08-02

... following respondents: SanDisk LLC of Milpitas, California; Western Digital Corporation of Irvine, California; Western Digital Technologies, Inc. of Milpitas, California; SanDisk Limited of Yokohama, Japan...

Titanium oxide nonvolatile memory device and its application

NASA Astrophysics Data System (ADS)

Wang, Wei

In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be explained by thermal dissolution model, and bipolar switching by local redox reaction model. Since it is generally agreed that the memory switching of TiOx NVM devices is based on conductive filaments, reusability of these conductive filaments becomes an intriguing issue to determine the memory device's endurance. A 1X3 cross-point test structure is built to investigate whether conductive filaments can be reused after RESET. It is found that the conductive filament is destroyed during unipolar switching, while can be reused during bipolar switching. The result is a good indication that bipolar switching should have better endurance than unipolar switching. Finally a novel application of the two-terminal resistive switching NVM devices is demonstrated. To reduce SRAM leakage power, we propose a nonvolatile SRAM cell with two back-up NVM devices. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty in this approach. Only a slight performance penalty is expected.

An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

NASA Technical Reports Server (NTRS)

Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

2001-01-01

Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

77 FR 35718 - Certain Universal Serial Bus (“USB”) Portable Storage Devices, Including USB Flash Drives and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-14

... on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons are... Sunnyvale, California; Kingston Technology Company, Inc. of Fountain Valley, California; Patriot Memory, LLC...

Total ionizing dose effect in an input/output device for flash memory

NASA Astrophysics Data System (ADS)

Liu, Zhang-Li; Hu, Zhi-Yuan; Zhang, Zheng-Xuan; Shao, Hua; Chen, Ming; Bi, Da-Wei; Ning, Bing-Xu; Zou, Shi-Chang

2011-12-01

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

A microcomputer-based daily living activity recording system.

PubMed

Matsuoka, Shingo; Yonezawa, Yoshiharu; Maki, Hiromichi; Ogawa, Hidekuni; Hahn, Allen W; Thayer, Julian F; Caldwell, W Morton

2003-01-01

A new daily living activity recording system has been developed for monitoring health conditions and living patterns, such as respiration, posture, activity/rest ratios and general activity level. The system employs a piezoelectric sensor, a dual axis accelerometer, two low-power active filters, a low-power 8-bit single chip microcomputer and a 128 MB compact flash memory. The piezoelectric sensor, whose electrical polarization voltage is produced by mechanical strain, detects body movements. Its high-frequency output components reflect body movements produced by walking and running activities, while the low frequency components are mainly respiratory. The dual axis accelerometer detects, from body X and Y tilt angles, whether the patient is standing, sitting or lying down (prone, supine, left side or right side). The detected respiratory, behavior and posture signals are stored by the compact flash memory. After recording, these data are downloaded to a desktop computer and analyzed.

Analysis of the Evaluation of a New Glucose Meter with Integrated Self-Management Software and USB Connectivity

PubMed Central

Crowe, Daniel J

2011-01-01

Glucose meter technology has not kept up with the advances that have occurred in other sectors in mobile and health care technology. A new device that combines strip-based capillary blood glucose monitoring and USB flash drive technology is evaluated in an industry-funded study in a cohort of patients and health care professionals. The expanded memory capacity of flash drives allows the software program to be stored on the device for analyzing the blood glucose readings in memory. The study analyzes the device for precision and accuracy as well as for ease of adaptability and usage. This analysis focuses on shortcomings in the design of the study and methodology in addition to features of the hardware device itself. Although the device has distinct advantages over many devices on the market, a challenge is made to device manufacturers to encourage further innovation. PMID:22027309

Mistaking the recent past for the present: false seeing by older adults.

PubMed

Jacoby, Larry L; Rogers, Chad S; Bishara, Anthony J; Shimizu, Yujiro

2012-03-01

Results of three experiments revealed that older, as compared to young, adults are more reliant on context when "seeing" a briefly flashed word that was preceded by a prime. In a congruent condition, the prime was the same word as flashed (e.g., DIRT dirt) whereas in an incongruent condition, the prime differed in a single letter from the word that was flashed (DART dirt). Following their attempt to identify the flashed word, participants were asked to report whether they had "seen" the flashed word or, instead, had responded on some other basis (knowing or guessing). Older adults showed dramatically higher false seeing by reporting the prime on incongruent trials and claiming to have seen it flashed. This was true even though a titration procedure was used to equate the performance of young and older adults on baseline trials which did not provide a biasing context. Results of Experiment 3 related age differences in false seeing to willingness to respond when given the option to withhold responses. Convergence of results with those showing higher false memory and false hearing are interpreted as evidence that older adults are less able to avoid misleading effects of context. That lessened ability may be associated with decline in frontal lobe functioning.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

The influence of thematic congruency, typicality and divided attention on memory for radio advertisements.

PubMed

Martín-Luengo, Beatriz; Luna, Karlos; Migueles, Malen

2014-01-01

We examined the effects of the thematic congruence between ads and the programme in which they are embedded. We also studied the typicality of the to-be-remembered information (high- and low-typicality elements), and the effect of divided attention in the memory for radio ad contents. Participants listened to four radio programmes with thematically congruent and incongruent ads embedded, and completed a true/false recognition test indicating the level of confidence in their answer. Half of the sample performed an additional task (divided attention group) while listening to the radio excerpts. In general, recognition memory was better for incongruent ads and low-typicality statements. Confidence in hits was higher in the undivided attention group, although there were no differences in performance. Our results suggest that the widespread idea of embedding ads into thematic-congruent programmes negatively affects memory for ads. In addition, low-typicality features that are usually highlighted by advertisers were better remembered than typical contents. Finally, metamemory evaluations were influenced by the inference that memory should be worse if we do several things at the same time.

Sounds can boost the awareness of visual events through attention without cross-modal integration.

PubMed

Pápai, Márta Szabina; Soto-Faraco, Salvador

2017-01-31

Cross-modal interactions can lead to enhancement of visual perception, even for visual events below awareness. However, the underlying mechanism is still unclear. Can purely bottom-up cross-modal integration break through the threshold of awareness? We used a binocular rivalry paradigm to measure perceptual switches after brief flashes or sounds which, sometimes, co-occurred. When flashes at the suppressed eye coincided with sounds, perceptual switches occurred the earliest. Yet, contrary to the hypothesis of cross-modal integration, this facilitation never surpassed the assumption of probability summation of independent sensory signals. A follow-up experiment replicated the same pattern of results using silent gaps embedded in continuous noise, instead of sounds. This manipulation should weaken putative sound-flash integration, although keep them salient as bottom-up attention cues. Additional results showed that spatial congruency between flashes and sounds did not determine the effectiveness of cross-modal facilitation, which was again not better than probability summation. Thus, the present findings fail to fully support the hypothesis of bottom-up cross-modal integration, above and beyond the independent contribution of two transient signals, as an account for cross-modal enhancement of visual events below level of awareness.

Development of template and mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Brooks, Cynthia; Selinidis, Kosta; Doyle, Gary; Brown, Laura; LaBrake, Dwayne; Resnick, Douglas J.; Sreenivasan, S. V.

2010-09-01

The Jet and Flash Imprint Lithography (J-FILTM)1-7 process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105 imprints. This suggests that tens of thousands of templates/masks will be required. It is not feasible to employ electronbeam patterning directly to deliver these volumes. Instead, a "master" template - created by directly patterning with an electron-beam tool - will be replicated many times with an imprint lithography tool to produce the required supply of "working" templates/masks. In this paper, we review the development of the pattern transfer process for both template and mask replicas. Pattern transfer of resolutions down to 25nm has been demonstrated for bit patterned media replication. In addition, final resolution on a semiconductor mask of 28nm has been confirmed. The early results on both etch depth and CD uniformity are promising, but more extensive work is required to characterize the pattern transfer process.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Non-volatile memory based on the ferroelectric photovoltaic effect

PubMed Central

Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

2013-01-01

The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

Out of sight but not out of mind: the neurophysiology of iconic memory in the superior temporal sulcus.

PubMed

Keysers, C; Xiao, D-K; Foldiak, P; Perrett, D I

2005-05-01

Iconic memory, the short-lasting visual memory of a briefly flashed stimulus, is an important component of most models of visual perception. Here we investigate what physiological mechanisms underlie this capacity by showing rapid serial visual presentation (RSVP) sequences with and without interstimulus gaps to human observers and macaque monkeys. For gaps of up to 93 ms between consecutive images, human observers and neurones in the temporal cortex of macaque monkeys were found to continue processing a stimulus as if it was still present on the screen. The continued firing of neurones in temporal cortex may therefore underlie iconic memory. Based on these findings, a neurophysiological vision of iconic memory is presented.

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

Strain-Detecting Composite Materials

NASA Technical Reports Server (NTRS)

Wallace, Terryl A. (Inventor); Smith, Stephen W. (Inventor); Piascik, Robert S. (Inventor); Horne, Michael R. (Inventor); Messick, Peter L. (Inventor); Alexa, Joel A. (Inventor); Glaessgen, Edward H. (Inventor); Hailer, Benjamin T. (Inventor)

2016-01-01

A composite material includes a structural material and a shape-memory alloy embedded in the structural material. The shape-memory alloy changes crystallographic phase from austenite to martensite in response to a predefined critical macroscopic average strain of the composite material. In a second embodiment, the composite material includes a plurality of particles of a ferromagnetic shape-memory alloy embedded in the structural material. The ferromagnetic shape-memory alloy changes crystallographic phase from austenite to martensite and changes magnetic phase in response to the predefined critical macroscopic average strain of the composite material. A method of forming a composite material for sensing the predefined critical macroscopic average strain includes providing the shape-memory alloy having an austenite crystallographic phase, changing a size and shape of the shape-memory alloy to thereby form a plurality of particles, and combining the structural material and the particles at a temperature of from about 100-700.degree. C. to form the composite material.

A wireless reflectance pulse oximeter with digital baseline control for unfiltered photoplethysmograms.

PubMed

Li, Kejia; Warren, Steve

2012-06-01

Pulse oximeters are central to the move toward wearable health monitoring devices and medical electronics either hosted by, e.g., smart phones or physically embedded in their design. This paper presents a small, low-cost pulse oximeter design appropriate for wearable and surface-based applications that also produces quality, unfiltered photo-plethysmograms (PPGs) ideal for emerging diagnostic algorithms. The design's "filter-free" embodiment, which employs only digital baseline subtraction as a signal compensation mechanism, distinguishes it from conventional pulse oximeters that incorporate filters for signal extraction and noise reduction. This results in high-fidelity PPGs with thousands of peak-to-peak digitization levels that are sampled at 240 Hz to avoid noise aliasing. Electronic feedback controls make these PPGs more resilient in the face of environmental changes (e.g., the device can operate in full room light), and data stream in real time across either a ZigBee wireless link or a wired USB connection to a host. On-board flash memory is available for store-and-forward applications. This sensor has demonstrated an ability to gather high-integrity data at fingertip, wrist, earlobe, palm, and temple locations from a group of 48 subjects (20 to 64 years old).

Fabrication of TiNi/CFRP smart composite using cold drawn TiNi wires

NASA Astrophysics Data System (ADS)

Xu, Ya; Otsuka, Kazuhiro; Toyama, Nobuyuki; Yoshida, Hitoshi; Jang, Byung-Koog; Nagai, Hideki; Oishi, Ryutaro; Kishi, Teruo

2002-07-01

In recent years, pre-strained TiNi shape memory alloys (SMA) have been used for fabricating smart structure with carbon fibers reinforced plastics (CFRP) in order to suppress microscopic mechanical damages. However, since the cure temperature of CFRP is higher than the reverse transformation temperatures of TiNi SMA, special fixture jigs have to be used for keeping the pre-strain during fabrication, which restricted its practical application. In order to overcome this difficulty, we developed a new method to fabricate SMA/CFRP smart composites without using special fixture jigs by controlling the transformation temperatures of SMA during fabrication. This method consists of using heavily cold-worked wires to increase the reverse transformation temperatures, and of using flash electrical heating of the wires after fabrication in order to decrease the reverse transformation temperatures to a lower temperature range again without damaging the epoxy resin around SMA wires. By choosing proper cold-working rate and composition of TiNi alloys, the reverse transformation temperatures were well controlled, and the TiNi/CFRP hybrid smart composite was fabricated without using special fixture jigs. The damage suppressing effect of cold drawn wires embedded in CFRP was confirmed.

Computer Game Play Reduces Intrusive Memories of Experimental Trauma via Reconsolidation-Update Mechanisms.

PubMed

James, Ella L; Bonsall, Michael B; Hoppitt, Laura; Tunbridge, Elizabeth M; Geddes, John R; Milton, Amy L; Holmes, Emily A

2015-08-01

Memory of a traumatic event becomes consolidated within hours. Intrusive memories can then flash back repeatedly into the mind's eye and cause distress. We investigated whether reconsolidation-the process during which memories become malleable when recalled-can be blocked using a cognitive task and whether such an approach can reduce these unbidden intrusions. We predicted that reconsolidation of a reactivated visual memory of experimental trauma could be disrupted by engaging in a visuospatial task that would compete for visual working memory resources. We showed that intrusive memories were virtually abolished by playing the computer game Tetris following a memory-reactivation task 24 hr after initial exposure to experimental trauma. Furthermore, both memory reactivation and playing Tetris were required to reduce subsequent intrusions (Experiment 2), consistent with reconsolidation-update mechanisms. A simple, noninvasive cognitive-task procedure administered after emotional memory has already consolidated (i.e., > 24 hours after exposure to experimental trauma) may prevent the recurrence of intrusive memories of those emotional events. © The Author(s) 2015.

Computer Game Play Reduces Intrusive Memories of Experimental Trauma via Reconsolidation-Update Mechanisms

PubMed Central

James, Ella L.; Bonsall, Michael B.; Hoppitt, Laura; Tunbridge, Elizabeth M.; Geddes, John R.; Milton, Amy L.

2015-01-01

Memory of a traumatic event becomes consolidated within hours. Intrusive memories can then flash back repeatedly into the mind’s eye and cause distress. We investigated whether reconsolidation—the process during which memories become malleable when recalled—can be blocked using a cognitive task and whether such an approach can reduce these unbidden intrusions. We predicted that reconsolidation of a reactivated visual memory of experimental trauma could be disrupted by engaging in a visuospatial task that would compete for visual working memory resources. We showed that intrusive memories were virtually abolished by playing the computer game Tetris following a memory-reactivation task 24 hr after initial exposure to experimental trauma. Furthermore, both memory reactivation and playing Tetris were required to reduce subsequent intrusions (Experiment 2), consistent with reconsolidation-update mechanisms. A simple, noninvasive cognitive-task procedure administered after emotional memory has already consolidated (i.e., > 24 hours after exposure to experimental trauma) may prevent the recurrence of intrusive memories of those emotional events. PMID:26133572

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Teaching Addition and Subtraction Operations with Schematic Place-Value Learning Aids & the Impact on Arithmetic Competency

ERIC Educational Resources Information Center

Kyriakidou-Christofidou, Athina

2016-01-01

The present mixed-methods quasi-experimental study (embedding a case study and a mixed factorial within-between ANOVA test), conducted in a private English school in Limassol, Cyprus, investigated how the use of the schematic learning aids (researcher-made color-coded flash-cards and grids) influence year-2 children's ability to read, write and…

Non-volatile memory for checkpoint storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.

A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, themore » non-volatile memory is a pluggable flash memory card.« less

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Merging with the path not taken: Wilhelm Wundt's work as a precursor to the embedded-processes approach to memory, attention, and consciousness.

PubMed

Cowan, Nelson; Rachev, Nikolay R

2018-06-04

Early research on memory was dominated by two researchers forging different paths: Hermann Ebbinghaus, interested in principles of learning and recall, and Wilhelm Wundt, founder of the first formal laboratory of experimental psychology, who was interested in empirical evidence to interpret conscious experience. Whereas the work of Ebbinghaus is a much-heralded precursor of modern research on long-term memory, the work of Wundt appears to be a mostly-forgotten precursor to research on working memory. We show how his scientific perspective is germane to more recent investigations, with emphasis on the embedded-processes approaches of Nelson Cowan and Klaus Oberauer, and how it is in contrast with most other recent theoretical approaches. This investigation is important because the embedded-process theorists, apparently like most modern researchers, have recognized few of Wundt's specific contributions. We explore commonalities between the approaches and suggest that an appreciation of these commonalities might enrich the field going forward. Copyright © 2018 Elsevier Inc. All rights reserved.

PCIE interface design for high-speed image storage system based on SSD

NASA Astrophysics Data System (ADS)

Wang, Shiming

2015-02-01

This paper proposes and implements a standard interface of miniaturized high-speed image storage system, which combines PowerPC with FPGA and utilizes PCIE bus as the high speed switching channel. Attached to the PowerPC, mSATA interface SSD(Solid State Drive) realizes RAID3 array storage. At the same time, a high-speed real-time image compression patent IP core also can be embedded in FPGA, which is in the leading domestic level with compression rate and image quality, making that the system can record higher image data rate or achieve longer recording time. The notebook memory card buckle type design is used in the mSATA interface SSD, which make it possible to complete the replacement in 5 seconds just using single hand, thus the total length of repeated recordings is increased. MSI (Message Signaled Interrupts) interruption guarantees the stability and reliability of continuous DMA transmission. Furthermore, only through the gigabit network, the remote display, control and upload to backup function can be realized. According to an optional 25 frame/s or 30 frame/s, upload speeds can be up to more than 84 MB/s. Compared with the existing FLASH array high-speed memory systems, it has higher degree of modularity, better stability and higher efficiency on development, maintenance and upgrading. Its data access rate is up to 300MB/s, realizing the high speed image storage system miniaturization, standardization and modularization, thus it is fit for image acquisition, storage and real-time transmission to server on mobile equipment.

Memory characteristics of metal-oxide-semiconductor structures based on Ge nanoclusters-embedded GeO(x) films grown at low temperature.

PubMed

Lin, Tzu-Shun; Lou, Li-Ren; Lee, Ching-Ting; Tsai, Tai-Cheng

2012-03-01

The memory devices constructed from the Ge-nanoclusters embedded GeO(x) layer deposited by the laser-assisted chemical vapor deposition (LACVD) system were fabricated. The Ge nanoclusters were observed by a high-resolution transmission electron microscopy. Using the capacitance versus voltage (C-V) and the conductance versus voltage (G-V) characteristics measured under various frequencies, the memory effect observed in the C-V curves was dominantly attributed to the charge storage in the Ge nanoclusters. Furthermore, the defects existed in the deposited film and the interface states were insignificant to the memory performances. Capacitance versus time (C-t) measurement was also executed to evaluate the charge retention characteristics. The charge storage and retention behaviors of the devices demonstrated that the Ge nanoclusters grown by the LACVD system at low temperature are promising for memory device applications.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

NASA Astrophysics Data System (ADS)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

NASA Astrophysics Data System (ADS)

Chen, Ting; Van Den Broeke, Doug; Hsu, Stephen; Hsu, Michael; Park, Sangbong; Berger, Gabriel; Coskun, Tamer; de Vocht, Joep; Chen, Fung; Socha, Robert; Park, JungChul; Gronlund, Keith

2005-11-01

Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k1, e.g. k1<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k1<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Modality independence of order coding in working memory: Evidence from cross-modal order interference at recall.

PubMed

Vandierendonck, André

2016-01-01

Working memory researchers do not agree on whether order in serial recall is encoded by dedicated modality-specific systems or by a more general modality-independent system. Although previous research supports the existence of autonomous modality-specific systems, it has been shown that serial recognition memory is prone to cross-modal order interference by concurrent tasks. The present study used a serial recall task, which was performed in a single-task condition and in a dual-task condition with an embedded memory task in the retention interval. The modality of the serial task was either verbal or visuospatial, and the embedded tasks were in the other modality and required either serial or item recall. Care was taken to avoid modality overlaps during presentation and recall. In Experiment 1, visuospatial but not verbal serial recall was more impaired when the embedded task was an order than when it was an item task. Using a more difficult verbal serial recall task, verbal serial recall was also more impaired by another order recall task in Experiment 2. These findings are consistent with the hypothesis of modality-independent order coding. The implications for views on short-term recall and the multicomponent view of working memory are discussed.

Evidence for modality-independent order coding in working memory.

PubMed

Depoorter, Ann; Vandierendonck, André

2009-03-01

The aim of the present study was to investigate the representation of serial order in working memory, more specifically whether serial order is coded by means of a modality-dependent or a modality-independent order code. This was investigated by means of a series of four experiments based on a dual-task methodology in which one short-term memory task was embedded between the presentation and recall of another short-term memory task. Two aspects were varied in these memory tasks--namely, the modality of the stimulus materials (verbal or visuo-spatial) and the presence of an order component in the task (an order or an item memory task). The results of this study showed impaired primary-task recognition performance when both the primary and the embedded task included an order component, irrespective of the modality of the stimulus materials. If one or both of the tasks did not contain an order component, less interference was found. The results of this study support the existence of a modality-independent order code.

Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2012-01-01

Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.

Portable flash lamp reflectance analyzer system and method

NASA Technical Reports Server (NTRS)

Kalshoven, James Edward (Inventor)

1999-01-01

The system and method allow spectroscopic analysis of vegetation or the like without effects from changing sun and cloud conditions, undesired portions of the area of interest or atmospheric disturbances. The system (1) includes a light source (5) such as a xenon flash lamp, a telescope (7), a spectrometer (9), an analog/digital converter (11), a memory (13), a display (15), and an on-board microprocessor (17) or a port (19) for attachment to a laptop computer. The system is taken to an area of interest in the woods (step 41), the vegetation is illuminated from below (step 43) and data are taken (step 45).

Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

NASA Astrophysics Data System (ADS)

Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming

2017-08-01

The attractive usability of quantum phenomena in futuristic devices is possible by using zero-dimensional systems like nanocrystals (NCs). The performance of nonvolatile flash memory devices has greatly benefited from the use of NCs over recent decades. The quantum abilities of NCs have been used to improve the reliability of flash devices. Its appeal is extended to the design of emerging devices such as resistive random-access memory (RRAM), a technology where the use of silicon is optional. Here, we are going to review the recent progress in the design, characterization, and utilization of NCs in RRAM devices. We will first introduce the physical design of the RRAM devices using NCs and the improvement of electrical performance in NC-RRAM over conventional ones. In particular, special care has been taken to review the ways of development provided by the NCs in the RRAM devices. In a broad sense, the NCs can play a charge trapping role in the NC-RRAM structure or it can be responsible for the localization and improvement of the stability of the conductive filament or it can play a part in the formation of the conductive filament chain by the NC migration under applied bias. Finally, the scope of NCs in the RRAM devices has also been discussed.

Structural health monitoring for DOT using magnetic shape memory alloy cables in concrete

NASA Astrophysics Data System (ADS)

Davis, Allen; Mirsayar, Mirmilad; Sheahan, Emery; Hartl, Darren

2018-03-01

Embedding shape memory alloy (SMA) wires in concrete components offers the potential to monitor their structural health via external magnetic field sensing. Currently, structural health monitoring (SHM) is dominated by acoustic emission and vibration-based methods. Thus, it is attractive to pursue alternative damage sensing techniques that may lower the cost or increase the accuracy of SHM. In this work, SHM via magnetic field detection applied to embedded magnetic shape memory alloy (MSMA) is demonstrated both experimentally and using computational models. A concrete beam containing iron-based MSMA wire is subjected to a 3-point bend test where structural damage is induced, thereby resulting in a localized phase change of the MSMA wire. Magnetic field lines passing through the embedded MSMA domain are altered by this phase change and can thus be used to detect damage within the structure. A good correlation is observed between the computational and experimental results. Additionally, the implementation of stranded MSMA cables in place of the MSMA wire is assessed through similar computational models. The combination of these computational models and their subsequent experimental validation provide sufficient support for the feasibility of SHM using magnetic field sensing via MSMA embedded components.

Incorporation of Fiber Bragg Sensors for Shape Memory Polyurethanes Characterization.

PubMed

Alberto, Nélia; Fonseca, Maria A; Neto, Victor; Nogueira, Rogério; Oliveira, Mónica; Moreira, Rui

2017-11-11

Shape memory polyurethanes (SMPUs) are thermally activated shape memory materials, which can be used as actuators or sensors in applications including aerospace, aeronautics, automobiles or the biomedical industry. The accurate characterization of the memory effect of these materials is therefore mandatory for the technology's success. The shape memory characterization is normally accomplished using mechanical testing coupled with a heat source, where a detailed knowledge of the heat cycle and its influence on the material properties is paramount but difficult to monitor. In this work, fiber Bragg grating (FBG) sensors were embedded into SMPU samples aiming to study and characterize its shape memory effect. The samples were obtained by injection molding, and the entire processing cycle was successfully monitored, providing a process global quality signature. Moreover, the integrity and functionality of the FBG sensors were maintained during and after the embedding process, demonstrating the feasibility of the technology chosen for the purpose envisaged. The results of the shape memory effect characterization demonstrate a good correlation between the reflected FBG peak with the temperature and induced strain, proving that this technology is suitable for this particular application.

Incorporation of Fiber Bragg Sensors for Shape Memory Polyurethanes Characterization

PubMed Central

Nogueira, Rogério; Moreira, Rui

2017-01-01

Shape memory polyurethanes (SMPUs) are thermally activated shape memory materials, which can be used as actuators or sensors in applications including aerospace, aeronautics, automobiles or the biomedical industry. The accurate characterization of the memory effect of these materials is therefore mandatory for the technology’s success. The shape memory characterization is normally accomplished using mechanical testing coupled with a heat source, where a detailed knowledge of the heat cycle and its influence on the material properties is paramount but difficult to monitor. In this work, fiber Bragg grating (FBG) sensors were embedded into SMPU samples aiming to study and characterize its shape memory effect. The samples were obtained by injection molding, and the entire processing cycle was successfully monitored, providing a process global quality signature. Moreover, the integrity and functionality of the FBG sensors were maintained during and after the embedding process, demonstrating the feasibility of the technology chosen for the purpose envisaged. The results of the shape memory effect characterization demonstrate a good correlation between the reflected FBG peak with the temperature and induced strain, proving that this technology is suitable for this particular application. PMID:29137136

Giant Electroresistance in Edge Metal-Insulator-Metal Tunnel Junctions Induced by Ferroelectric Fringe Fields

PubMed Central

Jung, Sungchul; Jeon, Youngeun; Jin, Hanbyul; Lee, Jung-Yong; Ko, Jae-Hyeon; Kim, Nam; Eom, Daejin; Park, Kibog

2016-01-01

An enormous amount of research activities has been devoted to developing new types of non-volatile memory devices as the potential replacements of current flash memory devices. Theoretical device modeling was performed to demonstrate that a huge change of tunnel resistance in an Edge Metal-Insulator-Metal (EMIM) junction of metal crossbar structure can be induced by the modulation of electric fringe field, associated with the polarization reversal of an underlying ferroelectric layer. It is demonstrated that single three-terminal EMIM/Ferroelectric structure could form an active memory cell without any additional selection devices. This new structure can open up a way of fabricating all-thin-film-based, high-density, high-speed, and low-power non-volatile memory devices that are stackable to realize 3D memory architecture. PMID:27476475

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer

NASA Astrophysics Data System (ADS)

Shen, Yung-Shao; Chen, Kuen-Yi; Chen, Po-Chun; Chen, Teng-Chuan; Wu, Yung-Hsien

2017-03-01

Crystalline ZrTiO4 (ZTO) in orthorhombic phase with different plasma treatments was explored as the charge-trapping layer for low-voltage operation flash memory. For ZTO without any plasma treatment, even with a high k value of 45.2, it almost cannot store charges due the oxygen vacancies-induced shallow-level traps that make charges easy to tunnel back to Si substrate. With CF4 plasma treatment, charge storage is still not improved even though incorporated F atoms could introduce additional traps since the F atoms disappear during the subsequent thermal annealing. On the contrary, nevertheless the k value degrades to 40.8, N2O plasma-treated ZTO shows promising performance in terms of 5-V hysteresis memory window by ±7-V sweeping voltage, 2.8-V flatband voltage shift by programming at +7 V for 100 μs, negligible memory window degradation with 105 program/erase cycles and 81.8% charge retention after 104 sec at 125 °C. These desirable characteristics are ascribed not only to passivation of oxygen vacancies-related shallow-level traps but to introduction of a large amount of deep-level bulk charge traps which have been proven by confirming thermally excited process as the charge loss mechanism and identifying traps located at energy level beneath ZTO conduction band by 0.84 eV~1.03 eV.

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer.

PubMed

Shen, Yung-Shao; Chen, Kuen-Yi; Chen, Po-Chun; Chen, Teng-Chuan; Wu, Yung-Hsien

2017-03-08

Crystalline ZrTiO 4 (ZTO) in orthorhombic phase with different plasma treatments was explored as the charge-trapping layer for low-voltage operation flash memory. For ZTO without any plasma treatment, even with a high k value of 45.2, it almost cannot store charges due the oxygen vacancies-induced shallow-level traps that make charges easy to tunnel back to Si substrate. With CF 4 plasma treatment, charge storage is still not improved even though incorporated F atoms could introduce additional traps since the F atoms disappear during the subsequent thermal annealing. On the contrary, nevertheless the k value degrades to 40.8, N 2 O plasma-treated ZTO shows promising performance in terms of 5-V hysteresis memory window by ±7-V sweeping voltage, 2.8-V flatband voltage shift by programming at +7 V for 100 μs, negligible memory window degradation with 10 5 program/erase cycles and 81.8% charge retention after 10 4  sec at 125 °C. These desirable characteristics are ascribed not only to passivation of oxygen vacancies-related shallow-level traps but to introduction of a large amount of deep-level bulk charge traps which have been proven by confirming thermally excited process as the charge loss mechanism and identifying traps located at energy level beneath ZTO conduction band by 0.84 eV~1.03 eV.

Noise Attenuation Performance Assessment of the Joint Helmet Mounted Cueing System (JHMCS)

DTIC Science & Technology

2010-08-01

Flash Drive (CFD) memory (Figure 9) and Sound Professionals SP-TFB-2 Miniature Binaural Microphones with the Sound Professionals SP-SPSB-1 Slim-line...flight noise. Sound Professionals binaural microphones were placed to record both internal and external sounds. One microphone was attached to the

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Carrier transport mechanisms of nonvolatile write-once-read-many-times memory devices with InP-ZnS core-shell nanoparticles embedded in a polymethyl methacrylate layer

NASA Astrophysics Data System (ADS)

Ham, Jung Hoon; Oh, Do Hyun; Cho, Sung Hwan; Jung, Jae Hun; Kim, Tae Whan; Ryu, Eui Dock; Kim, Sang Wook

2009-03-01

Current-voltage (I-V) curves at 300 K for Al/InP-ZnS nanoparticles embedded in a polymethyl methacrylate layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. From the I-V curves, the ON/OFF ratio for the device with InP-ZnS nanoparticles was significantly larger than that for the device without InP-ZnS nanoparticles, indicative of the existence of charge capture in the InP nanoparticles. The estimated retention time of the ON state for the WORM memory device was more than 10 years. The carrier transport mechanisms for the WORM memory devices are described by using several models to fit the experimental I-V data.

The Magnetic Response of the Solar Atmosphere to Umbral Flashes

NASA Astrophysics Data System (ADS)

Houston, S. J.; Jess, D. B.; Asensio Ramos, A.; Grant, S. D. T.; Beck, C.; Norton, A. A.; Krishna Prasad, S.

2018-06-01

Chromospheric observations of sunspot umbrae offer an exceptional view of magnetoacoustic shock phenomena and the impact they have on the surrounding magnetically dominated plasma. We employ simultaneous slit-based spectro-polarimetry and spectral imaging observations of the chromospheric He I 10830 Å and Ca II 8542 Å lines to examine fluctuations in the umbral magnetic field caused by the steepening of magnetoacoustic waves into umbral flashes. Following the application of modern inversion routines, we find evidence to support the scenario that umbral shock events cause expansion of the embedded magnetic field lines due to the increased adiabatic pressure. The large number statistics employed allow us to calculate the adiabatic index, γ = 1.12 ± 0.01, for chromospheric umbral locations. Examination of the vector magnetic field fluctuations perpendicular to the solar normal revealed changes up to ∼200 G at the locations of umbral flashes. Such transversal magnetic field fluctuations have not been described before. Through comparisons with nonlinear force-free field extrapolations, we find that the perturbations of the transverse field components are oriented in the same direction as the quiescent field geometries. This implies that magnetic field enhancements produced by umbral flashes are directed along the motion path of the developing shock, hence producing relatively small changes, up to a maximum of ∼8°, in the inclination and/or azimuthal directions of the magnetic field. Importantly, this work highlights that umbral flashes are able to modify the full vector magnetic field, with the detection of the weaker transverse magnetic field components made possible by high-resolution data combined with modern inversion routines.

Discourse accessibility constraints in children’s processing of object relative clauses

PubMed Central

Haendler, Yair; Kliegl, Reinhold; Adani, Flavia

2015-01-01

Children’s poor performance on object relative clauses has been explained in terms of intervention locality. This approach predicts that object relatives with a full DP head and an embedded pronominal subject are easier than object relatives in which both the head noun and the embedded subject are full DPs. This prediction is shared by other accounts formulated to explain processing mechanisms. We conducted a visual-world study designed to test the off-line comprehension and on-line processing of object relatives in German-speaking 5-year-olds. Children were tested on three types of object relatives, all having a full DP head noun and differing with respect to the type of nominal phrase that appeared in the embedded subject position: another full DP, a 1st- or a 3rd-person pronoun. Grammatical skills and memory capacity were also assessed in order to see whether and how they affect children’s performance. Most accurately processed were object relatives with 1st-person pronoun, independently of children’s language and memory skills. Performance on object relatives with two full DPs was overall more accurate than on object relatives with 3rd-person pronoun. In the former condition, children with stronger grammatical skills accurately processed the structure and their memory abilities determined how fast they were; in the latter condition, children only processed accurately the structure if they were strong both in their grammatical skills and in their memory capacity. The results are discussed in the light of accounts that predict different pronoun effects like the ones we find, which depend on the referential properties of the pronouns. We then discuss which role language and memory abilities might have in processing object relatives with various embedded nominal phrases. PMID:26157410

Charging/discharging behavior and mechanism of silicon quantum dots embedded in amorphous silicon carbide films

NASA Astrophysics Data System (ADS)

Wen, Xixing; Zeng, Xiangbin; Zheng, Wenjun; Liao, Wugang; Feng, Feng

2015-01-01

The charging/discharging behavior of Si quantum dots (QDs) embedded in amorphous silicon carbide (a-SiCx) was investigated based on the Al/insulating layer/Si QDs embedded in a-SiCx/SiO2/p-Si (metal-insulator-quantum dots-oxide-silicon) multilayer structure by capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. Transmission electron microscopy and Raman scattering spectroscopy measurements reveal the microstructure and distribution of Si QDs. The occurrence and shift of conductance peaks indicate the carrier transfer and the charging/discharging behavior of Si QDs. The multilayer structure shows a large memory window of 5.2 eV at ±8 V sweeping voltage. Analysis of the C-V and G-V results allows a quantification of the Coulomb charging energy and the trapped charge density associated with the charging/discharging behavior. It is found that the memory window is related to the size effect, and Si QDs with large size or low Coulomb charging energy can trap two or more electrons by changing the charging voltage. Meanwhile, the estimated lower potential barrier height between Si QD and a-SiCx, and the lower Coulomb charging energy of Si QDs could enhance the charging and discharging effect of Si QDs and lead to an enlarged memory window. Further studies of the charging/discharging mechanism of Si QDs embedded in a-SiCx can promote the application of Si QDs in low-power consumption semiconductor memory devices.

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

NASA Astrophysics Data System (ADS)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (<=30 ns), excellent endurance (~1012 cycles), stability (>106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Exploring stop-go decision zones at rural high-speed intersections with flashing green signal and insufficient yellow time in China.

PubMed

Tang, Keshuang; Xu, Yanqing; Wang, Fen; Oguchi, Takashi

2016-10-01

The objective of this study is to empirically analyze and model the stop-go decision behavior of drivers at rural high-speed intersections in China, where a flashing green signal of 3s followed by a yellow signal of 3s is commonly applied to end a green phase. 1, 186 high-resolution vehicle trajectories were collected at four typical high-speed intersection approaches in Shanghai and used for the identification of actual stop-go decision zones and the modeling of stop-go decision behavior. Results indicate that the presence of flashing green significantly changed the theoretical decision zones based on the conventional Dilemma Zone theory. The actual stop-go decision zones at the study intersections were thus formulated and identified based on the empirical data. Binary Logistic model and Fuzzy Logic model were then developed to further explore the impacts of flashing green on the stop-go behavior of drivers. It was found that the Fuzzy Logic model could produce comparably good estimation results as compared to the traditional Binary Logistic models. The findings of this study could contribute the development of effective dilemma zone protection strategies, the improvement of stop-go decision model embedded in the microscopic traffic simulation software and the proper design of signal change and clearance intervals at high-speed intersections in China. Copyright © 2016 Elsevier Ltd. All rights reserved.

Effects of Interfacial Fluorination on Performance Enhancement of High-k-Based Charge Trap Flash Memory

NASA Astrophysics Data System (ADS)

Wang, Chenjie; Huo, Zongliang; Liu, Ziyu; Liu, Yu; Cui, Yanxiang; Wang, Yumei; Li, Fanghua; Liu, Ming

2013-07-01

The effects of interfacial fluorination on the metal/Al2O3/HfO2/SiO2/Si (MAHOS) memory structure have been investigated. By comparing MAHOS memories with and without interfacial fluorination, it was identified that the deterioration of the performance and reliability of MAHOS memories is mainly due to the formation of an interfacial layer that generates excess oxygen vacancies at the interface. Interfacial fluorination suppresses the growth of the interfacial layer, which is confirmed by X-ray photoelectron spectroscopy depth profile analysis, increases enhanced program/erase efficiency, and improves data retention characteristics. Moreover, it was observed that fluorination at the SiO-HfO interface achieves a more effective performance enhancement than that at the HfO-AlO interface.

Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

2011-01-01

NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Long-Term Memory Biases Auditory Spatial Attention

ERIC Educational Resources Information Center

Zimmermann, Jacqueline F.; Moscovitch, Morris; Alain, Claude

2017-01-01

Long-term memory (LTM) has been shown to bias attention to a previously learned visual target location. Here, we examined whether memory-predicted spatial location can facilitate the detection of a faint pure tone target embedded in real world audio clips (e.g., soundtrack of a restaurant). During an initial familiarization task, participants…

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Because advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

76 FR 25707 - In the Matter of Certain Flash Memory and Products Containing Same; Notice of Commission Decision...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-05-05

... review of the ALJ's determination concerning the ALJ's findings on claim construction, infringement... Commission has also determined to review the ID's construction of the ``extracting'' limitation of claim 8 as... construction of the claim limitation ``accumulatively averaging working conditions of lots previously processed...

Charge injection and discharging of Si nanocrystals and arrays by atomic force microscopy

NASA Technical Reports Server (NTRS)

Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

Charge injection and storage in dense arrays of silicon nanocrystals in SiO(sub 2) is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few-or single- electron storage in a small number of nanocrystal elements.

An Analysis of MARSIS Radar Flash Memory Data from Lunae Planum, Mars: Searching for Subsurface Structures.

NASA Astrophysics Data System (ADS)

Caprarelli, G.; Orosei, R.; Mastrogiuseppe, M.; Cartacci, M.

2017-12-01

Lunae Planum is a Martian plain measuring approximately 1000 km in width and 2000 km in length, centered at coordinates 294°E-11°N. MOLA elevations range from +2500 m to +500 m in the south, gently sloping northward to -500 m. The plain is part of a belt of terrains located between the southern highlands and the northern lowlands, that are transitional in character (e.g., by elevation, age and morphology). These transitional terrains are poorly understood, in part because of their relative lack of major geomorphological features. They record however a very significant part of Mars's geologic history. The most evident features on Lunae Planum's Hesperian surface are regularly spaced, longitudinally striking, wrinkle ridges. These indicate the presence of blind thrust faults cutting through thick stacks of layers of volcanic or sedimentary rocks. The presence of fluidized ejecta craters scattered all over the region suggests also the presence of ice or volatiles in the subsurface. In a preliminary study of Lunae Planum's subsurface we used the Mars Express ground penetrating radar MARSIS dataset [1], in order to detect reflectors that could indicate the presence of fault planes or layering. Standard radargrams however, provided no evidence of changes in value of dielectric constant that could indicate possible geologic discontinuities or stratification of physically diverse materials. We thus started a new investigation based on processing of raw MARSIS data. Here we report on the preliminary results of this study. We searched the MARSIS archive for raw data stored in flash memory. When operating with flash storage, the radar collects 2 frequency bands along-track covering a distance = 100-250 km, depending on the orbiter altitude [2]. We found flash memory data from 24 orbits over the area. We processed the data focusing radar returns in off-nadir directions, to maximize the likelihood of detecting sloping subsurface structures, including those striking parallel to the Mars Express sub-polar orbits. We plan to follow this study by applying a new processor aimed at improving the resolution and signal to noise ratio of the data. [1] Caprarelli et al. (2017), LPSC 48, 1720. [2] Watters et al. (2017), LPSC 48, 1693.

Transplantation and Perfusion of Microvascular Fragments in a Rodent Model of Volumetric Muscle Loss Injury

DTIC Science & Technology

2014-07-01

solution. Tissue processing and histological procedures Tissues were excised, weighed, embedded in a talcum- based gel, and flash frozen in 2...the overall level of perfusion was low and was not distributed evenly throughout the defect. GFP MVF transplantation MVFs derived from GFP...support vasculogenesis. However, the levels of VEGF secreted by MVFs were significantly lower than that of ASCs under both normoxic and hypoxic

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

Thermomechanical response of NiTi shape-memory nanoprecipitates in TiV alloys

NASA Astrophysics Data System (ADS)

Maisel, S. B.; Ko, W.-S.; Zhang, J.-L.; Grabowski, B.; Neugebauer, J.

2017-08-01

We study the properties of NiTi shape-memory nanoparticles coherently embedded in TiV matrices using three-dimensional atomistic simulations based on the modified embedded-atom method. To this end, we develop and present a suitable NiTiV potential for our simulations. Employing this potential, we identify the conditions under which the martensitic phase transformation of such a nanoparticle is triggered—specifically, how these conditions can be tuned by modifying the size of the particle, the composition of the surrounding matrix, or the temperature and strain state of the system. Using these insights, we establish how the transformation temperature of such particles can be influenced and discuss the practical implications in the context of shape-memory strengthened alloys.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Influence of emotional content and context on memory in mild Alzheimer's disease.

PubMed

Perrin, Margaux; Henaff, Marie-Anne; Padovan, Catherine; Faillenot, Isabelle; Merville, Adrien; Krolak-Salmon, Pierre

2012-01-01

Healthy subjects remember emotional stimuli better than neutral, as well as stimuli embedded in an emotional context. This better memory of emotional messages is linked to an amygdalo-hippocampal cooperation taking place in a larger fronto-temporal network particularly sensitive to pathological aging. Amygdala is mainly involved in gist memory of emotional messages. Whether emotional content or context enhances memory in mild Alzheimer's disease (AD) patients is still debated. The aim of the present study is to examine the influence of emotional content and emotional context on the memory in mild AD, and whether this influence is linked to amygdala volume. Fifteen patients affected by mild AD and 15 age-matched controls were submitted to series of negative, positive, and neutral pictures. Each series was embedded in an emotional or neutral sound context. At the end of each series, participants had to freely recall pictures, and answer questions about each picture. Amygdala volumes were measured on patient 3D-MRI scans. In the present study, emotional content significantly favored memory of gist but not of details in healthy elderly and in AD patients. Patients' amygdala volume was positively correlated to emotional content memory effect, implying a reduced memory benefit from emotional content when amygdala was atrophied. A positive context enhanced memory of pictures in healthy elderly, but not in AD, corroborating early fronto-temporal dysfunction and early working memory limitation in this disease.

Electrophysiological Repetition Effects in Persons with Mild Cognitive Impairment depend upon Working Memory Demand.

PubMed

Broster, Lucas S; Jenkins, Shonna L; Holmes, Sarah D; Edwards, Matthew G; Jicha, Gregory A; Jiang, Yang

2018-05-07

Forms of implicit memory, including repetition effects, are preserved relative to explicit memory in clinical Alzheimer's disease. Consequently, cognitive interventions for persons with Alzheimer's disease have been developed that leverage this fact. However, despite the clinical robustness of behavioral repetition effects, altered neural mechanisms of repetition effects are studied as biomarkers of both clinical Alzheimer's disease and pre-morbid Alzheimer's changes in the brain. We hypothesized that the clinical preservation of behavioral repetition effects results in part from concurrent operation of discrete memory systems. We developed two experiments that included probes of emotional repetition effects differing in that one included an embedded working memory task. We found that neural repetition effects manifested in patients with amnestic mild cognitive impairment, the earliest form of clinical Alzheimer's disease, during emotional working memory tasks, but they did not manifest during the task that lacked the embedded working memory manipulation. Specifically, the working memory task evoked neural repetition effects in the P600 time-window, but the same neural mechanism was only minimally implicated in the task without a working memory component. We also found that group differences in behavioral repetition effects were smaller in the experiment with a working memory task. We suggest that cross-domain cognitive challenge can expose "defunct" neural capabilities of individuals with amnestic mild cognitive impairment. Copyright © 2018. Published by Elsevier Ltd.

Energy consumption estimation of an OMAP-based Android operating system

NASA Astrophysics Data System (ADS)

González, Gabriel; Juárez, Eduardo; Castro, Juan José; Sanz, César

2011-05-01

System-level energy optimization of battery-powered multimedia embedded systems has recently become a design goal. The poor operational time of multimedia terminals makes computationally demanding applications impractical in real scenarios. For instance, the so-called smart-phones are currently unable to remain in operation longer than several hours. The OMAP3530 processor basically consists of two processing cores, a General Purpose Processor (GPP) and a Digital Signal Processor (DSP). The former, an ARM Cortex-A8 processor, is aimed to run a generic Operating System (OS) while the latter, a DSP core based on the C64x+, has architecture optimized for video processing. The BeagleBoard, a commercial prototyping board based on the OMAP processor, has been used to test the Android Operating System and measure its performance. The board has 128 MB of SDRAM external memory, 256 MB of Flash external memory and several interfaces. Note that the clock frequency of the ARM and DSP OMAP cores is 600 MHz and 430 MHz, respectively. This paper describes the energy consumption estimation of the processes and multimedia applications of an Android v1.6 (Donut) OS on the OMAP3530-Based BeagleBoard. In addition, tools to communicate the two processing cores have been employed. A test-bench to profile the OS resource usage has been developed. As far as the energy estimates concern, the OMAP processor energy consumption model provided by the manufacturer has been used. The model is basically divided in two energy components. The former, the baseline core energy, describes the energy consumption that is independent of any chip activity. The latter, the module active energy, describes the energy consumed by the active modules depending on resource usage.

Smart composites with embedded shape memory alloy actuators and fibre Bragg grating sensors: activation and control

NASA Astrophysics Data System (ADS)

Balta, J. A.; Bosia, F.; Michaud, V.; Dunkel, G.; Botsis, J.; Månson, J.-A.

2005-08-01

This paper describes the production of an adaptive composite by embedding thin pre-strained shape memory alloy actuators into a Kevlar-epoxy host material. In order to combine the activation and sensing capabilities, fibre Bragg grating sensors are also embedded into the specimens, and the strain measured in situ during activation. The effect of manufacturing conditions, and hence of the initial stress state in the composite before activation, on the magnitude of the measured strains is discussed. The results of stress and strain simulations are compared with experimental data, and guidelines are provided for the optimization of the composite. Finally, a pilot experiment is carried out to provide an example of how a strain-stabilizing feedback mechanism can be implemented in the smart structure.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

Analogous Mechanisms of Selection and Updating in Declarative and Procedural Working Memory: Experiments and a Computational Model

ERIC Educational Resources Information Center

Oberauer, Klaus; Souza, Alessandra S.; Druey, Michel D.; Gade, Miriam

2013-01-01

The article investigates the mechanisms of selecting and updating representations in declarative and procedural working memory (WM). Declarative WM holds the objects of thought available, whereas procedural WM holds representations of what to do with these objects. Both systems consist of three embedded components: activated long-term memory, a…

The Explicit/Implicit Knowledge Distinction and Working Memory: Implications for Second-Language Reading Comprehension

ERIC Educational Resources Information Center

Ercetin, Gulcan; Alptekin, Cem

2013-01-01

Following an extensive overview of the subject, this study explores the relationships between second-language (L2) explicit/implicit knowledge sources, embedded in the declarative/procedural memory systems, and L2 working memory (WM) capacity. It further examines the relationships between L2 reading comprehension and L2 WM capacity as well as…

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Investigation of residual stresses in shape memory alloy (SMA) composites

NASA Astrophysics Data System (ADS)

Berman, Justin Bradley

Shape memory alloy (SMA) composites are a class of smart materials in which SMA actuators are embedded in a host matrix. The shape memory effect allows for stress induced phase transformations and large recoverable strains that make SMA composites promising candidates for structural shape/vibration control, impact absorption, aircraft deicing or in-flight airfoil shape control systems. However, the difference in thermal expansion between the SMA and the host material leads to residual stresses during processing. In addition, the SMA transformation from martensite to austenite, or the reverse, also generate stresses. These stresses acting in combination can lead to SMA/polymer interfacial debonding or microcracking of the host matrix. The present work was undertaken to study the behavior of nitinol shape memory alloys embedded in epoxy and glass/epoxy matrices and to investigate the development of residual stresses during their manufacture and actuation. A three-phase concentric cylinder micromechanics model and an SMA composite thermoelastic beam theory were developed to analyze the micromechanical and structural-level thermal and transformational stresses for nitinol composites induced by nitinol wires embedded in a host matrix. A series of warpage experiments were conducted on nitinol composite beams during heating cycles to provide experimental validation of model predictions and to assess their thermoelastic structural behavior under non-mechanical loading. Micromechanical model results indicate that excessive residual hoop stresses in nitino/graphite/epoxy composites leads to radial cracking around the embedded nitinol wires. Based on modeling results, the most important factor in reducing residual stresses (and thereby preventing radial cracking) is increasing the level of recovery strain for the nitinol wire. The SMA composite beam model agrees well with experimental data captured for the nitinol/epoxy beam series. Warpage experiments on nitinol/glass/epoxy beams showed a large increase in the effective austenitic start temperature (As) of 9.3°C. The elevation of the effective As together with other observations of warpage development indicates that plastic flow may have occurred in nitinol wires when embedded in glass/epoxy. These observations reinforce the need to train nitinol wires at modest recovery levels when embedding in relatively stiff materials.

Evaluation Data of a High Temperature COTS Flash Memory Module (TI SM28VLT32) for Use in Geothermal Electronics Packages

DOE Data Explorer

Cashion, Avery

2014-08-29

The accompanying raw data is composslection. Each file is 3 columns and tab-delimited with the first column being the data address, the second column being the first byte of the data, and the third column being the second byte of the data.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

NASA Astrophysics Data System (ADS)

Hou, Zhao-Zhao; Wang, Gui-Lei; Yao, Jia-Xin; Zhang, Qing-Zhu; Yin, Hua-Xiang

2018-05-01

Not Available Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

The role of spatial selective attention in working memory for locations: evidence from event-related potentials.

PubMed

Awh, E; Anllo-Vento, L; Hillyard, S A

2000-09-01

We investigated the hypothesis that the covert focusing of spatial attention mediates the on-line maintenance of location information in spatial working memory. During the delay period of a spatial working-memory task, behaviorally irrelevant probe stimuli were flashed at both memorized and nonmemorized locations. Multichannel recordings of event-related potentials (ERPs) were used to assess visual processing of the probes at the different locations. Consistent with the hypothesis of attention-based rehearsal, early ERP components were enlarged in response to probes that appeared at memorized locations. These visual modulations were similar in latency and topography to those observed after explicit manipulations of spatial selective attention in a parallel experimental condition that employed an identical stimulus display.

Individual differences in working memory capacity predict visual attention allocation.

PubMed

Bleckley, M Kathryn; Durso, Francis T; Crutchfield, Jerry M; Engle, Randall W; Khanna, Maya M

2003-12-01

To the extent that individual differences in working memory capacity (WMC) reflect differences in attention (Baddeley, 1993; Engle, Kane, & Tuholski, 1999), differences in WMC should predict performance on visual attention tasks. Individuals who scored in the upper and lower quartiles on the OSPAN working memory test performed a modification of Egly and Homa's (1984) selective attention task. In this task, the participants identified a central letter and localized a displaced letter flashed somewhere on one of three concentric rings. When the displaced letter occurred closer to fixation than the cue implied, high-WMC, but not low-WMC, individuals showed a cost in the letter localization task. This suggests that low-WMC participants allocated attention as a spotlight, whereas those with high WMC showed flexible allocation.

Novel approach for low-cost muzzle flash detection system

NASA Astrophysics Data System (ADS)

Voskoboinik, Asher

2008-04-01

A low-cost muzzle flash detection based on CMOS sensor technology is proposed. This low-cost technology makes it possible to detect various transient events with characteristic times between dozens of microseconds up to dozens of milliseconds while sophisticated algorithms successfully separate them from false alarms by utilizing differences in geometrical characteristics and/or temporal signatures. The proposed system consists of off-the-shelf smart CMOS cameras with built-in signal and image processing capabilities for pre-processing together with allocated memory for storing a buffer of images for further post-processing. Such a sensor does not require sending giant amounts of raw data to a real-time processing unit but provides all calculations in-situ where processing results are the output of the sensor. This patented CMOS muzzle flash detection concept exhibits high-performance detection capability with very low false-alarm rates. It was found that most false-alarms due to sun glints are from sources at distances of 500-700 meters from the sensor and can be distinguished by time examination techniques from muzzle flash signals. This will enable to eliminate up to 80% of falsealarms due to sun specular reflections in the battle field. Additional effort to distinguish sun glints from suspected muzzle flash signal is made by optimization of the spectral band in Near-IR region. The proposed system can be used for muzzle detection of small arms, missiles and rockets and other military applications.

NAFFS: network attached flash file system for cloud storage on portable consumer electronics

NASA Astrophysics Data System (ADS)

Han, Lin; Huang, Hao; Xie, Changsheng

Cloud storage technology has become a research hotspot in recent years, while the existing cloud storage services are mainly designed for data storage needs with stable high speed Internet connection. Mobile Internet connections are often unstable and the speed is relatively low. These native features of mobile Internet limit the use of cloud storage in portable consumer electronics. The Network Attached Flash File System (NAFFS) presented the idea of taking the portable device built-in NAND flash memory as the front-end cache of virtualized cloud storage device. Modern portable devices with Internet connection have built-in more than 1GB NAND Flash, which is quite enough for daily data storage. The data transfer rate of NAND flash device is much higher than mobile Internet connections[1], and its non-volatile feature makes it very suitable as the cache device of Internet cloud storage on portable device, which often have unstable power supply and intermittent Internet connection. In the present work, NAFFS is evaluated with several benchmarks, and its performance is compared with traditional network attached file systems, such as NFS. Our evaluation results indicate that the NAFFS achieves an average accessing speed of 3.38MB/s, which is about 3 times faster than directly accessing cloud storage by mobile Internet connection， and offers a more stable interface than that of directly using cloud storage API. Unstable Internet connection and sudden power off condition are tolerable, and no data in cache will be lost in such situation.

A large-scale cryoelectronic system for biological sample banking

NASA Astrophysics Data System (ADS)

Shirley, Stephen G.; Durst, Christopher H. P.; Fuchs, Christian C.; Zimmermann, Heiko; Ihmig, Frank R.

2009-11-01

We describe a polymorphic electronic infrastructure for managing biological samples stored over liquid nitrogen. As part of this system we have developed new cryocontainers and carrier plates attached to Flash memory chips to have a redundant and portable set of data at each sample. Our experimental investigations show that basic Flash operation and endurance is adequate for the application down to liquid nitrogen temperatures. This identification technology can provide the best sample identification, documentation and tracking that brings added value to each sample. The first application of the system is in a worldwide collaborative research towards the production of an AIDS vaccine. The functionality and versatility of the system can lead to an essential optimization of sample and data exchange for global clinical studies.

A system-level approach for embedded memory robustness

NASA Astrophysics Data System (ADS)

Mariani, Riccardo; Boschi, Gabriele

2005-11-01

New ultra-deep submicron technologies are bringing not only new advantages such extraordinary transistor densities or unforeseen performances, but also new uncertainties such soft-error susceptibility, modelling complexity, coupling effects, leakage contribution and increased sensitivity to internal and external disturbs. Nowadays, embedded memories are taking profit of such new technologies and they are more and more used in systems: therefore as robustness and reliability requirement increase, memory systems must be protected against different kind of faults (permanent and transient) and that should be done in an efficient way. It means that reliability and costs, such overhead and performance degradation, must be efficiently tuned based on the system and on the application. Moreover, the new emerging norms for safety-critical applications such IEC 61508 are requiring precise answers in terms of robustness also in the case of memory systems. In this paper, classical protection techniques for error detection and correction are enriched with a system-aware approach, where the memory system is analyzed based on its role in the application. A configurable memory protection system is presented, together with the results of its application to a proof-of-concept architecture. This work has been developed in the framework of MEDEA+ T126 project called BLUEBERRIES.

Network-Capable Application Process and Wireless Intelligent Sensors for ISHM

NASA Technical Reports Server (NTRS)

Figueroa, Fernando; Morris, Jon; Turowski, Mark; Wang, Ray

2011-01-01

Intelligent sensor technology and systems are increasingly becoming attractive means to serve as frameworks for intelligent rocket test facilities with embedded intelligent sensor elements, distributed data acquisition elements, and onboard data acquisition elements. Networked intelligent processors enable users and systems integrators to automatically configure their measurement automation systems for analog sensors. NASA and leading sensor vendors are working together to apply the IEEE 1451 standard for adding plug-and-play capabilities for wireless analog transducers through the use of a Transducer Electronic Data Sheet (TEDS) in order to simplify sensor setup, use, and maintenance, to automatically obtain calibration data, and to eliminate manual data entry and error. A TEDS contains the critical information needed by an instrument or measurement system to identify, characterize, interface, and properly use the signal from an analog sensor. A TEDS is deployed for a sensor in one of two ways. First, the TEDS can reside in embedded, nonvolatile memory (typically flash memory) within the intelligent processor. Second, a virtual TEDS can exist as a separate file, downloadable from the Internet. This concept of virtual TEDS extends the benefits of the standardized TEDS to legacy sensors and applications where the embedded memory is not available. An HTML-based user interface provides a visual tool to interface with those distributed sensors that a TEDS is associated with, to automate the sensor management process. Implementing and deploying the IEEE 1451.1-based Network-Capable Application Process (NCAP) can achieve support for intelligent process in Integrated Systems Health Management (ISHM) for the purpose of monitoring, detection of anomalies, diagnosis of causes of anomalies, prediction of future anomalies, mitigation to maintain operability, and integrated awareness of system health by the operator. It can also support local data collection and storage. This invention enables wide-area sensing and employs numerous globally distributed sensing devices that observe the physical world through the existing sensor network. This innovation enables distributed storage, distributed processing, distributed intelligence, and the availability of DiaK (Data, Information, and Knowledge) to any element as needed. It also enables the simultaneous execution of multiple processes, and represents models that contribute to the determination of the condition and health of each element in the system. The NCAP (intelligent process) can configure data-collection and filtering processes in reaction to sensed data, allowing it to decide when and how to adapt collection and processing with regard to sophisticated analysis of data derived from multiple sensors. The user will be able to view the sensing device network as a single unit that supports a high-level query language. Each query would be able to operate over data collected from across the global sensor network just as a search query encompasses millions of Web pages. The sensor web can preserve ubiquitous information access between the querier and the queried data. Pervasive monitoring of the physical world raises significant data and privacy concerns. This innovation enables different authorities to control portions of the sensing infrastructure, and sensor service authors may wish to compose services across authority boundaries.

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Ye, Zhengmao; Luo, Kang; Irving, J. W.; Lu, Xiaoming; Zhang, Wei; Fletcher, Brian; Liu, Weijun; Xu, Frank; LaBrake, Dwayne; Resnick, Douglas; Sreenivasan, S. V.

2013-03-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2014-12-08

Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative ofmore » the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.« less

Memory for Items and Relationships among Items Embedded in Realistic Scenes: Disproportionate Relational Memory Impairments in Amnesia

PubMed Central

Hannula, Deborah E.; Tranel, Daniel; Allen, John S.; Kirchhoff, Brenda A.; Nickel, Allison E.; Cohen, Neal J.

2014-01-01

Objective The objective of this study was to examine the dependence of item memory and relational memory on medial temporal lobe (MTL) structures. Patients with amnesia, who either had extensive MTL damage or damage that was relatively restricted to the hippocampus, were tested, as was a matched comparison group. Disproportionate relational memory impairments were predicted for both patient groups, and those with extensive MTL damage were also expected to have impaired item memory. Method Participants studied scenes, and were tested with interleaved two-alternative forced-choice probe trials. Probe trials were either presented immediately after the corresponding study trial (lag 1), five trials later (lag 5), or nine trials later (lag 9) and consisted of the studied scene along with a manipulated version of that scene in which one item was replaced with a different exemplar (item memory test) or was moved to a new location (relational memory test). Participants were to identify the exact match of the studied scene. Results As predicted, patients were disproportionately impaired on the test of relational memory. Item memory performance was marginally poorer among patients with extensive MTL damage, but both groups were impaired relative to matched comparison participants. Impaired performance was evident at all lags, including the shortest possible lag (lag 1). Conclusions The results are consistent with the proposed role of the hippocampus in relational memory binding and representation, even at short delays, and suggest that the hippocampus may also contribute to successful item memory when items are embedded in complex scenes. PMID:25068665

Nanoscale Reactive Ion Etching of Silicon Nitride Thin Films for Embedded Nanomagnetic Device Fabrication

NASA Astrophysics Data System (ADS)

Hibbard-Lubow, David Luke

The demands of digital memory have increased exponentially in recent history, requiring faster, smaller and more accurate storage methods. Two promising solutions to this ever-present problem are Bit Patterned Media (BPM) and Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). Producing these technologies requires difficult and expensive fabrication techniques. Thus, the production processes must be optimized to allow these storage methods to compete commercially while continuing to increase their information storage density and reliability. I developed a process for the production of nanomagnetic devices (which can take the form of several types of digital memory) embedded in thin silicon nitride films. My focus was on optimizing the reactive ion etching recipe required to embed the device in the film. Ultimately, I found that recipe 37 (Power: 250W, CF4 nominal/actual flow rate: 25/25.4 sccm, O2 nominal/actual flow rate: 3.1/5.2 sccm, which gave a maximum pressure around 400 mTorr) gave the most repeatable and anisotropic results. I successfully used processes described in this thesis to make embedded nanomagnets, which could be used as bit patterned media. Another promising application of this work is to make embedded magnetic tunneling junctions, which are the storage medium used in MRAM. Doing so will require still some tweaks to the fabrication methods. Techniques for making these changes and their potential effects are discussed.

Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications

NASA Astrophysics Data System (ADS)

He, Long-Fei; Zhu, Hao; Xu, Jing; Liu, Hao; Nie, Xin-Ran; Chen, Lin; Sun, Qing-Qing; Xia, Yang; Wei Zhang, David

2017-11-01

The continuous scaling and challenges in device integrations in modern portable electronic products have aroused many scientific interests, and a great deal of effort has been made in seeking solutions towards a more microminiaturized package assembled with smaller and more powerful components. In this study, an embedded light-erasable charge-trapping memory with a high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel has been fabricated and fully characterized. The memory exhibits a sufficient memory window, fast programming and erasing (P/E) speed, and high On/Off current ratio up to 107. Less than 25% memory window degradation is observed after projected 10-year retention, and the device functions perfectly after 8000 P/E operation cycles. Furthermore, the programmed device can be fully erased by incident light without electrical assistance. Such excellent memory performance originates from the intrinsic properties of two-dimensional (2D) MoS2 and the engineered back-gate dielectric stack. Our integration of 2D semiconductors in the infrastructure of light-erasable charge-trapping memory is very promising for future system-on-panel applications like storage of metadata and flexible imaging arrays.

Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

NASA Technical Reports Server (NTRS)

John, Caroline S.; MacLeod, Todd C.; Evans, Joe; Ho, Fat D.

2011-01-01

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Memory for radio advertisements: the effect of program and typicality.

PubMed

Martín-Luengo, Beatriz; Luna, Karlos; Migueles, Malen

2013-01-01

We examined the influence of the type of radio program on the memory for radio advertisements. We also investigated the role in memory of the typicality (high or low) of the elements of the products advertised. Participants listened to three types of programs (interesting, boring, enjoyable) with two advertisements embedded in each. After completing a filler task, the participants performed a true/false recognition test. Hits and false alarm rates were higher for the interesting and enjoyable programs than for the boring one. There were also more hits and false alarms for the high-typicality elements. The response criterion for the advertisements embedded in the boring program was stricter than for the advertisements in other types of programs. We conclude that the type of program in which an advertisement is inserted and the nature of the elements of the advertisement affect both the number of hits and false alarms and the response criterion, but not the accuracy of the memory.

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7

NASA Astrophysics Data System (ADS)

Appeltans, Raf; Weckx, Pieter; Raghavan, Praveen; Kim, Ryoung-Han; Kar, Gouri Sankar; Furnémont, Arnaud; Van der Perre, Liesbet; Dehaene, Wim

2017-03-01

Static Random Access Memory (SRAM) cells are used together with logic standard cells as the benchmark to develop the process flow for new logic technologies. In order to achieve successful integration of Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as area efficient higher level embedded cache, it also needs to be included as a benchmark. The simple cell structure of STT-MRAM brings extra patterning challenges to achieve high density. The two memory types are compared in terms of minimum area and critical design rules in both the iN10 and iN7 node, with an extra focus on patterning options in iN7. Both the use of Self-Aligned Quadruple Patterning (SAQP) mandrel and spacer engineering, as well as multi-level via's are explored. These patterning options result in large area gains for the STT-MRAM cell and moreover determine which cell variant is the smallest.

The LivePhoto Physics videos and video analysis site

NASA Astrophysics Data System (ADS)

Abbott, David

2009-09-01

The LivePhoto site is similar to an archive of short films for video analysis. Some videos have Flash tools for analyzing the video embedded in the movie. Most of the videos address mechanics topics with titles like Rolling Pencil (check this one out for pedagogy and content knowledge—nicely done!), Juggler, Yo-yo, Puck and Bar (this one is an inelastic collision with rotation), but there are a few titles in other areas (E&M, waves, thermo, etc.).

Wearable Wireless Sensor for Multi-Scale Physiological Monitoring

DTIC Science & Technology

2013-10-01

AD_________________ Award Number: W81XWH-12-1-0541 TITLE: Wearable Wireless Sensor for Multi-Scale...TYPE Annual 3. DATES COVERED 25 12- 13 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Wearable Wireless Sensor for Multi-Scale Physiological...peripheral management • Procedures for low power mode activation and wake - up • Routines for start- up state detection • Flash memory management

A Public + Private Mashup for Computer Science Education

ERIC Educational Resources Information Center

Wang, Kevin

2013-01-01

Getting called into the boss's office isn't always fun. Memories of trips to the school principal's office flash through one's mind. But the day last year that the author was called in to meet with their division vice president turned out to be a very good day. Executives at his company, Microsoft, had noticed the program he created in his spare…

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

ReHypar: A Recursive Hybrid Chunk Partitioning Method Using NAND-Flash Memory SSD

PubMed Central

Park, Sung-Soon; Lim, Cheol-Su

2014-01-01

Due to the rapid development of flash memory, SSD is considered to be the replacement of HDD in the storage market. Although SSD retains several promising characteristics, such as high random I/O performance and nonvolatility, its high expense per capacity is the main obstacle in replacing HDD in all storage solutions. An alternative is to provide a hybrid structure where a small portion of SSD address space is combined with the much larger HDD address space. In such a structure, maximizing the space utilization of SSD in a cost-effective way is extremely important to generate high I/O performance. We developed ReHypar (recursive hybrid chunk partitioning) that enables improving the space utilization of SSD in the hybrid structure. The first objective of ReHypar is to mitigate the fragmentation overhead of SSD address space, by reusing the remaining free space of I/O units as much as possible. Furthermore, ReHypar allows defining several, logical data sections in SSD address space, with each of those sections being configured with the different I/O unit. We integrated ReHypar with ext2 and ext4 and evaluated it using two public benchmarks including IOzone and Postmark. PMID:24987741

Effects of normal aging and Alzheimer's disease on emotional memory.

PubMed

Kensinger, Elizabeth A; Brierley, Barbara; Medford, Nick; Growdon, John H; Corkin, Suzanne

2002-06-01

Recall is typically better for emotional than for neutral stimuli. This enhancement is believed to rely on limbic regions. Memory is also better for neutral stimuli embedded in an emotional context. The neural substrate supporting this effect has not been thoroughly investigated but may include frontal lobe, as well as limbic circuits. Alzheimer's disease (AD) results in atrophy of limbic structures, whereas normal aging relatively spares limbic regions but affects prefrontal areas. The authors hypothesized that AD would reduce all enhancement effects, whereas aging would disproportionately affect enhancement based on emotional context. The results confirmed the authors' hypotheses: Young and older adults, but not AD patients, showed better memory for emotional versus neutral pictures and words. Older adults and AD patients showed no benefit from emotional context, whereas young adults remembered more items embedded in an emotional versus neutral context.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Light flash phenomena induced by HzE particles

NASA Technical Reports Server (NTRS)

Mcnulty, P. J.; Pease, V. P.

1980-01-01

Astronauts and Apollo and Skylab missions have reported observing a variety of visual phenomena when their eyes are closed and adapted to darkness. These phenomena have been collectively labelled as light flashes. Visual phenomena which are similar in appearance to those observed in space have been demonstrated at the number of accelerator facilities by expressing the eyes of human subjects to beams of various types of radiation. In some laboratory experiments Cerenkov radiation was found to be the basis for the flashes observed while in other experiments Cerenkov radiation could apparently be ruled out. Experiments that differentiate between Cerenkov radiation and other possible mechanisms for inducing visual phenomena was then compared. The phenomena obtained in the presence and absence of Cerenkov radiation were designed and conducted. A new mechanism proposed to explain the visual phenomena observed by Skylab astronauts as they passed through the South Atlantic Anomaly, namely nuclear interactions in and near the sensitive layer of the retina, is covered. Also some studies to search for similar transient effects of space radiation on sensors and microcomputer memories are described.

Real-time depth processing for embedded platforms

NASA Astrophysics Data System (ADS)

Rahnama, Oscar; Makarov, Aleksej; Torr, Philip

2017-05-01

Obtaining depth information of a scene is an important requirement in many computer-vision and robotics applications. For embedded platforms, passive stereo systems have many advantages over their active counterparts (i.e. LiDAR, Infrared). They are power efficient, cheap, robust to lighting conditions and inherently synchronized to the RGB images of the scene. However, stereo depth estimation is a computationally expensive task that operates over large amounts of data. For embedded applications which are often constrained by power consumption, obtaining accurate results in real-time is a challenge. We demonstrate a computationally and memory efficient implementation of a stereo block-matching algorithm in FPGA. The computational core achieves a throughput of 577 fps at standard VGA resolution whilst consuming less than 3 Watts of power. The data is processed using an in-stream approach that minimizes memory-access bottlenecks and best matches the raster scan readout of modern digital image sensors.

Word embeddings and recurrent neural networks based on Long-Short Term Memory nodes in supervised biomedical word sense disambiguation.

PubMed

Jimeno Yepes, Antonio

2017-09-01

Word sense disambiguation helps identifying the proper sense of ambiguous words in text. With large terminologies such as the UMLS Metathesaurus ambiguities appear and highly effective disambiguation methods are required. Supervised learning algorithm methods are used as one of the approaches to perform disambiguation. Features extracted from the context of an ambiguous word are used to identify the proper sense of such a word. The type of features have an impact on machine learning methods, thus affect disambiguation performance. In this work, we have evaluated several types of features derived from the context of the ambiguous word and we have explored as well more global features derived from MEDLINE using word embeddings. Results show that word embeddings improve the performance of more traditional features and allow as well using recurrent neural network classifiers based on Long-Short Term Memory (LSTM) nodes. The combination of unigrams and word embeddings with an SVM sets a new state of the art performance with a macro accuracy of 95.97 in the MSH WSD data set. Copyright © 2017 Elsevier Inc. All rights reserved.

A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

NASA Astrophysics Data System (ADS)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

Flash Spectroscopy: Emission Lines From the Ionized Circumstellar Material Around 10-Day-Old Type II Supernovae

NASA Technical Reports Server (NTRS)

Khazov, D.; Yaron, O.; Gal-Yam, A.; Manulis, I.; Rubin, A.; Kulkarni, S. R.; Arcavi, I.; Kasliwal, M. M.; Ofek, E. O.; Cao, Y.;

ADAPTIVE METHODS FOR STOCHASTIC DIFFERENTIAL EQUATIONS VIA NATURAL EMBEDDINGS AND REJECTION SAMPLING WITH MEMORY.

PubMed

Rackauckas, Christopher; Nie, Qing

2017-01-01

Adaptive time-stepping with high-order embedded Runge-Kutta pairs and rejection sampling provides efficient approaches for solving differential equations. While many such methods exist for solving deterministic systems, little progress has been made for stochastic variants. One challenge in developing adaptive methods for stochastic differential equations (SDEs) is the construction of embedded schemes with direct error estimates. We present a new class of embedded stochastic Runge-Kutta (SRK) methods with strong order 1.5 which have a natural embedding of strong order 1.0 methods. This allows for the derivation of an error estimate which requires no additional function evaluations. Next we derive a general method to reject the time steps without losing information about the future Brownian path termed Rejection Sampling with Memory (RSwM). This method utilizes a stack data structure to do rejection sampling, costing only a few floating point calculations. We show numerically that the methods generate statistically-correct and tolerance-controlled solutions. Lastly, we show that this form of adaptivity can be applied to systems of equations, and demonstrate that it solves a stiff biological model 12.28x faster than common fixed timestep algorithms. Our approach only requires the solution to a bridging problem and thus lends itself to natural generalizations beyond SDEs.

ADAPTIVE METHODS FOR STOCHASTIC DIFFERENTIAL EQUATIONS VIA NATURAL EMBEDDINGS AND REJECTION SAMPLING WITH MEMORY

PubMed Central

Rackauckas, Christopher

2017-01-01

Adaptive time-stepping with high-order embedded Runge-Kutta pairs and rejection sampling provides efficient approaches for solving differential equations. While many such methods exist for solving deterministic systems, little progress has been made for stochastic variants. One challenge in developing adaptive methods for stochastic differential equations (SDEs) is the construction of embedded schemes with direct error estimates. We present a new class of embedded stochastic Runge-Kutta (SRK) methods with strong order 1.5 which have a natural embedding of strong order 1.0 methods. This allows for the derivation of an error estimate which requires no additional function evaluations. Next we derive a general method to reject the time steps without losing information about the future Brownian path termed Rejection Sampling with Memory (RSwM). This method utilizes a stack data structure to do rejection sampling, costing only a few floating point calculations. We show numerically that the methods generate statistically-correct and tolerance-controlled solutions. Lastly, we show that this form of adaptivity can be applied to systems of equations, and demonstrate that it solves a stiff biological model 12.28x faster than common fixed timestep algorithms. Our approach only requires the solution to a bridging problem and thus lends itself to natural generalizations beyond SDEs. PMID:29527134

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures.

PubMed

Abhijith, T; Kumar, T V Arun; Reddy, V S

2017-03-03

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO 3 ) between two tris-(8-hydroxyquinoline)aluminum (Alq 3 ) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 10 3 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO 3 layer thickness and its location in the Alq 3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO 3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

NASA Astrophysics Data System (ADS)

Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

2017-03-01

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

76 FR 2681 - Amended Environmental Impact Statement Filing System Guidance for Implementing 40 CFR 1506.9 and...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-14

...., compact discs (CDs), USB flash drives, or memory cards. Please note that if a Federal agency prepares an... of the NOA in the Federal Register. If a calculated time period would end on a non- working day, the assigned time period will be the next working day (i.e., time periods will not end on weekends or Federal...

Highly Asynchronous VisitOr Queue Graph Toolkit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pearce, R.

2012-10-01

HAVOQGT is a C++ framework that can be used to create highly parallel graph traversal algorithms. The framework stores the graph and algorithmic data structures on external memory that is typically mapped to high performance locally attached NAND FLASH arrays. The framework supports a vertex-centered visitor programming model. The frameworkd has been used to implement breadth first search, connected components, and single source shortest path.

Research and Development of Collaborative Environments for Command and Control

DTIC Science & Technology

2011-05-01

at any state of building. The viewer tool presents the designed model with 360-degree perspective views even after regeneration of the design, which...and it shows the following prompt. GUM > APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED...11 First initialize the microSD card by typing GUM > mmcinit Then erase the old Linux kernel and the root file system on the flash memory

Temporal dynamics of encoding, storage and reallocation of visual working memory

PubMed Central

Bays, Paul M; Gorgoraptis, Nikos; Wee, Natalie; Marshall, Louise; Husain, Masud

2012-01-01

The process of encoding a visual scene into working memory has previously been studied using binary measures of recall. Here we examine the temporal evolution of memory resolution, based on observers’ ability to reproduce the orientations of objects presented in brief, masked displays. Recall precision was accurately described by the interaction of two independent constraints: an encoding limit that determines the maximum rate at which information can be transferred into memory, and a separate storage limit that determines the maximum fidelity with which information can be maintained. Recall variability decreased incrementally with time, consistent with a parallel encoding process in which visual information from multiple objects accumulates simultaneously in working memory. No evidence was observed for a limit on the number of items stored. Cueing one display item with a brief flash led to rapid development of a recall advantage for that item. This advantage was short-lived if the cue was simply a salient visual event, but was maintained if it indicated an object of particular relevance to the task. These cueing effects were observed even for items that had already been encoded into memory, indicating that limited memory resources can be rapidly reallocated to prioritize salient or goal-relevant information. PMID:21911739

Temporal dynamics of encoding, storage, and reallocation of visual working memory.

PubMed

Bays, Paul M; Gorgoraptis, Nikos; Wee, Natalie; Marshall, Louise; Husain, Masud

2011-09-12

The process of encoding a visual scene into working memory has previously been studied using binary measures of recall. Here, we examine the temporal evolution of memory resolution, based on observers' ability to reproduce the orientations of objects presented in brief, masked displays. Recall precision was accurately described by the interaction of two independent constraints: an encoding limit that determines the maximum rate at which information can be transferred into memory and a separate storage limit that determines the maximum fidelity with which information can be maintained. Recall variability decreased incrementally with time, consistent with a parallel encoding process in which visual information from multiple objects accumulates simultaneously in working memory. No evidence was observed for a limit on the number of items stored. Cuing one display item with a brief flash led to rapid development of a recall advantage for that item. This advantage was short-lived if the cue was simply a salient visual event but was maintained if it indicated an object of particular relevance to the task. These cuing effects were observed even for items that had already been encoded into memory, indicating that limited memory resources can be rapidly reallocated to prioritize salient or goal-relevant information.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

NASA Astrophysics Data System (ADS)

Cristoloveanu, S.; Lee, K. H.; Parihar, M. S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J.-Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y.-T.; Wan, J.; Bawedin, M.

2018-05-01

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Episodic memories.

PubMed

Conway, Martin A

2009-09-01

An account of episodic memories is developed that focuses on the types of knowledge they represent, their properties, and the functions they might serve. It is proposed that episodic memories consist of episodic elements, summary records of experience often in the form of visual images, associated to a conceptual frame that provides a conceptual context. Episodic memories are embedded in a more complex conceptual system in which they can become the basis of autobiographical memories. However, the function of episodic memories is to keep a record of progress with short-term goals and access to most episodic memories is lost soon after their formation. Finally, it is suggested that developmentally episodic memories form the basis of the conceptual system and it is from sets of episodic memories that early non-verbal conceptual knowledge is abstracted.

Cross-linguistic Differences in Processing Double-Embedded Relative Clauses: Working-Memory Constraints or Language Statistics?

ERIC Educational Resources Information Center

Frank, Stefan L.; Trompenaars, Thijs; Vasishth, Shravan

2016-01-01

An English double-embedded relative clause from which the middle verb is omitted can often be processed more easily than its grammatical counterpart, a phenomenon known as the grammaticality illusion. This effect has been found to be reversed in German, suggesting that the illusion is language specific rather than a consequence of universal…

Syntactic Complexity Effects of Russian Relative Clause Sentences in Children with and without Developmental Language Disorder

PubMed Central

Rakhlin, Natalia; Kornilov, Sergey A.; Kornilova, Tatiana V.

2016-01-01

We investigated relative clause (RC) comprehension in 44 Russian-speaking children with typical language (TD) and developmental language disorder (DLD); M age = 10.67, SD = 2.84, and 22 adults. Flexible word order and morphological case in Russian allowed us to isolate factors that are obscured in English, helping us to identify sources of syntactic complexity and evaluate their roles in RC comprehension by children with typical language and their peers with DLD. We administered a working memory and an RC comprehension (picture-choice) task, which contained subject- and object-gap center-embedded and right branching RCs. The TD group, but not adults, demonstrated the effects of gap, embedding, and case. Their lower accuracy relative to adults was not fully attributable to differences in working memory. The DLD group displayed lower than TD children overall accuracy, accounted for by their lower working memory scores. While the effect of gap and embedding on their performance was not different from what was found for the TD group, children with DLD exhibited a diminished effect of case, suggesting reduced sensitivity to morphological case markers as processing cues. The implications of these results to theories of syntactic complexity and core deficits in DLD are discussed. PMID:28626347

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

A qualitative study on personal information management (PIM) in clinical and basic sciences faculty members of a medical university in Iran

PubMed Central

Sedghi, Shahram; Abdolahi, Nida; Azimi, Ali; Tahamtan, Iman; Abdollahi, Leila

2015-01-01

Background: Personal Information Management (PIM) refers to the tools and activities to save and retrieve personal information for future uses. This study examined the PIM activities of faculty members of Iran University of Medical Sciences (IUMS) regarding their preferred PIM tools and four aspects of acquiring, organizing, storing and retrieving personal information. Methods: The qualitative design was based on phenomenology approach and we carried out 37 interviews with clinical and basic sciences faculty members of IUMS in 2014. The participants were selected using a random sampling method. All interviews were recorded by a digital voice recorder, and then transcribed, codified and finally analyzed using NVivo 8 software. Results: The use of PIM electronic tools (e-tools) was below expectation among the studied sample and just 37% had reasonable knowledge of PIM e-tools such as, external hard drivers, flash memories etc. However, all participants used both paper and electronic devices to store and access information. Internal mass memories (in Laptops) and flash memories were the most used e-tools to save information. Most participants used "subject" (41.00%) and "file name" (33.7 %) to save, organize and retrieve their stored information. Most users preferred paper-based rather than electronic tools to keep their personal information. Conclusion: Faculty members had little knowledge about PIM techniques and tools. Those who organized personal information could easier retrieve the stored information for future uses. Enhancing familiarity with PIM tools and training courses of PIM tools and techniques are suggested. PMID:26793648

Brownmillerite thin films as fast ion conductors for ultimate-performance resistance switching memory.

PubMed

Acharya, Susant Kumar; Jo, Janghyun; Raveendra, Nallagatlla Venkata; Dash, Umasankar; Kim, Miyoung; Baik, Hionsuck; Lee, Sangik; Park, Bae Ho; Lee, Jae Sung; Chae, Seung Chul; Hwang, Cheol Seong; Jung, Chang Uk

2017-07-27

An oxide-based resistance memory is a leading candidate to replace Si-based flash memory as it meets the emerging specifications for future memory devices. The non-uniformity in the key switching parameters and low endurance in conventional resistance memory devices are preventing its practical application. Here, a novel strategy to overcome the aforementioned challenges has been unveiled by tuning the growth direction of epitaxial brownmillerite SrFeO 2.5 thin films along the SrTiO 3 [111] direction so that the oxygen vacancy channels can connect both the top and bottom electrodes rather directly. The controlled oxygen vacancy channels help reduce the randomness of the conducting filament (CF). The resulting device displayed high endurance over 10 6 cycles, and a short switching time of ∼10 ns. In addition, the device showed very high uniformity in the key switching parameters for device-to-device and within a device. This work demonstrates a feasible example for improving the nanoscale device performance by controlling the atomic structure of a functional oxide layer.

Fusion Helmet: Electronic Analysis

DTIC Science & Technology

2014-04-01

Table 1: LYR203-101B Board Feature P1 (SEC MODULE) DM648 GPIO PORn Video Ports (2) Bootmode SPI/UART I2C CLKIN MDIO DDR2 128MB/16bit SPI Flash 16...McASP EMAC-SGMII /2 MDIO I2C GPIO DDR2 128MB/16bit JTAG Memory CLKGEN I2C PGoodPGood PORn Pwr LED Power DSP SPI/UART DSP SPI/UARTSPI/UART Video Display

Pigeons' Memory for Number of Events: Effects of Intertrial Interval and Delay Interval Illumination

ERIC Educational Resources Information Center

Hope, Chris; Santi, Angelo

2004-01-01

In Experiment 1, pigeons were trained at a 0-s baseline delay to discriminate sequences of light flashes (illumination of the feeder) that varied in number but not time (2f/4s and 8f/4s). During training, the intertrial interval was illuminated by the houselight for Group Light, but it was dark for Group Dark. Testing conducted with dark delay…

Smart Cards and remote entrusting

NASA Astrophysics Data System (ADS)

Aussel, Jean-Daniel; D'Annoville, Jerome; Castillo, Laurent; Durand, Stephane; Fabre, Thierry; Lu, Karen; Ali, Asad

Smart cards are widely used to provide security in end-to-end communication involving servers and a variety of terminals, including mobile handsets or payment terminals. Sometime, end-to-end server to smart card security is not applicable, and smart cards must communicate directly with an application executing on a terminal, like a personal computer, without communicating with a server. In this case, the smart card must somehow trust the terminal application before performing some secure operation it was designed for. This paper presents a novel method to remotely trust a terminal application from the smart card. For terminals such as personal computers, this method is based on an advanced secure device connected through the USB and consisting of a smart card bundled with flash memory. This device, or USB dongle, can be used in the context of remote untrusting to secure portable applications conveyed in the dongle flash memory. White-box cryptography is used to set the secure channel and a mechanism based on thumbprint is described to provide external authentication when session keys need to be renewed. Although not as secure as end-to-end server to smart card security, remote entrusting with smart cards is easy to deploy for mass-market applications and can provide a reasonable level of security.

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

Sb7Te3/Ge multilayer films for low power and high speed phase-change memory

NASA Astrophysics Data System (ADS)

Chen, Shiyu; Wu, Weihua; Zhai, Jiwei; Song, Sannian; Song, Zhitang

2017-06-01

Phase-change memory has attracted enormous attention for its excellent properties as compared to flash memories due to their high speed, high density, better date retention and low power consumption. Here we present Sb7Te3/Ge multilayer films by using a magnetron sputtering method. The 10 years’ data retention temperature is significantly increased compared with pure Sb7Te3. When the annealing temperature is above 250 °C, the Sb7Te3/Ge multilayer thin films have better interface properties, which renders faster crystallization speed and high thermal stability. The decrease in density of ST/Ge multilayer films is only around 5%, which is very suitable for phase change materials. Moreover, the low RESET power benefits from high resistivity and better thermal stability in the PCM cells. This work demonstrates that the multilayer configuration thin films with tailored properties are beneficial for improving the stability and speed in phase change memory applications.

Dynamic Organization of Hierarchical Memories

PubMed Central

Kurikawa, Tomoki; Kaneko, Kunihiko

2016-01-01

In the brain, external objects are categorized in a hierarchical way. Although it is widely accepted that objects are represented as static attractors in neural state space, this view does not take account interaction between intrinsic neural dynamics and external input, which is essential to understand how neural system responds to inputs. Indeed, structured spontaneous neural activity without external inputs is known to exist, and its relationship with evoked activities is discussed. Then, how categorical representation is embedded into the spontaneous and evoked activities has to be uncovered. To address this question, we studied bifurcation process with increasing input after hierarchically clustered associative memories are learned. We found a “dynamic categorization”; neural activity without input wanders globally over the state space including all memories. Then with the increase of input strength, diffuse representation of higher category exhibits transitions to focused ones specific to each object. The hierarchy of memories is embedded in the transition probability from one memory to another during the spontaneous dynamics. With increased input strength, neural activity wanders over a narrower state space including a smaller set of memories, showing more specific category or memory corresponding to the applied input. Moreover, such coarse-to-fine transitions are also observed temporally during transient process under constant input, which agrees with experimental findings in the temporal cortex. These results suggest the hierarchy emerging through interaction with an external input underlies hierarchy during transient process, as well as in the spontaneous activity. PMID:27618549

Interpreter composition issues in the formal verification of a processor-memory module

NASA Technical Reports Server (NTRS)

Fura, David A.; Cohen, Gerald C.

1994-01-01

This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.

Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency

NASA Astrophysics Data System (ADS)

Soderquist, Peter; Leeser, Miriam E.

1999-01-01

Digital video decoding, enabled by the MPEG-2 Video standard, is an important future application for embedded systems, particularly PDAs and other information appliances. Many such system require portability and wireless communication capabilities, and thus face severe limitations in size and power consumption. This places a premium on integration and efficiency, and favors software solutions for video functionality over specialized hardware. The processors in most embedded system currently lack the computational power needed to perform video decoding, but a related and equally important problem is the required data bandwidth, and the need to cost-effectively insure adequate data supply. MPEG data sets are very large, and generate significant amounts of excess memory traffic for standard data caches, up to 100 times the amount required for decoding. Meanwhile, cost and power limitations restrict cache sizes in embedded systems. Some systems, including many media processors, eliminate caches in favor of memories under direct, painstaking software control in the manner of digital signal processors. Yet MPEG data has locality which caches can exploit if properly optimized, providing fast, flexible, and automatic data supply. We propose a set of enhancements which target the specific needs of the heterogeneous types within the MPEG decoder working set. These optimizations significantly improve the efficiency of small caches, reducing cache-memory traffic by almost 70 percent, and can make an enhanced 4 KB cache perform better than a standard 1 MB cache. This performance improvement can enable high-resolution, full frame rate video playback in cheaper, smaller system than woudl otherwise be possible.

Nanoscale cross-point diode array accessing embedded high density PCM

NASA Astrophysics Data System (ADS)

Wang, Heng; Liu, Yan; Liu, Bo; Gao, Dan; Xu, Zhen; Zhan, Yipeng; Song, Zhitang; Feng, Songlin

2017-08-01

The main bottlenecks in the development of current embedded phase change memory (PCM) technology are the current density and data storage density. In this paper, we present a PCM with 4F2 cross-point diode selector and blade-type bottom electrode contact (BEC). A blade TiN BEC with a cross-sectional area of 630 nm2 (10 nm × 63 nm) reduces the reset current down to about 750 μA. The optimized diode array could supply this 750 μA reset current at about 1.7 V and low off-current 1 × 10-4 μA at about -5.05 V. The on-off ratio of this device is 7.5 × 106. The proposed nanoscale PCM device simultaneously exhibits an operation voltage as low as 3 V and a high density drive current with an ultra small cell size of 4F2 (108 nm × 108 nm). Over 106 cycling endurance properties guarantee that it can work effectively on the embedded memory.

KSC-05PD-0565

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. In the Vehicle Assembly Building at NASAs Kennedy Space Center, a digital still camera has been mounted in the External Tank (ET) umbilical well on the aft end of Space Shuttle Discovery. The camera is being used to obtain and downlink high-resolution images of the disconnect point on the ET following ET separation from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-05PD-0562

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. In the Vehicle Assembly Building at NASAs Kennedy Space Center, workers check the digital still camera they will mount in the External Tank (ET) umbilical well on the aft end of Space Shuttle Discovery. The camera is being used to obtain and downlink high-resolution images of the disconnect point on the ET following the tank's separation from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-05PD-0564

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. In the Vehicle Assembly Building at NASAs Kennedy Space Center, a worker mounts a digital still camera in the External Tank (ET) umbilical well on the aft end of Space Shuttle Discovery. The camera is being used to obtain and downlink high-resolution images of the disconnect point on the ET following the ET separation from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-05PD-0561

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. In the Vehicle Assembly Building at NASAs Kennedy Space Center, workers prepare a digital still camera they will mount in the External Tank (ET) umbilical well on the aft end of Space Shuttle Discovery. The camera is being used to obtain and downlink high-resolution images of the disconnect point on the ET following its separation from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-05PD-0563

NASA Technical Reports Server (NTRS)

2005-01-01

KENNEDY SPACE CENTER, FLA. In the Vehicle Assembly Building at NASAs Kennedy Space Center, workers prepare a digital still camera they will mount in the External Tank (ET) umbilical well on the aft end of Space Shuttle Discovery. The camera is being used to obtain and downlink high-resolution images of the disconnect point on the ET following the ET separation from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

Inverse Resistance Change Cr2Ge2Te6-Based PCRAM Enabling Ultralow-Energy Amorphization.

PubMed

Hatayama, Shogo; Sutou, Yuji; Shindo, Satoshi; Saito, Yuta; Song, Yun-Heub; Ando, Daisuke; Koike, Junichi

2018-01-24

Phase-change random access memory (PCRAM) has attracted much attention for next-generation nonvolatile memory that can replace flash memory and can be used for storage-class memory. Generally, PCRAM relies on the change in the electrical resistance of a phase-change material between high-resistance amorphous (reset) and low-resistance crystalline (set) states. Herein, we present an inverse resistance change PCRAM with Cr 2 Ge 2 Te 6 (CrGT) that shows a high-resistance crystalline reset state and a low-resistance amorphous set state. The inverse resistance change was found to be due to a drastic decrease in the carrier density upon crystallization, which causes a large increase in contact resistivity between CrGT and the electrode. The CrGT memory cell was demonstrated to show fast reversible resistance switching with a much lower operating energy for amorphization than a Ge 2 Sb 2 Te 5 memory cell. This low operating energy in CrGT should be due to a small programmed amorphous volume, which can be realized by a high-resistance crystalline matrix and a dominant contact resistance. Simultaneously, CrGT can break the trade-off relationship between the crystallization temperature and operating speed.

Modeling the Diffuse Cloud-Top Optical Emissions from Ground and Cloud Flashes

NASA Technical Reports Server (NTRS)

Solakiewicz, Richard; Koshak, William

2008-01-01

A number of studies have indicated that the diffuse cloud-top optical emissions from intra-cloud (IC) lightning are brighter than that from normal negative cloud-to-ground (CG) lightning, and hence would be easier to detect from a space-based sensor. The primary reason provided to substantiate this claim has been that the IC is at a higher altitude within the cloud and therefore is less obscured by the cloud multiple scattering medium. CGs at lower altitudes embedded deep within the cloud are more obscured, so CG detection is thought to be more difficult. However, other authors claim that because the CG source current (and hence luminosity) is typically substantially larger than IC currents, the greater CG source luminosity is large enough to overcome the effects of multiple scattering. These investigators suggest that the diffuse cloud top emissions from CGs are brighter than from ICs, and hence are easier to detect from space. Still other investigators claim that the detection efficiency of CGs and ICs is about the same because modern detector sensitivity is good enough to "see" either flash type no matter which produces a brighter cloud top emission. To better assess which of these opinions should be accepted, we introduce an extension of a Boltzmann lightning radiative transfer model previously developed. It considers characteristics of the cloud (geometry, dimensions, scattering properties) and specific lightning channel properties (length, geometry, location, current, optical wave front propagation speed/direction). As such, it represents the most detailed modeling effort to date. At least in the few cases studied thus far, it was found that IC flashes appear brighter at cloud top than the lower altitude negative ground flashes, but additional model runs are to be examined before finalizing our general conclusions.

FLASH SPECTROSCOPY: EMISSION LINES FROM THE IONIZED CIRCUMSTELLAR MATERIAL AROUND <10-DAY-OLD TYPE II SUPERNOVAE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khazov, D.; Yaron, O.; Gal-Yam, A.

Supernovae (SNe) embedded in dense circumstellar material (CSM) may show prominent emission lines in their early-time spectra (≤10 days after the explosion), owing to recombination of the CSM ionized by the shock-breakout flash. From such spectra (“flash spectroscopy”), we can measure various physical properties of the CSM, as well as the mass-loss rate of the progenitor during the year prior to its explosion. Searching through the Palomar Transient Factory (PTF and iPTF) SN spectroscopy databases from 2009 through 2014, we found 12 SNe II showing flash-ionized (FI) signatures in their first spectra. All are younger than 10 days. These eventsmore » constitute 14% of all 84 SNe in our sample having a spectrum within 10 days from explosion, and 18% of SNe II observed at ages <5 days, thereby setting lower limits on the fraction of FI events. We classified as “blue/featureless” (BF) those events having a first spectrum that is similar to that of a blackbody, without any emission or absorption signatures. It is possible that some BF events had FI signatures at an earlier phase than observed, or that they lack dense CSM around the progenitor. Within 2 days after explosion, 8 out of 11 SNe in our sample are either BF events or show FI signatures. Interestingly, we found that 19 out of 21 SNe brighter than an absolute magnitude M{sub R} = −18.2 belong to the FI or BF groups, and that all FI events peaked above M{sub R} = −17.6 mag, significantly brighter than average SNe II.« less

Flash Spectroscopy: Emission Lines from the Ionized Circumstellar Material Around <10-Day-Old Type II Supernovae

DOE PAGES

Khazov, Daniel; Yaron, O.; Gal-Yam, A.; ...

2016-02-02

Supernovae (SNe) embedded in dense circumstellar material (CSM) may show prominent emission lines in their early-time spectra (≤10 days after the explosion), owing to recombination of the CSM ionized by the shock-breakout flash. From such spectra ("flash spectroscopy"), we can measure various physical properties of the CSM, as well as the mass-loss rate of the progenitor during the year prior to its explosion. In this paper, by searching through the Palomar Transient Factory (PTF and iPTF) SN spectroscopy databases from 2009 through 2014, we found 12 SNe II showing flash-ionized (FI) signatures in their first spectra. All are younger thanmore » 10 days. These events constitute 14% of all 84 SNe in our sample having a spectrum within 10 days from explosion, and 18% of SNe II observed at ages <5 days, thereby setting lower limits on the fraction of FI events. We classified as "blue/featureless" (BF) those events having a first spectrum that is similar to that of a blackbody, without any emission or absorption signatures. It is possible that some BF events had FI signatures at an earlier phase than observed, or that they lack dense CSM around the progenitor. Within 2 days after explosion, 8 out of 11 SNe in our sample are either BF events or show FI signatures. Finally and interestingly, we found that 19 out of 21 SNe brighter than an absolute magnitude M R = -18.2 belong to the FI or BF groups, and that all FI events peaked above M R = -17.6 mag, significantly brighter than average SNe II.« less

Flash Spectroscopy: Emission Lines from the Ionized Circumstellar Material Around <10-Day-Old Type II Supernovae

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khazov, Daniel; Yaron, O.; Gal-Yam, A.

Supernovae (SNe) embedded in dense circumstellar material (CSM) may show prominent emission lines in their early-time spectra (≤10 days after the explosion), owing to recombination of the CSM ionized by the shock-breakout flash. From such spectra ("flash spectroscopy"), we can measure various physical properties of the CSM, as well as the mass-loss rate of the progenitor during the year prior to its explosion. In this paper, by searching through the Palomar Transient Factory (PTF and iPTF) SN spectroscopy databases from 2009 through 2014, we found 12 SNe II showing flash-ionized (FI) signatures in their first spectra. All are younger thanmore » 10 days. These events constitute 14% of all 84 SNe in our sample having a spectrum within 10 days from explosion, and 18% of SNe II observed at ages <5 days, thereby setting lower limits on the fraction of FI events. We classified as "blue/featureless" (BF) those events having a first spectrum that is similar to that of a blackbody, without any emission or absorption signatures. It is possible that some BF events had FI signatures at an earlier phase than observed, or that they lack dense CSM around the progenitor. Within 2 days after explosion, 8 out of 11 SNe in our sample are either BF events or show FI signatures. Finally and interestingly, we found that 19 out of 21 SNe brighter than an absolute magnitude M R = -18.2 belong to the FI or BF groups, and that all FI events peaked above M R = -17.6 mag, significantly brighter than average SNe II.« less

Using radar-derived parameters to forecast lightning cessation for nonisolated storms

NASA Astrophysics Data System (ADS)

Davey, Matthew J.; Fuelberg, Henry E.

2017-03-01

Lightning impacts operations at the Kennedy Space Center (KSC) and other outdoor venues leading to injuries, inconvenience, and detrimental economic impacts. This research focuses on cases of "nonisolated" lightning which we define as one cell whose flashes have ceased although it is still embedded in weak composite reflectivity (Z ≥ 15 dBZ) with another cell that is still producing flashes. The objective is to determine if any radar-derived parameters provide useful information about the occurrence of lightning cessation in remnant storms. The data set consists of 50 warm season (May-September) nonisolated storms near KSC during 2013. The research utilizes the National Lightning Detection Network, the second generation Lightning Detection and Ranging network, and polarized radar data. These data are merged and analyzed using the Warning Decision Support System-Integrated Information at 1 min intervals. Our approach only considers 62 parameters, most of which are related to the noninductive charging mechanism. They included the presence of graupel at various thermal altitudes, maximum reflectivity of the decaying storm at thermal altitudes, maximum connecting composite reflectivity between the decaying cell and active cell, minutes since the previous flash, and several others. Results showed that none of the parameters reliably indicated lightning cessation for even our restrictive definition of nonisolated storms. Additional research is needed before cessation can be determined operationally with the high degree of accuracy required for safety.

RTSJ Memory Areas and Their Affects on the Performance of a Flight-Like Attitude Control System

NASA Technical Reports Server (NTRS)

Niessner, Albert F.; Benowitz, Edward G.

2003-01-01

The two most important factors in improving performance in any software system, but especially a real-time, embedded system, are knowing which components are the low performers and knowing what can be done to improve their performance. The word performance with respect to a real-time, embedded system does not necessarily mean fast execution, which is the common definition when discussing non real-time systems. It also includes meeting all of the specified execution dead-lines and executing at the correct time without sacrificing non real-time performance. Using a Java prototype of an existing control system used on Deep Space 1[1], the effects from adding memory areas are measured and evaluated with respect to improving performance.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Foundry Technologies Focused on Environmental and Ecological Applications

NASA Astrophysics Data System (ADS)

Roizin, Ya.; Lisiansky, M.; Pikhay, E.

Solutions allowing fabrication of remote control systems with integrated sensors (motes) were introduced as a part of CMOS foundry production platform and verified on silicon. The integrated features include sensors employing principles previously verified in the development of ultra-low power consuming non-volatile memories (C-Flash, MRAM) and components allowing low-power energy harvesting (low voltage rectifiers, high -voltage solar cells). The developed systems are discussed with emphasis on their environmental and security applications.

Modular Electronics for Flash Memory Production

DTIC Science & Technology

2011-12-28

DEFENSE TECHNICAL INFORMATION CENTER ImuM ktkUmlimäj DTICfhas determined on oc öf^H AJI that this Technical Document has the Distribution...the second harmonic (8I2/8V2), and a normalization to remove the scale of the measured current. The red dashed lines represent notable vibrational...superimposed as red dashed lines. The agreement between the two spectroscopies is conclusive that we have successfully put our OPE derivative into the gap

Evaluation of the Radiation Susceptibility of a 3D NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Seidleck, Christina; Kim, Hak; Phan, Anthony; LaBel, Kenneth

2017-01-01

We evaluated the heavy ion and proton-induced single-event effects (SEE) for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of similar density and performance in the multiple-cell level (MLC) storage mode. However, the single-level-cell (SLC) storage mode of the 3D NAND showed significantly reduced SEU susceptibility. Additionally, the 3D NAND showed less MBU susceptibility than the planar NAND, with reduced number of upset bits per byte and reduced cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the latest generation planar NAND, indicating a variable upset rate for a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.

Effects of Presentation Format and List Length on Children's False Memories

ERIC Educational Resources Information Center

Swannell, Ellen R.; Dewhurst, Stephen A.

2013-01-01

The effect of list length on children's false memories was investigated using list and story versions of the Deese/Roediger-McDermott procedure. Short (7 items) and long (14 items) sequences of semantic associates were presented to children aged 6, 8, and 10 years old either in lists or embedded within a story that emphasized the list theme.…

Neuropsychology in a Memory Disorder Clinic.

PubMed

Ruchinskas, Robert A; Cullum, C Munro

2018-05-01

The rationale for and factors related to embedding a neuropsychologist in the midst of a neurology-based memory disorder clinic are discussed. Common conditions encountered are briefly reviewed, along with an evaluation aimed at assisting with differential diagnosis. Advice for neuropsychologists is offered in terms of creating and refining a working model in a neurology clinic and strategies to improve communication and effectiveness are presented.

Thermomechanical Modeling of Shape Memory Alloys and Applications

NASA Astrophysics Data System (ADS)

Lexcellent, C.; Leclercq, S.

The aim of the present paper is a general macroscopic description of the thermomechanical behavior of shape memory alloys (SMA). We use for framework the thermodynamics of irreversible processes. This model is efficient for describing the behavior of "smart" structures as a bronchial, a tentacle element and an prosthesis hybrid structure made of Ti Ni SMA wires embedded in a resin epoxy matrix.

Evaluation of Ferroelectric Materials for Memory Applications

DTIC Science & Technology

1990-06-01

as automobile odometers, access counters, and flight time recorders. Detailed product information is provided in Appendix A. 3. Optical Read...volatility but by definition are not reprogrammable , which severely restricts flexibility and makes error correction difficult. Magnetic core is non...battery-backed SRAMs as well. The programs for embedded controllers, such as those increasingly used in automobiles , are kept in nonvolatile memory. The

Organisational Structure and Information Technology (IT): Exploring the Implications of IT for Future Military Structures

DTIC Science & Technology

2006-07-01

4 Abbreviations AI Artificial Intelligence AM Artificial Memory CAD Computer Aided...memory (AM), artificial intelligence (AI), and embedded knowledge systems it is possible to expand the “effective span of competence” of...Technology J Joint J2 Joint Intelligence J3 Joint Operations NATO North Atlantic Treaty Organisation NCW Network Centric Warfare NHS National Health

Automatic Detection of Steganographic Content

DTIC Science & Technology

2005-06-30

Practically, it is mostly embedded into the media files, especially the image files. Consequently, a lot of the anti- steganography algorithms work with raw...1: not enough memory * -2: error running the removal algorithm EXPORT IMAGE *StegRemove( IMAGE * image , int *error); 2.8 Steganography Extraction API...researcher just invented a reliable algorithm that can detect the existence of a steganography if it is embedded anywhere in any uncompressed image . The

Segregating the core computational faculty of human language from working memory.

PubMed

Makuuchi, Michiru; Bahlmann, Jörg; Anwander, Alfred; Friederici, Angela D

2009-05-19

In contrast to simple structures in animal vocal behavior, hierarchical structures such as center-embedded sentences manifest the core computational faculty of human language. Previous artificial grammar learning studies found that the left pars opercularis (LPO) subserves the processing of hierarchical structures. However, it is not clear whether this area is activated by the structural complexity per se or by the increased memory load entailed in processing hierarchical structures. To dissociate the effect of structural complexity from the effect of memory cost, we conducted a functional magnetic resonance imaging study of German sentence processing with a 2-way factorial design tapping structural complexity (with/without hierarchical structure, i.e., center-embedding of clauses) and working memory load (long/short distance between syntactically dependent elements; i.e., subject nouns and their respective verbs). Functional imaging data revealed that the processes for structure and memory operate separately but co-operatively in the left inferior frontal gyrus; activities in the LPO increased as a function of structural complexity, whereas activities in the left inferior frontal sulcus (LIFS) were modulated by the distance over which the syntactic information had to be transferred. Diffusion tensor imaging showed that these 2 regions were interconnected through white matter fibers. Moreover, functional coupling between the 2 regions was found to increase during the processing of complex, hierarchically structured sentences. These results suggest a neuroanatomical segregation of syntax-related aspects represented in the LPO from memory-related aspects reflected in the LIFS, which are, however, highly interconnected functionally and anatomically.

KSC-04PD-1812

NASA Technical Reports Server (NTRS)

2004-01-01

KENNEDY SPACE CENTER, FLA. In the Orbiter Processing Facility, United Space Alliance worker Craig Meyer fits an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttles Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04PD-1813

NASA Technical Reports Server (NTRS)

2004-01-01

KENNEDY SPACE CENTER, FLA. In the Orbiter Processing Facility, an External Tank (ET) digital still camera is positioned into the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis to determine if it fits properly. NASA is pursuing use of the camera, beginning with the Shuttles Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04pd1813

NASA Image and Video Library

2004-09-17

KENNEDY SPACE CENTER, FLA. - In the Orbiter Processing Facility, an External Tank (ET) digital still camera is positioned into the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis to determine if it fits properly. NASA is pursuing use of the camera, beginning with the Shuttle’s Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04pd1812

NASA Image and Video Library

2004-09-17

KENNEDY SPACE CENTER, FLA. - In the Orbiter Processing Facility, United Space Alliance worker Craig Meyer fits an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttle’s Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

Data entry and error embedding system

NASA Technical Reports Server (NTRS)

Woo, Daniel N. (Inventor); Woo, Jr., John (Inventor)

1998-01-01

A data entry and error embedding system in which, first, a document is bitmapped and recorded in a first memory. Then, it is displayed, and portions of it to be replicated by data entry are underlayed by a window, into which window replicated data is entered in location and size such that it is juxtaposed just below that which is replicated, enhancing the accuracy of replication. Second, with this format in place, selected portions of the replicated data are altered by the insertion of character or word substitutions, thus the embedding of errors. Finally, a proofreader would endeavor to correct the error embedded data and a record of his or her changes recorded. In this manner, the skill level of the proofreader and accuracy of the data are computed.

Endurance cycling results in extreme environments

NASA Technical Reports Server (NTRS)

Guertin, S. M.; Nguyen, D. N.; Scheick, L. Z.

2003-01-01

A new test bed for life testing flash memories in extreme environments is introducted. the test bed is based on a state-of-the-art development board. Since space applications often desire state-of-the-art devices, such a basis seems appropriate. Comparison of this tester to other such systems, including those with data presented here in the past is made. Limitations of different testers for varying applications are discussed. Recently developed data, using this test bed is also presented.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Minimizing the Disruptive Effects of Prospective Memory in Simulated Air Traffic Control

PubMed Central

Loft, Shayne; Smith, Rebekah E.; Remington, Roger

2015-01-01

Prospective memory refers to remembering to perform an intended action in the future. Failures of prospective memory can occur in air traffic control. In two experiments, we examined the utility of external aids for facilitating air traffic management in a simulated air traffic control task with prospective memory requirements. Participants accepted and handed-off aircraft and detected aircraft conflicts. The prospective memory task involved remembering to deviate from a routine operating procedure when accepting target aircraft. External aids that contained details of the prospective memory task appeared and flashed when target aircraft needed acceptance. In Experiment 1, external aids presented either adjacent or non-adjacent to each of the 20 target aircraft presented over the 40min test phase reduced prospective memory error by 11% compared to a condition without external aids. In Experiment 2, only a single target aircraft was presented a significant time (39min–42min) after presentation of the prospective memory instruction, and the external aids reduced prospective memory error by 34%. In both experiments, costs to the efficiency of non-prospective memory air traffic management (non-target aircraft acceptance response time, conflict detection response time) were reduced by non-adjacent aids compared to no aids or adjacent aids. In contrast, in both experiments, the efficiency of the prospective memory air traffic management (target aircraft acceptance response time) was facilitated by adjacent aids compared to non-adjacent aids. Together, these findings have potential implications for the design of automated alerting systems to maximize multi-task performance in work settings where operators monitor and control demanding perceptual displays. PMID:24059825

Roll-to-roll nanopatterning using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Ahn, Sean; Ganapathisubramanian, Maha; Miller, Mike; Yang, Jack; Choi, Jin; Xu, Frank; Resnick, Douglas J.; Sreenivasan, S. V.

2012-03-01

The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area R2R manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we address the key challenges for roll based nanopatterning by introducing a novel concept: Ink Jet based Roll-to-Roll Nanopatterning. To address this challenge, we have introduced a J-FIL based demonstrator product, the LithoFlex 100. Topics that are discussed in the paper include tool design and process performance. In addition, we have used the LithoFlex 100 to fabricate high performance wire grid polarizers on flexible polycarbonate (PC) films. Transmission of better than 80% and extinction ratios on the order of 4500 have been achieved.

Blue light filtered white light induces depression-like responses and temporary spatial learning deficits in rats.

PubMed

Meng, Qinghe; Lian, Yuzheng; Jiang, Jianjun; Wang, Wei; Hou, Xiaohong; Pan, Yao; Chu, Hongqian; Shang, Lanqin; Wei, Xuetao; Hao, Weidong

2018-04-18

Ambient light has a vital impact on mood and cognitive functions. Blue light has been previously reported to play a salient role in the antidepressant effect via melanopsin. Whether blue light filtered white light (BFW) affects mood and cognitive functions remains unclear. The present study aimed to investigate whether BFW led to depression-like symptoms and cognitive deficits including spatial learning and memory abilities in rats, and whether they were associated with the light-responsive function in retinal explants. Male Sprague-Dawley albino rats were randomly divided into 2 groups (n = 10) and treated with a white light-emitting diode (LED) light source and BFW light source, respectively, under a standard 12 : 12 h L/D condition over 30 days. The sucrose consumption test, forced swim test (FST) and the level of plasma corticosterone (CORT) were employed to evaluate depression-like symptoms in rats. Cognitive functions were assessed by the Morris water maze (MWM) test. A multi-electrode array (MEA) system was utilized to measure electro-retinogram (ERG) responses induced by white or BFW flashes. The effect of BFW over 30 days on depression-like responses in rats was indicated by decreased sucrose consumption in the sucrose consumption test, an increased immobility time in the FST and an elevated level of plasma CORT. BFW led to temporary spatial learning deficits in rats, which was evidenced by prolonged escape latency and swimming distances in the spatial navigation test. However, no changes were observed in the short memory ability of rats treated with BFW. The micro-ERG results showed a delayed implicit time and reduced amplitudes evoked by BFW flashes compared to the white flash group. BFW induces depression-like symptoms and temporary spatial learning deficits in rats, which might be closely related to the impairment of light-evoked output signals in the retina.

Tree-based solvers for adaptive mesh refinement code FLASH - I: gravity and optical depths

NASA Astrophysics Data System (ADS)

Wünsch, R.; Walch, S.; Dinnbier, F.; Whitworth, A.

2018-04-01

We describe an OctTree algorithm for the MPI parallel, adaptive mesh refinement code FLASH, which can be used to calculate the gas self-gravity, and also the angle-averaged local optical depth, for treating ambient diffuse radiation. The algorithm communicates to the different processors only those parts of the tree that are needed to perform the tree-walk locally. The advantage of this approach is a relatively low memory requirement, important in particular for the optical depth calculation, which needs to process information from many different directions. This feature also enables a general tree-based radiation transport algorithm that will be described in a subsequent paper, and delivers excellent scaling up to at least 1500 cores. Boundary conditions for gravity can be either isolated or periodic, and they can be specified in each direction independently, using a newly developed generalization of the Ewald method. The gravity calculation can be accelerated with the adaptive block update technique by partially re-using the solution from the previous time-step. Comparison with the FLASH internal multigrid gravity solver shows that tree-based methods provide a competitive alternative, particularly for problems with isolated or mixed boundary conditions. We evaluate several multipole acceptance criteria (MACs) and identify a relatively simple approximate partial error MAC which provides high accuracy at low computational cost. The optical depth estimates are found to agree very well with those of the RADMC-3D radiation transport code, with the tree-solver being much faster. Our algorithm is available in the standard release of the FLASH code in version 4.0 and later.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

NASA Astrophysics Data System (ADS)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

NASA Astrophysics Data System (ADS)

Doi, Masafumi; Tokutomi, Tsukasa; Hachiya, Shogo; Kobayashi, Atsuro; Tanakamaru, Shuhei; Ning, Sheyang; Ogura Iwasaki, Tomoko; Takeuchi, Ken

2016-08-01

NAND flash memory’s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Ref’s in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Reconfigurable and Reprocessable Thermoset Shape Memory Polymer with Synergetic Triple Dynamic Covalent Bonds.

PubMed

Wang, Yongwei; Pan, Yi; Zheng, Zhaohui; Ding, Xiaobin

2018-04-20

Degradable shape memory polymers (SMPs), especially for polyurethane-based SMPs, have shown great potential for biomedical applications. How to reasonably fabricate SMPs with the ideal combination of degradability, shape reconfigurability, and reprocessability is a critical issue and remains a challenge for medical disposable materials. Herein, a shape memory poly(urethane-urea) with synergetic triple dynamic covalent bonds is reported via embedding polycaprolactone unit into poly(urethane-urea) with the hindered urea dynamic bond. The single polymer network is biodegradable, thermadapt, and reprocessable, without sacrificing the outstanding shape memory performance. Such a shape memory network with plasticity and reprocessability is expected to have significant and positive impact on the medical device industry. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Embedded real-time operating system micro kernel design

NASA Astrophysics Data System (ADS)

Cheng, Xiao-hui; Li, Ming-qiang; Wang, Xin-zheng

2005-12-01

Embedded systems usually require a real-time character. Base on an 8051 microcontroller, an embedded real-time operating system micro kernel is proposed consisting of six parts, including a critical section process, task scheduling, interruption handle, semaphore and message mailbox communication, clock managent and memory managent. Distributed CPU and other resources are among tasks rationally according to the importance and urgency. The design proposed here provides the position, definition, function and principle of micro kernel. The kernel runs on the platform of an ATMEL AT89C51 microcontroller. Simulation results prove that the designed micro kernel is stable and reliable and has quick response while operating in an application system.

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

Efficiently Communicating Rich Heterogeneous Geospatial Data from the FeMO2008 Dive Cruise with FlashMap on EarthRef.org

NASA Astrophysics Data System (ADS)

Minnett, R. C.; Koppers, A. A.; Staudigel, D.; Staudigel, H.

2008-12-01

EarthRef.org is comprehensive and convenient resource for Earth Science reference data and models. It encompasses four main portals: the Geochemical Earth Reference Model (GERM), the Magnetics Information Consortium (MagIC), the Seamount Biogeosciences Network (SBN), and the Enduring Resources for Earth Science Education (ERESE). Their underlying databases are publically available and the scientific community has contributed widely and is urged to continue to do so. However, the net result is a vast and largely heterogeneous warehouse of geospatial data ranging from carefully prepared maps of seamounts to geochemical data/metadata, daily reports from seagoing expeditions, large volumes of raw and processed multibeam data, images of paleomagnetic sampling sites, etc. This presents a considerable obstacle for integrating other rich media content, such as videos, images, data files, cruise tracks, and interoperable database results, without overwhelming the web user. The four EarthRef.org portals clearly lend themselves to a more intuitive user interface and has, therefore, been an invaluable test bed for the design and implementation of FlashMap, a versatile KML-driven geospatial browser written for reliability and speed in Adobe Flash. FlashMap allows layers of content to be loaded and displayed over a streaming high-resolution map which can be zoomed and panned similarly to Google Maps and Google Earth. Many organizations, from National Geographic to the USGS, have begun using Google Earth software to display geospatial content. However, Google Earth, as a desktop application, does not integrate cleanly with existing websites requiring the user to navigate away from the browser and focus on a separate application and Google Maps, written in Java Script, does not scale up reliably to large datasets. FlashMap remedies these problems as a web-based application that allows for seamless integration of the real-time display power of Google Earth and the flexibility of the web without losing scalability and control of the base maps. Our Flash-based application is fully compatible with KML (Keyhole Markup Language) 2.2, the most recent iteration of KML, allowing users with existing Google Earth KML files to effortlessly display their geospatial content embedded in a web page. As a test case for FlashMap, the annual Iron-Oxidizing Microbial Observatory (FeMO) dive cruise to the Loihi Seamount, in conjunction with data available from ongoing and published FeMO laboratory studies, showcases the flexibility of this single web-based application. With a KML 2.2 compatible web-service providing the content, any database can display results in FlashMap. The user can then hide and show multiple layers of content, potentially from several data sources, and rapidly digest a vast quantity of information to narrow the search results. This flexibility gives experienced users the ability to drill down to exactly the record they are looking for (SERC at Carleton College's educational application of FlashMap at http://serc.carleton.edu/sp/erese/activities/22223.html) and allows users familiar with Google Earth the ability to load and view geospatial data content within a browser from any computer with an internet connection.

Artificial neural networks as quantum associative memory

NASA Astrophysics Data System (ADS)

Hamilton, Kathleen; Schrock, Jonathan; Imam, Neena; Humble, Travis

We present results related to the recall accuracy and capacity of Hopfield networks implemented on commercially available quantum annealers. The use of Hopfield networks and artificial neural networks as content-addressable memories offer robust storage and retrieval of classical information, however, implementation of these models using currently available quantum annealers faces several challenges: the limits of precision when setting synaptic weights, the effects of spurious spin-glass states and minor embedding of densely connected graphs into fixed-connectivity hardware. We consider neural networks which are less than fully-connected, and also consider neural networks which contain multiple sparsely connected clusters. We discuss the effect of weak edge dilution on the accuracy of memory recall, and discuss how the multiple clique structure affects the storage capacity. Our work focuses on storage of patterns which can be embedded into physical hardware containing n < 1000 qubits. This work was supported by the United States Department of Defense and used resources of the Computational Research and Development Programs as Oak Ridge National Laboratory under Contract No. DE-AC0500OR22725 with the U. S. Department of Energy.

Segregating the core computational faculty of human language from working memory

PubMed Central

Makuuchi, Michiru; Bahlmann, Jörg; Anwander, Alfred; Friederici, Angela D.

2009-01-01

In contrast to simple structures in animal vocal behavior, hierarchical structures such as center-embedded sentences manifest the core computational faculty of human language. Previous artificial grammar learning studies found that the left pars opercularis (LPO) subserves the processing of hierarchical structures. However, it is not clear whether this area is activated by the structural complexity per se or by the increased memory load entailed in processing hierarchical structures. To dissociate the effect of structural complexity from the effect of memory cost, we conducted a functional magnetic resonance imaging study of German sentence processing with a 2-way factorial design tapping structural complexity (with/without hierarchical structure, i.e., center-embedding of clauses) and working memory load (long/short distance between syntactically dependent elements; i.e., subject nouns and their respective verbs). Functional imaging data revealed that the processes for structure and memory operate separately but co-operatively in the left inferior frontal gyrus; activities in the LPO increased as a function of structural complexity, whereas activities in the left inferior frontal sulcus (LIFS) were modulated by the distance over which the syntactic information had to be transferred. Diffusion tensor imaging showed that these 2 regions were interconnected through white matter fibers. Moreover, functional coupling between the 2 regions was found to increase during the processing of complex, hierarchically structured sentences. These results suggest a neuroanatomical segregation of syntax-related aspects represented in the LPO from memory-related aspects reflected in the LIFS, which are, however, highly interconnected functionally and anatomically. PMID:19416819

Temporal and Spatial Predictability of an Irrelevant Event Differently Affect Detection and Memory of Items in a Visual Sequence

PubMed Central

Ohyama, Junji; Watanabe, Katsumi

2016-01-01

We examined how the temporal and spatial predictability of a task-irrelevant visual event affects the detection and memory of a visual item embedded in a continuously changing sequence. Participants observed 11 sequentially presented letters, during which a task-irrelevant visual event was either present or absent. Predictabilities of spatial location and temporal position of the event were controlled in 2 × 2 conditions. In the spatially predictable conditions, the event occurred at the same location within the stimulus sequence or at another location, while, in the spatially unpredictable conditions, it occurred at random locations. In the temporally predictable conditions, the event timing was fixed relative to the order of the letters, while in the temporally unpredictable condition; it could not be predicted from the letter order. Participants performed a working memory task and a target detection reaction time (RT) task. Memory accuracy was higher for a letter simultaneously presented at the same location as the event in the temporally unpredictable conditions, irrespective of the spatial predictability of the event. On the other hand, the detection RTs were only faster for a letter simultaneously presented at the same location as the event when the event was both temporally and spatially predictable. Thus, to facilitate ongoing detection processes, an event must be predictable both in space and time, while memory processes are enhanced by temporally unpredictable (i.e., surprising) events. Evidently, temporal predictability has differential effects on detection and memory of a visual item embedded in a sequence of images. PMID:26869966

Temporal and Spatial Predictability of an Irrelevant Event Differently Affect Detection and Memory of Items in a Visual Sequence.

PubMed

Ohyama, Junji; Watanabe, Katsumi

2016-01-01

We examined how the temporal and spatial predictability of a task-irrelevant visual event affects the detection and memory of a visual item embedded in a continuously changing sequence. Participants observed 11 sequentially presented letters, during which a task-irrelevant visual event was either present or absent. Predictabilities of spatial location and temporal position of the event were controlled in 2 × 2 conditions. In the spatially predictable conditions, the event occurred at the same location within the stimulus sequence or at another location, while, in the spatially unpredictable conditions, it occurred at random locations. In the temporally predictable conditions, the event timing was fixed relative to the order of the letters, while in the temporally unpredictable condition; it could not be predicted from the letter order. Participants performed a working memory task and a target detection reaction time (RT) task. Memory accuracy was higher for a letter simultaneously presented at the same location as the event in the temporally unpredictable conditions, irrespective of the spatial predictability of the event. On the other hand, the detection RTs were only faster for a letter simultaneously presented at the same location as the event when the event was both temporally and spatially predictable. Thus, to facilitate ongoing detection processes, an event must be predictable both in space and time, while memory processes are enhanced by temporally unpredictable (i.e., surprising) events. Evidently, temporal predictability has differential effects on detection and memory of a visual item embedded in a sequence of images.

A memory of an aesthetic experience transferred to clinical practice.

PubMed

Wikström, Britt-Maj

2003-03-01

To examine the usefulness of writing about a memory of an aesthetic experience, and then transfer the aesthetic experience to a health care situation. The study was accomplished at two university colleges of health sciences in Sweden. It started with student nurses (N=291) writing about a memory of an aesthetic experience. Then they transferred the aesthetic experience to a purposeful clinical practice. The results showed that each student could report on a positive memory of an aesthetic experience. Embedded in each story was an aesthetic experience that was meaningful to the student. Domains of memory most frequently reported were music, work of art and nature. Themes derived from the aesthetic memory were happiness and awareness. The awareness theme comprized the value of aesthetic experiences for the patients, and for student nurses. The process of writing about a memory of an aesthetic experience provided an alternative model for nursing education that could improve patient care.

Visual memory performance for color depends on spatiotemporal context.

PubMed

Olivers, Christian N L; Schreij, Daniel

2014-10-01

Performance on visual short-term memory for features has been known to depend on stimulus complexity, spatial layout, and feature context. However, with few exceptions, memory capacity has been measured for abruptly appearing, single-instance displays. In everyday life, objects often have a spatiotemporal history as they or the observer move around. In three experiments, we investigated the effect of spatiotemporal history on explicit memory for color. Observers saw a memory display emerge from behind a wall, after which it disappeared again. The test display then emerged from either the same side as the memory display or the opposite side. In the first two experiments, memory improved for intermediate set sizes when the test display emerged in the same way as the memory display. A third experiment then showed that the benefit was tied to the original motion trajectory and not to the display object per se. The results indicate that memory for color is embedded in a richer episodic context that includes the spatiotemporal history of the display.

Prospective memory: effects of divided attention on spontaneous retrieval.

PubMed

Harrison, Tyler L; Mullet, Hillary G; Whiffen, Katie N; Ousterhout, Hunter; Einstein, Gilles O

2014-02-01

We examined the effects of divided attention on the spontaneous retrieval of a prospective memory intention. Participants performed an ongoing lexical decision task with an embedded prospective memory demand, and also performed a divided-attention task during some segments of lexical decision trials. In all experiments, monitoring was highly discouraged, and we observed no evidence that participants engaged monitoring processes. In Experiment 1, performing a moderately demanding divided-attention task (a digit detection task) did not affect prospective memory performance. In Experiment 2, performing a more challenging divided-attention task (random number generation) impaired prospective memory. Experiment 3 showed that this impairment was eliminated when the prospective memory cue was perceptually salient. Taken together, the results indicate that spontaneous retrieval is not automatic and that challenging divided-attention tasks interfere with spontaneous retrieval and not with the execution of a retrieved intention.

Integral Images: Efficient Algorithms for Their Computation and Storage in Resource-Constrained Embedded Vision Systems

PubMed Central

Ehsan, Shoaib; Clark, Adrian F.; ur Rehman, Naveed; McDonald-Maier, Klaus D.

2015-01-01

The integral image, an intermediate image representation, has found extensive use in multi-scale local feature detection algorithms, such as Speeded-Up Robust Features (SURF), allowing fast computation of rectangular features at constant speed, independent of filter size. For resource-constrained real-time embedded vision systems, computation and storage of integral image presents several design challenges due to strict timing and hardware limitations. Although calculation of the integral image only consists of simple addition operations, the total number of operations is large owing to the generally large size of image data. Recursive equations allow substantial decrease in the number of operations but require calculation in a serial fashion. This paper presents two new hardware algorithms that are based on the decomposition of these recursive equations, allowing calculation of up to four integral image values in a row-parallel way without significantly increasing the number of operations. An efficient design strategy is also proposed for a parallel integral image computation unit to reduce the size of the required internal memory (nearly 35% for common HD video). Addressing the storage problem of integral image in embedded vision systems, the paper presents two algorithms which allow substantial decrease (at least 44.44%) in the memory requirements. Finally, the paper provides a case study that highlights the utility of the proposed architectures in embedded vision systems. PMID:26184211

Embedded ensemble propagation for improving performance, portability, and scalability of uncertainty quantification on emerging computational architectures

DOE PAGES

Phipps, Eric T.; D'Elia, Marta; Edwards, Harold C.; ...

2017-04-18

In this study, quantifying simulation uncertainties is a critical component of rigorous predictive simulation. A key component of this is forward propagation of uncertainties in simulation input data to output quantities of interest. Typical approaches involve repeated sampling of the simulation over the uncertain input data, and can require numerous samples when accurately propagating uncertainties from large numbers of sources. Often simulation processes from sample to sample are similar and much of the data generated from each sample evaluation could be reused. We explore a new method for implementing sampling methods that simultaneously propagates groups of samples together in anmore » embedded fashion, which we call embedded ensemble propagation. We show how this approach takes advantage of properties of modern computer architectures to improve performance by enabling reuse between samples, reducing memory bandwidth requirements, improving memory access patterns, improving opportunities for fine-grained parallelization, and reducing communication costs. We describe a software technique for implementing embedded ensemble propagation based on the use of C++ templates and describe its integration with various scientific computing libraries within Trilinos. We demonstrate improved performance, portability and scalability for the approach applied to the simulation of partial differential equations on a variety of CPU, GPU, and accelerator architectures, including up to 131,072 cores on a Cray XK7 (Titan).« less

Integral Images: Efficient Algorithms for Their Computation and Storage in Resource-Constrained Embedded Vision Systems.

PubMed

Ehsan, Shoaib; Clark, Adrian F; Naveed ur Rehman; McDonald-Maier, Klaus D

2015-07-10

The integral image, an intermediate image representation, has found extensive use in multi-scale local feature detection algorithms, such as Speeded-Up Robust Features (SURF), allowing fast computation of rectangular features at constant speed, independent of filter size. For resource-constrained real-time embedded vision systems, computation and storage of integral image presents several design challenges due to strict timing and hardware limitations. Although calculation of the integral image only consists of simple addition operations, the total number of operations is large owing to the generally large size of image data. Recursive equations allow substantial decrease in the number of operations but require calculation in a serial fashion. This paper presents two new hardware algorithms that are based on the decomposition of these recursive equations, allowing calculation of up to four integral image values in a row-parallel way without significantly increasing the number of operations. An efficient design strategy is also proposed for a parallel integral image computation unit to reduce the size of the required internal memory (nearly 35% for common HD video). Addressing the storage problem of integral image in embedded vision systems, the paper presents two algorithms which allow substantial decrease (at least 44.44%) in the memory requirements. Finally, the paper provides a case study that highlights the utility of the proposed architectures in embedded vision systems.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

KSC-04PD-1810

NASA Technical Reports Server (NTRS)

2004-01-01

KENNEDY SPACE CENTER, FLA. In the Orbiter Processing Facility, from left, United Space Alliance workers Loyd Turner, Craig Meyer and Erik Visser prepare to conduct a fit check of an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttles Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04PD-1811

NASA Technical Reports Server (NTRS)

2004-01-01

KENNEDY SPACE CENTER, FLA. In the Orbiter Processing Facility, from left, United Space Alliance workers Loyd Turner, Craig Meyer and Erik Visser conduct a fit check of an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttles Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04pd1811

NASA Image and Video Library

2004-09-17

KENNEDY SPACE CENTER, FLA. - In the Orbiter Processing Facility, from left, United Space Alliance workers Loyd Turner, Craig Meyer and Erik Visser conduct a fit check of an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttle’s Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

KSC-04pd1810

NASA Image and Video Library

2004-09-17

KENNEDY SPACE CENTER, FLA. - In the Orbiter Processing Facility, from left, United Space Alliance workers Loyd Turner, Craig Meyer and Erik Visser prepare to conduct a fit check of an External Tank (ET) digital still camera in the right-hand liquid oxygen umbilical well on Space Shuttle Atlantis. NASA is pursuing use of the camera, beginning with the Shuttle’s Return To Flight, to obtain and downlink high-resolution images of the ET following separation of the ET from the orbiter after launch. The Kodak camera will record 24 images, at one frame per 1.5 seconds, on a flash memory card. After orbital insertion, the crew will transfer the images from the memory card to a laptop computer. The files will then be downloaded through the Ku-band system to the Mission Control Center in Houston for analysis.

Block-Parallel Data Analysis with DIY2

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morozov, Dmitriy; Peterka, Tom

DIY2 is a programming model and runtime for block-parallel analytics on distributed-memory machines. Its main abstraction is block-structured data parallelism: data are decomposed into blocks; blocks are assigned to processing elements (processes or threads); computation is described as iterations over these blocks, and communication between blocks is defined by reusable patterns. By expressing computation in this general form, the DIY2 runtime is free to optimize the movement of blocks between slow and fast memories (disk and flash vs. DRAM) and to concurrently execute blocks residing in memory with multiple threads. This enables the same program to execute in-core, out-of-core, serial,more » parallel, single-threaded, multithreaded, or combinations thereof. This paper describes the implementation of the main features of the DIY2 programming model and optimizations to improve performance. DIY2 is evaluated on benchmark test cases to establish baseline performance for several common patterns and on larger complete analysis codes running on large-scale HPC machines.« less

Microstructure and Shape Memory Behavior of Ti-Nb Shape Memory Alloy Thin Film

NASA Astrophysics Data System (ADS)

Meng, X. L.; Sun, B.; Sun, J. Y.; Gao, Z. Y.; Cai, W.; Zhao, L. C.

2017-09-01

Ti-Nb shape memory alloy (SMA) thin film is a promising candidate applied as microactuator in biomedical field. In this study, the microstructure and shape memory behavior of Ti-Nb SMA thin films in different heat treatment conditions have been investigated. Fine ω phases embedded in the β phase matrix suppress the martensitic transformation of the films. As a result, the as-deposited and most of the annealed films consist of the β and α″ dual phases. The annealed Ti-Nb thin film shows excellent superelasticity effect when deformed above the reverse martensitic transformation temperature, that is 3.5% total recovery strain can be obtained when 4% pre-strain is loaded.

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Development of Deployable Elastic Composite Shape Memory Alloy Reinforced (DECSMAR) Structures

DTIC Science & Technology

2006-05-01

battens nest. To mitigate the compromise of deployed performance due to the hinge cross-section, Nitinol SMA wires can be embedded in the composite...proportional limit by slip or conventional plastic deformation. As a logistics example, the particular Nitinol alloy used for proto-typing has...Memory Alloys,” Johnson Matthey, 2004. 10Cross, WB, Kariotis, AH, & Stimler, FJ, “ Nitinol Characterization Study,” NASA CR-1433, 1970. 11Proft, JL

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memoriesmore » for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)« less

Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash

NASA Astrophysics Data System (ADS)

Zhang, Yu; Jin, Lei; Jiang, Dandan; Zou, Xingqi; Zhao, Zhiguo; Gao, Jing; Zeng, Ming; Zhou, Wenbin; Tang, Zhaoyun; Huo, Zongliang

2018-03-01

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

Heavy Ion and Proton-Induced Single Event Upset Characteristics of a 3D NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Seidleck, Christina; Kim, Hak; Phan, Anthony; Label, Kenneth

2017-01-01

We evaluated the effects of heavy ion and proton irradiation for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of identical density in the multiple-cell level (MLC) storage mode. The 3D NAND showed significantly reduced SEU susceptibility in single-level-cell (SLC) storage mode. Additionally, the 3D NAND showed less multiple-bit upset susceptibility than the planar NAND, with fewer number of upset bits per byte and smaller cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the Micron 16 nm planar NAND, which suggests that typical heavy ion test fluences will underestimate the upset rate during a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.

Fabricating Composite-Material Structures Containing SMA Ribbons

NASA Technical Reports Server (NTRS)

Turner, Travis L.; Cano, Roberto J.; Lach, Cynthia L.

2003-01-01

An improved method of designing and fabricating laminated composite-material (matrix/fiber) structures containing embedded shape-memory-alloy (SMA) actuators has been devised. Structures made by this method have repeatable, predictable properties, and fabrication processes can readily be automated. Such structures, denoted as shape-memory-alloy hybrid composite (SMAHC) structures, have been investigated for their potential to satisfy requirements to control the shapes or thermoelastic responses of themselves or of other structures into which they might be incorporated, or to control noise and vibrations. Much of the prior work on SMAHC structures has involved the use SMA wires embedded within matrices or within sleeves through parent structures. The disadvantages of using SMA wires as the embedded actuators include (1) complexity of fabrication procedures because of the relatively large numbers of actuators usually needed; (2) sensitivity to actuator/ matrix interface flaws because voids can be of significant size, relative to wires; (3) relatively high rates of breakage of actuators during curing of matrix materials because of sensitivity to stress concentrations at mechanical restraints; and (4) difficulty of achieving desirable overall volume fractions of SMA wires when trying to optimize the integration of the wires by placing them in selected layers only.

Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Swift, Gary M.; Allen, Gregory S.; Farmanesh, Farhad; George, Jeffrey; Petrick, David J.; Chayab, Fayez

2006-01-01

Shown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.

Electromagnetic Characterization Of Metallic Sensory Alloy

NASA Technical Reports Server (NTRS)

Wincheski, Russell A.; Simpson, John; Wallace, Terryl A.; Newman, John A.; Leser, Paul; Lahue, Rob

2012-01-01

Ferromagnetic shape-memory alloy (FSMA) particles undergo changes in both electromagnetic properties and crystallographic structure when strained. When embedded in a structural material, these attributes can provide sensory output of the strain state of the structure. In this work, a detailed characterization of the electromagnetic properties of a FSMA under development for sensory applications is performed. In addition, a new eddy current probe is used to interrogate the electromagnetic properties of individual FSMA particles embedded in the sensory alloy during controlled fatigue tests on the multifunctional material.

Electromagnetic characterization of metallic sensory alloy

NASA Astrophysics Data System (ADS)

Wincheski, Buzz; Simpson, John; Wallace, Terryl; Newman, Andy; Leser, Paul; Lahue, Rob

2013-01-01

Ferromagnetic shape-memory alloy (FSMA) particles undergo changes in both electromagnetic properties and crystallographic structure when strained. When embedded in a structural material, these attributes can provide sensory output of the strain state of the structure. In this work, a detailed characterization of the electromagnetic properties of a FSMA under development for sensory applications is performed. In addition, a new eddy current probe is used to interrogate the electromagnetic properties of individual FSMA particles embedded in the sensory alloy during controlled fatigue tests on the multifunctional material.

Interfacial Redox Reactions Associated Ionic Transport in Oxide-Based Memories.

PubMed

Younis, Adnan; Chu, Dewei; Shah, Abdul Hadi; Du, Haiwei; Li, Sean

2017-01-18

As an alternative to transistor-based flash memories, redox reactions mediated resistive switches are considered as the most promising next-generation nonvolatile memories that combine the advantages of a simple metal/solid electrolyte (insulator)/metal structure, high scalability, low power consumption, and fast processing. For cation-based memories, the unavailability of in-built mobile cations in many solid electrolytes/insulators (e.g., Ta 2 O 5 , SiO 2 , etc.) instigates the essential role of absorbed water in films to keep electroneutrality for redox reactions at counter electrodes. Herein, we demonstrate electrochemical characteristics (oxidation/reduction reactions) of active electrodes (Ag and Cu) at the electrode/electrolyte interface and their subsequent ions transportation in Fe 3 O 4 film by means of cyclic voltammetry measurements. By posing positive potentials on Ag/Cu active electrodes, Ag preferentially oxidized to Ag + , while Cu prefers to oxidize into Cu 2+ first, followed by Cu/Cu + oxidation. By sweeping the reverse potential, the oxidized ions can be subsequently reduced at the counter electrode. The results presented here provide a detailed understanding of the resistive switching phenomenon in Fe 3 O 4 -based memory cells. The results were further discussed on the basis of electrochemically assisted cations diffusions in the presence of absorbed surface water molecules in the film.

CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW)

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Orozco, David S.; Byrne, D. J.; Allen, Steven J.; Sahasrabudhe, Adit; Lang, Minh

2012-01-01

This software provides essential startup and initialization routines for the CoNNeCT baseband processor module (BPM) hardware upon power-up. A command and data handling (C&DH) interface is provided via 1553 and diagnostic serial interfaces to invoke operational, reconfiguration, and test commands within the code. The BCSW has features unique to the hardware it is responsible for managing. In this case, the CoNNeCT BPM is configured with an updated CPU (Atmel AT697 SPARC processor) and a unique set of memory and I/O peripherals that require customized software to operate. These features include configuration of new AT697 registers, interfacing to a new HouseKeeper with a flash controller interface, a new dual Xilinx configuration/scrub interface, and an updated 1553 remote terminal (RT) core. The BCSW is intended to provide a "safe" mode for the BPM when initially powered on or when an unexpected trap occurs, causing the processor to reset. The BCSW allows the 1553 bus controller in the spacecraft or payload controller to operate the BPM over 1553 to upload code; upload Xilinx bit files; perform rudimentary tests; read, write, and copy the non-volatile flash memory; and configure the Xilinx interface. Commands also exist over 1553 to cause the CPU to jump or call a specified address to begin execution of user-supplied code. This may be in the form of a real-time operating system, test routine, or specific application code to run on the BPM.

Specificity and detail in autobiographical memory: Same or different constructs?

PubMed

Kyung, Yoonhee; Yanes-Lukin, Paula; Roberts, John E

2016-01-01

Research on autobiographical memory has focused on whether memories are coded as specific (i.e., describe a single event that happened at a particular time and place). Although some theory and research suggests that the amount of detail in autobiographical memories reflects a similar underlying construct as memory specificity, past research has not investigated whether these variables converge. Therefore, the present study compared the proportion of specific memories and the amount of detail embedded in memory responses to cue words. Results demonstrated that memory detail and proportion of specific memories were not correlated with each other and showed different patterns of association with other conceptually relevant variables. When responses to neutral cue words were examined in multiple linear and logistic regression analyses, the proportion of specific memories uniquely predicted less depressive symptoms, low emotional avoidance, lower emotion reactivity, better executive control and lower rumination, whereas the amount of memory detail uniquely predicted the presence of depression diagnosis, as well as greater depressive symptoms, subjective stress, emotion reactivity and rumination. Findings suggest that the ability to retrieve specific memories and the tendency to retrieve detailed personal memories reflect different constructs that have different implications in the development of emotional distress.

Rapid induction of false memory for pictures.

PubMed

Weinstein, Yana; Shanks, David R

2010-07-01

Recognition of pictures is typically extremely accurate, and it is thus unclear whether the reconstructive nature of memory can yield substantial false recognition of highly individuated stimuli. A procedure for the rapid induction of false memories for distinctive colour photographs is proposed. Participants studied a set of object pictures followed by a list of words naming those objects, but embedded in the list were names of unseen objects. When subsequently shown full colour pictures of these unseen objects, participants consistently claimed that they had seen them, while discriminating with high accuracy between studied pictures and new pictures whose names did not appear in the misleading word list. These false memories can be reported with high confidence as well as the feeling of recollection. This new procedure allows the investigation of factors that influence false memory reports with ecologically valid stimuli and of the similarities and differences between true and false memories.

Low-complexity object detection with deep convolutional neural network for embedded systems

NASA Astrophysics Data System (ADS)

Tripathi, Subarna; Kang, Byeongkeun; Dane, Gokce; Nguyen, Truong

2017-09-01

We investigate low-complexity convolutional neural networks (CNNs) for object detection for embedded vision applications. It is well-known that consolidation of an embedded system for CNN-based object detection is more challenging due to computation and memory requirement comparing with problems like image classification. To achieve these requirements, we design and develop an end-to-end TensorFlow (TF)-based fully-convolutional deep neural network for generic object detection task inspired by one of the fastest framework, YOLO.1 The proposed network predicts the localization of every object by regressing the coordinates of the corresponding bounding box as in YOLO. Hence, the network is able to detect any objects without any limitations in the size of the objects. However, unlike YOLO, all the layers in the proposed network is fully-convolutional. Thus, it is able to take input images of any size. We pick face detection as an use case. We evaluate the proposed model for face detection on FDDB dataset and Widerface dataset. As another use case of generic object detection, we evaluate its performance on PASCAL VOC dataset. The experimental results demonstrate that the proposed network can predict object instances of different sizes and poses in a single frame. Moreover, the results show that the proposed method achieves comparative accuracy comparing with the state-of-the-art CNN-based object detection methods while reducing the model size by 3× and memory-BW by 3 - 4× comparing with one of the best real-time CNN-based object detectors, YOLO. Our 8-bit fixed-point TF-model provides additional 4× memory reduction while keeping the accuracy nearly as good as the floating-point model. Moreover, the fixed- point model is capable of achieving 20× faster inference speed comparing with the floating-point model. Thus, the proposed method is promising for embedded implementations.

A categorical recall strategy does not explain animacy effects in episodic memory.

PubMed

VanArsdall, Joshua E; Nairne, James S; Pandeirada, Josefa N S; Cogdill, Mindi

2017-04-01

Animate stimuli are better remembered than matched inanimate stimuli in free recall. Three experiments tested the hypothesis that animacy advantages are due to a more efficient use of a categorical retrieval cue. Experiment 1 developed an "embedded list" procedure that was designed to disrupt participants' ability to perceive category structure at encoding; a strong animacy effect remained. Experiments 2 and 3 employed animate and inanimate word lists consisting of tightly constrained categories (four-footed animals and furniture). Experiment 2 failed to find an animacy advantage when the categorical structure was readily apparent, but the advantage returned in Experiment 3 when the embedded list procedure was employed using the same target words. These results provide strong evidence against an organizational account of the animacy effect, indicating that the animacy effect in episodic memory is probably due to item-specific factors related to animacy.

Thermal and damping behaviour of magnetic shape memory alloy composites

NASA Astrophysics Data System (ADS)

Glock, Susanne; Michaud, Véronique

2015-06-01

Single crystals of ferromagnetic shape memory alloys (MSMA) exhibit magnetic field and stress induced strains via energy dissipating twinning. Embedding single crystalline MSMA particles into a polymer matrix could thus produce composites with enhanced energy dissipation, suitable for damping applications. Composites of ferromagnetic, martensitic or austenitic Ni-Mn-Ga powders embedded in a standard epoxy matrix were produced by casting. The martensitic powder composites showed a crystal structure dependent damping behaviour that was more dissipative than that of austenitic powder or Cu-Ni reference powder composites and than that of the pure matrix. The loss ratio also increased with increasing strain amplitude and decreasing frequency, respectively. Furthermore, Ni-Mn-Ga powder composites exhibited an increased damping behaviour at the martensite/austenite transformation temperature of the Ni-Mn-Ga particles in addition to that at the glass transition temperature of the epoxy matrix, creating possible synergetic effects.

Hardware/software codesign for embedded RISC core

NASA Astrophysics Data System (ADS)

Liu, Peng

2001-12-01

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls the pipeline stage status and cooperation among the pipeline phase. Since description use high level language and structure is distributed, VIRGO core has highly extension that can meet the requirements of application. We take look at the high-definition television MPEG2 MPHL decoder chip, constructed the hardware/software codesign virtual prototyping machine that can research on VIRGO core instruction set architecture, and system on chip memory size requirements, and system on chip software, etc. We also can evaluate the system on chip design and RISC instruction set based on the virtual prototyping machine platform.

From brain synapses to systems for learning and memory: Object recognition, spatial navigation, timed conditioning, and movement control.

PubMed

Grossberg, Stephen

2015-09-24

This article provides an overview of neural models of synaptic learning and memory whose expression in adaptive behavior depends critically on the circuits and systems in which the synapses are embedded. It reviews Adaptive Resonance Theory, or ART, models that use excitatory matching and match-based learning to achieve fast category learning and whose learned memories are dynamically stabilized by top-down expectations, attentional focusing, and memory search. ART clarifies mechanistic relationships between consciousness, learning, expectation, attention, resonance, and synchrony. ART models are embedded in ARTSCAN architectures that unify processes of invariant object category learning, recognition, spatial and object attention, predictive remapping, and eye movement search, and that clarify how conscious object vision and recognition may fail during perceptual crowding and parietal neglect. The generality of learned categories depends upon a vigilance process that is regulated by acetylcholine via the nucleus basalis. Vigilance can get stuck at too high or too low values, thereby causing learning problems in autism and medial temporal amnesia. Similar synaptic learning laws support qualitatively different behaviors: Invariant object category learning in the inferotemporal cortex; learning of grid cells and place cells in the entorhinal and hippocampal cortices during spatial navigation; and learning of time cells in the entorhinal-hippocampal system during adaptively timed conditioning, including trace conditioning. Spatial and temporal processes through the medial and lateral entorhinal-hippocampal system seem to be carried out with homologous circuit designs. Variations of a shared laminar neocortical circuit design have modeled 3D vision, speech perception, and cognitive working memory and learning. A complementary kind of inhibitory matching and mismatch learning controls movement. This article is part of a Special Issue entitled SI: Brain and Memory. Copyright © 2014 Elsevier B.V. All rights reserved.

Diverse Power Iteration Embeddings and Its Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang H.; Yoo S.; Yu, D.

2014-12-14

Abstract—Spectral Embedding is one of the most effective dimension reduction algorithms in data mining. However, its computation complexity has to be mitigated in order to apply it for real-world large scale data analysis. Many researches have been focusing on developing approximate spectral embeddings which are more efficient, but meanwhile far less effective. This paper proposes Diverse Power Iteration Embeddings (DPIE), which not only retains the similar efficiency of power iteration methods but also produces a series of diverse and more effective embedding vectors. We test this novel method by applying it to various data mining applications (e.g. clustering, anomaly detectionmore » and feature selection) and evaluating their performance improvements. The experimental results show our proposed DPIE is more effective than popular spectral approximation methods, and obtains the similar quality of classic spectral embedding derived from eigen-decompositions. Moreover it is extremely fast on big data applications. For example in terms of clustering result, DPIE achieves as good as 95% of classic spectral clustering on the complex datasets but 4000+ times faster in limited memory environment.« less

A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

PubMed

Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

2018-02-01

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

NASA Technical Reports Server (NTRS)

MacLeod, Todd; Ho, Fat D.

2012-01-01

The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere with the satellite s primary mission.

Ultralow-fatigue shape memory alloy films

NASA Astrophysics Data System (ADS)

Chluba, Christoph; Ge, Wenwei; Lima de Miranda, Rodrigo; Strobel, Julian; Kienle, Lorenz; Quandt, Eckhard; Wuttig, Manfred

2015-05-01

Functional shape memory alloys need to operate reversibly and repeatedly. Quantitative measures of reversibility include the relative volume change of the participating phases and compatibility matrices for twinning. But no similar argument is known for repeatability. This is especially crucial for many future applications, such as artificial heart valves or elastocaloric cooling, in which more than 10 million transformation cycles will be required. We report on the discovery of an ultralow-fatigue shape memory alloy film system based on TiNiCu that allows at least 10 million transformation cycles. We found that these films contain Ti2Cu precipitates embedded in the base alloy that serve as sentinels to ensure complete and reproducible transformation in the course of each memory cycle.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Transition from Target to Gaze Coding in Primate Frontal Eye Field during Memory Delay and Memory-Motor Transformation.

PubMed

Sajad, Amirsaman; Sadeh, Morteza; Yan, Xiaogang; Wang, Hongying; Crawford, John Douglas

2016-01-01

The frontal eye fields (FEFs) participate in both working memory and sensorimotor transformations for saccades, but their role in integrating these functions through time remains unclear. Here, we tracked FEF spatial codes through time using a novel analytic method applied to the classic memory-delay saccade task. Three-dimensional recordings of head-unrestrained gaze shifts were made in two monkeys trained to make gaze shifts toward briefly flashed targets after a variable delay (450-1500 ms). A preliminary analysis of visual and motor response fields in 74 FEF neurons eliminated most potential models for spatial coding at the neuron population level, as in our previous study (Sajad et al., 2015). We then focused on the spatiotemporal transition from an eye-centered target code (T; preferred in the visual response) to an eye-centered intended gaze position code (G; preferred in the movement response) during the memory delay interval. We treated neural population codes as a continuous spatiotemporal variable by dividing the space spanning T and G into intermediate T-G models and dividing the task into discrete steps through time. We found that FEF delay activity, especially in visuomovement cells, progressively transitions from T through intermediate T-G codes that approach, but do not reach, G. This was followed by a final discrete transition from these intermediate T-G delay codes to a "pure" G code in movement cells without delay activity. These results demonstrate that FEF activity undergoes a series of sensory-memory-motor transformations, including a dynamically evolving spatial memory signal and an imperfect memory-to-motor transformation.

An interference account of the missing-VP effect

PubMed Central

Häussler, Jana; Bader, Markus

2015-01-01

Sentences with doubly center-embedded relative clauses in which a verb phrase (VP) is missing are sometimes perceived as grammatical, thus giving rise to an illusion of grammaticality. In this paper, we provide a new account of why missing-VP sentences, which are both complex and ungrammatical, lead to an illusion of grammaticality, the so-called missing-VP effect. We propose that the missing-VP effect in particular, and processing difficulties with multiply center-embedded clauses more generally, are best understood as resulting from interference during cue-based retrieval. When processing a sentence with double center-embedding, a retrieval error due to interference can cause the verb of an embedded clause to be erroneously attached into a higher clause. This can lead to an illusion of grammaticality in the case of missing-VP sentences and to processing complexity in the case of complete sentences with double center-embedding. Evidence for an interference account of the missing-VP effect comes from experiments that have investigated the missing-VP effect in German using a speeded grammaticality judgments procedure. We review this evidence and then present two new experiments that show that the missing-VP effect can be found in German also with less restricting procedures. One experiment was a questionnaire study which required grammaticality judgments from participants without imposing any time constraints. The second experiment used a self-paced reading procedure and did not require any judgments. Both experiments confirm the prior findings of missing-VP effects in German and also show that the missing-VP effect is subject to a primacy effect as known from the memory literature. Based on this evidence, we argue that an account of missing-VP effects in terms of interference during cue-based retrieval is superior to accounts in terms of limited memory resources or in terms of experience with embedded structures. PMID:26136698

Chromatin accessibility prediction via convolutional long short-term memory networks with k-mer embedding.

PubMed

Min, Xu; Zeng, Wanwen; Chen, Ning; Chen, Ting; Jiang, Rui

2017-07-15

Experimental techniques for measuring chromatin accessibility are expensive and time consuming, appealing for the development of computational approaches to predict open chromatin regions from DNA sequences. Along this direction, existing methods fall into two classes: one based on handcrafted k -mer features and the other based on convolutional neural networks. Although both categories have shown good performance in specific applications thus far, there still lacks a comprehensive framework to integrate useful k -mer co-occurrence information with recent advances in deep learning. We fill this gap by addressing the problem of chromatin accessibility prediction with a convolutional Long Short-Term Memory (LSTM) network with k -mer embedding. We first split DNA sequences into k -mers and pre-train k -mer embedding vectors based on the co-occurrence matrix of k -mers by using an unsupervised representation learning approach. We then construct a supervised deep learning architecture comprised of an embedding layer, three convolutional layers and a Bidirectional LSTM (BLSTM) layer for feature learning and classification. We demonstrate that our method gains high-quality fixed-length features from variable-length sequences and consistently outperforms baseline methods. We show that k -mer embedding can effectively enhance model performance by exploring different embedding strategies. We also prove the efficacy of both the convolution and the BLSTM layers by comparing two variations of the network architecture. We confirm the robustness of our model to hyper-parameters by performing sensitivity analysis. We hope our method can eventually reinforce our understanding of employing deep learning in genomic studies and shed light on research regarding mechanisms of chromatin accessibility. The source code can be downloaded from https://github.com/minxueric/ismb2017_lstm . tingchen@tsinghua.edu.cn or ruijiang@tsinghua.edu.cn. Supplementary materials are available at Bioinformatics online. © The Author 2017. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com

Chromatin accessibility prediction via convolutional long short-term memory networks with k-mer embedding

PubMed Central

Min, Xu; Zeng, Wanwen; Chen, Ning; Chen, Ting; Jiang, Rui

2017-01-01

Abstract Motivation: Experimental techniques for measuring chromatin accessibility are expensive and time consuming, appealing for the development of computational approaches to predict open chromatin regions from DNA sequences. Along this direction, existing methods fall into two classes: one based on handcrafted k-mer features and the other based on convolutional neural networks. Although both categories have shown good performance in specific applications thus far, there still lacks a comprehensive framework to integrate useful k-mer co-occurrence information with recent advances in deep learning. Results: We fill this gap by addressing the problem of chromatin accessibility prediction with a convolutional Long Short-Term Memory (LSTM) network with k-mer embedding. We first split DNA sequences into k-mers and pre-train k-mer embedding vectors based on the co-occurrence matrix of k-mers by using an unsupervised representation learning approach. We then construct a supervised deep learning architecture comprised of an embedding layer, three convolutional layers and a Bidirectional LSTM (BLSTM) layer for feature learning and classification. We demonstrate that our method gains high-quality fixed-length features from variable-length sequences and consistently outperforms baseline methods. We show that k-mer embedding can effectively enhance model performance by exploring different embedding strategies. We also prove the efficacy of both the convolution and the BLSTM layers by comparing two variations of the network architecture. We confirm the robustness of our model to hyper-parameters by performing sensitivity analysis. We hope our method can eventually reinforce our understanding of employing deep learning in genomic studies and shed light on research regarding mechanisms of chromatin accessibility. Availability and implementation: The source code can be downloaded from https://github.com/minxueric/ismb2017_lstm. Contact: tingchen@tsinghua.edu.cn or ruijiang@tsinghua.edu.cn Supplementary information: Supplementary materials are available at Bioinformatics online. PMID:28881969

Securing resource constraints embedded devices using elliptic curve cryptography

NASA Astrophysics Data System (ADS)

Tam, Tony; Alfasi, Mohamed; Mozumdar, Mohammad

2014-06-01

The use of smart embedded device has been growing rapidly in recent time because of miniaturization of sensors and platforms. Securing data from these embedded devices is now become one of the core challenges both in industry and research community. Being embedded, these devices have tight constraints on resources such as power, computation, memory, etc. Hence it is very difficult to implement traditional Public Key Cryptography (PKC) into these resource constrained embedded devices. Moreover, most of the public key security protocols requires both public and private key to be generated together. In contrast with this, Identity Based Encryption (IBE), a public key cryptography protocol, allows a public key to be generated from an arbitrary string and the corresponding private key to be generated later on demand. While IBE has been actively studied and widely applied in cryptography research, conventional IBE primitives are also computationally demanding and cannot be efficiently implemented on embedded system. Simplified version of the identity based encryption has proven its competence in being robust and also satisfies tight budget of the embedded platform. In this paper, we describe the choice of several parameters for implementing lightweight IBE in resource constrained embedded sensor nodes. Our implementation of IBE is built using elliptic curve cryptography (ECC).

Super-active shape memory alloy composites

NASA Astrophysics Data System (ADS)

Barrett, Ronald M.; Gross, R. Steven

1995-05-01

A new type of very low stiffness super-active composite material is presented. This laminate uses shape-memory alloy (SMA) filaments which are embedded within a low Durometer silicone matrix. The purpose is to develop an active composite in which the local strains within the SMA actuator material will be approximately 1% while the laminate strains will be at least an order of magnitude larger. This type of laminate will be useful for biomimetic, biomedical, surgical and prosthetic applications in which the very high actuator strength of conventional SMA filaments is too great for biological tissues. A modified form of moment and force-balance analysis is used to model the performance of the super-active shape-memory alloy composite (SASMAC). The analytical models are used to predict the performance of a SASMAC pull-pull actuator which uses 10 mil diameter Tinel alloy K actuators embedded in a 0.10' thick, 25 Durometer silicon matrix. The results of testing demonstrate that the laminate is capable of straining up to 10% with theory and experiment in good agreement. Fatigue testing was conducted on the actuator for 1,000 cycles. Because the local strains within the SMA were kept to less than 1%, the element showed no degradation in performance.

Super-active shape-memory alloy composites

NASA Astrophysics Data System (ADS)

Barrett, Ron; Gross, R. Steven

1996-06-01

A new type of very-low-stiffness super-active composite material is presented. This laminate uses shape-memory alloy (SMA) filaments which are embedded within a low-hardness silicone matrix. The purpose is to develop an active composite in which the local strains within the SMA actuator material will be approximately 1%, while the laminate strains will be at least an order of magnitude larger. This type of laminate will be useful for biomimetic, biomedical, surgical and prosthetic applications in which the very high stiffness and actuation strength of conventional SMA filaments are too great for biological tissues. A modified form of moment and force-balance analysis is used to model the performance of the super-active shape-memory alloy composite (SASMAC). The analytical models are used to predict the performance of a SASMAC pull - pull actuator which uses 10 mil diameter Tinel alloy K actuators embedded in a 0.10" thick, 25 Durometer silicone matrix. The results of testing demonstrate that the laminate is capable of straining up to 10% with theory and experiment in good agreement. Fatigue testing was conducted on the actuator for 1 000 cycles. Because the local strains within the SMA were kept to less than 1%, the element showed no degradation in performance.

Sptrace

NASA Technical Reports Server (NTRS)

Burleigh, Scott C.

2011-01-01

Sptrace is a general-purpose space utilization tracing system that is conceptually similar to the commercial Purify product used to detect leaks and other memory usage errors. It is designed to monitor space utilization in any sort of heap, i.e., a region of data storage on some device (nominally memory; possibly shared and possibly persistent) with a flat address space. This software can trace usage of shared and/or non-volatile storage in addition to private RAM (random access memory). Sptrace is implemented as a set of C function calls that are invoked from within the software that is being examined. The function calls fall into two broad classes: (1) functions that are embedded within the heap management software [e.g., JPL's SDR (Simple Data Recorder) and PSM (Personal Space Management) systems] to enable heap usage analysis by populating a virtual time-sequenced log of usage activity, and (2) reporting functions that are embedded within the application program whose behavior is suspect. For ease of use, these functions may be wrapped privately inside public functions offered by the heap management software. Sptrace can be used for VxWorks or RTEMS realtime systems as easily as for Linux or OS/X systems.

Embedding memories in colloidal gels though oscillatory shear

NASA Astrophysics Data System (ADS)

Schwen, Eric; Ramaswamay, Meera; Jan, Linda; Cheng, Chieh-Min; Cohen, Itai

While gels are ubiquitous in applications from food products to filtration, their mechanical properties are usually determined by self-assembly. We use oscillatory shear to train colloidal gels, embedding memories of the training protocol in rheological responses such as the yield strain and the gel network structures. When our gels undergo shear, the particles are forced to rearrange until they organize into structures that can locally undergo reversible shear cycles. We utilize a high-speed confocal microscope and a shear cell to image a colloidal gel while simultaneously straining the gel and measuring its shear stresses. By comparing stroboscopic images of the gel, we quantify the decrease in particle rearrangement as the gel develops reversible structures. We analyze and construct a model for the rates at which different regions in the gel approach reversible configurations. Through characterizing the gel network, we determine the structural origins of these shear training memories in gels. These results may allow us to use shear training protocols to produce gels with controllable yield strains and to better understand changes in the microstructure and rheology of gels that undergo repeated shear through mixing or flowing. This research was supported in part by NSF CBET 1509308 and Xerox Corporation.

Power impact of loop buffer schemes for biomedical wireless sensor nodes.

PubMed

Artes, Antonio; Ayala, Jose L; Catthoor, Francky

2012-11-06

Instruction memory organisations are pointed out as one of the major sources of energy consumption in embedded systems. As these systems are characterised by restrictive resources and a low-energy budget, any enhancement in this component allows not only to decrease the energy consumption but also to have a better distribution of the energy budget throughout the system. Loop buffering is an effective scheme to reduce energy consumption in instruction memory organisations. In this paper, the loop buffer concept is applied in real-life embedded applications that are widely used in biomedical Wireless Sensor Nodes, to show which scheme of loop buffer is more suitable for applications with certain behaviour. Post-layout simulations demonstrate that a trade-off exists between the complexity of the loop buffer architecture and the energy savings of utilising it. Therefore, the use of loop buffer architectures in order to optimise the instruction memory organisation from the energy efficiency point of view should be evaluated carefully, taking into account two factors: (1) the percentage of the execution time of the application that is related to the execution of the loops, and (2) the distribution of the execution time percentage over each one of the loops that form the application.

Noncredible cognitive performance at clinical evaluation of adult ADHD: An embedded validity indicator in a visuospatial working memory test.

PubMed

Fuermaier, Anselm B M; Tucha, Oliver; Koerts, Janneke; Lange, Klaus W; Weisbrod, Matthias; Aschenbrenner, Steffen; Tucha, Lara

2017-12-01

The assessment of performance validity is an essential part of the neuropsychological evaluation of adults with attention-deficit/hyperactivity disorder (ADHD). Most available tools, however, are inaccurate regarding the identification of noncredible performance. This study describes the development of a visuospatial working memory test, including a validity indicator for noncredible cognitive performance of adults with ADHD. Visuospatial working memory of adults with ADHD (n = 48) was first compared to the test performance of healthy individuals (n = 48). Furthermore, a simulation design was performed including 252 individuals who were randomly assigned to either a control group (n = 48) or to 1 of 3 simulation groups who were requested to feign ADHD (n = 204). Additional samples of 27 adults with ADHD and 69 instructed simulators were included to cross-validate findings from the first samples. Adults with ADHD showed impaired visuospatial working memory performance of medium size as compared to healthy individuals. Simulation groups committed significantly more errors and had shorter response times as compared to patients with ADHD. Moreover, binary logistic regression analysis was carried out to derive a validity index that optimally differentiates between true and feigned ADHD. ROC analysis demonstrated high classification rates of the validity index, as shown in excellent specificity (95.8%) and adequate sensitivity (60.3%). The visuospatial working memory test as presented in this study therefore appears sensitive in indicating cognitive impairment of adults with ADHD. Furthermore, the embedded validity index revealed promising results concerning the detection of noncredible cognitive performance of adults with ADHD. (PsycINFO Database Record (c) 2017 APA, all rights reserved).

Short-term memory for spatial, sequential and duration information.

PubMed

Manohar, Sanjay G; Pertzov, Yoni; Husain, Masud

2017-10-01

Space and time appear to play key roles in the way that information is organized in short-term memory (STM). Some argue that they are crucial contexts within which other stored features are embedded, allowing binding of information that belongs together within STM. Here we review recent behavioral, neurophysiological and imaging studies that have sought to investigate the nature of spatial, sequential and duration representations in STM, and how these might break down in disease. Findings from these studies point to an important role of the hippocampus and other medial temporal lobe structures in aspects of STM, challenging conventional accounts of involvement of these regions in only long-term memory.

Multiprocessor and memory architecture of the neurocomputer SYNAPSE-1.

PubMed

Ramacher, U; Raab, W; Anlauf, J; Hachmann, U; Beichter, J; Brüls, N; Wesseling, M; Sicheneder, E; Männer, R; Glass, J

1993-12-01

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude--including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural algorithms programming language, embedded in C(+2) has been defined for the user to cope with the neurocomputer. In a benchmark test, the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.

Detection of weak signals in memory thermal baths.

PubMed

Jiménez-Aquino, J I; Velasco, R M; Romero-Bastida, M

2014-11-01

The nonlinear relaxation time and the statistics of the first passage time distribution in connection with the quasideterministic approach are used to detect weak signals in the decay process of the unstable state of a Brownian particle embedded in memory thermal baths. The study is performed in the overdamped approximation of a generalized Langevin equation characterized by an exponential decay in the friction memory kernel. A detection criterion for each time scale is studied: The first one is referred to as the receiver output, which is given as a function of the nonlinear relaxation time, and the second one is related to the statistics of the first passage time distribution.

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

NASA Astrophysics Data System (ADS)

Sakamoto, Toshitsugu; Tada, Munehiro; Tsuji, Yukihide; Makiyama, Hideki; Hasegawa, Takumi; Yamamoto, Yoshiki; Okanishi, Shinobu; Banno, Naoki; Miyamura, Makoto; Okamoto, Koichiro; Iguchi, Noriyuki; Ogasahara, Yasuhiro; Oda, Hidekazu; Kamohara, Shiro; Yamagata, Yasushi; Sugii, Nobuyuki; Hada, Hiromitsu

2015-04-01

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34-1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.

Evaluating automatic attentional capture by self-relevant information.

PubMed

Ocampo, Brenda; Kahan, Todd A

2016-01-01

Our everyday decisions and memories are inadvertently influenced by self-relevant information. For example, we are faster and more accurate at making perceptual judgments about stimuli associated with ourselves, such as our own face or name, as compared with familiar non-self-relevant stimuli. Humphreys and Sui propose a "self-attention network" to account for these effects, wherein self-relevant stimuli automatically capture our attention and subsequently enhance the perceptual processing of self-relevant information. We propose that the masked priming paradigm and continuous flash suppression represent two ways to experimentally examine these controversial claims.

Micron MT29F128G08AJAAA 128GB Asynchronous Flash Memory Total Ionizing Dose Characterization Test Report

NASA Technical Reports Server (NTRS)

Campola, Michael; Wyrwas, Edward

2017-01-01

The purpose of this test was to characterize the Micron MT29F128G08AJAAAs parameter degradation for total dose response and to evaluate and compare lot date codes for sensitivity. In the test, the device was exposed to both low dose and high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits and overall chip and die health were investigated to determine which lot is more robust.

High performance wire grid polarizers using jet and flashTM imprint lithography

NASA Astrophysics Data System (ADS)

Ahn, Sean; Yang, Jack; Miller, Mike; Ganapathisubramanian, Maha; Menezes, Marlon; Choi, Jin; Xu, Frank; Resnick, Douglas J.; Sreenivasan, S. V.

2013-03-01

The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area roll to roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we have developed a roll based J-FIL process and applied it to technology demonstrator tool, the LithoFlex 100, to fabricate large area flexible bilayer wire grid polarizers (WGP) and high performance WGPs on rigid glass substrates. Extinction ratios of better than 10000 were obtained for the glass-based WGPs. Two simulation packages were also employed to understand the effects of pitch, aluminum thickness and pattern defectivity on the optical performance of the WGP devices. It was determined that the WGPs can be influenced by both clear and opaque defects in the gratings, however the defect densities are relaxed relative to the requirements of a high density semiconductor device.

Progress in mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Selinidis, Kosta S.; Brooks, Cynthia B.; Doyle, Gary F.; Brown, Laura; Jones, Chris; Imhof, Joseph; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2011-04-01

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and processes specifically for semiconductor applications. The requirements needed for semiconductors dictate the need for a well defined form factor for both master and replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6" x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting such as a pre-patterned mesa. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm, 3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance results of this marks are comparable to the baseline fused silica align marks.

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

NASA Astrophysics Data System (ADS)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these issues is provided from a materials science point of view.

Event boundaries and memory improvement.

PubMed

Pettijohn, Kyle A; Thompson, Alexis N; Tamplin, Andrea K; Krawietz, Sabine A; Radvansky, Gabriel A

2016-03-01

The structure of events can influence later memory for information that is embedded in them, with evidence indicating that event boundaries can both impair and enhance memory. The current study explored whether the presence of event boundaries during encoding can structure information to improve memory. In Experiment 1, memory for a list of words was tested in which event structure was manipulated by having participants walk through a doorway, or not, halfway through the word list. In Experiment 2, memory for lists of words was tested in which event structure was manipulated using computer windows. Finally, in Experiments 3 and 4, event structure was manipulated by having event shifts described in narrative texts. The consistent finding across all of these methods and materials was that memory was better when the information was distributed across two events rather than combined into a single event. Moreover, Experiment 4 demonstrated that increasing the number of event boundaries from one to two increased the memory benefit. These results are interpreted in the context of the Event Horizon Model of event cognition. Copyright © 2015 Elsevier B.V. All rights reserved.

Sequential associative memory with nonuniformity of the layer sizes.

PubMed

Teramae, Jun-Nosuke; Fukai, Tomoki

2007-01-01

Sequence retrieval has a fundamental importance in information processing by the brain, and has extensively been studied in neural network models. Most of the previous sequential associative memory embedded sequences of memory patterns have nearly equal sizes. It was recently shown that local cortical networks display many diverse yet repeatable precise temporal sequences of neuronal activities, termed "neuronal avalanches." Interestingly, these avalanches displayed size and lifetime distributions that obey power laws. Inspired by these experimental findings, here we consider an associative memory model of binary neurons that stores sequences of memory patterns with highly variable sizes. Our analysis includes the case where the statistics of these size variations obey the above-mentioned power laws. We study the retrieval dynamics of such memory systems by analytically deriving the equations that govern the time evolution of macroscopic order parameters. We calculate the critical sequence length beyond which the network cannot retrieve memory sequences correctly. As an application of the analysis, we show how the present variability in sequential memory patterns degrades the power-law lifetime distribution of retrieved neural activities.

The BlueGene/L supercomputer

NASA Astrophysics Data System (ADS)

Bhanota, Gyan; Chen, Dong; Gara, Alan; Vranas, Pavlos

2003-05-01

The architecture of the BlueGene/L massively parallel supercomputer is described. Each computing node consists of a single compute ASIC plus 256 MB of external memory. The compute ASIC integrates two 700 MHz PowerPC 440 integer CPU cores, two 2.8 Gflops floating point units, 4 MB of embedded DRAM as cache, a memory controller for external memory, six 1.4 Gbit/s bi-directional ports for a 3-dimensional torus network connection, three 2.8 Gbit/s bi-directional ports for connecting to a global tree network and a Gigabit Ethernet for I/O. 65,536 of such nodes are connected into a 3-d torus with a geometry of 32×32×64. The total peak performance of the system is 360 Teraflops and the total amount of memory is 16 TeraBytes.

Development of a monolithic ferrite memory array

NASA Technical Reports Server (NTRS)

Heckler, C. H., Jr.; Bhiwandker, N. C.

1972-01-01

The results of the development and testing of ferrite monolithic memory arrays are presented. This development required the synthesis of ferrite materials having special magnetic and physical characteristics and the development of special processes; (1) for making flexible sheets (laminae) of the ferrite composition, (2) for embedding conductors in ferrite, and (3) bonding ferrite laminae together to form a monolithic structure. Major problems encountered in each of these areas and their solutions are discussed. Twenty-two full-size arrays were fabricated and fired during the development of these processes. The majority of these arrays were tested for their memory characteristics as well as for their physical characteristics and the results are presented. The arrays produced during this program meet the essential goals and demonstrate the feasibility of fabricating monolithic ferrite memory arrays by the processes developed.

Modiolus-Hugging Intracochlear Electrode Array with Shape Memory Alloy

PubMed Central

Min, Kyou Sik; Lim, Yoon Seob; Park, Se-Ik; Kim, Sung June

2013-01-01

In the cochlear implant system, the distance between spiral ganglia and the electrodes within the volume of the scala tympani cavity significantly affects the efficiency of the electrical stimulation in terms of the threshold current level and spatial selectivity. Because the spiral ganglia are situated inside the modiolus, the central axis of the cochlea, it is desirable that the electrode array hugs the modiolus to minimize the distance between the electrodes and the ganglia. In the present study, we propose a shape-memory-alloy-(SMA-) embedded intracochlear electrode which gives a straight electrode a curved modiolus-hugging shape using the restoration force of the SMA as triggered by resistive heating after insertion into the cochlea. An eight-channel ball-type electrode array is fabricated with an embedded titanium-nickel SMA backbone wire. It is demonstrated that the electrode array changes its shape in a transparent plastic human cochlear model. To verify the safe insertion of the electrode array into the human cochlea, the contact pressures during insertion at the electrode tip and the contact pressures over the electrode length after insertion were calculated using a 3D finite element analysis. The results indicate that the SMA-embedded electrode is functionally and mechanically feasible for clinical applications. PMID:23762181

Improving energy efficiency of Embedded DRAM Caches for High-end Computing Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

2014-01-01

With increasing system core-count, the size of last level cache (LLC) has increased and since SRAM consumes high leakage power, power consumption of LLCs is becoming a significant fraction of processor power consumption. To address this, researchers have used embedded DRAM (eDRAM) LLCs which consume low-leakage power. However, eDRAM caches consume a significant amount of energy in the form of refresh energy. In this paper, we propose ESTEEM, an energy saving technique for embedded DRAM caches. ESTEEM uses dynamic cache reconfiguration to turn-off a portion of the cache to save both leakage and refresh energy. It logically divides the cachemore » sets into multiple modules and turns-off possibly different number of ways in each module. Microarchitectural simulations confirm that ESTEEM is effective in improving performance and energy efficiency and provides better results compared to a recently-proposed eDRAM cache energy saving technique, namely Refrint. For single and dual-core simulations, the average saving in memory subsystem (LLC+main memory) on using ESTEEM is 25.8% and 32.6%, respectively and average weighted speedup are 1.09X and 1.22X, respectively. Additional experiments confirm that ESTEEM works well for a wide-range of system parameters.« less

Low-temperature spin dynamics of Mn-rich Mn(Ga)As nanoclusters embedded in a GaAs matrix

NASA Astrophysics Data System (ADS)

Wang, Weizhu; Deng, Jiajun; Lu, Jun; Sun, Baoquan; Zhao, Jianhua

2008-03-01

Recently, the composite systems of Mn-rich Mn(Ga)As nanoclusters embedded in GaAs matrices have received an increasing attention due to the large magneto-optical and magneto-resistance effects at room temperature which could be applied to spin-electronic devices. In this work, we report the low-temperature spin dynamic behaviours including memory effects and slow magnetic relaxation of such composite systems. The systems can be formed by in situ postgrowth annealing of (Ga,Mn)As films at 650 ^oC for 10 min because of spinodal decomposition. High-resolution TEM images show zincblende Mn-rich Mn(Ga)As nanoclusters with a diameter in the range of 10-20 nm embedded in a GaAs matrix. From zero-field cooled and field cooled measurements, we can observe a clear bifurcation of the two curves demonstrating the existence of the spin-glass-like phase below the blocking temperature in the systems with high Mn concentration. Memory effects and slow magnetic relaxation, the typical characteristics of spin-glass-like phases, are also detected, and the hierarchical model is confirmed to be in accordance with such low-temperature behaviours. On the other hand, for samples with low Mn content, ferromagnetic order remains up to 360K.

Computer vision camera with embedded FPGA processing

NASA Astrophysics Data System (ADS)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Status of climacteric symptoms among middle-aged to elderly Japanese women: comparison of general healthy women with women presenting at a menopausal clinic.

PubMed

Ikeda, Toshiyuki; Makita, Kazuya; Ishitani, Ken; Takamatsu, Kiyoshi; Horiguchi, Fumi; Nozawa, Shiro

2005-04-01

To examine the status and characteristics of climacteric symptoms reported by generally healthy middle-aged to elderly women in Japan, those living in Saitama Prefecture were surveyed . The subjects comprised 398 women ranging in age from 40 to <60 years (mean age, 50.5 years). Climacteric symptoms were objectively assessed using the Keio questionnaire. The total scores obtained for the 40 symptoms were used to calculate symptom prevalence and severity. (i) The most frequent symptom was poor memory, reported by 88.7% of the women. (ii) Lumbar-sacral back pain was rated as a severe symptom by the highest percentage of women (15.3%). (iii) The prevalence and severity of poor memory and lumbar-sacral back pain did not differ with menopausal status. (iv) Hot flashes and sweats were slightly higher in peri- and early postmenopausal women than in premenopausal women. The present study showed that healthy women who do not consult physicians because of climacteric symptoms are primarily concerned with age-related symptoms, such as poor memory, loss of hair, and forgetfulness.

[Development of a video image system for wireless capsule endoscopes based on DSP].

PubMed

Yang, Li; Peng, Chenglin; Wu, Huafeng; Zhao, Dechun; Zhang, Jinhua

2008-02-01

A video image recorder to record video picture for wireless capsule endoscopes was designed. TMS320C6211 DSP of Texas Instruments Inc. is the core processor of this system. Images are periodically acquired from Composite Video Broadcast Signal (CVBS) source and scaled by video decoder (SAA7114H). Video data is transported from high speed buffer First-in First-out (FIFO) to Digital Signal Processor (DSP) under the control of Complex Programmable Logic Device (CPLD). This paper adopts JPEG algorithm for image coding, and the compressed data in DSP was stored to Compact Flash (CF) card. TMS320C6211 DSP is mainly used for image compression and data transporting. Fast Discrete Cosine Transform (DCT) algorithm and fast coefficient quantization algorithm are used to accelerate operation speed of DSP and decrease the executing code. At the same time, proper address is assigned for each memory, which has different speed;the memory structure is also optimized. In addition, this system uses plenty of Extended Direct Memory Access (EDMA) to transport and process image data, which results in stable and high performance.

Resistive Switching of Ta2O5-Based Self-Rectifying Vertical-Type Resistive Switching Memory

NASA Astrophysics Data System (ADS)

Ryu, Sungyeon; Kim, Seong Keun; Choi, Byung Joon

2018-01-01

To efficiently increase the capacity of resistive switching random-access memory (RRAM) while maintaining the same area, a vertical structure similar to a vertical NAND flash structure is needed. In addition, the sneak-path current through the half-selected neighboring memory cell should be mitigated by integrating a selector device with each RRAM cell. In this study, an integrated vertical-type RRAM cell and selector device was fabricated and characterized. Ta2O5 as the switching layer and TaOxNy as the selector layer were used to preliminarily study the feasibility of such an integrated device. To make the side contact of the bottom electrode with active layers, a thick Al2O3 insulating layer was placed between the Pt bottom electrode and the Ta2O5/TaOxNy stacks. Resistive switching phenomena were observed under relatively low currents (below 10 μA) in this vertical-type RRAM device. The TaOxNy layer acted as a nonlinear resistor with moderate nonlinearity. Its low-resistance-state and high-resistance-state were well retained up to 1000 s.

Prospective memory in an air traffic control simulation: External aids that signal when to act

PubMed Central

Loft, Shayne; Smith, Rebekah E.; Bhaskara, Adella

2011-01-01

At work and in our personal life we often need to remember to perform intended actions at some point in the future, referred to as Prospective Memory. Individuals sometimes forget to perform intentions in safety-critical work contexts. Holding intentions can also interfere with ongoing tasks. We applied theories and methods from the experimental literature to test the effectiveness of external aids in reducing prospective memory error and costs to ongoing tasks in an air traffic control simulation. Participants were trained to accept and hand-off aircraft, and to detect aircraft conflicts. For the prospective memory task participants were required to substitute alternative actions for routine actions when accepting target aircraft. Across two experiments, external display aids were provided that presented the details of target aircraft and associated intended actions. We predicted that aids would only be effective if they provided information that was diagnostic of target occurrence and in this study we examined the utility of aids that directly cued participants when to allocate attention to the prospective memory task. When aids were set to flash when the prospective memory target aircraft needed to be accepted, prospective memory error and costs to ongoing tasks of aircraft acceptance and conflict detection were reduced. In contrast, aids that did not alert participants specifically when the target aircraft were present provided no advantage compared to when no aids we used. These findings have practical implications for the potential relative utility of automated external aids for occupations where individuals monitor multi-item dynamic displays. PMID:21443381

Prospective memory in an air traffic control simulation: external aids that signal when to act.

PubMed

Loft, Shayne; Smith, Rebekah E; Bhaskara, Adella

2011-03-01

At work and in our personal life we often need to remember to perform intended actions at some point in the future, referred to as Prospective Memory. Individuals sometimes forget to perform intentions in safety-critical work contexts. Holding intentions can also interfere with ongoing tasks. We applied theories and methods from the experimental literature to test the effectiveness of external aids in reducing prospective memory error and costs to ongoing tasks in an air traffic control simulation. Participants were trained to accept and hand-off aircraft and to detect aircraft conflicts. For the prospective memory task, participants were required to substitute alternative actions for routine actions when accepting target aircraft. Across two experiments, external display aids were provided that presented the details of target aircraft and associated intended actions. We predicted that aids would only be effective if they provided information that was diagnostic of target occurrence, and in this study, we examined the utility of aids that directly cued participants when to allocate attention to the prospective memory task. When aids were set to flash when the prospective memory target aircraft needed to be accepted, prospective memory error and costs to ongoing tasks of aircraft acceptance and conflict detection were reduced. In contrast, aids that did not alert participants specifically when the target aircraft were present provided no advantage compared to when no aids were used. These findings have practical implications for the potential relative utility of automated external aids for occupations where individuals monitor multi-item dynamic displays.

The conjunction of non-consciously perceived object identity and spatial position can be retained during a visual short-term memory task.

PubMed

Bergström, Fredrik; Eriksson, Johan

2015-01-01

Although non-consciously perceived information has previously been assumed to be short-lived (< 500 ms), recent findings show that non-consciously perceived information can be maintained for at least 15 s. Such findings can be explained as working memory without a conscious experience of the information to be retained. However, whether or not working memory can operate on non-consciously perceived information remains controversial, and little is known about the nature of such non-conscious visual short-term memory (VSTM). Here we used continuous flash suppression to render stimuli non-conscious, to investigate the properties of non-consciously perceived representations in delayed match-to-sample (DMS) tasks. In Experiment I we used variable delays (5 or 15 s) and found that performance was significantly better than chance and was unaffected by delay duration, thereby replicating previous findings. In Experiment II the DMS task required participants to combine information of spatial position and object identity on a trial-by-trial basis to successfully solve the task. We found that the conjunction of spatial position and object identity was retained, thereby verifying that non-conscious, trial-specific information can be maintained for prospective use. We conclude that our results are consistent with a working memory interpretation, but that more research is needed to verify this interpretation.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V. A. L.

2013-02-01

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics.The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al2O3) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al2O3 dielectric layer) could be potentially integrated with large area flexible electronics. Electronic supplementary information (ESI) available: UV-vis spectrum of Au nanoparticle aqueous solution, transfer characteristics of the transistors without inserting an Au nanoparticle monolayer, AFM image of the pentacene layer, transfer characteristics at different program voltages and memory windows with respect to the P/E voltage. See DOI: 10.1039/c2nr32579a

Minimizing embedding impact in steganography using trellis-coded quantization

NASA Astrophysics Data System (ADS)

Filler, Tomáš; Judas, Jan; Fridrich, Jessica

2010-01-01

In this paper, we propose a practical approach to minimizing embedding impact in steganography based on syndrome coding and trellis-coded quantization and contrast its performance with bounds derived from appropriate rate-distortion bounds. We assume that each cover element can be assigned a positive scalar expressing the impact of making an embedding change at that element (single-letter distortion). The problem is to embed a given payload with minimal possible average embedding impact. This task, which can be viewed as a generalization of matrix embedding or writing on wet paper, has been approached using heuristic and suboptimal tools in the past. Here, we propose a fast and very versatile solution to this problem that can theoretically achieve performance arbitrarily close to the bound. It is based on syndrome coding using linear convolutional codes with the optimal binary quantizer implemented using the Viterbi algorithm run in the dual domain. The complexity and memory requirements of the embedding algorithm are linear w.r.t. the number of cover elements. For practitioners, we include detailed algorithms for finding good codes and their implementation. Finally, we report extensive experimental results for a large set of relative payloads and for different distortion profiles, including the wet paper channel.

Task set induces dynamic reallocation of resources in visual short-term memory.

PubMed

Sheremata, Summer L; Shomstein, Sarah

2017-08-01

Successful interaction with the environment requires the ability to flexibly allocate resources to different locations in the visual field. Recent evidence suggests that visual short-term memory (VSTM) resources are distributed asymmetrically across the visual field based upon task demands. Here, we propose that context, rather than the stimulus itself, determines asymmetrical distribution of VSTM resources. To test whether context modulates the reallocation of resources to the right visual field, task set, defined by memory-load, was manipulated to influence visual short-term memory performance. Performance was measured for single-feature objects embedded within predominantly single- or two-feature memory blocks. Therefore, context was varied to determine whether task set directly predicts changes in visual field biases. In accord with the dynamic reallocation of resources hypothesis, task set, rather than aspects of the physical stimulus, drove improvements in performance in the right- visual field. Our results show, for the first time, that preparation for upcoming memory demands directly determines how resources are allocated across the visual field.

Syntactic Recursion Facilitates and Working Memory Predicts Recursive Theory of Mind

PubMed Central

Arslan, Burcu; Hohenberger, Annette; Verbrugge, Rineke

2017-01-01

In this study, we focus on the possible roles of second-order syntactic recursion and working memory in terms of simple and complex span tasks in the development of second-order false belief reasoning. We tested 89 Turkish children in two age groups, one younger (4;6–6;5 years) and one older (6;7–8;10 years). Although second-order syntactic recursion is significantly correlated with the second-order false belief task, results of ordinal logistic regressions revealed that the main predictor of second-order false belief reasoning is complex working memory span. Unlike simple working memory and second-order syntactic recursion tasks, the complex working memory task required processing information serially with additional reasoning demands that require complex working memory strategies. Based on our results, we propose that children’s second-order theory of mind develops when they have efficient reasoning rules to process embedded beliefs serially, thus overcoming a possible serial processing bottleneck. PMID:28072823

Automatic selection of irrelevant object features through working memory: evidence for top-down attentional capture.

PubMed

Soto, David; Humphreys, Glyn W

2009-01-01

Recent research has shown that the contents of working memory (WM) can guide the early deployment of attention in visual search. Here, we assessed whether this guidance occurred for all attributes of items held in WM, or whether effects are based on just the attributes relevant for the memory task. We asked observers to hold in memory just the shape of a coloured object and to subsequently search for a target line amongst distractor lines, each embedded within a different object. On some trials, one of the objects in the search display could match the shape, the colour or both dimensions of the cue, but this object never contained the relevant target line. Relative to a neutral baseline, where there was no match between the memory and the search displays, search performance was impaired when a distractor object matched both the colour and the shape of the memory cue. The implications for the understanding of the interaction between WM and selection are discussed.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

PCI bus content-addressable-memory (CAM) implementation on FPGA for pattern recognition/image retrieval in a distributed environment

NASA Astrophysics Data System (ADS)

Megherbi, Dalila B.; Yan, Yin; Tanmay, Parikh; Khoury, Jed; Woods, C. L.

2004-11-01

Recently surveillance and Automatic Target Recognition (ATR) applications are increasing as the cost of computing power needed to process the massive amount of information continues to fall. This computing power has been made possible partly by the latest advances in FPGAs and SOPCs. In particular, to design and implement state-of-the-Art electro-optical imaging systems to provide advanced surveillance capabilities, there is a need to integrate several technologies (e.g. telescope, precise optics, cameras, image/compute vision algorithms, which can be geographically distributed or sharing distributed resources) into a programmable system and DSP systems. Additionally, pattern recognition techniques and fast information retrieval, are often important components of intelligent systems. The aim of this work is using embedded FPGA as a fast, configurable and synthesizable search engine in fast image pattern recognition/retrieval in a distributed hardware/software co-design environment. In particular, we propose and show a low cost Content Addressable Memory (CAM)-based distributed embedded FPGA hardware architecture solution with real time recognition capabilities and computing for pattern look-up, pattern recognition, and image retrieval. We show how the distributed CAM-based architecture offers a performance advantage of an order-of-magnitude over RAM-based architecture (Random Access Memory) search for implementing high speed pattern recognition for image retrieval. The methods of designing, implementing, and analyzing the proposed CAM based embedded architecture are described here. Other SOPC solutions/design issues are covered. Finally, experimental results, hardware verification, and performance evaluations using both the Xilinx Virtex-II and the Altera Apex20k are provided to show the potential and power of the proposed method for low cost reconfigurable fast image pattern recognition/retrieval at the hardware/software co-design level.

On the relationship between parallel computation and graph embedding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gupta, A.K.

1989-01-01

The problem of efficiently simulating an algorithm designed for an n-processor parallel machine G on an m-processor parallel machine H with n > m arises when parallel algorithms designed for an ideal size machine are simulated on existing machines which are of a fixed size. The author studies this problem when every processor of H takes over the function of a number of processors in G, and he phrases the simulation problem as a graph embedding problem. New embeddings presented address relevant issues arising from the parallel computation environment. The main focus centers around embedding complete binary trees into smaller-sizedmore » binary trees, butterflies, and hypercubes. He also considers simultaneous embeddings of r source machines into a single hypercube. Constant factors play a crucial role in his embeddings since they are not only important in practice but also lead to interesting theoretical problems. All of his embeddings minimize dilation and load, which are the conventional cost measures in graph embeddings and determine the maximum amount of time required to simulate one step of G on H. His embeddings also optimize a new cost measure called ({alpha},{beta})-utilization which characterizes how evenly the processors of H are used by the processors of G. Ideally, the utilization should be balanced (i.e., every processor of H simulates at most (n/m) processors of G) and the ({alpha},{beta})-utilization measures how far off from a balanced utilization the embedding is. He presents embeddings for the situation when some processors of G have different capabilities (e.g. memory or I/O) than others and the processors with different capabilities are to be distributed uniformly among the processors of H. Placing such conditions on an embedding results in an increase in some of the cost measures.« less

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

RTSJ memory areas and their affects on the performance of a flight-like attitude control system

NASA Technical Reports Server (NTRS)

Niessner, Albert F.; Benowitz, Edward G.

2003-01-01

The two most important factors in improving performance in any software system, but especially a real-time, embeded system, are knowing which components are the low performers, and knowing what can be done to improve their performance.

A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors.

PubMed

Acevedo-Avila, Ricardo; Gonzalez-Mendoza, Miguel; Garcia-Garcia, Andres

2016-05-28

Blob detection is a common task in vision-based applications. Most existing algorithms are aimed at execution on general purpose computers; while very few can be adapted to the computing restrictions present in embedded platforms. This paper focuses on the design of an algorithm capable of real-time blob detection that minimizes system memory consumption. The proposed algorithm detects objects in one image scan; it is based on a linked-list data structure tree used to label blobs depending on their shape and node information. An example application showing the results of a blob detection co-processor has been built on a low-powered field programmable gate array hardware as a step towards developing a smart video surveillance system. The detection method is intended for general purpose application. As such, several test cases focused on character recognition are also examined. The results obtained present a fair trade-off between accuracy and memory requirements; and prove the validity of the proposed approach for real-time implementation on resource-constrained computing platforms.

A Scalable Nonuniform Pointer Analysis for Embedded Program

NASA Technical Reports Server (NTRS)

Venet, Arnaud

2004-01-01

In this paper we present a scalable pointer analysis for embedded applications that is able to distinguish between instances of recursively defined data structures and elements of arrays. The main contribution consists of an efficient yet precise algorithm that can handle multithreaded programs. We first perform an inexpensive flow-sensitive analysis of each function in the program that generates semantic equations describing the effect of the function on the memory graph. These equations bear numerical constraints that describe nonuniform points-to relationships. We then iteratively solve these equations in order to obtain an abstract storage graph that describes the shape of data structures at every point of the program for all possible thread interleavings. We bring experimental evidence that this approach is tractable and precise for real-size embedded applications.

Enhancement of memory margins in the polymer composite of [6,6]-phenyl-C61-butyric acid methyl ester and polystyrene.

PubMed

Sun, Yanmei; Lu, Junguo; Ai, Chunpeng; Wen, Dianzhong; Bai, Xuduo

2016-11-09

Memory devices based on composites of polystyrene (PS) and [6,6]-phenyl-C 61 -butyric acid methyl ester (PCBM) were investigated with bistable resistive switching behavior. Current-voltage (I-V) curves for indium-tin-oxide (ITO)/PS + PCBM/Al devices with 33 wt% PCBM showed non-volatile, rewritable, flash memory properties with a maximum ON/OFF current ratio of 1 × 10 4 , which was 100 times larger than the ON/OFF ratio of the device with 5 wt% PCBM. For ITO/PS + PCBM/Al devices with 33 wt% PCBM, the write-read-erase-read test cycles demonstrated the bistable devices with ON and OFF states at the same voltage. The programmable ON and OFF states endured up to 10 4 read pulses and possessed a retention time of over 10 5 s, indicative of the memory stability of the device. In the OFF state, the I-V curve at lower voltages up to 0.45 V was attributed to the thermionic emission mechanism, and the I-V characteristics in the applied voltage above 0.5 V dominantly followed the space-charge-limited-current behaviors. In the ON state, the curve in the applied voltage range was related to an Ohmic mechanism.

On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortese, Simone, E-mail: simone.cortese@soton.ac.uk; Trapatseli, Maria; Khiat, Ali

2016-08-14

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin filmmore » sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.« less

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells.

PubMed

Paydavosi, Sarah; Aidala, Katherine E; Brown, Patrick R; Hashemi, Pouya; Supran, Geoffrey J; Osedach, Timothy P; Hoyt, Judy L; Bulović, Vladimir

2012-03-14

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells. © 2012 American Chemical Society

Impact of Recent Hardware and Software Trends on High Performance Transaction Processing and Analytics

NASA Astrophysics Data System (ADS)

Mohan, C.

In this paper, I survey briefly some of the recent and emerging trends in hardware and software features which impact high performance transaction processing and data analytics applications. These features include multicore processor chips, ultra large main memories, flash storage, storage class memories, database appliances, field programmable gate arrays, transactional memory, key-value stores, and cloud computing. While some applications, e.g., Web 2.0 ones, were initially built without traditional transaction processing functionality in mind, slowly system architects and designers are beginning to address such previously ignored issues. The availability, analytics and response time requirements of these applications were initially given more importance than ACID transaction semantics and resource consumption characteristics. A project at IBM Almaden is studying the implications of phase change memory on transaction processing, in the context of a key-value store. Bitemporal data management has also become an important requirement, especially for financial applications. Power consumption and heat dissipation properties are also major considerations in the emergence of modern software and hardware architectural features. Considerations relating to ease of configuration, installation, maintenance and monitoring, and improvement of total cost of ownership have resulted in database appliances becoming very popular. The MapReduce paradigm is now quite popular for large scale data analysis, in spite of the major inefficiencies associated with it.

Trichotomous processes in early memory development, aging, and neurocognitive impairment: a unified theory.

PubMed

Brainerd, C J; Reyna, V F; Howe, M L

2009-10-01

One of the most extensively investigated topics in the adult memory literature, dual memory processes, has had virtually no impact on the study of early memory development. The authors remove the key obstacles to such research by formulating a trichotomous theory of recall that combines the traditional dual processes of recollection and familiarity with a reconstruction process. The theory is then embedded in a hidden Markov model that measures all 3 processes with low-burden tasks that are appropriate for even young children. These techniques are applied to a large corpus of developmental studies of recall, yielding stable findings about the emergence of dual memory processes between childhood and young adulthood and generating tests of many theoretical predictions. The techniques are extended to the study of healthy aging and to the memory sequelae of common forms of neurocognitive impairment, resulting in a theoretical framework that is unified over 4 major domains of memory research: early development, mainstream adult research, aging, and neurocognitive impairment. The techniques are also extended to recognition, creating a unified dual process framework for recall and recognition.

Memory for faces: the effect of facial appearance and the context in which the face is encountered.

PubMed

Mattarozzi, Katia; Todorov, Alexander; Codispoti, Maurizio

2015-03-01

We investigated the effects of appearance of emotionally neutral faces and the context in which the faces are encountered on incidental face memory. To approximate real-life situations as closely as possible, faces were embedded in a newspaper article, with a headline that specified an action performed by the person pictured. We found that facial appearance affected memory so that faces perceived as trustworthy or untrustworthy were remembered better than neutral ones. Furthermore, the memory of untrustworthy faces was slightly better than that of trustworthy faces. The emotional context of encoding affected the details of face memory. Faces encountered in a neutral context were more likely to be recognized as only familiar. In contrast, emotionally relevant contexts of encoding, whether pleasant or unpleasant, increased the likelihood of remembering semantic and even episodic details associated with faces. These findings suggest that facial appearance (i.e., perceived trustworthiness) affects face memory. Moreover, the findings support prior evidence that the engagement of emotion processing during memory encoding increases the likelihood that events are not only recognized but also remembered.

Power Impact of Loop Buffer Schemes for Biomedical Wireless Sensor Nodes

PubMed Central

Artes, Antonio; Ayala, Jose L.; Catthoor, Francky

2012-01-01

Instruction memory organisations are pointed out as one of the major sources of energy consumption in embedded systems. As these systems are characterised by restrictive resources and a low-energy budget, any enhancement in this component allows not only to decrease the energy consumption but also to have a better distribution of the energy budget throughout the system. Loop buffering is an effective scheme to reduce energy consumption in instruction memory organisations. In this paper, the loop buffer concept is applied in real-life embedded applications that are widely used in biomedical Wireless Sensor Nodes, to show which scheme of loop buffer is more suitable for applications with certain behaviour. Post-layout simulations demonstrate that a trade-off exists between the complexity of the loop buffer architecture and the energy savings of utilising it. Therefore, the use of loop buffer architectures in order to optimise the instruction memory organisation from the energy efficiency point of view should be evaluated carefully, taking into account two factors: (1) the percentage of the execution time of the application that is related to the execution of the loops, and (2) the distribution of the execution time percentage over each one of the loops that form the application. PMID:23202202

Formation of SiGe nanocrystals embedded in Al2O3 for the application of write-once-read-many-times memory

NASA Astrophysics Data System (ADS)

Wu, Min-Lin; Wu, Yung-Hsien; Lin, Chia-Chun; Chen, Lun-Lun

2012-10-01

The structure of SiGe nanocrystals embedded in Al2O3 formed by sequential deposition of Al2O3/Si/Ge/Al2O3 and a subsequent annealing was confirmed by transmission electron microscopy and energy dispersive spectroscopy (EDS), and its application for write-once-read-many-times (WORM) memory devices was explored in this study. By applying a -10 V pulse for 1 s, a large amount of holes injected from Si substrate are stored in the nanocrystals and consequently, the current at +1.5 V increases by a factor of 104 as compared to that of the initial state. Even with a smaller -5 V pulse for 1 μs, a sufficiently large current ratio of 36 can still be obtained, verifying the low power operation. Since holes are stored in nanocrystals which are isolated from Si substrate by Al2O3 with good integrity and correspond to a large valence band offset with respect to Al2O3, desirable read endurance up to 105 cycles and excellent retention over 100 yr are achieved. Combining these promising characteristics, WORM memory devices are appropriate for high-performance archival storage applications.

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

NASA Astrophysics Data System (ADS)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage shift of 5.0 V has been achieved. For comparison purposes, metal nanocrystals have also been investigated by utilizing both of the physical deposition methods as mentioned above. Silver (Ag) nanocrystals with size of 10--40 nm have been embedded in HfAlO matrix in the trilayer capacitor structure and a flat-band voltage shift of 2.0 V has been achieved.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lei, Huan; Baker, Nathan A.; Li, Xiantao

We present a data-driven approach to determine the memory kernel and random noise of the generalized Langevin equation. To facilitate practical implementations, we parameterize the kernel function in the Laplace domain by a rational function, with coefficients directly linked to the equilibrium statistics of the coarse-grain variables. Further, we show that such an approximation can be constructed to arbitrarily high order. Within these approximations, the generalized Langevin dynamics can be embedded in an extended stochastic model without memory. We demonstrate how to introduce the stochastic noise so that the fluctuation-dissipation theorem is exactly satisfied.

Why Flash Type Matters: A Statistical Analysis

NASA Astrophysics Data System (ADS)

Mecikalski, Retha M.; Bitzer, Phillip M.; Carey, Lawrence D.

2017-09-01

While the majority of research only differentiates between intracloud (IC) and cloud-to-ground (CG) flashes, there exists a third flash type, known as hybrid flashes. These flashes have extensive IC components as well as return strokes to ground but are misclassified as CG flashes in current flash type analyses due to the presence of a return stroke. In an effort to show that IC, CG, and hybrid flashes should be separately classified, the two-sample Kolmogorov-Smirnov (KS) test was applied to the flash sizes, flash initiation, and flash propagation altitudes for each of the three flash types. The KS test statistically showed that IC, CG, and hybrid flashes do not have the same parent distributions and thus should be separately classified. Separate classification of hybrid flashes will lead to improved lightning-related research, because unambiguously classified hybrid flashes occur on the same order of magnitude as CG flashes for multicellular storms.

Nocturnal Hot Flashes: Relationship to Objective Awakenings and Sleep Stage Transitions

PubMed Central

Bianchi, Matt T.; Kim, Semmie; Galvan, Thania; White, David P.; Joffe, Hadine

2016-01-01

Study Objectives: While women report sleep interruption secondary to nighttime hot flashes, the sleep disrupting impact of nocturnal hot flashes (HF) is not well characterized. We utilized a model of induced HF to investigate the relationship of nighttime HF to sleep architecture and sleep-stage transitions. Methods: Twenty-eight healthy, premenopausal volunteers received the depot gonadotropin-releasing hormone agonist (GnRHa) leuprolide to rapidly induce menopause, manifesting with HF. Sleep disruption was measured on 2 polysomnograms conducted before and after 4–5 weeks on leuprolide, when HF had developed. Results: 165 HF episodes were recorded objectively during 48 sleep studies (mean 3.4 HF/night). After standardizing to sleep-stage time distribution, the majority of HF were recorded during wake (51.0%) and stage N1 (18.8%). Sixty-six percent of HF occurred within 5 minutes of an awakening, with 80% occurring just before or during the awakening. Objective HF were not associated with sleep disruption as measured by increased transitions to wake or N1, but self-reported nocturnal HF correlated with an increase from pre- to post-leuprolide in the rate of transitions to wake (p = 0.01), and to N1 (p = 0.008). Conclusions: By isolating the effect of HF on sleep in women without the confound of age-related sleep changes associated with natural menopause, this experimental model shows that HF arise most commonly during N1 and wake, typically preceding or occurring simultaneously with wake episodes. Perception of HF, but not objective HF, is linked to increased sleep-stage transitions, suggesting that sleep disruption increases awareness of and memory for nighttime HF events. Clinical Trial Registration: ClinicalTrials.gov Identifier: NCT01116401. Citation: Bianchi MT, Kim S, Galvan T, White DP, Joffe H. Nocturnal hot flashes: relationship to objective awakenings and sleep stage transitions. J Clin Sleep Med 2016;12(7):1003–1009. PMID:26951410

Time evolution of coherent structures in networks of Hindmarch Rose neurons

NASA Astrophysics Data System (ADS)

Mainieri, M. S.; Erichsen, R.; Brunnet, L. G.

2005-08-01

In the regime of partial synchronization, networks of diffusively coupled Hindmarch-Rose neurons show coherent structures developing in a region of the phase space which is wider than in the correspondent single neuron. Such structures are kept, without important changes, during several bursting periods. In this work, we study the time evolution of these structures and their dynamical stability under damage. This system may model the behavior of ensembles of neurons coupled through a bidirectional gap junction or, in a broader sense, it could also account for the molecular cascades present in the formation of flash and short time memory.

Moore's law realities for recording systems and memory storage components: HDD, tape, NAND, and optical

NASA Astrophysics Data System (ADS)

Fontana, Robert E.; Decad, Gary M.

2018-05-01

This paper describes trends in the storage technologies associated with Linear Tape Open (LTO) Tape cartridges, hard disk drives (HDD), and NAND Flash based storage devices including solid-state drives (SSD). This technology discussion centers on the relationship between cost/bit and bit density and, specifically on how the Moore's Law perception that areal density doubling and cost/bit halving every two years is no longer being achieved for storage based components. This observation and a Moore's Law Discussion are demonstrated with data from 9-year storage technology trends, assembled from publically available industry reporting sources.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Synchronizing Photography For High-Speed-Engine Research

NASA Technical Reports Server (NTRS)

Chun, K. S.

1989-01-01

Light flashes when shaft reaches predetermined angle. Synchronization system facilitates visualization of flow in high-speed internal-combustion engines. Designed for cinematography and holographic interferometry, system synchronizes camera and light source with predetermined rotational angle of engine shaft. 10-bit resolution of absolute optical shaft encoder adapted, and 2 to tenth power combinations of 10-bit binary data computed to corresponding angle values. Pre-computed angle values programmed into EPROM's (erasable programmable read-only memories) to use as angle lookup table. Resolves shaft angle to within 0.35 degree at rotational speeds up to 73,240 revolutions per minute.

A microcontroller-based implantable nerve stimulator used for rats.

PubMed

Sha, Hong; Zheng, Zheng; Wang, Yan; Ren, Chaoshi

2005-01-01

A microcontroller-based stimulator that can be flexible programmed after it has been implanted into a rat was studied. Programmability enables implanted stimulators to generate customized, complex protocols for experiments. After implantation, a coded light pulse train that contains information of specific identification will unlock a certain stimulator. If a command that changing the parameters is received, the microcontroller will update its flash memory after it affirms the commands. The whole size of it is only 1.6 cubic centimeters, and it can work for a month. The devices have been successfully used in animal behavior experiments, especially on rats.

UDCM Operating Procedure (Limited Functionality prototype)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Newell, Matthew R.

2016-06-14

The UDCM is a two channel low current measurement device designed to record sub-nano-amp to micro-amp currents from radiation detectors. The UDCM incorporates a Commercial-Off-The- Shelf (COTS) processor enabling both serial over USB as well as Ethernet communications. The instrument includes microSD and USB flash memory for data storage as well as a programmable High Voltage (HV) power supply for detector bias. The UDCM incorporates a unique TTL output feature first used in the LANL Current to Pulse Converter (CPC). Two SMA connectors on the UDCM provide TTL pulses at a frequency proportional to the input currents.

JTAG-based remote configuration of FPGAs over optical fibers

DOE PAGES

Deng, B.; Xu, H.; Liu, C.; ...

2015-01-28

In this study, a remote FPGA-configuration method based on JTAG extension over optical fibers is presented. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. The method has been verified successfully and used in the Demonstrator of Liquid-Argon Trigger Digitization Board (LTDB) for the ATLAS liquid argon calorimeter Phase-I trigger upgrade. All components on the FPGA side are verified to meet the radiation tolerance requirements.

Embedding Number-Combinations Practice Within Word-Problem Tutoring

PubMed Central

Powell, Sarah R.; Fuchs, Lynn S.; Fuchs, Douglas

2012-01-01

Two aspects of mathematics with which students with mathematics learning difficulty (MLD) often struggle are word problems and number-combination skills. This article describes a math program in which students receive instruction on using algebraic equations to represent the underlying problem structure for three word-problem types. Students also learn counting strategies for answering number combinations that they cannot retrieve from memory. Results from randomized-control trials indicated that embedding the counting strategies for number combinations produces superior word-problem and number-combination outcomes for students with MLD beyond tutoring programs that focus exclusively on number combinations or word problems. PMID:22661880

Embedding Number-Combinations Practice Within Word-Problem Tutoring.

PubMed

Powell, Sarah R; Fuchs, Lynn S; Fuchs, Douglas

2010-09-01

Two aspects of mathematics with which students with mathematics learning difficulty (MLD) often struggle are word problems and number-combination skills. This article describes a math program in which students receive instruction on using algebraic equations to represent the underlying problem structure for three word-problem types. Students also learn counting strategies for answering number combinations that they cannot retrieve from memory. Results from randomized-control trials indicated that embedding the counting strategies for number combinations produces superior word-problem and number-combination outcomes for students with MLD beyond tutoring programs that focus exclusively on number combinations or word problems.

Sensor Authentication: Embedded Processor Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

Svoboda, John

2012-09-25

Described is the c code running on the embedded Microchip 32bit PIC32MX575F256H located on the INL developed noise analysis circuit board. The code performs the following functions: Controls the noise analysis circuit board preamplifier voltage gains of 1, 10, 100, 000 Initializes the analog to digital conversion hardware, input channel selection, Fast Fourier Transform (FFT) function, USB communications interface, and internal memory allocations Initiates high resolution 4096 point 200 kHz data acquisition Computes complex 2048 point FFT and FFT magnitude. Services Host command set Transfers raw data to Host Transfers FFT result to host Communication error checking

Remembering Collective Violence: Broadening the Notion of Traumatic Memory in Post-Conflict Rehabilitation.

PubMed

Kevers, Ruth; Rober, Peter; Derluyn, Ilse; De Haene, Lucia

2016-12-01

In the aftermath of war and armed conflict, individuals and communities face the challenge of dealing with recollections of violence and atrocity. This article aims to contribute to a better understanding of processes of remembering and forgetting histories of violence in post-conflict communities and to reflect on related implications for trauma rehabilitation in post-conflict settings. Starting from the observation that memory operates at the core of PTSD symptomatology, we more closely explore how this notion of traumatic memory is conceptualized within PTSD-centered research and interventions. Subsequently, we aim to broaden this understanding of traumatic memory and post-trauma care by connecting to findings from social memory studies and transcultural trauma research. Drawing on an analysis of scholarly literature, this analysis develops into a perspective on memory that moves beyond a symptomatic framing toward an understanding of memory that emphasizes its relational, political, moral, and cultural nature. Post-conflict memory is presented as inextricably embedded in communal relations, involving ongoing trade-offs between individual and collective responses to trauma and a complex negotiation of speech and silence. In a concluding discussion, we develop implications of this broadened understanding for post-conflict trauma-focused rehabilitation.

Music training and working memory: an ERP study.

PubMed

George, Elyse M; Coch, Donna

2011-04-01

While previous research has suggested that music training is associated with improvements in various cognitive and linguistic skills, the mechanisms mediating or underlying these associations are mostly unknown. Here, we addressed the hypothesis that previous music training is related to improved working memory. Using event-related potentials (ERPs) and a standardized test of working memory, we investigated both neural and behavioral aspects of working memory in college-aged, non-professional musicians and non-musicians. Behaviorally, musicians outperformed non-musicians on standardized subtests of visual, phonological, and executive memory. ERPs were recorded in standard auditory and visual oddball paradigms (participants responded to infrequent deviant stimuli embedded in lists of standard stimuli). Electrophysiologically, musicians demonstrated faster updating of working memory (shorter latency P300s) in both the auditory and visual domains and musicians allocated more neural resources to auditory stimuli (larger amplitude P300), showing increased sensitivity to the auditory standard/deviant difference and less effortful updating of auditory working memory. These findings demonstrate that long-term music training is related to improvements in working memory, in both the auditory and visual domains and in terms of both behavioral and ERP measures. Copyright © 2011 Elsevier Ltd. All rights reserved.

Determination of the methylation status of MGMT in different regions within glioblastoma multiforme.

PubMed

Hamilton, Mark G; Roldán, Gloria; Magliocco, Anthony; McIntyre, John B; Parney, Ian; Easaw, Jacob C

2011-04-01

Epigenetic silencing of the MGMT gene through promoter methylation correlates with improved survival in Glioblastoma Multiforme (GBM) patients receiving concurrent chemoradiotherapy. Although the clinical benefit is primarily seen in patients with methylated MGMT promoter, some unmethylated patients also respond to Temozolomide. One possible explanation may be intratumoral heterogeneity. This study was designed to assess the methylation status of the MGMT promoter in different areas of GBM and determine if methylation status varied depending on the fixation technique (paraffin-embedding versus fresh frozen) used to store tissue. Using intraoperative navigation, biopsies were obtained from three distinct regions: the enhancing outer area, the non-enhancing inner core, and an area immediately outside the enhancing region. Only patients with GBM were included for evaluation and analysis. Samples taken from each area were divided with half stored by flash freezing and the other half stored using paraffin fixation. Methylation Specific-PCR (MS-PCR) was used for analysis of MGMT promoter methylation. Thirteen patients were included. Ten were male with a median age of 62 years. In each patient, samples were taken from the enhancing rim and the necrotic centre. However, it was not considered safe or feasible to obtain samples from the area immediately adjacent to the enhancing tumor rim in one case. All patients were homogeneous for methylation status throughout their tumor and tissue taken adjacent to it when frozen tissue was used. However, four patients had discrepancies in the MGMT promoter status between the frozen and paraffin-embedded blocks and one patient was not homogeneous within the tumor when paraffin-embedded tissue was used. MGMT promoter methylation status was homogeneous in all GBM tumors. Our observation that methylation status varied depending if the DNA was extracted from paraffin-embedded versus frozen tissue is concerning. Although the reason for this is unclear, we postulate that the timing from resection to fixation or the process of fixation itself may potentially alter methylation status in paraffin-embedded tumors.

Strong Motion Seismograph Based On MEMS Accelerometer

NASA Astrophysics Data System (ADS)

Teng, Y.; Hu, X.

2013-12-01

The MEMS strong motion seismograph we developed used the modularization method to design its software and hardware.It can fit various needs in different application situation.The hardware of the instrument is composed of a MEMS accelerometer,a control processor system,a data-storage system,a wired real-time data transmission system by IP network,a wireless data transmission module by 3G broadband,a GPS calibration module and power supply system with a large-volumn lithium battery in it. Among it,the seismograph's sensor adopted a three-axis with 14-bit high resolution and digital output MEMS accelerometer.Its noise level just reach about 99μg/√Hz and ×2g to ×8g dynamically selectable full-scale.Its output data rates from 1.56Hz to 800Hz. Its maximum current consumption is merely 165μA,and the device is so small that it is available in a 3mm×3mm×1mm QFN package. Furthermore,there is access to both low pass filtered data as well as high pass filtered data,which minimizes the data analysis required for earthquake signal detection. So,the data post-processing can be simplified. Controlling process system adopts a 32-bit low power consumption embedded ARM9 processor-S3C2440 and is based on the Linux operation system.The processor's operating clock at 400MHz.The controlling system's main memory is a 64MB SDRAM with a 256MB flash-memory.Besides,an external high-capacity SD card data memory can be easily added.So the system can meet the requirements for data acquisition,data processing,data transmission,data storage,and so on. Both wired and wireless network can satisfy remote real-time monitoring, data transmission,system maintenance,status monitoring or updating software.Linux was embedded and multi-layer designed conception was used.The code, including sensor hardware driver,the data acquisition,earthquake setting out and so on,was written on medium layer.The hardware driver consist of IIC-Bus interface driver, IO driver and asynchronous notification driver. The application program layer mainly concludes: earthquake parameter module, local database managing module, data transmission module, remote monitoring, FTP service and so on. The application layer adopted multi-thread process. The whole strong motion seismograph was encapsulated in a small aluminum box, which size is 80mm×120mm×55mm. The inner battery can work continuesly more than 24 hours. The MEMS accelerograph uses modular design for its software part and hardware part. It has remote software update function and can meet the following needs: a) Auto picking up the earthquake event; saving the data on wave-event files and hours files; It may be used for monitoring strong earthquake, explosion, bridge and house health. b) Auto calculate the earthquake parameters, and transferring those parameters by 3G wireless broadband network. This kind of seismograph has characteristics of low cost, easy installation. They can be concentrated in the urban region or areas need to specially care. We can set up a ground motion parameters quick report sensor network while large earthquake break out. Then high-resolution-fine shake-map can be easily produced for the need of emergency rescue. c) By loading P-wave detection program modules, it can be used for earthquake early warning for large earthquakes; d) Can easily construct a high-density layout seismic monitoring network owning remote control and modern intelligent earthquake sensor.

Operating characteristics of the implicit learning system supporting serial interception sequence learning.

PubMed

Sanchez, Daniel J; Reber, Paul J

2012-04-01

The memory system that supports implicit perceptual-motor sequence learning relies on brain regions that operate separately from the explicit, medial temporal lobe memory system. The implicit learning system therefore likely has distinct operating characteristics and information processing constraints. To attempt to identify the limits of the implicit sequence learning mechanism, participants performed the serial interception sequence learning (SISL) task with covertly embedded repeating sequences that were much longer than most previous studies: ranging from 30 to 60 (Experiment 1) and 60 to 90 (Experiment 2) items in length. Robust sequence-specific learning was observed for sequences up to 80 items in length, extending the known capacity of implicit sequence learning. In Experiment 3, 12-item repeating sequences were embedded among increasing amounts of irrelevant nonrepeating sequences (from 20 to 80% of training trials). Despite high levels of irrelevant trials, learning occurred across conditions. A comparison of learning rates across all three experiments found a surprising degree of constancy in the rate of learning regardless of sequence length or embedded noise. Sequence learning appears to be constant with the logarithm of the number of sequence repetitions practiced during training. The consistency in learning rate across experiments and conditions implies that the mechanisms supporting implicit sequence learning are not capacity-constrained by very long sequences nor adversely affected by high rates of irrelevant sequences during training.

Embedded performance validity tests within the Hopkins Verbal Learning Test - Revised and the Brief Visuospatial Memory Test - Revised.

PubMed

Sawyer, R John; Testa, S Marc; Dux, Moira

2017-01-01

Various research studies and neuropsychology practice organizations have reiterated the importance of developing embedded performance validity tests (PVTs) to detect potentially invalid neurocognitive test data. This study investigated whether measures within the Hopkins Verbal Learning Test - Revised (HVLT-R) and the Brief Visuospatial Memory Test - Revised (BVMT-R) could accurately classify individuals who fail two or more PVTs during routine clinical assessment. The present sample of 109 United States military veterans (Mean age = 52.4, SD = 13.3), all consisted of clinically referred patients and received a battery of neuropsychological tests. Based on performance validity findings, veterans were assigned to valid (n = 86) or invalid (n = 23) groups. Of the 109 patients in the overall sample, 77 were administered the HLVT-R and 75 were administered the BVMT-R, which were examined for classification accuracy. The HVLT-R Recognition Discrimination Index and the BVMT-R Retention Percentage showed good to adequate discrimination with an area under the curve of .78 and .70, respectively. The HVLT-R Recognition Discrimination Index showed sensitivity of .53 with specificity of .93. The BVMT-R Retention Percentage demonstrated sensitivity of .31 with specificity of .92. When used in conjunction with other PVTs, these new embedded PVTs may be effective in the detection of invalid test data, although they are not intended for use in patients with dementia.

Analysis of shape memory alloy sensory particles for damage detection via substructure and continuum damage modeling

NASA Astrophysics Data System (ADS)

Bielefeldt, Brent R.; Benzerga, A. Amine; Hartl, Darren J.

2016-04-01

The ability to monitor and predict the structural health of an aircraft is of growing importance to the aerospace industry. Currently, structural inspections and maintenance are based upon experiences with similar aircraft operating in similar conditions. While effective, these methods are time-intensive and unnecessary if the aircraft is not in danger of structural failure. It is imagined that future aircraft will utilize non-destructive evaluation methods, allowing for the near real-time monitoring of structural health. A particularly interesting method involves utilizing the unique transformation response of shape memory alloy (SMA) particles embedded in an aircraft structure. By detecting changes in the mechanical and/or electromagnetic responses of embedded particles, operators could detect the formation or propagation of fatigue cracks in the vicinity of these particles. This work focuses on a finite element model of SMA particles embedded in an aircraft wing using a substructure modeling approach in which degrees of freedom are retained only at specified points of connection to other parts or the application of boundary conditions, greatly reducing computational cost. Previous work evaluated isolated particle response to a static crack to numerically demonstrate and validate this damage detection method. This paper presents the implementation of a damage model to account for crack propagation and examine for the first time the effect of particle configuration and/or relative placement with respect to the ability to detect damage.

The Interplay of News Frames on Cognitive Complexity

ERIC Educational Resources Information Center

Shah, Dhavan V.; Kwak, Nojin; Schmierbach, Mike; Zubric, Jessica

2004-01-01

This research considers how distinct news frames work in combination to influence information processing. It extends framing research grounded in prospect theory (Tversky & Kahneman, 1981) and attribution theory (Iyengar, 1991) to study conditional framing effects on associative memory. Using a 2 x 3 experimental design embedded within a…

Research to create public memory of wilderness

Treesearch

William Stewart

2012-01-01

If wilderness experiences are distinct from general outdoor recreation experiences, then wilderness visitor research needs to reflect the distinction. If there are distinguishing characteristics, they would be linked to social and cultural meanings embedded in the Wilderness Act of 1964 and contemporary interpretations of it. Most research on wilderness visitor...

[Malaria and memory in the Veneto region of Italy].

PubMed

Pegoraro, Manuela; Crotti, Daniele

2009-09-01

Malaria and emigration are two terms deeply embedded in Veneto history, related to images far back in the past, unknown to younger generations. Losing one's own collective historical memory is a source of personal and cultural impoverishment and inevitably compromises one's awareness of the present, possibly leading to superficial judgements and hastily formed opinions. Such a situation is all the more serious in a geographical area, north-eastern Italy, where immigration is so abundant. In this paper the authors seek to retrieve, at least in part, this memory, especially in terms of history (to what extent malaria afflicted residents in Veneto and migrants from the region) and biology (how much imprinting from malaria has remained in the native population's genetic make-up).

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Development of damage suppression system using embedded SMA foil in CFRP laminates

NASA Astrophysics Data System (ADS)

Ogisu, Toshimichi; Nomura, Masato; Ando, Norio; Takaki, Junji; Kobayashi, Masakazu; Okabe, Tomonaga; Takeda, Nobuo

2001-07-01

Some recent studies have suggested possible applications of Shape Memory Alloy (SMA) for a smart health monitoring and suppression of damage growth. The authors have been conducting research and development studies on applications of embedded SMA foil actuators in CFRP laminates as the basic research for next generation aircrafts. First the effective surface treatment for improvement of bonding properties between SMA and CFRP was studied. It was certified that the anodic oxide treatment by 10% NaOH solution was the most effective treatment from the results of peel resistance test and shear strength test. Then, CFRP laminates with embedded SMA foils were successfully fabricated using this effective surface treatment. The damage behavior of quasi-isotropic CFRP laminates with embedded SMA foils was characterized in both quasi-static load-unload and fatigue tests. The relationship between crack density and applied strain was obtained. The recovery stress generated by embedded SMA foils could increase the onset strain of transverse cracking by 0.2%. The onset strain of delmination in CFRP laminates was also increased accordingly. The shear-lag analysis was also conducted to predict the damage evolution in CFRP laminates with embedded SMA foils. The adhesive layers on both sides of SMA foils were treated as shear elements. The theoretical analysis successfully predicted the experimental results.

Are Categorical Spatial Relations Encoded by Shifting Visual Attention between Objects?

PubMed Central

Uttal, David; Franconeri, Steven

2016-01-01

Perceiving not just values, but relations between values, is critical to human cognition. We tested the predictions of a proposed mechanism for processing categorical spatial relations between two objects—the shift account of relation processing—which states that relations such as ‘above’ or ‘below’ are extracted by shifting visual attention upward or downward in space. If so, then shifts of attention should improve the representation of spatial relations, compared to a control condition of identity memory. Participants viewed a pair of briefly flashed objects and were then tested on either the relative spatial relation or identity of one of those objects. Using eye tracking to reveal participants’ voluntary shifts of attention over time, we found that when initial fixation was on neither object, relational memory showed an absolute advantage for the object following an attention shift, while identity memory showed no advantage for either object. This result is consistent with the shift account of relation processing. When initial fixation began on one of the objects, identity memory strongly benefited this fixated object, while relational memory only showed a relative benefit for objects following an attention shift. This result is also consistent, although not as uniquely, with the shift account of relation processing. Taken together, we suggest that the attention shift account provides a mechanistic explanation for the overall results. This account can potentially serve as the common mechanism underlying both linguistic and perceptual representations of spatial relations. PMID:27695104

Are Categorical Spatial Relations Encoded by Shifting Visual Attention between Objects?

PubMed

Yuan, Lei; Uttal, David; Franconeri, Steven

2016-01-01

Perceiving not just values, but relations between values, is critical to human cognition. We tested the predictions of a proposed mechanism for processing categorical spatial relations between two objects-the shift account of relation processing-which states that relations such as 'above' or 'below' are extracted by shifting visual attention upward or downward in space. If so, then shifts of attention should improve the representation of spatial relations, compared to a control condition of identity memory. Participants viewed a pair of briefly flashed objects and were then tested on either the relative spatial relation or identity of one of those objects. Using eye tracking to reveal participants' voluntary shifts of attention over time, we found that when initial fixation was on neither object, relational memory showed an absolute advantage for the object following an attention shift, while identity memory showed no advantage for either object. This result is consistent with the shift account of relation processing. When initial fixation began on one of the objects, identity memory strongly benefited this fixated object, while relational memory only showed a relative benefit for objects following an attention shift. This result is also consistent, although not as uniquely, with the shift account of relation processing. Taken together, we suggest that the attention shift account provides a mechanistic explanation for the overall results. This account can potentially serve as the common mechanism underlying both linguistic and perceptual representations of spatial relations.

An Augmented Lagrangian Filter Method for Real-Time Embedded Optimization

DOE PAGES

Chiang, Nai -Yuan; Huang, Rui; Zavala, Victor M.

2017-04-17

We present a filter line-search algorithm for nonconvex continuous optimization that combines an augmented Lagrangian function and a constraint violation metric to accept and reject steps. The approach is motivated by real-time optimization applications that need to be executed on embedded computing platforms with limited memory and processor speeds. The proposed method enables primal–dual regularization of the linear algebra system that in turn permits the use of solution strategies with lower computing overheads. We prove that the proposed algorithm is globally convergent and we demonstrate the developments using a nonconvex real-time optimization application for a building heating, ventilation, and airmore » conditioning system. Our numerical tests are performed on a standard processor and on an embedded platform. Lastly, we demonstrate that the approach reduces solution times by a factor of over 1000.« less

Flight code validation simulator

NASA Astrophysics Data System (ADS)

Sims, Brent A.

1996-05-01

An End-To-End Simulation capability for software development and validation of missile flight software on the actual embedded computer has been developed utilizing a 486 PC, i860 DSP coprocessor, embedded flight computer and custom dual port memory interface hardware. This system allows real-time interrupt driven embedded flight software development and checkout. The flight software runs in a Sandia Digital Airborne Computer and reads and writes actual hardware sensor locations in which Inertial Measurement Unit data resides. The simulator provides six degree of freedom real-time dynamic simulation, accurate real-time discrete sensor data and acts on commands and discretes from the flight computer. This system was utilized in the development and validation of the successful premier flight of the Digital Miniature Attitude Reference System in January of 1995 at the White Sands Missile Range on a two stage attitude controlled sounding rocket.

An Augmented Lagrangian Filter Method for Real-Time Embedded Optimization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Nai -Yuan; Huang, Rui; Zavala, Victor M.

We present a filter line-search algorithm for nonconvex continuous optimization that combines an augmented Lagrangian function and a constraint violation metric to accept and reject steps. The approach is motivated by real-time optimization applications that need to be executed on embedded computing platforms with limited memory and processor speeds. The proposed method enables primal–dual regularization of the linear algebra system that in turn permits the use of solution strategies with lower computing overheads. We prove that the proposed algorithm is globally convergent and we demonstrate the developments using a nonconvex real-time optimization application for a building heating, ventilation, and airmore » conditioning system. Our numerical tests are performed on a standard processor and on an embedded platform. Lastly, we demonstrate that the approach reduces solution times by a factor of over 1000.« less

On the Suitability of Suffix Arrays for Lempel-Ziv Data Compression

NASA Astrophysics Data System (ADS)

Ferreira, Artur J.; Oliveira, Arlindo L.; Figueiredo, Mário A. T.

Lossless compression algorithms of the Lempel-Ziv (LZ) family are widely used nowadays. Regarding time and memory requirements, LZ encoding is much more demanding than decoding. In order to speed up the encoding process, efficient data structures, like suffix trees, have been used. In this paper, we explore the use of suffix arrays to hold the dictionary of the LZ encoder, and propose an algorithm to search over it. We show that the resulting encoder attains roughly the same compression ratios as those based on suffix trees. However, the amount of memory required by the suffix array is fixed, and much lower than the variable amount of memory used by encoders based on suffix trees (which depends on the text to encode). We conclude that suffix arrays, when compared to suffix trees in terms of the trade-off among time, memory, and compression ratio, may be preferable in scenarios (e.g., embedded systems) where memory is at a premium and high speed is not critical.

Emotion and false memory: The context-content paradox.

PubMed

Bookbinder, S H; Brainerd, C J

2016-12-01

False memories are influenced by a variety of factors, but emotion is a variable of special significance, for theoretical and practical reasons. Interestingly, emotion's effects on false memory depend on whether it is embedded in the content of to-be-remembered events or in our moods, where mood is an aspect of the context in which events are encoded. We sketch the theoretical basis for this content-context dissociation and then review accumulated evidence that content and context effects are indeed different. Paradoxically, we find that in experiments on spontaneous and implanted false memories, negatively valenced content foments distortion, but negatively valenced moods protect against it. In addition, correlational data show that enduring negative natural moods (e.g., depression) foment false memory. Current opponent-process models of false memory, such as fuzzy-trace theory, are able to explain the content-context dissociation: Variations in emotional content primarily affect memory for the gist of events, whereas variations in emotional context primarily affect memory for events' exact verbatim form. Important questions remain about how these effects are modulated by variations in memory tests and in arousal. Promising methods of tackling those questions are outlined, especially designs that separate the gist and verbatim influences of emotion. (PsycINFO Database Record (c) 2016 APA, all rights reserved).

The effect of memory and context changes on color matches to real objects.

PubMed

Allred, Sarah R; Olkkonen, Maria

2015-07-01

Real-world color identification tasks often require matching the color of objects between contexts and after a temporal delay, thus placing demands on both perceptual and memory processes. Although the mechanisms of matching colors between different contexts have been widely studied under the rubric of color constancy, little research has investigated the role of long-term memory in such tasks or how memory interacts with color constancy. To investigate this relationship, observers made color matches to real study objects that spanned color space, and we independently manipulated the illumination impinging on the objects, the surfaces in which objects were embedded, and the delay between seeing the study object and selecting its color match. Adding a 10-min delay increased both the bias and variability of color matches compared to a baseline condition. These memory errors were well accounted for by modeling memory as a noisy but unbiased version of perception constrained by the matching methods. Surprisingly, we did not observe significant increases in errors when illumination and surround changes were added to the 10-minute delay, although the context changes alone did elicit significant errors.

Evidence for spontaneous retrieval of suspended but not finished prospective memories.

PubMed

Scullin, Michael K; Einstein, Gilles O; McDaniel, Mark A

2009-06-01

McDaniel and Einstein (2007) argued that prospective memories can be retrieved through spontaneous retrieval processes stimulated by the presence of a target cue. To test this claim, we investigated whether presenting a prospective memory cue during a task that did not require an intention to be performed spontaneously triggered remembering of that intention. In two experiments, participants performed an image-rating task in which a prospective memory task (to press the "Q" key when a target word appeared) was embedded. Then, participants were told that their intention was finished or suspended. Finally, participants performed a lexical decision task in which each target (and a matched control) word appeared. RTs were slower to target words than to control words when the intention was suspended but not when it was finished. These results suggest that target cues associated with suspended intentions can spontaneously trigger remembering but that finished intentions are quickly deactivated.

Stressing the mind: the effect of cognitive load and articulatory suppression on attentional guidance from working memory.

PubMed

Soto, David; Humphreys, Glyn W

2008-07-01

Four experiments explored the effect of cognitive load on the time course of top-down guidance of attention from working memory (WM). Observers had to search for a target presented among several distractors, with the target and distractor stimuli embedded inside different objects. On half of the trials, one of the distractor objects was cued by a matching item held in WM. When a single item was maintained in memory, search performance was impaired relative to a neutral baseline, where the memory and search displays did not match. These effects of WM on subsequent search were reduced by including a verbal suppression task during the WM and search displays, and by varying the WM load. The degree of competition for resources in WM is a key factor in determining the time course and magnitude of the interaction between WM and visual selection.

Electrical reliability, multilevel data storage and mechanical stability of MoS2-PMMA nanocomposite-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Bhattacharjee, Snigdha; Sarkar, Pranab Kumar; Prajapat, Manoj; Roy, Asim

2017-07-01

Molybdenum disulfide (MoS2) is of great interest for its applicability in various optoelectronic devices. Here we report the resistive switching properties of polymethylmethacrylate embedding MoS2 nano-crystals. The devices are developed on an ITO-coated PET substrate with copper as the top electrode. Systematic evaluation of resistive switching parameters, on the basis of MoS2 content, suggests non-volatile memory characteristics. A decent ON/OFF ratio, high retention time and long endurance of 3  ×  103, 105 s and 105 cycles are respectively recorded in a device with 1 weight percent (wt%) of MoS2. The bending cyclic measurements confirm the flexibility of the memory devices with good electrical reliability as well as mechanical stability. In addition, multilevel storage has been demonstrated by controlling the current compliance and span of voltage sweeping in the memory device.

Ternary Polymeric Composites Exhibiting Bulk and Surface Quadruple-Shape Memory Properties.

PubMed

Buffington, Shelby Lois; Posnick, Benjamin M; Paul, Justine Elizabeth; Mather, Patrick T

2018-06-19

We report the design and characterization of a multiphase quadruple shape memory composite capable of switching between 4 programmed shapes, three temporary and one permanent. Our approach combined two previously reported fabrication methods by embedding an electrospun mat of PCL in a miscible blend of epoxy monomers and PMMA as a composite matrix. As epoxy polymerization occurred the matrix underwent phase separation between the epoxy and PMMA materials. This created a multiphase composite with PCL fibers and a two-phase matrix composed of phase-separated epoxy and PMMA. The resulting composite demonstrated three separate thermal transitions and amenability to mechanical programming of three separate temporary shapes in addition to one final, equilibrium shape. In addition, quadruple surface shape memory abilities are successfully demonstrated. The versatility of this approach offers a large degree of design flexibility for multi-shape memory materials. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

PubMed Central

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-01-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories. PMID:28513590

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

NASA Astrophysics Data System (ADS)

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-05-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories.

NASA's 3D Flight Computer for Space Applications

NASA Technical Reports Server (NTRS)

Alkalai, Leon

2000-01-01

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Measuring hot flash phenomenonology using ambulatory prospective digital diaries

PubMed Central

Fisher, William I.; Thurston, Rebecca C.

2016-01-01

Objective This study provides the description, protocol, and results from a novel prospective ambulatory digital hot flash phenomenon diary. Methods This study included 152 midlife women with daily hot flashes who completed an ambulatory electronic hot flash diary continuously for the waking hours of 3 consecutive days. In this diary, women recorded their hot flashes and accompanying characteristics and associations as the hot flashes occurred. Results Self-reported hot flash severity on the digital diaries indicated that the majority of hot flashes were rated as mild (41.3%) or moderate (43.7%). Severe (13.1%) and very severe (1.8%) hot flashes were less common. Hot flash bother ratings were rated as mild (43%), or moderate (33.5%), with fewer hot flashes reported bothersome (17.5%) or very bothersome (6%). The majority of hot flashes were reported as occurring on the on the face (78.9%), neck (74.7%), and chest (61.3%). Prickly skin was reported concurrently with 32% of hot flashes, 7% with anxiety and 5% with nausea. A novel finding, 38% of hot flashes were accompanied by a premonitory aura. Conclusion A prospective electronic digital hot flash diary allows for a more precise quantitation of hot flashes while overcoming many of the limitations of commonly employed retrospective questionnaires and paper diaries. Unique insights into the phenomenology, loci and associated characteristics of hot flashes were obtained using this device. The digital hot flash phenomenology diary is recommended for future ambulatory studies of hot flashes as a prospective measure of the hot flash experience. PMID:27404030

Measuring hot flash phenomenonology using ambulatory prospective digital diaries.

PubMed

Fisher, William I; Thurston, Rebecca C

2016-11-01

This study provides the description, protocol, and results from a novel prospective ambulatory digital hot flash phenomenon diary. This study included 152 midlife women with daily hot flashes who completed an ambulatory electronic hot flash diary continuously for the waking hours of three consecutive days. In this diary, women recorded their hot flashes and accompanying characteristics and associations as the hot flashes occurred. Self-reported hot flash severity on the digital diaries indicated that the majority of hot flashes were rated as mild (41.3%) or moderate (43.7%). Severe (13.1%) and very severe (1.8%) hot flashes were less common. Hot flash bother ratings were rated as mild (43%), or moderate (33.5%), with fewer hot flashes reported bothersome (17.5%) or very bothersome (6%). The majority of hot flashes were reported as occurring on the face (78.9%), neck (74.7%), and chest (61.3%). Of all reported hot flashes, 32% occurred concurrently with prickly skin, 7% with anxiety, and 5% with nausea. A novel finding from the study was that 38% of hot flashes were accompanied by a premonitory aura. A prospective electronic digital hot flash diary allows for a more precise quantitation of hot flashes while overcoming many of the limitations of commonly used retrospective questionnaires and paper diaries. Unique insights into the phenomenology, loci, and associated characteristics of hot flashes were obtained using this device. The digital hot flash phenomenology diary is recommended for future ambulatory studies of hot flashes as a prospective measure of the hot flash experience.

Individuals with Low Working Memory Spans Show Greater Interference from Irrelevant Information Because of Poor Source Monitoring, Not Greater Activation

PubMed Central

Lilienthal, Lindsey; Rose, Nathan S.; Tamez, Elaine; Myerson, Joel; Hale, Sandra

2014-01-01

Although individuals with high and low working memory (WM) span appear to differ in the extent to which irrelevant information interferes with their performance on WM tasks, the locus of this interference is not clear. The present study investigated whether, when performing a WM task, high- and low-span individuals differ in the activation of formerly relevant, but now irrelevant items, and/or in their ability to correctly identify such irrelevant items. This was done in two experiments, both of which used modified complex WM span tasks. In Experiment 1, the span task included an embedded lexical decision task designed to obtain an implicit measure of the activation of both currently and formerly relevant items. In Experiment 2, the span task included an embedded recognition judgment task designed to obtain an explicit measure of both item and source recognition ability. The results of these experiments indicate that low-span individuals do not hold irrelevant information in a more active state in memory than high-span individuals, but rather that low-span individuals are significantly poorer at identifying such information as irrelevant at the time of retrieval. These results suggest that differences in the ability to monitor the source of information, rather than differences in the activation of irrelevant information, are the more important determinant of performance on WM tasks. PMID:25921723

Method and system for training dynamic nonlinear adaptive filters which have embedded memory

NASA Technical Reports Server (NTRS)

Rabinowitz, Matthew (Inventor)

2002-01-01

Described herein is a method and system for training nonlinear adaptive filters (or neural networks) which have embedded memory. Such memory can arise in a multi-layer finite impulse response (FIR) architecture, or an infinite impulse response (IIR) architecture. We focus on filter architectures with separate linear dynamic components and static nonlinear components. Such filters can be structured so as to restrict their degrees of computational freedom based on a priori knowledge about the dynamic operation to be emulated. The method is detailed for an FIR architecture which consists of linear FIR filters together with nonlinear generalized single layer subnets. For the IIR case, we extend the methodology to a general nonlinear architecture which uses feedback. For these dynamic architectures, we describe how one can apply optimization techniques which make updates closer to the Newton direction than those of a steepest descent method, such as backpropagation. We detail a novel adaptive modified Gauss-Newton optimization technique, which uses an adaptive learning rate to determine both the magnitude and direction of update steps. For a wide range of adaptive filtering applications, the new training algorithm converges faster and to a smaller value of cost than both steepest-descent methods such as backpropagation-through-time, and standard quasi-Newton methods. We apply the algorithm to modeling the inverse of a nonlinear dynamic tracking system 5, as well as a nonlinear amplifier 6.

Weaknesses in Lexical-Semantic Knowledge Among College Students With Specific Learning Disabilities: Evidence From a Semantic Fluency Task

PubMed Central

McGregor, Karla K.; Oleson, Jacob

2017-01-01

Purpose The purpose of this study is to determine whether deficits in executive function and lexical-semantic memory compromise the linguistic performance of young adults with specific learning disabilities (LD) enrolled in postsecondary studies. Method One hundred eighty-five students with LD (n = 53) or normal language development (ND, n = 132) named items in the categories animals and food for 1 minute for each category and completed tests of lexical-semantic knowledge and executive control of memory. Groups were compared on total names, mean cluster size, frequency of embedded clusters, frequency of cluster switches, and change in fluency over time. Secondary analyses of variability within the LD group were also conducted. Results The LD group was less fluent than the ND group. Within the LD group, lexical-semantic knowledge predicted semantic fluency and cluster size; executive control of memory predicted semantic fluency and cluster switches. The LD group produced smaller clusters and fewer embedded clusters than the ND group. Groups did not differ in switching or change over time. Conclusions Deficits in the lexical-semantic system associated with LD may persist into young adulthood, even among those who have managed their disability well enough to attend college. Lexical-semantic deficits are associated with compromised semantic fluency, and the two problems are more likely among students with more severe disabilities. PMID:28267833

Formation of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} for the application of write-once-read-many-times memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Min-Lin; Wu, Yung-Hsien; Lin, Chia-Chun

2012-10-15

The structure of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} formed by sequential deposition of Al{sub 2}O{sub 3}/Si/Ge/Al{sub 2}O{sub 3} and a subsequent annealing was confirmed by transmission electron microscopy and energy dispersive spectroscopy (EDS), and its application for write-once-read-many-times (WORM) memory devices was explored in this study. By applying a -10 V pulse for 1 s, a large amount of holes injected from Si substrate are stored in the nanocrystals and consequently, the current at +1.5 V increases by a factor of 10{sup 4} as compared to that of the initial state. Even with a smaller -5 V pulsemore » for 1 {mu}s, a sufficiently large current ratio of 36 can still be obtained, verifying the low power operation. Since holes are stored in nanocrystals which are isolated from Si substrate by Al{sub 2}O{sub 3} with good integrity and correspond to a large valence band offset with respect to Al{sub 2}O{sub 3}, desirable read endurance up to 10{sup 5} cycles and excellent retention over 100 yr are achieved. Combining these promising characteristics, WORM memory devices are appropriate for high-performance archival storage applications.« less

Weaknesses in Lexical-Semantic Knowledge Among College Students With Specific Learning Disabilities: Evidence From a Semantic Fluency Task.

PubMed

Hall, Jessica; McGregor, Karla K; Oleson, Jacob

2017-03-01

The purpose of this study is to determine whether deficits in executive function and lexical-semantic memory compromise the linguistic performance of young adults with specific learning disabilities (LD) enrolled in postsecondary studies. One hundred eighty-five students with LD (n = 53) or normal language development (ND, n = 132) named items in the categories animals and food for 1 minute for each category and completed tests of lexical-semantic knowledge and executive control of memory. Groups were compared on total names, mean cluster size, frequency of embedded clusters, frequency of cluster switches, and change in fluency over time. Secondary analyses of variability within the LD group were also conducted. The LD group was less fluent than the ND group. Within the LD group, lexical-semantic knowledge predicted semantic fluency and cluster size; executive control of memory predicted semantic fluency and cluster switches. The LD group produced smaller clusters and fewer embedded clusters than the ND group. Groups did not differ in switching or change over time. Deficits in the lexical-semantic system associated with LD may persist into young adulthood, even among those who have managed their disability well enough to attend college. Lexical-semantic deficits are associated with compromised semantic fluency, and the two problems are more likely among students with more severe disabilities.

Processing and memory of information presented in narrative or expository texts.

PubMed

Wolfe, Michael B W; Woodwyk, Joshua M

2010-09-01

Previous research suggests that narrative and expository texts differ in the extent to which they prompt students to integrate to-be-learned content with relevant prior knowledge during comprehension. We expand on previous research by examining on-line processing and representation in memory of to-be-learned content that is embedded in narrative or expository texts. We are particularly interested in how differences in the use of relevant prior knowledge leads to differences in terms of levels of discourse representation (textbase vs. situation model). A total of 61 university undergraduates in Expt 1, and 160 in Expt 2. In Expt 1, subjects thought out loud while comprehending circulatory system content embedded in a narrative or expository text, followed by free recall of text content. In Expt 2, subjects read silently and completed a sentence recognition task to assess memory. In Expt 1, subjects made more associations to prior knowledge while reading the expository text, and recalled more content. Content recall was also correlated with amount of relevant prior knowledge for subjects who read the expository text but not the narrative text. In Expt 2, subjects reading the expository text (compared to the narrative text) had a weaker textbase representation of the to-be-learned content, but a marginally stronger situation model. Results suggest that in terms of to-be-learned content, expository texts trigger students to utilize relevant prior knowledge more than narrative texts.

Designing high-performance cost-efficient embedded SRAM in deep-submicron era

NASA Astrophysics Data System (ADS)

Kobozeva, Olga; Venkatraman, Ramnath; Castagnetti, Ruggero; Duan, Franklin; Kamath, Arvind; Ramesh, Shiva

2004-05-01

We have previously presented the smallest and fastest 6 Transistor (6T)-Static Random Access Memories (SRAM) bitcells for System-on-Chip (SoC) high-density (HD) memories in 0.18 μm and 0.13 μm technologies. Our 1.87 μm2 6TSRAM bitcell with cell current of 47 μA and industry lowest soft error rate (0.35 FIT/Kbit) is used to assemble memory blocks embedded into SoC designs in 0.13 μm process technology. Excellent performance is achieved at a low overall cost, as our bitcells are based on standard CMOS process and demonstrate high yields in manufacturing. This paper discusses our methodology of embedded SRAM bitcell design. The key aspects of our approach are: 1) judicious selection of tightest achievable yet manufacturable design rules to build the cell; 2) compatibility with standard Optical Proximity Correction (OPC) flow; 3) use of parametric testing and yield analysis to achieve excellent design robustness and manufacturability. A thorough understanding of process limitations, particularly those related to photolithography was critical to the successful design and manufacturing of our aggressive, yet robust SRAM bitcells. The patterning of critical layers, such as diffusion, poly gate, contact and metal 1 has profound implications on functionality, electrical performance and manufacturability of memories. We have conducted the development of SRAM bitcells using two approaches for OPC: a) "manual" OPC, wherein the bitcell layout of each of the critical layers is achieved using iterative improvement of layout & aerial image simulation and b) automated OPC-compatible design, wherein the drawn bitcell layout becomes a subject of a full chip OPC. While manual-OPC remains a popular option, automated OPC-compatible bitcell design is very attractive, as it does not require additional development costs to achieve fab-to-fab portability. In both cases we have obtained good results with respect to patterning of the critical layers, electrical performance of the bitcell and memory yields. A critical part of our memory technology development effort is the design of memory-specific test structures that are used for: a) verifying electrical characteristics of SRAM transistors and b) confirming the robustness of the design rules used within the SRAM cell. In addition to electrical test structures, we have a fully functional SRAM test chip called RAMPCM that is composed of sub-blocks each designated to evaluate the robustness of a specific critical design rule used within the bitcells. The results from the electrical testing and RAMPCM yield analysis are used to identify opportunities for improvements in the layout design. The paper will also suggest some techniques that can result in more design friendly OPC solutions. Our work indicates that future IC designs can benefit from an automated OPC tool that can intelligently handle layout modifications according to design priorities.

Ethernet-Enabled Power and Communication Module for Embedded Processors

NASA Technical Reports Server (NTRS)

Perotti, Jose; Oostdyk, Rebecca

2010-01-01

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.