Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide.

PubMed

Min Lee, Seung; Hwan Yum, Jung; Larsen, Eric S; Chul Lee, Woo; Keun Kim, Seong; Bielawski, Christopher W; Oh, Jungwoo

2017-10-16

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

Fabrication and design of vanadium oxide microbolometer

NASA Astrophysics Data System (ADS)

Abdel-Rahman, M.; Al-Khalli, N.; Zia, M. F.; Alduraibi, M.; Ilahi, B.; Awad, E.; Debbar, N.

2017-02-01

Vanadium oxide (VxOy) multilayer sandwich structures previously studied by our group were found to yield a sensitive thermometer thin film material suitable for microbolometer applications. In this work, we aim to estimate the performance of a proposed air-bridge microbolometer configuration based on VxOy multilayer sandwich structure thermometer thin films. For this purpose, a microbolometer was fabricated on silicon (Si) substrate covered with a silicon nitride (Si3N4) insulating layer using VxOy thermometer thin film material. The fabricated microbolometer was patterned using electron-beam lithography and liftoff techniques and it was characterized in terms of its voltage repsonsivity (Rv), signal to noise ratio (SNR), noise equivalent power (NEP) and detectivity D*. A model was then developed by the aid of numerical optical/thermal simulations and experimentally measured parameters to estimate the performance of the microbolometer when fabricated in an air-bridge configuration. The estimated D* was found to be 1.55×107 cm.√Hz/ W.

Buried oxide layer in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

NASA Astrophysics Data System (ADS)

Li, Yi-Shao; Wu, Chun-Yi; Chou, Chia-Hsin; Liao, Chan-Yu; Chuang, Kai-Chi; Luo, Jun-Dao; Li, Wei-Shuo; Cheng, Huang-Chung

2018-06-01

A tetraethyl-orthosilicate (TEOS) capping oxide was deposited by low-pressure chemical vapor deposition (LPCVD) on a 200-nm-thick amorphous Si (a-Si) film as a heat reservoir to improve the crystallinity and surface roughness of polycrystalline silicon (poly-Si) formed by continuous-wave laser crystallization (CLC). The effects of four thicknesses of the capping oxide layer to satisfy an antireflection condition, namely, 90, 270, 450, and 630 nm, were investigated. The largest poly-Si grain size of 2.5 × 20 µm2 could be achieved using a capping oxide layer with an optimal thickness of 450 nm. Moreover, poly-Si nanorod (NR) thin-film transistors (TFTs) fabricated using the aforementioned technique exhibited a superior electron field-effect mobility of 1093.3 cm2 V‑1 s‑1 and an on/off current ratio of 2.53 × 109.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Minahan, J. A.

1981-01-01

The fabrication of solar cells from several unconventional silicon materials is described, and cell performance measured and analyzed. Unconventional materials evaluated are edge defined film fed grown (EFG), heat exchanger method (HEM), dendritic web grown, and continuous CZ silicons. Resistivity, current voltage, and spectral sensitivity of the cells were measured. Current voltage was measured under AM0 and AM1 conditions. Maximum conversion efficiencies of cells fabricated from these and other unconventional silicons were compared and test results analyzed. The HEM and continuous CZ silicon were found to be superior to silicon materials considered previously.

Lithography-free fabrication of silicon nanowire and nanohole arrays by metal-assisted chemical etching

PubMed Central

2013-01-01

We demonstrated a novel, simple, and low-cost method to fabricate silicon nanowire (SiNW) arrays and silicon nanohole (SiNH) arrays based on thin silver (Ag) film dewetting process combined with metal-assisted chemical etching. Ag mesh with holes and semispherical Ag nanoparticles can be prepared by simple thermal annealing of Ag thin film on a silicon substrate. Both the diameter and the distribution of mesh holes as well as the nanoparticles can be manipulated by the film thickness and the annealing temperature. The silicon underneath Ag coverage was etched off with the catalysis of metal in an aqueous solution containing HF and an oxidant, which form silicon nanostructures (either SiNW or SiNH arrays). The morphologies of the corresponding etched SiNW and SiNH arrays matched well with that of Ag holes and nanoparticles. This novel method allows lithography-free fabrication of the SiNW and SiNH arrays with control of the size and distribution. PMID:23557325

Fabrication and characterization of a chemically oxidized-nanostructured porous silicon based biosensor implementing orienting protein A.

PubMed

Naveas, Nelson; Hernandez-Montelongo, Jacobo; Pulido, Ruth; Torres-Costa, Vicente; Villanueva-Guerrero, Raúl; Predestinación García Ruiz, Josefa; Manso-Silván, Miguel

2014-03-01

Nanostructured porous silicon (PSi) elicits as a very attractive material for future biosensing systems due to its high surface area, biocompatibility and well-established fabrication methods. In order to engineer its performance as a biosensor transducer platform, the density of immunoglobulins properly immobilized and oriented onto the surface needs to be optimized. In this work we fabricated and characterized a novel biosensing system focusing on the improvement of the biofunctionalization cascade. The system consists on a chemically oxidized PSi platform derivatized with 3-aminopropyltriethoxysilane (APTS) that is coupled to Staphylococcus protein A (SpA). The chemical oxidation has previously demonstrated to enhance the biofunctionalization process and here "by implementing SpA" a molecularly oriented immunosensor is achieved. The biosensor system is characterized in terms of its chemical composition, wettability and optical reflectance. Finally, this system is successfully exploited to develop a biosensor for detecting asymmetric dimethylarginine (ADMA), an endogenous molecule involved in cardiovascular diseases. Therefore, this work is relevant from the point of view of design and optimization of the biomolecular immobilization cascade on PSi surfaces with the added value of contribution to the development of new assays for detecting ADMA with a view on prevention of cardiovascular diseases. Copyright © 2013 Elsevier B.V. All rights reserved.

Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing

NASA Astrophysics Data System (ADS)

Yuan, Zhishan; Wang, Chengyong; Chen, Ke; Ni, Zhonghua; Chen, Yunfei

2017-08-01

In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 103 Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.

Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing.

PubMed

Yuan, Zhishan; Wang, Chengyong; Chen, Ke; Ni, Zhonghua; Chen, Yunfei

2017-08-10

In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H 2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO 2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 10 3  Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

NASA Technical Reports Server (NTRS)

Tu, Juliana; Smith, Rosemary L.

1995-01-01

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Micromachining of silicon carbide on silicon fabricated by low-pressure chemical vapour deposition

NASA Astrophysics Data System (ADS)

Behrens, Ingo; Peiner, Erwin; Bakin, Andrey S.; Schlachetzki, Andreas

2002-07-01

We describe the fabrication of silicon carbide layers for micromechanical applications using low-pressure metal-organic chemical vapour deposition at temperatures below 1000 °C. The layers can be structured by lift-off using silicon dioxide as a sacrificial layer. A large selectivity with respect to silicon can be exploited for bulk micromachining. Thin membranes are fabricated which exhibit high mechanical quality, as necessary for applications in harsh environments.

Fabrication of Highly Ordered Anodic Aluminium Oxide Templates on Silicon Substrates

DTIC Science & Technology

2007-01-01

highly ordered anodic aluminium oxide ( AAO ) templates of unprecedented pore uniformity directly on Si, enabled by new advances on two fronts – direct...field emitter, sensors, oscillators and photodetectors. 15. SUBJECT TERMS Anodic aluminum oxide , template-assisted nanofabrication, carbon nanotube...Fabrication of the aligned and patterned carbon nanotube field emitters using the anodic aluminum oxide nano-template on a Si wafer’, Synth. Met

Method to fabricate silicon chromatographic column comprising fluid ports

DOEpatents

Manginell, Ronald P.; Frye-Mason, Gregory C.; Heller, Edwin J.; Adkins, Douglas R.

2004-03-02

A new method for fabricating a silicon chromatographic column comprising through-substrate fluid ports has been developed. This new method enables the fabrication of multi-layer interconnected stacks of silicon chromatographic columns.

Thin silicon-solar cell fabrication

NASA Technical Reports Server (NTRS)

Lindmayer, J.

1979-01-01

Flexible silicon slices of uniform thicknesses are fabricated by etching in sodium hydroxide solution. Maintaining uniform thickness across slices during process(fabrication) is important for cell strength and resistance to damage in handling. Slices formed by procedure have reproducible surface with fine orange peel texture, and are far superior to slices prepared by other methods.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Femtosecond laser fabricating black silicon in alkaline solution

NASA Astrophysics Data System (ADS)

Meng, Jiao; Song, Haiying; Li, Xiaoli; Liu, Shibing

2015-03-01

An efficient approach for enhancing the surface antireflection is proposed, in which a black silicon is fabricated by a femtosecond laser in alkaline solution. In the experiment, 2 wt% NaOH solution is formulated at room temperature (22 ± 1 °C). Then, a polished silicon is scanned via femtosecond laser irradiation in 2 wt% NaOH solution. Jungle-like microstructures on the black silicon surface are characterized using an atomic force microscopy. The reflectance of the black silicon is measured at the wavelengths ranging from 400 to 750 nm. Compared to the polished silicon, the black silicon can significantly suppress the optical reflection throughout the visible region (<5 %). Meanwhile, we also investigated the factors of the black silicon, including the femtosecond laser pulse energy and the scanning speed. This method is simple and effective to acquire the black silicon, which probably has a large advantage in fast and cost-effective black silicon fabrication.

Nanopatterning of Crystalline Silicon Using Anodized Aluminum Oxide Templates for Photovoltaics

NASA Astrophysics Data System (ADS)

Chao, Tsu-An

A novel thin film anodized aluminum oxide templating process was developed and applied to make nanopatterns on crystalline silicon to enhance the optical properties of silicon. The thin film anodized aluminum oxide was created to improve the conventional thick aluminum templating method with the aim for potential large scale fabrication. A unique two-step anodizing method was introduced to create high quality nanopatterns and it was demonstrated that this process is superior over the original one-step approach. Optical characterization of the nanopatterned silicon showed up to 10% reduction in reflection in the short wavelength range. Scanning electron microscopy was also used to analyze the nanopatterned surface structure and it was found that interpore spacing and pore density can be tuned by changing the anodizing potential.

Effect of fabrication parameters on morphological and optical properties of highly doped p-porous silicon

NASA Astrophysics Data System (ADS)

Zare, Maryam; Shokrollahi, Abbas; Seraji, Faramarz E.

2011-09-01

Porous silicon (PS) layers were fabricated by anodization of low resistive (highly doped) p-type silicon in HF/ethanol solution, by varying current density, etching time and HF concentration. Atomic force microscopy (AFM) and field emission scanning electron microscope (FESEM) analyses were used to investigate the physical properties and reflection spectrum was used to investigate the optical behavior of PS layers in different fabrication conditions. Vertically aligned mesoporous morphology is observed in fabricated films and with HF concentration higher than 20%. The dependence of porosity, layer thickness and rms roughness of the PS layer on current density, etching time and composition of electrolyte is also observed in obtained results. Correlation between reflectivity and fabrication parameters was also explored. Thermal oxidation was performed on some mesoporous layers that resulted in changes of surface roughness, mean height and reflectivity of the layers.

Silicon heterojunction solar cells with novel fluorinated n-type nanocrystalline silicon oxide emitters on p-type crystalline silicon

NASA Astrophysics Data System (ADS)

Dhar, Sukanta; Mandal, Sourav; Das, Gourab; Mukhopadhyay, Sumita; Pratim Ray, Partha; Banerjee, Chandan; Barua, Asok Kumar

2015-08-01

A novel fluorinated phosphorus doped silicon oxide based nanocrystalline material have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) Czochralski (CZ) wafers. The n-type nc-SiO:F:H material were deposited by radio frequency plasma enhanced chemical vapor deposition. Deposited films were characterized in detail by using atomic force microscopy (AFM), high resolution transmission electron microscopy (HRTEM), Raman, fourier transform infrared spectroscopy (FTIR) and optoelectronics properties have been studied using temperature dependent conductivity measurement, Ellipsometry, UV-vis spectrum analysis etc. It is observed that the cell fabricated with fluorinated silicon oxide emitter showing higher initial efficiency (η = 15.64%, Jsc = 32.10 mA/cm2, Voc = 0.630 V, FF = 0.77) for 1 cm2 cell area compare to conventional n-a-Si:H emitter (14.73%) on flat c-Si wafer. These results indicate that n type nc-SiO:F:H material is a promising candidate for heterojunction solar cell on p-type crystalline wafers. The high Jsc value is associated with excellent quantum efficiencies at short wavelengths (<500 nm).

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

FABRICATION OF A RETINAL PROSTHETIC TEST DEVICE USING ELECTRODEPOSITED SILICON OVER POLYPYRROLE PATTERNED WITH SU-8 PHOTORESIST

PubMed Central

Miller, Eric; Ellis, Daniel; Charles, Duran; McKenzie, Jason

2016-01-01

A materials fabrication study of a photodiode array for possible application of retina prosthesis was undertaken. A test device was fabricated using a glassy carbon electrode patterned with SU-8 photoresist. In the openings, p-type polypyrrole was first electrodeposited using 1-butyl-1-methylpyridinium bis(trifluoromethylsulfonyl)imide ionic liquid. The polypyrrole was self-doped with imide ion at ~1.5 mole %, was verified as p-type, and had a resistivity of ~20 Ωcm. N-type Silicon was then electrodeposited over this layer using silicon tetrachloride / phosphorus trichloride in acetonitrile and passivated in a second electrodeposition using trimethylchlorosilane. Electron microscopy revealed the successful electrodeposition of silicon over patterned polypyrrole. Rudimentary photodiode behavior was observed. The passivation improved but did not completely protect the electrodeposited silicon from oxidation by air. PMID:27616940

Tailored porous silicon microparticles: fabrication and properties

PubMed Central

Chiappini, Ciro; Tasciotti, Ennio; Fakhoury, Jean R.; Fine, Daniel; Pullan, Lee; Wang, Young-Chung; Fu, Lianfeng

2010-01-01

The use of mesoporous silicon particles for drug delivery has been widely explored thanks to their biodegradability and biocompatibility. The ability to tailor the physicochemical properties of porous silicon at the micro and nano scale confers versatility to this material. We present a method for the fabrication of highly reproducible, monodisperse mesoporous silicon particles with controlled physical characteristics through electrochemical etch of patterned silicon trenches. We tailored particle size in the micrometer range and pore size in the nanometer range, shape from tubular to discoidal to hemispherical, and porosity from 46% to over 80%. In addition, we correlated the properties of the porous matrix with the loading of model nanoparticles (Q-dots) and observed their three-dimensional arrangement within the matrix by transmission electron microscopy tomography. The methods developed in this study provide effective means to fabricate mesoporous silicon particles according to the principles of rational design for therapeutic vectors and to characterize the distribution of nanoparticles within the porous matrix PMID:20162656

Photoluminescence of amorphous and crystalline silicon nanoclusters in silicon nitride and oxide superlattices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shuleiko, D. V., E-mail: shuleyko.dmitriy@physics.msu.ru; Zabotnov, S. V.; Zhigunov, D. M.

2017-02-15

The photoluminescence properties of silicon nitride and oxide superlattices fabricated by plasmaenhanced chemical vapor deposition are studied. In the structures annealed at a temperature of 1150°C, photoluminescence peaks at about 1.45 eV are recorded. The peaks are defined by exciton recombination in silicon nanocrystals formed upon annealing. Along with the 1.45-eV peaks, a number of peaks defined by recombination at defects at the interface between the nanocrystals and silicon-nitride matrix are detected. The structures annealed at 900°C exhibit a number of photoluminescence peaks in the range 1.3–2.0 eV. These peaks are defined by both the recombination at defects and excitonmore » recombination in amorphous silicon nanoclusters formed at an annealing temperature of 900°C. The observed features of all of the photoluminescence spectra are confirmed by the nature of the photoluminescence kinetics.« less

Oxidation Protection of Porous Reaction-Bonded Silicon Nitride

NASA Technical Reports Server (NTRS)

Fox, D. S.

1994-01-01

Oxidation kinetics of both as-fabricated and coated reaction-bonded silicon nitride (RBSN) were studied at 900 and 1000 C with thermogravimetry. Uncoated RBSN exhibited internal oxidation and parabolic kinetics. An amorphous Si-C-O coating provided the greatest degree of protection to oxygen, with a small linear weight loss observed. Linear weight gains were measured on samples with an amorphous Si-N-C coating. Chemically vapor deposited (CVD) Si3N4 coated RBSN exhibited parabolic kinetics, and the coating cracked severely. A continuous-SiC-fiber-reinforced RBSN composite was also coated with the Si-C-O material, but no substantial oxidation protection was observed.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Silicon oxidation in fluoride solutions

NASA Technical Reports Server (NTRS)

Sancier, K. M.; Kapur, V.

1980-01-01

Silicon is produced in a NaF, Na2SiF6, and Na matrix when SiF4 is reduced by metallic sodium. Hydrogen is evolved during acid leaching to separate the silicon from the accompanying reaction products, NaF and Na2SiF6. The hydrogen evolution reaction was studied under conditions simulating leaching conditions by making suspensions of the dry silicon powder in aqueous fluoride solutions. The mechanism for the hydrogen evolution is discussed in terms of spontaneous oxidation of silicon resulting from the cooperative effects of (1) elemental sodium in the silicon that reacts with water to remove a protective silica layer, leaving clean reactive silicon, and (2) fluoride in solution that complexes with the oxidized silicon in solution and retards formation of a protective hydrous oxide gel.

Novel fabrication of silicon carbide based ceramics for nuclear applications

NASA Astrophysics Data System (ADS)

Singh, Abhishek Kumar

Advances in nuclear reactor technology and the use of gas-cooled fast reactors require the development of new materials that can operate at the higher temperatures expected in these systems. These materials include refractory alloys based on Nb, Zr, Ta, Mo, W, and Re; ceramics and composites such as SiC--SiCf; carbon--carbon composites; and advanced coatings. Besides the ability to handle higher expected temperatures, effective heat transfer between reactor components is necessary for improved efficiency. Improving thermal conductivity of the fuel can lower the center-line temperature and, thereby, enhance power production capabilities and reduce the risk of premature fuel pellet failure. Crystalline silicon carbide has superior characteristics as a structural material from the viewpoint of its thermal and mechanical properties, thermal shock resistance, chemical stability, and low radioactivation. Therefore, there have been many efforts to develop SiC based composites in various forms for use in advanced energy systems. In recent years, with the development of high yield preceramic precursors, the polymer infiltration and pyrolysis (PIP) method has aroused interest for the fabrication of ceramic based materials, for various applications ranging from disc brakes to nuclear reactor fuels. The pyrolysis of preceramic polymers allow new types of ceramic materials to be processed at relatively low temperatures. The raw materials are element-organic polymers whose composition and architecture can be tailored and varied. The primary focus of this study is to use a pyrolysis based process to fabricate a host of novel silicon carbide-metal carbide or oxide composites, and to synthesize new materials based on mixed-metal silicocarbides that cannot be processed using conventional techniques. Allylhydridopolycarbosilane (AHPCS), which is an organometal polymer, was used as the precursor for silicon carbide. Inert gas pyrolysis of AHPCS produces near-stoichiometric amorphous

Method for fabricating pixelated silicon device cells

DOEpatents

Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose Luis; Nelson, Jeffrey S.; Anderson, Benjamin John

2015-08-18

A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps.

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

NASA Astrophysics Data System (ADS)

Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Fabrication of silicon-based shape memory alloy micro-actuators

NASA Technical Reports Server (NTRS)

Johnson, A. David; Busch, John D.; Ray, Curtis A.; Sloan, Charles L.

1992-01-01

Thin film shape memory alloy has been integrated with silicon in a new actuation mechanism for microelectromechanical systems. This paper compares nickel-titanium film with other actuators, describes recent results of chemical milling processes developed to fabricate shape memory alloy microactuators in silicon, and describes simple actuation mechanisms which have been fabricated and tested.

Silicon photonics and challenges for fabrication

NASA Astrophysics Data System (ADS)

Feilchenfeld, N. B.; Nummy, K.; Barwicz, T.; Gill, D.; Kiewra, E.; Leidy, R.; Orcutt, J. S.; Rosenberg, J.; Stricker, A. D.; Whiting, C.; Ayala, J.; Cucci, B.; Dang, D.; Doan, T.; Ghosal, M.; Khater, M.; McLean, K.; Porth, B.; Sowinski, Z.; Willets, C.; Xiong, C.; Yu, C.; Yum, S.; Giewont, K.; Green, W. M. J.

2017-03-01

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

Aminosilane functionalizations of mesoporous oxidized silicon for oligonucleotide synthesis and detection

PubMed Central

De Stefano, Luca; Oliviero, Giorgia; Amato, Jussara; Borbone, Nicola; Piccialli, Gennaro; Mayol, Luciano; Rendina, Ivo; Terracciano, Monica; Rea, Ilaria

2013-01-01

Direct solid phase synthesis of peptides and oligonucleotides (ONs) requires high chemical stability of the support material. In this work, we have investigated the passivation ability of porous oxidized silicon multilayered structures by two aminosilane compounds, 3-aminopropyltriethoxysilane and 3-aminopropyldimethylethoxysilane (APDMES), for optical label-free ON biosensor fabrication. We have also studied by spectroscopic reflectometry the hybridization between a 13 bases ON, directly grown on the aminosilane modified porous oxidized silicon by in situ synthesis, and its complementary sequence. Even if the results show that both devices are stable to the chemicals (carbonate/methanol) used, the porous silica structure passivated by APDMES reveals higher functionalization degree due to less steric hindrance of pores. PMID:23536541

Fabrication and stabilization of silicon-based photonic crystals with tuned morphology for multi-band optical filtering

NASA Astrophysics Data System (ADS)

Salem, Mohamed Shaker; Abdelaleem, Asmaa Mohamed; El-Gamal, Abear Abdullah; Amin, Mohamed

2017-01-01

One-dimensional silicon-based photonic crystals are formed by the electrochemical anodization of silicon substrates in hydrofluoric acid-based solution using an appropriate current density profile. In order to create a multi-band optical filter, two fabrication approaches are compared and discussed. The first approach utilizes a current profile composed of a linear combination of sinusoidal current waveforms having different frequencies. The individual frequency of the waveform maps to a characteristic stop band in the reflectance spectrum. The stopbands of the optical filter created by the second approach, on the other hand, are controlled by stacking multiple porous silicon rugate multilayers having different fabrication conditions. The morphology of the resulting optical filters is tuned by controlling the electrolyte composition and the type of the silicon substrate. The reduction of sidelobes arising from the interference in the multilayers is observed by applying an index matching current profile to the anodizing current waveform. In order to stabilize the resulting optical filters against natural oxidation, atomic layer deposition of silicon dioxide on the pore wall is employed.

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

PubMed Central

Rossi, Alessandro; Tanttu, Tuomo; Hudson, Fay E.; Sun, Yuxin; Möttönen, Mikko; Dzurak, Andrew S.

2015-01-01

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization. PMID:26067215

Fabrication of silicon-based template-assisted nanoelectrode arrays and ohmic contact properties investigation.

PubMed

Bai, Anqi; Cheng, Buwen; Wang, Xiaofeng; Xue, Chunlai; Zuo, Yuhua; Wang, Qiming

2010-11-01

A convenient fabrication technology for large-area, highly-ordered nanoelectrode arrays on silicon substrate has been described here, using porous anodic alumina (PAA) as a template. The ultrathin PAA membranes were anodic oxidized utilizing a two-step anodization method, from Al film evaporated on substrate. The purposes for the use of two-step anodization were, first, improving the regularity of the porous structures, and second reducing the thickness of the membranes to 100-200 nm we desired. Then the nanoelectrode arrays were obtained by electroless depositing Ni-W alloy into the through pores of PAA membranes, making the alloy isolated by the insulating pore walls and contacting with the silicon substrates at the bottoms of pores. The Ni-W alloy was also electroless deposited at the back surface of silicon to form back electrode. Then ohmic contact properties between silicon and Ni-W alloy were investigated after rapid thermal annealing. Scanning electron microscopy (SEM) observations showed the structure characteristics, and the influence factors of fabrication effect were discussed. The current-voltage (I-V) curves revealed the contact properties. After annealing in N2 at 700 degrees C, good linear property was shown with contact resistance of 33 omega, which confirmed ohmic contacts between silicon and electrodes. These results presented significant application potential of this technology in nanosize current-injection devices in optoelectronics, microelectronics and bio-medical fields.

Optimization of contaminated oxide inversion layer solar cell. [considering silicon oxide coating

NASA Technical Reports Server (NTRS)

Call, R. L.

1976-01-01

Contaminated oxide cells have been fabricated with efficiencies of 8.6% with values of I sub sc = 120 ma, V sub oc = .54 volts, and curve factor of .73. Attempts to optimize the fabrication step to yield a higher output have not been successful. The fundamental limitation is the inadequate antireflection coating afforded by the silicon dioxide coating used to hold the contaminating ions. Coatings of SiO, therefore, were used to obtain a good antireflection coating, but the thinness of the coatings prevented a large concentration of the contaminating ions, and the cells was weak. Data of the best cell were .52 volts V sub oc, 110 ma I sub sc, .66 CFF and 6.7% efficiency.

Inversion layer solar cell fabrication and evaluation. [etching on silicon films

NASA Technical Reports Server (NTRS)

Call, R. L.

1974-01-01

Inversion layer solar cells were fabricated by etching through the diffused layer on p-type silicon wafers in a comb-like contact pattern. The charge separation comes from an induced p-n junction at the surface. The inverted surface is caused by a layer of transparent material applied to the surface that either contains free positive ions or that creates donor states at the interface. Cells are increased from 3 ma I sub sc to 100 ma by application of sodium silicate. The action is unstable, however, and decays. Non-mesa contaminated oxide cells were fabricated with short circuit currents of over 100 ma measured in the sun. Cells of this type have demonstrated stability.

Low-loss silicon-on-insulator shallow-ridge TE and TM waveguides formed using thermal oxidation.

PubMed

Pafchek, R; Tummidi, R; Li, J; Webster, M A; Chen, E; Koch, T L

2009-02-10

A thermal oxidation fabrication technique is employed to form low-loss high-index-contrast silicon shallow-ridge waveguides in silicon-on-insulator (SOI) with maximally tight vertical confinement. Drop-port responses from weakly coupled ring resonators demonstrate propagation losses below 0.36 dB/cm for TE modes. This technique is also combined with "magic width" designs mitigating severe lateral radiation leakage for TM modes to achieve propagation loss values of 0.94 dB/cm. We discuss the fabrication process utilized to form these low-loss waveguides and implications for sensor devices in particular.

Fabrication of highly selective tungsten oxide ammonia sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llobet, E.; Molas, G.; Molinas, P.

Tungsten oxide is shown to be a very promising material for the fabrication of highly selective ammonia sensors. Films of WO{sub 3} were deposited onto a silicon substrate by means of the drop-coating method. Then, the films were annealed in dry air at two different temperatures (300 and 400 C). X-ray photoelectron spectroscopy was used to investigate the composition of the films. Tungsten appeared both in WO{sub 2} and WO{sub 3} oxidation states, but the second state was clearly dominant. Scanning electron microscopy results showed that the oxide was amorphous or nanocrystalline. The WO{sub 3}-based devices were sensitive to ammoniamore » vapors when operated between 250 and 350 C. The optimal operating temperature for the highest sensitivity to ammonia was 300 C. Furthermore, when the devices were operated at 300 C, their sensitivity to other reducing species such as ethanol, methane, toluene, and water vapor was significantly lower, and this resulted in a high selectivity to ammonia. A model for the sensing mechanisms of the fabricated sensors is proposed.« less

Method of forming buried oxide layers in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Design, fabrication and characterization of a poly-silicon PN junction

NASA Astrophysics Data System (ADS)

Tower, Jason D.

This thesis details the design, fabrication, and characterization of a PN junction formed from p-type mono-crystalline silicon and n-type poly-crystalline silicon. The primary product of this project was a library of standard operating procedures (SOPs) for the fabrication of such devices, laying the foundations for future work and the development of a class in fabrication processes. The fabricated PN junction was characterized; in particular its current-voltage relationship was measured and fit to models. This characterization was to determine whether or not the fabrication process could produce working PN junctions with acceptable operational parameters.

Study of properties of modified silicones at solid-liquid interface: fabric-silicone interactions.

PubMed

Purohit, P; Somasundaran, P; Kulkarni, R

2006-06-15

Silicones are special reagents that impart desired surface properties such as softness, bounciness and antiwrinkle properties to fabrics and related materials. Although these finishing processes have been practiced routinely, very little is known about the mechanisms involved in modification so that they could be improved. The current study was undertaken to develop basic understanding of the mechanisms responsible for surface modification of fibers using silicones. PDMS based amino silicone emulsions, quaternized to various degrees using dimethyl sulphate, were used in the present study. The electrokinetic properties of the modified silicones were studied as a function of pH. It was expected that the silicone emulsions would show a steady positive zeta potential throughout the pH range due to the quaternization by dimethyl sulphate. Surprisingly, a sudden drop in the zeta potential was observed around pH 8 with the samples turning hazy in the pH range of 8-10. Turbidimetric studies also showed a sudden increase in the turbidity in the pH range 8-10 where commercial processes also encounter problems. It was concluded that the emulsions were destabilized at pH 8-10 thus rendering them ineffective for surface treatment. In order to identify reason for the improvement in fabric properties, fiber structure was monitored using atomic force microscopy. It was observed that the treated fibers were far smoother, relaxed and uniform as compared to the untreated fibers. Thus the morphology of the fabric is modified in a specific way by treatment with specialty silicones.

Fabrication of optical filters using multilayered porous silicon

NASA Astrophysics Data System (ADS)

Gaber, Noha; Khalil, Diaa; Shaarawi, Amr

2011-02-01

In this work we describe a method for fabricating optical filters using multilayered porous silicon 1D photonic structure. An electrochemical cell is constructed to control the porosity of variable layers in p-type Si wafers. Porous silicon multilayered structures are formed of λ/4 (or multiples) thin films that construct optical interference filters. By changing the anodizing current density of the cell during fabrication, different porosities can be obtained as the optical refractive index is a direct function of the layer porosity. To determine the morphology, the wavelength dependent refractive index n and absorption coefficient α, first, porous silicon free standing mono-layers have been fabricated at different conditions and characterized in the near infrared region (from 1000 to 2500nm). Large difference in refractive index (between 1.6 and 2.6) is obtained. Subsequently, multilayer structures have been fabricated and tested. Their spectral response has been measured and it shows good agreement with numerical simulations. A technique based on inserting etching breaks is adopted to ensure the depth homogeneity. The effect of differing etching/break times on the reproducibility of the filters is studied.

Selective doping of silicon nanowires by means of electron beam stimulated oxide etching.

PubMed

Pennelli, G; Totaro, M; Piotto, M

2012-02-08

Direct patterning of silicon dioxide by means of electron beam stimulated etching is shown, and a full characterization of exposure dose is presented. For its high dose, this technique is unsuitable for large areas but can be usefully employed like a precision scalpel for removing silicon dioxide by well-localized points. In this work, this technique is applied to the definition of windows through the oxide surrounding top down fabricated n-doped silicon nanowires. These windows will be employed for a selective doping of the nanowire by boron diffusion. In this way, pn junctions can be fabricated in well-localized points in the longitudinal direction of the nanowire, and an electrical contact to the different junctions can be provided. Electrical I-V characteristics of a nanowire with pn longitudinal junctions are reported and discussed. © 2012 American Chemical Society

Supersoft lithography: Candy-based fabrication of soft silicone microstructures

PubMed Central

Moraes, Christopher; Labuz, Joseph M.; Shao, Yue; Fu, Jianping; Takayama, Shuichi

2015-01-01

We designed a fabrication technique able to replicate microstructures in soft silicone materials (E < 1 kPa). Sugar-based ‘hard candy’ recipes from the confectionery industry were modified to be compatible with silicone processing conditions, and used as templates for replica molding. Microstructures fabricated in soft silicones can then be easily released by dissolving the template in water. We anticipate that this technique will be of particular importance in replicating physiologically soft, microstructured environments for cell culture, and demonstrate a first application in which intrinsically soft microstructures are used to measure forces generated by fibroblast-laden contractile tissues. PMID:26245893

Supersoft lithography: candy-based fabrication of soft silicone microstructures.

PubMed

Moraes, Christopher; Labuz, Joseph M; Shao, Yue; Fu, Jianping; Takayama, Shuichi

2015-01-01

We designed a fabrication technique able to replicate microstructures in soft silicone materials (E < 1 kPa). Sugar-based 'hard candy' recipes from the confectionery industry were modified to be compatible with silicone processing conditions, and used as templates for replica molding. Microstructures fabricated in soft silicones can then be easily released by dissolving the template in water. We anticipate that this technique will be of particular importance in replicating physiologically soft, microstructured environments for cell culture, and demonstrate a first application in which intrinsically soft microstructures are used to measure forces generated by fibroblast-laden contractile tissues.

Template-free fabrication of silicon micropillar/nanowire composite structure by one-step etching

PubMed Central

2012-01-01

A template-free fabrication method for silicon nanostructures, such as silicon micropillar (MP)/nanowire (NW) composite structure is presented. Utilizing an improved metal-assisted electroless etching (MAEE) of silicon in KMnO4/AgNO3/HF solution and silicon composite nanostructure of the long MPs erected in the short NWs arrays were generated on the silicon substrate. The morphology evolution of the MP/NW composite nanostructure and the role of self-growing K2SiF6 particles as the templates during the MAEE process were investigated in detail. Meanwhile, a fabrication mechanism based on the etching of silver nanoparticles (catalyzed) and the masking of K2SiF6 particles is proposed, which gives guidance for fabricating different silicon nanostructures, such as NW and MP arrays. This one-step method provides a simple and cost-effective way to fabricate silicon nanostructures. PMID:23043719

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Rapid fabrication of a silicon modification layer on silicon carbide substrate.

PubMed

Bai, Yang; Li, Longxiang; Xue, Donglin; Zhang, Xuejun

2016-08-01

We develop a kind of magnetorheological (MR) polishing fluid for the fabrication of a silicon modification layer on a silicon carbide substrate based on chemical theory and actual polishing requirements. The effect of abrasive concentration in MR polishing fluid on material removal rate and removal function shape is investigated. We conclude that material removal rate will increase and tends to peak value as the abrasive concentration increases to 0.3 vol. %, and the removal function profile will become steep, which is a disadvantage to surface frequency error removal at the same time. The removal function stability is also studied and the results show that the prepared MR polishing fluid can satisfy actual fabrication requirements. An aspheric reflective mirror of silicon carbide modified by silicon is well polished by combining magnetorheological finishing (MRF) using two types of MR polishing fluid and computer controlled optical surfacing (CCOS) processes. The surface accuracy root mean square (RMS) is improved from 0.087λ(λ=632.8  nm) initially to 0.020λ(λ=632.8  nm) in 5.5 h total and the tool marks resulting from MRF are negligible. The PSD analysis results also shows that the final surface is uniformly polished.

Heavily Boron-Doped Silicon Layer for the Fabrication of Nanoscale Thermoelectric Devices

PubMed Central

Liu, Yang; Deng, Lingxiao; Zhang, Mingliang; Zhang, Shuyuan; Ma, Jing; Song, Peishuai; Liu, Qing; Ji, An; Yang, Fuhua; Wang, Xiaodong

2018-01-01

Heavily boron-doped silicon layers and boron etch-stop techniques have been widely used in the fabrication of microelectromechanical systems (MEMS). This paper provides an introduction to the fabrication process of nanoscale silicon thermoelectric devices. Low-dimensional structures such as silicon nanowire (SiNW) have been considered as a promising alternative for thermoelectric applications in order to achieve a higher thermoelectric figure of merit (ZT) than bulk silicon. Here, heavily boron-doped silicon layers and boron etch-stop processes for the fabrication of suspended SiNWs will be discussed in detail, including boron diffusion, electron beam lithography, inductively coupled plasma (ICP) etching and tetramethylammonium hydroxide (TMAH) etch-stop processes. A 7 μm long nanowire structure with a height of 280 nm and a width of 55 nm was achieved, indicating that the proposed technique is useful for nanoscale fabrication. Furthermore, a SiNW thermoelectric device has also been demonstrated, and its performance shows an obvious reduction in thermal conductivity. PMID:29385759

Fabrication of wear-resistant silicon microprobe tips for high-speed surface roughness scanning devices

NASA Astrophysics Data System (ADS)

Wasisto, Hutomo Suryo; Yu, Feng; Doering, Lutz; Völlmeke, Stefan; Brand, Uwe; Bakin, Andrey; Waag, Andreas; Peiner, Erwin

2015-05-01

Silicon microprobe tips are fabricated and integrated with piezoresistive cantilever sensors for high-speed surface roughness scanning systems. The fabrication steps of the high-aspect-ratio silicon microprobe tips were started with photolithography and wet etching of potassium hydroxide (KOH) resulting in crystal-dependent micropyramids. Subsequently, thin conformal wear-resistant layer coating of aluminum oxide (Al2O3) was demonstrated on the backside of the piezoresistive cantilever free end using atomic layer deposition (ALD) method in a binary reaction sequence with a low thermal process and precursors of trimethyl aluminum and water. The deposited Al2O3 layer had a thickness of 14 nm. The captured atomic force microscopy (AFM) image exhibits a root mean square deviation of 0.65 nm confirming the deposited Al2O3 surface quality. Furthermore, vacuum-evaporated 30-nm/200-nm-thick Au/Cr layers were patterned by lift-off and served as an etch mask for Al2O3 wet etching and in ICP cryogenic dry etching. By using SF6/O2 plasma during inductively coupled plasma (ICP) cryogenic dry etching, micropillar tips were obtained. From the preliminary friction and wear data, the developed silicon cantilever sensor has been successfully used in 100 fast measurements of 5- mm-long standard artifact surface with a speed of 15 mm/s and forces of 60-100 μN. Moreover, the results yielded by the fabricated silicon cantilever sensor are in very good agreement with those of calibrated profilometer. These tactile sensors are targeted for use in high-aspect-ratio microform metrology.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Silicon-based photonic crystals fabricated using proton beam writing combined with electrochemical etching method

PubMed Central

2012-01-01

A method for fabrication of three-dimensional (3D) silicon nanostructures based on selective formation of porous silicon using ion beam irradiation of bulk p-type silicon followed by electrochemical etching is shown. It opens a route towards the fabrication of two-dimensional (2D) and 3D silicon-based photonic crystals with high flexibility and industrial compatibility. In this work, we present the fabrication of 2D photonic lattice and photonic slab structures and propose a process for the fabrication of 3D woodpile photonic crystals based on this approach. Simulated results of photonic band structures for the fabricated 2D photonic crystals show the presence of TE or TM gap in mid-infrared range. PMID:22824206

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Passivation mechanism in silicon heterojunction solar cells with intrinsic hydrogenated amorphous silicon oxide layers

NASA Astrophysics Data System (ADS)

Deligiannis, Dimitrios; van Vliet, Jeroen; Vasudevan, Ravi; van Swaaij, René A. C. M. M.; Zeman, Miro

2017-02-01

In this work, we use intrinsic hydrogenated amorphous silicon oxide layers (a-SiOx:H) with varying oxygen content (cO) but similar hydrogen content to passivate the crystalline silicon wafers. Using our deposition conditions, we obtain an effective lifetime (τeff) above 5 ms for cO ≤ 6 at. % for passivation layers with a thickness of 36 ± 2 nm. We subsequently reduce the thickness of the layers using an accurate wet etching method to ˜7 nm and deposit p- and n-type doped layers fabricating a device structure. After the deposition of the doped layers, τeff appears to be predominantly determined by the doped layers themselves and is less dependent on the cO of the a-SiOx:H layers. The results suggest that τeff is determined by the field-effect rather than by chemical passivation.

Physical Properties of Polyester Fabrics Treated with Nano, Micro and Macro Emulsion Silicones

NASA Astrophysics Data System (ADS)

Parvinzadeh, M.; Hajiraissi, R.

2007-08-01

The processing of textile to achieve a particular handle is one of the most important aspects of finishing technology. Fabrics softeners are liquid composition added to washing machines during the rinse cycle to make clothes feel better to the touch. The first fabric softeners were developed by the textile industry during the early twentieth century. In this research polyester fabrics were treated with nano, micro and macro emulsion silicone softeners. Some of the physical properties of the treated fabric samples are discussed. The drapeability of treated samples was improved after treatment with nano silicone softeners. The colorimetric measurement of softener-treated fabrics is evaluated with a reflectance spectrophotometer. Moisture regain of treated samples is increased due to coating of silicone softeners. There is some increase in the weight of softener-treated samples. Samples treated with nano emulsion silicones gave better results compared to micro- and macro-emulsion treated ones.

Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo

2013-12-02

A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobilitymore » of 609 cm{sup 2} V{sup −1} s{sup −1}.« less

Fabrication, strength and oxidation of molybdenum-silicon-boron alloys from reaction synthesis

NASA Astrophysics Data System (ADS)

Middlemas, Michael Robert

Mo-Si-B alloys are a leading candidate for the next generation of jet turbine engine blades and have the potential to raise the operating temperatures by 300-400°C, which would dramatically increase power and efficiency. The alloys of interest are a three-phase mixture of the molybdenum solid solution (Moss) and two intermetallic phases, Mo3Si (A15) and Mo5SiB2 (T2). A novel powder metallurgical method was developed which uses the reaction of molybdenum, silicon nitride (Si3N4) and boron nitride (BN) powders to synthesize a fine dispersion of the intermetallic phases in a Moss matrix. The covalent nitrides are stable in oxidizing environments up to 1000ºC, allowing for fine particle processing without the formation of silicon and boron oxides. The process developed uses standard powder processing techniques to create Mo-Si-B alloys in a less complex and expensive manner than previously demonstrated. The formation of the intermetallic phases was examined by thermo-gravimetric analysis and x-ray diffraction. The start of the reactions to form the T2 and A15 phases were observed at 1140°C and 1193°C and the reactions have been demonstrated to be complete in as little as two hours at 1300°C. This powder metallurgy approach yields a fine dispersion of intermetallics in the Moss matrix, with average grain sizes of 2-4mum. Densities up to 95% of theoretical were attained from pressureless sintering at 1600°C and full theoretical density was achieved by hot-isostatic pressing (HIP). Low temperature sintering and HIPing was attempted to limit grain growth and to reduce the equilibrium silicon concentration in the Moss matrix. Sintering and HIPing at 1300°C reduced the grain sizes of all three phases by over a factor of two. Powder metallurgy provides an opportunity for microstructure control through changes in raw materials and processing parameters. Microstructure examination by electron back-scatter diffraction (EBSD) imaging was used to precisely define the

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method of making silicon carbide-silicon composite having improved oxidation resistance

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2002-01-01

A Silicon carbide-silicon matrix composite having improved oxidation resistance at high temperatures in dry or water-containing environments is provided. A method is given for sealing matrix cracks in situ in melt infiltrated silicon carbide-silicon matrix composites. The composite cracks are sealed by the addition of various additives, such as boron compounds, into the melt infiltrated silicon carbide-silicon matrix.

Silicon Web Process Development. [for solar cell fabrication

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Seidensticker, R. G.; Hopkins, R. H.; Mchugh, J. P.; Hill, F. E.; Heimlich, M. E.; Driggers, J. M.

1979-01-01

Silicon dendritic web, ribbon form of silicon and capable of fabrication into solar cells with greater than 15% AMl conversion efficiency, was produced from the melt without die shaping. Improvements were made both in the width of the web ribbons grown and in the techniques to replenish the liquid silicon as it is transformed to web. Through means of improved thermal shielding stress was reduced sufficiently so that web crystals nearly 4.5 cm wide were grown. The development of two subsystems, a silicon feeder and a melt level sensor, necessary to achieve an operational melt replenishment system, is described. A gas flow management technique is discussed and a laser reflection method to sense and control the melt level as silicon is replenished is examined.

Development of a high efficiency thin silicon solar cell. [fabrication and stability tests

NASA Technical Reports Server (NTRS)

Lindmayer, J.

1976-01-01

One hundred thin (120 microns to 260 microns) silicon-aluminum solar cells were fabricated and tested. Silicon slices were prepared, into which an aluminum alloy was evaporated over a range of temperatures and times. Antireflection coatings of tantalum oxide were applied to the cells. Reflectance of the silicon-aluminum interfaces was correlated to alloy temperature (graphs are shown). Optical measurements of the rear surface-internal reflectance of the cells were performed using a Beckman spectrophotometer. An improved gridline pattern was evaluated and stability tests (thermal cycling tests) were performed. Results show that: (1) a high-index, high-transmittance antireflection coating was obtained; (2) the improved metallization of the cells gave a 60 percent rear surface-internal reflectance, and the cells displayed excellent fill factors and blue response of the spectrum; (3) an improved gridline pattern (5 micron linewidths compared to 13 micron linewidths) resulted in a 1.3 percent improvement in short circuit currents; and (4) the stability tests showed no change in cell properties.

Low loss poly-silicon for high performance capacitive silicon modulators.

PubMed

Douix, Maurin; Baudot, Charles; Marris-Morini, Delphine; Valéry, Alexia; Fowler, Daivid; Acosta-Alba, Pablo; Kerdilès, Sébastien; Euvrard, Catherine; Blanc, Romuald; Beneyton, Rémi; Souhaité, Aurélie; Crémer, Sébastien; Vulliet, Nathalie; Vivien, Laurent; Boeuf, Frédéric

2018-03-05

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

Oxidation resistance of silicon ceramics

NASA Technical Reports Server (NTRS)

Yasutoshi, H.; Hirota, K.

1984-01-01

Oxidation resistance, and examples of oxidation of SiC, Si3N4 and sialon are reviewed. A description is given of the oxidation mechanism, including the oxidation product, oxidation reaction and the bubble size. The oxidation reactions are represented graphically. An assessment is made of the oxidation process, and an oxidation example of silicon ceramics is given.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

CMUT Fabrication Based On A Thick Buried Oxide Layer.

PubMed

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O; Khuri-Yakub, Butrus T

2010-10-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required - in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

NASA Astrophysics Data System (ADS)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Modelling and fabrication of high-efficiency silicon solar cells

NASA Astrophysics Data System (ADS)

Rohatgi, A.; Smith, A. W.; Salami, J.

1991-10-01

This report covers the research conducted on modelling and development of high efficiency silicon solar cells during the period May 1989 to August 1990. First, considerable effort was devoted toward developing a ray tracing program for the photovoltaic community to quantify and optimize surface texturing for solar cells. Second, attempts were made to develop a hydrodynamic model for device simulation. Such a model is somewhat slower than drift-diffusion type models like PC-1D, but it can account for more physical phenomena in the device, such as hot carrier effects, temperature gradients, thermal diffusion, and lattice heat flow. In addition, Fermi-Dirac statistics have been incorporated into the model to deal with heavy doping effects more accurately. The third and final component of the research includes development of silicon cell fabrication capabilities and fabrication of high efficiency silicon cells.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Thin-Film Transistors Fabricated Using Sputter Deposition of Zinc Oxide

NASA Astrophysics Data System (ADS)

Xiao, Nan

2013-01-01

Development of thin film transistors (TFTs) with conventional channel layer materials, such as amorphous silicon (a-Si) and polysilicon (poly-Si), has been extensively investigated. A-Si TFT currently serves the large flat panel industry; however advanced display products are demanding better TFT performance because of the associated low electron mobility of a-Si. This has motivated interest in semiconducting metal oxides, such as Zinc Oxide (ZnO), for TFT backplanes. This work involves the fabrication and characterization of TFTs using ZnO deposited by sputtering. An overview of the process details and results from recently fabricated TFTs following a full-factorial designed experiment will be presented. Material characterization and analysis of electrical results will be described. The investigated process variables were the gate dielectric and ZnO sputtering process parameters including power density and oxygen partial pressure. Electrical results showed clear differences in treatment combinations, with certain I-V characteristics demonstrating superior performance to preliminary work. A study of device stability will also be discussed.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors

NASA Astrophysics Data System (ADS)

Krishnan, Anand Thiruvengadathan

2000-10-01

The proliferation of devices with built-in displays, such as personal digital assistants and cellular phones has created a demand for rugged light-weight displays. Polymeric substrates could be suited for these applications, and they offer the possibility of flexible displays also. However, driver circuitry needs to be integrated in the display if the cost is to be reduced. Low temperature (<350°C) polycrystalline silicon (poly-Si) thin film transistors, if developed, offer driver circuitry integration during pixel transistor fabrication on top of flexible substrates. This thesis addresses several issues related to the fabrication of thin film transistors at low temperatures on glass substrates. A high-density plasma (electron cyclotron resonance (ECR)) based approach was adopted for deposition of thin films. A process for deposition of n-type doped silicon (n-type doped Si) at T < 350°C and having resistivity <1 ohm/cm has been developed. Intrinsic poly-Si was deposited under different conditions of microwave power, RF bias and deposition times. The properties of n-type doped Si and intrinsic poly-Si were correlated with the structure and the deposition conditions. A novel TFT structure has been proposed and implemented in this work. This top gate TFT structure uses n-type doped Si and utilizes only two masks and one alignment step. There are no critical etch steps and good interface quality could be obtained even without post-processing hydrogenation as the poly-Si surface was not exposed to air before deposition of the gate dielectric. TFTs using this top gate structure were fabricated with no process step exceeding 340°C electrode temperature (surface temperature <300°C). These TFTs show ON/OFF ratios in excess of 105. Their sub-threshold swing is ˜0.5 V/decade and mobility is 1--10 cm2/V-s. Several TFTs were also fabricated using alternative dielectrics such as oxide deposited from tetramethyl silane in an RFPECVD chamber and silicon nitride deposited in

Silicon carbide-silicon composite having improved oxidation resistance and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

1999-01-01

A Silicon carbide-silicon matrix composite having improved oxidation resistance at high temperatures in dry or water-containing environments is provided. A method is given for sealing matrix cracks in situ in melt infiltrated silicon carbide-silicon matrix composites. The composite cracks are sealed by the addition of various additives, such as boron compounds, into the melt infiltrated silicon carbide-silicon matrix.

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Effect of nano-oxide concentration on the mechanical properties of a maxillofacial silicone elastomer.

PubMed

Han, Ying; Kiat-amnuay, Sudarat; Powers, John M; Zhao, Yimin

2008-12-01

Contemporary silicone-based elastomeric prostheses tend to degrade over time because of the effect of mechanical loading. Little has been reported on how the mechanical properties of a maxillofacial prosthetic elastomer may be affected by the addition of nanosized oxide particles used as an opacifier. The purpose of this study was to evaluate the effect of different concentrations of nanosized oxides of various composition on the mechanical properties of a commercially available silicone elastomer. Nanosized oxides (Ti, Zn, or Ce) were added in various concentrations (0.5%, 1.0%, 1.5%, 2.0%, 2.5%, or 3.0% by weight) to a commercial silicone elastomer (A-2186), commonly used for fabricating extraoral maxillofacial prostheses. Silicone elastomer A-2186 without nanosized oxides served as a control group. Specimens (n=5) were polymerized according to manufacturer's recommendations and tested for tensile strength (ASTM D412) and tear strength (ASTM D624), and percent elongation in a universal testing machine. Uniformity of particle dispersion within the processed elastomer was assessed using scanning electron microscopic imaging. For each property, a 2-way ANOVA was performed evaluating the effect of oxide type and strength, and Fisher's PLSD test was used for pairwise comparisons (alpha=.05). SEM examination indicated that all 3 nanosized oxides distribute evenly throughout the silicone specimens, except for the 3.0% group, which are partly agglomerated. The 2.0% and 2.5% groups of all nanosized oxides demonstrated significantly higher tensile and tear strengths and percent elongation (P<.001) than the control group. CeO(2) had significantly lower tensile strength than TiO2 and ZnO (P<.05). The ZnO group had significantly higher tear strength than TiO(2) and CeO(2) (P <.05). Most of specimens became somewhat harder when compared with the control group. CeO(2) group had significantly higher Shore A hardness than TiO(2) and ZnO (P<.001). There was no significant

Low Cost Fabrication of Silicon Carbide Based Ceramics and Fiber Reinforced Composites

NASA Technical Reports Server (NTRS)

Singh, M.; Levine, S. R.

1995-01-01

A low cost processing technique called reaction forming for the fabrication of near-net and complex shaped components of silicon carbide based ceramics and composites is presented. This process consists of the production of a microporous carbon preform and subsequent infiltration with liquid silicon or silicon-refractory metal alloys. The microporous preforms are made by the pyrolysis of a polymerized resin mixture with very good control of pore volume and pore size thereby yielding materials with tailorable microstructure and composition. Mechanical properties (elastic modulus, flexural strength, and fracture toughness) of reaction-formed silicon carbide ceramics are presented. This processing approach is suitable for various kinds of reinforcements such as whiskers, particulates, fibers (tows, weaves, and filaments), and 3-D architectures. This approach has also been used to fabricate continuous silicon carbide fiber reinforced ceramic composites (CFCC's) with silicon carbide based matrices. Strong and tough composites with tailorable matrix microstructure and composition have been obtained. Microstructure and thermomechanical properties of a silicon carbide (SCS-6) fiber reinforced reaction-formed silicon carbide matrix composites are discussed.

Evaluation of Porous Silicon Oxide on Silicon Microcantilevers for Sensitive Detection of Gaseous HF.

PubMed

Wallace, Ryan A; Sepaniak, Michael J; Lavrik, Nickolay V; Datskos, Panos G

2017-06-06

Sensitive detection of harmful chemicals in industrial applications is pertinent to safety. In this work, we demonstrate the use of a sensitive silicon microcantilever (MC) system with a porous silicon oxide layer deposited on the active side of the MCs that have been mechanically manipulated to increase sensitivity. Included is the evaluation of porous silicon oxide present on different geometries of MCs and exposed to varying concentrations of hydrogen fluoride in humid air. Profilometry and the signal generated by the stress-induced porous silicon oxide (PSO) coating and bending of the MC were used as methods of evaluation.

Evaluation of Porous Silicon Oxide on Silicon Microcantilevers for Sensitive Detection of Gaseous HF

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wallace, Ryan A.; Sepaniak, Michael J.; Lavrik, Nickolay V.

Sensitive detection of harmful chemicals in industrial applications is pertinent to safety. In this paper, we demonstrate the use of a sensitive silicon microcantilever (MC) system with a porous silicon oxide layer deposited on the active side of the MCs that have been mechanically manipulated to increase sensitivity. Included is the evaluation of porous silicon oxide present on different geometries of MCs and exposed to varying concentrations of hydrogen fluoride in humid air. Finally, profilometry and the signal generated by the stress-induced porous silicon oxide (PSO) coating and bending of the MC were used as methods of evaluation.

Evaluation of Porous Silicon Oxide on Silicon Microcantilevers for Sensitive Detection of Gaseous HF

DOE PAGES

Wallace, Ryan A.; Sepaniak, Michael J.; Lavrik, Nickolay V.; ...

2017-05-10

Sensitive detection of harmful chemicals in industrial applications is pertinent to safety. In this paper, we demonstrate the use of a sensitive silicon microcantilever (MC) system with a porous silicon oxide layer deposited on the active side of the MCs that have been mechanically manipulated to increase sensitivity. Included is the evaluation of porous silicon oxide present on different geometries of MCs and exposed to varying concentrations of hydrogen fluoride in humid air. Finally, profilometry and the signal generated by the stress-induced porous silicon oxide (PSO) coating and bending of the MC were used as methods of evaluation.

Method for fabricating silicon cells

DOEpatents

Ruby, Douglas S.; Basore, Paul A.; Schubert, W. Kent

1998-08-11

A process for making high-efficiency solar cells. This is accomplished by forming a diffusion junction and a passivating oxide layer in a single high-temperature process step. The invention includes the class of solar cells made using this process, including high-efficiency solar cells made using Czochralski-grown silicon.

Fabrication and Modification of Nanoporous Silicon Particles

NASA Technical Reports Server (NTRS)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Fabrication and secondary-phase crystallization of rare-earth disilicate-silicon nitride ceramics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cinibulk, M.K.; Thomas, G.; Johnson, S.M.

1992-08-01

In this paper, the fabrication and intergranular-phase devitrification of silicon nitride densified with rare-earth (RE) oxide additives is investigated. The additions of the oxides of Sm, Gd, Dy, Er, and Yb, having high melting points and behaving similarly to Y[sub 2]O[sub 3], were compositionally controlled to tailor a microstructure with a crystalline secondary phase of RE[sub 2]Si[sub 2]O[sub 7]. The lanthanide oxides were found to be ass effective as Y[sub 2]O[sub 3] in densifying Si[sub 3]N[sub 4], resulting in identical microstructures and densities of 98-99% of theoretical density. The crystallization behavior of all six disilicates was similar, characterized by amore » limited nucleation and rapid growth mechanism resulting in large single crystals. Complete crystallization of the intergranular phase was obtained with the exception of a thin residual amorphous film which was observed at interfaces and believed to be rich in impurities, the cause of incomplete devitrification.« less

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

A practical guide for the fabrication of microfluidic devices using glass and silicon

PubMed Central

Iliescu, Ciprian; Taylor, Hayden; Avram, Marioara; Miao, Jianmin; Franssila, Sami

2012-01-01

This paper describes the main protocols that are used for fabricating microfluidic devices from glass and silicon. Methods for micropatterning glass and silicon are surveyed, and their limitations are discussed. Bonding methods that can be used for joining these materials are summarized and key process parameters are indicated. The paper also outlines techniques for forming electrical connections between microfluidic devices and external circuits. A framework is proposed for the synthesis of a complete glass/silicon device fabrication flow. PMID:22662101

Fabrication of multi-functional silicon surface by direct laser writing

NASA Astrophysics Data System (ADS)

Verma, Ashwani Kumar; Soni, R. K.

2018-05-01

We present a simple, quick and one-step methodology based on nano-second laser direct writing for the fabrication of micro-nanostructures on silicon surface. The fabricated surfaces suppress the optical reflection by multiple reflection due to light trapping effect to a much lower value than polished silicon surface. These textured surfaces offer high enhancement ability after gold nanoparticle deposition and then explored for Surface Enhanced Raman Scattering (SERS) for specific molecular detection. The effect of laser scanning line interval on optical reflection and SERS signal enhancement ability was also investigated. Our results indicate that low optical reflection substrates exhibit uniform SERS enhancement with enhancement factor of the order of 106. Furthermore, this methodology provide an alternative approach for cost-effective large area fabrication with good control over feature size.

Silica substrate or portion formed from oxidation of monocrystalline silicon

DOEpatents

Matzke, Carolyn M.; Rieger, Dennis J.; Ellis, Robert V.

2003-07-15

A method is disclosed for forming an inclusion-free silica substrate using a monocrystalline silicon substrate as the starting material and oxidizing the silicon substrate to convert it entirely to silica. The oxidation process is performed from both major surfaces of the silicon substrate using a conventional high-pressure oxidation system. The resulting product is an amorphous silica substrate which is expected to have superior etching characteristics for microfabrication than conventional fused silica substrates. The present invention can also be used to convert only a portion of a monocrystalline silicon substrate to silica by masking the silicon substrate and locally thinning a portion the silicon substrate prior to converting the silicon portion entirely to silica. In this case, the silica formed by oxidizing the thinned portion of the silicon substrate can be used, for example, as a window to provide optical access through the silicon substrate.

Composite silicon nanostructure arrays fabricated on optical fibre by chemical etching of multicrystal silicon film.

PubMed

Zuo, Zewen; Zhu, Kai; Ning, Lixin; Cui, Guanglei; Qu, Jun; Huang, Wanxia; Shi, Yi; Liu, Hong

2015-04-17

Integrating nanostructures onto optical fibers presents a promising strategy for developing new-fashioned devices and extending the scope of nanodevices' applications. Here we report the first fabrication of a composite silicon nanostructure on an optical fiber. Through direct chemical etching using an H2O2/HF solution, multicrystal silicon films with columnar microstructures are etched into a vertically aligned, inverted-cone-like nanorod array embedded in a nanocone array. A faster dissolution rate of the silicon at the void-rich boundary regions between the columns is found to be responsible for the separation of the columns, and thus the formation of the nanostructure array. The morphology of the nanorods primarily depends on the microstructure of the columns in the film. Through controlling the microstructure of the as-grown film and the etching parameters, the structural control of the nanostructure is promising. This fabrication method can be extended to a larger length scale, and it even allows roll-to-roll processing.

Method for fabricating silicon cells

DOEpatents

Ruby, D.S.; Basore, P.A.; Schubert, W.K.

1998-08-11

A process is described for making high-efficiency solar cells. This is accomplished by forming a diffusion junction and a passivating oxide layer in a single high-temperature process step. The invention includes the class of solar cells made using this process, including high-efficiency solar cells made using Czochralski-grown silicon. 9 figs.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Method of fabricating silicon carbide coatings on graphite surfaces

DOEpatents

Varacalle, D.J. Jr.; Herman, H.; Burchell, T.D.

1994-07-26

The vacuum plasma spray process produces well-bonded, dense, stress-free coatings for a variety of materials on a wide range of substrates. The process is used in many industries to provide for the excellent wear, corrosion resistance, and high temperature behavior of the fabricated coatings. In this application, silicon metal is deposited on graphite. This invention discloses the optimum processing parameters for as-sprayed coating qualities. The method also discloses the effect of thermal cycling on silicon samples in an inert helium atmosphere at about 1,600 C which transforms the coating to silicon carbide. 3 figs.

Method of fabricating silicon carbide coatings on graphite surfaces

DOEpatents

Varacalle, Jr., Dominic J.; Herman, Herbert; Burchell, Timothy D.

1994-01-01

The vacuum plasma spray process produces well-bonded, dense, stress-free coatings for a variety of materials on a wide range of substrates. The process is used in many industries to provide for the excellent wear, corrosion resistance, and high temperature behavior of the fabricated coatings. In this application, silicon metal is deposited on graphite. This invention discloses the optimum processing parameters for as-sprayed coating qualities. The method also discloses the effect of thermal cycling on silicon samples in an inert helium atmosphere at about 1600.degree.C. which transforms the coating to silicon carbide.

Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO2/Si interfaces with low defect densities

NASA Astrophysics Data System (ADS)

Stegemann, Bert; Gad, Karim M.; Balamou, Patrice; Sixtensson, Daniel; Vössing, Daniel; Kasemann, Martin; Angermann, Heike

2017-02-01

Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO2/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO2/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO2/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO2/Si interfaces have been shown to generate less interface defect states.

Demonstration of the feasibility of automated silicon solar cell fabrication

NASA Technical Reports Server (NTRS)

Taylor, W. E.; Schwartz, F. M.

1975-01-01

A study effort was undertaken to determine the process, steps and design requirements of an automated silicon solar cell production facility. Identification of the key process steps was made and a laboratory model was conceptually designed to demonstrate the feasibility of automating the silicon solar cell fabrication process. A detailed laboratory model was designed to demonstrate those functions most critical to the question of solar cell fabrication process automating feasibility. The study and conceptual design have established the technical feasibility of automating the solar cell manufacturing process to produce low cost solar cells with improved performance. Estimates predict an automated process throughput of 21,973 kilograms of silicon a year on a three shift 49-week basis, producing 4,747,000 hexagonal cells (38mm/side), a total of 3,373 kilowatts at an estimated manufacturing cost of $0.866 per cell or $1.22 per watt.

Fabrication of optical ring resonators in silicon on insulator

NASA Astrophysics Data System (ADS)

Headley, William R.; Reed, Graham T.; Liu, Ansheng; Cohen, Oded; Hak, D.; Paniccia, Mario J.; Howe, Simon; Huille, Inga

2004-07-01

In an effort to determine low-cost alternatives for components currently used in DWDM, optical ring resonators are currently being investigated. The well-known microfabrication techniques of silicon, coupled with the low propagation loss of single crystal silicon, make SOI an attractive material. Laterally coupled racetrack resonators utilising rib waveguides have been fabricated and preliminary results are discussed. An extinction ratio of 15.9 dB and a finesse of 11 have been measured.

The fabrication of nitrogen detector porous silicon nanostructures

NASA Astrophysics Data System (ADS)

Husairi, F. S.; Othman, N.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

2018-05-01

In this study the porous silicon nanostructure used as a the nitrogen detector was fabricated by using anodization method because of simple and easy to handle. This method using 20 mA/ cm2 of current density and the etching time is from 10 - 40 minutes. The properties of the porous silicon nanostructure analyzed using I-V testing (electrical properties) and photoluminescence spectroscopy. From the I-V testing, sample PsiE40 where the sensitivity is 25.4% is a sensitivity of PSiE40 at 10 seconds exposure time.

Oxidation of silicon with a 5 eV O(-) beam

NASA Technical Reports Server (NTRS)

Hecht, M. H.; Orient, O. J.; Chutjian, A.; Vasquez, R. P.

1989-01-01

A silicon wafer has been oxidized at room temperature in vacuum using a pure, ground-state beam of O(-) ions. The beam was of sufficiently low energy that no displacement damage or implantation was energetically possible. The resulting SiO2 films were analyzed with X-ray photoelectron spectroscopy. A logarithmic dependence of oxide thickness on dose was observed, with an extrapolated oxidation efficiency of unity for the clean silicon surface. A distinct initial oxidation phase was observed, with an anomalously high level of silicon suboxides. In addition, the valence-band offset between the silicon and the oxide was unusually small, suggesting a large interfacial dipole.

Oxide driven strength evolution of silicon surfaces

DOE PAGES

Grutzik, Scott J.; Milosevic, Erik; Boyce, Brad L.; ...

2015-11-19

Previous experiments have shown a link between oxidation and strength changes in single crystal silicon nanostructures but provided no clues as to the mechanisms leading to this relationship. Using atomic force microscope-based fracture strength experiments, molecular dynamics modeling, and measurement of oxide development with angle resolved x-ray spectroscopy we study the evolution of strength of silicon (111) surfaces as they oxidize and with fully developed oxide layers. We find that strength drops with partial oxidation but recovers when a fully developed oxide is formed and that surfaces intentionally oxidized from the start maintain their high initial strengths. MD simulations showmore » that strength decreases with the height of atomic layer steps on the surface. These results are corroborated by a completely separate line of testing using micro-scale, polysilicon devices, and the slack chain method in which strength recovers over a long period of exposure to the atmosphere. Lastly, combining our results with insights from prior experiments we conclude that previously described strength decrease is a result of oxidation induced roughening of an initially flat silicon (1 1 1) surface and that this effect is transient, a result consistent with the observation that surfaces flatten upon full oxidation.« less

Atomic force microscopy nanomanipulation of silicon nanocrystals for nanodevice fabrication

NASA Astrophysics Data System (ADS)

Decossas, Sébastien; Mazen, Frédéric; Baron, Thierry; Brémond, Georges; Souifi, Abdelkader

2003-12-01

An atomic force microscopy (AFM) tip has been used to manipulate silicon nanocrystals deposited by low-pressure chemical vapour deposition on thermally oxidized p-type Si wafer. Three nanomanipulation methods are presented. The first one catches a nanocrystal with the AFM tip and deposits it elsewhere: the tip is used as an electrostatic 'nano-crane'. The second one simultaneously manipulates a set of nanocrystals in order to draw well-defined unidimensional lines: the tip is used as a 'nano-broom'. The third one manipulates individual nanocrystals with a precision of about 10 nm using both oscillating and contact AFM modes. Switching from strong interaction forces (chemical) to weak ones (van der Waals, electrostatic or capillarity) is the basis of these manipulation methods. We have applied the second method to connect two electrodes drawn by e-beam and lift-off with a 70 nm long silicon nanocrystal chain. Current versus voltage characterization of the nanofabricated device shows that the increase in nanocrystal density gives rise to conduction between the connected electrodes. Resonant tunnelling effects resulting from Si nanocrystal (nc-Si) multiple tunnel junctions have been observed at 300 K. We also show that offset charges directly influence the position of the resonant tunnelling peaks. Finally, the possibility of manipulating nc-Si with a diameter of around 5 nm is shown to be a promising way to fabricate single electron devices operating at room temperature and fully compatible with silicon technology.

3D-fabrication of tunable and high-density arrays of crystalline silicon nanostructures

NASA Astrophysics Data System (ADS)

Wilbers, J. G. E.; Berenschot, J. W.; Tiggelaar, R. M.; Dogan, T.; Sugimura, K.; van der Wiel, W. G.; Gardeniers, J. G. E.; Tas, N. R.

2018-04-01

In this report, a procedure for the 3D-nanofabrication of ordered, high-density arrays of crystalline silicon nanostructures is described. Two nanolithography methods were utilized for the fabrication of the nanostructure array, viz. displacement Talbot lithography (DTL) and edge lithography (EL). DTL is employed to perform two (orthogonal) resist-patterning steps to pattern a thin Si3N4 layer. The resulting patterned double layer serves as an etch mask for all further etching steps for the fabrication of ordered arrays of silicon nanostructures. The arrays are made by means of anisotropic wet etching of silicon in combination with an isotropic retraction etch step of the etch mask, i.e. EL. The procedure enables fabrication of nanostructures with dimensions below 15 nm and a potential density of 1010 crystals cm-2.

Silicon micro-fabricated miniature polymer electrolyte fuel cells

NASA Astrophysics Data System (ADS)

Kelley, Shawn Christopher

2000-10-01

The present thesis relates the design, fabrication, and testing of a unique type of silicon-based, miniature fuel cell. The fuel cell electrodes were constructed using standard silicon micro-fabrication techniques, and were used to construct miniature polymer electrolyte fuel cells (PEFCs) using NafionRTM. During testing, methanol and oxygen were the common reactants, but hydrogen and oxygen could be used as well. A novel form of an electrodeposited Pt:Ru alloy was developed for use as a methanol electrooxidation catalyst in the mini-PEFCs. An optimized mini-PEFC design was developed, tested, and compared with large PEFCs on the basis of performance. Mini-PEFC performance was equivalent to that of large PEFCs when scaled for active-area, but was limited by the function of the oxygen electrode. The rate of methanol crossover in a methanol/oxygen mini-PEFC was predicted using Fick's first law and the electrode chip feed-hole area. It was shown that the present mini-PEFC design could function as a fuel cell material test structure. Additionally, the mini-PEFCs were tested as two-cell stacks and as methanol sensors. The miniature, silicon-based PEFCs developed here successfully incorporate the essential aspects of a large PEFC in a smaller, simpler design.

Microbridge testing of plasma-enhanced chemical-vapor deposited silicon oxide films on silicon wafers

NASA Astrophysics Data System (ADS)

Cao, Zhiqiang; Zhang, Tong-Yi; Zhang, Xin

2005-05-01

Plasma-enhanced chemical-vapor deposited (PECVD) silane-based oxides (SiOx) have been widely used in both microelectronics and microelectromechanical systems (MEMS) to form electrical and/or mechanical components. In this paper, a nanoindentation-based microbridge testing method is developed to measure both the residual stresses and Young's modulus of PECVD SiOx films on silicon wafers. Theoretically, we considered both the substrate deformation and residual stress in the thin film and derived a closed formula of deflection versus load. The formula fitted the experimental curves almost perfectly, from which the residual stresses and Young's modulus of the film were determined. Experimentally, freestanding microbridges made of PECVD SiOx films were fabricated using the silicon undercut bulk micromachining technique. Some microbridges were subjected to rapid thermal annealing (RTA) at a temperature of 400 °C, 600 °C, or 800 °C to simulate the thermal process in the device fabrication. The results showed that the as-deposited PECVD SiOx films had a residual stress of -155±17MPa and a Young's modulus of 74.8±3.3GPa. After the RTA, Young's modulus remained relatively unchanged at around 75 GPa, however, significant residual stress hysteresis was found in all the films. A microstructure-based mechanism was then applied to explain the experimental results of the residual stress changes in the PECVD SiOx films after the thermal annealing.

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Engineering functionalized multi-phased silicon/silicon oxide nano-biomaterials to passivate the aggressive proliferation of cancer

PubMed Central

Premnath, P.; Tan, B.; Venkatakrishnan, K.

2015-01-01

Currently, the use of nano silicon in cancer therapy is limited as drug delivery vehicles and markers in imaging, not as manipulative/controlling agents. This is due to limited properties that native states of nano silicon and silicon oxides offers. We introduce nano-functionalized multi-phased silicon/silicon oxide biomaterials synthesized via ultrashort pulsed laser synthesis, with tunable properties that possess inherent cancer controlling properties that can passivate the progression of cancer. This nanostructured biomaterial is composed of individual functionalized nanoparticles made of a homogenous hybrid of multiple phases of silicon and silicon oxide in increasing concentration outwards from the core. The chemical properties of the proposed nanostructure such as number of phases, composition of phases and crystal orientation of each functionalized nanoparticle in the three dimensional nanostructure is defined based on precisely tuned ultrashort pulsed laser-material interaction mechanisms. The amorphous rich phased biomaterial shows a 30 fold (95%) reduction in number of cancer cells compared to bulk silicon in 48 hours. Further, the size of the cancer cells reduces by 76% from 24 to 48 hours. This method exposes untapped properties of combination of multiple phases of silicon oxides and its applications in cancer therapy. PMID:26190009

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

NASA Technical Reports Server (NTRS)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Silicon solar cell process. Development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Tanner, D. P.

1978-01-01

Solar cells were fabricated from unconventional silicon sheets, and the performances were characterized with an emphasis on statistical evaluation. A number of solar cell fabrication processes were used and conversion efficiency was measured under AMO condition at 25 C. Silso solar cells using standard processing showed an average efficiency of about 9.6%. Solar cells with back surface field process showed about the same efficiency as the cells from standard process. Solar cells from grain boundary passivation process did not show any improvements in solar cell performance.

Photoluminescence of Porous Silicon-Zinc Oxide Hybrid structures

NASA Astrophysics Data System (ADS)

Olenych, I. B.; Monastyrskii, L. S.; Luchechko, A. P.

2017-03-01

Arrays of ZnO nanostructures, which are optically transparent in the visible range, were grown on the surface of porous silicon by electrochemical deposition. Photoluminescence excitation and emission spectra of the obtained hybrid structures were investigated in 220-450 and 400-800 nm regions, respectively. It is established that multicolor emission is formed by combining the luminescence bands of porous silicon and zinc oxide. The possibility of controlling the photoluminescence spectra by changing the excitation energy is demonstrated. It is revealed that thermal annealing has an effect on the luminescent properties of porous silicon/zinc oxide hybrid structures. Thermal processing at 500°C leads to a sharp decrease of long-wavelength luminescence associated with porous silicon and to an increase of short-wavelength luminescence intensity related to zinc oxide.

Fabricating amorphous silicon solar cells by varying the temperature _of the substrate during deposition of the amorphous silicon layer

DOEpatents

Carlson, David E.

1982-01-01

An improved process for fabricating amorphous silicon solar cells in which the temperature of the substrate is varied during the deposition of the amorphous silicon layer is described. Solar cells manufactured in accordance with this process are shown to have increased efficiencies and fill factors when compared to solar cells manufactured with a constant substrate temperature during deposition of the amorphous silicon layer.

Silicon Carbide Nanotube Oxidation at High Temperatures

NASA Technical Reports Server (NTRS)

Ahlborg, Nadia; Zhu, Dongming

2012-01-01

Silicon Carbide Nanotubes (SiCNTs) have high mechanical strength and also have many potential functional applications. In this study, SiCNTs were investigated for use in strengthening high temperature silicate and oxide materials for high performance ceramic nanocomposites and environmental barrier coating bond coats. The high · temperature oxidation behavior of the nanotubes was of particular interest. The SiCNTs were synthesized by a direct reactive conversion process of multiwall carbon nanotubes and silicon at high temperature. Thermogravimetric analysis (TGA) was used to study the oxidation kinetics of SiCNTs at temperatures ranging from 800degC to1300degC. The specific oxidation mechanisms were also investigated.

Trimming of silicon ring resonator by electron beam induced compaction and strain.

PubMed

Schrauwen, J; Van Thourhout, D; Baets, R

2008-03-17

Silicon is becoming the preferable platform for future integrated components, mostly due to the mature and reliable fabrication capabilities of electronics industry. Nevertheless, even the most advanced fabrication technologies suffer from non-uniformity on wafer scale and on chip scale, causing variations in the critical dimensions of fabricated components. This is an important issue since photonic circuits, and especially cavities such as ring resonators, are extremely sensitive to these variations. In this paper we present a way to circumvent these problems by trimming using electron beam induced compaction of oxide in silicon on insulator. Volume compaction of the oxide cladding causes both changes in the refractive index and creates strain in the silicon lattice. We demonstrate a resonance wavelength red shift 4.91 nm in a silicon ring resonator.

Polyelectrolyte multilayer-assisted fabrication of non-periodic silicon nanocolumn substrates for cellular interface applications

NASA Astrophysics Data System (ADS)

Lee, Seyeong; Kim, Dongyoon; Kim, Seong-Min; Kim, Jeong-Ah; Kim, Taesoo; Kim, Dong-Yu; Yoon, Myung-Han

2015-08-01

Recent advances in nanostructure-based biotechnology have resulted in a growing demand for vertical nanostructure substrates with elaborate control over the nanoscale geometry and a high-throughput preparation. In this work, we report the fabrication of non-periodic vertical silicon nanocolumn substrates via polyelectrolyte multilayer-enabled randomized nanosphere lithography. Owing to layer-by-layer deposited polyelectrolyte adhesives, uniformly-separated polystyrene nanospheres were securely attached on large silicon substrates and utilized as masks for the subsequent metal-assisted silicon etching in solution. Consequently, non-periodic vertical silicon nanocolumn arrays were successfully fabricated on a wafer scale, while each nanocolumn geometric factor, such as the diameter, height, density, and spatial patterning, could be fully controlled in an independent manner. Finally, we demonstrate that our vertical silicon nanocolumn substrates support viable cell culture with minimal cell penetration and unhindered cell motility due to the blunt nanocolumn morphology. These results suggest that vertical silicon nanocolumn substrates may serve as a useful cellular interface platform for performing a statistically meaningful number of cellular experiments in the fields of biomolecular delivery, stem cell research, etc.Recent advances in nanostructure-based biotechnology have resulted in a growing demand for vertical nanostructure substrates with elaborate control over the nanoscale geometry and a high-throughput preparation. In this work, we report the fabrication of non-periodic vertical silicon nanocolumn substrates via polyelectrolyte multilayer-enabled randomized nanosphere lithography. Owing to layer-by-layer deposited polyelectrolyte adhesives, uniformly-separated polystyrene nanospheres were securely attached on large silicon substrates and utilized as masks for the subsequent metal-assisted silicon etching in solution. Consequently, non-periodic vertical

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Sponge-like Si-SiO2 nanocomposite—Morphology studies of spinodally decomposed silicon-rich oxide

NASA Astrophysics Data System (ADS)

Friedrich, D.; Schmidt, B.; Heinig, K. H.; Liedke, B.; Mücklich, A.; Hübner, R.; Wolf, D.; Kölling, S.; Mikolajick, T.

2013-09-01

Sponge-like Si nanostructures embedded in SiO2 were fabricated by spinodal decomposition of sputter-deposited silicon-rich oxide with a stoichiometry close to that of silicon monoxide. After thermal treatment a mean feature size of about 3 nm was found in the phase-separated structure. The structure of the Si-SiO2 nanocomposite was investigated by energy-filtered transmission electron microscopy (EFTEM), EFTEM tomography, and atom probe tomography, which revealed a percolated Si morphology. It was shown that the percolation of the Si network in 3D can also be proven on the basis of 2D EFTEM images by comparison with 3D kinetic Monte Carlo simulations.

Al transmon qubits on silicon-on-insulator for quantum device integration

NASA Astrophysics Data System (ADS)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Fabrication Process of Silicone-based Dielectric Elastomer Actuators

PubMed Central

Rosset, Samuel; Araromi, Oluwaseun A.; Schlatter, Samuel; Shea, Herbert R.

2016-01-01

This contribution demonstrates the fabrication process of dielectric elastomer transducers (DETs). DETs are stretchable capacitors consisting of an elastomeric dielectric membrane sandwiched between two compliant electrodes. The large actuation strains of these transducers when used as actuators (over 300% area strain) and their soft and compliant nature has been exploited for a wide range of applications, including electrically tunable optics, haptic feedback devices, wave-energy harvesting, deformable cell-culture devices, compliant grippers, and propulsion of a bio-inspired fish-like airship. In most cases, DETs are made with a commercial proprietary acrylic elastomer and with hand-applied electrodes of carbon powder or carbon grease. This combination leads to non-reproducible and slow actuators exhibiting viscoelastic creep and a short lifetime. We present here a complete process flow for the reproducible fabrication of DETs based on thin elastomeric silicone films, including casting of thin silicone membranes, membrane release and prestretching, patterning of robust compliant electrodes, assembly and testing. The membranes are cast on flexible polyethylene terephthalate (PET) substrates coated with a water-soluble sacrificial layer for ease of release. The electrodes consist of carbon black particles dispersed into a silicone matrix and patterned using a stamping technique, which leads to precisely-defined compliant electrodes that present a high adhesion to the dielectric membrane on which they are applied. PMID:26863283

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Fully Tunable Silicon Nanowire Arrays Fabricated by Soft Nanoparticle Templating.

PubMed

Rey, By Marcel; Elnathan, Roey; Ditcovski, Ran; Geisel, Karen; Zanini, Michele; Fernandez-Rodriguez, Miguel-Angel; Naik, Vikrant V; Frutiger, Andreas; Richtering, Walter; Ellenbogen, Tal; Voelcker, Nicolas H; Isa, Lucio

2016-01-13

We demonstrate a fabrication breakthrough to produce large-area arrays of vertically aligned silicon nanowires (VA-SiNWs) with full tunability of the geometry of the single nanowires and of the whole array, paving the way toward advanced programmable designs of nanowire platforms. At the core of our fabrication route, termed "Soft Nanoparticle Templating", is the conversion of gradually compressed self-assembled monolayers of soft nanoparticles (microgels) at a water-oil interface into customized lithographical masks to create VA-SiNW arrays by means of metal-assisted chemical etching (MACE). This combination of bottom-up and top-down techniques affords excellent control of nanowire etching site locations, enabling independent control of nanowire spacing, diameter and height in a single fabrication route. We demonstrate the fabrication of centimeter-scale two-dimensional gradient photonic crystals exhibiting continuously varying structural colors across the entire visible spectrum on a single silicon substrate, and the formation of tunable optical cavities supported by the VA-SiNWs, as unambiguously demonstrated through numerical simulations. Finally, Soft Nanoparticle Templating is combined with optical lithography to create hierarchical and programmable VA-SiNW patterns.

Mechanical Properties and Microstructure of Biomorphic Silicon Carbide Ceramics Fabricated from Wood Precursors

NASA Technical Reports Server (NTRS)

Singh, Mrityunjay; Salem, J. A.; Gray, Hugh R. (Technical Monitor)

2002-01-01

Silicon carbide based, environment friendly, biomorphic ceramics have been fabricated by the pyrolysis and infiltration of natural wood (maple and mahogany) precursors. This technology provides an eco-friendly route to advanced ceramic materials. These biomorphic silicon carbide ceramics have tailorable properties and behave like silicon carbide based materials manufactured by conventional approaches. The elastic moduli and fracture toughness of biomorphic ceramics strongly depend on the properties of starting wood preforms and the degree of molten silicon infiltration. Mechanical properties of silicon carbide ceramics fabricated from maple wood precursors indicate the flexural strengths of 3441+/-58 MPa at room temperature and 230136 MPa at 1350C. Room temperature fracture toughness of the maple based material is 2.6 +/- 0.2 MPa(square root of)m while the mahogany precursor derived ceramics show a fracture toughness of 2.0 +/- 0.2 Mpa(square root of)m. The fracture toughness and the strength increase as the density of final material increases. Fractographic characterization indicates the failure origins to be pores and chipped pockets of silicon.

Processing of uranium oxide and silicon carbide based fuel using polymer infiltration and pyrolysis

NASA Astrophysics Data System (ADS)

Singh, Abhishek K.; Zunjarrao, Suraj C.; Singh, Raman P.

2008-09-01

Ceramic composite pellets consisting of uranium oxide, UO 2, contained within a silicon carbide matrix, were fabricated using a novel processing technique based on polymer infiltration and pyrolysis (PIP). In this process, particles of depleted uranium oxide, in the form of U 3O 8, were dispersed in liquid allylhydridopolycarbosilane (AHPCS), and subjected to pyrolysis up to 900 °C under a continuous flow of ultra high purity argon. The pyrolysis of AHPCS, at these temperatures, produced near-stoichiometric amorphous silicon carbide ( a-SiC). Multiple polymer infiltration and pyrolysis (PIP) cycles were performed to minimize open porosity and densify the silicon carbide matrix. Analytical characterization was conducted to investigate chemical interaction between U 3O 8 and SiC. It was observed that U 3O 8 reacted with AHPCS during the very first pyrolysis cycle, and was converted to UO 2. As a result, final composition of the material consisted of UO 2 particles contained in an a-SiC matrix. The physical and mechanical properties were also quantified. It is shown that this processing scheme promotes uniform distribution of uranium fuel source along with a high ceramic yield of the parent matrix.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Demonstration of submicron square-like silicon waveguide using optimized LOCOS process.

PubMed

Desiatov, Boris; Goykhman, Ilya; Levy, Uriel

2010-08-30

We demonstrate the design, fabrication and experimental characterization of a submicron-scale silicon waveguide that is fabricated by local oxidation of silicon. The use of local oxidation process allows defining the waveguide geometry and obtaining smooth sidewalls. The process can be tuned to precisely control the shape and the dimensions of the waveguide. The fabricated waveguides are measured using near field scanning optical microscope at 1550 nm wavelength. These measurements show mode width of 0.4 µm and effective refractive index of 2.54. Finally, we demonstrate the low loss characteristics of our waveguide by imaging the light scattering using an infrared camera.

Fabrication of flexible and vertical silicon nanowire electronics.

PubMed

Weisse, Jeffrey M; Lee, Chi Hwan; Kim, Dong Rip; Zheng, Xiaolin

2012-06-13

Vertical silicon nanowire (SiNW) array devices directly connected on both sides to metallic contacts were fabricated on various non-Si-based substrates (e.g., glass, plastics, and metal foils) in order to fully exploit the nanomaterial properties for final applications. The devices were realized with uniform length Ag-assisted electroless etched SiNW arrays that were detached from their fabrication substrate, typically Si wafers, reattached to arbitrary substrates, and formed with metallic contacts on both sides of the NW array. Electrical characterization of the SiNW array devices exhibits good current-voltage characteristics consistent with the SiNW morphology.

Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

NASA Astrophysics Data System (ADS)

Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

2018-01-01

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

Spherical silicon-shell photonic band gap structures fabricated by laser-assisted chemical vapor deposition

NASA Astrophysics Data System (ADS)

Wang, H.; Yang, Z. Y.; Lu, Y. F.

2007-02-01

Laser-assisted chemical vapor deposition was applied in fabricating three-dimensional (3D) spherical-shell photonic band gap (PBG) structures by depositing silicon shells covering silica particles, which had been self-assembled into 3D colloidal crystals. The colloidal crystals of self-assembled silica particles were formed on silicon substrates using the isothermal heating evaporation approach. A continuous wave Nd:YAG laser (1064nm wavelength) was used to deposit silicon shells by thermally decomposing disilane gas. Periodic silicon-shell/silica-particle PBG structures were obtained. By removing the silica particles enclosed in the silicon shells using hydrofluoric acid, hollow spherical silicon-shell arrays were produced. This technique is capable of fabricating structures with complete photonic band gaps, which is predicted by simulations with the plane wave method. The techniques developed in this study have the potential to flexibly engineer the positions of the PBGs by varying both the silica particle size and the silicon-shell thickness. Ellipsometry was used to investigate the specific photonic band gaps for both structures.

Road to Silicon Microsphere Fabrication and Mode Coupling

DTIC Science & Technology

2014-07-01

from optical fiber onto a microsphere in whispering gallery mode (courtesy of B. Butkus, Biophotonics International [2...Butkus, Biophotonics International [5]). 2 BACKGROUND SILICON MICROSPHERE FABRICATION METHODS Processes for forming spherical structures exist in...Sensitive DNA Detection.” October 2003. Biophotonics International. http://www.rowland.org/rjf/vollmer/images/biophotonics.pdf [6] James E. McDonald

Fabrication of thermal microphotonic sensors and sensor arrays

DOEpatents

Shaw, Michael J.; Watts, Michael R.; Nielson, Gregory N.

2010-10-26

A thermal microphotonic sensor is fabricated on a silicon substrate by etching an opening and a trench into the substrate, and then filling in the opening and trench with silicon oxide which can be deposited or formed by thermally oxidizing a portion of the silicon substrate surrounding the opening and trench. The silicon oxide forms a support post for an optical resonator which is subsequently formed from a layer of silicon nitride, and also forms a base for an optical waveguide formed from the silicon nitride layer. Part of the silicon substrate can be selectively etched away to elevate the waveguide and resonator. The thermal microphotonic sensor, which is useful to detect infrared radiation via a change in the evanescent coupling of light between the waveguide and resonator, can be formed as a single device or as an array.

Infrared Dielectric Properties of Low-Stress Silicon Oxide

NASA Technical Reports Server (NTRS)

Cataldo, Giuseppe; Wollack, Edward J.; Brown, Ari D.; Miller, Kevin H.

2016-01-01

Silicon oxide thin films play an important role in the realization of optical coatings and high-performance electrical circuits. Estimates of the dielectric function in the far- and mid-infrared regime are derived from the observed transmittance spectrum for a commonly employed low-stress silicon oxide formulation. The experimental, modeling, and numerical methods used to extract the dielectric function are presented.

Graphene oxide nanostructures modified multifunctional cotton fabrics

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Karthikeyan; Navaneethaiyer, Umasuthan; Mohan, Rajneesh; Lee, Jehee; Kim, Sang-Jae

2012-06-01

Surface modification of cotton fabrics using graphene oxide (GO) nanostructures was reported. Scanning electron microscopic (SEM) investigations revealed that the GO nanostructure was coated onto the cotton fabric. The molecular level interaction between the graphene oxide and the cotton fabric is studied in detail using the Fourier transform infra-red (FTIR) spectra. Thermogravimetric analysis (TGA) showed that GO loaded cotton fabrics have enhanced thermal stability compared to the bare cotton fabrics. The photocatalytic activity of the GO-coated cotton fabrics was investigated by measuring the photoreduction of resazurin (RZ) into resorufin (RF) under UV light irradiation. The antibacterial activity was evaluated against both Gram-negative and Gram-positive bacteria and the results indicated that the GO-coated cotton fabrics are more toxic towards the Gram-positive ones. Our results provide a way to develop graphene oxide-based devices for the biomedical applications for improving health care.

Anti resonant reflecting optical waveguide structure based on oxidized porous silicon for label free bio sensing applications

NASA Astrophysics Data System (ADS)

Haji, L.; Hiraoui, M.; Lorrain, N.; Guendouz, M.

2012-03-01

In this letter we report on the use of an electrochemical process for the fabrication of anti resonant reflecting optical waveguide based on oxidized porous silicon. This method is known to allow the formation of various photonic structures (Bragg mirror, microcavity), thanks to the easy and in situ modulation of the porosity and thus of the refractive index. Planar anti resonant reflecting optical waveguide structure made from porous silicon is demonstrated to be very effective for low losses as compared to conventional resonant waveguide. Optical measurements carried out for TE and TM polarizations are reported and related to optical sensing.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Sintered silicon nitrode recuperator fabrication

NASA Technical Reports Server (NTRS)

Gatti, A.; Chiu, W. S.; Mccreight, L. R.

1980-01-01

The preliminary design and a demonstration of the feasibility of fabricating submodules of an automotive Stirling engine recuperator for waste heat recovery at 370 C are described. Sinterable silicon nitride (Sialon) tubing and plates were fabricated by extrusion and hydrostatic pressing, respectively, suitable for demonstrating a potential method of constructing ceramic recuperator-type heat exchangers. These components were fired in nitrogen atmosphere to 1800 C without significant scale formation so that they can be used in the as-fired condition. A refractory glass composition (Al2O3 x 4.5 CaO.MgO x 11SiO2) was used to join and seal component parts by a brazing technique which formed strong recuperator submodules capable of withstanding repeated thermal cycling to 1370 C. The corrosion resistance of these materials to Na2SO4 + NaCl carbon mixtures was also assessed in atmospheres of air, hydrogen and CO2-N2-H2O mixtures at both 870 C and 1370 C for times to 1000 hours. No significant reaction was observed under any of these test conditions.

Key Processes of Silicon-On-Glass MEMS Fabrication Technology for Gyroscope Application.

PubMed

Ma, Zhibo; Wang, Yinan; Shen, Qiang; Zhang, Han; Guo, Xuetao

2018-04-17

MEMS fabrication that is based on the silicon-on-glass (SOG) process requires many steps, including patterning, anodic bonding, deep reactive ion etching (DRIE), and chemical mechanical polishing (CMP). The effects of the process parameters of CMP and DRIE are investigated in this study. The process parameters of CMP, such as abrasive size, load pressure, and pH value of SF1 solution are examined to optimize the total thickness variation in the structure and the surface quality. The ratio of etching and passivation cycle time and the process pressure are also adjusted to achieve satisfactory performance during DRIE. The process is optimized to avoid neither the notching nor lag effects on the fabricated silicon structures. For demonstrating the capability of the modified CMP and DRIE processes, a z-axis micro gyroscope is fabricated that is based on the SOG process. Initial test results show that the average surface roughness of silicon is below 1.13 nm and the thickness of the silicon is measured to be 50 μm. All of the structures are well defined without the footing effect by the use of the modified DRIE process. The initial performance test results of the resonant frequency for the drive and sense modes are 4.048 and 4.076 kHz, respectively. The demands for this kind of SOG MEMS device can be fulfilled using the optimized process.

Silicon Integrated Optics: Fabrication and Characterization

NASA Astrophysics Data System (ADS)

Shearn, Michael Joseph, II

For decades, the microelectronics industry has sought integration and miniaturization as canonized in Moore's Law, and has continued doubling transistor density about every two years. However, further miniaturization of circuit elements is creating a bandwidth problem as chip interconnect wires shrink as well. A potential solution is the creation of an on-chip optical network with low delays that would be impossible to achieve using metal buses. However, this technology requires integrating optics with silicon microelectronics. The lack of efficient silicon optical sources has stymied efforts of an all-Si optical platform. Instead, the integration of efficient emitter materials, such as III-V semiconductors, with Si photonic structures is a low-cost, CMOS-compatible alternative platform. This thesis focuses on making and measuring on-chip photonic structures suitable for on-chip optical networking. The first part of the thesis assesses processing techniques of silicon and other semiconductor materials. Plasmas for etching and surface modification are described and used to make bonded, hybrid Si/III-V structures. Additionally, a novel masking method using gallium implantation into silicon for pattern definition is characterized. The second part of the thesis focuses on demonstrations of fabricated optical structures. A dense array of silicon devices is measured, consisting of fully-etched grating couplers, low-loss waveguides and ring resonators. Finally, recent progress in the Si/III-V hybrid system is discussed. Supermode control of devices is described, which uses changing Si waveguide width to control modal overlap with the gain material. Hybrid Si/III-V, Fabry-Perot evanescent lasers are demonstrated, utilizing a CMOS-compatible process suitable for integration on in electronics platforms. Future prospects and ultimate limits of Si devices and the hybrid Si/III-V system are also considered.

A room temperature method for the formation of ultrathin silicon oxide films

NASA Astrophysics Data System (ADS)

Muisener, Richard John

Growing interest surrounds the use of thin films to impart unique surface properties without adversely affecting those of the bulk. One such example is the formation of a stable high-energy silicon oxide surface on polymers. Thin silicon oxide films have been used to tailor the surface properties of many materials. Conventional methods for SiOx film fabrication such as chemical vapor deposition require either high temperature or expensive vacuum chambers. This research focuses on the intrinsically inexpensive process of UV-ozone to form ultrathin SiOx films from polysiloxane precursors at room temperature and atmospheric pressure. Chemical evidence suggests a complete conversion from organic polymer to inorganic ceramic. Through XPS, the UV-ozone treatment oxidizes over 95% of the silicone's organic side groups with a resulting stoichiometry Of Si 1O2.2C0.08. The silicon oxidation state changes from 2+ in poly(dimethylsiloxane) to 93% 4+ corresponding to SiO2. IR studies show a total loss of methyl bands and the growth of a new Si-O band centered at 1225 cm-1. Gas phase reaction products suggest a radical driven process. The physical properties also suggest a complete conversion to SiO x. Excellent control of film thickness, as low as 2 nm, has been demonstrated by variable angle spectroscopic ellipsometry. The ellipsometrically determined thickness loss of 55% during treatment corresponds to an SiOx film density of 1.9 g/cm3. The continuity of the film is demonstrated by electrical properties and a very low water contact angle consistent with SiOx. The later property ensures that the SiOx films are anti-fogging in nature. Unique hydrophilic-hydrophobic structures were formed through photo-patterning. The reaction has been successfully modeled as self-limiting based on the diffusion of ozone. The chief reactant, atomic oxygen, is generated by the photochemical dissociation of ozone and quickly generates radical species within the polymer film. The reaction proceeds

Fabrication and Characterization of Thermo-Optic Mach-Zehnder Silicon Modulator

NASA Astrophysics Data System (ADS)

Park, Yeongho

This thesis focuses on the modeling, design, and fabrication of the Thermo-Optic Mach-Zehnder Modulator, which is one of the simple active devices in silicon photonics. The Mach-Zehnder interferometer (MZI) was formed as an optical path on a silicon on insulator (SOI) wafer of 2040+/-80 nm thick, and the thermo-optic effect was used to modulate the infrared light of 1553 nm wavelength by controlling the temperature of the one arm of the MZI. To fabricate and understand the Si photonic device, the whole process from theory to the measurement setup is introduced. Additionally, all the fabrication details and some informative experiments which were performed during the fabrication are discussed for students who will study the more developed devices. The width of the designed waveguide is 4 mum, but the width of the fabricated waveguide is 3.0+/-0.2 mum due to the isotropic etching. For the lithography for both patterning waveguides and metal contacts, the AZ 5214 photoresist was used, and the details of the lithography was discussed. Furthermore, the lift-off method was performed and introduced to solve the over-etching problem. The fabricated metal contacts can withstand up to 1.6W, and the electric power 0.3W is required to make Pi phase difference according to the simulation result by the simulation software Lumerical. The optical output of the device was not detected due to the huge losses from the sidewall roughness and the insertion loss, so it is discussed in the experimental measurement chapter.

Effect of solvents on optical band gap of silicon-doped graphene oxide

NASA Astrophysics Data System (ADS)

Tul Ain, Qura; Al-Modlej, Abeer; Alshammari, Abeer; Naeem Anjum, Muhammad

2018-03-01

The objective of this study was to determine the influence on the optical band gap when the same amount of silicon-doped graphene oxide was dissolved in three different solvents namely, distilled water, benzene, and dichloroethane. Ultraviolet-visible spectroscopy was used to analyse the optical properties of the solutions. Among all these solutions distilled water containing silicon-doped graphene oxide has the smallest optical band gap of 2.9 eV and is considered a semiconductor. Other solutions are not considered as semiconductors as they have optical band gaps greater than 4 eV. It was observed that there is an increase in the value of optical band gap of distilled water, benzene, and dichloroethane solutions indicating a rise in the insulating behaviour. In this experiment, graphene oxide was synthesised from graphite powder by modified Hummer’s method and was then doped with silicon. Synthesis and doping of graphene oxide were confirmed by various characterization techniques. Fourier transmission infrared spectroscopy was used for identification of surface functional groups. X-ray diffraction was carried out to confirm the formation of crystalline graphene oxide and silicon doped graphene oxide. In x-ray diffraction pattern, shifting of intensity peak from a 2θ value of 26.5° to 10° confirmed the synthesis of graphene oxide and various intensity peaks at different values of 2θ confirmed doping of graphene oxide with silicon. Scanning electron microscopy images indicated that graphene oxide sheets were decorated with spherical silicon nanoparticles. Energy dispersive x-ray spectroscopy showed that silicon doped graphene oxide powder contained 63.36% carbon, 34.05% oxygen, and 2.6% silicon.

A radiation detector fabricated from silicon photodiode.

PubMed

Yamamoto, H; Hatakeyama, S; Norimura, T; Tsuchiya, T

1984-12-01

A silicon photodiode is converted to a low energy charged particle radiation detector. The window thickness of the fabricated detector is evaluated to be 50 micrograms/cm2. The area of the depletion region is 13.2 mm2 and the depth of it is estimated to be about 100 microns. The energy resolution (FWHM) is 14.5 ke V for alpha-particles from 241Am and 2.5 ke V for conversion electrons from 109Cd, respectively.

Silicon Qubits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ladd, Thaddeus D.; Carroll, Malcolm S.

2018-02-28

Silicon is a promising material candidate for qubits due to the combination of worldwide infrastructure in silicon microelectronics fabrication and the capability to drastically reduce decohering noise channels via chemical purification and isotopic enhancement. However, a variety of challenges in fabrication, control, and measurement leaves unclear the best strategy for fully realizing this material’s future potential. In this article, we survey three basic qubit types: those based on substitutional donors, on metal-oxide-semiconductor (MOS) structures, and on Si/SiGe heterostructures. We also discuss the multiple schema used to define and control Si qubits, which may exploit the manipulation and detection of amore » single electron charge, the state of a single electron spin, or the collective states of multiple spins. Far from being comprehensive, this article provides a brief orientation to the rapidly evolving field of silicon qubit technology and is intended as an approachable entry point for a researcher new to this field.« less

Mode-converting coupler for silicon-on-sapphire devices

NASA Astrophysics Data System (ADS)

Zlatanovic, S.; Offord, B. W.; Owen, M.; Shimabukuro, R.; Jacobs, E. W.

2015-02-01

Silicon-on-sapphire devices are attractive for the mid-infrared optical applications up to 5 microns due to the low loss of both silicon and sapphire in this wavelength band. Designing efficient couplers for silicon-on-sapphire devices presents a challenge due to a highly confined mode in silicon and large values of refractive index of both silicon and sapphire. Here, we present design, fabrication, and measurements of a mode-converting coupler for silicon-on-sapphire waveguides. We utilize a mode converter layout that consists of a large waveguide that is overlays a silicon inverse tapered waveguide. While this geometry was previously utilized for silicon-on-oxide devices, the novelty is in using materials that are compatible with the silicon-on-sapphire platform. In the current coupler the overlaying waveguide is made of silicon nitride. Silicon nitride is the material of choice because of the large index of refraction and low absorption from near-infrared to mid-infrared. The couplers were fabricated using a 0.25 micron silicon-on-sapphire process. The measured coupling loss from tapered lensed silica fibers to the silicon was 4.8dB/coupler. We will describe some challenges in fabrication process and discuss ways to overcome them.

Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Tanner, D. P.

1979-01-01

Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance.

Fabricating micro-instruments in surface-micromachined polycrystalline silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comtois, J.H.; Michalicek, M.A.; Barron, C.C.

1997-04-01

Smaller, lighter instruments can be fabricated as Micro-Electro-Mechanical Systems (MEMS), having micron scale moving parts packaged together with associated control and measurement electronics. Batch fabrication of these devices will make economical applications such as condition-based machine maintenance and remote sensing. The choice of instrumentation is limited only by the designer`s imagination. This paper presents one genre of MEMS fabrication, surface-micromachined polycrystalline silicon (polysilicon). Two currently available but slightly different polysilicon processes are presented. One is the ARPA-sponsored ``Multi-User MEMS ProcesS`` (MUMPS), available commercially through MCNC; the other is the Sandia National Laboratories ``Sandia Ultra-planar Multilevel MEMS Technology`` (SUMMiT). Example componentsmore » created in both processes will be presented, with an emphasis on actuators, actuator force testing instruments, and incorporating actuators into larger instruments.« less

Tribological interaction between polytetrafluoroethylene and silicon oxide surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Uçar, A.; Çopuroğlu, M.; Suzer, S., E-mail: suzer@fen.bilkent.edu.tr

2014-10-28

We investigated the tribological interaction between polytetrafluoroethylene (PTFE) and silicon oxide surfaces. A simple rig was designed to bring about a friction between the surfaces via sliding a piece of PTFE on a thermally oxidized silicon wafer specimen. A very mild inclination (∼0.5°) along the sliding motion was also employed in order to monitor the tribological interaction in a gradual manner as a function of increasing contact force. Additionally, some patterns were sketched on the silicon oxide surface using the PTFE tip to investigate changes produced in the hydrophobicity of the surface, where the approximate water contact angle was 45°more » before the transfer. The nature of the transferred materials was characterized by X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). XPS results revealed that PTFE was faithfully transferred onto the silicon oxide surface upon even at the slightest contact and SEM images demonstrated that stable morphological changes could be imparted onto the surface. The minimum apparent contact pressure to realize the PTFE transfer is estimated as 5 kPa, much lower than reported previously. Stability of the patterns imparted towards many chemical washing processes lead us to postulate that the interaction is most likely to be chemical. Contact angle measurements, which were carried out to characterize and monitor the hydrophobicity of the silicon oxide surface, showed that upon PTFE transfer the hydrophobicity of the SiO{sub 2} surface could be significantly enhanced, which might also depend upon the pattern sketched onto the surface. Contact angle values above 100° were obtained.« less

Fabrication and RF characterization of zinc oxide based Film Bulk Acoustic Resonator

NASA Astrophysics Data System (ADS)

Patel, Raju; Bansal, Deepak; Agrawal, Vimal Kumar; Rangra, Kamaljit; Boolchandani, Dharmendar

2018-06-01

This work reports fabrication and characterization of Film Bulk Acoustic Resonator (FBAR) to improve the performance characteristics for RF filter and sensing application. Zinc oxide as a piezoelectric (PZE) material was deposited on an aluminum bottom electrode using an RF magnetron sputtering, at room temperature, and gold as top electrode for the resonator. Tetramethyl ammonium hydroxide (TMAH) setup was used for bulk silicon etching to make back side cavity to confine the acoustic signals. The transmission characteristics show that the FBARs have a central frequency at 1.77 GHz with a return loss of -10.7 dB.

Deformable silicone grating fabricated with a photo-imprinted polymer mold

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yamada, Itsunari, E-mail: yamada.i@e.usp.ac.jp; Nishii, Junji; Saito, Mitsunori

A tunable transmission grating was fabricated by molding a silicone elastomer (polydimethylsiloxane). Its optical characteristics were then evaluated during compression. For fabrication, a glass plate with a photoimprinted polymer grating film was used as a mold. Both the grating period and diffraction transmittance of the molded elastomer were functions of the compressive stress. The grating period changed from 3.02 to 2.86 μm during compressing the elastomer in the direction perpendicular to the grooves.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Fabrication of two-dimensional periodic structures on silicon after scanning irradiation with femtosecond laser multi-beams

NASA Astrophysics Data System (ADS)

Pan, An; Si, Jinhai; Chen, Tao; Li, Cunxia; Hou, Xun

2016-04-01

Two-dimensional (2D) periodic structures were fabricated on silicon surfaces by femtosecond laser irradiation in air and water, with the assistance of a microlens array (MLA) placed in the beam's path. By scanning the laser beam along the silicon surface, multiple grooves were simultaneously fabricated in parallel along with smaller laser-induced ripples. The 2D periodic structures contained long-periodic grooves and perpendicular short-periodic laser-induced ripples, which had periods of several microns and several hundred nanometers, respectively. We investigated the influence of laser power and scanning velocity on the morphological evolution of the 2D periodic structures in air and water. Large-area grid-like structures with ripples were fabricated by successively scanning once along each direction of the silicon's surface, which showed enhanced optical absorption. Hydrofluoric acid was then used to remove any oxygen and laser-induced defects for all-silicon structures.

Hexagonal Ag nanoarrays induced enhancement of blue light emission from amorphous oxidized silicon nitride via localized surface plasmon coupling.

PubMed

Ma, Zhongyuan; Ni, Xiaodong; Zhang, Wenping; Jiang, Xiaofan; Yang, Huafeng; Yu, Jie; Wang, Wen; Xu, Ling; Xu, Jun; Chen, Kunji; Feng, Duan

2014-11-17

A significant enhancement of blue light emission from amorphous oxidized silicon nitride (a-SiNx:O) films is achieved by introduction of ordered and size-controllable arrays of Ag nanoparticles between the silicon substrate and a-SiNx:O films. Using hexagonal arrays of Ag nanoparticles fabricated by nanosphere lithography, the localized surface plasmons (LSPs) resonance can effectively increase the internal quantum efficiency from 3.9% to 13.3%. Theoretical calculation confirms that the electromagnetic field-intensity enhancement is through the dipole surface plasma coupling with the excitons of a-SiNx:O films, which demonstrates a-SiNx:O films with enhanced blue emission are promising for silicon-based light-emitting applications by patterned Ag arrays.

High-aspect-ratio, silicon oxide-enclosed pillar structures in microfluidic liquid chromatography.

PubMed

Taylor, Lisa C; Lavrik, Nickolay V; Sepaniak, Michael J

2010-11-15

The present paper discusses the ability to separate chemical species using high-aspect-ratio, silicon oxide-enclosed pillar arrays. These miniaturized chromatographic systems require smaller sample volumes, experience less flow resistance, and generate superior separation efficiency over traditional packed bed liquid chromatographic columns, improvements controlled by the increased order and decreased pore size of the systems. In our distinctive fabrication sequence, plasma-enhanced chemical vapor deposition (PECVD) of silicon oxide is used to alter the surface and structural properties of the pillars for facile surface modification while improving the pillar mechanical stability and increasing surface area. The separation behavior of model compounds within our pillar systems indicated an unexpected hydrophobic-like separation mechanism. The effects of organic modifier, ionic concentration, and pressure-driven flow rate were studied. A decrease in the organic content of the mobile phase increased peak resolution while detrimentally effecting peak shape. A resolution of 4.7 (RSD = 3.7%) was obtained for nearly perfect Gaussian shaped peaks, exhibiting plate heights as low as 1.1 and 1.8 μm for fluorescein and sulforhodamine B, respectively. Contact angle measurements and DART mass spectrometry analysis indicate that our employed elastomeric soft bonding technique modifies pillar properties, creating a fortuitous stationary phase. This discovery provides evidence supporting the ability to easily functionalize PECVD oxide surfaces by gas-phase reactions.

Metal Oxide Thin Film Transistors on Paper Substrate: Fabrication, Characterization, and Printing Process

NASA Astrophysics Data System (ADS)

Choi, Nack-Bong

Flexible electronics is an emerging next-generation technology that offers many advantages such as light weight, durability, comfort, and flexibility. These unique features enable many new applications such as flexible display, flexible sensors, conformable electronics, and so forth. For decades, a variety of flexible substrates have been demonstrated for the application of flexible electronics. Most of them are plastic films and metal foils so far. For the fundamental device of flexible circuits, thin film transistors (TFTs) using poly silicon, amorphous silicon, metal oxide and organic semiconductor have been successfully demonstrated. Depending on application, low-cost and disposable flexible electronics will be required for convenience. Therefore it is important to study inexpensive substrates and to explore simple processes such as printing technology. In this thesis, paper is introduced as a new possible substrate for flexible electronics due to its low-cost and renewable property, and amorphous indium gallium zinc oxide (a-IGZO) TFTs are realized as the promising device on the paper substrate. The fabrication process and characterization of a-IGZO TFT on the paper substrate are discussed. a-IGZO TFTs using a polymer gate dielectric on the paper substrate demonstrate excellent performances with field effect mobility of ˜20 cm2 V-1 s-1, on/off current ratio of ˜106, and low leakage current, which show the enormous potential for flexible electronics application. In order to complement the n-channel a-IGZO TFTs and then enable complementary metal-oxide semiconductor (CMOS) circuit architectures, cuprous oxide is studied as a candidate material of p-channel oxide TFTs. In this thesis, a printing process is investigated as an alternative method for the fabrication of low-cost and disposable electronics. Among several printing methods, a modified offset roll printing that prints high resolution patterns is presented. A new method to fabricate a high resolution

Plastic-Syringe Induced Silicone Contamination in Organic Photvoltaic Fabrication: Implications for Small-Volume Additives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carr, John A.; Nalwa, Kanwar S.; Mahadevapuram, Rakesh

Herein, the implications of silicone contamination found in solution-processed conjugated polymer solar cells are explored. Similar to a previous work based on molecular cells, we find this contamination as a result of the use of plastic syringes during fabrication. However, in contrast to the molecular case, we find that glass-syringe fabricated devices give superior performance than plastic-syringe fabricated devices in poly(3-hexylthiophene)-based cells. We find that the unintentional silicone addition alters the solution’s wettability, which translates to a thinner, less absorbent film on spinning. With many groups studying the effects of small-volume additives, this work should be closely considered as manymore » of these additives may also directly alter the solutions’ wettability, or the amount of silicone dissolved off the plastic syringes, or both. Thereby, film thickness, which generally is not reported in detail, can vary significantly from device to device.« less

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Fabrication of a high-precision spherical micromirror by bending a silicon plate with a metal pad.

PubMed

Wu, Tong; Hane, Kazuhiro

2011-09-20

We demonstrate here the fabrication of a smooth mirror surface by bending a thin silicon plate. A spherical surface is achieved by the bending moment generated in the circumference of the micromirror. Both convex and concave spherical micromirrors are realized through the anodic bonding of silicon and Pyrex glass. Since the mirror surface is originated from the polished silicon surface and no additional etching is introduced for manufacturing, the surface roughness is thus limited to the polishing error. This novel approach opens possibilities for fabricating a smooth surface for micromirror and microlens applications.

Dopants Diffusion in Silicon during Molecular Oxygen/nitrogen Trifluoride Oxidation and Related Phenomena

NASA Astrophysics Data System (ADS)

Kim, U. S.

1990-01-01

To date, chlorine has been used as useful additives in silicon oxidation. However, rapid scaling of device dimensions motivates the development of a new dielectric layer or modification of the silicon dioxide itself. More recently, chemically enhanced thermal oxidation by the use of fluorine containing species has been introduced to verify the potential of fluorine in the silicon oxidation process. In this study, gaseous nitrogen trifluoride (NF _3) was selected as the fluorine oxidizing source based on ease of use and was compared with the dichlorofluoroethane (C_2H _3Cl_2F) source. Two different kinds of boron marker samples were prepared and oxidized in O_2/NF_3 ambient for the comparison of surface vs bulk oxidation enhanced/retarded diffusion (OED/ORD). The phosphorus, arsenic and antimony diffusion in silicon during fluorine oxidation has been studied using the various covering layers such as SiO_2, Si_3 N_4, and SiO_2 + Si_3N_4 layers. The oxidation related phenomena, i.e. enhanced silicon and silicon nitride oxidation in fluorine ambient were studied and correlated with the point defect balance at the oxidizing interface. The results of this investigation were discussed with special emphasis on the effect of fluorine on enhanced oxidation and dopant diffusion.

Fe₃O₄⁻Silicone Mixture as Flexible Actuator.

PubMed

Song, Kahye; Cha, Youngsu

2018-05-08

In this study, we introduce Fe₃O₄-silicone flexible composite actuators fabricated by combining silicone and iron oxide particles. The actuators exploit the flexibility of silicone and the electric conductivity of iron oxide particles. These actuators are activated by electrostatic force using the properties of the metal particles. Herein, we investigate the characteristic changes in actuation performance by increasing the concentration of iron oxide from 1% to 20%. The developed flexible actuators exhibit a resonant frequency near 3 Hz and their actuation amplitudes increase with increasing input voltage. We found that the actuator can move well at metal particle concentrations >2.5%. We also studied the changes in actuation behavior, depending on the portion of the Fe₃O₄-silicone in the length. Overall, we experimentally analyzed the characteristics of the newly proposed metal particle-silicone composite actuators.

Plasma-Sprayed Refractory Oxide Coatings on Silicon-Base Ceramics

NASA Technical Reports Server (NTRS)

Tewari, Surendra

1997-01-01

Silicon-base ceramics are promising candidate materials for high temperature structural applications such as heat exchangers, gas turbines and advanced internal combustion engines. Composites based on these materials are leading candidates for combustor materials for HSCT gas turbine engines. These materials possess a combination of excellent physical and mechanical properties at high temperatures, for example, high strength, high toughness, high thermal shock resistance, high thermal conductivity, light weight and excellent oxidation resistance. However, environmental durability can be significantly reduced in certain conditions such as when molten salts, H2 or water vapor are present. The oxidation resistance of silicon-base materials is provided by SiO2 protective layer. Molten salt reacts with SiO2 and forms a mixture of SiO2 and liquid silicate at temperatures above 800C. Oxygen diffuses more easily through the chemically altered layer, resulting in a catastrophic degradation of the substrate. SiC and Si3N4 are not stable in pure H2 and decompose to silicon and gaseous species such as CH4, SiH, SiH4, N2, and NH3. Water vapor is known to slightly increase the oxidation rate of SiC and Si3N4. Refractory oxides such as alumina, yttria-stabilized zirconia, yttria and mullite (3Al2O3.2SiO2) possess excellent environmental durability in harsh conditions mentioned above. Therefore, refractory oxide coatings on silicon-base ceramics can substantially improve the environmental durability of these materials by acting as a chemical reaction barrier. These oxide coatings can also serve as a thermal barrier. The purpose of this research program has been to develop refractory oxide chemical/thermal barrier coatings on silicon-base ceramics to provide extended temperature range and lifetime to these materials in harsh environments.

Ion implantation reduces radiation sensitivity of metal oxide silicon /MOS/ devices

NASA Technical Reports Server (NTRS)

1971-01-01

Implanting nitrogen ions improves hardening of silicon oxides 30 percent to 60 percent against ionizing radiation effects. Process reduces sensitivity, but retains stability normally shown by interfaces between silicon and thermally grown oxides.

Net shape fabrication of Alpha Silicon Carbide turbine components

NASA Technical Reports Server (NTRS)

Storm, R. S.

1982-01-01

Development of Alpha Silicon Carbide components by net shape fabrication techniques has continued in conjunction with several turbine engine programs. Progress in injection molding of simple parts has been extended to much larger components. Turbine rotors fabricated by a one piece molding have been successfully spin tested above design speeds. Static components weighing up to 4.5 kg and 33 cc in diameter have also been produced using this technique. Use of sintering fixtures significantly improves dimensional control. A new Si-SiC composite material has also been developed with average strengths up to 1000 MPa (150 ksi) at 1200 C.

Wet-Chemical Preparation of Silicon Tunnel Oxides for Transparent Passivated Contacts in Crystalline Silicon Solar Cells.

PubMed

Köhler, Malte; Pomaska, Manuel; Lentz, Florian; Finger, Friedhelm; Rau, Uwe; Ding, Kaining

2018-05-02

Transparent passivated contacts (TPCs) using a wide band gap microcrystalline silicon carbide (μc-SiC:H(n)), silicon tunnel oxide (SiO 2 ) stack are an alternative to amorphous silicon-based contacts for the front side of silicon heterojunction solar cells. In a systematic study of the μc-SiC:H(n)/SiO 2 /c-Si contact, we investigated selected wet-chemical oxidation methods for the formation of ultrathin SiO 2 , in order to passivate the silicon surface while ensuring a low contact resistivity. By tuning the SiO 2 properties, implied open-circuit voltages of 714 mV and contact resistivities of 32 mΩ cm 2 were achieved using μc-SiC:H(n)/SiO 2 /c-Si as transparent passivated contacts.

Flexural plate wave devices fabricated from silicon carbide membrane

NASA Astrophysics Data System (ADS)

Diagne, Ndeye Fama

Flexural Plate Wave (FPW) devices fabricated from Silicon Carbide (SiC) membranes are presented here which exhibit electrical and mechanical characteristics in its transfer functions that makes it very useful as a low voltage probe device capable of functioning in small areas that are commonly inaccessible to ordinary devices. The low input impedance characteristic of this current driven device makes it possible for it to operate at very low voltages, thereby reducing the hazards for flammable or explosive areas to be probed. The Flexural Plate Wave (FPW) devices are of a family of gravimetric type sensors that permit direct measurements of the mass of the vibrating element. The primary objective was to study the suitability of Silicon Carbide (SiC) membranes as a replacement of Silicon Nitride (SiN) membrane in flexural plate wave devices developed by Sandia National Laboratories. Fabrication of the Flexural Plate Wave devices involves the overlaying a silicon wafer with membranes of 3C-SiC thin film upon which conducting meander lines are placed. The input excitation energy is in the form of an input current. The lines of current along the direction of the conducting Meander Lines Transducer (MLTs) and the applied perpendicular external magnetic field set up a mechanical wave perpendicular to both, exciting the membrane by means of a Lorentz force, which in turn sets up flexural waves that propagate along the thin membrane. The physical dimensions, the mass density, the tension in the membrane and the meander spacing are physical characteristics that determine resonance frequency of the Flexural Plate Wave (FPW) device. Of primary interest is the determination of the resonant frequency of the silicon carbide membrane as functions of the device physical characteristic parameters. The appropriate transduction scheme with Meander Line Transducers (IDTs) are used to excite the membrane. Equivalent circuit models characterizing the reflection response S11 (amplitude

Forward-bias diode parameters, electronic noise, and photoresponse of graphene/silicon Schottky junctions with an interfacial native oxide layer

NASA Astrophysics Data System (ADS)

An, Yanbin; Behnam, Ashkan; Pop, Eric; Bosman, Gijs; Ural, Ant

2015-09-01

Metal-semiconductor Schottky junction devices composed of chemical vapor deposition grown monolayer graphene on p-type silicon substrates are fabricated and characterized. Important diode parameters, such as the Schottky barrier height, ideality factor, and series resistance, are extracted from forward bias current-voltage characteristics using a previously established method modified to take into account the interfacial native oxide layer present at the graphene/silicon junction. It is found that the ideality factor can be substantially increased by the presence of the interfacial oxide layer. Furthermore, low frequency noise of graphene/silicon Schottky junctions under both forward and reverse bias is characterized. The noise is found to be 1/f dominated and the shot noise contribution is found to be negligible. The dependence of the 1/f noise on the forward and reverse current is also investigated. Finally, the photoresponse of graphene/silicon Schottky junctions is studied. The devices exhibit a peak responsivity of around 0.13 A/W and an external quantum efficiency higher than 25%. From the photoresponse and noise measurements, the bandwidth is extracted to be ˜1 kHz and the normalized detectivity is calculated to be 1.2 ×109 cm Hz1/2 W-1. These results provide important insights for the future integration of graphene with silicon device technology.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

Solid oxide membrane (SOM) process for ytterbium and silicon production from their oxides

NASA Astrophysics Data System (ADS)

Jiang, Yihong

The Solid oxide membrane (SOM) electrolysis is an innovative green technology that produces technologically important metals directly from their respective oxides. A yttria-stabilized zirconia (YSZ) tube, closed at one end is employed to separate the molten salt containing dissolved metal oxides from the anode inside the YSZ tube. When the applied electric potential between the cathode in the molten salt and the anode exceeds the dissociation potential of the desired metal oxides, oxygen ions in the molten salt migrate through the YSZ membrane and are oxidized at the anode while the dissolved metal cations in the flux are reduced to the desired metal at the cathode. Compared with existing metal production processes, the SOM process has many advantages such as one unit operation, less energy consumption, lower capital costs and zero carbon emission. Successful implementation of the SOM electrolysis process would provide a way to mitigate the negative environmental impact of the metal industry. Successful demonstration of producing ytterbium (Yb) and silicon (Si) directly from their respective oxides utilizing the SOM electrolysis process is presented in this dissertation. During the SOM electrolysis process, Yb2O3 was reduced to Yb metal on an inert cathode. The melting point of the supporting electrolyte (LiF-YbF3-Yb2O3) was determined by differential thermal analysis (DTA). Static stability testing confirmed that the YSZ tube was stable with the flux at operating temperature. Yb metal deposit on the cathode was confirmed by scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy (EDS). During the SOM electrolysis process for silicon production, a fluoride based flux based on BaF2, MgF2, and YF3 was engineered to serve as the liquid electrolyte for dissolving silicon dioxide. YSZ tube was used to separate the molten salt from an anode current collector in the liquid silver. Liquid tin was chosen as cathode to dissolve the reduced silicon during

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Hemispherical cavities on silicon substrates: an overview of micro fabrication techniques

NASA Astrophysics Data System (ADS)

Poncelet, O.; Rasson, J.; Tuyaerts, R.; Coulombier, M.; Kotipalli, R.; Raskin, J.-P.; Francis, L. A.

2018-04-01

Hemispherical photonic crystals found in species like Papilio blumei and Cicendella chinensis have inspired new applications like anti-counterfeiting devices and gas sensors. In this work, we investigate and compare four different ways to micro fabricate such hemispherical cavities: using colloids as template, by wet (HNA) or dry (XeF2) isotropic etching of silicon and by electrochemical etching of silicon. The shape and the roughness of the obtained cavities have been discussed and the pros/cons for each method are highlighted.

Design and grayscale fabrication of beamfanners in a silicon substrate

NASA Astrophysics Data System (ADS)

Ellis, Arthur Cecil

2001-11-01

This dissertation addresses important first steps in the development of a grayscale fabrication process for multiple phase diffractive optical elements (DOS's) in silicon. Specifically, this process was developed through the design, fabrication, and testing of 1-2 and 1-4 beamfanner arrays for 5-micron illumination. The 1-2 beamfanner arrays serve as a test-of- concept and basic developmental step toward the construction of the 1-4 beamfanners. The beamfanners are 50 microns wide, and have features with dimensions of between 2 and 10 microns. The Iterative Annular Spectrum Approach (IASA) method, developed by Steve Mellin of UAH, and the Boundary Element Method (BEM) are the design and testing tools used to create the beamfanner profiles and predict their performance. Fabrication of the beamfanners required the techniques of grayscale photolithography and reactive ion etching (RIE). A 2-3micron feature size 1-4 silicon beamfanner array was fabricated, but the small features and contact photolithographic techniques available prevented its construction to specifications. A second and more successful attempt was made in which both 1-4 and 1-2 beamfanner arrays were fabricated with a 5-micron minimum feature size. Photolithography for the UAH array was contracted to MEMS-Optical of Huntsville, Alabama. A repeatability study was performed, using statistical techniques, of 14 photoresist arrays and the subsequent RIE process used to etch the arrays in silicon. The variance in selectivity between the 14 processes was far greater than the variance between the individual etched features within each process. Specifically, the ratio of the variance of the selectivities averaged over each of the 14 etch processes to the variance of individual feature selectivities within the processes yielded a significance level below 0.1% by F-test, indicating that good etch-to-etch process repeatability was not attained. One of the 14 arrays had feature etch-depths close enough to design

Fabrication of Silicon Nanobelts and Nanopillars by Soft Lithography for Hydrophobic and Hydrophilic Photonic Surfaces.

PubMed

Baquedano, Estela; Martinez, Ramses V; Llorens, José M; Postigo, Pablo A

2017-05-11

Soft lithography allows for the simple and low-cost fabrication of nanopatterns with different shapes and sizes over large areas. However, the resolution and the aspect ratio of the nanostructures fabricated by soft lithography are limited by the depth and the physical properties of the stamp. In this work, silicon nanobelts and nanostructures were achieved by combining soft nanolithography patterning with optimized reactive ion etching (RIE) in silicon. Using polymethylmethacrylate (PMMA) nanopatterned layers with thicknesses ranging between 14 and 50 nm, we obtained silicon nanobelts in areas of square centimeters with aspect ratios up to ~1.6 and linewidths of 225 nm. The soft lithographic process was assisted by a thin film of SiO x (less than 15 nm) used as a hard mask and RIE. This simple patterning method was also used to fabricate 2D nanostructures (nanopillars) with aspect ratios of ~2.7 and diameters of ~200 nm. We demonstrate that large areas patterned with silicon nanobelts exhibit a high reflectivity peak in the ultraviolet C (UVC) spectral region (280 nm) where some aminoacids and peptides have a strong absorption. We also demonstrated how to tailor the aspect ratio and the wettability of these photonic surfaces (contact angles ranging from 8.1 to 96.2°) by changing the RIE power applied during the fabrication process.

Fabrication of tri metal oxides gas detector for lung inflammation

NASA Astrophysics Data System (ADS)

Othman, Farhad M.; Abdul-Hamead, Alaa A.; Aljanabi, Zena A.

2018-05-01

This paper describes the use of semiconductor gas sensor for detection of Carbon monoxide levels in exhaled human breath serving as breath marker of lung inflammation. In this research tri metal oxides were fabricated by simple chemical spray pyrolysis technique from mixtures of tow composition (Na2WO4: SnCl2 and Na2WO4, : 3 SnCl2) salts at concentration (0.1M), were fabricated on silicon substrate n-type (100) with thickness was about (625 µm) using water soluble as precursors at a substrate temperature (350 °C ±5), with spray distance (25 cm) and their gas sensing properties toward Carbon monoxide gas at concentration (10) ppm in air were investigated at room temperature, furthermore structural and morphology properties were inspecting. Experimental results show that the WSnO4 and SnO2 thin films were achieved from the used salts with thickness about (0.2 ± 0.05 nm), which make the sensor suitable for the detection of carbon monoxide levels in in exhaled human breath.

Design, fabrication, and measurement of two silicon-based ultraviolet and blue-extended photodiodes

NASA Astrophysics Data System (ADS)

Chen, Changping; Wang, Han; Jiang, Zhenyu; Jin, Xiangliang; Luo, Jun

2014-12-01

Two silicon-based ultraviolet (UV) and blue-extended photodiodes are presented, which were fabricated for light detection in the ultraviolet/blue spectral range. Stripe-shaped and octagon-ring-shaped structures were designed to verify parameters of the UV-responsivity, UV-selectivity, breakdown voltage, and response time. The ultra-shallow lateral pn junction had been successfully realized in a standard 0.5-μm complementary metal oxide semiconductor (CMOS) process to enlarge the pn junction area, enhance the absorption of UV light, and improve the responsivity and quantum efficiency. The test results illustrated that the stripe-shaped structure has the lower breakdown voltage, higher UV-responsicity, and higher UV-selectivity. But the octagon-ring-shaped structure has the lower dark current. The response time of both structures was almost the same.

Ultra-thin alumina and silicon nitride MEMS fabricated membranes for the electron multiplication

NASA Astrophysics Data System (ADS)

Prodanović, V.; Chan, H. W.; Graaf, H. V. D.; Sarro, P. M.

2018-04-01

In this paper we demonstrate the fabrication of large arrays of ultrathin freestanding membranes (tynodes) for application in a timed photon counter (TiPC), a novel photomultiplier for single electron detection. Low pressure chemical vapour deposited silicon nitride (Si x N y ) and atomic layer deposited alumina (Al2O3) with thicknesses down to only 5 nm are employed for the membrane fabrication. Detailed characterization of structural, mechanical and chemical properties of the utilized films is carried out for different process conditions and thicknesses. Furthermore, the performance of the tynodes is investigated in terms of secondary electron emission, a fundamental attribute that determines their applicability in TiPC. Studied features and presented fabrication methods may be of interest for other MEMS application of alumina and silicon nitride as well, in particular where strong ultra-thin membranes are required.

Functionalization of 2D macroporous silicon under the high-pressure oxidation

NASA Astrophysics Data System (ADS)

Karachevtseva, L.; Kartel, M.; Kladko, V.; Gudymenko, O.; Bo, Wang; Bratus, V.; Lytvynenko, O.; Onyshchenko, V.; Stronska, O.

2018-03-01

Addition functionalization after high-pressure oxidation of 2D macroporous silicon structures is evaluated. X-ray diffractometry indicates formation of orthorhombic SiO2 phase on macroporous silicon at oxide thickness of 800-1200 nm due to cylindrical symmetry of macropores and high thermal expansion coefficient of SiO2. Pb center concentration grows with the splitting energy of LO- and TO-phonons and SiO2 thickness in oxidized macroporous silicon structures. This increase EPR signal amplitude and GHz radiation absorption and is promising for development of high-frequency devices and electronically controlled elements.

Synthesis of silicone softener and its characteristics on cotton fabric.

PubMed

Robati, D

2007-02-15

This study was undertaken to examine the unresolved questions surrounding the influence of silicon softener on cotton fabrics. Results showed that the synthesized silicon softener was comparable with other tested conventional softener, According to present investigations the emulsions E1 and E2 is not economical and it is not evenly qualified and it become two phased after 24 h. But emulsion E3 was even and more economical. Moreover, it has high stability. In addition, measurement of kinetic and static friction show that the general effect of silicon softener on cotton cloth is the decrease of friction. Also, it was concluded that with increasing the add on percentage of softener, the crease of reflection angle did not change bending length and static and kinetic friction index significantly.

Fabrication and characterization of resonant SOI micromechanical silicon sensors based on DRIE micromachining, freestanding release process and silicon direct bonding

NASA Astrophysics Data System (ADS)

Gigan, Olivier; Chen, Hua; Robert, Olivier; Renard, Stephane; Marty, Frederic

2002-11-01

This paper is dedicated to the fabrication and technological aspect of a silicon microresonator sensor. The entire project includes the fabrication processes, the system modelling/simulation, and the electronic interface. The mechanical model of such resonator is presented including description of frequency stability and Hysterises behaviour of the electrostatically driven resonator. Numeric model and FEM simulations are used to simulate the system dynamic behaviour. The complete fabrication process is based on standard microelectronics technology with specific MEMS technological steps. The key steps are described: micromachining on SOI by Deep Reactive Ion Etching (DRIE), specific release processes to prevent sticking (resist and HF-vapour release process) and collective vacuum encapsulation by Silicon Direct Bonding (SDB). The complete process has been validated and prototypes have been fabricated. The ASIC was designed to interface the sensor and to control the vibration amplitude. This electronic was simulated and designed to work up to 200°C and implemented in a standard 0.6μ CMOS technology. Characterizations of sensor prototypes are done both mechanically and electrostatically. These measurements showed good agreements with theory and FEM simulations.

Fabrication and characterization of active nanostructures

NASA Astrophysics Data System (ADS)

Opondo, Noah F.

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface. A micro-vacuum electron device based on silicon field emitters for cold cathode emission is also presented. The presented work utilizes vertical Si nanowires fabricated by means of self-assembly, standard lithography and etching techniques as field emitters in this dissertation. To obtain a high nanowire density, hence a high current density, a simple and inexpensive Langmuir Blodgett technique

Fabricating and Controlling Silicon Zigzag Nanowires by Diffusion-Controlled Metal-Assisted Chemical Etching Method.

PubMed

Chen, Yun; Zhang, Cheng; Li, Liyi; Tuan, Chia-Chi; Wu, Fan; Chen, Xin; Gao, Jian; Ding, Yong; Wong, Ching-Ping

2017-07-12

Silicon (Si) zigzag nanowires (NWs) have a great potential in many applications because of its high surface/volume ratio. However, fabricating Si zigzag NWs has been challenging. In this work, a diffusion-controlled metal-assisted chemical etching method is developed to fabricate Si zigzag NWs. By tailoring the composition of etchant to change its diffusivity, etching direction, and etching time, various zigzag NWs can be easily fabricated. In addition, it is also found that a critical length of NW (>1 μm) is needed to form zigzag nanowires. Also, the amplitude of zigzag increases as the location approaches the center of the substrate and the length of zigzag nanowire increases. It is also demonstrated that such zigzag NWs can help the silicon substrate for self-cleaning and antireflection. This method may provide a feasible and economical way to fabricate zigzag NWs and novel structures for broad applications.

Fabrication of a 20.5-inch-diameter segmented silicon annular optic prototype for the ROMA program

NASA Astrophysics Data System (ADS)

Hassell, Frank R.; Groark, Frank M.

1995-10-01

Recent advancements in single crystal silicon material science and fabrication capabilities and very low absorption (VLA) multi-layer dielectric coating technology have led to the development of uncooled, large aperture, high power mirrors for high energy laser (HEL) systems. Based on this success, a segmented single-crystal silicon substrate concept has been selected as the baseline fabrication approach for uncooled 1.2 meter diameter resonator annular optics for the Alpha space based high energy laser. The objective of this Resonator Optics Materials Assessment (ROMA) task was to demonstrate all of the key fabrication processes required to fabricate the full sized annular optics for the Alpha space based high energy laser. This paper documents the fabrication of a half-scale annular optic prototype (AOP) of the Alpha laser rear cone.

Design, fabrication and test of prototype furnace for continuous growth of wide silicon ribbon

NASA Technical Reports Server (NTRS)

Duncan, C. S.; Seidensticker, R. G.

1975-01-01

Progress is reported during the apparatus design, fabrication, and assembly phases of a program to grow wide, thin silicon dendritic web. The growth facility was essentially completed with any significant problems arising. A complete set of detailed fabrication drawings is included as an appendix.

High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures.

PubMed

Liu, Yuan; Sheng, Jiming; Wu, Hao; He, Qiyuan; Cheng, Hung-Chieh; Shakir, Muhammad Imran; Huang, Yu; Duan, Xiangfeng

2016-06-01

Scalable fabrication of vertical-tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm(-2) . This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene-silicon heterostructures. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Arsenic silicide formation by oxidation of arsenic implanted silicon

NASA Astrophysics Data System (ADS)

Hagmann, D.; Euen, W.; Schorer, G.; Metzger, G.

1989-07-01

Wet oxidations of (100) silicon implanted with an arsenic dose of 2 × 1016 cm-2 and an energy of 30 keV were carried out in the temperature range between 600 and 900° C. The oxidation rate is increased on the arsenic implanted samples up to a factor of 2000 as compared to undoped samples. During these oxidations the arsenic suicide phase AsSi is precipitated at the oxide/silicon interface. After short oxidation times at 600° C, a continuous AsSi layer is found. It is dissolved during extended oxidation times and finally almost all As is incorporated in the oxide. After 900° C oxidations, substantial AsSi crystallites remain at the Si/SiO2 interface. They are still observed up to the larg-est oxide thickness grown (2.3 µm). The AsSi phase and the distribution of the im-planted arsenic were analyzed by TEM, SIMS and XRF measurements.

Silicon Nanowire Fabric as a Lithium Ion Battery Electrode Material

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chockla, Aaron M.; Harris, Justin T.; Akhavan, Vahid A.

2011-11-09

A nonwoven fabric with paperlike qualities composed of silicon nanowires is reported. The nanowires, made by the supercritical-fluid–liquid–solid process, are crystalline, range in diameter from 10 to 50 nm with an average length of >100 μm, and are coated with a thin chemisorbed polyphenylsilane shell. About 90% of the nanowire fabric volume is void space. Thermal annealing of the nanowire fabric in a reducing environment converts the polyphenylsilane coating to a carbonaceous layer that significantly increases the electrical conductivity of the material. This makes the nanowire fabric useful as a self-supporting, mechanically flexible, high-energy-storage anode material in a lithium ionmore » battery. Anode capacities of more than 800 mA h g{sup –1} were achieved without the addition of conductive carbon or binder.« less

Synthesis of metal silicide at metal/silicon oxide interface by electronic excitation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, J.-G., E-mail: jglee36@kims.re.kr; Nagase, T.; Yasuda, H.

The synthesis of metal silicide at the metal/silicon oxide interface by electronic excitation was investigated using transmission electron microscopy. A platinum silicide, α-Pt{sub 2}Si, was successfully formed at the platinum/silicon oxide interface under 25–200 keV electron irradiation. This is of interest since any platinum silicide was not formed at the platinum/silicon oxide interface by simple thermal annealing under no-electron-irradiation conditions. From the electron energy dependence of the cross section for the initiation of the silicide formation, it is clarified that the silicide formation under electron irradiation was not due to a knock-on atom-displacement process, but a process induced by electronic excitation.more » It is suggested that a mechanism related to the Knotek and Feibelman mechanism may play an important role in silicide formation within the solid. Similar silicide formation was also observed at the palladium/silicon oxide and nickel/silicon oxide interfaces, indicating a wide generality of the silicide formation by electronic excitation.« less

Compact silicon diffractive sensor: design, fabrication, and prototype.

PubMed

Maikisch, Jonathan S; Gaylord, Thomas K

2012-07-01

An in-plane constant-efficiency variable-diffraction-angle grating and an in-plane high-angular-selectivity grating are combined to enable a new compact silicon diffractive sensor. This sensor is fabricated in silicon-on-insulator and uses telecommunications wavelengths. A single sensor element has a micron-scale device size and uses intensity-based (as opposed to spectral-based) detection for increased integrability. In-plane diffraction gratings provide an intrinsic splitting mechanism to enable a two-dimensional sensor array. Detection of the relative values of diffracted and transmitted intensities is independent of attenuation and is thus robust. The sensor prototype measures refractive index changes of 10(-4). Simulations indicate that this sensor configuration may be capable of measuring refractive index changes three or four orders of magnitude smaller. The characteristics of this sensor type make it promising for lab-on-a-chip applications.

Silicon Satellites: Picosats, Nanosats, and Microsats

NASA Technical Reports Server (NTRS)

Janson, Siegfried W.

1995-01-01

Silicon, the most abundant solid element in the Earth's lithosphere, is a useful material for spacecraft construction. Silicon is stronger than stainless steel, has a thermal conductivity about half that of aluminum, is transparent to much of the infrared radiation spectrum, and can form a stable oxide. These unique properties enable silicon to become most of the mass of a satellite, it can simultaneously function as structure, heat transfer system, radiation shield, optics, and semiconductor substrate. Semiconductor batch-fabrication techniques can produce low-power digital circuits, low-power analog circuits, silicon-based radio frequency circuits, and micro-electromechanical systems (MEMS) such as thrusters and acceleration sensors on silicon substrates. By exploiting these fabrication techniques, it is possible to produce highly-integrated satellites for a number of applications. This paper analyzes the limitations of silicon satellites due to size. Picosatellites (approximately 1 gram mass), nanosatellites (about 1 kg mass), and highly capable microsatellites (about 10 kg mass) can perform various missions with lifetimes of a few days to greater than a decade.

Sliding Speed-Dependent Tribochemical Wear of Oxide-Free Silicon

NASA Astrophysics Data System (ADS)

Chen, Lei; Qi, Yaqiong; Yu, Bingjun; Qian, Linmao

2017-06-01

Fundamental understanding of tribochemical wear mechanism of oxide-free single crystalline silicon (without native oxide layer) is essential to optimize the process of ultra-precision surface manufacturing. Here, we report sliding speed-dependent nanowear of oxide-free silicon against SiO2 microspheres in air and in deionized water. When contact pressure is too low to induce Si yield, tribochemical wear occurs with the existence of water molecules and wear volume decreases logarithmically to constant as sliding speed increased. TEM and Raman observations indicate that the dynamics of rupture and reformation of interfacial bonding bridges result in the variation of tribochemical wear of the oxide-free Si with the increase of sliding speed.

22.5% efficient silicon heterojunction solar cell with molybdenum oxide hole collector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Geissbühler, Jonas, E-mail: jonas.geissbuehler@epfl.ch; Werner, Jérémie; Martin de Nicolas, Silvia

2015-08-24

Substituting the doped amorphous silicon films at the front of silicon heterojunction solar cells with wide-bandgap transition metal oxides can mitigate parasitic light absorption losses. This was recently proven by replacing p-type amorphous silicon with molybdenum oxide films. In this article, we evidence that annealing above 130 °C—often needed for the curing of printed metal contacts—detrimentally impacts hole collection of such devices. We circumvent this issue by using electrodeposited copper front metallization and demonstrate a silicon heterojunction solar cell with molybdenum oxide hole collector, featuring a fill factor value higher than 80% and certified energy conversion efficiency of 22.5%.

22.5% efficient silicon heterojunction solar cell with molybdenum oxide hole collector

DOE PAGES

Geissbühler, Jonas; Werner, Jérémie; Nicolas, Silvia Martin de; ...

2015-08-24

Substituting the doped amorphous silicon films at the front of silicon heterojunction solar cells with wide-bandgap transition metal oxides can mitigate parasitic light absorption losses. This was recently proven by replacing p-type amorphous silicon with molybdenum oxide films. In this article, we evidence that annealing above 130 °C—often needed for the curing of printed metal contacts—detrimentally impacts hole collection of such devices. Furthermore, we circumvent this issue by using electrodeposited copper front metallization and demonstrate a silicon heterojunction solar cell with molybdenum oxide hole collector, featuring a fill factor value higher than 80% and certified energy conversion efficiency of 22.5%.

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Waveguide silicon nitride grating coupler

NASA Astrophysics Data System (ADS)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

Ion irradiation of the native oxide/silicon surface increases the thermal boundary conductance across aluminum/silicon interfaces

NASA Astrophysics Data System (ADS)

Gorham, Caroline S.; Hattar, Khalid; Cheaito, Ramez; Duda, John C.; Gaskins, John T.; Beechem, Thomas E.; Ihlefeld, Jon F.; Biedermann, Laura B.; Piekos, Edward S.; Medlin, Douglas L.; Hopkins, Patrick E.

2014-07-01

The thermal boundary conductance across solid-solid interfaces can be affected by the physical properties of the solid boundary. Atomic composition, disorder, and bonding between materials can result in large deviations in the phonon scattering mechanisms contributing to thermal boundary conductance. Theoretical and computational studies have suggested that the mixing of atoms around an interface can lead to an increase in thermal boundary conductance by creating a region with an average vibrational spectra of the two materials forming the interface. In this paper, we experimentally demonstrate that ion irradiation and subsequent modification of atoms at solid surfaces can increase the thermal boundary conductance across solid interfaces due to a change in the acoustic impedance of the surface. We measure the thermal boundary conductance between thin aluminum films and silicon substrates with native silicon dioxide layers that have been subjected to proton irradiation and post-irradiation surface cleaning procedures. The thermal boundary conductance across the Al/native oxide/Si interfacial region increases with an increase in proton dose. Supported with statistical simulations, we hypothesize that ion beam mixing of the native oxide and silicon substrate within ˜2.2nm of the silicon surface results in the observed increase in thermal boundary conductance. This ion mixing leads to the spatial gradation of the silicon native oxide into the silicon substrate, which alters the acoustic impedance and vibrational characteristics at the interface of the aluminum film and native oxide/silicon substrate. We confirm this assertion with picosecond acoustic analyses. Our results demonstrate that under specific conditions, a "more disordered and defected" interfacial region can have a lower resistance than a more "perfect" interface.

Fe3O4–Silicone Mixture as Flexible Actuator

PubMed Central

Song, Kahye

2018-01-01

In this study, we introduce Fe3O4-silicone flexible composite actuators fabricated by combining silicone and iron oxide particles. The actuators exploit the flexibility of silicone and the electric conductivity of iron oxide particles. These actuators are activated by electrostatic force using the properties of the metal particles. Herein, we investigate the characteristic changes in actuation performance by increasing the concentration of iron oxide from 1% to 20%. The developed flexible actuators exhibit a resonant frequency near 3 Hz and their actuation amplitudes increase with increasing input voltage. We found that the actuator can move well at metal particle concentrations >2.5%. We also studied the changes in actuation behavior, depending on the portion of the Fe3O4-silicone in the length. Overall, we experimentally analyzed the characteristics of the newly proposed metal particle-silicone composite actuators. PMID:29738466

Sponge-like reduced graphene oxide/silicon/carbon nanotube composites for lithium ion batteries

NASA Astrophysics Data System (ADS)

Fang, Menglu; Wang, Zhao; Chen, Xiaojun; Guan, Shiyou

2018-04-01

Three-dimensional sponge-like reduced graphene oxide/silicon/carbon nanotube composites were synthesized by one-step hydrothermal self-assembly using silicon nanoparticles, graphene oxide and amino modified carbon nanotubes to develop high-performance anode materials of lithium ion batteries. Scanning electron microscopy and transmission electron microscopy images show the structure of composites that Silicon nanoparticles are coated with reduced graphene oxide while amino modified carbon nanotubes wrap around the reduced graphene oxide in the composites. When applied to lithium ion battery, these composites exhibit high initial specific capacity of 2552 mA h/g at a current density of 0.05 A/g. In addition, reduced graphene oxide/silicon/carbon nanotube composites also have better cycle stability than bare Silicon nanoparticles electrode with the specific capacity of 1215 mA h/g after 100 cycles. The three-dimension sponge-like structure not only ensures the electrical conductivity but also buffers the huge volume change, which has broad potential application in the field of battery.

Preparation of rich handles soft cellulosic fabric using amino silicone based softener. Part-I: Surface smoothness and softness properties.

PubMed

Zia, Khalid Mahmood; Tabassum, Shazia; Barkaat-ul-Hasin, Syed; Zuber, Mohammad; Jamil, Tahir; Jamal, Muhammad Asghar

2011-04-01

A series of amino silicone based softeners with different emulsifiers were prepared and adsorbed onto the surfaces of cotton and blends of cotton/polyester fabrics. Factors affecting the performance properties of the finished substrate such as post-treatment with amino functional silicone based softener varying different emulsifiers in their formulations and its concentration on different processed fabrics were studied. Fixation of the amino-functional silicone softener onto/or within the cellulose structure is accompanied by the formation of semi-inter-penetrated network structure thereby enhancing both the extent of crosslinking and networking as well as providing very high softness. The results of the experiments indicate that the amino silicone can form a hydrophobic film on both cotton and blends of cotton/polyester fabrics and its coating reduces the surface roughness significantly. Furthermore, the roughness becomes lesser with an increase in the applied strength of amino silicone based softener. Copyright © 2011 Elsevier B.V. All rights reserved.

A novel method to fabricate silicon tubular gratings with broadband antireflection and super-hydrophobicity.

PubMed

Gao, Yang; Shi, Tielin; Tan, Xianhua; Liao, Guanglan

2014-06-01

We have developed a novel method to fabricate micro/nano structure based on the coherent diffraction lithography, and acquired periodic silicon tubular gratings with deep nano-scale tapered profiles at the top part. The optical properties of these tubular gratings were similar to an effective gradient-index antireflective surface, resulting in a broadband antireflective combining super-hydrophobic behavior. The mechanism of the method was simulated by rigorous coupled wave analysis algorithms. Then coherent diffraction lithography by use of suitable mask, in which periodic micro-scale circular opaque patters were distributed, was realized on the traditional aligner. Due to coherent diffraction, we obtained enough light intensity for photoresist exposure under the center of the opaque area in the mask together with transparent areas. The tapered line profiles and hollow photoresist gratings over large areas could be fabricated on the silicon wafer after development. The dry etching process was carried out, and high aspect ratio silicon tubular gratings with deep tapered profiles at the top were fabricated. The optical property and wettability of the structure were verified, proving that the proposed method and obtained micro/nano structure provide application potential in the future.

Fabrication of Large Lateral Polycrystalline Silicon Film by Laser Dehydrogenation and Lateral Crystallization of Hydrogenated Nanocrystalline Silicon Films

NASA Astrophysics Data System (ADS)

Sato, Tadashi; Yamamoto, Kenichi; Kambara, Junji; Kitahara, Kuninori; Hara, Akito

2009-12-01

Hydrogenated nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) have attracted attention for application to the operation of organic light-emitting diodes (OLEDs). The monolithic integration of nc-Si:H TFTs and polycrystalline silicon (poly-Si) TFTs and the use of nc-Si:H TFTs for operating an OLED are candidate technologies to achieve OLED system-on-glass. To develop such a system, it is necessary to fabricate poly-Si films without employing thermal dehydrogenation because hydrogen needs to be maintained in the channel region of nc-Si:H TFTs. In this study, we optimized the laser dehydrogenation process as a substitute for thermal dehydrogenation by using a diode-pumped solid-state continuous-wave green laser (Nd:YVO4, 2ω=532 nm) to fabricate large lateral poly-Si films with grain sizes of 3×20 µm2. The performance of poly-Si TFTs is well known to be sensitive to the quality of poly-Si films. In order to evaluate the electrical properties of poly-Si films, TFTs were fabricated by conventional processes. The field-effect mobility, threshold voltage, and S-value of the poly-Si TFTs were 220 cm2 V-1 s-1, -1.0 V, and 0.45 V/dec, respectively. The quality of the poly-Si film fabricated in this experiment was sufficiently high for the integration of peripheral circuits.

Synthesis of silicon nanotubes with cobalt silicide ends using anodized aluminum oxide template.

PubMed

Zhang, Zhang; Liu, Lifeng; Shimizu, Tomohiro; Senz, Stephan; Gösele, Ulrich

2010-02-05

Silicon nanotubes (SiNTs) are compatible with Si-based semiconductor technology. In particular, the small diameters and controllable structure of such nanotubes are remaining challenges. Here we describe a method to fabricate SiNTs intrinsically connected with cobalt silicide ends based on highly ordered anodic aluminum oxide (AAO) templates. Size and growth direction of the SiNTs can be well controlled via the templates. The growth of SiNTs is catalyzed by the Co nanoparticles reduced on the pore walls of the AAO after annealing, with a controllable thickness at a given growth temperature and time. Simultaneously, cobalt silicide forms on the bottom side of the SiNTs.

Covalent Surface Modification of Silicon Oxides with Alcohols in Polar Aprotic Solvents.

PubMed

Lee, Austin W H; Gates, Byron D

2017-09-05

Alcohol-based monolayers were successfully formed on the surfaces of silicon oxides through reactions performed in polar aprotic solvents. Monolayers prepared from alcohol-based reagents have been previously introduced as an alternative approach to covalently modify the surfaces of silicon oxides. These reagents are readily available, widely distributed, and are minimally susceptible to side reactions with ambient moisture. A limitation of using alcohol-based compounds is that previous reactions required relatively high temperatures in neat solutions, which can degrade some alcohol compounds or could lead to other unwanted side reactions during the formation of the monolayers. To overcome these challenges, we investigate the condensation reaction of alcohols on silicon oxides carried out in polar aprotic solvents. In particular, propylene carbonate has been identified as a polar aprotic solvent that is relatively nontoxic, readily accessible, and can facilitate the formation of alcohol-based monolayers. We have successfully demonstrated this approach for tuning the surface chemistry of silicon oxide surfaces with a variety of alcohol containing compounds. The strategy introduced in this research can be utilized to create silicon oxide surfaces with hydrophobic, oleophobic, or charged functionalities.

Performance characteristics of supercapacitor electrodes made of silicon carbide nanowires grown on carbon fabric

NASA Astrophysics Data System (ADS)

Gu, Lin; Wang, Yewu; Fang, Yanjun; Lu, Ren; Sha, Jian

2013-12-01

In this paper, we report the supercapacitor electrodes with excellent cycle stability, which are made of silicon carbide nanowires (SiC NWs) grown on flexible carbon fabric. A high areal capacitance of 23 mF cm-2 is achieved at a scan rate of 50 mV s-1 at room temperature and capacitances increase with the rise of the working temperature. Owing to the excellent thermal stability of SiC NWs and carbon fabric, no observable decrease of capacitance occurs at room temperature (20 °C) after 105 cycles, which satisfies the demands of the commercial applications. Further increasing the measurement temperature to 60 °C, 90% of the initial capacitance is still retained after 105 cycles. This study shows that silicon carbide nanowires on carbon fabric are a promising electrode material for high temperature and stable micro-supercapacitors.

High-temperature oxidation behavior of reaction-formed silicon carbide ceramics

NASA Technical Reports Server (NTRS)

Ogbuji, Linus U. J. T.; Singh, M.

1995-01-01

The oxidation behavior of reaction-formed silicon carbide (RFSC) ceramics was investigated in the temperature range of 1100 to 1400 C. The oxidation weight change was recorded by TGA; the oxidized materials were examined by light and electron microscopy, and the oxidation product by x-ray diffraction analysis (XRD). The materials exhibited initial weight loss, followed by passive weight gain (with enhanced parabolic rates, k(sub p)), and ending with a negative (logarithmic) deviation from the parabolic law. The weight loss arose from the oxidation of residual carbon, and the enhanced k(sub p) values from internal oxidation and the oxidation of residual silicon, while the logarithmic kinetics is thought to have resulted from crystallization of the oxide. The presence of a small amount of MoSi, in the RFSC material caused a further increase in the oxidation rate. The only solid oxidation product for all temperatures studied was silica.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Fabrication and single-electron-transfer operation of a triple-dot single-electron transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Mingyu, E-mail: mingyujo@eis.hokudai.ac.jp; Uchida, Takafumi; Tsurumaki-Fukuchi, Atsushi

2015-12-07

A triple-dot single-electron transistor was fabricated on silicon-on-insulator wafer using pattern-dependent oxidation. A specially designed one-dimensional silicon wire having small constrictions at both ends was converted to a triple-dot single-electron transistor by means of pattern-dependent oxidation. The fabrication of the center dot involved quantum size effects and stress-induced band gap reduction, whereas that of the two side dots involved thickness modulation because of the complex edge structure of two-dimensional silicon. Single-electron turnstile operation was confirmed at 8 K when a 100-mV, 1-MHz square wave was applied. Monte Carlo simulations indicated that such a device with inhomogeneous tunnel and gate capacitances canmore » exhibit single-electron transfer.« less

Travelling wave resonators fabricated with low-loss hydrogenated amorphous silicon

NASA Astrophysics Data System (ADS)

Lipka, Timo; Amthor, Julia; Trieu, Hoc Khiem; Müller, Jörg

2013-05-01

Low-loss hydrogenated amorphous silicon is employed for the fabrication of various planar integrated travelling wave resonators. Microring, racetrack, and disk resonators of different dimensions were fabricated with CMOS-compatible processes and systematically investigated. The key properties of notch filter ring resonators as extinction ratio, Q-factor, free spectral range, and the group refractive index were determined for resonators of varying radius, thereby achieving critically coupled photonic systems with high extinction ratios of about 20 dB for both polarizations. Racetrack resonators that are arranged in add/drop configuration and high quality factor microdisk resonators were optically characterized, with the microdisks exhibiting Q-factors of greater than 100000. Four-channel add/drop wavelength-division multiplexing filters that are based on cascaded racetrack resonators are studied. The design, the fabrication, and the optical characterization are presented.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

NASA Astrophysics Data System (ADS)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

The microstructure of laterally seeded silicon-on-oxide

NASA Astrophysics Data System (ADS)

Pinizzotto, R. F.; Lam, H. W.; Vaandrager, B. L.

1982-03-01

The production of large scale integrated circuits in thin silicon films on insulating substrates is currently of much interest in the electronics industry. One of the most promising techniques of forming this composite structure is by lateral seeding. We have used optical microscopy and transmission electron microscopy to characterize the microstructure of silicon-on-oxide formed by scanning CW laser induced lateral epitaxy. The primary defects are dislocations. Dislocation rearrangement leads to the formation of both small angle boundaries (stable, regular dislocation arrays) and grain boundaries. The grains were found to be misoriented to the <100> direction perpendicular to the film plane by ≤ 4° and to the <100> directions in the plane of the film by ≤ 2°. Internal reflection twins are a common defect. Microtwinning was found to occur at the vertical step caused by the substrate-oxide interface if the substrate to oxide step height was > 120 nm. The microstructure is continuous across successive scan lines. Microstructural defects are found to initiate at the same topographical location in different oxide pads. We propose that this is due to the meeting of two crystallization growth fronts. The liquid silicon between the fronts causes large stresses in this area because of the 9% volume increase during solidification. The defects observed in the bulk may form by a similar mechanism or by dislocation generation at substrate-oxide interface irregularities. The models predict that slower growth leads to improved material quality. This has been observed experimentally.

The Active Oxidation of Silicon Carbide

NASA Technical Reports Server (NTRS)

Jacobson, Nathan S.; Myers, Dwight L.

2009-01-01

The high temperature oxidation of silicon carbide occurs in two very different modes. Passive oxidation forms a protective oxide film which limits further attack of the SiC: SiC(s) + 3/2 O2(g) = SiO2(s) + CO(g) Active oxidation forms a volatile oxide and may lead to extensive attack of the SiC: SiC(s) + O2(g) = SiO(g) + CO(g) Generally passive oxidation occurs at higher oxidant pressures and active oxidation occurs at lower oxidant pressures and elevated temperatures. Active oxidation is a concern for reentry, where the flight trajectory involves the latter conditions. Thus the transition points and rates of active oxidation are a major concern. Passive/active transitions have been studied by a number of investigators. An examination of the literature indicates many questions remain regarding the effect of impurity, the hysteresis of the transition (i.e. the difference between active-to-passive and passive-toactive), and the effect of total pressure. In this study we systematically investigate each of these effects. Experiments were done in both an alumina furnace tube and a quartz furnace tube. It is known that alumina tubes release impurities such as sodium and increase the kinetics in the passive region [1]. We have observed that the active-to-passive transition occurs at a lower oxygen pressure when the experiment is conducted in alumina tubes and the resultant passive silica scale contains sodium. Thus the tests in this study are conducted in quartz tubes. The hysteresis of the transition has been discussed in the detail in the original theoretical treatise of this problem for pure silicon by Wagner [2], yet there is little mention of it in subsequent literature. Essentially Wagner points out that the active-to-passive transition is governed by the criterion for a stable Si/SiO2 equilibria and the passive-to-active transition is governed by the decomposition of the SiO2 film. A series of experiments were conducted for active-to-passive and passive

Micrometer-scale fabrication of complex three dimensional lattice + basis structures in silicon

DOE PAGES

Burckel, D. Bruce; Resnick, Paul J.; Finnegan, Patrick S.; ...

2015-01-01

A complementary metal oxide semiconductor (CMOS) compatible version of membrane projection lithography (MPL) for fabrication of micrometer-scale three-dimensional structures is presented. The approach uses all inorganic materials and standard CMOS processing equipment. In a single layer, MPL is capable of creating all 5 2D-Bravais lattices. Furthermore, standard semiconductor processing steps can be used in a layer-by-layer approach to create fully three dimensional structures with any of the 14 3D-Bravais lattices. The unit cell basis is determined by the projection of the membrane pattern, with many degrees of freedom for defining functional inclusions. Here we demonstrate several unique structural motifs, andmore » characterize 2D arrays of unit cells with split ring resonators in a silicon matrix. The structures exhibit strong polarization dependent resonances and, for properly oriented split ring resonators (SRRs), coupling to the magnetic field of a normally incident transverse electromagnetic wave, a response unique to 3D inclusions.« less

Improved reaction sintered silicon nitride. [protective coatings to improve oxidation resistance

NASA Technical Reports Server (NTRS)

Baumgartner, H. R.

1978-01-01

Processing treatments were applied to as-nitrided reaction sintered silicon nitride (RSSN) with the purposes of improving strength after processing to above 350 MN/m2 and improving strength after oxidation exposure. The experimental approaches are divided into three broad classifications: sintering of surface-applied powders; impregnation of solution followed by further thermal processing; and infiltration of molten silicon and subsequent carburization or nitridation of the silicon. The impregnation of RSSN with solutions of aluminum nitrate and zirconyl chloride, followed by heating at 1400-1500 C in a nitrogen atmosphere containing silicon monoxide, improved RSSN strength and oxidation resistance. The room temperature bend strength of RSSN was increased nearly fifty percent above the untreated strength with mean absolute strengths up to 420 MN/m2. Strengths of treated samples that were measured after a 12 hour oxidation exposure in air were up to 90 percent of the original as-nitrided strength, as compared to retained strengths in the range of 35 to 60 percent for untreated RSSN after the same oxidation exposure.

Rapid Covalent Modification of Silicon Oxide Surfaces through Microwave-Assisted Reactions with Alcohols.

PubMed

Lee, Austin W H; Gates, Byron D

2016-07-26

We demonstrate the method of a rapid covalent modification of silicon oxide surfaces with alcohol-containing compounds with assistance by microwave reactions. Alcohol-containing compounds are prevalent reagents in the laboratory, which are also relatively easy to handle because of their stability against exposure to atmospheric moisture. The condensation of these alcohols with the surfaces of silicon oxides is often hindered by slow reaction kinetics. Microwave radiation effectively accelerates this condensation reaction by heating the substrates and/or solvents. A variety of substrates were modified in this demonstration, such as silicon oxide films of various thicknesses, glass substrates such as microscope slides (soda lime), and quartz. The monolayers prepared through this strategy demonstrated the successful formation of covalent surface modifications of silicon oxides with water contact angles of up to 110° and typical hysteresis values of 2° or less. An evaluation of the hydrolytic stability of these monolayers demonstrated their excellent stability under acidic conditions. The techniques introduced in this article were successfully applied to tune the surface chemistry of silicon oxides to achieve hydrophobic, oleophobic, and/or charged surfaces.

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Conformal coating of amorphous silicon and germanium by high pressure chemical vapor deposition for photovoltaic fabrics

NASA Astrophysics Data System (ADS)

Ji, Xiaoyu; Cheng, Hiu Yan; Grede, Alex J.; Molina, Alex; Talreja, Disha; Mohney, Suzanne E.; Giebink, Noel C.; Badding, John V.; Gopalan, Venkatraman

2018-04-01

Conformally coating textured, high surface area substrates with high quality semiconductors is challenging. Here, we show that a high pressure chemical vapor deposition process can be employed to conformally coat the individual fibers of several types of flexible fabrics (cotton, carbon, steel) with electronically or optoelectronically active materials. The high pressure (˜30 MPa) significantly increases the deposition rate at low temperatures. As a result, it becomes possible to deposit technologically important hydrogenated amorphous silicon (a-Si:H) from silane by a simple and very practical pyrolysis process without the use of plasma, photochemical, hot-wire, or other forms of activation. By confining gas phase reactions in microscale reactors, we show that the formation of undesired particles is inhibited within the microscale spaces between the individual wires in the fabric structures. Such a conformal coating approach enables the direct fabrication of hydrogenated amorphous silicon-based Schottky junction devices on a stainless steel fabric functioning as a solar fabric.

Research on silicon microchannel array oxidation insulation technology and stress issues

NASA Astrophysics Data System (ADS)

Chai, Jin; Li, Mo; Liang, Yong-zhao; Yang, Ji-kai; Wang, Guo-zheng; Duanmu, Qing-duo

2013-08-01

Microchannel plate is widely used in the field of low light level night vision, photomultiplier, tubes, X-ray enhancer and so on. In order to meet the requirement of microchannel plate electron multiplier, we used the method of thermal oxidation to produce a thin film of silicon dioxide which could play a role in electric insulation. Silicon dioxide film has a high breakdown voltage, it can satisfy the high breakdown voltage requirements of electron multiplier. We should find the reasonable parameter values and preparation process in the oxidation so that the thickness and uniformity of the silicon dioxide layer would meet requirement. This article has been focused on researching and analyzing of the problem of oxide insulation and thermal stress in the process of production of silicon dioxide film. In this experiment, dry oxygen and wet oxygen were carried out respectively for 8 hours. The thickness of dry oxygen silicon dioxide films was 458 nm and wet oxygen silicon dioxide films was 1.4 μm. Under these conditions, the silicon microchannel is uniformity and neat, meanwhile the insulating layer's breakdown voltage was measured at 450 V after the wet oxygen oxidation. By using ANSYS finite element software, we analyze the thermal stress, which came from the microchannel oxygen processes, under the conditions of which ambient temperature was 27 ℃ and porosity was 64%, we simulated the thermal stress in the temperature of 1200 ℃ and 1000 ℃, finally we got the maximum equivalent thermal stress of 472 MPa and 403 MPa respectively. The higher thermal stress area was spread over Si-SiO2 interface, by simulate conditions 50% porosity silicon microchannel sample was selected for simulation analysis at 1100 ℃, we got the maximum equivalent thermal stress of 472 MPa, Thermal stress is the minimum value of 410 MPa.

Silicon induced stability and mobility of indium zinc oxide based bilayer thin film transistors

NASA Astrophysics Data System (ADS)

Chauhan, Ram Narayan; Tiwari, Nidhi; Liu, Po-Tsun; Shieh, Han-Ping D.; Kumar, Jitendra

2016-11-01

Indium zinc oxide (IZO), silicon containing IZO, and IZO/IZO:Si bilayer thin films have been prepared by dual radio frequency magnetron sputtering on glass and SiO2/Si substrates for studying their chemical compositions and electrical characteristics in order to ascertain reliability for thin film transistor (TFT) applications. An attempt is therefore made here to fabricate single IZO and IZO/IZO:Si bilayer TFTs to study the effect of film thickness, silicon incorporation, and bilayer active channel on device performance and negative bias illumination stress (NBIS) stability. TFTs with increasing single active IZO layer thickness exhibit decrease in carrier mobility but steady improvement in NBIS; the best values being μFE ˜ 27.0, 22.0 cm2/Vs and ΔVth ˜ -13.00, -6.75 V for a channel thickness of 7 and 27 nm, respectively. While silicon incorporation is shown to reduce the mobility somewhat, it raises the stability markedly (ΔVth ˜ -1.20 V). Further, IZO (7 nm)/IZO:Si (27 nm) bilayer based TFTs display useful characteristics (field effect mobility, μFE = 15.3 cm2/Vs and NBIS value, ΔVth =-0.75 V) for their application in transparent electronics.

Control of the interaction strength of photonic molecules by nanometer precise 3D fabrication.

PubMed

Rawlings, Colin D; Zientek, Michal; Spieser, Martin; Urbonas, Darius; Stöferle, Thilo; Mahrt, Rainer F; Lisunova, Yuliya; Brugger, Juergen; Duerig, Urs; Knoll, Armin W

2017-11-28

Applications for high resolution 3D profiles, so-called grayscale lithography, exist in diverse fields such as optics, nanofluidics and tribology. All of them require the fabrication of patterns with reliable absolute patterning depth independent of the substrate location and target materials. Here we present a complete patterning and pattern-transfer solution based on thermal scanning probe lithography (t-SPL) and dry etching. We demonstrate the fabrication of 3D profiles in silicon and silicon oxide with nanometer scale accuracy of absolute depth levels. An accuracy of less than 1nm standard deviation in t-SPL is achieved by providing an accurate physical model of the writing process to a model-based implementation of a closed-loop lithography process. For transfering the pattern to a target substrate we optimized the etch process and demonstrate linear amplification of grayscale patterns into silicon and silicon oxide with amplification ratios of ∼6 and ∼1, respectively. The performance of the entire process is demonstrated by manufacturing photonic molecules of desired interaction strength. Excellent agreement of fabricated and simulated structures has been achieved.

The role of hydrogenated amorphous silicon oxide buffer layer on improving the performance of hydrogenated amorphous silicon germanium single-junction solar cells

NASA Astrophysics Data System (ADS)

Sritharathikhun, Jaran; Inthisang, Sorapong; Krajangsang, Taweewat; Krudtad, Patipan; Jaroensathainchok, Suttinan; Hongsingtong, Aswin; Limmanee, Amornrat; Sriprapha, Kobsak

2016-12-01

Hydrogenated amorphous silicon oxide (a-Si1-xOx:H) film was used as a buffer layer at the p-layer (μc-Si1-xOx:H)/i-layer (a-Si1-xGex:H) interface for a narrow band gap hydrogenated amorphous silicon germanium (a-Si1-xGex:H) single-junction solar cell. The a-Si1-xOx:H film was deposited by plasma enhanced chemical vapor deposition (PECVD) at 40 MHz in a same processing chamber as depositing the p-type layer. An optimization of the thickness of the a-Si1-xOx:H buffer layer and the CO2/SiH4 ratio was performed in the fabrication of the a-Si1-xGex:H single junction solar cells. By using the wide band gap a-Si1-xOx:H buffer layer with optimum thickness and CO2/SiH4 ratio, the solar cells showed an improvement in the open-circuit voltage (Voc), fill factor (FF), and short circuit current density (Jsc), compared with the solar cells fabricated using the conventional a-Si:H buffer layer. The experimental results indicated the excellent potential of the wide-gap a-Si1-xOx:H buffer layers for narrow band gap a-Si1-xGex:H single junction solar cells.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

NASA Astrophysics Data System (ADS)

Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro

2013-04-01

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Electrochemical Fabrication of Nanostructures on Porous Silicon for Biochemical Sensing Platforms.

PubMed

Ko, Euna; Hwang, Joonki; Kim, Ji Hye; Lee, Joo Heon; Lee, Sung Hwan; Tran, Van-Khue; Chung, Woo Sung; Park, Chan Ho; Choo, Jaebum; Seong, Gi Hun

2016-01-01

We present a method for the electrochemical patterning of gold nanoparticles (AuNPs) or silver nanoparticles (AgNPs) on porous silicon, and explore their applications in: (1) the quantitative analysis of hydroxylamine as a chemical sensing electrode and (2) as a highly sensitive surface-enhanced Raman spectroscopy (SERS) substrate for Rhodamine 6G. For hydroxylamine detection, AuNPs-porous silicon can enhance the electrochemical oxidation of hydroxylamine. The current changed linearly for concentrations ranging from 100 μM to 1.32 mM (R(2) = 0.995), and the detection limit was determined to be as low as 55 μM. When used as SERS substrates, these materials also showed that nanoparticles decorated on porous silicon substrates have more SERS hot spots than those decorated on crystalline silicon substrates, resulting in a larger SERS signal. Moreover, AgNPs-porous silicon provided five-times higher signal compared to AuNPs-porous silicon. From these results, we expect that nanoparticles decorated on porous silicon substrates can be used in various types of biochemical sensing platforms.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Towards nanometer-spaced silicon contacts to proteins.

PubMed

Schukfeh, Muhammed I; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-18

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p(+) silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices' electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes' edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions' conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein's denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Low resistance Ohmic contact to p-type crystalline silicon via nitrogen-doped copper oxide films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Xinyu, E-mail: xinyu.zhang@anu.edu.au; Wan, Yimao; Bullock, James

2016-08-01

This work explores the application of transparent nitrogen doped copper oxide (CuO{sub x}:N) films deposited by reactive sputtering to create hole-selective contacts for p-type crystalline silicon (c-Si) solar cells. It is found that CuO{sub x}:N sputtered directly onto crystalline silicon is able to form an Ohmic contact. X-ray photoelectron spectroscopy and Raman spectroscopy measurements are used to characterise the structural and physical properties of the CuO{sub x}:N films. Both the oxygen flow rate and the substrate temperature during deposition have a significant impact on the film composition, as well as on the resulting contact resistivity. After optimization, a low contactmore » resistivity of ∼10 mΩ cm{sup 2} has been established. This result offers significant advantages over conventional contact structures in terms of carrier transport and device fabrication.« less

Thermal oxidation of silicon in a residual oxygen atmosphere—the RESOX process—for self-limiting growth of thin silicon dioxide films

NASA Astrophysics Data System (ADS)

Wright, Jason T.; Carbaugh, Daniel J.; Haggerty, Morgan E.; Richard, Andrea L.; Ingram, David C.; Kaya, Savas; Jadwisienczak, Wojciech M.; Rahman, Faiz

2016-10-01

We describe in detail the growth procedures and properties of thermal silicon dioxide grown in a limited and dilute oxygen atmosphere. Thin thermal oxide films have become increasingly important in recent years due to the continuing down-scaling of ultra large scale integration metal oxide silicon field effect transistors. Such films are also of importance for organic transistors where back-gating is needed. The technique described here is novel and allows self-limited formation of high quality thin oxide films on silicon surfaces. This technique is easy to implement in both research laboratory and industrial settings. Growth conditions and their effects on film growth have been described. Properties of the resulting oxide films, relevant for microelectronic device applications, have also been investigated and reported here. Overall, our findings are that thin, high quality, dense silicon dioxide films of thicknesses up to 100 nm can be easily grown in a depleted oxygen environment at temperatures similar to that used for usual silicon dioxide thermal growth in flowing dry oxygen.

One-step Maskless Fabrication and Optical Characterization of Silicon Surfaces with Antireflective Properties and a White Color Appearance

PubMed Central

Schneider, Ling; Feidenhans’l, Nikolaj A.; Telecka, Agnieszka; Taboryski, Rafael J.

2016-01-01

We report a simple one-step maskless fabrication of inverted pyramids on silicon wafers by reactive ion etching. The fabricated surface structures exhibit excellent anti-reflective properties: The total reflectance of the nano inverted pyramids fabricated by our method can be as low as 12% without any anti-reflective layers, and down to only 0.33% with a silicon nitride coating. The results from angle resolved scattering measurements indicate that the existence of triple reflections is responsible for the reduced reflectance. The surfaces with the nano inverted pyramids also exhibit a distinct milky white color. PMID:27725703

Speckle lithography for fabricating Gaussian, quasi-random 2D structures and black silicon structures.

PubMed

Bingi, Jayachandra; Murukeshan, Vadakke Matham

2015-12-18

Laser speckle pattern is a granular structure formed due to random coherent wavelet interference and generally considered as noise in optical systems including photolithography. Contrary to this, in this paper, we use the speckle pattern to generate predictable and controlled Gaussian random structures and quasi-random structures photo-lithographically. The random structures made using this proposed speckle lithography technique are quantified based on speckle statistics, radial distribution function (RDF) and fast Fourier transform (FFT). The control over the speckle size, density and speckle clustering facilitates the successful fabrication of black silicon with different surface structures. The controllability and tunability of randomness makes this technique a robust method for fabricating predictable 2D Gaussian random structures and black silicon structures. These structures can enhance the light trapping significantly in solar cells and hence enable improved energy harvesting. Further, this technique can enable efficient fabrication of disordered photonic structures and random media based devices.

Speckle lithography for fabricating Gaussian, quasi-random 2D structures and black silicon structures

PubMed Central

Bingi, Jayachandra; Murukeshan, Vadakke Matham

2015-01-01

Laser speckle pattern is a granular structure formed due to random coherent wavelet interference and generally considered as noise in optical systems including photolithography. Contrary to this, in this paper, we use the speckle pattern to generate predictable and controlled Gaussian random structures and quasi-random structures photo-lithographically. The random structures made using this proposed speckle lithography technique are quantified based on speckle statistics, radial distribution function (RDF) and fast Fourier transform (FFT). The control over the speckle size, density and speckle clustering facilitates the successful fabrication of black silicon with different surface structures. The controllability and tunability of randomness makes this technique a robust method for fabricating predictable 2D Gaussian random structures and black silicon structures. These structures can enhance the light trapping significantly in solar cells and hence enable improved energy harvesting. Further, this technique can enable efficient fabrication of disordered photonic structures and random media based devices. PMID:26679513

Very high-cycle fatigue failure in micron-scale polycrystalline silicon films: Effects of environment and surface oxide thickness

NASA Astrophysics Data System (ADS)

Alsem, D. H.; Timmerman, R.; Boyce, B. L.; Stach, E. A.; De Hosson, J. Th. M.; Ritchie, R. O.

2007-01-01

Fatigue failure in micron-scale polycrystalline silicon structural films, a phenomenon that is not observed in bulk silicon, can severely impact the durability and reliability of microelectromechanical system devices. Despite several studies on the very high-cycle fatigue behavior of these films (up to 1012cycles), there is still an on-going debate on the precise mechanisms involved. We show here that for devices fabricated in the multiuser microelectromechanical system process (MUMPs) foundry and Sandia Ultra-planar, Multi-level MEMS Technology (SUMMiT V™) process and tested under equi-tension/compression loading at ˜40kHz in different environments, stress-lifetime data exhibit similar trends in fatigue behavior in ambient room air, shorter lifetimes in higher relative humidity environments, and no fatigue failure at all in high vacuum. The transmission electron microscopy of the surface oxides in the test samples shows a four- to sixfold thickening of the surface oxide at stress concentrations after fatigue failure, but no thickening after overload fracture in air or after fatigue cycling in vacuo. We find that such oxide thickening and premature fatigue failure (in air) occur in devices with initial oxide thicknesses of ˜4nm (SUMMiT V™) as well as in devices with much thicker initial oxides ˜20nm (MUMPs). Such results are interpreted and explained by a reaction-layer fatigue mechanism. Specifically, moisture-assisted subcritical cracking within a cyclic stress-assisted thickened oxide layer occurs until the crack reaches a critical size to cause catastrophic failure of the entire device. The entirety of the evidence presented here strongly indicates that the reaction-layer fatigue mechanism is the governing mechanism for fatigue failure in micron-scale polycrystalline silicon thin films.

Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization

NASA Astrophysics Data System (ADS)

Tsai, Chun-Chien; Lee, Yao-Jen; Chiang, Ko-Yu; Wang, Jyh-Liang; Lee, I.-Che; Chen, Hsu-Hsin; Wei, Kai-Fang; Chang, Ting-Kuo; Chen, Bo-Ting; Cheng, Huang-Chung

2007-11-01

In this paper, location-controlled silicon crystal grains are fabricated by the excimer laser crystallization method which employs amorphous silicon spacer structure and prepatterned thin films. The amorphous silicon spacer in nanometer-sized width formed using spacer technology is served as seed crystal to artificially control superlateral growth phenomenon during excimer laser irradiation. An array of 1.8-μm-sized disklike silicon grains is formed, and the n-channel thin-film transistors whose channels located inside the artificially-controlled crystal grains exhibit higher performance of field-effect-mobility reaching 308cm2/Vs as compared with the conventional ones. This position-manipulated silicon grains are essential to high-performance and good uniformity devices.

Indium oxide/n-silicon heterojunction solar cells

DOEpatents

Feng, Tom; Ghosh, Amal K.

1982-12-28

A high photo-conversion efficiency indium oxide/n-silicon heterojunction solar cell is spray deposited from a solution containing indium trichloride. The solar cell exhibits an Air Mass One solar conversion efficiency in excess of about 10%.

Induced nano-scale self-formed metal-oxide interlayer in amorphous silicon tin oxide thin film transistors.

PubMed

Liu, Xianzhe; Xu, Hua; Ning, Honglong; Lu, Kuankuan; Zhang, Hongke; Zhang, Xiaochen; Yao, Rihui; Fang, Zhiqiang; Lu, Xubing; Peng, Junbiao

2018-03-07

Amorphous Silicon-Tin-Oxide thin film transistors (a-STO TFTs) with Mo source/drain electrodes were fabricated. The introduction of a ~8 nm MoO x interlayer between Mo electrodes and a-STO improved the electron injection in a-STO TFT. Mo adjacent to the a-STO semiconductor mainly gets oxygen atoms from the oxygen-rich surface of a-STO film to form MoO x interlayer. The self-formed MoO x interlayer acting as an efficient interface modification layer could conduce to the stepwise internal transport barrier formation while blocking Mo atoms diffuse into a-STO layer, which would contribute to the formation of ohmic contact between Mo and a-STO film. It can effectively improve device performance, reduce cost and save energy for the realization of large-area display with high resolution in future.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Low-damage direct patterning of silicon oxide mask by mechanical processing

PubMed Central

2014-01-01

To realize the nanofabrication of silicon surfaces using atomic force microscopy (AFM), we investigated the etching of mechanically processed oxide masks using potassium hydroxide (KOH) solution. The dependence of the KOH solution etching rate on the load and scanning density of the mechanical pre-processing was evaluated. Particular load ranges were found to increase the etching rate, and the silicon etching rate also increased with removal of the natural oxide layer by diamond tip sliding. In contrast, the local oxide pattern formed (due to mechanochemical reaction of the silicon) by tip sliding at higher load was found to have higher etching resistance than that of unprocessed areas. The profile changes caused by the etching of the mechanically pre-processed areas with the KOH solution were also investigated. First, protuberances were processed by diamond tip sliding at lower and higher stresses than that of the shearing strength. Mechanical processing at low load and scanning density to remove the natural oxide layer was then performed. The KOH solution selectively etched the low load and scanning density processed area first and then etched the unprocessed silicon area. In contrast, the protuberances pre-processed at higher load were hardly etched. The etching resistance of plastic deformed layers was decreased, and their etching rate was increased because of surface damage induced by the pre-processing. These results show that etching depth can be controlled by controlling the etching time through natural oxide layer removal and mechanochemical oxide layer formation. These oxide layer removal and formation processes can be exploited to realize low-damage mask patterns. PMID:24948891

High Aspect Ratio Sub-15 nm Silicon Trenches From Block Copolymer Templates

NASA Astrophysics Data System (ADS)

Gu, Xiaodan; Liu, Zuwei; Gunkel, Ilja; Olynick, Deirdre; Russell, Thomas; University of Massachusetts Amherst Collaboration; Oxford Instrument Collaboration; Lawrence Berkeley National Lab Collaboration

2013-03-01

High-aspect-ratio sub-15 nm silicon trenches are fabricated directly from plasma etching of a block copolymer (BCP) mask. Polystyrene-b-poly(2-vinyl pyridine) (PS-b-P2VP) 40k-b-18k was spin coated and solvent annealed to form cylindrical structures parallel to the silicon substrate. The BCP thin film was reconstructed by immersion in ethanol and then subjected to an oxygen and argon reactive ion etching to fabricate the polymer mask. A low temperature ion coupled plasma with sulfur hexafluoride and oxygen was used to pattern transfer block copolymer structure to silicon with high selectivity (8:1) and fidelity. The silicon pattern was characterized by scanning electron microscopy and grazing incidence x-ray scattering. We also demonstrated fabrication of silicon nano-holes using polystyrene-b-polyethylene oxide (PS-b-PEO) using same methodology described above for PS-b-P2VP. Finally, we show such silicon nano-strucutre serves as excellent nano-imprint master template to pattern various functional materials like poly 3-hexylthiophene (P3HT).

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Silicon microring resonators

NASA Astrophysics Data System (ADS)

Tan, Ying; Dai, Daoxin

2018-05-01

Silicon microring resonators (MRRs) are very popular for many applications because of the advantages of footprint compactness, easy scalability, and functional versatility. Ultra-compact silicon MRRs with box-like spectral responses are realized with a very large free-spectral range (FSR) by introducing bent directional couplers. The measured box-like spectral response has an FSR of >30 nm. The permanent wavelength-alignment techniques for MRRs are also presented, including the laser-induced local-oxidation technique as well as the local-etching technique. With these techniques, one can control finely the permanent wavelength shift, which is also large enough to compensate the random wavelength variation due to the random fabrication errors.

Fabrication of amorphous silica nanowires via oxygen plasma treatment of polymers on silicon

NASA Astrophysics Data System (ADS)

Chen, Zhuojie; She, Didi; Chen, Qinghua; Li, Yanmei; Wu, Wengang

2018-02-01

We demonstrate a facile non-catalytic method of fabricating silica nanowires at room temperature. Different polymers including photoresists, parylene C and polystyrene are patterned into pedestals on the silicon substrates. The silica nanowires are obtained via the oxygen plasma treatment on those pedestals. Compared to traditional strategies of silica nanowire fabrication, this method is much simpler and low-cost. Through designing the proper initial patterns and plasma process parameters, the method can be used to fabricate various regiment nano-scale silica structure arrays in any laboratory with a regular oxygen-plasma-based cleaner or reactive-ion-etching equipment.

Liquid gallium ball/crystalline silicon polyhedrons/aligned silicon oxide nanowires sandwich structure: An interesting nanowire growth route

NASA Astrophysics Data System (ADS)

Pan, Zheng Wei; Dai, Sheng; Beach, David B.; Lowndes, Douglas H.

2003-10-01

We demonstrate the growth of silicon oxide nanowires through a sandwich-like configuration, i.e., Ga ball/Si polyhedrons/silicon oxide nanowires, by using Ga as the catalyst and SiO powder as the source material. The sandwich-like structures have a carrot-like morphology, consisting of three materials with different morphologies, states, and crystallographic structures. The "carrot" top is a liquid Ga ball with diameter of ˜10-30 μm; the middle part is a Si ring usually composed of about 10 μm-sized, clearly faceted, and crystalline Si polyhedrons that are arranged sequentially in a band around the lower hemisphere surface of the Ga ball; the bottom part is a carrot-shaped bunch of highly aligned silicon oxide nanowires that grow out from the downward facing facets of the Si polyhedrons. This study reveals several interesting nanowire growth phenomena that enrich the conventional vapor-liquid-solid nanowire growth mechanism.

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

DOEpatents

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Method of electrode fabrication for solid oxide electrochemical cells

DOEpatents

Jensen, R.R.

1990-11-20

A process for fabricating cermet electrodes for solid oxide electrochemical cells by sintering is disclosed. First, a porous metal electrode is fabricated on a solid oxide cell, such as a fuel cell by, for example, sintering, and is then infiltrated with a high volume fraction stabilized zirconia suspension. A second sintering step is used to sinter the infiltrated zirconia to a high density in order to more securely attach the electrode to the solid oxide electrolyte of the cell. High performance fuel electrodes can be obtained with this process. Further electrode performance enhancement may be achieved if stabilized zirconia doped with cerium oxide, chromium oxide, titanium oxide, and/or praseodymium oxide for electronic conduction is used. 5 figs.

Method of electrode fabrication for solid oxide electrochemical cells

DOEpatents

Jensen, Russell R.

1990-01-01

A process for fabricating cermet electrodes for solid oxide electrochemical cells by sintering is disclosed. First, a porous metal electrode is fabricated on a solid oxide cell, such as a fuel cell by, for example, sintering, and is then infiltrated with a high volume fraction stabilized zirconia suspension. A second sintering step is used to sinter the infiltrated zirconia to a high density in order to more securely attach the electrode to the solid oxide electrolyte of the cell. High performance fuel electrodes can be obtained with this process. Further electrode performance enhancement may be achieved if stabilized zirconia doped with cerium oxide, chromium oxide, titanium oxide, and/or praseodymium oxide for electronic conduction is used.

Monolithic Integration of a Silicon Nanowire Field-Effect Transistors Array on a Complementary Metal-Oxide Semiconductor Chip for Biochemical Sensor Applications

PubMed Central

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2017-01-01

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I−V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs. PMID:26348408

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

PubMed

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

NASA Astrophysics Data System (ADS)

Balpande, Suresh S.; Pande, Rajesh S.

2016-04-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

PubMed Central

Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ömer

2017-01-01

Silicon is an excellent material for microelectronics and integrated photonics1–3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e., “in-chip” microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances. PMID:28983323

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

NASA Astrophysics Data System (ADS)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

NASA Astrophysics Data System (ADS)

Sakamoto, Toshitsugu; Tada, Munehiro; Tsuji, Yukihide; Makiyama, Hideki; Hasegawa, Takumi; Yamamoto, Yoshiki; Okanishi, Shinobu; Banno, Naoki; Miyamura, Makoto; Okamoto, Koichiro; Iguchi, Noriyuki; Ogasahara, Yasuhiro; Oda, Hidekazu; Kamohara, Shiro; Yamagata, Yasushi; Sugii, Nobuyuki; Hada, Hiromitsu

2015-04-01

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34-1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.

Novel Iron-oxide Catalyzed CNT Formation on Semiconductor Silicon Nanowire

PubMed Central

Adam, Tijjani; U, Hashim

2014-01-01

An aqueous ferric nitrate nonahydrate (Fe(NO3)3.9H2O) and magnesium oxide (MgO) were mixed and deposited on silicon nanowires (SiNWs), the carbon nanotubes (CNTs) formed by the concentration of Fe3O4/MgO catalysts with the mole ratio set at 0.15:9.85 and 600°C had diameter between 15.23 to 90nm with high-density distribution of CNT while those with the mole ratio set at 0.45:9.55 and 730°C had diameter of 100 to 230nm. The UV/Vis/NIR and FT-IR spectroscopes clearly confirmed the presence of the silicon-CNTs hybrid structure. UV/Vis/NIR, FT-IR spectra and FESEM images confirmed the silicon-CNT structure exists with diameters ranging between 15-230nm. Thus, the study demonstrated cost effective method of silicon-CNT composite nanowire formation via Iron-oxide Catalyze synthesis. PMID:25237290

Efficient Flame Detection and Early Warning Sensors on Combustible Materials Using Hierarchical Graphene Oxide/Silicone Coatings.

PubMed

Wu, Qian; Gong, Li-Xiu; Li, Yang; Cao, Cheng-Fei; Tang, Long-Cheng; Wu, Lianbin; Zhao, Li; Zhang, Guo-Dong; Li, Shi-Neng; Gao, Jiefeng; Li, Yongjin; Mai, Yiu-Wing

2018-01-23

Design and development of smart sensors for rapid flame detection in postcombustion and early fire warning in precombustion situations are critically needed to improve the fire safety of combustible materials in many applications. Herein, we describe the fabrication of hierarchical coatings created by assembling a multilayered graphene oxide (GO)/silicone structure onto different combustible substrate materials. The resulting coatings exhibit distinct temperature-responsive electrical resistance change as efficient early warning sensors for detecting abnormal high environmental temperature, thus enabling fire prevention below the ignition temperature of combustible materials. After encountering a flame attack, we demonstrate extremely rapid flame detection response in 2-3 s and excellent flame self-extinguishing retardancy for the multilayered GO/silicone structure that can be synergistically transformed to a multiscale graphene/nanosilica protection layer. The hierarchical coatings developed are promising for fire prevention and protection applications in various critical fire risk and related perilous circumstances.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Process to produce silicon carbide fibers using a controlled concentration of boron oxide vapor

NASA Technical Reports Server (NTRS)

Barnard, Thomas Duncan (Inventor); Lipowitz, Jonathan (Inventor); Nguyen, Kimmai Thi (Inventor)

2001-01-01

A process for producing polycrystalline silicon carbide by heating an amorphous ceramic fiber that contains silicon and carbon in an environment containing boron oxide vapor. The boron oxide vapor is produced in situ by the reaction of a boron containing material such as boron carbide and an oxidizing agent such as carbon dioxide, and the amount of boron oxide vapor can be controlled by varying the amount and rate of addition of the oxidizing agent.

Process to produce silicon carbide fibers using a controlled concentration of boron oxide vapor

NASA Technical Reports Server (NTRS)

Barnard, Thomas Duncan (Inventor); Lipowitz, Jonathan (Inventor); Nguyen, Kimmai Thi (Inventor)

2000-01-01

A process for producing polycrystalline silicon carbide includes heating an amorphous ceramic fiber that contains silicon and carbon in an environment containing boron oxide vapor. The boron oxide vapor is produced in situ by the reaction of a boron containing material such as boron carbide and an oxidizing agent such as carbon dioxide, and the amount of boron oxide vapor can be controlled by varying the amount and rate of addition of the oxidizing agent.

Electrochemical Formation of a p-n Junction on Thin Film Silicon Deposited in Molten Salt.

PubMed

Zou, Xingli; Ji, Li; Yang, Xiao; Lim, Taeho; Yu, Edward T; Bard, Allen J

2017-11-15

Herein we report the demonstration of electrochemical deposition of silicon p-n junctions all in molten salt. The results show that a dense robust silicon thin film with embedded junction formation can be produced directly from inexpensive silicates/silicon oxide precursors by a two-step electrodeposition process. The fabricated silicon p-n junction exhibits clear diode rectification behavior and photovoltaic effects, indicating promise for application in low-cost silicon thin film solar cells.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Towards nanometer-spaced silicon contacts to proteins

NASA Astrophysics Data System (ADS)

Schukfeh, Muhammed I.; Sepunaru, Lior; Behr, Pascal; Li, Wenjie; Pecht, Israel; Sheves, Mordechai; Cahen, David; Tornow, Marc

2016-03-01

A vertical nanogap device (VND) structure comprising all-silicon contacts as electrodes for the investigation of electronic transport processes in bioelectronic systems is reported. Devices were fabricated from silicon-on-insulator substrates whose buried oxide (SiO2) layer of a few nanometers in thickness is embedded within two highly doped single crystalline silicon layers. Individual VNDs were fabricated by standard photolithography and a combination of anisotropic and selective wet etching techniques, resulting in p+ silicon contacts, vertically separated by 4 or 8 nm, depending on the chosen buried oxide thickness. The buried oxide was selectively recess-etched with buffered hydrofluoric acid, exposing a nanogap. For verification of the devices’ electrical functionality, gold nanoparticles were successfully trapped onto the nanogap electrodes’ edges using AC dielectrophoresis. Subsequently, the suitability of the VND structures for transport measurements on proteins was investigated by functionalizing the devices with cytochrome c protein from solution, thereby providing non-destructive, permanent semiconducting contacts to the proteins. Current-voltage measurements performed after protein deposition exhibited an increase in the junctions’ conductance of up to several orders of magnitude relative to that measured prior to cytochrome c immobilization. This increase in conductance was lost upon heating the functionalized device to above the protein’s denaturation temperature (80 °C). Thus, the VND junctions allow conductance measurements which reflect the averaged electronic transport through a large number of protein molecules, contacted in parallel with permanent contacts and, for the first time, in a symmetrical Si-protein-Si configuration.

Evaluation of transition metal oxide as carrier-selective contacts for silicon heterojunction solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ding, L.; Boccard, Matthieu; Holman, Zachary

2015-04-06

"Reducing light absorption in the non-active solar cell layers, while enabling the extraction of the photogenerated minority carriers at quasi-Fermi levels are two key factors to improve current generation and voltage, and therefore efficiency of silicon heterojunction solar devices. To address these two critical aspects, transition metal oxide materials have been proposed as alternative to the n- and p-type amorphous silicon used as electron and hole selective contacts, respectively. Indeed, transition metal oxides such as molybdenum oxide, titanium oxide, nickel oxide or tungsten oxide combine a wide band gap typically over 3 eV with a band structure and theoretical bandmore » alignment with silicon that results in high transparency to the solar spectrum and in selectivity for the transport of only one carrier type. Improving carrier extraction or injection using transition metal oxide has been a topic of investigation in the field of organic solar cells and organic LEDs; from these pioneering works a lot of knowledge has been gained on materials properties, ways to control these during synthesis and deposition, and their impact on device performance. Recently, the transfer of some of this knowledge to silicon solar cells and the successful application of some metal oxide to contact heterojunction devices have gained much attention. In this contribution, we investigate the suitability of various transition metal oxide films (molybdenum oxide, titanium oxide, and tungsten oxide) deposited either by thermal evaporation or sputtering as transparent hole or electron selective transport layer for silicon solar cells. In addition to systematically characterize their optical and structural properties, we use photoemission spectroscopy to relate compound stoichiometry to band structure and characterize band alignment to silicon. The direct silicon/metal oxide interface is further analyzed by quasi-steady state photoconductance decay method to assess the quality of

Titanium-silicon oxide film structures for polarization-modulated infrared reflection absorption spectroscopy

PubMed Central

Dunlop, Iain E.; Zorn, Stefan; Richter, Gunther; Srot, Vesna; Kelsch, Marion; van Aken, Peter A.; Skoda, Maximilian; Gerlach, Alexander; Spatz, Joachim P.; Schreiber, Frank

2010-01-01

We present a titanium-silicon oxide film structure that permits polarization modulated infrared reflection absorption spectroscopy on silicon oxide surfaces. The structure consists of a ~6 nm sputtered silicon oxide film on a ~200 nm sputtered titanium film. Characterization using conventional and scanning transmission electron microscopy, electron energy loss spectroscopy, X-ray photoelectron spectroscopy and X-ray reflectometry is presented. We demonstrate the use of this structure to investigate a selectively protein-resistant self-assembled monolayer (SAM) consisting of silane-anchored, biotin-terminated poly(ethylene glycol) (PEG). PEG-associated IR bands were observed. Measurements of protein-characteristic band intensities showed that this SAM adsorbed streptavidin whereas it repelled bovine serum albumin, as had been expected from its structure. PMID:20418963

Growth and Etch Rate Study of Low Temperature Anodic Silicon Dioxide Thin Films

PubMed Central

Ashok, Akarapu; Pal, Prem

2014-01-01

Silicon dioxide (SiO2) thin films are most commonly used insulating films in the fabrication of silicon-based integrated circuits (ICs) and microelectromechanical systems (MEMS). Several techniques with different processing environments have been investigated to deposit silicon dioxide films at temperatures down to room temperature. Anodic oxidation of silicon is one of the low temperature processes to grow oxide films even below room temperature. In the present work, uniform silicon dioxide thin films are grown at room temperature by using anodic oxidation technique. Oxide films are synthesized in potentiostatic and potentiodynamic regimes at large applied voltages in order to investigate the effect of voltage, mechanical stirring of electrolyte, current density and the water percentage on growth rate, and the different properties of as-grown oxide films. Ellipsometry, FTIR, and SEM are employed to investigate various properties of the oxide films. A 5.25 Å/V growth rate is achieved in potentiostatic mode. In the case of potentiodynamic mode, 160 nm thickness is attained at 300 V. The oxide films developed in both modes are slightly silicon rich, uniform, and less porous. The present study is intended to inspect various properties which are considered for applications in MEMS and Microelectronics. PMID:24672287

Crack healing behavior of hot pressed silicon nitride due to oxidation

NASA Technical Reports Server (NTRS)

Choi, S. R.; Tikare, V.

1992-01-01

It is shown that limited oxidation of an MgO-containing, hot-pressed silicon nitride ceramic at 800 deg C and above results in increased strength due to crack healing. Slight oxidation of the surface produces enstatite and cristobalite which fills in cracks. More extensive oxidation leads to strength degradation due to the formation of new flaws by the evolution of N2 gas at the surface. The apparent fracture toughness also increased at 800 deg C and above due to oxidation. Bonds formed between the two surfaces of the crack during oxidation leads to a reduction in stress intensity at the crack tip, suggesting that valid high-temperature toughness values cannot be obtained in an air environment. The increase in strength due to crack healing by oxidation can be achieved without compromising the fatigue properties of the silicon nitride ceramic.

Comparative surface studies on wet and dry sacrificial thermal oxidation on silicon carbide

NASA Astrophysics Data System (ADS)

Koh, A.; Kestle, A.; Wright, C.; Wilks, S. P.; Mawby, P. A.; Bowen, W. R.

2001-04-01

A comparative study on the effect of wet and dry thermal oxidation on 4H-silicon carbide (SiC) and on sacrificial silicon (Si) thermal oxidation on 4H-SiC surface has been conducted using atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS). The AFM images show the formation of 'nano-islands' of varying density on the SiC surface after the removal of thermal oxide using hydrofluoric (HF) acid etch. These nano-islands are resistant to HF acid and have been previously linked to residual carbon [1-3] resulting from the oxidation process. This paper presents the use of a sacrificial silicon oxidation (SSO) step as a form of surface preparation that gives a reproducible clean SiC surface. XPS results show a slight electrical shift in binding energy between the wet and dry thermal oxidation on the standard SiC surface, while the surface produced by the SSO technique shows a minimal shift.

Multichannel silicon WDM ring filters fabricated with DUV lithography

NASA Astrophysics Data System (ADS)

Lee, Jong-Moo; Park, Sahnggi; Kim, Gyungock

2008-09-01

We have fabricated 9-channel silicon wavelength-division-multiplexing (WDM) ring filters using 193 nm deep-ultraviolet (DUV) lithography and investigated the spectral properties of the ring filters by comparing the transmission spectra with and without an upper cladding. The average channel-spacing of the 9-channel WDM ring filter with a polymeric upper cladding is measured about 1.86 nm with the standard deviation of the channel-spacing about 0.34 nm. The channel crosstalk is about -30 dB, and the minimal drop loss is about 2 dB.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Simple fabrication of closed-packed IR microlens arrays on silicon by femtosecond laser wet etching

NASA Astrophysics Data System (ADS)

Meng, Xiangwei; Chen, Feng; Yang, Qing; Bian, Hao; Du, Guangqing; Hou, Xun

2015-10-01

We demonstrate a simple route to fabricate closed-packed infrared (IR) silicon microlens arrays (MLAs) based on femtosecond laser irradiation assisted by wet etching method. The fabricated MLAs show high fill factor, smooth surface and good uniformity. They can be used as optical devices for IR applications. The exposure and etching parameters are optimized to obtain reproducible microlens with hexagonal and rectangular arrangements. The surface roughness of the concave MLAs is only 56 nm. This presented method is a maskless process and can flexibly change the size, shape and the fill factor of the MLAs by controlling the experimental parameters. The concave MLAs on silicon can work in IR region and can be used for IR sensors and imaging applications.

Deep Etching Process Developed for the Fabrication of Silicon Carbide Microsystems

NASA Technical Reports Server (NTRS)

Beheim, Glenn M.

2000-01-01

Silicon carbide (SiC), because of its superior electrical and mechanical properties at elevated temperatures, is a nearly ideal material for the microminiature sensors and actuators that are used in harsh environments where temperatures may reach 600 C or greater. Deep etching using plasma methods is one of the key processes used to fabricate silicon microsystems for more benign environments, but SiC has proven to be a more difficult material to etch, and etch depths in SiC have been limited to several micrometers. Recently, the Sensors and Electronics Technology Branch at the NASA Glenn Research Center at Lewis Field developed a plasma etching process that was shown to be capable of etching SiC to a depth of 60 mm. Deep etching of SiC is achieved by inductive coupling of radiofrequency electrical energy to a sulfur hexafluoride (SF6) plasma to direct a high flux of energetic ions and reactive fluorine atoms to the SiC surface. The plasma etch is performed at a low pressure, 5 mtorr, which together with a high gas throughput, provides for rapid removal of the gaseous etch products. The lateral topology of the SiC microstructure is defined by a thin film of etch-resistant material, such as indium-tin-oxide, which is patterned using conventional photolithographic processes. Ions from the plasma bombard the exposed SiC surfaces and supply the energy needed to initiate a reaction between SiC and atomic fluorine. In the absence of ion bombardment, no reaction occurs, so surfaces perpendicular to the wafer surface (the etch sidewalls) are etched slowly, yielding the desired vertical sidewalls.

Fabrication of back-contacted silicon solar cells using thermomigration to create conductive vias

DOEpatents

Gee, James M; Schmit, Russell R.

2007-01-30

Methods of manufacturing back-contacted silicon solar cells fabricated using a gradient-driven solute transport process, such as thermomigration or electromigration, to create n-type conductive vias connecting the n-type emitter layer on the front side to n-type ohmic contacts located on the back side.

X-ray reflectivity study of formation of multilayer porous anodic oxides of silicon.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chu, Y.; Fenollosa, R.; Parkhutik, V.

1999-07-21

The paper reports data on the kinetics of anodic oxide films growth on silicon in aqueous solutions of phosphoric acids as well as a study of the morphology of the oxides grown in a special regime of the oscillating anodic potential. X-ray reflectivity measurements were performed on the samples of anodic oxides using an intense synchrotron radiation source. They have a multilayer structure as revealed by theoretical fitting of the reflectivity data. The oscillations of the anodic potential are explained in terms of synchronized oxidation/dissolution reactions at the silicon surface and accumulation of mechanic stress in the oxide film.

Quantitative determination of the clustered silicon concentration in substoichiometric silicon oxide layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spinella, Corrado; Bongiorno, Corrado; Nicotra, Giuseppe

2005-07-25

We present an analytical methodology, based on electron energy loss spectroscopy (EELS) and energy-filtered transmission electron microscopy, which allows us to quantify the clustered silicon concentration in annealed substoichiometric silicon oxide layers, deposited by plasma-enhanced chemical vapor deposition. The clustered Si volume fraction was deduced from a fit to the experimental EELS spectrum using a theoretical description proposed to calculate the dielectric function of a system of spherical particles of equal radii, located at random in a host material. The methodology allowed us to demonstrate that the clustered Si concentration is only one half of the excess Si concentration dissolvedmore » in the layer.« less

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Fabrication of hollow boron-doped diamond nanostructure via electrochemical corrosion of a tungsten oxide template.

PubMed

Lim, Young-Kyun; Lee, Eung-Seok; Lee, Choong-Hyun; Lim, Dae-Soon

2018-08-10

In the study, a hollow boron-doped diamond (BDD) nanostructure electrode is fabricated to increase the reactive surface area for electrochemical applications. Tungsten oxide nanorods are deposited on the silicon substrate as a template by the hot filament chemical vapor deposition (HFCVD) method. The template is coated with a 100 nm BDD layer deposited by HFCVD to form a core-shell nanostructure. The WO x core is finally electrochemically dissolved to form hollow BDD nanostructure. The fabricated hollow BDD nanostructure electrode is investigated via scanning electron microscopy, transmission electron microscopy, and Raman spectroscopy. The specific surface areas of the electrodes were analyzed and compared by using Brunauer-Emmett-Teller method. Furthermore, cyclic voltammetry and chronocoulometry are used to investigate the electrochemical characteristics and the reactive surface area of the as-prepared hollow BDD nanostructure electrode. A hollow BDD nanostructure electrode exhibits a reactive area that is 15 times that of a planar BDD thin electrode.

Silicon Oxide Deposition into a Hole Using a Focused Ion Beam

NASA Astrophysics Data System (ADS)

Nakamura, Hiroko; Komano, Haruki; Norimatu, Kenji; Gomei, Yoshio

1991-11-01

Focused ion beam (FIB)-induced deposition of silicon oxide in terms of filling a hole is reported. It was found that a vacant space was formed when an ion beam was simply scanned through the hole area. To investigate the mechanism to form the vacancy, deposition on the sample, which has a step with a height of 0.8 μm, was carried out by using a Si2+ and a Be2+ ion beam. An extruded deposit resembling a pent roof was observed from the step ridge. The mechanism of the pent roof growth on the steplike sample was considered and the vacancy formation in the hole can be explained by the same mechanism. For silicon oxide, the high growth rate of the extruded deposit is thought to be the key to the vacancy formation. A useful way is proposed to fill the hole with silicon oxide with almost no vacancy.

Method for forming fibrous silicon carbide insulating material

DOEpatents

Wei, G.C.

1983-10-12

A method whereby silicon carbide-bonded SiC fiber composites are prepared from carbon-bonded C fiber composites is disclosed. Carbon-bonded C fiber composite material is treated with gaseous silicon monoxide generated from the reaction of a mixture of colloidal silica and carbon black at an elevated temperature in an argon atmosphere. The carbon in the carbon bond and fiber is thus chemically converted to SiC resulting in a silicon carbide-bonded SiC fiber composite that can be used for fabricating dense, high-strength high-toughness SiC composites or as thermal insulating materials in oxidizing environments.

Method for forming fibrous silicon carbide insulating material

DOEpatents

Wei, George C.

1984-01-01

A method whereby silicon carbide-bonded SiC fiber composites are prepared from carbon-bonded C fiber composites is disclosed. Carbon-bonded C fiber composite material is treated with gaseous silicon monoxide generated from the reaction of a mixture of colloidal silica and carbon black at an elevated temperature in an argon atmosphere. The carbon in the carbon bond and fiber is thus chemically converted to SiC resulting in a silicon carbide-bonded SiC fiber composite that can be used for fabricating dense, high-strength high-toughness SiC composites or as thermal insulating materials in oxidizing environments.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Balpande, Suresh S., E-mail: balpandes@rknec.edu; Pande, Rajesh S.

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition tomore » this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Surface texture of single-crystal silicon oxidized under a thin V{sub 2}O{sub 5} layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nikitin, S. E., E-mail: nikitin@mail.ioffe.ru; Verbitskiy, V. N.; Nashchekin, A. V.

The process of surface texturing of single-crystal silicon oxidized under a V{sub 2}O{sub 5} layer is studied. Intense silicon oxidation at the Si–V{sub 2}O{sub 5} interface begins at a temperature of 903 K which is 200 K below than upon silicon thermal oxidation in an oxygen atmosphere. A silicon dioxide layer 30–50 nm thick with SiO{sub 2} inclusions in silicon depth up to 400 nm is formed at the V{sub 2}O{sub 5}–Si interface. The diffusion coefficient of atomic oxygen through the silicon-dioxide layer at 903 K is determined (D ≥ 2 × 10{sup –15} cm{sup 2} s{sup –1}). A modelmore » of low-temperature silicon oxidation, based on atomic oxygen diffusion from V{sub 2}O{sub 5} through the SiO{sub 2} layer to silicon, and SiO{sub x} precipitate formation in silicon is proposed. After removing the V{sub 2}O{sub 5} and silicon-dioxide layers, texture is formed on the silicon surface, which intensely scatters light in the wavelength range of 300–550 nm and is important in the texturing of the front and rear surfaces of solar cells.« less

Planar-type ferromagnetic tunnel junctions fabricated by SPM local oxidation

NASA Astrophysics Data System (ADS)

Tomoda, Y.; Kayashima, S.; Ogino, T.; Motoyama, M.; Takemura, Y.; Shirakashi, J.

Nanometer-scale oxide wires were fabricated by local oxidation nanolithography using scanning probe microscope (SPM). This technique was applied to the fabrication of planar-type Ni/Ni oxide/Ni ferromagnetic tunnel junctions. In order to induce magnetic shape anisotropy, asymmetrical channel structure was patterned by conventional photolithography and wet etching processes. The magnetoresistance (MR) characteristics were clearly shown in the planar-type Ni/Ni oxide/Ni ferromagnetic tunnel junctions. MR ratio of above 100% was obtained at 17 K. This result suggests that the local oxidation nanolithography using SPM is useful for the application to planar-type ferromagnetic tunnel junctions.

Fabrication of super slippery sheet-layered and porous anodic aluminium oxide surfaces and its anticorrosion property

NASA Astrophysics Data System (ADS)

Song, Tingting; Liu, Qi; Liu, Jingyuan; Yang, Wanlu; Chen, Rongrong; Jing, Xiaoyan; Takahashi, Kazunobu; Wang, Jun

2015-11-01

Inspired by natural plants such as Nepenthes pitcher plants, super slippery surfaces have been developed to improve the attributes of repellent surfaces. In this report, super slippery porous anodic aluminium oxide (AAO) surfaces have fabricated by a simple and reproducible method. Firstly, the aluminium substrates were treated by an anodic process producing micro-nano structured sheet-layered pores, and then immersed in Methyl Silicone Oil, Fluororalkylsilane (FAS) and DuPont Krytox, respectively, generating super slippery surfaces. Such a good material with excellent anti-corrosion property through a simple and repeatable method may be potential candidates for metallic application in anti-corrosion and extreme environment.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Aluminum-catalyzed silicon nanowires: Growth methods, properties, and applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hainey, Mel F.; Redwing, Joan M.

Metal-mediated vapor-liquid-solid (VLS) growth is a promising approach for the fabrication of silicon nanowires, although residual metal incorporation into the nanowires during growth can adversely impact electronic properties particularly when metals such as gold and copper are utilized. Aluminum, which acts as a shallow acceptor in silicon, is therefore of significant interest for the growth of p-type silicon nanowires but has presented challenges due to its propensity for oxidation. This paper summarizes the key aspects of aluminum-catalyzed nanowire growth along with wire properties and device results. In the first section, aluminum-catalyzed nanowire growth is discussed with a specific emphasis onmore » methods to mitigate aluminum oxide formation. Next, the influence of growth parameters such as growth temperature, precursor partial pressure, and hydrogen partial pressure on nanowire morphology is discussed, followed by a brief review of the growth of templated and patterned arrays of nanowires. Aluminum incorporation into the nanowires is then discussed in detail, including measurements of the aluminum concentration within wires using atom probe tomography and assessment of electrical properties by four point resistance measurements. Finally, the use of aluminum-catalyzed VLS growth for device fabrication is reviewed including results on single-wire radial p-n junction solar cells and planar solar cells fabricated with nanowire/nanopyramid texturing.« less

Oxygen absorption in free-standing porous silicon: a structural, optical and kinetic analysis.

PubMed

Cisneros, Rodolfo; Pfeiffer, Heriberto; Wang, Chumin

2010-01-16

Porous silicon (PSi) is a nanostructured material possessing a huge surface area per unit volume. In consequence, the adsorption and diffusion of oxygen in PSi are particularly important phenomena and frequently cause significant changes in its properties. In this paper, we study the thermal oxidation of p+-type free-standing PSi fabricated by anodic electrochemical etching. These free-standing samples were characterized by nitrogen adsorption, thermogravimetry, atomic force microscopy and powder X-ray diffraction. The results show a structural phase transition from crystalline silicon to a combination of cristobalite and quartz, passing through amorphous silicon and amorphous silicon-oxide structures, when the thermal oxidation temperature increases from 400 to 900 °C. Moreover, we observe some evidence of a sinterization at 400 °C and an optimal oxygen-absorption temperature about 700 °C. Finally, the UV/Visible spectrophotometry reveals a red and a blue shift of the optical transmittance spectra for samples with oxidation temperatures lower and higher than 700 °C, respectively.

The Oxidation of CVD Silicon Carbide in Carbon Dioxide

NASA Technical Reports Server (NTRS)

Opila, Elizabeth J.; Nguyen, QuynchGiao N.

1997-01-01

Chemically-vapor-deposited silicon carbide (CVD SiC) was oxidized in carbon dioxide (CO2) at temperatures of 1200-1400 C for times between 100 and 500 hours at several gas flow rates. Oxidation weight gains were monitored by thermogravimetric analysis (TGA) and were found to be very small and independent of temperature. Possible rate limiting kinetic laws are discussed. Oxidation of SiC by CO2 is negligible compared to the rates measured for other oxidants typically found in combustion environments: oxygen and water vapor.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Spectroellipsometric detection of silicon substrate damage caused by radiofrequency sputtering of niobium oxide

NASA Astrophysics Data System (ADS)

Lohner, Tivadar; Serényi, Miklós; Szilágyi, Edit; Zolnai, Zsolt; Czigány, Zsolt; Khánh, Nguyen Quoc; Petrik, Péter; Fried, Miklós

2017-11-01

Substrate surface damage induced by deposition of metal atoms by radiofrequency (rf) sputtering or ion beam sputtering onto single-crystalline silicon (c-Si) surface has been characterized earlier by electrical measurements. The question arises whether it is possible to characterize surface damage using spectroscopic ellipsometry (SE). In our experiments niobium oxide layers were deposited by rf sputtering on c-Si substrates in gas mixture of oxygen and argon. Multiple angle of incidence spectroscopic ellipsometry measurements were performed, a four-layer optical model (surface roughness layer, niobium oxide layer, native silicon oxide layer and ion implantation-amorphized silicon [i-a-Si] layer on a c-Si substrate) was created in order to evaluate the spectra. The evaluations yielded thicknesses of several nm for the i-a-Si layer. Better agreement could be achieved between the measured and the generated spectra by inserting a mixed layer (with components of c-Si and i-a-Si applying the effective medium approximation) between the silicon oxide layer and the c-Si substrate. High depth resolution Rutherford backscattering (RBS) measurements were performed to investigate the interface disorder between the deposited niobium oxide layer and the c-Si substrate. Atomic resolution cross-sectional transmission electron microscopy investigation was applied to visualize the details of the damaged subsurface region of the substrate.

Micromechanical Structures Fabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rajic, S

2001-05-08

Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continuallymore » vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon micro-devices and the second impediment is communicating with these novel devices. We have implemented an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We also implemented a mechanical, electrical, and optical self-aligning hybridization technique for these alternate-material MEMS substrates.« less

Method for removing oxide contamination from silicon carbide powders

DOEpatents

Brynestad, J.; Bamberger, C.E.

1984-08-01

The described invention is directed to a method for removing oxide contamination in the form of oxygen-containing compounds such as SiO/sub 2/ and B/sub 2/O/sub 3/ from a charge of finely divided silicon carbide. The silicon carbide charge is contacted with a stream of hydrogen fluoride mixed with an inert gas carrier such as argon at a temperature in the range of about 200/sup 0/ to 650/sup 0/C. The oxides in the charge react with the heated hydrogen fluoride to form volatile gaseous fluorides such as SiF/sub 4/ and BF/sub 3/ which pass through the charge along with unreacted hydrogen fluoride and the carrier gas. Any residual gaseous reaction products and hydrogen fluoride remaining in the charge are removed by contacting the charge with the stream of inert gas which also cools the powder to room temperature. The removal of the oxygen contamination by practicing the present method provides silicon carbide powders with desirable pressing and sintering characteristics. 1 tab.

Improving Mechanical Properties of Molded Silicone Rubber for Soft Robotics Through Fabric Compositing.

PubMed

Wang, Yue; Gregory, Cherry; Minor, Mark A

2018-06-01

Molded silicone rubbers are common in manufacturing of soft robotic parts, but they are often prone to tears, punctures, and tensile failures when strained. In this article, we present a fabric compositing method for improving the mechanical properties of soft robotic parts by creating a fabric/rubber composite that increases the strength and durability of the molded rubber. Comprehensive ASTM material tests evaluating the strength, tear resistance, and puncture resistance are conducted on multiple composites embedded with different fabrics, including polyester, nylon, silk, cotton, rayon, and several blended fabrics. Results show that strong fabrics increase the strength and durability of the composite, valuable in pneumatic soft robotic applications, while elastic fabrics maintain elasticity and enhance tear strength, suitable for robotic skins or soft strain sensors. Two case studies then validate the proposed benefits of the fabric compositing for soft robotic pressure vessel applications and soft strain sensor applications. Evaluations of the fabric/rubber composite samples and devices indicate that such methods are effective for improving mechanical properties of soft robotic parts, resulting in parts that can have customized stiffness, strength, and vastly improved durability.

Carrier Selective, Passivated Contacts for High Efficiency Silicon Solar Cells based on Transparent Conducting Oxides

DOE PAGES

Young, David L.; Nemeth, William; Grover, Sachit; ...

2014-01-01

We describe the design, fabrication and results of passivated contacts to n-type silicon utilizing thin SiO 2 and transparent conducting oxide layers. High temperature silicon dioxide is grown on both surfaces of an n-type wafer to a thickness <50 Å, followed by deposition of tin-doped indium oxide (ITO) and a patterned metal contacting layer. As deposited, the thin-film stack has a very high J0, contact, and a non-ohmic, high contact resistance. However, after a forming gas anneal, the passivation quality and the contact resistivity improve significantly. The contacts are characterized by measuring the recombination parameter of the contact (J0, contact)more » and the specific contact resistivity (ρ contact) using a TLM pattern. The best ITO/SiO 2 passivated contact in this study has J 0,contact = 92.5 fA/cm 2 and ρ contact = 11.5 mOhm-cm 2. These values are placed in context with other passivating contacts using an analysis that determines the ultimate efficiency and the optimal area fraction for contacts for a given set of (J0, contact, ρ contact) values. The ITO/SiO 2 contacts are found to have a higher J0, contact, but a similar ρ contact compared to the best reported passivated contacts.« less

A Model for the Oxidation of Carbon Silicon Carbide Composite Structures

NASA Technical Reports Server (NTRS)

Sullivan, Roy M.

2004-01-01

A mathematical theory and an accompanying numerical scheme have been developed for predicting the oxidation behavior of carbon silicon carbide (C/SiC) composite structures. The theory is derived from the mechanics of the flow of ideal gases through a porous solid. The result of the theoretical formulation is a set of two coupled nonlinear differential equations written in terms of the oxidant and oxide partial pressures. The differential equations are solved simultaneously to obtain the partial vapor pressures of the oxidant and oxides as a function of the spatial location and time. The local rate of carbon oxidation is determined using the map of the local oxidant partial vapor pressure along with the Arrhenius rate equation. The nonlinear differential equations are cast into matrix equations by applying the Bubnov-Galerkin weighted residual method, allowing for the solution of the differential equations numerically. The numerical method is demonstrated by utilizing the method to model the carbon oxidation and weight loss behavior of C/SiC specimens during thermogravimetric experiments. The numerical method is used to study the physics of carbon oxidation in carbon silicon carbide composites.

Waveguide based compact silicon Schottky photodetector with enhanced responsivity in the telecom spectral band.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2012-12-17

We experimentally demonstrate an on-chip compact and simple to fabricate silicon Schottky photodetector for telecom wavelengths operating on the basis of internal photoemission process. The device is realized using CMOS compatible approach of local-oxidation of silicon, which enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. The photodetector demonstrates enhanced internal responsivity of 12.5mA/W for operation wavelength of 1.55µm corresponding to an internal quantum efficiency of 1%, about two orders of magnitude higher than our previously demonstrated results [22]. We attribute this improved detection efficiency to the presence of surface roughness at the boundary between the materials forming the Schottky contact. The combination of enhanced quantum efficiency together with a simple fabrication process provides a promising platform for the realization of all silicon photodetectors and their integration with other nanophotonic and nanoplasmonic structures towards the construction of monolithic silicon opto-electronic circuitry on-chip.

NbN superconducting nanonetwork fabricated using porous silicon templates and high-resolution electron beam lithography

NASA Astrophysics Data System (ADS)

Salvato, M.; Baghdadi, R.; Cirillo, C.; Prischepa, S. L.; Dolgiy, A. L.; Bondarenko, V. P.; Lombardi, F.; Attanasio, C.

2017-11-01

Superconducting NbN nanonetworks with a very small number of interconnected nanowires, with diameter of the order of 4 nm, are fabricated combining a bottom-up (use of porous silicon nanotemplates) with a top-down technique (high-resolution electron beam lithography). The method is easy to control and allows the fabrication of devices, on a robust support, with electrical properties close to a one-dimensional superconductor that can be used fruitfully for novel applications.

Structural evolution in Ar+ implanted Si-rich silicon oxide

NASA Astrophysics Data System (ADS)

Brusa, R. S.; Karwasz, G. P.; Mariotto, G.; Zecca, A.; Ferragut, R.; Folegati, P.; Dupasquier, A.; Ottaviani, G.; Tonini, R.

2003-12-01

Silicon-rich silicon oxide films were deposited by plasma-enhanced chemical vapor deposition. Energy was released into the film by ion bombardment, with the aim of promoting formation of Si nanoclusters and reordering the oxide matrix. The effect of the initial stoichiometry, as well as the evolution of the oxide films due to the ion bombardment and to subsequent thermal treatments, has been studied by depth-resolved positron annihilation Doppler spectroscopy, Raman scattering and Fourier transform infrared spectroscopy. As-deposited films were found to contain an open volume fraction in the form of subnanometric cavities that are positively correlated with oxygen deficiency. No Si aggregates were observed. The ion bombardment was found to promote the formation of amorphous Si nanoclusters, together with a reduction of the open volume in the matrix and a substantial release of hydrogen. It also leaves electrically active sites in the oxide and produces gas-filled vacancy defects in the substrate, with the concentrations depending on the implantation temperature. Thermal treatment at 500 °C removes charge defects in the oxide, but vacancy defects are not completely annealed even at 1100 °C. In one case, heating at 1100 °C produced cavities of about 0.6 nm in the oxide. Transformation of Si nanoclusters into nanocrystals is observed to occur from 800 °C.

Cobalt germanide nanostructure formation and memory characteristic enhancement in silicon oxide films

NASA Astrophysics Data System (ADS)

Joo, Beom Soo; Kim, Hyunseung; Jang, Seunghun; Han, Dongwoo; Han, Moonsup

2018-08-01

We investigated nano-floating gate memory having a charge trap layer (CTL) composed of cobalt germanide nanostructure (ns-CoGe). A tunneling oxide layer; a CTL containing Co, Ge, and Si; and a blocking oxide layer were sequentially deposited on a p-type silicon substrate by RF magnetron sputtering and low-pressure chemical vapor deposition. We optimized the CTL formation conditions by rapid thermal annealing at a somewhat low temperature (about 830 °C) by considering the differences in Gibbs free energy and chemical enthalpy among the components. To characterize the charge storage properties, capacitance-voltage (C-V) measurements were performed. Further, we used X-ray photoelectron spectroscopy for chemical analysis of the CTL. In this work, we not only report that the C-V measurement shows a remarkable opening of the memory window for the ns-CoGe compared with those of nanostructures composed of Co or Ge alone, but also clarify that the improvement in the memory characteristics originates in the nanostructure formation, which consists mainly of Co-Ge bonds. We expect ns-CoGe to be a strong candidate for fabrication of next-generation memory devices.

Electroluminescent Yb2O3:Er and Yb2Si2O7:Er nanolaminate films fabricated by atomic layer deposition on silicon

NASA Astrophysics Data System (ADS)

Ouyang, Zhongtao; Yang, Yang; Sun, Jiaming

2018-06-01

Atomic layer doped Yb2O3:Er and Yb2Si2O7:Er nanolaminate films are fabricated on silicon by atomic layer deposition, and ∼1530 nm electroluminescence (EL) is obtained from the metal-oxide-semiconductor light-emitting devices (MOSLEDs) based on these films. The Yb2O3 films transfer to Yb2Si2O7 phase after annealing above 1000 °C. Intense photoluminescence from Yb2Si2O7 film confirms high efficiency and energy transfer under optical excitation, but the limited electron conduction restricts the EL performance. EL from the Yb2O3:Er MOSLED outperforms, presenting an external quantum efficiency up to 8.5% and the power efficiency of 1 × 10-3. The EL is derived to result from the impact excitation of Er3+ ions by hot electrons, which stem from Fowler-Nordheim tunneling mechanism under sufficient bias voltage. The critical distance for the cross relaxation of doped Er3+ ions in nanolaminate Yb2O3 matrix is experimentally determined to be ∼3 nm. Such devices manifest the technological potential of Er-doped Yb-oxides for applications in silicon-based optoelectronics.

Postfabrication Phase Error Correction of Silicon Photonic Circuits by Single Femtosecond Laser Pulses

DOE PAGES

Bachman, Daniel; Chen, Zhijiang; Wang, Christopher; ...

2016-11-29

Phase errors caused by fabrication variations in silicon photonic integrated circuits are an important problem, which negatively impacts device yield and performance. This study reports our recent progress in the development of a method for permanent, postfabrication phase error correction of silicon photonic circuits based on femtosecond laser irradiation. Using beam shaping technique, we achieve a 14-fold enhancement in the phase tuning resolution of the method with a Gaussian-shaped beam compared to a top-hat beam. The large improvement in the tuning resolution makes the femtosecond laser method potentially useful for very fine phase trimming of silicon photonic circuits. Finally, wemore » also show that femtosecond laser pulses can directly modify silicon photonic devices through a SiO 2 cladding layer, making it the only permanent post-fabrication method that can tune silicon photonic circuits protected by an oxide cladding.« less

Design, fabrication, and characterization of 4H-silicon carbide rectifiers for power switching applications

NASA Astrophysics Data System (ADS)

Sheridan, David Charles

Silicon Carbide has received a substantial increase in research interest over the past few years as a base material system for high-frequency and high-power semiconductor devices. Of the over 1200 polytypes, 4H-SiC is the most attractive polytype for power devices due to its wide band gap (3.2eV), excellent thermal conductivity (4.9 W/cm·K), and high critical field strength (˜2 x 106 V/cm). Important for power devices, the 10x increase in critical field strength of SiC allows high voltage blocking layers to be fabricated significantly thinner than for comparable Si devices. For power rectifiers, this reduces device on-resistance, while maintaining the same high voltage blocking capability. In this work, 4H-SiC Schottky, pn, and junction barrier Schottky (JBS) rectifiers for use in high voltage switching applications have been designed, fabricated, and extensively characterized. First, a detailed review of 4H-SiC material parameters was performed and SiC models were implemented into a standard Si drift-diffusion numerical simulator. Using these models, a SiC simulation methodology was developed in order to enable predictive SiC device design. A wide variety of rectifier and edge termination designs were investigated and optimized with respect to breakdown efficiency, area consumption, resistance to interface charge, and fabrication practicality. Simulated termination methods include: field plates, floating guard rings, and a variety of junction termination extensions (JTE). Using the device simulation results, both Schottky and JBS rectifiers were fabricated with a novel self-aligned edge termination design, and fabricated with process elements developed at the Alabama Microelectronics Science and Technology Center facility. These rectifiers exhibited near-ideal forward characteristics and had blocking voltages in excess of 2.5kV. The SiC diodes were subjected to inductive switching tests, and were found to have superior reverse recovery characteristics compared

Bio-inspired silicon nanospikes fabricated by metal-assisted chemical etching for antibacterial surfaces

NASA Astrophysics Data System (ADS)

Hu, Huan; Siu, Vince S.; Gifford, Stacey M.; Kim, Sungcheol; Lu, Minhua; Meyer, Pablo; Stolovitzky, Gustavo A.

2017-12-01

The recently discovered bactericidal properties of nanostructures on wings of insects such as cicadas and dragonflies have inspired the development of similar nanostructured surfaces for antibacterial applications. Since most antibacterial applications require nanostructures covering a considerable amount of area, a practical fabrication method needs to be cost-effective and scalable. However, most reported nanofabrication methods require either expensive equipment or a high temperature process, limiting cost efficiency and scalability. Here, we report a simple, fast, low-cost, and scalable antibacterial surface nanofabrication methodology. Our method is based on metal-assisted chemical etching that only requires etching a single crystal silicon substrate in a mixture of silver nitrate and hydrofluoric acid for several minutes. We experimentally studied the effects of etching time on the morphology of the silicon nanospikes and the bactericidal properties of the resulting surface. We discovered that 6 minutes of etching results in a surface containing silicon nanospikes with optimal geometry. The bactericidal properties of the silicon nanospikes were supported by bacterial plating results, fluorescence images, and scanning electron microscopy images.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

One-Step Formation of Silicon-Graphene Composites from Silicon Sludge Waste and Graphene Oxide via Aerosol Process for Lithium Ion Batteries

PubMed Central

Kim, Sun Kyung; Kim, Hyekyoung; Chang, Hankwon; Cho, Bong-Gyoo; Huang, Jiaxing; Yoo, Hyundong; Kim, Hansu; Jang, Hee Dong

2016-01-01

Over 40% of high-purity silicon (Si) is consumed as sludge waste consisting of Si, silicon carbide (SiC) particles and metal impurities from the fragments of cutting wire mixed in ethylene glycol based cutting fluid during Si wafer slicing in semiconductor fabrication. Recovery of Si from the waste Si sludge has been a great concern because Si particles are promising high-capacity anode materials for Li ion batteries. In this study, we report a novel one-step aerosol process that not only extracts Si particles but also generates Si-graphene (GR) composites from the colloidal mixture of waste Si sludge and graphene oxide (GO) at the same time by ultrasonic atomization-assisted spray pyrolysis. This process supports many advantages such as eco-friendly, low-energy, rapid, and simple method for forming Si-GR composite. The morphology of the as-formed Si-GR composites looked like a crumpled paper ball and the average size of the composites varied from 0.6 to 0.8 μm with variation of the process variables. The electrochemical performance was then conducted with the Si-GR composites for Lithium Ion Batteries (LIBs). The Si-GR composites exhibited very high performance as Li ion battery anodes in terms of capacity, cycling stability, and Coulombic efficiency. PMID:27646853

Low-temperature silicon thin films for large-area electronics: Device fabrication using soft lithography and laser-crystallization by sequential lateral solidification

NASA Astrophysics Data System (ADS)

Jin, Hyun-Chul

This work demonstrates possible routes for fabricating large-area electronic devices on glass or plastic substrates using low-temperature materials deposition and soft lithographic device patterning. Hydrogenated amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) have been extensively studied as the semiconducting material for flat panel displays and solar cells. On glass substrates, we have deposited a-Si:H films at a temperature lower than 125°C, and we have used pulsed excimer laser crystallization in the sequential lateral solidification (SLS) regime to fabricate poly-Si films. We use micromolding in capillaries (MIMIC), a form of soft lithography involving micrometer-scale polymer molding, as a means to fabricate amorphous silicon thin-film transistors (TFTs), and photoconductive sensor arrays on both planar and curved substrates. The use of non-planar substrates has captured considerable attention in the field because it would open up new applications and new designs. Field-effect transistors made by SLS poly-Si show excellent mobility and on/off current ratio; however, the microstructure of the material had never been well documented. We determined the microtexture using electron backscattering diffraction (EBSD): the first crystallites formed in the a-Si layer are random; along the direction of the solidification, a strong <100> in-plane orientation quickly develops due to competitive growth and occlusion. The misorientation angle between neighboring grains is also analyzed. A large fraction of the boundaries within the material are low-angle and coincidence site lattice (CSL) types. We discuss the implications of the findings on the defect generation mechanism and on the electrical properties of the films. We have analyzed the electrical properties of SLS poly-Si films on oxidized Si wafer using the pseudo-MOSFET geometry; the majority carrier mobility is extracted from the transconductance. However, the data are non-ideal due to large

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

NASA Astrophysics Data System (ADS)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Fabrication of implantable microelectrode arrays by laser cutting of silicone rubber and platinum foil.

PubMed

Schuettler, M; Stiess, S; King, B V; Suaning, G J

2005-03-01

A new method for fabrication of microelectrode arrays comprised of traditional implant materials is presented. The main construction principle is the use of spun-on medical grade silicone rubber as insulating substrate material and platinum foil as conductor (tracks, pads and electrodes). The silicone rubber and the platinum foil are patterned by laser cutting using an Nd:YAG laser and a microcontroller-driven, stepper-motor operated x-y table. The method does not require expensive clean room facilities and offers an extremely short design-to-prototype time of below 1 day. First prototypes demonstrate a minimal achievable feature size of about 30 microm.

Tuning of structural, light emission and wetting properties of nanostructured copper oxide-porous silicon matrix formed on electrochemically etched copper-coated silicon substrates

NASA Astrophysics Data System (ADS)

Naddaf, M.

2017-01-01

Matrices of copper oxide-porous silicon nanostructures have been formed by electrochemical etching of copper-coated silicon surfaces in HF-based solution at different etching times (5-15 min). Micro-Raman, X-ray diffraction and X-ray photoelectron spectroscopy results show that the nature of copper oxide in the matrix changes from single-phase copper (I) oxide (Cu2O) to single-phase copper (II) oxide (CuO) on increasing the etching time. This is accompanied with important variation in the content of carbon, carbon hydrides, carbonyl compounds and silicon oxide in the matrix. The matrix formed at the low etching time (5 min) exhibits a single broad "blue" room-temperature photoluminescence (PL) band. On increasing the etching time, the intensity of this band decreases and a much stronger "red" PL band emerges in the PL spectra. The relative intensity of this band with respect to the "blue" band significantly increases on increasing the etching time. The "blue" and "red" PL bands are attributed to Cu2O and porous silicon of the matrix, respectively. In addition, the water contact angle measurements reveal that the hydrophobicity of the matrix surface can be tuned from hydrophobic to superhydrophobic state by controlling the etching time.

Characterization of zinc oxide thin film for pH detector

NASA Astrophysics Data System (ADS)

Hashim, Uda; Fathil, M. F. M.; Arshad, M. K. Md; Gopinath, Subash C. B.; Uda, M. N. A.

2017-03-01

This paper presents the fabrication process of the zinc oxide thin films for using to act as pH detection by using different PH solution. Sol-gel solution technique is used for preparing zinc oxide seed solution, followed by metal oxide deposition process by using spin coater on the silicon dioxide. Silicon dioxide layer is grown on the silicon wafer, then, ZnO seed solution is deposited on the silicon layer, baked, and annealing process carried on to undergo the characterization of its surface morphology, structural and crystalline phase. Electrical characterization is showed by using PH 4, 7, and 10 is dropped on the surface of the die, in addition, APTES solution is used as linker and also as a references of the electrical characterization.

[Effect of surface organic modified nano-silicon-oxide on mechanical properties of A-2186 silicone elastomers].

PubMed

Guo, Nan; Jiao, Ting

2011-08-01

To study the effect of surface organic modified nano-silicon-oxide (SiO(x)) on mechanical properties of A-2186 silicone elastomers. Surface organic modified nano-silicon-oxide (SiO(x)) was added into A-2186 silicone elastomers by weight percentage of 2%, 4% and 6%. The one without addition served as a control. Standard specimens were made according to American Society for Testing Materials (ASTM). Their tensile strength, elongation at break, tear strength, and Shore A hardness were measured. The results were analyzed statistically by SPSS 10.0 software package. The tensile strength in the experimental groups was significantly lower than the control group (P<0.001).The elongation in the experimental groups was lower than the control group, but there was no significant difference between the 2wt% group and the control group (P=0.068). The tear strength in both the 2wt= group and 4wt= group were higher than the control group, and the difference was statistically significant; in addition, the tear strength in 2wt= group was higher than 4wt= group, which also showed statistical significance (P<0.001). With the increase of the added amount of surface modified nano-SiO(x), Shore A hardness increased and there was significant difference among them (P<0.001). Adding surface modified nano-SiO(x) has an effect on mechanical properties of A-2186 silicone elastomer, when 2wt= and 4wt= are added, tear strength of A-2186 improves significantly, with an increase of Shore A hardness and an decrease of tensile strength.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

A silicon nanowire-reduced graphene oxide composite as a high-performance lithium ion battery anode material.

PubMed

Ren, Jian-Guo; Wang, Chundong; Wu, Qi-Hui; Liu, Xiang; Yang, Yang; He, Lifang; Zhang, Wenjun

2014-03-21

Toward the increasing demands of portable energy storage and electric vehicle applications, silicon has been emerging as a promising anode material for lithium-ion batteries (LIBs) owing to its high specific capacity. However, serious pulverization of bulk silicon during cycling limits its cycle life. Herein, we report a novel hierarchical Si nanowire (Si NW)-reduced graphene oxide (rGO) composite fabricated using a solvothermal method followed by a chemical vapor deposition process. In the composite, the uniform-sized [111]-oriented Si NWs are well dispersed on the rGO surface and in between rGO sheets. The flexible rGO enables us to maintain the structural integrity and to provide a continuous conductive network of the electrode, which results in over 100 cycles serving as an anode in half cells at a high lithium storage capacity of 2300 mA h g(-1). Due to its [111] growth direction and the large contact area with rGO, the Si NWs in the composite show substantially enhanced reaction kinetics compared with other Si NWs or Si particles.

Fabrication of a symmetric micro supercapacitor based on tubular ruthenium oxide on silicon 3D microstructures

NASA Astrophysics Data System (ADS)

Wang, Xiaofeng; Yin, Yajiang; Li, Xiangyu; You, Zheng

2014-04-01

A micro-supercapacitor with a three-dimensional configuration has been fabricated using an ICP etching technique. Hydrous ruthenium oxide with a tubular morphology is successfully synthesized using a cathodic deposition technique with a Si micro prominence as a template. The desired tubular RuO2·xH2O architecture facilitates electrolyte penetration and proton exchange/diffusion. A single MEMS electrode is studied using cyclic voltammetry, and a specific capacitance of 99.3 mF cm-2 and 70 F g-1 is presented at 5 mV s-1 in neutral Na2SO4 solution. The accelerated cycle life is tested at 80 mV s-1, and satisfactory cyclability is observed. When placed on a chip, the symmetric cell exhibits good supercapacitor properties, and a specific capacitance as high as 23 mF cm-2 is achieved at 10 mA cm-2. Therefore, 3D MEMS microelectrode arrays with electrochemically deposited ruthenium oxide films are promising candidates for on-chip electrochemical micro-capacitor applications.

Atomic-Layer-Deposited Transparent Electrodes for Silicon Heterojunction Solar Cells

DOE PAGES

Demaurex, Benedicte; Seif, Johannes P.; Smit, Sjoerd; ...

2014-11-01

We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing,more » between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection.« less

Impact of Parameter Variation in Fabrication of Nanostructure by Atomic Force Microscopy Nanolithography

PubMed Central

Dehzangi, Arash; Larki, Farhad; Hutagalung, Sabar D.; Goodarz Naseri, Mahmood; Majlis, Burhanuddin Y.; Navasery, Manizheh; Hamid, Norihan Abdul; Noor, Mimiwaty Mohd

2013-01-01

In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (1015 cm−3) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are implemented to reach the structures. The impact of contributing parameters in oxidation such as tip materials, applying voltage on the tip, relative humidity and exposure time are studied. The effect of the etchant concentration (10% to 30% wt) of potassium hydroxide and its mixture with isopropyl alcohol (10%vol. IPA ) at different temperatures on silicon surface are expressed. For different KOH concentrations, the effect of etching with the IPA admixture and the effect of the immersing time in the etching process on the structure are investigated. The etching processes are accurately optimized by 30%wt. KOH +10%vol. IPA in appropriate time, temperature, and humidity. PMID:23776479

Method of fabrication of display pixels driven by silicon thin film transistors

DOEpatents

Carey, Paul G.; Smith, Patrick M.

1999-01-01

Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

Viscous properties of aluminum oxide nanotubes and aluminium oxide nanoparticles - silicone oil suspensions

NASA Astrophysics Data System (ADS)

Thapa, Ram; French, Steven; Delgado, Adrian; Ramos, Carlos; Gutierrez, Jose; Chipara, Mircea; Lozano, Karen

2010-03-01

Electrorheological (ER) fluids consisting of γ-aluminum oxide nanotubes and γ-aluminum oxide nanoparticles dispersed within silicone oil were prepared. The relationship between shear stress and shear rate was measured and theoretically simulated by using an extended Bingham model for both the rheological and electrorheological features of these systems. Shear stress and viscosity showed a sharp increase for the aluminum oxide nanotubes suspensions subjected to applied electric fields whereas aluminum oxide nanoparticles suspensions showed a moderate change. It was found that the transition from liquid to solid state (mediated by the applied electric field) can be described by a power law and that for low applied voltages the relationship is almost linear.

Nitric oxide-generating silicone as a blood-contacting biomaterial

PubMed Central

Amoako, Kagya A.; Cook, Keith E.

2011-01-01

Coagulation upon blood-contacting biomaterials remains a problem for short and long-term clinical applications. This study examined the ability of copper(II)-doped silicone surfaces to generate nitric oxide (NO) and locally inhibit coagulation. Silicone was doped with 3-micron copper (Cu(0)) particles yielding 3 to 10 weight percent (wt%) Cu in 70-μm thick Cu/Silicone polymeric matrix composites (Cu/Si PMCs). At 3, 5, 8 and 10 wt% Cu doping, the surface expression of Cu was 12.1 ± 2.8%, 19.7 ± 5.4%, 29.0 ± 3.8%, and 33.8 ± 6.5% respectively. After oxidizing Cu(0) to Cu(II) by spontaneous corrosion, NO flux, JNO (mol*cm−2*min−1), as measured by chemiluminescence, increased with surface Cu expression according to the relationship JNO =(1.63 %SACu −0.81) ×10−11, R2 = 0.98 where %SACu is the percentage of surface occupied by Cu. NO flux at 10 wt% Cu was 5.35± 0.74 ×10−10 mol*cm−2*min−1. The clotting time of sheep blood exposed to these surfaces was 80 ± 13s with pure silicone and 339 ± 44s when 10 wt% Cu(II) was added. SEMs of coatings showed clots occurred away from exposed Cu-dendrites. In conclusion, Cu/Si PMCs inhibit coagulation in a dose-dependent fashion related to the extent of copper exposure on the coated surface. PMID:22036723

Fluorescence of silicon nanoparticles prepared by nanosecond pulsed laser

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Chunyang, E-mail: chunyangliu@126.com; Sui, Xin; Yang, Fang

2014-03-15

A pulsed laser fabrication method is used to prepare fluorescent microstructures on silicon substrates in this paper. A 355 nm nanosecond pulsed laser micromachining system was designed, and the performance was verified and optimized. Fluorescence microscopy was used to analyze the photoluminescence of the microstructures which were formed using the pulsed laser processing technique. Photoluminescence spectra of the microstructure reveal a peak emission around 500 nm, from 370 nm laser irradiation. The light intensity also shows an exponential decay with irradiation time, which is similar to attenuation processes seen in porous silicon. The surface morphology and chemical composition of themore » microstructure in the fabricated region was also analyzed with multifunction scanning electron microscopy. Spherical particles are produced with diameters around 100 nm. The structure is compared with porous silicon. It is likely that these nanoparticles act as luminescence recombination centers on the silicon surface. The small diameter of the particles modifies the band gap of silicon by quantum confinement effects. Electron-hole pairs recombine and the fluorescence emission shifts into the visible range. The chemical elements of the processed region are also changed during the interaction between laser and silicon. Oxidation and carbonization play an important role in the enhancement of fluorescence emission.« less

Fabrication of through-silicon via arrays by photo-assisted electrochemical etching and supercritical electroplating

NASA Astrophysics Data System (ADS)

Chuang, Ho-Chiao; Yang, Hsi-Min; Wu, Cheng-Xiang; Sanchez, Jorge; Shyu, Jenq-Huey

2017-01-01

This paper aims to fabricate high aspect ratio through silicon via (TSV) by photo-assisted electrochemical etching (PAECE) and supercritical CO2 copper electroplating. A blind-holed silicon array was first fabricated by PAECE. By studying the etching parameters, including hydrofluoric acid concentration, etchant temperature, stirring speed, tetrabutylammonium perchlorate (TBAP) content, and Ohmic contact thickness, an array of pores with a 1∶45 aspect ratio (height=250 μm and diameter=5.5 μm) was obtained successfully. Moreover, TBAP and Kodak Photo-Flo (PF) solution were added into the etchant to acquire smooth sidewalls for the first time. TBAP was added for the first time to serve as an antistatic agent in deionized water-based etchant to prevent side-branch etching, and PF was used to degasify hydrogen bubbles in the etchant. The effect of gold thickness over Ohmic contact was investigated. Randomized etching was observed with an Au thickness of 200 Å, but it can be improved by increasing the etching voltage. The silicon mold of through-holes was filled with metal using supercritical CO2 copper electroplating, which features high diffusivity, permeability, and density. The TSV structure (aspect ratio=1∶35) was obtained at a supercritical pressure of 2000 psi, temperature of 50°C, and current density of 30 mA/cm2 in 2.5 h.

Oxidation effects on the mechanical properties of SiC fiber-reinforced reaction-bonded silicon nitride matrix composites

NASA Technical Reports Server (NTRS)

Bhatt, Ramakrishna T.

1989-01-01

The room temperature mechanical properties of SiC fiber reinforced reaction bonded silicon nitride composites were measured after 100 hrs exposure at temperatures to 1400 C in nitrogen and oxygen environments. The composites consisted of approx. 30 vol percent uniaxially aligned 142 micron diameter SiC fibers in a reaction bonded Si3N4 matrix. The results indicate that composites heat treated in a nitrogen environment at temperatures to 1400 C showed deformation and fracture behavior equivalent to that of the as-fabricated composites. Also, the composites heat treated in an oxidizing environment beyond 400 C yielded significantly lower tensile strength values. Specifically in the temperature range from 600 to 1000 C, composites retained approx. 40 percent of their as-fabricated strength, and those heat treated in the temperatures from 1200 to 1400 C retained 70 percent. Nonetheless, for all oxygen heat treatment conditions, composite specimens displayed strain capability beyond the matrix fracture stress; a typical behavior of a tough composite.

A novel 2D silicon nano-mold fabrication technique for linear nanochannels over a 4 inch diameter substrate

PubMed Central

Yin, Zhifu; Qi, Liping; Zou, Helin; Sun, Lei

2016-01-01

A novel low-cost 2D silicon nano-mold fabrication technique was developed based on Cu inclined-deposition and Ar+ (argon ion) etching. With this technique, sub-100 nm 2D (two dimensional) nano-channels can be etched economically over the whole area of a 4 inch n-type <100> silicon wafer. The fabricating process consists of only 4 steps, UV (Ultraviolet) lithography, inclined Cu deposition, Ar+ sputter etching, and photoresist & Cu removing. During this nano-mold fabrication process, we investigated the influence of the deposition angle on the width of the nano-channels and the effect of Ar+ etching time on their depth. Post-etching measurements showed the accuracy of the nanochannels over the whole area: the variation in width is 10%, in depth it is 11%. However, post-etching measurements also showed the accuracy of the nanochannels between chips: the variation in width is 2%, in depth it is 5%. With this newly developed technology, low-cost and large scale 2D nano-molds can be fabricated, which allows commercial manufacturing of nano-components over large areas. PMID:26752559

Effect of tetramethylammonium hydroxide/isopropyl alcohol wet etching on geometry and surface roughness of silicon nanowires fabricated by AFM lithography

PubMed Central

Yusoh, Siti Noorhaniah

2016-01-01

Summary The optimization of etchant parameters in wet etching plays an important role in the fabrication of semiconductor devices. Wet etching of tetramethylammonium hydroxide (TMAH)/isopropyl alcohol (IPA) on silicon nanowires fabricated by AFM lithography is studied herein. TMAH (25 wt %) with different IPA concentrations (0, 10, 20, and 30 vol %) and etching time durations (30, 40, and 50 s) were investigated. The relationships between etching depth and width, and etching rate and surface roughness of silicon nanowires were characterized in detail using atomic force microscopy (AFM). The obtained results indicate that increased IPA concentration in TMAH produced greater width of the silicon nanowires with a smooth surface. It was also observed that the use of a longer etching time causes more unmasked silicon layers to be removed. Importantly, throughout this study, wet etching with optimized parameters can be applied in the design of the devices with excellent performance for many applications. PMID:27826521

Preparation of silicon carbide fibers

DOEpatents

Wei, G.C.

1983-10-12

Silicon carbide fibers suitable for use in the fabrication of dense, high-strength, high-toughness SiC composites or as thermal insulating materials in oxidizing environments are fabricated by a new, simplified method wherein a mixture of short-length rayon fibers and colloidal silica is homogenized in a water slurry. Water is removed from the mixture by drying in air at 120/sup 0/C and the fibers are carbonized by (pyrolysis) heating the mixture to 800 to 1000/sup 0/C in argon. The mixture is subsequently reacted at 1550 to 1900/sup 0/C in argon to yield pure ..beta..-SiC fibers.

Single-crystal silicon trench etching for fabrication of highly integrated circuits

NASA Astrophysics Data System (ADS)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

Oxidation of Chemically-Vapor-Deposited Silicon Carbide in Carbon Dioxide

NASA Technical Reports Server (NTRS)

Opila, Elizabeth J.; Nguyen, QuynhGiao N.

1998-01-01

Chemically-vapor-deposited silicon carbide (CVD SiC) was oxidized in carbon dioxide (CO2) at temperatures of 1200-1400 C for times between 96 and 500 h at several gas flow rates. Oxidation weight gains were monitored by thermogravimetric analysis (TGA) and were found to be very small and independent of temperature. Possible rate limiting kinetic mechanisms are discussed. Passive oxidation of SiC by CO2 is negligible compared to the rates measured for other oxidants that are also found in combustion environments, oxygen and water vapor.

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

NASA Astrophysics Data System (ADS)

Fan, Ji; Zhang, Wen Ting; Liu, Jin Quan; Wu, Wen Jie; Zhu, Tao; Tu, Liang Cheng

2015-04-01

We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactive-ion etching, a HAR (˜25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

Preparation of rich handles soft cellulosic fabric using amino silicone based softener, part II: colorfastness properties.

PubMed

Zuber, Mohammad; Zia, Khalid Mahmood; Tabassum, Shazia; Jamil, Tahir; Barkaat-Ul-Hasin, Syed; Khosa, Muhammad Kaleem

2011-07-01

The preparation of amino silicone based softeners with different emulsifiers was carried out and adsorbed onto the surfaces of cotton and blends of cotton/polyester fabrics. The softened fabrics have high surface area, so poorly performance in washing and rubbing fastness. It is obvious from the results of colorfastness to rubbing and washing that some of the samples of the dyed fabric treated with prepared softeners have shown some poor rating as compared to the untreated fabrics. However the other two samples have shown acceptable rubbing fastness results without losing softness and permanent handle. It can be observed that washing of the printed treated fabric remains unaffected almost in all the studied samples. Moreover, the application of the prepared softeners has imparted anti pilling property to the fabric. It can be seen that there is a remarkable increase in weights of treated fabrics as compared to the untreated fabrics. Copyright © 2011 Elsevier B.V. All rights reserved.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Structurally stable, thin silicon solar cells

NASA Technical Reports Server (NTRS)

Arndt, R. A.; Meulenberg, A.

1984-01-01

A fabrication process for structurally stable thin solar cell wafers that produce good power output after irradiation is described. The fabrication process is as follows. A 6 mil, circular wafer is oxidized on both sides. One side is then patterned with a rectangular array of holes in the oxide that are nominally 75 mils square and separated by 2 mil spacings. Wells are then etched into the silicon with KOH to a depth of 4 mils, leaving a 2 mil, unetched thickness. Two areas on the surface are left unetched to provide pads for bonding or testing. All oxide is then removed and the rest of the processing is normal; the unetched face is used as the illuminated face. When all other processing is complete, a 2 X 2 cm cell is sawed from the starting wafer leaving a border that is approximately 10 mils wide. The effective thickness, determined by weighing an unmetallized sample, of such a cell is about 2.4 mil.

Fabrication of porous silicon nanowires by MACE method in HF/H2O2/AgNO3 system at room temperature

PubMed Central

2014-01-01

In this paper, the moderately and lightly doped porous silicon nanowires (PSiNWs) were fabricated by the ‘one-pot procedure’ metal-assisted chemical etching (MACE) method in the HF/H2O2/AgNO3 system at room temperature. The effects of H2O2 concentration on the nanostructure of silicon nanowires (SiNWs) were investigated. The experimental results indicate that porous structure can be introduced by the addition of H2O2 and the pore structure could be controlled by adjusting the concentration of H2O2. The H2O2 species replaces Ag+ as the oxidant and the Ag nanoparticles work as catalyst during the etching. And the concentration of H2O2 influences the nucleation and motility of Ag particles, which leads to formation of different porous structure within the nanowires. A mechanism based on the lateral etching which is catalyzed by Ag particles under the motivation by H2O2 reduction is proposed to explain the PSiNWs formation. PMID:24910568

Fabricating solar cells with silicon nanoparticles

DOEpatents

Loscutoff, Paul; Molesa, Steve; Kim, Taeseok

2014-09-02

A laser contact process is employed to form contact holes to emitters of a solar cell. Doped silicon nanoparticles are formed over a substrate of the solar cell. The surface of individual or clusters of silicon nanoparticles is coated with a nanoparticle passivation film. Contact holes to emitters of the solar cell are formed by impinging a laser beam on the passivated silicon nanoparticles. For example, the laser contact process may be a laser ablation process. In that case, the emitters may be formed by diffusing dopants from the silicon nanoparticles prior to forming the contact holes to the emitters. As another example, the laser contact process may be a laser melting process whereby portions of the silicon nanoparticles are melted to form the emitters and contact holes to the emitters.

The effect of nanocrystalline silicon host on magnetic properties of encapsulated iron oxide nanoparticles.

PubMed

Granitzer, P; Rumpf, K; Gonzalez-Rodriguez, R; Coffer, J L; Reissner, M

2015-12-21

The purpose of this work is a detailed comparison of the fundamental magnetic properties of nanocomposite systems consisting of Fe3O4 nanoparticle-loaded porous silicon as well as silicon nanotubes. Such composite structures are of potential merit in the area of magnetically guided drug delivery. For magnetic systems to be utilized in biomedical applications, there are certain magnetic properties that must be fulfilled. Therefore magnetic properties of embedded Fe3O4-nanoparticles in these nanostructured silicon host matrices, porous silicon and silicon nanotubes, are investigated. Temperature-dependent magnetic investigations have been carried out for four types of iron oxide particle sizes (4, 5, 8 and 10 nm). The silicon host, in interplay with the iron oxide nanoparticle size, plays a sensitive role. It is shown that Fe3O4 loaded porous silicon and SiNTs differ significantly in their magnetic behavior, especially the transition between superparamagnetic behavior and blocked state, due to host morphology-dependent magnetic interactions. Importantly, it is found that all investigated samples meet the magnetic precondition of possible biomedical applications of exhibiting a negligible magnetic remanence at room temperature.

Interference lithographically defined and catalytically etched, large-area silicon nanocones from nanowires.

PubMed

Dawood, M K; Liew, T H; Lianto, P; Hong, M H; Tripathy, S; Thong, J T L; Choi, W K

2010-05-21

We report a simple and cost effective method for the synthesis of large-area, precisely located silicon nanocones from nanowires. The nanowires were obtained from our interference lithography and catalytic etching (IL-CE) method. We found that porous silicon was formed near the Au catalyst during the fabrication of the nanowires. The porous silicon exhibited enhanced oxidation ability when exposed to atmospheric conditions or in wet oxidation ambient. Very well located nanocones with uniform sharpness resulted when these oxidized nanowires were etched in 10% HF. Nanocones of different heights were obtained by varying the doping concentration of the silicon wafers. We believe this is a novel method of producing large-area, low cost, well defined nanocones from nanowires both in terms of the control of location and shape of the nanocones. A wide range of potential applications of the nanocone array can be found as a master copy for nanoimprinted polymer substrates for possible biomedical research; as a candidate for making sharp probes for scanning probe nanolithography; or as a building block for field emitting tips or photodetectors in electronic/optoelectronic applications.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Low-Temperature UV-Assisted Fabrication of Metal Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Zhu, Shuanglin

Solution processed metal oxide semiconductors have attracted intensive attention in the last several decades and have emerged as a promising candidate for the application of thin film transistor (TFT) due to their nature of transparency, flexibility, high mobility, simple processing technique and potential low manufacturing cost. However, metal oxide thin film fabricated by solution process usually requires a high temperature (over 300 °C), which is above the glass transition temperature of some conventional polymer substrates. In order to fabricate the flexible electronic device on polymer substrates, it is necessary to find a facile approach to lower the fabrication temperature and minimize defects in metal oxide thin film. In this thesis, the electrical properties dependency on temperature is discussed and an UV-assisted annealing method incorporating Deep ultraviolet (DUV)-decomposable additives is demonstrated, which can effectively improve electrical properties solution processed metal oxide semiconductors processed at temperature as low as 220 °C. By studying a widely used indium oxide (In2O3) TFT as a model system, it is worth noted that compared with the sample without UV treatment, the linear mobility and saturation mobility of UV-annealing sample are improved by 56% and 40% respectively. Meanwhile, the subthreshold swing is decreased by 32%, indicating UV-treated device could turn on and off more efficiently. In addition to pure In2O3 film, the similar phenomena have also been observed in indium oxide based Indium-Gallium-Zinc Oxide (IGZO) system. These finding presented in this thesis suggest that the UV assisted annealing process open a new route to fabricate high performance metal oxide semiconductors under low temperatures.

Interface bonding in silicon oxide nanocontacts: interaction potentials and force measurements.

PubMed

Wierez-Kien, M; Craciun, A D; Pinon, A V; Roux, S Le; Gallani, J L; Rastei, M V

2018-04-01

The interface bonding between two silicon-oxide nanoscale surfaces has been studied as a function of atomic nature and size of contacting asperities. The binding forces obtained using various interaction potentials are compared with experimental force curves measured in vacuum with an atomic force microscope. In the limit of small nanocontacts (typically <10 3 nm 2 ) measured with sensitive probes the bonding is found to be influenced by thermal-induced fluctuations. Using interface interactions described by Morse, embedded atom model, or Lennard-Jones potential within reaction rate theory, we investigate three bonding types of covalent and van der Waals nature. The comparison of numerical and experimental results reveals that a Lennard-Jones-like potential originating from van der Waals interactions captures the binding characteristics of dry silicon oxide nanocontacts, and likely of other nanoscale materials adsorbed on silicon oxide surfaces. The analyses reveal the importance of the dispersive surface energy and of the effective contact area which is altered by stretching speeds. The mean unbinding force is found to decrease as the contact spends time in the attractive regime. This contact weakening is featured by a negative aging coefficient which broadens and shifts the thermal-induced force distribution at low stretching speeds.

Interface bonding in silicon oxide nanocontacts: interaction potentials and force measurements

NASA Astrophysics Data System (ADS)

Wierez-Kien, M.; Craciun, A. D.; Pinon, A. V.; Le Roux, S.; Gallani, J. L.; Rastei, M. V.

2018-04-01

The interface bonding between two silicon-oxide nanoscale surfaces has been studied as a function of atomic nature and size of contacting asperities. The binding forces obtained using various interaction potentials are compared with experimental force curves measured in vacuum with an atomic force microscope. In the limit of small nanocontacts (typically <103 nm2) measured with sensitive probes the bonding is found to be influenced by thermal-induced fluctuations. Using interface interactions described by Morse, embedded atom model, or Lennard-Jones potential within reaction rate theory, we investigate three bonding types of covalent and van der Waals nature. The comparison of numerical and experimental results reveals that a Lennard-Jones-like potential originating from van der Waals interactions captures the binding characteristics of dry silicon oxide nanocontacts, and likely of other nanoscale materials adsorbed on silicon oxide surfaces. The analyses reveal the importance of the dispersive surface energy and of the effective contact area which is altered by stretching speeds. The mean unbinding force is found to decrease as the contact spends time in the attractive regime. This contact weakening is featured by a negative aging coefficient which broadens and shifts the thermal-induced force distribution at low stretching speeds.

Design, fabrication, and characterization of high density silicon photonic components

NASA Astrophysics Data System (ADS)

Jones, Adam Michael

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve eciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satised by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which ecient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modied racetrack resonator is then presented enabling extraction of insertion loss data for highly ecient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.

Surface Coatings for Gas Detection via Porous Silicon

NASA Astrophysics Data System (ADS)

Ozdemir, Serdar; Li, Ji-Guang; Gole, James

2009-03-01

Nanopore covered microporous silicon interfaces have been formed via an electrochemical etch for gas sensor applications. Rapid reversible and sensitive gas sensors have been fabricated. The fabricated porous silicon (PS) gas sensors display the advantages of operation at room temperature as well as at a single, readily accessible temperature with an insensitivity to temperature drift; operation in a heat-sunk configuration, ease of coating with gas-selective materials; low cost of fabrication and operation, and the ability to rapidly assess false positives by operating the sensor in a pulsed mode. The PS surface has been modified with unique coatings on the basis of a general theory in order to achieve maximum sensitivity and selectivity. Sensing of NH3, NOx and PH3 at or below the ppm level have been observed. A typical PS nanostructure coated microstructured hybrid configuration when coated with tin oxide (NOx, CO) and gold nanostructures (NH3) provides a greatly increased sensitivity to the indicated gases. Al2O3 coating of the porous silicon using atomic layer deposition and its effect on PH3 sensing has been investigated. 20-100 nm TiO2 nanoparticles have been produced using sol-gel methods to coat PS surfaces and the effects on the selectivity and the sensitivity have been studied.

Formation of superhydrophobic/superhydrophilic patterns by combination of nanostructure-imprinted perfluoropolymer and nanostructured silicon oxide for biological droplet generation

NASA Astrophysics Data System (ADS)

Kobayashi, Taizo; Shimizu, Kazunori; Kaizuma, Yoshihiro; Konishi, Satoshi

2011-03-01

In this letter, we report a technology for fabricating superhydrophobic/superhydrophilic patterns using a combination of a nanostructure-imprinted perfluoropolymer and nanostructured silicon oxide. In our previous study, we used a combination of hydrophobic and superhydrophilic materials. However, it was difficult to split low-surface-tension liquids such as biological liquids into droplets solely using hydrophobic/hydrophilic patterns. In this study, the contact angle of the hydrophobic region was enhanced from 109.3° to 155.6° by performing nanostructure imprinting on a damage-reduced perfluoropolymer. The developed superhydrophobic/superhydrophilic patterns allowed the splitting of even those media that contained fetal bovine serum into droplets of a desired shape.

Fabrication of long-term stable superoleophobic surface based on copper oxide/cobalt oxide with micro-nanoscale hierarchical roughness

NASA Astrophysics Data System (ADS)

Barthwal, Sumit; Lim, Si-Hyung

2015-02-01

We have demonstrated a simple and cost-effective technique for the large-area fabrication of a superoleophobic surface using copper as a substrate. The whole process included three simple steps: First, the copper substrate was oxidized under hot alkaline conditions to fabricate flower-like copper oxide microspheres by heating at a particular temperature for an interval of time. Second, the copper-oxide-covered copper substrate was further heated in a solution of cobalt nitrate and ammonium nitrate in the presence of an ammonia solution to fabricate cobalt oxide nanostructures. We applied this second step to increase the surface roughness because it is an important criterion for improved superoleophobicity. Finally, to reduce the surface energy of the fabricated structures, the surfaces were chemically modified with perfluorooctyltrichlorosilane. Contact-angle measurements indicate that the micro-nano binary (MNB) hierarchical structures fabricated on the copper substrate became super-repellent toward a broad range of liquids with surface tension in the range of 21.5-72 mN/m. In an attempt to significantly improve the superoleophobic property of the surface, we also examined and compared the role of nanostructures in MNB hierarchical structures with only micro-fabricated surfaces. The fabricated MNB hierarchical structures also displays thermal stability and excellent long-term stability after exposure in air for more than 9 months. Our method might provide a general route toward the preparation of novel hierarchical films on metal substrates for various industrial applications.

Design and fabrication of absorber coupled TES microbolometers on continuous silicon-nitride windows.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, C. L.; Carlstrom, J. E.; Datesman, A.

2008-04-01

The implementation of TES based microbolometer arrays will achieve unprecedented sensitivities for mm and sub-mm astronomy through fabrication of large format arrays and improved linearity and stability arising from strong electro-thermal feedback. We report on progress in developing TES microbolometers using Mo/Au thin films and Au absorbing structures. We present measurements of suppressing the thermal conductance through the etching of features on a continuous Silicon-Nitride window.

Method for forming indium oxide/n-silicon heterojunction solar cells

DOEpatents

Feng, Tom; Ghosh, Amal K.

1984-03-13

A high photo-conversion efficiency indium oxide/n-silicon heterojunction solar cell is spray deposited from a solution containing indium trichloride. The solar cell exhibits an Air Mass One solar conversion efficiency in excess of about 10%.

SPM oxidation and parallel writing on zirconium nitride thin films

NASA Astrophysics Data System (ADS)

Farkas, N.; Comer, J. R.; Zhang, G.; Evans, E. A.; Ramsier, R. D.; Dagata, J. A.

2005-07-01

Systematic investigation of the SPM oxidation process of sputter-deposited ZrN thin films is reported. During the intrinsic part of the oxidation, the density of the oxide increases until the total oxide thickness is approximately twice the feature height. Further oxide growth is sustainable as the system undergoes plastic flow followed by delamination from the ZrN-silicon interface keeping the oxide density constant. ZrN exhibits superdiffusive oxidation kinetics in these single tip SPM studies. We extend this work to the fabrication of parallel oxide patterns 70 nm in height covering areas in the square centimeter range. This simple, quick, and well-controlled parallel nanolithographic technique has great potential for biomedical template fabrication.

Super-oxidation of silicon nanoclusters: magnetism and reactive oxygen species at the surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lepeshkin, Sergey; Baturin, Vladimir; Tikhonov, Evgeny

2016-01-01

Oxidation of silicon nanoclusters depending on the temperature and oxygen pressure is explored from first principles using the evolutionary algorithm, and structural and thermodynamic analysis. From our calculations of 90 SinOm clusters we found that under normal conditions oxidation does not stop at the stoichiometric SiO2 composition, as it does in bulk silicon, but goes further placing extra oxygen atoms on the cluster surface. These extra atoms are responsible for light emission, relevant to reactive oxygen species and many of them are magnetic. We argue that the super-oxidation effect is size-independent and discuss its relevance to nanotechnology and miscellaneous applications,more » including biomedical ones.« less

Hollow Microtube Resonators via Silicon Self-Assembly toward Subattogram Mass Sensing Applications.

PubMed

Kim, Joohyun; Song, Jungki; Kim, Kwangseok; Kim, Seokbeom; Song, Jihwan; Kim, Namsu; Khan, M Faheem; Zhang, Linan; Sader, John E; Park, Keunhan; Kim, Dongchoul; Thundat, Thomas; Lee, Jungchul

2016-03-09

Fluidic resonators with integrated microchannels (hollow resonators) are attractive for mass, density, and volume measurements of single micro/nanoparticles and cells, yet their widespread use is limited by the complexity of their fabrication. Here we report a simple and cost-effective approach for fabricating hollow microtube resonators. A prestructured silicon wafer is annealed at high temperature under a controlled atmosphere to form self-assembled buried cavities. The interiors of these cavities are oxidized to produce thin oxide tubes, following which the surrounding silicon material is selectively etched away to suspend the oxide tubes. This simple three-step process easily produces hollow microtube resonators. We report another innovation in the capping glass wafer where we integrate fluidic access channels and getter materials along with residual gas suction channels. Combined together, only five photolithographic steps and one bonding step are required to fabricate vacuum-packaged hollow microtube resonators that exhibit quality factors as high as ∼ 13,000. We take one step further to explore additionally attractive features including the ability to tune the device responsivity, changing the resonator material, and scaling down the resonator size. The resonator wall thickness of ∼ 120 nm and the channel hydraulic diameter of ∼ 60 nm are demonstrated solely by conventional microfabrication approaches. The unique characteristics of this new fabrication process facilitate the widespread use of hollow microtube resonators, their translation between diverse research fields, and the production of commercially viable devices.

Color stability of pigmented maxillofacial silicone elastomer: effects of nano-oxides as opacifiers.

PubMed

Han, Ying; Zhao, Yimin; Xie, Chao; Powers, John M; Kiat-amnuay, Sudarat

2010-01-01

This study evaluated the effects of nano-oxides on the color stability of pigmented silicone A-2186 maxillofacial prosthetic elastomers before and after artificial aging. Each of three widely used UV-shielding nano-sized particle oxides (TiO(2), ZnO, CeO(2)), based on recent survey of the industry at 1%, 2%, 2.5% concentrations were combined with each of five intrinsic silicone pigment types (no pigments, red, yellow, blue, and a mixture of the three pigments). Silicone A-2186 without nano-oxides or pigments served as control, for a total of 46 experimental groups of elastomers. In each group of the study, all specimens were aged in an artificial aging chamber for an energy exposure of 450kJ/m(2). CIE L*a*b* values were measured by a spectrophotometer. The 50:50% perceptibility (ΔE*=1.1) and acceptability threshold (ΔE*=3.0) were used in interpretation of recorded color differences. Color differences after aging were subjected to three-way analysis of variance. Means were compared by Fisher's PLSD intervals at the 0.05 level of significance. Yellow pigments mixed with all three nano-oxides at all intervals increased ΔE* values significantly from 3.7 up to 8.4. When mixed pigment groups were considered, TiO(2) at 2%, and 2.5% exhibited the smallest color changes, followed by ZnO and CeO(2), respectively (p<0.001). At 1%, CeO(2) exhibited the smallest color changes, followed by TiO(2) and ZnO, respectively (p<0.001). The smallest color differences, observed for nano-oxides groups, were recorded for CeO(2) at 1%, and TiO(2) at 2% and 2.5%. When the nano-oxides were tested at all concentrations, CeO(2) groups overall had the most color changes, and TiO(2) groups had the least. All ΔE* values of the mixed pigment groups were below the 50:50% acceptability threshold (ΔE*=1.2-2.3, below 3.0) except 2% CeO(2) (ΔE*=4.2). 1% nano-CeO(2) and 2% and 2.5% nano-TiO(2) used as opacifiers for silicone A-2186 maxillofacial prostheses with mixed pigments exhibited the least

Resistance of Silicon Nitride Turbine Components to Erosion and Hot Corrosion/oxidation Attack

NASA Technical Reports Server (NTRS)

Strangmen, Thomas E.; Fox, Dennis S.

1994-01-01

Silicon nitride turbine components are under intensive development by AlliedSignal to enable a new generation of higher power density auxiliary power systems. In order to be viable in the intended applications, silicon nitride turbine airfoils must be designed for survival in aggressive oxidizing combustion gas environments. Erosive and corrosive damage to ceramic airfoils from ingested sand and sea salt must be avoided. Recent engine test experience demonstrated that NT154 silicon nitride turbine vanes have exceptional resistance to sand erosion, relative to superalloys used in production engines. Similarly, NT154 silicon nitride has excellent resistance to oxidation in the temperature range of interest - up to 1400 C. Hot corrosion attack of superalloy gas turbine components is well documented. While hot corrosion from ingested sea salt will attack silicon nitride substantially less than the superalloys being replaced in initial engine applications, this degradation has the potential to limit component lives in advanced engine applications. Hot corrosion adversely affects the strength of silicon nitride in the 850 to 1300 C range. Since unacceptable reductions in strength must be rapidly identified and avoided, AlliedSignal and the NASA Lewis Research Center have pioneered the development of an environmental life prediction model for silicon nitride turbine components. Strength retention in flexure specimens following 1 to 3300 hour exposures to high temperature oxidation and hot corrosion has been measured and used to calibrate the life prediction model. Predicted component life is dependent upon engine design (stress, temperature, pressure, fuel/air ratio, gas velocity, and inlet air filtration), mission usage (fuel sulfur content, location (salt in air), and times at duty cycle power points), and material parameters. Preliminary analyses indicate that the hot corrosion resistance of NT154 silicon nitride is adequate for AlliedSignal's initial engine

Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

DOEpatents

Manginell, Ronald P.; Schubert, W. Kent; Shul, Randy J.

2005-08-16

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Triple-junction thin-film silicon solar cell fabricated on periodically textured substrate with a stabilized efficiency of 13.6%

NASA Astrophysics Data System (ADS)

Sai, Hitoshi; Matsui, Takuya; Koida, Takashi; Matsubara, Koji; Kondo, Michio; Sugiyama, Shuichiro; Katayama, Hirotaka; Takeuchi, Yoshiaki; Yoshida, Isao

2015-05-01

We report a high-efficiency triple-junction thin-film silicon solar cell fabricated with the so-called substrate configuration. It was verified whether the design criteria for developing single-junction microcrystalline silicon (μc-Si:H) solar cells are applicable to multijunction solar cells. Furthermore, a notably high short-circuit current density of 32.9 mA/cm2 was achieved in a single-junction μc-Si:H cell fabricated on a periodically textured substrate with a high-mobility front transparent contacting layer. These technologies were also combined into a-Si:H/μc-Si:H/μc-Si:H triple-junction cells, and a world record stabilized efficiency of 13.6% was achieved.

Review of silicon photonics: history and recent advances

NASA Astrophysics Data System (ADS)

Ye, Winnie N.; Xiong, Yule

2013-09-01

Silicon photonics has attracted tremendous attention and research effort as a promising technology in optoelectronic integration for computing, communications, sensing, and solar harvesting. Mainly due to the combination of its excellent material properties and the complementary metal-oxide semiconductor (CMOS) fabrication processing technology, silicon has becoming the material choice for photonic and optoelectronic circuits with low cost, ultra-compact device footprint, and high-density integration. This review paper provides an overview on silicon photonics, by highlighting the early work from the mid-1980s on the fundamental building blocks such as silicon platforms and waveguides, and the main milestones that have been achieved so far in the field. A summary of reported work on functional elements in both passive and active devices, as well as the applications of the technology in interconnect, sensing, and solar cells, is identified.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Density change and viscous flow during structural relaxation of plasma-enhanced chemical-vapor-deposited silicon oxide films

NASA Astrophysics Data System (ADS)

Cao, Zhiqiang; Zhang, Xin

2004-10-01

The structural relaxation of plasma-enhanced chemical-vapor-deposited (PECVD) silane-based silicon oxide films during thermal cycling and annealing has been studied using wafer curvature measurements. These measurements, which determine stress in the amorphous silicon oxide films, are sensitive to both plastic deformation and density changes. A quantitative case study of such changes has been done based upon the experimental results. A microstructure-based mechanism elucidates seams as a source of density change and voids as a source of plastic deformation, accompanied by a viscous flow. This theory was then used to explain a series of experimental results that are related to thermal cycling as well as annealing of PECVD silicon oxide films including stress hysteresis generation and reduction and coefficient of thermal-expansion changes. In particular, the thickness effect was examined; PECVD silicon oxide films with a thickness varying from 1to40μm were studied, as certain demanding applications in microelectromechanical systems require such thick films serving as heat/electrical insulation layers.

Efficient photovoltaic heterojunctions of indium tin oxides on silicon

NASA Technical Reports Server (NTRS)

Dubow, J. B.; Sites, J. R.; Burk, D. E.

1976-01-01

Heterojunction diodes of indium tin oxide films sputtered on to p-silicon using ion-beam techniques display significant photovoltaic effects when exposed to sunlight. Galvanomagnetic and optical measurements confirm that the oxide films are highly degenerate transparent semiconductors. At a tin oxide concentration of 10%, an open-circuit voltage of 0.51 V was observed along with a short-circuit current of 32 mA/sq cm, a fill factor of 0.70, and a conversion efficiency of 12%. As the concentration was raised to 70%, the voltage remained steady, the current fell to 27 mA/sq cm, and the fill factor fell to 0.60

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Lithographically defined few-electron silicon quantum dots based on a silicon-on-insulator substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horibe, Kosuke; Oda, Shunri; Kodera, Tetsuo, E-mail: kodera.t.ac@m.titech.ac.jp

2015-02-23

Silicon quantum dot (QD) devices with a proximal single-electron transistor (SET) charge sensor have been fabricated in a metal-oxide-semiconductor structure based on a silicon-on-insulator substrate. The charge state of the QDs was clearly read out using the charge sensor via the SET current. The lithographically defined small QDs enabled clear observation of the few-electron regime of a single QD and a double QD by charge sensing. Tunnel coupling on tunnel barriers of the QDs can be controlled by tuning the top-gate voltages, which can be used for manipulation of the spin quantum bit via exchange interaction between tunnel-coupled QDs. Themore » lithographically defined silicon QD device reported here is technologically simple and does not require electrical gates to create QD confinement potentials, which is advantageous for the integration of complicated constructs such as multiple QD structures with SET charge sensors for the purpose of spin-based quantum computing.« less

Direct fabrication of silicone lenses with 3D printed parts

NASA Astrophysics Data System (ADS)

Kamal, Tahseen; Watkins, Rachel; Cen, Zijian; Lee, W. M.

2016-11-01

The traditional process of making glass lenses requires grinding and polishing of the material which is a tedious and sensitive process. Existing polymer lens making techniques, such as high temperature reflow techniques, have been significantly simple lens making processes which cater well to customer industry. Recently, the use of UV-curing liquid lens has ushered in customized lens making (Printed Optics), but contains undesirable yellowing effects. Polydimethylsiloxane (PDMS) is a transparent polymer curable at low temperature (<100°C) provides an alternative to lens making. In this work, we showed that PDMS lenses are fabricated using single silicone droplets which are formed in a guided and controlled passive manner using 3D printed tools. These silicone lenses have attributes such as smoothness of curvature, resilience to temperature change, low optical aberrations, high transparency (>95%) and minimal aging (yellowing). Moreover, these lenses have a range of focal lengths (3.5 mm to 14.5 mm as well as magnifications (up to 160X). In addition, we created smartphone attachment to turn smart device (tablet or smartphone) into a low-powered microscope. In future we plan to extend this method to produce microlens array.

Fabrication of porous silicon nitride ceramics using binder jetting technology

NASA Astrophysics Data System (ADS)

Rabinskiy, L.; Ripetsky, A.; Sitnikov, S.; Solyaev, Y.; Kahramanov, R.

2016-07-01

This paper presents the results of the binder jetting technology application for the processing of the Si3N4-based ceramics. The difference of the developed technology from analogues used for additive manufacturing of silicon nitride ceramics is a method of the separate deposition of the mineral powder and binder without direct injection of suspensions/slurries. It is assumed that such approach allows reducing the technology complexity and simplifying the process of the feedstock preparation, including the simplification of the composite materials production. The binders based on methyl ester of acrylic acid with polyurethane and modified starch were studied. At this stage of the investigations, the technology of green body's fabrication is implemented using a standard HP cartridge mounted on the robotic arm. For the coordinated operation of the cartridge and robot the specially developed software was used. Obtained green bodies of silicon powder were used to produce the ceramic samples via reaction sintering. The results of study of ceramics samples microstructure and composition are presented. Sintered ceramics are characterized by fibrous α-Si3N4 structure and porosity up to 70%.

A sub-atmospheric chemical vapor deposition process for deposition of oxide liner in high aspect ratio through silicon vias.

PubMed

Lisker, Marco; Marschmeyer, Steffen; Kaynak, Mehmet; Tekin, Ibrahim

2011-09-01

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

Silicon solar cell process development, fabrication, and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Work has progressed in fabrication and characterization of solar cells from ubiquitous crystallization process (UCP) wafers and LASS ribbons. Gettering tests applied to UCP wafers made little change on their performance compared with corresponding baseline data. Advanced processes such as shallow junction (SJ), back surface field (BSF), and multilayer antireflection (MLAR) were also applied. While BSF by Al paste had shunting problems, cells with SJ and BSF by evaporated Al, and MLAR did achieve 14.1% AMI on UCP silicon. The study of LASS material was very preliminary. Only a few cells with SJ, BSR, (no BSF) and MLAR were completed due to mechanical yield problems after lapping the material. Average efficiency was 10.7% AMI with 13.4% AMI for CZ controls. Relatively high minority carrier diffusion lengths were obtained. The lower than expected Jsc could be partially explained by low active area due to irregular sizes.

Silicon carbide, a semiconductor for space power electronics

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Matus, Lawrence G.

1991-01-01

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Electronic structure of indium-tungsten-oxide alloys and their energy band alignment at the heterojunction to crystalline silicon

NASA Astrophysics Data System (ADS)

Menzel, Dorothee; Mews, Mathias; Rech, Bernd; Korte, Lars

2018-01-01

The electronic structure of thermally co-evaporated indium-tungsten-oxide films is investigated. The stoichiometry is varied from pure tungsten oxide to pure indium oxide, and the band alignment at the indium-tungsten-oxide/crystalline silicon heterointerface is monitored. Using in-system photoelectron spectroscopy, optical spectroscopy, and surface photovoltage measurements, we show that the work function of indium-tungsten-oxide continuously decreases from 6.3 eV for tungsten oxide to 4.3 eV for indium oxide, with a concomitant decrease in the band bending at the hetero interface to crystalline silicon than indium oxide.

Role of an Oxidant Mixture as Surface Modifier of Porous Silicon Microstructures Evaluated by Spectroscopic Ellipsometry

PubMed Central

Montiel-González, Zeuz; Escobar, Salvador; Nava, Rocío; del Río, J. Antonio; Tagüeña-Martínez, Julia

2016-01-01

Current research on porous silicon includes the construction of complex structures with luminescent and/or photonic properties. However, their preparation with both characteristics is still challenging. Recently, our group reported a possible method to achieve that by adding an oxidant mixture to the electrolyte used to produce porous silicon. This mixture can chemically modify their microstructure by changing the thickness and surface passivation of the pore walls. In this work, we prepared a series of samples (with and without oxidant mixture) and we evaluated the structural differences through their scanning electron micrographs and their optical properties determined by spectroscopic ellipsometry. The results showed that ellipsometry is sensitive to slight variations in the porous silicon structure, caused by changes in their preparation. The fitting process, based on models constructed from the features observed in the micrographs, allowed us to see that the mayor effect of the oxidant mixture is on samples of high porosity, where the surface oxidation strongly contributes to the skeleton thinning during the electrochemical etching. This suggests the existence of a porosity threshold for the action of the oxidant mixture. These results could have a significant impact on the design of complex porous silicon structures for different optoelectronic applications. PMID:27097767

Role of an Oxidant Mixture as Surface Modifier of Porous Silicon Microstructures Evaluated by Spectroscopic Ellipsometry.

PubMed

Montiel-González, Zeuz; Escobar, Salvador; Nava, Rocío; del Río, J Antonio; Tagüeña-Martínez, Julia

2016-04-21

Current research on porous silicon includes the construction of complex structures with luminescent and/or photonic properties. However, their preparation with both characteristics is still challenging. Recently, our group reported a possible method to achieve that by adding an oxidant mixture to the electrolyte used to produce porous silicon. This mixture can chemically modify their microstructure by changing the thickness and surface passivation of the pore walls. In this work, we prepared a series of samples (with and without oxidant mixture) and we evaluated the structural differences through their scanning electron micrographs and their optical properties determined by spectroscopic ellipsometry. The results showed that ellipsometry is sensitive to slight variations in the porous silicon structure, caused by changes in their preparation. The fitting process, based on models constructed from the features observed in the micrographs, allowed us to see that the mayor effect of the oxidant mixture is on samples of high porosity, where the surface oxidation strongly contributes to the skeleton thinning during the electrochemical etching. This suggests the existence of a porosity threshold for the action of the oxidant mixture. These results could have a significant impact on the design of complex porous silicon structures for different optoelectronic applications.

Nanopore arrays in a silicon membrane for parallel single-molecule detection: fabrication

NASA Astrophysics Data System (ADS)

Schmidt, Torsten; Zhang, Miao; Sychugov, Ilya; Roxhed, Niclas; Linnros, Jan

2015-08-01

Solid state nanopores enable translocation and detection of single bio-molecules such as DNA in buffer solutions. Here, sub-10 nm nanopore arrays in silicon membranes were fabricated by using electron-beam lithography to define etch pits and by using a subsequent electrochemical etching step. This approach effectively decouples positioning of the pores and the control of their size, where the pore size essentially results from the anodizing current and time in the etching cell. Nanopores with diameters as small as 7 nm, fully penetrating 300 nm thick membranes, were obtained. The presented fabrication scheme to form large arrays of nanopores is attractive for parallel bio-molecule sensing and DNA sequencing using optical techniques. In particular the signal-to-noise ratio is improved compared to other alternatives such as nitride membranes suffering from a high-luminescence background.

Nanopore arrays in a silicon membrane for parallel single-molecule detection: fabrication.

PubMed

Schmidt, Torsten; Zhang, Miao; Sychugov, Ilya; Roxhed, Niclas; Linnros, Jan

2015-08-07

Solid state nanopores enable translocation and detection of single bio-molecules such as DNA in buffer solutions. Here, sub-10 nm nanopore arrays in silicon membranes were fabricated by using electron-beam lithography to define etch pits and by using a subsequent electrochemical etching step. This approach effectively decouples positioning of the pores and the control of their size, where the pore size essentially results from the anodizing current and time in the etching cell. Nanopores with diameters as small as 7 nm, fully penetrating 300 nm thick membranes, were obtained. The presented fabrication scheme to form large arrays of nanopores is attractive for parallel bio-molecule sensing and DNA sequencing using optical techniques. In particular the signal-to-noise ratio is improved compared to other alternatives such as nitride membranes suffering from a high-luminescence background.

Electron-irradiation-induced crystallization at metallic amorphous/silicon oxide interfaces caused by electronic excitation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nagase, Takeshi, E-mail: t-nagase@uhvem.osaka-u.ac.jp; Division of Materials and Manufacturing Science, Graduate School of Engineering, Osaka University, 2-1, Yamada-Oka, Suita, Osaka 565-0871; Yamashita, Ryo

2016-04-28

Irradiation-induced crystallization of an amorphous phase was stimulated at a Pd-Si amorphous/silicon oxide (a(Pd-Si)/SiO{sub x}) interface at 298 K by electron irradiation at acceleration voltages ranging between 25 kV and 200 kV. Under irradiation, a Pd-Si amorphous phase was initially formed at the crystalline face-centered cubic palladium/silicon oxide (Pd/SiO{sub x}) interface, followed by the formation of a Pd{sub 2}Si intermetallic compound through irradiation-induced crystallization. The irradiation-induced crystallization can be considered to be stimulated not by defect introduction through the electron knock-on effects and electron-beam heating, but by the electronic excitation mechanism. The observed irradiation-induced structural change at the a(Pd-Si)/SiO{sub x} and Pd/SiO{sub x}more » interfaces indicates multiple structural modifications at the metal/silicon oxide interfaces through electronic excitation induced by the electron-beam processes.« less

Design Fabrication and Characterization of High Density Silicon Photonic Components

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, Adam

2015-02-01

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve e ciency while reducing on-chip area even as photonic components expand to ll application spaces no longer satis ed by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which e cient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling onmore » a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the rst experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modi ed racetrack resonator is then presented enabling extraction of insertion loss data for highly e cient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.« less

Thromboresistance Characterization of Extruded Nitric Oxide-Releasing Silicone Catheters

PubMed Central

Amoako, Kagya A.; Archangeli, Christopher; Handa, Hitesh; Major, Terry; Meyerhoff, Mark E.; Annich, Gail M.; Bartlett, Robert H.

2013-01-01

Intravascular catheters used in clinical practice can activate platelets, leading to thrombus formation and stagnation of blood flow. Nitric oxide (NO)-releasing polymers have been shown previously to reduce clot formation on a number of blood contacting devices. In this work, trilaminar NO-releasing silicone catheters were fabricated and tested for their thrombogenicity. All catheters had specifications of L = 6 cm, inner diameter = 21 gauge (0.0723 cm), outer diameter = 12 gauge (0.2052 cm), and NO-releasing layer thickness = 200 ± 11 μm. Control and NO-releasing catheters were characterized in vitro for their NO flux and NO release duration by gas phase chemiluminescence measurements. The catheters were then implanted in the right and left internal jugular veins of (N = 6 and average weight = 3 kg) adult male rabbits for 4 hours thrombogenicity testing. Platelet counts and function, methemoglobin (metHb), hemoglobin (Hb), and white cell counts and functional time (defined as patency time of catheter) were monitored as measured outcomes. Nitric oxide-releasing catheters (N = 6) maintained an average flux above (2 ± 0.5) × 10−10 mol/min/cm2 for more than 24 hours, whereas controls showed no NO release. Methemoglobin, Hb, white cell, and platelet counts and platelet function at 4 hours were not significantly different from baseline (α = 0.05). However, clots on controls were visibly larger and prevented blood draws at a significantly (p < 0.05) earlier time (2.3 ± 0.7 hours) into the experiment, whereas all NO-releasing catheters survived the entire 4 hours test period. Results indicate that catheter NO flux levels attenuated thrombus formation in a short-term animal model. PMID:22395119

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, V.K.

1990-08-21

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications is disclosed. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al[sub x]N[sub y]O[sub z] layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al[sub x]N[sub y]O[sub z] layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, Vinod K.

1990-01-01

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al.sub.x N.sub.y O.sub.z layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al.sub.x N.sub.y O.sub.z layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Catalytically enhanced thermal decomposition of chemically grown silicon oxide layers on Si(001)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leroy, F., E-mail: leroy@cinam.univ-mrs.fr; Passanante, T.; Cheynis, F.

2016-03-14

The thermal decomposition of Si dioxide layers formed by wet chemical treatment on Si(001) has been studied by low-energy electron microscopy. Independent nucleations of voids occur into the Si oxide layers that open by reaction at the void periphery. Depending on the voids, the reaction rates exhibit large differences via the occurrence of a nonlinear growth of the void radius. This non-steady state regime is attributed to the accumulation of defects and silicon hydroxyl species at the SiO{sub 2}/Si interface that enhances the silicon oxide decomposition at the void periphery.

Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Abbaspour, R.; Brown, D. K.; Bakir, M. S.

2017-02-01

This paper presents the fabrication and electrical characterization of high aspect-ratio (AR) sub-micron diameter through silicon vias (TSVs) for densely interconnected three-dimensional (3D) stacked integrated circuits (ICs). The fabricated TSV technology features an AR of 16:1 with 680 nm diameter copper (Cu) core and 920 nm overall diameter. To address the challenges in scaling TSVs, scallop-free low roughness nano-Bosch silicon etching and direct Cu electroplating on a titanium-nitride (TiN) diffusion barrier layer have been developed as key enabling modules. The electrical resistance of the sub-micron TSVs is measured to be on average 1.2 Ω, and the Cu resistivity is extracted to be approximately 2.95 µΩ cm. Furthermore, the maximum achievable current-carrying capacity (CCC) of the scaled TSVs is characterized to be approximately 360 µA for the 680 nm Cu core.

Study on fabrication technology of silicon-based silica array waveguide grating

NASA Astrophysics Data System (ADS)

Sun, Yanjun; Dong, Lianhe; Leng, Yanbing

2009-05-01

Array waveguide grating (AWG) is an important plane optical element in dense wavelength division multiplex/demultiplex system. There are many virtue, channel quantity larger,lower loss, lower crosstalk, size smaller and high reliability etc. This article describs AWG fabrication technics utilizing IC(Integrated Circles) techniques, based on sixteen channel Silicon-Based Silica Array Waveguide Grating, put emphasis on discussing doping and deposition of waveguide core film,technics theory and interrelated parameter condition of photoetch and ion etching. Experiment result indicates that it depens on electrode structure, energy of radio-frequency electrode gas component, pressure ,flowing speed and substrate temperature by CVD depositing film .During depositing waveguide film by PE-CVD, the silicon is not reacted, When temperature becomes lower,it is reacted and it is easy to realize the control of film thickness and time with a result of film thickness uniformity reaching about 4% after optimizing deposition parameter and condition. We get the result of high etching speed rate, outline zoom, and side frame smooth by photoresist/Cr multiple mask and optimizing etching technics.

Epitaxial regrowth of silicon for the fabrication of radial junction nanowire solar cells

NASA Astrophysics Data System (ADS)

Kendrick, Chito E.; Eichfeld, Sarah M.; Ke, Yue; Weng, Xiaojun; Wang, Xin; Mayer, Theresa S.; Redwing, Joan M.

2010-08-01

Radial p-n silicon nanowire (SiNW) solar cells are of interest as a potential pathway to increase the efficiency of crystalline silicon photovoltaics by reducing the junction length and surface reflectivity. Our studies have focused on the use of vapor-liquid-solid (VLS) growth in combination with chemical vapor deposition (CVD) processing for the fabrication of radial p-n junction SiNW array solar cells. High aspect ratio p-type SiNW arrays were initially grown on gold-coated (111) Si substrates by CVD using SiCl4 as the source gas and B2H6 as the p-type dopant source. The epitaxial re-growth of n-type Si shell layers on the Si nanowires was then investigated using SiH4 as the source gas and PH3 as the dopant. Highly conformal coatings were achieved on nanowires up to 25 μm in length. The microstructure of the Si shell layer changed from polycrystalline to single crystal as the deposition temperature was raised from 650oC to 950oC. Electrical test structures were fabricated by aligning released SiNWs onto pre-patterned substrates via fieldassisted assembly followed by selective removal of the n-type shell layer and contact deposition. Current-voltage measurements of the radial p-n SiNWs diodes fabricated with re-grown Si shell layers at 950°C demonstrate rectifying behavior with an ideality factor of 1.93. Under illumination from an AM1.5g spectrum and efficiency for this single SiNW radial p-n junction was determined to be 1.8%, total wire diameter was 985 nm.

Fabrication and characterization of silicon quantum dots in Si-rich silicon carbide films.

PubMed

Chang, Geng-Rong; Ma, Fei; Ma, Dayan; Xu, Kewei

2011-12-01

Amorphous Si-rich silicon carbide films were prepared by magnetron co-sputtering and subsequently annealed at 900-1100 degrees C. After annealing at 1100 degrees C, this configuration of silicon quantum dots embedded in amorphous silicon carbide formed. X-ray photoelectron spectroscopy was used to study the chemical modulation of the films. The formation and orientation of silicon quantum dots were characterized by glancing angle X-ray diffraction, which shows that the ratio of silicon and carbon significantly influences the species of quantum dots. High-resolution transmission electron microscopy investigations directly demonstrated that the formation of silicon quantum dots is heavily dependent on the annealing temperatures and the ratio of silicon and carbide. Only the temperature of about 1100 degrees C is enough for the formation of high-density and small-size silicon quantum dots due to phase separation and thermal crystallization. Deconvolution of the first order Raman spectra shows the existence of a lower frequency peak in the range 500-505 cm(-1) corresponding to silicon quantum dots with different atom ratio of silicon and carbon.

Properties of silicon carbide fiber-reinforced silicon nitride matrix composites

NASA Technical Reports Server (NTRS)

Bhatt, Ramakrishna T.

1988-01-01

The mechanical properties of NASA Lewis developed SiC/RBSN composites and their thermal and environmental stability havd been studied. The composites consist of nearly 30 vol pct of aligned 142 micron diameter chemically vapor-deposited SiC fibers in a relatively porous silicon nitride matrix. In the as-fabricated condition, the unidirectional and 2-D composites exhibited metal-like stress-strain behavior, graceful failure, and showed improved properties when compared with unreinforced matrix of comparable density. Furthermore, the measured room temperature tensile properties were relativley independent of tested volume and were unaffected by artifical notches normal to the loading direction or by thermal shocking from temperatures up to 800 C. The four-point bend strength data measured as a function of temperature to 1400 C in air showed that as-fabricated strength was maintained to 1200 C. At 1400 C, however, nearly 15 pct loss in strength was observed. Measurement of room temperature tensile strength after 100 hr exposure at temperatures to 1400 C in a nitrogen environment indicated no loss from the as-fabricated composite strength. On the other hand, after 100 hr exposure in flowing oxygen at 1200 and 1400 C, the composites showed approximately 40 pct loss from their as-fabricated ultimate tensile strength. Those exposed between 400 to 1200 C showed nearly 60 pct strength loss. Oxidation of the fiber/matrix interface as well as internal oxidation of the porous Si3N4 matrix are likely mechanisms for strength degradation. The excellent strength reproducibility, notch insensitivity, and high temperature strength of the composite makes it an ideal candidate for advanced heat engine applications provided coating or densification methods are developed to avoid internal oxidation attack.

Tunnel oxide passivated contacts formed by ion implantation for applications in silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reichel, Christian, E-mail: christian.reichel@ise.fraunhofer.de; National Renewable Energy Laboratory; Feldmann, Frank

Passivated contacts (poly-Si/SiO{sub x}/c-Si) doped by shallow ion implantation are an appealing technology for high efficiency silicon solar cells, especially for interdigitated back contact (IBC) solar cells where a masked ion implantation facilitates their fabrication. This paper presents a study on tunnel oxide passivated contacts formed by low-energy ion implantation into amorphous silicon (a-Si) layers and examines the influence of the ion species (P, B, or BF{sub 2}), the ion implantation dose (5 × 10{sup 14 }cm{sup −2} to 1 × 10{sup 16 }cm{sup −2}), and the subsequent high-temperature anneal (800 °C or 900 °C) on the passivation quality and junction characteristics using double-sided contacted silicon solar cells.more » Excellent passivation quality is achieved for n-type passivated contacts by P implantations into either intrinsic (undoped) or in-situ B-doped a-Si layers with implied open-circuit voltages (iV{sub oc}) of 725 and 720 mV, respectively. For p-type passivated contacts, BF{sub 2} implantations into intrinsic a-Si yield well passivated contacts and allow for iV{sub oc} of 690 mV, whereas implanted B gives poor passivation with iV{sub oc} of only 640 mV. While solar cells featuring in-situ B-doped selective hole contacts and selective electron contacts with P implanted into intrinsic a-Si layers achieved V{sub oc} of 690 mV and fill factor (FF) of 79.1%, selective hole contacts realized by BF{sub 2} implantation into intrinsic a-Si suffer from drastically reduced FF which is caused by a non-Ohmic Schottky contact. Finally, implanting P into in-situ B-doped a-Si layers for the purpose of overcompensation (counterdoping) allowed for solar cells with V{sub oc} of 680 mV and FF of 80.4%, providing a simplified and promising fabrication process for IBC solar cells featuring passivated contacts.« less

Alternative method for steam generation for thermal oxidation of silicon

NASA Astrophysics Data System (ADS)

Spiegelman, Jeffrey J.

2010-02-01

Thermal oxidation of silicon is an important process step in MEMS device fabrication. Thicker oxide layers are often used as structural components and can take days or weeks to grow, causing high gas costs, maintenance issues, and a process bottleneck. Pyrolytic steam, which is generated from hydrogen and oxygen combustion, was the default process, but has serious drawbacks: cost, safety, particles, permitting, reduced growth rate, rapid hydrogen consumption, component breakdown and limited steam flow rates. Results from data collected over a 24 month period by a MEMS manufacturer supports replacement of pyrolytic torches with RASIRC Steamer technology to reduce process cycle time and enable expansion previously limited by local hydrogen permitting. Data was gathered to determine whether Steamers can meet or exceed pyrolytic torch performance. The RASIRC Steamer uses de-ionized water as its steam source, eliminating dependence on hydrogen and oxygen. A non-porous hydrophilic membrane selectively allows water vapor to pass. All other molecules are greatly restricted, so contaminants in water such as dissolved gases, ions, total organic compounds (TOC), particles, and metals can be removed in the steam phase. The MEMS manufacturer improved growth rate by 7% over the growth range from 1μm to 3.5μm. Over a four month period, wafer uniformity, refractive index, wafer stress, and etch rate were tracked with no significant difference found. The elimination of hydrogen generated a four-month return on investment (ROI). Mean time between failure (MTBF) was increased from 3 weeks to 32 weeks based on three Steamers operating over eight months.

Turning the undesired voids in silicon into a tool: In-situ fabrication of free-standing 3C-SiC membranes

NASA Astrophysics Data System (ADS)

Khazaka, Rami; Michaud, Jean François; Vennéguès, Philippe; Alquier, Daniel; Portail, Marc

2017-02-01

In this contribution, we present a method to form free-standing cubic silicon carbide (3C-SiC) membranes in-situ during the growth stage. To do so, we exploit the presence of voids in the silicon (Si) epilayer underneath the 3C-SiC membrane, in stark contrast to the conventional view of voids as defects. The shape and the size of the 3C-SiC membranes can be controlled by a preceding patterning step of the Si epilayer. Afterwards, by controlling the expansion of voids in Si, the structured sacrificial layer is consumed during the 3C-SiC growth step. Consequently, the membranes are grown and released simultaneously in a single step process. This straightforward technique is expected to markedly simplify the fabrication process of membranes by reducing the fabrication duration and cost. Furthermore, it helps to overcome several technical issues and presents the cornerstone for micro and nano-electromechanical systems applications, profiting from the outstanding properties of cubic silicon carbide.

Shrinking of silicon nanocrystals embedded in an amorphous silicon oxide matrix during rapid thermal annealing in a forming gas atmosphere

NASA Astrophysics Data System (ADS)

van Sebille, M.; Fusi, A.; Xie, L.; Ali, H.; van Swaaij, R. A. C. M. M.; Leifer, K.; Zeman, M.

2016-09-01

We report the effect of hydrogen on the crystallization process of silicon nanocrystals embedded in a silicon oxide matrix. We show that hydrogen gas during annealing leads to a lower sub-band gap absorption, indicating passivation of defects created during annealing. Samples annealed in pure nitrogen show expected trends according to crystallization theory. Samples annealed in forming gas, however, deviate from this trend. Their crystallinity decreases for increased annealing time. Furthermore, we observe a decrease in the mean nanocrystal size and the size distribution broadens, indicating that hydrogen causes a size reduction of the silicon nanocrystals.

A Novel Silicone-Magnetite Composite Material Used in the Fabrication of Biomimetic Cilia

NASA Astrophysics Data System (ADS)

Carstens, B. L.; Evans, B. A.; Shields, A. R.; Su, J.; Washburn, S.; Falvo, M. R.; Superfine, R.

2008-10-01

We have developed a novel polymer-magnetite composite that we use to fabricate arrays of magnetically actuable biomimetic cilia. Biomimetic cilia are flexible nanorods 750 nm in diameter and 25 microns tall. They generate fluid flows similar to those produced by biological cilia. Polymer-magnetic nanoparticle materials such as ours are becoming increasingly useful in biomedical applications and microelectromechanical systems (MEMS). Comprised of magnetite (Fe3O4), the nanoparticles have a diameter of 5-7 nm and are complexed with a silicone copolymer and crosslinked into a flexible, magnetic solid. Amine groups make up 6-7 percent of the silicone copolymer, providing a simple means of functionalization. We present a detailed mechanical and magnetic analysis of our bulk crosslinked material. The high-aspect ratio biomimetic cilia we create with this magnetite-copolymer complex may have applications in microfluidic mixing, biofouling, and MEMS.

Porous silicon technology for integrated microsystems

NASA Astrophysics Data System (ADS)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

Scalable Preparation of Ternary Hierarchical Silicon Oxide-Nickel-Graphite Composites for Lithium-Ion Batteries.